1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_LAN_TX_RX_H_
5 #define _ICE_LAN_TX_RX_H_
7 union ice_32byte_rx_desc
{
9 __le64 pkt_addr
; /* Packet buffer address */
10 __le64 hdr_addr
; /* Header buffer address */
11 /* bit 0 of hdr_addr is DD bit */
18 __le16 mirroring_status
;
22 __le32 rss
; /* RSS Hash */
23 __le32 fd_id
; /* Flow Director filter ID */
27 /* status/error/PTYPE/length */
28 __le64 status_error_len
;
31 __le16 ext_status
; /* extended status */
43 struct ice_rx_ptype_decoded
{
50 u32 tunnel_end_prot
:2;
51 u32 tunnel_end_frag
:1;
56 enum ice_rx_ptype_outer_ip
{
57 ICE_RX_PTYPE_OUTER_L2
= 0,
58 ICE_RX_PTYPE_OUTER_IP
= 1,
61 enum ice_rx_ptype_outer_ip_ver
{
62 ICE_RX_PTYPE_OUTER_NONE
= 0,
63 ICE_RX_PTYPE_OUTER_IPV4
= 1,
64 ICE_RX_PTYPE_OUTER_IPV6
= 2,
67 enum ice_rx_ptype_outer_fragmented
{
68 ICE_RX_PTYPE_NOT_FRAG
= 0,
69 ICE_RX_PTYPE_FRAG
= 1,
72 enum ice_rx_ptype_tunnel_type
{
73 ICE_RX_PTYPE_TUNNEL_NONE
= 0,
74 ICE_RX_PTYPE_TUNNEL_IP_IP
= 1,
75 ICE_RX_PTYPE_TUNNEL_IP_GRENAT
= 2,
76 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC
= 3,
77 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN
= 4,
80 enum ice_rx_ptype_tunnel_end_prot
{
81 ICE_RX_PTYPE_TUNNEL_END_NONE
= 0,
82 ICE_RX_PTYPE_TUNNEL_END_IPV4
= 1,
83 ICE_RX_PTYPE_TUNNEL_END_IPV6
= 2,
86 enum ice_rx_ptype_inner_prot
{
87 ICE_RX_PTYPE_INNER_PROT_NONE
= 0,
88 ICE_RX_PTYPE_INNER_PROT_UDP
= 1,
89 ICE_RX_PTYPE_INNER_PROT_TCP
= 2,
90 ICE_RX_PTYPE_INNER_PROT_SCTP
= 3,
91 ICE_RX_PTYPE_INNER_PROT_ICMP
= 4,
92 ICE_RX_PTYPE_INNER_PROT_TIMESYNC
= 5,
95 enum ice_rx_ptype_payload_layer
{
96 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE
= 0,
97 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2
= 1,
98 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3
= 2,
99 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4
= 3,
102 /* Rx Flex Descriptor
103 * This descriptor is used instead of the legacy version descriptor when
104 * ice_rlan_ctx.adv_desc is set
106 union ice_32b_rx_flex_desc
{
108 __le64 pkt_addr
; /* Packet buffer address */
109 __le64 hdr_addr
; /* Header buffer address */
110 /* bit 0 of hdr_addr is DD bit */
116 u8 rxdid
; /* descriptor builder profile ID */
117 u8 mir_id_umb_cast
; /* mirror=[5:0], umb=[7:6] */
118 __le16 ptype_flex_flags0
; /* ptype=[9:0], ff0=[15:10] */
119 __le16 pkt_len
; /* [15:14] are reserved */
120 __le16 hdr_len_sph_flex_flags1
; /* header=[10:0] */
122 /* ff1/ext=[15:12] */
125 __le16 status_error0
;
131 __le16 status_error1
;
147 } wb
; /* writeback */
150 /* Rx Flex Descriptor NIC Profile
151 * This descriptor corresponds to RxDID 2 which contains
152 * metadata fields for RSS, flow ID and timestamp info
154 struct ice_32b_rx_flex_desc_nic
{
158 __le16 ptype_flexi_flags0
;
160 __le16 hdr_len_sph_flex_flags1
;
163 __le16 status_error0
;
168 __le16 status_error1
;
185 /* Receive Flex Descriptor profile IDs: There are a total
186 * of 64 profiles where profile IDs 0/1 are for legacy; and
187 * profiles 2-63 are flex profiles that can be programmed
188 * with a specific metadata (profile 7 reserved for HW)
191 ICE_RXDID_LEGACY_0
= 0,
192 ICE_RXDID_LEGACY_1
= 1,
193 ICE_RXDID_FLEX_NIC
= 2,
194 ICE_RXDID_FLEX_NIC_2
= 6,
199 /* Receive Flex Descriptor Rx opcode values */
200 #define ICE_RX_OPC_MDID 0x01
202 /* Receive Descriptor MDID values */
203 enum ice_flex_rx_mdid
{
204 ICE_RX_MDID_FLOW_ID_LOWER
= 5,
205 ICE_RX_MDID_FLOW_ID_HIGH
,
206 ICE_RX_MDID_SRC_VSI
= 19,
207 ICE_RX_MDID_HASH_LOW
= 56,
208 ICE_RX_MDID_HASH_HIGH
,
211 /* Rx/Tx Flag64 packet flag bits */
212 enum ice_flg64_bits
{
214 ICE_FLG_EVLAN_x8100
= 15,
217 ICE_FLG_TNL_MAC
= 22,
230 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
231 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */
233 /* for ice_32byte_rx_flex_desc.pkt_length member */
234 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */
236 enum ice_rx_flex_desc_status_error_0_bits
{
237 /* Note: These are predefined bit offsets */
238 ICE_RX_FLEX_DESC_STATUS0_DD_S
= 0,
239 ICE_RX_FLEX_DESC_STATUS0_EOF_S
,
240 ICE_RX_FLEX_DESC_STATUS0_HBO_S
,
241 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S
,
242 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S
,
243 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S
,
244 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S
,
245 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S
,
246 ICE_RX_FLEX_DESC_STATUS0_LPBK_S
,
247 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S
,
248 ICE_RX_FLEX_DESC_STATUS0_RXE_S
,
249 ICE_RX_FLEX_DESC_STATUS0_CRCP_S
,
250 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S
,
251 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S
,
252 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S
,
253 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S
,
254 ICE_RX_FLEX_DESC_STATUS0_LAST
/* this entry must be last!!! */
257 #define ICE_RXQ_CTX_SIZE_DWORDS 8
258 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
259 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
260 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5
261 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
263 /* RLAN Rx queue context data
265 * The sizes of the variables may be larger than needed due to crossing byte
266 * boundaries. If we do not have the width of the variable set to the correct
267 * size then we could end up shifting bits off the top of the variable when the
268 * variable is at the top of a byte and crosses over into the next byte.
270 struct ice_rlan_ctx
{
272 u16 cpuid
; /* bigger than needed, see above for reason */
273 #define ICE_RLAN_BASE_S 7
276 #define ICE_RLAN_CTX_DBUF_S 7
277 u16 dbuf
; /* bigger than needed, see above for reason */
278 #define ICE_RLAN_CTX_HBUF_S 6
279 u16 hbuf
; /* bigger than needed, see above for reason */
287 u32 rxmax
; /* bigger than needed, see above for reason */
292 u16 lrxqthresh
; /* bigger than needed, see above for reason */
293 u8 prefena
; /* NOTE: normally must be set to 1 at init */
303 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \
304 .offset = offsetof(struct _struct, _ele), \
305 .size_of = FIELD_SIZEOF(struct _struct, _ele), \
310 /* for hsplit_0 field of Rx RLAN context */
311 enum ice_rlan_ctx_rx_hsplit_0
{
312 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT
= 0,
313 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2
= 1,
314 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP
= 2,
315 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP
= 4,
316 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP
= 8,
319 /* for hsplit_1 field of Rx RLAN context */
320 enum ice_rlan_ctx_rx_hsplit_1
{
321 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT
= 0,
322 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2
= 1,
323 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS
= 2,
328 __le64 buf_addr
; /* Address of descriptor's data buf */
329 __le64 cmd_type_offset_bsz
;
332 enum ice_tx_desc_dtype_value
{
333 ICE_TX_DESC_DTYPE_DATA
= 0x0,
334 ICE_TX_DESC_DTYPE_CTX
= 0x1,
335 /* DESC_DONE - HW has completed write-back of descriptor */
336 ICE_TX_DESC_DTYPE_DESC_DONE
= 0xF,
339 #define ICE_TXD_QW1_CMD_S 4
340 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S)
342 enum ice_tx_desc_cmd_bits
{
343 ICE_TX_DESC_CMD_EOP
= 0x0001,
344 ICE_TX_DESC_CMD_RS
= 0x0002,
345 ICE_TX_DESC_CMD_IL2TAG1
= 0x0008,
346 ICE_TX_DESC_CMD_IIPT_IPV6
= 0x0020,
347 ICE_TX_DESC_CMD_IIPT_IPV4
= 0x0040,
348 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM
= 0x0060,
349 ICE_TX_DESC_CMD_L4T_EOFT_TCP
= 0x0100,
350 ICE_TX_DESC_CMD_L4T_EOFT_SCTP
= 0x0200,
351 ICE_TX_DESC_CMD_L4T_EOFT_UDP
= 0x0300,
354 #define ICE_TXD_QW1_OFFSET_S 16
355 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
357 enum ice_tx_desc_len_fields
{
358 /* Note: These are predefined bit offsets */
359 ICE_TX_DESC_LEN_MACLEN_S
= 0, /* 7 BITS */
360 ICE_TX_DESC_LEN_IPLEN_S
= 7, /* 7 BITS */
361 ICE_TX_DESC_LEN_L4_LEN_S
= 14 /* 4 BITS */
364 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
365 #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
366 #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
368 /* Tx descriptor field limits in bytes */
369 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
370 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
371 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
372 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
373 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
374 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
376 #define ICE_TXD_QW1_TX_BUF_SZ_S 34
377 #define ICE_TXD_QW1_L2TAG1_S 48
379 /* Context descriptors */
380 struct ice_tx_ctx_desc
{
381 __le32 tunneling_params
;
387 #define ICE_TXD_CTX_QW1_CMD_S 4
388 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
390 #define ICE_TXD_CTX_QW1_TSO_LEN_S 30
391 #define ICE_TXD_CTX_QW1_TSO_LEN_M \
392 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
394 #define ICE_TXD_CTX_QW1_MSS_S 50
396 enum ice_tx_ctx_desc_cmd_bits
{
397 ICE_TX_CTX_DESC_TSO
= 0x01,
398 ICE_TX_CTX_DESC_TSYN
= 0x02,
399 ICE_TX_CTX_DESC_IL2TAG2
= 0x04,
400 ICE_TX_CTX_DESC_IL2TAG2_IL2H
= 0x08,
401 ICE_TX_CTX_DESC_SWTCH_NOTAG
= 0x00,
402 ICE_TX_CTX_DESC_SWTCH_UPLINK
= 0x10,
403 ICE_TX_CTX_DESC_SWTCH_LOCAL
= 0x20,
404 ICE_TX_CTX_DESC_SWTCH_VSI
= 0x30,
405 ICE_TX_CTX_DESC_RESERVED
= 0x40
408 #define ICE_LAN_TXQ_MAX_QGRPS 127
409 #define ICE_LAN_TXQ_MAX_QDIS 1023
411 /* Tx queue context data
413 * The sizes of the variables may be larger than needed due to crossing byte
414 * boundaries. If we do not have the width of the variable set to the correct
415 * size then we could end up shifting bits off the top of the variable when the
416 * variable is at the top of a byte and crosses over into the next byte.
418 struct ice_tlan_ctx
{
419 #define ICE_TLAN_CTX_BASE_S 7
420 u64 base
; /* base is defined in 128-byte units */
422 u16 cgd_num
; /* bigger than needed, see above for reason */
426 #define ICE_TLAN_CTX_VMVF_TYPE_VF 0
427 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1
428 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2
431 u8 internal_usage_flag
;
433 u16 cpuid
; /* bigger than needed, see above for reason */
440 u8 itr_notification_mode
;
442 u32 qlen
; /* bigger than needed, see above for reason */
449 u8 pkt_shaper_prof_idx
;
450 u8 int_q_state
; /* width not needed - internal do not write */
453 /* macro to make the table lines short */
454 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
457 ICE_RX_PTYPE_OUTER_##OUTER_IP, \
458 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
459 ICE_RX_PTYPE_##OUTER_FRAG, \
460 ICE_RX_PTYPE_TUNNEL_##T, \
461 ICE_RX_PTYPE_TUNNEL_END_##TE, \
462 ICE_RX_PTYPE_##TEF, \
463 ICE_RX_PTYPE_INNER_PROT_##I, \
464 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
466 #define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
468 /* shorter macros makes the table fit but are terse */
469 #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG
471 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
472 static const struct ice_rx_ptype_decoded ice_ptype_lkup
[] = {
473 /* L2 Packet types */
474 ICE_PTT_UNUSED_ENTRY(0),
475 ICE_PTT(1, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, PAY2
),
476 ICE_PTT(2, L2
, NONE
, NOF
, NONE
, NONE
, NOF
, NONE
, NONE
),
479 static inline struct ice_rx_ptype_decoded
ice_decode_rx_desc_ptype(u16 ptype
)
481 return ice_ptype_lkup
[ptype
];
484 #define ICE_LINK_SPEED_UNKNOWN 0
485 #define ICE_LINK_SPEED_10MBPS 10
486 #define ICE_LINK_SPEED_100MBPS 100
487 #define ICE_LINK_SPEED_1000MBPS 1000
488 #define ICE_LINK_SPEED_2500MBPS 2500
489 #define ICE_LINK_SPEED_5000MBPS 5000
490 #define ICE_LINK_SPEED_10000MBPS 10000
491 #define ICE_LINK_SPEED_20000MBPS 20000
492 #define ICE_LINK_SPEED_25000MBPS 25000
493 #define ICE_LINK_SPEED_40000MBPS 40000
494 #define ICE_LINK_SPEED_50000MBPS 50000
495 #define ICE_LINK_SPEED_100000MBPS 100000
497 #endif /* _ICE_LAN_TX_RX_H_ */