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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58
59 #define MAJ 5
60 #define MIN 3
61 #define BUILD 0
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73 };
74
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter, bool set);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static int igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 static int igb_disable_sriov(struct pci_dev *dev);
183 static int igb_pci_disable_sriov(struct pci_dev *dev);
184 #endif
185
186 #ifdef CONFIG_PM
187 #ifdef CONFIG_PM_SLEEP
188 static int igb_suspend(struct device *);
189 #endif
190 static int igb_resume(struct device *);
191 static int igb_runtime_suspend(struct device *dev);
192 static int igb_runtime_resume(struct device *dev);
193 static int igb_runtime_idle(struct device *dev);
194 static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198 };
199 #endif
200 static void igb_shutdown(struct pci_dev *);
201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202 #ifdef CONFIG_IGB_DCA
203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204 static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208 };
209 #endif
210 #ifdef CONFIG_NET_POLL_CONTROLLER
211 /* for netdump / net console */
212 static void igb_netpoll(struct net_device *);
213 #endif
214 #ifdef CONFIG_PCI_IOV
215 static unsigned int max_vfs;
216 module_param(max_vfs, uint, 0);
217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218 #endif /* CONFIG_PCI_IOV */
219
220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223 static void igb_io_resume(struct pci_dev *);
224
225 static const struct pci_error_handlers igb_err_handler = {
226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229 };
230
231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
232
233 static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
237 .remove = igb_remove,
238 #ifdef CONFIG_PM
239 .driver.pm = &igb_pm_ops,
240 #endif
241 .shutdown = igb_shutdown,
242 .sriov_configure = igb_pci_sriov_configure,
243 .err_handler = &igb_err_handler
244 };
245
246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248 MODULE_LICENSE("GPL");
249 MODULE_VERSION(DRV_VERSION);
250
251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252 static int debug = -1;
253 module_param(debug, int, 0);
254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
256 struct igb_reg_info {
257 u32 ofs;
258 char *name;
259 };
260
261 static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295 };
296
297 /* igb_regdump - register printout routine */
298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299 {
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
361 }
362
363 /* igb_dump - Print registers, Tx-rings and Rx-rings */
364 static void igb_dump(struct igb_adapter *adapter)
365 {
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
375 u16 i, n;
376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
383 pr_info("Device Name state trans_start last_rx\n");
384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
390 pr_info(" Register Name Value\n");
391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
402 for (n = 0; n < adapter->num_tx_queues; n++) {
403 struct igb_tx_buffer *buffer_info;
404 tx_ring = adapter->tx_ring[n];
405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
461 buffer_info->skb, next_desc);
462
463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
466 16, 1, buffer_info->skb->data,
467 dma_unmap_len(buffer_info, len),
468 true);
469 }
470 }
471
472 /* Print RX Rings Summary */
473 rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 pr_info("Queue [NTU] [NTC]\n");
476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
516
517 for (i = 0; i < rx_ring->count; i++) {
518 const char *next_desc;
519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
521 rx_desc = IGB_RX_DESC(rx_ring, i);
522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
538 next_desc);
539 } else {
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
545 next_desc);
546
547 if (netif_msg_pktdata(adapter) &&
548 buffer_info->dma && buffer_info->page) {
549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
554 IGB_RX_BUFSZ, true);
555 }
556 }
557 }
558 }
559
560 exit:
561 return;
562 }
563
564 /**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
570 **/
571 static int igb_get_i2c_data(void *data)
572 {
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
577 return !!(i2cctl & E1000_I2C_DATA_IN);
578 }
579
580 /**
581 * igb_set_i2c_data - Sets the I2C data bit
582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
586 **/
587 static void igb_set_i2c_data(void *data, int state)
588 {
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603 }
604
605 /**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
611 **/
612 static void igb_set_i2c_clk(void *data, int state)
613 {
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627 }
628
629 /**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
634 **/
635 static int igb_get_i2c_clk(void *data)
636 {
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
641 return !!(i2cctl & E1000_I2C_CLK_IN);
642 }
643
644 static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651 };
652
653 /**
654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
658 **/
659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
660 {
661 struct igb_adapter *adapter = hw->back;
662 return adapter->netdev;
663 }
664
665 /**
666 * igb_init_module - Driver Registration Routine
667 *
668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
670 **/
671 static int __init igb_init_module(void)
672 {
673 int ret;
674
675 pr_info("%s - version %s\n",
676 igb_driver_string, igb_driver_version);
677 pr_info("%s\n", igb_copyright);
678
679 #ifdef CONFIG_IGB_DCA
680 dca_register_notify(&dca_notifier);
681 #endif
682 ret = pci_register_driver(&igb_driver);
683 return ret;
684 }
685
686 module_init(igb_init_module);
687
688 /**
689 * igb_exit_module - Driver Exit Cleanup Routine
690 *
691 * igb_exit_module is called just before the driver is removed
692 * from memory.
693 **/
694 static void __exit igb_exit_module(void)
695 {
696 #ifdef CONFIG_IGB_DCA
697 dca_unregister_notify(&dca_notifier);
698 #endif
699 pci_unregister_driver(&igb_driver);
700 }
701
702 module_exit(igb_exit_module);
703
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705 /**
706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
708 *
709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
711 **/
712 static void igb_cache_ring_register(struct igb_adapter *adapter)
713 {
714 int i = 0, j = 0;
715 u32 rbase_offset = adapter->vfs_allocated_count;
716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
724 if (adapter->vfs_allocated_count) {
725 for (; i < adapter->rss_queues; i++)
726 adapter->rx_ring[i]->reg_idx = rbase_offset +
727 Q_IDX_82576(i);
728 }
729 /* Fall through */
730 case e1000_82575:
731 case e1000_82580:
732 case e1000_i350:
733 case e1000_i354:
734 case e1000_i210:
735 case e1000_i211:
736 /* Fall through */
737 default:
738 for (; i < adapter->num_rx_queues; i++)
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 for (; j < adapter->num_tx_queues; j++)
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
742 break;
743 }
744 }
745
746 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747 {
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766 }
767
768 /**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782 {
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792 }
793
794 #define IGB_N0_QUEUE -1
795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
796 {
797 struct igb_adapter *adapter = q_vector->adapter;
798 struct e1000_hw *hw = &adapter->hw;
799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
801 u32 msixbm = 0;
802
803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
807
808 switch (hw->mac.type) {
809 case e1000_82575:
810 /* The 82575 assigns vectors using a bitmask, which matches the
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
815 if (rx_queue > IGB_N0_QUEUE)
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 if (tx_queue > IGB_N0_QUEUE)
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 msixbm |= E1000_EIMS_OTHER;
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 q_vector->eims_value = msixbm;
823 break;
824 case e1000_82576:
825 /* 82576 uses a table that essentially consists of 2 columns
826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
838 q_vector->eims_value = 1 << msix_vector;
839 break;
840 case e1000_82580:
841 case e1000_i350:
842 case e1000_i354:
843 case e1000_i210:
844 case e1000_i211:
845 /* On 82580 and newer adapters the scheme is similar to 82576
846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
859 q_vector->eims_value = 1 << msix_vector;
860 break;
861 default:
862 BUG();
863 break;
864 }
865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
871 }
872
873 /**
874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
876 *
877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
879 **/
880 static void igb_configure_msix(struct igb_adapter *adapter)
881 {
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
887
888 /* set vector for other causes, i.e. link changes */
889 switch (hw->mac.type) {
890 case e1000_82575:
891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
900
901 /* enable msix_other interrupt */
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 adapter->eims_other = E1000_EIMS_OTHER;
904
905 break;
906
907 case e1000_82576:
908 case e1000_82580:
909 case e1000_i350:
910 case e1000_i354:
911 case e1000_i210:
912 case e1000_i211:
913 /* Turn on MSI-X capability first, or our settings
914 * won't stick. And it will take days to debug.
915 */
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
923
924 wr32(E1000_IVAR_MISC, tmp);
925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
935
936 wrfl();
937 }
938
939 /**
940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
942 *
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
945 **/
946 static int igb_request_msix(struct igb_adapter *adapter)
947 {
948 struct net_device *netdev = adapter->netdev;
949 int i, err = 0, vector = 0, free_vector = 0;
950
951 err = request_irq(adapter->msix_entries[vector].vector,
952 igb_msix_other, 0, netdev->name, adapter);
953 if (err)
954 goto err_out;
955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
959 vector++;
960
961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
962
963 if (q_vector->rx.ring && q_vector->tx.ring)
964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
971 q_vector->rx.ring->queue_index);
972 else
973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
975 err = request_irq(adapter->msix_entries[vector].vector,
976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
978 if (err)
979 goto err_free;
980 }
981
982 igb_configure_msix(adapter);
983 return 0;
984
985 err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994 err_out:
995 return err;
996 }
997
998 /**
999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
1002 *
1003 * This function frees the memory allocated to the q_vector.
1004 **/
1005 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006 {
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
1016 }
1017
1018 /**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027 {
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1041
1042 netif_napi_del(&q_vector->napi);
1043
1044 }
1045
1046 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047 {
1048 int v_idx = adapter->num_q_vectors;
1049
1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1051 pci_disable_msix(adapter->pdev);
1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1053 pci_disable_msi(adapter->pdev);
1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
1057 }
1058
1059 /**
1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
1062 *
1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
1066 **/
1067 static void igb_free_q_vectors(struct igb_adapter *adapter)
1068 {
1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
1073 adapter->num_q_vectors = 0;
1074
1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
1077 igb_free_q_vector(adapter, v_idx);
1078 }
1079 }
1080
1081 /**
1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
1084 *
1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
1087 */
1088 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089 {
1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092 }
1093
1094 /**
1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
1098 *
1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
1101 **/
1102 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1103 {
1104 int err;
1105 int numvecs, i;
1106
1107 if (!msix)
1108 goto msi_only;
1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
1110
1111 /* Number of supported queues. */
1112 adapter->num_rx_queues = adapter->rss_queues;
1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
1117
1118 /* start with one vector for every Rx queue */
1119 numvecs = adapter->num_rx_queues;
1120
1121 /* if Tx handler is separate add 1 for every Tx queue */
1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
1138 return;
1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143 msi_only:
1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1145 #ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1156 wrfl();
1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160 #endif
1161 adapter->vfs_allocated_count = 0;
1162 adapter->rss_queues = 1;
1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1164 adapter->num_rx_queues = 1;
1165 adapter->num_tx_queues = 1;
1166 adapter->num_q_vectors = 1;
1167 if (!pci_enable_msi(adapter->pdev))
1168 adapter->flags |= IGB_FLAG_HAS_MSI;
1169 }
1170
1171 static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173 {
1174 head->ring = ring;
1175 head->count++;
1176 }
1177
1178 /**
1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
1187 *
1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1189 **/
1190 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
1194 {
1195 struct igb_q_vector *q_vector;
1196 struct igb_ring *ring;
1197 int ring_count, size;
1198
1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
1208 q_vector = adapter->q_vector[v_idx];
1209 if (!q_vector) {
1210 q_vector = kzalloc(size, GFP_KERNEL);
1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
1215 memset(q_vector, 0, size);
1216 }
1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
1276 }
1277
1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
1282
1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
1285
1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
1288
1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1292
1293 /* On i350, i354, i210, and i211, loopback VLAN packets
1294 * have the tag byte-swapped.
1295 */
1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1298
1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
1303 u64_stats_init(&ring->rx_syncp);
1304
1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
1310 }
1311
1312
1313 /**
1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
1316 *
1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
1319 **/
1320 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1321 {
1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
1327
1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
1332
1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
1339 }
1340 }
1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1345
1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
1359 return 0;
1360
1361 err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
1370 }
1371
1372 /**
1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
1376 *
1377 * This function initializes the interrupts and allocates all of the queues.
1378 **/
1379 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1380 {
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
1384 igb_set_interrupt_capability(adapter, msix);
1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
1392 igb_cache_ring_register(adapter);
1393
1394 return 0;
1395
1396 err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399 }
1400
1401 /**
1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
1404 *
1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
1407 **/
1408 static int igb_request_irq(struct igb_adapter *adapter)
1409 {
1410 struct net_device *netdev = adapter->netdev;
1411 struct pci_dev *pdev = adapter->pdev;
1412 int err = 0;
1413
1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1415 err = igb_request_msix(adapter);
1416 if (!err)
1417 goto request_done;
1418 /* fall back to MSI */
1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
1421
1422 igb_clear_interrupt_scheme(adapter);
1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
1425 goto request_done;
1426
1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
1429 igb_configure(adapter);
1430 }
1431
1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
1436 netdev->name, adapter);
1437 if (!err)
1438 goto request_done;
1439
1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1443 }
1444
1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1446 netdev->name, adapter);
1447
1448 if (err)
1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1450 err);
1451
1452 request_done:
1453 return err;
1454 }
1455
1456 static void igb_free_irq(struct igb_adapter *adapter)
1457 {
1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1459 int vector = 0, i;
1460
1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
1462
1463 for (i = 0; i < adapter->num_q_vectors; i++)
1464 free_irq(adapter->msix_entries[vector++].vector,
1465 adapter->q_vector[i]);
1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
1468 }
1469 }
1470
1471 /**
1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
1474 **/
1475 static void igb_irq_disable(struct igb_adapter *adapter)
1476 {
1477 struct e1000_hw *hw = &adapter->hw;
1478
1479 /* we need to be careful when disabling interrupts. The VFs are also
1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1484 u32 regval = rd32(E1000_EIAM);
1485
1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1490 }
1491
1492 wr32(E1000_IAM, 0);
1493 wr32(E1000_IMC, ~0);
1494 wrfl();
1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1496 int i;
1497
1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
1503 }
1504
1505 /**
1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
1508 **/
1509 static void igb_irq_enable(struct igb_adapter *adapter)
1510 {
1511 struct e1000_hw *hw = &adapter->hw;
1512
1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1515 u32 regval = rd32(E1000_EIAC);
1516
1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
1521 if (adapter->vfs_allocated_count) {
1522 wr32(E1000_MBVFIMR, 0xFF);
1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
1526 } else {
1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
1531 }
1532 }
1533
1534 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535 {
1536 struct e1000_hw *hw = &adapter->hw;
1537 u16 pf_id = adapter->vfs_allocated_count;
1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
1543 igb_vfta_set(hw, vid, pf_id, true, true);
1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
1551 !test_bit(old_vid, adapter->active_vlans)) {
1552 /* remove VID from filter table */
1553 igb_vfta_set(hw, vid, pf_id, false, true);
1554 }
1555 }
1556
1557 /**
1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
1560 *
1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
1564 **/
1565 static void igb_release_hw_control(struct igb_adapter *adapter)
1566 {
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574 }
1575
1576 /**
1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
1579 *
1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
1583 **/
1584 static void igb_get_hw_control(struct igb_adapter *adapter)
1585 {
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593 }
1594
1595 /**
1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
1598 **/
1599 static void igb_configure(struct igb_adapter *adapter)
1600 {
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
1605 igb_set_rx_mode(netdev);
1606
1607 igb_restore_vlan(adapter);
1608
1609 igb_setup_tctl(adapter);
1610 igb_setup_mrqc(adapter);
1611 igb_setup_rctl(adapter);
1612
1613 igb_configure_tx(adapter);
1614 igb_configure_rx(adapter);
1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
1618 /* call igb_desc_unused which always leaves
1619 * at least 1 descriptor unused to make sure
1620 * next_to_use != next_to_clean
1621 */
1622 for (i = 0; i < adapter->num_rx_queues; i++) {
1623 struct igb_ring *ring = adapter->rx_ring[i];
1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1625 }
1626 }
1627
1628 /**
1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
1631 **/
1632 void igb_power_up_link(struct igb_adapter *adapter)
1633 {
1634 igb_reset_phy(&adapter->hw);
1635
1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
1640
1641 igb_setup_link(&adapter->hw);
1642 }
1643
1644 /**
1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
1647 */
1648 static void igb_power_down_link(struct igb_adapter *adapter)
1649 {
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654 }
1655
1656 /**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660 static void igb_check_swap_media(struct igb_adapter *adapter)
1661 {
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721 }
1722
1723 /**
1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
1726 **/
1727 int igb_up(struct igb_adapter *adapter)
1728 {
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1741 igb_configure_msix(adapter);
1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
1752
1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
1757 netif_tx_start_all_queues(adapter->netdev);
1758
1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
1767 return 0;
1768 }
1769
1770 void igb_down(struct igb_adapter *adapter)
1771 {
1772 struct net_device *netdev = adapter->netdev;
1773 struct e1000_hw *hw = &adapter->hw;
1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
1778 * reschedule our watchdog timer
1779 */
1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
1787 netif_carrier_off(netdev);
1788 netif_tx_stop_all_queues(netdev);
1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
1796 usleep_range(10000, 11000);
1797
1798 igb_irq_disable(adapter);
1799
1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
1802 for (i = 0; i < adapter->num_q_vectors; i++) {
1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
1807 }
1808
1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
1812 /* record the stats before reset*/
1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
1816
1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
1822
1823 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1824 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1825
1826 igb_clean_all_tx_rings(adapter);
1827 igb_clean_all_rx_rings(adapter);
1828 #ifdef CONFIG_IGB_DCA
1829
1830 /* since we reset the hardware DCA settings were cleared */
1831 igb_setup_dca(adapter);
1832 #endif
1833 }
1834
1835 void igb_reinit_locked(struct igb_adapter *adapter)
1836 {
1837 WARN_ON(in_interrupt());
1838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1839 usleep_range(1000, 2000);
1840 igb_down(adapter);
1841 igb_up(adapter);
1842 clear_bit(__IGB_RESETTING, &adapter->state);
1843 }
1844
1845 /** igb_enable_mas - Media Autosense re-enable after swap
1846 *
1847 * @adapter: adapter struct
1848 **/
1849 static void igb_enable_mas(struct igb_adapter *adapter)
1850 {
1851 struct e1000_hw *hw = &adapter->hw;
1852 u32 connsw = rd32(E1000_CONNSW);
1853
1854 /* configure for SerDes media detect */
1855 if ((hw->phy.media_type == e1000_media_type_copper) &&
1856 (!(connsw & E1000_CONNSW_SERDESD))) {
1857 connsw |= E1000_CONNSW_ENRGSRC;
1858 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1859 wr32(E1000_CONNSW, connsw);
1860 wrfl();
1861 }
1862 }
1863
1864 void igb_reset(struct igb_adapter *adapter)
1865 {
1866 struct pci_dev *pdev = adapter->pdev;
1867 struct e1000_hw *hw = &adapter->hw;
1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
1870 u32 pba, hwm;
1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
1875 switch (mac->type) {
1876 case e1000_i350:
1877 case e1000_i354:
1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
1882 case e1000_82576:
1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
1885 break;
1886 case e1000_82575:
1887 case e1000_i210:
1888 case e1000_i211:
1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
1892 }
1893
1894 if (mac->type == e1000_82575) {
1895 u32 min_rx_space, min_tx_space, needed_tx_space;
1896
1897 /* write Rx PBA so that hardware can report correct Tx PBA */
1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
1905 * expressed in KB.
1906 */
1907 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1908
1909 /* The Tx FIFO also stores 16 bytes of information about the Tx
1910 * but don't include Ethernet FCS because hardware appends it.
1911 * We only need to round down to the nearest 512 byte block
1912 * count since the value we care about is 2 frames, not 1.
1913 */
1914 min_tx_space = adapter->max_frame_size;
1915 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1916 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1917
1918 /* upper 16 bits has Tx packet buffer allocation size in KB */
1919 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
1920
1921 /* If current Tx allocation is less than the min Tx FIFO size,
1922 * and the min Tx FIFO size is less than the current Rx FIFO
1923 * allocation, take space away from current Rx allocation.
1924 */
1925 if (needed_tx_space < pba) {
1926 pba -= needed_tx_space;
1927
1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
1934
1935 /* adjust PBA for jumbo frames */
1936 wr32(E1000_PBA, pba);
1937 }
1938
1939 /* flow control settings
1940 * The high water mark must be low enough to fit one full frame
1941 * after transmitting the pause frame. As such we must have enough
1942 * space to allow for us to complete our current transmit and then
1943 * receive the frame that is in progress from the link partner.
1944 * Set it to:
1945 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
1946 */
1947 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
1948
1949 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1950 fc->low_water = fc->high_water - 16;
1951 fc->pause_time = 0xFFFF;
1952 fc->send_xon = 1;
1953 fc->current_mode = fc->requested_mode;
1954
1955 /* disable receive for all VFs and wait one second */
1956 if (adapter->vfs_allocated_count) {
1957 int i;
1958
1959 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1960 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1961
1962 /* ping all the active vfs to let them know we are going down */
1963 igb_ping_all_vfs(adapter);
1964
1965 /* disable transmits and receives */
1966 wr32(E1000_VFRE, 0);
1967 wr32(E1000_VFTE, 0);
1968 }
1969
1970 /* Allow time for pending master requests to run */
1971 hw->mac.ops.reset_hw(hw);
1972 wr32(E1000_WUC, 0);
1973
1974 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1975 /* need to resetup here after media swap */
1976 adapter->ei.get_invariants(hw);
1977 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1978 }
1979 if ((mac->type == e1000_82575) &&
1980 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1981 igb_enable_mas(adapter);
1982 }
1983 if (hw->mac.ops.init_hw(hw))
1984 dev_err(&pdev->dev, "Hardware Error\n");
1985
1986 /* Flow control settings reset on hardware reset, so guarantee flow
1987 * control is off when forcing speed.
1988 */
1989 if (!hw->mac.autoneg)
1990 igb_force_mac_fc(hw);
1991
1992 igb_init_dmac(adapter, pba);
1993 #ifdef CONFIG_IGB_HWMON
1994 /* Re-initialize the thermal sensor on i350 devices. */
1995 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1996 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1997 /* If present, re-initialize the external thermal sensor
1998 * interface.
1999 */
2000 if (adapter->ets)
2001 mac->ops.init_thermal_sensor_thresh(hw);
2002 }
2003 }
2004 #endif
2005 /* Re-establish EEE setting */
2006 if (hw->phy.media_type == e1000_media_type_copper) {
2007 switch (mac->type) {
2008 case e1000_i350:
2009 case e1000_i210:
2010 case e1000_i211:
2011 igb_set_eee_i350(hw, true, true);
2012 break;
2013 case e1000_i354:
2014 igb_set_eee_i354(hw, true, true);
2015 break;
2016 default:
2017 break;
2018 }
2019 }
2020 if (!netif_running(adapter->netdev))
2021 igb_power_down_link(adapter);
2022
2023 igb_update_mng_vlan(adapter);
2024
2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2027
2028 /* Re-enable PTP, where applicable. */
2029 igb_ptp_reset(adapter);
2030
2031 igb_get_phy_info(hw);
2032 }
2033
2034 static netdev_features_t igb_fix_features(struct net_device *netdev,
2035 netdev_features_t features)
2036 {
2037 /* Since there is no support for separate Rx/Tx vlan accel
2038 * enable/disable make sure Tx flag is always in same state as Rx.
2039 */
2040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2041 features |= NETIF_F_HW_VLAN_CTAG_TX;
2042 else
2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2044
2045 return features;
2046 }
2047
2048 static int igb_set_features(struct net_device *netdev,
2049 netdev_features_t features)
2050 {
2051 netdev_features_t changed = netdev->features ^ features;
2052 struct igb_adapter *adapter = netdev_priv(netdev);
2053
2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2055 igb_vlan_mode(netdev, features);
2056
2057 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2058 return 0;
2059
2060 netdev->features = features;
2061
2062 if (netif_running(netdev))
2063 igb_reinit_locked(adapter);
2064 else
2065 igb_reset(adapter);
2066
2067 return 0;
2068 }
2069
2070 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2071 struct net_device *dev,
2072 const unsigned char *addr, u16 vid,
2073 u16 flags)
2074 {
2075 /* guarantee we can provide a unique filter for the unicast address */
2076 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2077 struct igb_adapter *adapter = netdev_priv(dev);
2078 struct e1000_hw *hw = &adapter->hw;
2079 int vfn = adapter->vfs_allocated_count;
2080 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2081
2082 if (netdev_uc_count(dev) >= rar_entries)
2083 return -ENOMEM;
2084 }
2085
2086 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2087 }
2088
2089 static const struct net_device_ops igb_netdev_ops = {
2090 .ndo_open = igb_open,
2091 .ndo_stop = igb_close,
2092 .ndo_start_xmit = igb_xmit_frame,
2093 .ndo_get_stats64 = igb_get_stats64,
2094 .ndo_set_rx_mode = igb_set_rx_mode,
2095 .ndo_set_mac_address = igb_set_mac,
2096 .ndo_change_mtu = igb_change_mtu,
2097 .ndo_do_ioctl = igb_ioctl,
2098 .ndo_tx_timeout = igb_tx_timeout,
2099 .ndo_validate_addr = eth_validate_addr,
2100 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2101 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2102 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2103 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2104 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2105 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2106 .ndo_get_vf_config = igb_ndo_get_vf_config,
2107 #ifdef CONFIG_NET_POLL_CONTROLLER
2108 .ndo_poll_controller = igb_netpoll,
2109 #endif
2110 .ndo_fix_features = igb_fix_features,
2111 .ndo_set_features = igb_set_features,
2112 .ndo_fdb_add = igb_ndo_fdb_add,
2113 .ndo_features_check = passthru_features_check,
2114 };
2115
2116 /**
2117 * igb_set_fw_version - Configure version string for ethtool
2118 * @adapter: adapter struct
2119 **/
2120 void igb_set_fw_version(struct igb_adapter *adapter)
2121 {
2122 struct e1000_hw *hw = &adapter->hw;
2123 struct e1000_fw_version fw;
2124
2125 igb_get_fw_version(hw, &fw);
2126
2127 switch (hw->mac.type) {
2128 case e1000_i210:
2129 case e1000_i211:
2130 if (!(igb_get_flash_presence_i210(hw))) {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%2d.%2d-%d",
2134 fw.invm_major, fw.invm_minor,
2135 fw.invm_img_type);
2136 break;
2137 }
2138 /* fall through */
2139 default:
2140 /* if option is rom valid, display its version too */
2141 if (fw.or_valid) {
2142 snprintf(adapter->fw_version,
2143 sizeof(adapter->fw_version),
2144 "%d.%d, 0x%08x, %d.%d.%d",
2145 fw.eep_major, fw.eep_minor, fw.etrack_id,
2146 fw.or_major, fw.or_build, fw.or_patch);
2147 /* no option rom */
2148 } else if (fw.etrack_id != 0X0000) {
2149 snprintf(adapter->fw_version,
2150 sizeof(adapter->fw_version),
2151 "%d.%d, 0x%08x",
2152 fw.eep_major, fw.eep_minor, fw.etrack_id);
2153 } else {
2154 snprintf(adapter->fw_version,
2155 sizeof(adapter->fw_version),
2156 "%d.%d.%d",
2157 fw.eep_major, fw.eep_minor, fw.eep_build);
2158 }
2159 break;
2160 }
2161 }
2162
2163 /**
2164 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2165 *
2166 * @adapter: adapter struct
2167 **/
2168 static void igb_init_mas(struct igb_adapter *adapter)
2169 {
2170 struct e1000_hw *hw = &adapter->hw;
2171 u16 eeprom_data;
2172
2173 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2174 switch (hw->bus.func) {
2175 case E1000_FUNC_0:
2176 if (eeprom_data & IGB_MAS_ENABLE_0) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_1:
2184 if (eeprom_data & IGB_MAS_ENABLE_1) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 case E1000_FUNC_2:
2192 if (eeprom_data & IGB_MAS_ENABLE_2) {
2193 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2194 netdev_info(adapter->netdev,
2195 "MAS: Enabling Media Autosense for port %d\n",
2196 hw->bus.func);
2197 }
2198 break;
2199 case E1000_FUNC_3:
2200 if (eeprom_data & IGB_MAS_ENABLE_3) {
2201 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2202 netdev_info(adapter->netdev,
2203 "MAS: Enabling Media Autosense for port %d\n",
2204 hw->bus.func);
2205 }
2206 break;
2207 default:
2208 /* Shouldn't get here */
2209 netdev_err(adapter->netdev,
2210 "MAS: Invalid port configuration, returning\n");
2211 break;
2212 }
2213 }
2214
2215 /**
2216 * igb_init_i2c - Init I2C interface
2217 * @adapter: pointer to adapter structure
2218 **/
2219 static s32 igb_init_i2c(struct igb_adapter *adapter)
2220 {
2221 s32 status = 0;
2222
2223 /* I2C interface supported on i350 devices */
2224 if (adapter->hw.mac.type != e1000_i350)
2225 return 0;
2226
2227 /* Initialize the i2c bus which is controlled by the registers.
2228 * This bus will use the i2c_algo_bit structue that implements
2229 * the protocol through toggling of the 4 bits in the register.
2230 */
2231 adapter->i2c_adap.owner = THIS_MODULE;
2232 adapter->i2c_algo = igb_i2c_algo;
2233 adapter->i2c_algo.data = adapter;
2234 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2235 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2236 strlcpy(adapter->i2c_adap.name, "igb BB",
2237 sizeof(adapter->i2c_adap.name));
2238 status = i2c_bit_add_bus(&adapter->i2c_adap);
2239 return status;
2240 }
2241
2242 /**
2243 * igb_probe - Device Initialization Routine
2244 * @pdev: PCI device information struct
2245 * @ent: entry in igb_pci_tbl
2246 *
2247 * Returns 0 on success, negative on failure
2248 *
2249 * igb_probe initializes an adapter identified by a pci_dev structure.
2250 * The OS initialization, configuring of the adapter private structure,
2251 * and a hardware reset occur.
2252 **/
2253 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2254 {
2255 struct net_device *netdev;
2256 struct igb_adapter *adapter;
2257 struct e1000_hw *hw;
2258 u16 eeprom_data = 0;
2259 s32 ret_val;
2260 static int global_quad_port_a; /* global quad port a indication */
2261 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2262 int err, pci_using_dac;
2263 u8 part_str[E1000_PBANUM_LENGTH];
2264
2265 /* Catch broken hardware that put the wrong VF device ID in
2266 * the PCIe SR-IOV capability.
2267 */
2268 if (pdev->is_virtfn) {
2269 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2270 pci_name(pdev), pdev->vendor, pdev->device);
2271 return -EINVAL;
2272 }
2273
2274 err = pci_enable_device_mem(pdev);
2275 if (err)
2276 return err;
2277
2278 pci_using_dac = 0;
2279 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2280 if (!err) {
2281 pci_using_dac = 1;
2282 } else {
2283 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2284 if (err) {
2285 dev_err(&pdev->dev,
2286 "No usable DMA configuration, aborting\n");
2287 goto err_dma;
2288 }
2289 }
2290
2291 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2292 IORESOURCE_MEM),
2293 igb_driver_name);
2294 if (err)
2295 goto err_pci_reg;
2296
2297 pci_enable_pcie_error_reporting(pdev);
2298
2299 pci_set_master(pdev);
2300 pci_save_state(pdev);
2301
2302 err = -ENOMEM;
2303 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2304 IGB_MAX_TX_QUEUES);
2305 if (!netdev)
2306 goto err_alloc_etherdev;
2307
2308 SET_NETDEV_DEV(netdev, &pdev->dev);
2309
2310 pci_set_drvdata(pdev, netdev);
2311 adapter = netdev_priv(netdev);
2312 adapter->netdev = netdev;
2313 adapter->pdev = pdev;
2314 hw = &adapter->hw;
2315 hw->back = adapter;
2316 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2317
2318 err = -EIO;
2319 adapter->io_addr = pci_iomap(pdev, 0, 0);
2320 if (!adapter->io_addr)
2321 goto err_ioremap;
2322 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2323 hw->hw_addr = adapter->io_addr;
2324
2325 netdev->netdev_ops = &igb_netdev_ops;
2326 igb_set_ethtool_ops(netdev);
2327 netdev->watchdog_timeo = 5 * HZ;
2328
2329 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2330
2331 netdev->mem_start = pci_resource_start(pdev, 0);
2332 netdev->mem_end = pci_resource_end(pdev, 0);
2333
2334 /* PCI config space info */
2335 hw->vendor_id = pdev->vendor;
2336 hw->device_id = pdev->device;
2337 hw->revision_id = pdev->revision;
2338 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2339 hw->subsystem_device_id = pdev->subsystem_device;
2340
2341 /* Copy the default MAC, PHY and NVM function pointers */
2342 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2343 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2344 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2345 /* Initialize skew-specific constants */
2346 err = ei->get_invariants(hw);
2347 if (err)
2348 goto err_sw_init;
2349
2350 /* setup the private structure */
2351 err = igb_sw_init(adapter);
2352 if (err)
2353 goto err_sw_init;
2354
2355 igb_get_bus_info_pcie(hw);
2356
2357 hw->phy.autoneg_wait_to_complete = false;
2358
2359 /* Copper options */
2360 if (hw->phy.media_type == e1000_media_type_copper) {
2361 hw->phy.mdix = AUTO_ALL_MODES;
2362 hw->phy.disable_polarity_correction = false;
2363 hw->phy.ms_type = e1000_ms_hw_default;
2364 }
2365
2366 if (igb_check_reset_block(hw))
2367 dev_info(&pdev->dev,
2368 "PHY reset is blocked due to SOL/IDER session.\n");
2369
2370 /* features is initialized to 0 in allocation, it might have bits
2371 * set by igb_sw_init so we should use an or instead of an
2372 * assignment.
2373 */
2374 netdev->features |= NETIF_F_SG |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_TSO |
2378 NETIF_F_TSO6 |
2379 NETIF_F_RXHASH |
2380 NETIF_F_RXCSUM |
2381 NETIF_F_HW_VLAN_CTAG_RX |
2382 NETIF_F_HW_VLAN_CTAG_TX;
2383
2384 /* copy netdev features into list of user selectable features */
2385 netdev->hw_features |= netdev->features;
2386 netdev->hw_features |= NETIF_F_RXALL;
2387
2388 /* set this bit last since it cannot be part of hw_features */
2389 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2390
2391 netdev->vlan_features |= NETIF_F_TSO |
2392 NETIF_F_TSO6 |
2393 NETIF_F_IP_CSUM |
2394 NETIF_F_IPV6_CSUM |
2395 NETIF_F_SG;
2396
2397 netdev->priv_flags |= IFF_SUPP_NOFCS;
2398
2399 if (pci_using_dac) {
2400 netdev->features |= NETIF_F_HIGHDMA;
2401 netdev->vlan_features |= NETIF_F_HIGHDMA;
2402 }
2403
2404 if (hw->mac.type >= e1000_82576) {
2405 netdev->hw_features |= NETIF_F_SCTP_CRC;
2406 netdev->features |= NETIF_F_SCTP_CRC;
2407 }
2408
2409 netdev->priv_flags |= IFF_UNICAST_FLT;
2410
2411 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2412
2413 /* before reading the NVM, reset the controller to put the device in a
2414 * known good starting state
2415 */
2416 hw->mac.ops.reset_hw(hw);
2417
2418 /* make sure the NVM is good , i211/i210 parts can have special NVM
2419 * that doesn't contain a checksum
2420 */
2421 switch (hw->mac.type) {
2422 case e1000_i210:
2423 case e1000_i211:
2424 if (igb_get_flash_presence_i210(hw)) {
2425 if (hw->nvm.ops.validate(hw) < 0) {
2426 dev_err(&pdev->dev,
2427 "The NVM Checksum Is Not Valid\n");
2428 err = -EIO;
2429 goto err_eeprom;
2430 }
2431 }
2432 break;
2433 default:
2434 if (hw->nvm.ops.validate(hw) < 0) {
2435 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2436 err = -EIO;
2437 goto err_eeprom;
2438 }
2439 break;
2440 }
2441
2442 /* copy the MAC address out of the NVM */
2443 if (hw->mac.ops.read_mac_addr(hw))
2444 dev_err(&pdev->dev, "NVM Read Error\n");
2445
2446 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2447
2448 if (!is_valid_ether_addr(netdev->dev_addr)) {
2449 dev_err(&pdev->dev, "Invalid MAC Address\n");
2450 err = -EIO;
2451 goto err_eeprom;
2452 }
2453
2454 /* get firmware version for ethtool -i */
2455 igb_set_fw_version(adapter);
2456
2457 /* configure RXPBSIZE and TXPBSIZE */
2458 if (hw->mac.type == e1000_i210) {
2459 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2460 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2461 }
2462
2463 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2464 (unsigned long) adapter);
2465 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2466 (unsigned long) adapter);
2467
2468 INIT_WORK(&adapter->reset_task, igb_reset_task);
2469 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2470
2471 /* Initialize link properties that are user-changeable */
2472 adapter->fc_autoneg = true;
2473 hw->mac.autoneg = true;
2474 hw->phy.autoneg_advertised = 0x2f;
2475
2476 hw->fc.requested_mode = e1000_fc_default;
2477 hw->fc.current_mode = e1000_fc_default;
2478
2479 igb_validate_mdi_setting(hw);
2480
2481 /* By default, support wake on port A */
2482 if (hw->bus.func == 0)
2483 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2484
2485 /* Check the NVM for wake support on non-port A ports */
2486 if (hw->mac.type >= e1000_82580)
2487 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2488 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2489 &eeprom_data);
2490 else if (hw->bus.func == 1)
2491 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2492
2493 if (eeprom_data & IGB_EEPROM_APME)
2494 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2495
2496 /* now that we have the eeprom settings, apply the special cases where
2497 * the eeprom may be wrong or the board simply won't support wake on
2498 * lan on a particular port
2499 */
2500 switch (pdev->device) {
2501 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2502 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2503 break;
2504 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2505 case E1000_DEV_ID_82576_FIBER:
2506 case E1000_DEV_ID_82576_SERDES:
2507 /* Wake events only supported on port A for dual fiber
2508 * regardless of eeprom setting
2509 */
2510 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2511 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2512 break;
2513 case E1000_DEV_ID_82576_QUAD_COPPER:
2514 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2515 /* if quad port adapter, disable WoL on all but port A */
2516 if (global_quad_port_a != 0)
2517 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2518 else
2519 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2520 /* Reset for multiple quad port adapters */
2521 if (++global_quad_port_a == 4)
2522 global_quad_port_a = 0;
2523 break;
2524 default:
2525 /* If the device can't wake, don't set software support */
2526 if (!device_can_wakeup(&adapter->pdev->dev))
2527 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2528 }
2529
2530 /* initialize the wol settings based on the eeprom settings */
2531 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2532 adapter->wol |= E1000_WUFC_MAG;
2533
2534 /* Some vendors want WoL disabled by default, but still supported */
2535 if ((hw->mac.type == e1000_i350) &&
2536 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2537 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2538 adapter->wol = 0;
2539 }
2540
2541 device_set_wakeup_enable(&adapter->pdev->dev,
2542 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2543
2544 /* reset the hardware with the new settings */
2545 igb_reset(adapter);
2546
2547 /* Init the I2C interface */
2548 err = igb_init_i2c(adapter);
2549 if (err) {
2550 dev_err(&pdev->dev, "failed to init i2c interface\n");
2551 goto err_eeprom;
2552 }
2553
2554 /* let the f/w know that the h/w is now under the control of the
2555 * driver.
2556 */
2557 igb_get_hw_control(adapter);
2558
2559 strcpy(netdev->name, "eth%d");
2560 err = register_netdev(netdev);
2561 if (err)
2562 goto err_register;
2563
2564 /* carrier off reporting is important to ethtool even BEFORE open */
2565 netif_carrier_off(netdev);
2566
2567 #ifdef CONFIG_IGB_DCA
2568 if (dca_add_requester(&pdev->dev) == 0) {
2569 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2570 dev_info(&pdev->dev, "DCA enabled\n");
2571 igb_setup_dca(adapter);
2572 }
2573
2574 #endif
2575 #ifdef CONFIG_IGB_HWMON
2576 /* Initialize the thermal sensor on i350 devices. */
2577 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2578 u16 ets_word;
2579
2580 /* Read the NVM to determine if this i350 device supports an
2581 * external thermal sensor.
2582 */
2583 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2584 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2585 adapter->ets = true;
2586 else
2587 adapter->ets = false;
2588 if (igb_sysfs_init(adapter))
2589 dev_err(&pdev->dev,
2590 "failed to allocate sysfs resources\n");
2591 } else {
2592 adapter->ets = false;
2593 }
2594 #endif
2595 /* Check if Media Autosense is enabled */
2596 adapter->ei = *ei;
2597 if (hw->dev_spec._82575.mas_capable)
2598 igb_init_mas(adapter);
2599
2600 /* do hw tstamp init after resetting */
2601 igb_ptp_init(adapter);
2602
2603 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2604 /* print bus type/speed/width info, not applicable to i354 */
2605 if (hw->mac.type != e1000_i354) {
2606 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2607 netdev->name,
2608 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2609 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2610 "unknown"),
2611 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2612 "Width x4" :
2613 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2614 "Width x2" :
2615 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2616 "Width x1" : "unknown"), netdev->dev_addr);
2617 }
2618
2619 if ((hw->mac.type >= e1000_i210 ||
2620 igb_get_flash_presence_i210(hw))) {
2621 ret_val = igb_read_part_string(hw, part_str,
2622 E1000_PBANUM_LENGTH);
2623 } else {
2624 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2625 }
2626
2627 if (ret_val)
2628 strcpy(part_str, "Unknown");
2629 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2630 dev_info(&pdev->dev,
2631 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2632 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2633 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2634 adapter->num_rx_queues, adapter->num_tx_queues);
2635 if (hw->phy.media_type == e1000_media_type_copper) {
2636 switch (hw->mac.type) {
2637 case e1000_i350:
2638 case e1000_i210:
2639 case e1000_i211:
2640 /* Enable EEE for internal copper PHY devices */
2641 err = igb_set_eee_i350(hw, true, true);
2642 if ((!err) &&
2643 (!hw->dev_spec._82575.eee_disable)) {
2644 adapter->eee_advert =
2645 MDIO_EEE_100TX | MDIO_EEE_1000T;
2646 adapter->flags |= IGB_FLAG_EEE;
2647 }
2648 break;
2649 case e1000_i354:
2650 if ((rd32(E1000_CTRL_EXT) &
2651 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2652 err = igb_set_eee_i354(hw, true, true);
2653 if ((!err) &&
2654 (!hw->dev_spec._82575.eee_disable)) {
2655 adapter->eee_advert =
2656 MDIO_EEE_100TX | MDIO_EEE_1000T;
2657 adapter->flags |= IGB_FLAG_EEE;
2658 }
2659 }
2660 break;
2661 default:
2662 break;
2663 }
2664 }
2665 pm_runtime_put_noidle(&pdev->dev);
2666 return 0;
2667
2668 err_register:
2669 igb_release_hw_control(adapter);
2670 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2671 err_eeprom:
2672 if (!igb_check_reset_block(hw))
2673 igb_reset_phy(hw);
2674
2675 if (hw->flash_address)
2676 iounmap(hw->flash_address);
2677 err_sw_init:
2678 kfree(adapter->shadow_vfta);
2679 igb_clear_interrupt_scheme(adapter);
2680 #ifdef CONFIG_PCI_IOV
2681 igb_disable_sriov(pdev);
2682 #endif
2683 pci_iounmap(pdev, adapter->io_addr);
2684 err_ioremap:
2685 free_netdev(netdev);
2686 err_alloc_etherdev:
2687 pci_release_selected_regions(pdev,
2688 pci_select_bars(pdev, IORESOURCE_MEM));
2689 err_pci_reg:
2690 err_dma:
2691 pci_disable_device(pdev);
2692 return err;
2693 }
2694
2695 #ifdef CONFIG_PCI_IOV
2696 static int igb_disable_sriov(struct pci_dev *pdev)
2697 {
2698 struct net_device *netdev = pci_get_drvdata(pdev);
2699 struct igb_adapter *adapter = netdev_priv(netdev);
2700 struct e1000_hw *hw = &adapter->hw;
2701
2702 /* reclaim resources allocated to VFs */
2703 if (adapter->vf_data) {
2704 /* disable iov and allow time for transactions to clear */
2705 if (pci_vfs_assigned(pdev)) {
2706 dev_warn(&pdev->dev,
2707 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2708 return -EPERM;
2709 } else {
2710 pci_disable_sriov(pdev);
2711 msleep(500);
2712 }
2713
2714 kfree(adapter->vf_data);
2715 adapter->vf_data = NULL;
2716 adapter->vfs_allocated_count = 0;
2717 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2718 wrfl();
2719 msleep(100);
2720 dev_info(&pdev->dev, "IOV Disabled\n");
2721
2722 /* Re-enable DMA Coalescing flag since IOV is turned off */
2723 adapter->flags |= IGB_FLAG_DMAC;
2724 }
2725
2726 return 0;
2727 }
2728
2729 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2730 {
2731 struct net_device *netdev = pci_get_drvdata(pdev);
2732 struct igb_adapter *adapter = netdev_priv(netdev);
2733 int old_vfs = pci_num_vf(pdev);
2734 int err = 0;
2735 int i;
2736
2737 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2738 err = -EPERM;
2739 goto out;
2740 }
2741 if (!num_vfs)
2742 goto out;
2743
2744 if (old_vfs) {
2745 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2746 old_vfs, max_vfs);
2747 adapter->vfs_allocated_count = old_vfs;
2748 } else
2749 adapter->vfs_allocated_count = num_vfs;
2750
2751 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2752 sizeof(struct vf_data_storage), GFP_KERNEL);
2753
2754 /* if allocation failed then we do not support SR-IOV */
2755 if (!adapter->vf_data) {
2756 adapter->vfs_allocated_count = 0;
2757 dev_err(&pdev->dev,
2758 "Unable to allocate memory for VF Data Storage\n");
2759 err = -ENOMEM;
2760 goto out;
2761 }
2762
2763 /* only call pci_enable_sriov() if no VFs are allocated already */
2764 if (!old_vfs) {
2765 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2766 if (err)
2767 goto err_out;
2768 }
2769 dev_info(&pdev->dev, "%d VFs allocated\n",
2770 adapter->vfs_allocated_count);
2771 for (i = 0; i < adapter->vfs_allocated_count; i++)
2772 igb_vf_configure(adapter, i);
2773
2774 /* DMA Coalescing is not supported in IOV mode. */
2775 adapter->flags &= ~IGB_FLAG_DMAC;
2776 goto out;
2777
2778 err_out:
2779 kfree(adapter->vf_data);
2780 adapter->vf_data = NULL;
2781 adapter->vfs_allocated_count = 0;
2782 out:
2783 return err;
2784 }
2785
2786 #endif
2787 /**
2788 * igb_remove_i2c - Cleanup I2C interface
2789 * @adapter: pointer to adapter structure
2790 **/
2791 static void igb_remove_i2c(struct igb_adapter *adapter)
2792 {
2793 /* free the adapter bus structure */
2794 i2c_del_adapter(&adapter->i2c_adap);
2795 }
2796
2797 /**
2798 * igb_remove - Device Removal Routine
2799 * @pdev: PCI device information struct
2800 *
2801 * igb_remove is called by the PCI subsystem to alert the driver
2802 * that it should release a PCI device. The could be caused by a
2803 * Hot-Plug event, or because the driver is going to be removed from
2804 * memory.
2805 **/
2806 static void igb_remove(struct pci_dev *pdev)
2807 {
2808 struct net_device *netdev = pci_get_drvdata(pdev);
2809 struct igb_adapter *adapter = netdev_priv(netdev);
2810 struct e1000_hw *hw = &adapter->hw;
2811
2812 pm_runtime_get_noresume(&pdev->dev);
2813 #ifdef CONFIG_IGB_HWMON
2814 igb_sysfs_exit(adapter);
2815 #endif
2816 igb_remove_i2c(adapter);
2817 igb_ptp_stop(adapter);
2818 /* The watchdog timer may be rescheduled, so explicitly
2819 * disable watchdog from being rescheduled.
2820 */
2821 set_bit(__IGB_DOWN, &adapter->state);
2822 del_timer_sync(&adapter->watchdog_timer);
2823 del_timer_sync(&adapter->phy_info_timer);
2824
2825 cancel_work_sync(&adapter->reset_task);
2826 cancel_work_sync(&adapter->watchdog_task);
2827
2828 #ifdef CONFIG_IGB_DCA
2829 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2830 dev_info(&pdev->dev, "DCA disabled\n");
2831 dca_remove_requester(&pdev->dev);
2832 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2833 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2834 }
2835 #endif
2836
2837 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2838 * would have already happened in close and is redundant.
2839 */
2840 igb_release_hw_control(adapter);
2841
2842 #ifdef CONFIG_PCI_IOV
2843 igb_disable_sriov(pdev);
2844 #endif
2845
2846 unregister_netdev(netdev);
2847
2848 igb_clear_interrupt_scheme(adapter);
2849
2850 pci_iounmap(pdev, adapter->io_addr);
2851 if (hw->flash_address)
2852 iounmap(hw->flash_address);
2853 pci_release_selected_regions(pdev,
2854 pci_select_bars(pdev, IORESOURCE_MEM));
2855
2856 kfree(adapter->shadow_vfta);
2857 free_netdev(netdev);
2858
2859 pci_disable_pcie_error_reporting(pdev);
2860
2861 pci_disable_device(pdev);
2862 }
2863
2864 /**
2865 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2866 * @adapter: board private structure to initialize
2867 *
2868 * This function initializes the vf specific data storage and then attempts to
2869 * allocate the VFs. The reason for ordering it this way is because it is much
2870 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2871 * the memory for the VFs.
2872 **/
2873 static void igb_probe_vfs(struct igb_adapter *adapter)
2874 {
2875 #ifdef CONFIG_PCI_IOV
2876 struct pci_dev *pdev = adapter->pdev;
2877 struct e1000_hw *hw = &adapter->hw;
2878
2879 /* Virtualization features not supported on i210 family. */
2880 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2881 return;
2882
2883 /* Of the below we really only want the effect of getting
2884 * IGB_FLAG_HAS_MSIX set (if available), without which
2885 * igb_enable_sriov() has no effect.
2886 */
2887 igb_set_interrupt_capability(adapter, true);
2888 igb_reset_interrupt_capability(adapter);
2889
2890 pci_sriov_set_totalvfs(pdev, 7);
2891 igb_enable_sriov(pdev, max_vfs);
2892
2893 #endif /* CONFIG_PCI_IOV */
2894 }
2895
2896 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2897 {
2898 struct e1000_hw *hw = &adapter->hw;
2899 u32 max_rss_queues;
2900
2901 /* Determine the maximum number of RSS queues supported. */
2902 switch (hw->mac.type) {
2903 case e1000_i211:
2904 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2905 break;
2906 case e1000_82575:
2907 case e1000_i210:
2908 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2909 break;
2910 case e1000_i350:
2911 /* I350 cannot do RSS and SR-IOV at the same time */
2912 if (!!adapter->vfs_allocated_count) {
2913 max_rss_queues = 1;
2914 break;
2915 }
2916 /* fall through */
2917 case e1000_82576:
2918 if (!!adapter->vfs_allocated_count) {
2919 max_rss_queues = 2;
2920 break;
2921 }
2922 /* fall through */
2923 case e1000_82580:
2924 case e1000_i354:
2925 default:
2926 max_rss_queues = IGB_MAX_RX_QUEUES;
2927 break;
2928 }
2929
2930 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2931
2932 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2933 }
2934
2935 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2936 const u32 max_rss_queues)
2937 {
2938 struct e1000_hw *hw = &adapter->hw;
2939
2940 /* Determine if we need to pair queues. */
2941 switch (hw->mac.type) {
2942 case e1000_82575:
2943 case e1000_i211:
2944 /* Device supports enough interrupts without queue pairing. */
2945 break;
2946 case e1000_82576:
2947 case e1000_82580:
2948 case e1000_i350:
2949 case e1000_i354:
2950 case e1000_i210:
2951 default:
2952 /* If rss_queues > half of max_rss_queues, pair the queues in
2953 * order to conserve interrupts due to limited supply.
2954 */
2955 if (adapter->rss_queues > (max_rss_queues / 2))
2956 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2957 else
2958 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
2959 break;
2960 }
2961 }
2962
2963 /**
2964 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2965 * @adapter: board private structure to initialize
2966 *
2967 * igb_sw_init initializes the Adapter private data structure.
2968 * Fields are initialized based on PCI device information and
2969 * OS network device settings (MTU size).
2970 **/
2971 static int igb_sw_init(struct igb_adapter *adapter)
2972 {
2973 struct e1000_hw *hw = &adapter->hw;
2974 struct net_device *netdev = adapter->netdev;
2975 struct pci_dev *pdev = adapter->pdev;
2976
2977 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2978
2979 /* set default ring sizes */
2980 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2981 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2982
2983 /* set default ITR values */
2984 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2985 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2986
2987 /* set default work limits */
2988 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2989
2990 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2991 VLAN_HLEN;
2992 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2993
2994 spin_lock_init(&adapter->stats64_lock);
2995 #ifdef CONFIG_PCI_IOV
2996 switch (hw->mac.type) {
2997 case e1000_82576:
2998 case e1000_i350:
2999 if (max_vfs > 7) {
3000 dev_warn(&pdev->dev,
3001 "Maximum of 7 VFs per PF, using max\n");
3002 max_vfs = adapter->vfs_allocated_count = 7;
3003 } else
3004 adapter->vfs_allocated_count = max_vfs;
3005 if (adapter->vfs_allocated_count)
3006 dev_warn(&pdev->dev,
3007 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3008 break;
3009 default:
3010 break;
3011 }
3012 #endif /* CONFIG_PCI_IOV */
3013
3014 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3015 adapter->flags |= IGB_FLAG_HAS_MSIX;
3016
3017 igb_probe_vfs(adapter);
3018
3019 igb_init_queue_configuration(adapter);
3020
3021 /* Setup and initialize a copy of the hw vlan table array */
3022 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3023 GFP_ATOMIC);
3024
3025 /* This call may decrease the number of queues */
3026 if (igb_init_interrupt_scheme(adapter, true)) {
3027 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3028 return -ENOMEM;
3029 }
3030
3031 /* Explicitly disable IRQ since the NIC can be in any state. */
3032 igb_irq_disable(adapter);
3033
3034 if (hw->mac.type >= e1000_i350)
3035 adapter->flags &= ~IGB_FLAG_DMAC;
3036
3037 set_bit(__IGB_DOWN, &adapter->state);
3038 return 0;
3039 }
3040
3041 /**
3042 * igb_open - Called when a network interface is made active
3043 * @netdev: network interface device structure
3044 *
3045 * Returns 0 on success, negative value on failure
3046 *
3047 * The open entry point is called when a network interface is made
3048 * active by the system (IFF_UP). At this point all resources needed
3049 * for transmit and receive operations are allocated, the interrupt
3050 * handler is registered with the OS, the watchdog timer is started,
3051 * and the stack is notified that the interface is ready.
3052 **/
3053 static int __igb_open(struct net_device *netdev, bool resuming)
3054 {
3055 struct igb_adapter *adapter = netdev_priv(netdev);
3056 struct e1000_hw *hw = &adapter->hw;
3057 struct pci_dev *pdev = adapter->pdev;
3058 int err;
3059 int i;
3060
3061 /* disallow open during test */
3062 if (test_bit(__IGB_TESTING, &adapter->state)) {
3063 WARN_ON(resuming);
3064 return -EBUSY;
3065 }
3066
3067 if (!resuming)
3068 pm_runtime_get_sync(&pdev->dev);
3069
3070 netif_carrier_off(netdev);
3071
3072 /* allocate transmit descriptors */
3073 err = igb_setup_all_tx_resources(adapter);
3074 if (err)
3075 goto err_setup_tx;
3076
3077 /* allocate receive descriptors */
3078 err = igb_setup_all_rx_resources(adapter);
3079 if (err)
3080 goto err_setup_rx;
3081
3082 igb_power_up_link(adapter);
3083
3084 /* before we allocate an interrupt, we must be ready to handle it.
3085 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3086 * as soon as we call pci_request_irq, so we have to setup our
3087 * clean_rx handler before we do so.
3088 */
3089 igb_configure(adapter);
3090
3091 err = igb_request_irq(adapter);
3092 if (err)
3093 goto err_req_irq;
3094
3095 /* Notify the stack of the actual queue counts. */
3096 err = netif_set_real_num_tx_queues(adapter->netdev,
3097 adapter->num_tx_queues);
3098 if (err)
3099 goto err_set_queues;
3100
3101 err = netif_set_real_num_rx_queues(adapter->netdev,
3102 adapter->num_rx_queues);
3103 if (err)
3104 goto err_set_queues;
3105
3106 /* From here on the code is the same as igb_up() */
3107 clear_bit(__IGB_DOWN, &adapter->state);
3108
3109 for (i = 0; i < adapter->num_q_vectors; i++)
3110 napi_enable(&(adapter->q_vector[i]->napi));
3111
3112 /* Clear any pending interrupts. */
3113 rd32(E1000_ICR);
3114
3115 igb_irq_enable(adapter);
3116
3117 /* notify VFs that reset has been completed */
3118 if (adapter->vfs_allocated_count) {
3119 u32 reg_data = rd32(E1000_CTRL_EXT);
3120
3121 reg_data |= E1000_CTRL_EXT_PFRSTD;
3122 wr32(E1000_CTRL_EXT, reg_data);
3123 }
3124
3125 netif_tx_start_all_queues(netdev);
3126
3127 if (!resuming)
3128 pm_runtime_put(&pdev->dev);
3129
3130 /* start the watchdog. */
3131 hw->mac.get_link_status = 1;
3132 schedule_work(&adapter->watchdog_task);
3133
3134 return 0;
3135
3136 err_set_queues:
3137 igb_free_irq(adapter);
3138 err_req_irq:
3139 igb_release_hw_control(adapter);
3140 igb_power_down_link(adapter);
3141 igb_free_all_rx_resources(adapter);
3142 err_setup_rx:
3143 igb_free_all_tx_resources(adapter);
3144 err_setup_tx:
3145 igb_reset(adapter);
3146 if (!resuming)
3147 pm_runtime_put(&pdev->dev);
3148
3149 return err;
3150 }
3151
3152 static int igb_open(struct net_device *netdev)
3153 {
3154 return __igb_open(netdev, false);
3155 }
3156
3157 /**
3158 * igb_close - Disables a network interface
3159 * @netdev: network interface device structure
3160 *
3161 * Returns 0, this is not allowed to fail
3162 *
3163 * The close entry point is called when an interface is de-activated
3164 * by the OS. The hardware is still under the driver's control, but
3165 * needs to be disabled. A global MAC reset is issued to stop the
3166 * hardware, and all transmit and receive resources are freed.
3167 **/
3168 static int __igb_close(struct net_device *netdev, bool suspending)
3169 {
3170 struct igb_adapter *adapter = netdev_priv(netdev);
3171 struct pci_dev *pdev = adapter->pdev;
3172
3173 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3174
3175 if (!suspending)
3176 pm_runtime_get_sync(&pdev->dev);
3177
3178 igb_down(adapter);
3179 igb_free_irq(adapter);
3180
3181 igb_free_all_tx_resources(adapter);
3182 igb_free_all_rx_resources(adapter);
3183
3184 if (!suspending)
3185 pm_runtime_put_sync(&pdev->dev);
3186 return 0;
3187 }
3188
3189 static int igb_close(struct net_device *netdev)
3190 {
3191 return __igb_close(netdev, false);
3192 }
3193
3194 /**
3195 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3196 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3197 *
3198 * Return 0 on success, negative on failure
3199 **/
3200 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3201 {
3202 struct device *dev = tx_ring->dev;
3203 int size;
3204
3205 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3206
3207 tx_ring->tx_buffer_info = vzalloc(size);
3208 if (!tx_ring->tx_buffer_info)
3209 goto err;
3210
3211 /* round up to nearest 4K */
3212 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3213 tx_ring->size = ALIGN(tx_ring->size, 4096);
3214
3215 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3216 &tx_ring->dma, GFP_KERNEL);
3217 if (!tx_ring->desc)
3218 goto err;
3219
3220 tx_ring->next_to_use = 0;
3221 tx_ring->next_to_clean = 0;
3222
3223 return 0;
3224
3225 err:
3226 vfree(tx_ring->tx_buffer_info);
3227 tx_ring->tx_buffer_info = NULL;
3228 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3229 return -ENOMEM;
3230 }
3231
3232 /**
3233 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3234 * (Descriptors) for all queues
3235 * @adapter: board private structure
3236 *
3237 * Return 0 on success, negative on failure
3238 **/
3239 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3240 {
3241 struct pci_dev *pdev = adapter->pdev;
3242 int i, err = 0;
3243
3244 for (i = 0; i < adapter->num_tx_queues; i++) {
3245 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3246 if (err) {
3247 dev_err(&pdev->dev,
3248 "Allocation for Tx Queue %u failed\n", i);
3249 for (i--; i >= 0; i--)
3250 igb_free_tx_resources(adapter->tx_ring[i]);
3251 break;
3252 }
3253 }
3254
3255 return err;
3256 }
3257
3258 /**
3259 * igb_setup_tctl - configure the transmit control registers
3260 * @adapter: Board private structure
3261 **/
3262 void igb_setup_tctl(struct igb_adapter *adapter)
3263 {
3264 struct e1000_hw *hw = &adapter->hw;
3265 u32 tctl;
3266
3267 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3268 wr32(E1000_TXDCTL(0), 0);
3269
3270 /* Program the Transmit Control Register */
3271 tctl = rd32(E1000_TCTL);
3272 tctl &= ~E1000_TCTL_CT;
3273 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3274 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3275
3276 igb_config_collision_dist(hw);
3277
3278 /* Enable transmits */
3279 tctl |= E1000_TCTL_EN;
3280
3281 wr32(E1000_TCTL, tctl);
3282 }
3283
3284 /**
3285 * igb_configure_tx_ring - Configure transmit ring after Reset
3286 * @adapter: board private structure
3287 * @ring: tx ring to configure
3288 *
3289 * Configure a transmit ring after a reset.
3290 **/
3291 void igb_configure_tx_ring(struct igb_adapter *adapter,
3292 struct igb_ring *ring)
3293 {
3294 struct e1000_hw *hw = &adapter->hw;
3295 u32 txdctl = 0;
3296 u64 tdba = ring->dma;
3297 int reg_idx = ring->reg_idx;
3298
3299 /* disable the queue */
3300 wr32(E1000_TXDCTL(reg_idx), 0);
3301 wrfl();
3302 mdelay(10);
3303
3304 wr32(E1000_TDLEN(reg_idx),
3305 ring->count * sizeof(union e1000_adv_tx_desc));
3306 wr32(E1000_TDBAL(reg_idx),
3307 tdba & 0x00000000ffffffffULL);
3308 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3309
3310 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3311 wr32(E1000_TDH(reg_idx), 0);
3312 writel(0, ring->tail);
3313
3314 txdctl |= IGB_TX_PTHRESH;
3315 txdctl |= IGB_TX_HTHRESH << 8;
3316 txdctl |= IGB_TX_WTHRESH << 16;
3317
3318 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3319 wr32(E1000_TXDCTL(reg_idx), txdctl);
3320 }
3321
3322 /**
3323 * igb_configure_tx - Configure transmit Unit after Reset
3324 * @adapter: board private structure
3325 *
3326 * Configure the Tx unit of the MAC after a reset.
3327 **/
3328 static void igb_configure_tx(struct igb_adapter *adapter)
3329 {
3330 int i;
3331
3332 for (i = 0; i < adapter->num_tx_queues; i++)
3333 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3334 }
3335
3336 /**
3337 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3338 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3339 *
3340 * Returns 0 on success, negative on failure
3341 **/
3342 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3343 {
3344 struct device *dev = rx_ring->dev;
3345 int size;
3346
3347 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3348
3349 rx_ring->rx_buffer_info = vzalloc(size);
3350 if (!rx_ring->rx_buffer_info)
3351 goto err;
3352
3353 /* Round up to nearest 4K */
3354 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3355 rx_ring->size = ALIGN(rx_ring->size, 4096);
3356
3357 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3358 &rx_ring->dma, GFP_KERNEL);
3359 if (!rx_ring->desc)
3360 goto err;
3361
3362 rx_ring->next_to_alloc = 0;
3363 rx_ring->next_to_clean = 0;
3364 rx_ring->next_to_use = 0;
3365
3366 return 0;
3367
3368 err:
3369 vfree(rx_ring->rx_buffer_info);
3370 rx_ring->rx_buffer_info = NULL;
3371 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3372 return -ENOMEM;
3373 }
3374
3375 /**
3376 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3377 * (Descriptors) for all queues
3378 * @adapter: board private structure
3379 *
3380 * Return 0 on success, negative on failure
3381 **/
3382 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3383 {
3384 struct pci_dev *pdev = adapter->pdev;
3385 int i, err = 0;
3386
3387 for (i = 0; i < adapter->num_rx_queues; i++) {
3388 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3389 if (err) {
3390 dev_err(&pdev->dev,
3391 "Allocation for Rx Queue %u failed\n", i);
3392 for (i--; i >= 0; i--)
3393 igb_free_rx_resources(adapter->rx_ring[i]);
3394 break;
3395 }
3396 }
3397
3398 return err;
3399 }
3400
3401 /**
3402 * igb_setup_mrqc - configure the multiple receive queue control registers
3403 * @adapter: Board private structure
3404 **/
3405 static void igb_setup_mrqc(struct igb_adapter *adapter)
3406 {
3407 struct e1000_hw *hw = &adapter->hw;
3408 u32 mrqc, rxcsum;
3409 u32 j, num_rx_queues;
3410 u32 rss_key[10];
3411
3412 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3413 for (j = 0; j < 10; j++)
3414 wr32(E1000_RSSRK(j), rss_key[j]);
3415
3416 num_rx_queues = adapter->rss_queues;
3417
3418 switch (hw->mac.type) {
3419 case e1000_82576:
3420 /* 82576 supports 2 RSS queues for SR-IOV */
3421 if (adapter->vfs_allocated_count)
3422 num_rx_queues = 2;
3423 break;
3424 default:
3425 break;
3426 }
3427
3428 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3429 for (j = 0; j < IGB_RETA_SIZE; j++)
3430 adapter->rss_indir_tbl[j] =
3431 (j * num_rx_queues) / IGB_RETA_SIZE;
3432 adapter->rss_indir_tbl_init = num_rx_queues;
3433 }
3434 igb_write_rss_indir_tbl(adapter);
3435
3436 /* Disable raw packet checksumming so that RSS hash is placed in
3437 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3438 * offloads as they are enabled by default
3439 */
3440 rxcsum = rd32(E1000_RXCSUM);
3441 rxcsum |= E1000_RXCSUM_PCSD;
3442
3443 if (adapter->hw.mac.type >= e1000_82576)
3444 /* Enable Receive Checksum Offload for SCTP */
3445 rxcsum |= E1000_RXCSUM_CRCOFL;
3446
3447 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3448 wr32(E1000_RXCSUM, rxcsum);
3449
3450 /* Generate RSS hash based on packet types, TCP/UDP
3451 * port numbers and/or IPv4/v6 src and dst addresses
3452 */
3453 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3454 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3455 E1000_MRQC_RSS_FIELD_IPV6 |
3456 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3457 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3458
3459 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3460 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3461 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3462 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3463
3464 /* If VMDq is enabled then we set the appropriate mode for that, else
3465 * we default to RSS so that an RSS hash is calculated per packet even
3466 * if we are only using one queue
3467 */
3468 if (adapter->vfs_allocated_count) {
3469 if (hw->mac.type > e1000_82575) {
3470 /* Set the default pool for the PF's first queue */
3471 u32 vtctl = rd32(E1000_VT_CTL);
3472
3473 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3474 E1000_VT_CTL_DISABLE_DEF_POOL);
3475 vtctl |= adapter->vfs_allocated_count <<
3476 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3477 wr32(E1000_VT_CTL, vtctl);
3478 }
3479 if (adapter->rss_queues > 1)
3480 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3481 else
3482 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3483 } else {
3484 if (hw->mac.type != e1000_i211)
3485 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3486 }
3487 igb_vmm_control(adapter);
3488
3489 wr32(E1000_MRQC, mrqc);
3490 }
3491
3492 /**
3493 * igb_setup_rctl - configure the receive control registers
3494 * @adapter: Board private structure
3495 **/
3496 void igb_setup_rctl(struct igb_adapter *adapter)
3497 {
3498 struct e1000_hw *hw = &adapter->hw;
3499 u32 rctl;
3500
3501 rctl = rd32(E1000_RCTL);
3502
3503 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3504 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3505
3506 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3507 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3508
3509 /* enable stripping of CRC. It's unlikely this will break BMC
3510 * redirection as it did with e1000. Newer features require
3511 * that the HW strips the CRC.
3512 */
3513 rctl |= E1000_RCTL_SECRC;
3514
3515 /* disable store bad packets and clear size bits. */
3516 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3517
3518 /* enable LPE to allow for reception of jumbo frames */
3519 rctl |= E1000_RCTL_LPE;
3520
3521 /* disable queue 0 to prevent tail write w/o re-config */
3522 wr32(E1000_RXDCTL(0), 0);
3523
3524 /* Attention!!! For SR-IOV PF driver operations you must enable
3525 * queue drop for all VF and PF queues to prevent head of line blocking
3526 * if an un-trusted VF does not provide descriptors to hardware.
3527 */
3528 if (adapter->vfs_allocated_count) {
3529 /* set all queue drop enable bits */
3530 wr32(E1000_QDE, ALL_QUEUES);
3531 }
3532
3533 /* This is useful for sniffing bad packets. */
3534 if (adapter->netdev->features & NETIF_F_RXALL) {
3535 /* UPE and MPE will be handled by normal PROMISC logic
3536 * in e1000e_set_rx_mode
3537 */
3538 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3539 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3540 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3541
3542 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
3543 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3544 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3545 * and that breaks VLANs.
3546 */
3547 }
3548
3549 wr32(E1000_RCTL, rctl);
3550 }
3551
3552 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3553 int vfn)
3554 {
3555 struct e1000_hw *hw = &adapter->hw;
3556 u32 vmolr;
3557
3558 if (size > MAX_JUMBO_FRAME_SIZE)
3559 size = MAX_JUMBO_FRAME_SIZE;
3560
3561 vmolr = rd32(E1000_VMOLR(vfn));
3562 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3563 vmolr |= size | E1000_VMOLR_LPE;
3564 wr32(E1000_VMOLR(vfn), vmolr);
3565
3566 return 0;
3567 }
3568
3569 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3570 int vfn, bool aupe)
3571 {
3572 struct e1000_hw *hw = &adapter->hw;
3573 u32 vmolr;
3574
3575 /* This register exists only on 82576 and newer so if we are older then
3576 * we should exit and do nothing
3577 */
3578 if (hw->mac.type < e1000_82576)
3579 return;
3580
3581 vmolr = rd32(E1000_VMOLR(vfn));
3582 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3583 if (hw->mac.type == e1000_i350) {
3584 u32 dvmolr;
3585
3586 dvmolr = rd32(E1000_DVMOLR(vfn));
3587 dvmolr |= E1000_DVMOLR_STRVLAN;
3588 wr32(E1000_DVMOLR(vfn), dvmolr);
3589 }
3590 if (aupe)
3591 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3592 else
3593 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3594
3595 /* clear all bits that might not be set */
3596 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3597
3598 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3599 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3600 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3601 * multicast packets
3602 */
3603 if (vfn <= adapter->vfs_allocated_count)
3604 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3605
3606 wr32(E1000_VMOLR(vfn), vmolr);
3607 }
3608
3609 /**
3610 * igb_configure_rx_ring - Configure a receive ring after Reset
3611 * @adapter: board private structure
3612 * @ring: receive ring to be configured
3613 *
3614 * Configure the Rx unit of the MAC after a reset.
3615 **/
3616 void igb_configure_rx_ring(struct igb_adapter *adapter,
3617 struct igb_ring *ring)
3618 {
3619 struct e1000_hw *hw = &adapter->hw;
3620 u64 rdba = ring->dma;
3621 int reg_idx = ring->reg_idx;
3622 u32 srrctl = 0, rxdctl = 0;
3623
3624 /* disable the queue */
3625 wr32(E1000_RXDCTL(reg_idx), 0);
3626
3627 /* Set DMA base address registers */
3628 wr32(E1000_RDBAL(reg_idx),
3629 rdba & 0x00000000ffffffffULL);
3630 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3631 wr32(E1000_RDLEN(reg_idx),
3632 ring->count * sizeof(union e1000_adv_rx_desc));
3633
3634 /* initialize head and tail */
3635 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3636 wr32(E1000_RDH(reg_idx), 0);
3637 writel(0, ring->tail);
3638
3639 /* set descriptor configuration */
3640 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3641 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3642 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3643 if (hw->mac.type >= e1000_82580)
3644 srrctl |= E1000_SRRCTL_TIMESTAMP;
3645 /* Only set Drop Enable if we are supporting multiple queues */
3646 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3647 srrctl |= E1000_SRRCTL_DROP_EN;
3648
3649 wr32(E1000_SRRCTL(reg_idx), srrctl);
3650
3651 /* set filtering for VMDQ pools */
3652 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3653
3654 rxdctl |= IGB_RX_PTHRESH;
3655 rxdctl |= IGB_RX_HTHRESH << 8;
3656 rxdctl |= IGB_RX_WTHRESH << 16;
3657
3658 /* enable receive descriptor fetching */
3659 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3660 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3661 }
3662
3663 /**
3664 * igb_configure_rx - Configure receive Unit after Reset
3665 * @adapter: board private structure
3666 *
3667 * Configure the Rx unit of the MAC after a reset.
3668 **/
3669 static void igb_configure_rx(struct igb_adapter *adapter)
3670 {
3671 int i;
3672
3673 /* set the correct pool for the PF default MAC address in entry 0 */
3674 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3675 adapter->vfs_allocated_count);
3676
3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3678 * the Base and Length of the Rx Descriptor Ring
3679 */
3680 for (i = 0; i < adapter->num_rx_queues; i++)
3681 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3682 }
3683
3684 /**
3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
3687 *
3688 * Free all transmit software resources
3689 **/
3690 void igb_free_tx_resources(struct igb_ring *tx_ring)
3691 {
3692 igb_clean_tx_ring(tx_ring);
3693
3694 vfree(tx_ring->tx_buffer_info);
3695 tx_ring->tx_buffer_info = NULL;
3696
3697 /* if not set, then don't free */
3698 if (!tx_ring->desc)
3699 return;
3700
3701 dma_free_coherent(tx_ring->dev, tx_ring->size,
3702 tx_ring->desc, tx_ring->dma);
3703
3704 tx_ring->desc = NULL;
3705 }
3706
3707 /**
3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
3710 *
3711 * Free all transmit software resources
3712 **/
3713 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3714 {
3715 int i;
3716
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3718 if (adapter->tx_ring[i])
3719 igb_free_tx_resources(adapter->tx_ring[i]);
3720 }
3721
3722 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3723 struct igb_tx_buffer *tx_buffer)
3724 {
3725 if (tx_buffer->skb) {
3726 dev_kfree_skb_any(tx_buffer->skb);
3727 if (dma_unmap_len(tx_buffer, len))
3728 dma_unmap_single(ring->dev,
3729 dma_unmap_addr(tx_buffer, dma),
3730 dma_unmap_len(tx_buffer, len),
3731 DMA_TO_DEVICE);
3732 } else if (dma_unmap_len(tx_buffer, len)) {
3733 dma_unmap_page(ring->dev,
3734 dma_unmap_addr(tx_buffer, dma),
3735 dma_unmap_len(tx_buffer, len),
3736 DMA_TO_DEVICE);
3737 }
3738 tx_buffer->next_to_watch = NULL;
3739 tx_buffer->skb = NULL;
3740 dma_unmap_len_set(tx_buffer, len, 0);
3741 /* buffer_info must be completely set up in the transmit path */
3742 }
3743
3744 /**
3745 * igb_clean_tx_ring - Free Tx Buffers
3746 * @tx_ring: ring to be cleaned
3747 **/
3748 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3749 {
3750 struct igb_tx_buffer *buffer_info;
3751 unsigned long size;
3752 u16 i;
3753
3754 if (!tx_ring->tx_buffer_info)
3755 return;
3756 /* Free all the Tx ring sk_buffs */
3757
3758 for (i = 0; i < tx_ring->count; i++) {
3759 buffer_info = &tx_ring->tx_buffer_info[i];
3760 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3761 }
3762
3763 netdev_tx_reset_queue(txring_txq(tx_ring));
3764
3765 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3766 memset(tx_ring->tx_buffer_info, 0, size);
3767
3768 /* Zero out the descriptor ring */
3769 memset(tx_ring->desc, 0, tx_ring->size);
3770
3771 tx_ring->next_to_use = 0;
3772 tx_ring->next_to_clean = 0;
3773 }
3774
3775 /**
3776 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3777 * @adapter: board private structure
3778 **/
3779 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3780 {
3781 int i;
3782
3783 for (i = 0; i < adapter->num_tx_queues; i++)
3784 if (adapter->tx_ring[i])
3785 igb_clean_tx_ring(adapter->tx_ring[i]);
3786 }
3787
3788 /**
3789 * igb_free_rx_resources - Free Rx Resources
3790 * @rx_ring: ring to clean the resources from
3791 *
3792 * Free all receive software resources
3793 **/
3794 void igb_free_rx_resources(struct igb_ring *rx_ring)
3795 {
3796 igb_clean_rx_ring(rx_ring);
3797
3798 vfree(rx_ring->rx_buffer_info);
3799 rx_ring->rx_buffer_info = NULL;
3800
3801 /* if not set, then don't free */
3802 if (!rx_ring->desc)
3803 return;
3804
3805 dma_free_coherent(rx_ring->dev, rx_ring->size,
3806 rx_ring->desc, rx_ring->dma);
3807
3808 rx_ring->desc = NULL;
3809 }
3810
3811 /**
3812 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3813 * @adapter: board private structure
3814 *
3815 * Free all receive software resources
3816 **/
3817 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3818 {
3819 int i;
3820
3821 for (i = 0; i < adapter->num_rx_queues; i++)
3822 if (adapter->rx_ring[i])
3823 igb_free_rx_resources(adapter->rx_ring[i]);
3824 }
3825
3826 /**
3827 * igb_clean_rx_ring - Free Rx Buffers per Queue
3828 * @rx_ring: ring to free buffers from
3829 **/
3830 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3831 {
3832 unsigned long size;
3833 u16 i;
3834
3835 if (rx_ring->skb)
3836 dev_kfree_skb(rx_ring->skb);
3837 rx_ring->skb = NULL;
3838
3839 if (!rx_ring->rx_buffer_info)
3840 return;
3841
3842 /* Free all the Rx ring sk_buffs */
3843 for (i = 0; i < rx_ring->count; i++) {
3844 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3845
3846 if (!buffer_info->page)
3847 continue;
3848
3849 dma_unmap_page(rx_ring->dev,
3850 buffer_info->dma,
3851 PAGE_SIZE,
3852 DMA_FROM_DEVICE);
3853 __free_page(buffer_info->page);
3854
3855 buffer_info->page = NULL;
3856 }
3857
3858 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3859 memset(rx_ring->rx_buffer_info, 0, size);
3860
3861 /* Zero out the descriptor ring */
3862 memset(rx_ring->desc, 0, rx_ring->size);
3863
3864 rx_ring->next_to_alloc = 0;
3865 rx_ring->next_to_clean = 0;
3866 rx_ring->next_to_use = 0;
3867 }
3868
3869 /**
3870 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3871 * @adapter: board private structure
3872 **/
3873 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3874 {
3875 int i;
3876
3877 for (i = 0; i < adapter->num_rx_queues; i++)
3878 if (adapter->rx_ring[i])
3879 igb_clean_rx_ring(adapter->rx_ring[i]);
3880 }
3881
3882 /**
3883 * igb_set_mac - Change the Ethernet Address of the NIC
3884 * @netdev: network interface device structure
3885 * @p: pointer to an address structure
3886 *
3887 * Returns 0 on success, negative on failure
3888 **/
3889 static int igb_set_mac(struct net_device *netdev, void *p)
3890 {
3891 struct igb_adapter *adapter = netdev_priv(netdev);
3892 struct e1000_hw *hw = &adapter->hw;
3893 struct sockaddr *addr = p;
3894
3895 if (!is_valid_ether_addr(addr->sa_data))
3896 return -EADDRNOTAVAIL;
3897
3898 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3899 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3900
3901 /* set the correct pool for the new PF MAC address in entry 0 */
3902 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3903 adapter->vfs_allocated_count);
3904
3905 return 0;
3906 }
3907
3908 /**
3909 * igb_write_mc_addr_list - write multicast addresses to MTA
3910 * @netdev: network interface device structure
3911 *
3912 * Writes multicast address list to the MTA hash table.
3913 * Returns: -ENOMEM on failure
3914 * 0 on no addresses written
3915 * X on writing X addresses to MTA
3916 **/
3917 static int igb_write_mc_addr_list(struct net_device *netdev)
3918 {
3919 struct igb_adapter *adapter = netdev_priv(netdev);
3920 struct e1000_hw *hw = &adapter->hw;
3921 struct netdev_hw_addr *ha;
3922 u8 *mta_list;
3923 int i;
3924
3925 if (netdev_mc_empty(netdev)) {
3926 /* nothing to program, so clear mc list */
3927 igb_update_mc_addr_list(hw, NULL, 0);
3928 igb_restore_vf_multicasts(adapter);
3929 return 0;
3930 }
3931
3932 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3933 if (!mta_list)
3934 return -ENOMEM;
3935
3936 /* The shared function expects a packed array of only addresses. */
3937 i = 0;
3938 netdev_for_each_mc_addr(ha, netdev)
3939 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3940
3941 igb_update_mc_addr_list(hw, mta_list, i);
3942 kfree(mta_list);
3943
3944 return netdev_mc_count(netdev);
3945 }
3946
3947 /**
3948 * igb_write_uc_addr_list - write unicast addresses to RAR table
3949 * @netdev: network interface device structure
3950 *
3951 * Writes unicast address list to the RAR table.
3952 * Returns: -ENOMEM on failure/insufficient address space
3953 * 0 on no addresses written
3954 * X on writing X addresses to the RAR table
3955 **/
3956 static int igb_write_uc_addr_list(struct net_device *netdev)
3957 {
3958 struct igb_adapter *adapter = netdev_priv(netdev);
3959 struct e1000_hw *hw = &adapter->hw;
3960 unsigned int vfn = adapter->vfs_allocated_count;
3961 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3962 int count = 0;
3963
3964 /* return ENOMEM indicating insufficient memory for addresses */
3965 if (netdev_uc_count(netdev) > rar_entries)
3966 return -ENOMEM;
3967
3968 if (!netdev_uc_empty(netdev) && rar_entries) {
3969 struct netdev_hw_addr *ha;
3970
3971 netdev_for_each_uc_addr(ha, netdev) {
3972 if (!rar_entries)
3973 break;
3974 igb_rar_set_qsel(adapter, ha->addr,
3975 rar_entries--,
3976 vfn);
3977 count++;
3978 }
3979 }
3980 /* write the addresses in reverse order to avoid write combining */
3981 for (; rar_entries > 0 ; rar_entries--) {
3982 wr32(E1000_RAH(rar_entries), 0);
3983 wr32(E1000_RAL(rar_entries), 0);
3984 }
3985 wrfl();
3986
3987 return count;
3988 }
3989
3990 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
3991 {
3992 struct e1000_hw *hw = &adapter->hw;
3993 u32 i, pf_id;
3994
3995 switch (hw->mac.type) {
3996 case e1000_i210:
3997 case e1000_i211:
3998 case e1000_i350:
3999 /* VLAN filtering needed for VLAN prio filter */
4000 if (adapter->netdev->features & NETIF_F_NTUPLE)
4001 break;
4002 /* fall through */
4003 case e1000_82576:
4004 case e1000_82580:
4005 case e1000_i354:
4006 /* VLAN filtering needed for pool filtering */
4007 if (adapter->vfs_allocated_count)
4008 break;
4009 /* fall through */
4010 default:
4011 return 1;
4012 }
4013
4014 /* We are already in VLAN promisc, nothing to do */
4015 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4016 return 0;
4017
4018 if (!adapter->vfs_allocated_count)
4019 goto set_vfta;
4020
4021 /* Add PF to all active pools */
4022 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4023
4024 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4025 u32 vlvf = rd32(E1000_VLVF(i));
4026
4027 vlvf |= 1 << pf_id;
4028 wr32(E1000_VLVF(i), vlvf);
4029 }
4030
4031 set_vfta:
4032 /* Set all bits in the VLAN filter table array */
4033 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4034 hw->mac.ops.write_vfta(hw, i, ~0U);
4035
4036 /* Set flag so we don't redo unnecessary work */
4037 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4038
4039 return 0;
4040 }
4041
4042 #define VFTA_BLOCK_SIZE 8
4043 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4044 {
4045 struct e1000_hw *hw = &adapter->hw;
4046 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4047 u32 vid_start = vfta_offset * 32;
4048 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4049 u32 i, vid, word, bits, pf_id;
4050
4051 /* guarantee that we don't scrub out management VLAN */
4052 vid = adapter->mng_vlan_id;
4053 if (vid >= vid_start && vid < vid_end)
4054 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4055
4056 if (!adapter->vfs_allocated_count)
4057 goto set_vfta;
4058
4059 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4060
4061 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4062 u32 vlvf = rd32(E1000_VLVF(i));
4063
4064 /* pull VLAN ID from VLVF */
4065 vid = vlvf & VLAN_VID_MASK;
4066
4067 /* only concern ourselves with a certain range */
4068 if (vid < vid_start || vid >= vid_end)
4069 continue;
4070
4071 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4072 /* record VLAN ID in VFTA */
4073 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4074
4075 /* if PF is part of this then continue */
4076 if (test_bit(vid, adapter->active_vlans))
4077 continue;
4078 }
4079
4080 /* remove PF from the pool */
4081 bits = ~(1 << pf_id);
4082 bits &= rd32(E1000_VLVF(i));
4083 wr32(E1000_VLVF(i), bits);
4084 }
4085
4086 set_vfta:
4087 /* extract values from active_vlans and write back to VFTA */
4088 for (i = VFTA_BLOCK_SIZE; i--;) {
4089 vid = (vfta_offset + i) * 32;
4090 word = vid / BITS_PER_LONG;
4091 bits = vid % BITS_PER_LONG;
4092
4093 vfta[i] |= adapter->active_vlans[word] >> bits;
4094
4095 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4096 }
4097 }
4098
4099 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4100 {
4101 u32 i;
4102
4103 /* We are not in VLAN promisc, nothing to do */
4104 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4105 return;
4106
4107 /* Set flag so we don't redo unnecessary work */
4108 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4109
4110 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4111 igb_scrub_vfta(adapter, i);
4112 }
4113
4114 /**
4115 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4116 * @netdev: network interface device structure
4117 *
4118 * The set_rx_mode entry point is called whenever the unicast or multicast
4119 * address lists or the network interface flags are updated. This routine is
4120 * responsible for configuring the hardware for proper unicast, multicast,
4121 * promiscuous mode, and all-multi behavior.
4122 **/
4123 static void igb_set_rx_mode(struct net_device *netdev)
4124 {
4125 struct igb_adapter *adapter = netdev_priv(netdev);
4126 struct e1000_hw *hw = &adapter->hw;
4127 unsigned int vfn = adapter->vfs_allocated_count;
4128 u32 rctl = 0, vmolr = 0;
4129 int count;
4130
4131 /* Check for Promiscuous and All Multicast modes */
4132 if (netdev->flags & IFF_PROMISC) {
4133 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
4134 vmolr |= E1000_VMOLR_MPME;
4135
4136 /* enable use of UTA filter to force packets to default pool */
4137 if (hw->mac.type == e1000_82576)
4138 vmolr |= E1000_VMOLR_ROPE;
4139 } else {
4140 if (netdev->flags & IFF_ALLMULTI) {
4141 rctl |= E1000_RCTL_MPE;
4142 vmolr |= E1000_VMOLR_MPME;
4143 } else {
4144 /* Write addresses to the MTA, if the attempt fails
4145 * then we should just turn on promiscuous mode so
4146 * that we can at least receive multicast traffic
4147 */
4148 count = igb_write_mc_addr_list(netdev);
4149 if (count < 0) {
4150 rctl |= E1000_RCTL_MPE;
4151 vmolr |= E1000_VMOLR_MPME;
4152 } else if (count) {
4153 vmolr |= E1000_VMOLR_ROMPE;
4154 }
4155 }
4156 }
4157
4158 /* Write addresses to available RAR registers, if there is not
4159 * sufficient space to store all the addresses then enable
4160 * unicast promiscuous mode
4161 */
4162 count = igb_write_uc_addr_list(netdev);
4163 if (count < 0) {
4164 rctl |= E1000_RCTL_UPE;
4165 vmolr |= E1000_VMOLR_ROPE;
4166 }
4167
4168 /* enable VLAN filtering by default */
4169 rctl |= E1000_RCTL_VFE;
4170
4171 /* disable VLAN filtering for modes that require it */
4172 if ((netdev->flags & IFF_PROMISC) ||
4173 (netdev->features & NETIF_F_RXALL)) {
4174 /* if we fail to set all rules then just clear VFE */
4175 if (igb_vlan_promisc_enable(adapter))
4176 rctl &= ~E1000_RCTL_VFE;
4177 } else {
4178 igb_vlan_promisc_disable(adapter);
4179 }
4180
4181 /* update state of unicast, multicast, and VLAN filtering modes */
4182 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4183 E1000_RCTL_VFE);
4184 wr32(E1000_RCTL, rctl);
4185
4186 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4187 * the VMOLR to enable the appropriate modes. Without this workaround
4188 * we will have issues with VLAN tag stripping not being done for frames
4189 * that are only arriving because we are the default pool
4190 */
4191 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4192 return;
4193
4194 /* set UTA to appropriate mode */
4195 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4196
4197 vmolr |= rd32(E1000_VMOLR(vfn)) &
4198 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4199
4200 /* enable Rx jumbo frames, no need for restriction */
4201 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4202 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4203
4204 wr32(E1000_VMOLR(vfn), vmolr);
4205 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4206
4207 igb_restore_vf_multicasts(adapter);
4208 }
4209
4210 static void igb_check_wvbr(struct igb_adapter *adapter)
4211 {
4212 struct e1000_hw *hw = &adapter->hw;
4213 u32 wvbr = 0;
4214
4215 switch (hw->mac.type) {
4216 case e1000_82576:
4217 case e1000_i350:
4218 wvbr = rd32(E1000_WVBR);
4219 if (!wvbr)
4220 return;
4221 break;
4222 default:
4223 break;
4224 }
4225
4226 adapter->wvbr |= wvbr;
4227 }
4228
4229 #define IGB_STAGGERED_QUEUE_OFFSET 8
4230
4231 static void igb_spoof_check(struct igb_adapter *adapter)
4232 {
4233 int j;
4234
4235 if (!adapter->wvbr)
4236 return;
4237
4238 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4239 if (adapter->wvbr & (1 << j) ||
4240 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4241 dev_warn(&adapter->pdev->dev,
4242 "Spoof event(s) detected on VF %d\n", j);
4243 adapter->wvbr &=
4244 ~((1 << j) |
4245 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4246 }
4247 }
4248 }
4249
4250 /* Need to wait a few seconds after link up to get diagnostic information from
4251 * the phy
4252 */
4253 static void igb_update_phy_info(unsigned long data)
4254 {
4255 struct igb_adapter *adapter = (struct igb_adapter *) data;
4256 igb_get_phy_info(&adapter->hw);
4257 }
4258
4259 /**
4260 * igb_has_link - check shared code for link and determine up/down
4261 * @adapter: pointer to driver private info
4262 **/
4263 bool igb_has_link(struct igb_adapter *adapter)
4264 {
4265 struct e1000_hw *hw = &adapter->hw;
4266 bool link_active = false;
4267
4268 /* get_link_status is set on LSC (link status) interrupt or
4269 * rx sequence error interrupt. get_link_status will stay
4270 * false until the e1000_check_for_link establishes link
4271 * for copper adapters ONLY
4272 */
4273 switch (hw->phy.media_type) {
4274 case e1000_media_type_copper:
4275 if (!hw->mac.get_link_status)
4276 return true;
4277 case e1000_media_type_internal_serdes:
4278 hw->mac.ops.check_for_link(hw);
4279 link_active = !hw->mac.get_link_status;
4280 break;
4281 default:
4282 case e1000_media_type_unknown:
4283 break;
4284 }
4285
4286 if (((hw->mac.type == e1000_i210) ||
4287 (hw->mac.type == e1000_i211)) &&
4288 (hw->phy.id == I210_I_PHY_ID)) {
4289 if (!netif_carrier_ok(adapter->netdev)) {
4290 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4291 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4292 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4293 adapter->link_check_timeout = jiffies;
4294 }
4295 }
4296
4297 return link_active;
4298 }
4299
4300 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4301 {
4302 bool ret = false;
4303 u32 ctrl_ext, thstat;
4304
4305 /* check for thermal sensor event on i350 copper only */
4306 if (hw->mac.type == e1000_i350) {
4307 thstat = rd32(E1000_THSTAT);
4308 ctrl_ext = rd32(E1000_CTRL_EXT);
4309
4310 if ((hw->phy.media_type == e1000_media_type_copper) &&
4311 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4312 ret = !!(thstat & event);
4313 }
4314
4315 return ret;
4316 }
4317
4318 /**
4319 * igb_check_lvmmc - check for malformed packets received
4320 * and indicated in LVMMC register
4321 * @adapter: pointer to adapter
4322 **/
4323 static void igb_check_lvmmc(struct igb_adapter *adapter)
4324 {
4325 struct e1000_hw *hw = &adapter->hw;
4326 u32 lvmmc;
4327
4328 lvmmc = rd32(E1000_LVMMC);
4329 if (lvmmc) {
4330 if (unlikely(net_ratelimit())) {
4331 netdev_warn(adapter->netdev,
4332 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4333 lvmmc);
4334 }
4335 }
4336 }
4337
4338 /**
4339 * igb_watchdog - Timer Call-back
4340 * @data: pointer to adapter cast into an unsigned long
4341 **/
4342 static void igb_watchdog(unsigned long data)
4343 {
4344 struct igb_adapter *adapter = (struct igb_adapter *)data;
4345 /* Do the rest outside of interrupt context */
4346 schedule_work(&adapter->watchdog_task);
4347 }
4348
4349 static void igb_watchdog_task(struct work_struct *work)
4350 {
4351 struct igb_adapter *adapter = container_of(work,
4352 struct igb_adapter,
4353 watchdog_task);
4354 struct e1000_hw *hw = &adapter->hw;
4355 struct e1000_phy_info *phy = &hw->phy;
4356 struct net_device *netdev = adapter->netdev;
4357 u32 link;
4358 int i;
4359 u32 connsw;
4360 u16 phy_data, retry_count = 20;
4361
4362 link = igb_has_link(adapter);
4363
4364 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4365 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4366 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4367 else
4368 link = false;
4369 }
4370
4371 /* Force link down if we have fiber to swap to */
4372 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4373 if (hw->phy.media_type == e1000_media_type_copper) {
4374 connsw = rd32(E1000_CONNSW);
4375 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4376 link = 0;
4377 }
4378 }
4379 if (link) {
4380 /* Perform a reset if the media type changed. */
4381 if (hw->dev_spec._82575.media_changed) {
4382 hw->dev_spec._82575.media_changed = false;
4383 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4384 igb_reset(adapter);
4385 }
4386 /* Cancel scheduled suspend requests. */
4387 pm_runtime_resume(netdev->dev.parent);
4388
4389 if (!netif_carrier_ok(netdev)) {
4390 u32 ctrl;
4391
4392 hw->mac.ops.get_speed_and_duplex(hw,
4393 &adapter->link_speed,
4394 &adapter->link_duplex);
4395
4396 ctrl = rd32(E1000_CTRL);
4397 /* Links status message must follow this format */
4398 netdev_info(netdev,
4399 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4400 netdev->name,
4401 adapter->link_speed,
4402 adapter->link_duplex == FULL_DUPLEX ?
4403 "Full" : "Half",
4404 (ctrl & E1000_CTRL_TFCE) &&
4405 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4406 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4407 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4408
4409 /* disable EEE if enabled */
4410 if ((adapter->flags & IGB_FLAG_EEE) &&
4411 (adapter->link_duplex == HALF_DUPLEX)) {
4412 dev_info(&adapter->pdev->dev,
4413 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4414 adapter->hw.dev_spec._82575.eee_disable = true;
4415 adapter->flags &= ~IGB_FLAG_EEE;
4416 }
4417
4418 /* check if SmartSpeed worked */
4419 igb_check_downshift(hw);
4420 if (phy->speed_downgraded)
4421 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4422
4423 /* check for thermal sensor event */
4424 if (igb_thermal_sensor_event(hw,
4425 E1000_THSTAT_LINK_THROTTLE))
4426 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4427
4428 /* adjust timeout factor according to speed/duplex */
4429 adapter->tx_timeout_factor = 1;
4430 switch (adapter->link_speed) {
4431 case SPEED_10:
4432 adapter->tx_timeout_factor = 14;
4433 break;
4434 case SPEED_100:
4435 /* maybe add some timeout factor ? */
4436 break;
4437 }
4438
4439 if (adapter->link_speed != SPEED_1000)
4440 goto no_wait;
4441
4442 /* wait for Remote receiver status OK */
4443 retry_read_status:
4444 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4445 &phy_data)) {
4446 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4447 retry_count) {
4448 msleep(100);
4449 retry_count--;
4450 goto retry_read_status;
4451 } else if (!retry_count) {
4452 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4453 }
4454 } else {
4455 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4456 }
4457 no_wait:
4458 netif_carrier_on(netdev);
4459
4460 igb_ping_all_vfs(adapter);
4461 igb_check_vf_rate_limit(adapter);
4462
4463 /* link state has changed, schedule phy info update */
4464 if (!test_bit(__IGB_DOWN, &adapter->state))
4465 mod_timer(&adapter->phy_info_timer,
4466 round_jiffies(jiffies + 2 * HZ));
4467 }
4468 } else {
4469 if (netif_carrier_ok(netdev)) {
4470 adapter->link_speed = 0;
4471 adapter->link_duplex = 0;
4472
4473 /* check for thermal sensor event */
4474 if (igb_thermal_sensor_event(hw,
4475 E1000_THSTAT_PWR_DOWN)) {
4476 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4477 }
4478
4479 /* Links status message must follow this format */
4480 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4481 netdev->name);
4482 netif_carrier_off(netdev);
4483
4484 igb_ping_all_vfs(adapter);
4485
4486 /* link state has changed, schedule phy info update */
4487 if (!test_bit(__IGB_DOWN, &adapter->state))
4488 mod_timer(&adapter->phy_info_timer,
4489 round_jiffies(jiffies + 2 * HZ));
4490
4491 /* link is down, time to check for alternate media */
4492 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4493 igb_check_swap_media(adapter);
4494 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4495 schedule_work(&adapter->reset_task);
4496 /* return immediately */
4497 return;
4498 }
4499 }
4500 pm_schedule_suspend(netdev->dev.parent,
4501 MSEC_PER_SEC * 5);
4502
4503 /* also check for alternate media here */
4504 } else if (!netif_carrier_ok(netdev) &&
4505 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4506 igb_check_swap_media(adapter);
4507 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4508 schedule_work(&adapter->reset_task);
4509 /* return immediately */
4510 return;
4511 }
4512 }
4513 }
4514
4515 spin_lock(&adapter->stats64_lock);
4516 igb_update_stats(adapter, &adapter->stats64);
4517 spin_unlock(&adapter->stats64_lock);
4518
4519 for (i = 0; i < adapter->num_tx_queues; i++) {
4520 struct igb_ring *tx_ring = adapter->tx_ring[i];
4521 if (!netif_carrier_ok(netdev)) {
4522 /* We've lost link, so the controller stops DMA,
4523 * but we've got queued Tx work that's never going
4524 * to get done, so reset controller to flush Tx.
4525 * (Do the reset outside of interrupt context).
4526 */
4527 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4528 adapter->tx_timeout_count++;
4529 schedule_work(&adapter->reset_task);
4530 /* return immediately since reset is imminent */
4531 return;
4532 }
4533 }
4534
4535 /* Force detection of hung controller every watchdog period */
4536 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4537 }
4538
4539 /* Cause software interrupt to ensure Rx ring is cleaned */
4540 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4541 u32 eics = 0;
4542
4543 for (i = 0; i < adapter->num_q_vectors; i++)
4544 eics |= adapter->q_vector[i]->eims_value;
4545 wr32(E1000_EICS, eics);
4546 } else {
4547 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4548 }
4549
4550 igb_spoof_check(adapter);
4551 igb_ptp_rx_hang(adapter);
4552
4553 /* Check LVMMC register on i350/i354 only */
4554 if ((adapter->hw.mac.type == e1000_i350) ||
4555 (adapter->hw.mac.type == e1000_i354))
4556 igb_check_lvmmc(adapter);
4557
4558 /* Reset the timer */
4559 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4560 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4561 mod_timer(&adapter->watchdog_timer,
4562 round_jiffies(jiffies + HZ));
4563 else
4564 mod_timer(&adapter->watchdog_timer,
4565 round_jiffies(jiffies + 2 * HZ));
4566 }
4567 }
4568
4569 enum latency_range {
4570 lowest_latency = 0,
4571 low_latency = 1,
4572 bulk_latency = 2,
4573 latency_invalid = 255
4574 };
4575
4576 /**
4577 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4578 * @q_vector: pointer to q_vector
4579 *
4580 * Stores a new ITR value based on strictly on packet size. This
4581 * algorithm is less sophisticated than that used in igb_update_itr,
4582 * due to the difficulty of synchronizing statistics across multiple
4583 * receive rings. The divisors and thresholds used by this function
4584 * were determined based on theoretical maximum wire speed and testing
4585 * data, in order to minimize response time while increasing bulk
4586 * throughput.
4587 * This functionality is controlled by ethtool's coalescing settings.
4588 * NOTE: This function is called only when operating in a multiqueue
4589 * receive environment.
4590 **/
4591 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4592 {
4593 int new_val = q_vector->itr_val;
4594 int avg_wire_size = 0;
4595 struct igb_adapter *adapter = q_vector->adapter;
4596 unsigned int packets;
4597
4598 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4599 * ints/sec - ITR timer value of 120 ticks.
4600 */
4601 if (adapter->link_speed != SPEED_1000) {
4602 new_val = IGB_4K_ITR;
4603 goto set_itr_val;
4604 }
4605
4606 packets = q_vector->rx.total_packets;
4607 if (packets)
4608 avg_wire_size = q_vector->rx.total_bytes / packets;
4609
4610 packets = q_vector->tx.total_packets;
4611 if (packets)
4612 avg_wire_size = max_t(u32, avg_wire_size,
4613 q_vector->tx.total_bytes / packets);
4614
4615 /* if avg_wire_size isn't set no work was done */
4616 if (!avg_wire_size)
4617 goto clear_counts;
4618
4619 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4620 avg_wire_size += 24;
4621
4622 /* Don't starve jumbo frames */
4623 avg_wire_size = min(avg_wire_size, 3000);
4624
4625 /* Give a little boost to mid-size frames */
4626 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4627 new_val = avg_wire_size / 3;
4628 else
4629 new_val = avg_wire_size / 2;
4630
4631 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4632 if (new_val < IGB_20K_ITR &&
4633 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4634 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4635 new_val = IGB_20K_ITR;
4636
4637 set_itr_val:
4638 if (new_val != q_vector->itr_val) {
4639 q_vector->itr_val = new_val;
4640 q_vector->set_itr = 1;
4641 }
4642 clear_counts:
4643 q_vector->rx.total_bytes = 0;
4644 q_vector->rx.total_packets = 0;
4645 q_vector->tx.total_bytes = 0;
4646 q_vector->tx.total_packets = 0;
4647 }
4648
4649 /**
4650 * igb_update_itr - update the dynamic ITR value based on statistics
4651 * @q_vector: pointer to q_vector
4652 * @ring_container: ring info to update the itr for
4653 *
4654 * Stores a new ITR value based on packets and byte
4655 * counts during the last interrupt. The advantage of per interrupt
4656 * computation is faster updates and more accurate ITR for the current
4657 * traffic pattern. Constants in this function were computed
4658 * based on theoretical maximum wire speed and thresholds were set based
4659 * on testing data as well as attempting to minimize response time
4660 * while increasing bulk throughput.
4661 * This functionality is controlled by ethtool's coalescing settings.
4662 * NOTE: These calculations are only valid when operating in a single-
4663 * queue environment.
4664 **/
4665 static void igb_update_itr(struct igb_q_vector *q_vector,
4666 struct igb_ring_container *ring_container)
4667 {
4668 unsigned int packets = ring_container->total_packets;
4669 unsigned int bytes = ring_container->total_bytes;
4670 u8 itrval = ring_container->itr;
4671
4672 /* no packets, exit with status unchanged */
4673 if (packets == 0)
4674 return;
4675
4676 switch (itrval) {
4677 case lowest_latency:
4678 /* handle TSO and jumbo frames */
4679 if (bytes/packets > 8000)
4680 itrval = bulk_latency;
4681 else if ((packets < 5) && (bytes > 512))
4682 itrval = low_latency;
4683 break;
4684 case low_latency: /* 50 usec aka 20000 ints/s */
4685 if (bytes > 10000) {
4686 /* this if handles the TSO accounting */
4687 if (bytes/packets > 8000)
4688 itrval = bulk_latency;
4689 else if ((packets < 10) || ((bytes/packets) > 1200))
4690 itrval = bulk_latency;
4691 else if ((packets > 35))
4692 itrval = lowest_latency;
4693 } else if (bytes/packets > 2000) {
4694 itrval = bulk_latency;
4695 } else if (packets <= 2 && bytes < 512) {
4696 itrval = lowest_latency;
4697 }
4698 break;
4699 case bulk_latency: /* 250 usec aka 4000 ints/s */
4700 if (bytes > 25000) {
4701 if (packets > 35)
4702 itrval = low_latency;
4703 } else if (bytes < 1500) {
4704 itrval = low_latency;
4705 }
4706 break;
4707 }
4708
4709 /* clear work counters since we have the values we need */
4710 ring_container->total_bytes = 0;
4711 ring_container->total_packets = 0;
4712
4713 /* write updated itr to ring container */
4714 ring_container->itr = itrval;
4715 }
4716
4717 static void igb_set_itr(struct igb_q_vector *q_vector)
4718 {
4719 struct igb_adapter *adapter = q_vector->adapter;
4720 u32 new_itr = q_vector->itr_val;
4721 u8 current_itr = 0;
4722
4723 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4724 if (adapter->link_speed != SPEED_1000) {
4725 current_itr = 0;
4726 new_itr = IGB_4K_ITR;
4727 goto set_itr_now;
4728 }
4729
4730 igb_update_itr(q_vector, &q_vector->tx);
4731 igb_update_itr(q_vector, &q_vector->rx);
4732
4733 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4734
4735 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4736 if (current_itr == lowest_latency &&
4737 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4738 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4739 current_itr = low_latency;
4740
4741 switch (current_itr) {
4742 /* counts and packets in update_itr are dependent on these numbers */
4743 case lowest_latency:
4744 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4745 break;
4746 case low_latency:
4747 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4748 break;
4749 case bulk_latency:
4750 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4751 break;
4752 default:
4753 break;
4754 }
4755
4756 set_itr_now:
4757 if (new_itr != q_vector->itr_val) {
4758 /* this attempts to bias the interrupt rate towards Bulk
4759 * by adding intermediate steps when interrupt rate is
4760 * increasing
4761 */
4762 new_itr = new_itr > q_vector->itr_val ?
4763 max((new_itr * q_vector->itr_val) /
4764 (new_itr + (q_vector->itr_val >> 2)),
4765 new_itr) : new_itr;
4766 /* Don't write the value here; it resets the adapter's
4767 * internal timer, and causes us to delay far longer than
4768 * we should between interrupts. Instead, we write the ITR
4769 * value at the beginning of the next interrupt so the timing
4770 * ends up being correct.
4771 */
4772 q_vector->itr_val = new_itr;
4773 q_vector->set_itr = 1;
4774 }
4775 }
4776
4777 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4778 u32 type_tucmd, u32 mss_l4len_idx)
4779 {
4780 struct e1000_adv_tx_context_desc *context_desc;
4781 u16 i = tx_ring->next_to_use;
4782
4783 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4784
4785 i++;
4786 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4787
4788 /* set bits to identify this as an advanced context descriptor */
4789 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4790
4791 /* For 82575, context index must be unique per ring. */
4792 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4793 mss_l4len_idx |= tx_ring->reg_idx << 4;
4794
4795 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4796 context_desc->seqnum_seed = 0;
4797 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4798 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4799 }
4800
4801 static int igb_tso(struct igb_ring *tx_ring,
4802 struct igb_tx_buffer *first,
4803 u8 *hdr_len)
4804 {
4805 struct sk_buff *skb = first->skb;
4806 u32 vlan_macip_lens, type_tucmd;
4807 u32 mss_l4len_idx, l4len;
4808 int err;
4809
4810 if (skb->ip_summed != CHECKSUM_PARTIAL)
4811 return 0;
4812
4813 if (!skb_is_gso(skb))
4814 return 0;
4815
4816 err = skb_cow_head(skb, 0);
4817 if (err < 0)
4818 return err;
4819
4820 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4821 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4822
4823 if (first->protocol == htons(ETH_P_IP)) {
4824 struct iphdr *iph = ip_hdr(skb);
4825 iph->tot_len = 0;
4826 iph->check = 0;
4827 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4828 iph->daddr, 0,
4829 IPPROTO_TCP,
4830 0);
4831 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4832 first->tx_flags |= IGB_TX_FLAGS_TSO |
4833 IGB_TX_FLAGS_CSUM |
4834 IGB_TX_FLAGS_IPV4;
4835 } else if (skb_is_gso_v6(skb)) {
4836 ipv6_hdr(skb)->payload_len = 0;
4837 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4838 &ipv6_hdr(skb)->daddr,
4839 0, IPPROTO_TCP, 0);
4840 first->tx_flags |= IGB_TX_FLAGS_TSO |
4841 IGB_TX_FLAGS_CSUM;
4842 }
4843
4844 /* compute header lengths */
4845 l4len = tcp_hdrlen(skb);
4846 *hdr_len = skb_transport_offset(skb) + l4len;
4847
4848 /* update gso size and bytecount with header size */
4849 first->gso_segs = skb_shinfo(skb)->gso_segs;
4850 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4851
4852 /* MSS L4LEN IDX */
4853 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4854 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4855
4856 /* VLAN MACLEN IPLEN */
4857 vlan_macip_lens = skb_network_header_len(skb);
4858 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4859 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4860
4861 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4862
4863 return 1;
4864 }
4865
4866 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4867 {
4868 struct sk_buff *skb = first->skb;
4869 u32 vlan_macip_lens = 0;
4870 u32 mss_l4len_idx = 0;
4871 u32 type_tucmd = 0;
4872
4873 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4874 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4875 return;
4876 } else {
4877 u8 l4_hdr = 0;
4878
4879 switch (first->protocol) {
4880 case htons(ETH_P_IP):
4881 vlan_macip_lens |= skb_network_header_len(skb);
4882 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4883 l4_hdr = ip_hdr(skb)->protocol;
4884 break;
4885 case htons(ETH_P_IPV6):
4886 vlan_macip_lens |= skb_network_header_len(skb);
4887 l4_hdr = ipv6_hdr(skb)->nexthdr;
4888 break;
4889 default:
4890 if (unlikely(net_ratelimit())) {
4891 dev_warn(tx_ring->dev,
4892 "partial checksum but proto=%x!\n",
4893 first->protocol);
4894 }
4895 break;
4896 }
4897
4898 switch (l4_hdr) {
4899 case IPPROTO_TCP:
4900 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4901 mss_l4len_idx = tcp_hdrlen(skb) <<
4902 E1000_ADVTXD_L4LEN_SHIFT;
4903 break;
4904 case IPPROTO_SCTP:
4905 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4906 mss_l4len_idx = sizeof(struct sctphdr) <<
4907 E1000_ADVTXD_L4LEN_SHIFT;
4908 break;
4909 case IPPROTO_UDP:
4910 mss_l4len_idx = sizeof(struct udphdr) <<
4911 E1000_ADVTXD_L4LEN_SHIFT;
4912 break;
4913 default:
4914 if (unlikely(net_ratelimit())) {
4915 dev_warn(tx_ring->dev,
4916 "partial checksum but l4 proto=%x!\n",
4917 l4_hdr);
4918 }
4919 break;
4920 }
4921
4922 /* update TX checksum flag */
4923 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4924 }
4925
4926 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4927 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4928
4929 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4930 }
4931
4932 #define IGB_SET_FLAG(_input, _flag, _result) \
4933 ((_flag <= _result) ? \
4934 ((u32)(_input & _flag) * (_result / _flag)) : \
4935 ((u32)(_input & _flag) / (_flag / _result)))
4936
4937 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4938 {
4939 /* set type for advanced descriptor with frame checksum insertion */
4940 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4941 E1000_ADVTXD_DCMD_DEXT |
4942 E1000_ADVTXD_DCMD_IFCS;
4943
4944 /* set HW vlan bit if vlan is present */
4945 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4946 (E1000_ADVTXD_DCMD_VLE));
4947
4948 /* set segmentation bits for TSO */
4949 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4950 (E1000_ADVTXD_DCMD_TSE));
4951
4952 /* set timestamp bit if present */
4953 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4954 (E1000_ADVTXD_MAC_TSTAMP));
4955
4956 /* insert frame checksum */
4957 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4958
4959 return cmd_type;
4960 }
4961
4962 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4963 union e1000_adv_tx_desc *tx_desc,
4964 u32 tx_flags, unsigned int paylen)
4965 {
4966 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4967
4968 /* 82575 requires a unique index per ring */
4969 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4970 olinfo_status |= tx_ring->reg_idx << 4;
4971
4972 /* insert L4 checksum */
4973 olinfo_status |= IGB_SET_FLAG(tx_flags,
4974 IGB_TX_FLAGS_CSUM,
4975 (E1000_TXD_POPTS_TXSM << 8));
4976
4977 /* insert IPv4 checksum */
4978 olinfo_status |= IGB_SET_FLAG(tx_flags,
4979 IGB_TX_FLAGS_IPV4,
4980 (E1000_TXD_POPTS_IXSM << 8));
4981
4982 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4983 }
4984
4985 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4986 {
4987 struct net_device *netdev = tx_ring->netdev;
4988
4989 netif_stop_subqueue(netdev, tx_ring->queue_index);
4990
4991 /* Herbert's original patch had:
4992 * smp_mb__after_netif_stop_queue();
4993 * but since that doesn't exist yet, just open code it.
4994 */
4995 smp_mb();
4996
4997 /* We need to check again in a case another CPU has just
4998 * made room available.
4999 */
5000 if (igb_desc_unused(tx_ring) < size)
5001 return -EBUSY;
5002
5003 /* A reprieve! */
5004 netif_wake_subqueue(netdev, tx_ring->queue_index);
5005
5006 u64_stats_update_begin(&tx_ring->tx_syncp2);
5007 tx_ring->tx_stats.restart_queue2++;
5008 u64_stats_update_end(&tx_ring->tx_syncp2);
5009
5010 return 0;
5011 }
5012
5013 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5014 {
5015 if (igb_desc_unused(tx_ring) >= size)
5016 return 0;
5017 return __igb_maybe_stop_tx(tx_ring, size);
5018 }
5019
5020 static void igb_tx_map(struct igb_ring *tx_ring,
5021 struct igb_tx_buffer *first,
5022 const u8 hdr_len)
5023 {
5024 struct sk_buff *skb = first->skb;
5025 struct igb_tx_buffer *tx_buffer;
5026 union e1000_adv_tx_desc *tx_desc;
5027 struct skb_frag_struct *frag;
5028 dma_addr_t dma;
5029 unsigned int data_len, size;
5030 u32 tx_flags = first->tx_flags;
5031 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
5032 u16 i = tx_ring->next_to_use;
5033
5034 tx_desc = IGB_TX_DESC(tx_ring, i);
5035
5036 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5037
5038 size = skb_headlen(skb);
5039 data_len = skb->data_len;
5040
5041 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5042
5043 tx_buffer = first;
5044
5045 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5046 if (dma_mapping_error(tx_ring->dev, dma))
5047 goto dma_error;
5048
5049 /* record length, and DMA address */
5050 dma_unmap_len_set(tx_buffer, len, size);
5051 dma_unmap_addr_set(tx_buffer, dma, dma);
5052
5053 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5054
5055 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5056 tx_desc->read.cmd_type_len =
5057 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
5058
5059 i++;
5060 tx_desc++;
5061 if (i == tx_ring->count) {
5062 tx_desc = IGB_TX_DESC(tx_ring, 0);
5063 i = 0;
5064 }
5065 tx_desc->read.olinfo_status = 0;
5066
5067 dma += IGB_MAX_DATA_PER_TXD;
5068 size -= IGB_MAX_DATA_PER_TXD;
5069
5070 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5071 }
5072
5073 if (likely(!data_len))
5074 break;
5075
5076 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
5077
5078 i++;
5079 tx_desc++;
5080 if (i == tx_ring->count) {
5081 tx_desc = IGB_TX_DESC(tx_ring, 0);
5082 i = 0;
5083 }
5084 tx_desc->read.olinfo_status = 0;
5085
5086 size = skb_frag_size(frag);
5087 data_len -= size;
5088
5089 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
5090 size, DMA_TO_DEVICE);
5091
5092 tx_buffer = &tx_ring->tx_buffer_info[i];
5093 }
5094
5095 /* write last descriptor with RS and EOP bits */
5096 cmd_type |= size | IGB_TXD_DCMD;
5097 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
5098
5099 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5100
5101 /* set the timestamp */
5102 first->time_stamp = jiffies;
5103
5104 /* Force memory writes to complete before letting h/w know there
5105 * are new descriptors to fetch. (Only applicable for weak-ordered
5106 * memory model archs, such as IA-64).
5107 *
5108 * We also need this memory barrier to make certain all of the
5109 * status bits have been updated before next_to_watch is written.
5110 */
5111 wmb();
5112
5113 /* set next_to_watch value indicating a packet is present */
5114 first->next_to_watch = tx_desc;
5115
5116 i++;
5117 if (i == tx_ring->count)
5118 i = 0;
5119
5120 tx_ring->next_to_use = i;
5121
5122 /* Make sure there is space in the ring for the next send. */
5123 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5124
5125 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
5126 writel(i, tx_ring->tail);
5127
5128 /* we need this if more than one processor can write to our tail
5129 * at a time, it synchronizes IO on IA64/Altix systems
5130 */
5131 mmiowb();
5132 }
5133 return;
5134
5135 dma_error:
5136 dev_err(tx_ring->dev, "TX DMA map failed\n");
5137
5138 /* clear dma mappings for failed tx_buffer_info map */
5139 for (;;) {
5140 tx_buffer = &tx_ring->tx_buffer_info[i];
5141 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5142 if (tx_buffer == first)
5143 break;
5144 if (i == 0)
5145 i = tx_ring->count;
5146 i--;
5147 }
5148
5149 tx_ring->next_to_use = i;
5150 }
5151
5152 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5153 struct igb_ring *tx_ring)
5154 {
5155 struct igb_tx_buffer *first;
5156 int tso;
5157 u32 tx_flags = 0;
5158 unsigned short f;
5159 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5160 __be16 protocol = vlan_get_protocol(skb);
5161 u8 hdr_len = 0;
5162
5163 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5164 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5165 * + 2 desc gap to keep tail from touching head,
5166 * + 1 desc for context descriptor,
5167 * otherwise try next time
5168 */
5169 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5170 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5171
5172 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5173 /* this is a hard error */
5174 return NETDEV_TX_BUSY;
5175 }
5176
5177 /* record the location of the first descriptor for this packet */
5178 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5179 first->skb = skb;
5180 first->bytecount = skb->len;
5181 first->gso_segs = 1;
5182
5183 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5184 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5185
5186 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5187 &adapter->state)) {
5188 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5189 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5190
5191 adapter->ptp_tx_skb = skb_get(skb);
5192 adapter->ptp_tx_start = jiffies;
5193 if (adapter->hw.mac.type == e1000_82576)
5194 schedule_work(&adapter->ptp_tx_work);
5195 }
5196 }
5197
5198 skb_tx_timestamp(skb);
5199
5200 if (skb_vlan_tag_present(skb)) {
5201 tx_flags |= IGB_TX_FLAGS_VLAN;
5202 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5203 }
5204
5205 /* record initial flags and protocol */
5206 first->tx_flags = tx_flags;
5207 first->protocol = protocol;
5208
5209 tso = igb_tso(tx_ring, first, &hdr_len);
5210 if (tso < 0)
5211 goto out_drop;
5212 else if (!tso)
5213 igb_tx_csum(tx_ring, first);
5214
5215 igb_tx_map(tx_ring, first, hdr_len);
5216
5217 return NETDEV_TX_OK;
5218
5219 out_drop:
5220 igb_unmap_and_free_tx_resource(tx_ring, first);
5221
5222 return NETDEV_TX_OK;
5223 }
5224
5225 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5226 struct sk_buff *skb)
5227 {
5228 unsigned int r_idx = skb->queue_mapping;
5229
5230 if (r_idx >= adapter->num_tx_queues)
5231 r_idx = r_idx % adapter->num_tx_queues;
5232
5233 return adapter->tx_ring[r_idx];
5234 }
5235
5236 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5237 struct net_device *netdev)
5238 {
5239 struct igb_adapter *adapter = netdev_priv(netdev);
5240
5241 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5242 * in order to meet this minimum size requirement.
5243 */
5244 if (skb_put_padto(skb, 17))
5245 return NETDEV_TX_OK;
5246
5247 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5248 }
5249
5250 /**
5251 * igb_tx_timeout - Respond to a Tx Hang
5252 * @netdev: network interface device structure
5253 **/
5254 static void igb_tx_timeout(struct net_device *netdev)
5255 {
5256 struct igb_adapter *adapter = netdev_priv(netdev);
5257 struct e1000_hw *hw = &adapter->hw;
5258
5259 /* Do the reset outside of interrupt context */
5260 adapter->tx_timeout_count++;
5261
5262 if (hw->mac.type >= e1000_82580)
5263 hw->dev_spec._82575.global_device_reset = true;
5264
5265 schedule_work(&adapter->reset_task);
5266 wr32(E1000_EICS,
5267 (adapter->eims_enable_mask & ~adapter->eims_other));
5268 }
5269
5270 static void igb_reset_task(struct work_struct *work)
5271 {
5272 struct igb_adapter *adapter;
5273 adapter = container_of(work, struct igb_adapter, reset_task);
5274
5275 igb_dump(adapter);
5276 netdev_err(adapter->netdev, "Reset adapter\n");
5277 igb_reinit_locked(adapter);
5278 }
5279
5280 /**
5281 * igb_get_stats64 - Get System Network Statistics
5282 * @netdev: network interface device structure
5283 * @stats: rtnl_link_stats64 pointer
5284 **/
5285 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5286 struct rtnl_link_stats64 *stats)
5287 {
5288 struct igb_adapter *adapter = netdev_priv(netdev);
5289
5290 spin_lock(&adapter->stats64_lock);
5291 igb_update_stats(adapter, &adapter->stats64);
5292 memcpy(stats, &adapter->stats64, sizeof(*stats));
5293 spin_unlock(&adapter->stats64_lock);
5294
5295 return stats;
5296 }
5297
5298 /**
5299 * igb_change_mtu - Change the Maximum Transfer Unit
5300 * @netdev: network interface device structure
5301 * @new_mtu: new value for maximum frame size
5302 *
5303 * Returns 0 on success, negative on failure
5304 **/
5305 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5306 {
5307 struct igb_adapter *adapter = netdev_priv(netdev);
5308 struct pci_dev *pdev = adapter->pdev;
5309 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5310
5311 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5312 dev_err(&pdev->dev, "Invalid MTU setting\n");
5313 return -EINVAL;
5314 }
5315
5316 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5317 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5318 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5319 return -EINVAL;
5320 }
5321
5322 /* adjust max frame to be at least the size of a standard frame */
5323 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5324 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5325
5326 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5327 usleep_range(1000, 2000);
5328
5329 /* igb_down has a dependency on max_frame_size */
5330 adapter->max_frame_size = max_frame;
5331
5332 if (netif_running(netdev))
5333 igb_down(adapter);
5334
5335 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5336 netdev->mtu, new_mtu);
5337 netdev->mtu = new_mtu;
5338
5339 if (netif_running(netdev))
5340 igb_up(adapter);
5341 else
5342 igb_reset(adapter);
5343
5344 clear_bit(__IGB_RESETTING, &adapter->state);
5345
5346 return 0;
5347 }
5348
5349 /**
5350 * igb_update_stats - Update the board statistics counters
5351 * @adapter: board private structure
5352 **/
5353 void igb_update_stats(struct igb_adapter *adapter,
5354 struct rtnl_link_stats64 *net_stats)
5355 {
5356 struct e1000_hw *hw = &adapter->hw;
5357 struct pci_dev *pdev = adapter->pdev;
5358 u32 reg, mpc;
5359 int i;
5360 u64 bytes, packets;
5361 unsigned int start;
5362 u64 _bytes, _packets;
5363
5364 /* Prevent stats update while adapter is being reset, or if the pci
5365 * connection is down.
5366 */
5367 if (adapter->link_speed == 0)
5368 return;
5369 if (pci_channel_offline(pdev))
5370 return;
5371
5372 bytes = 0;
5373 packets = 0;
5374
5375 rcu_read_lock();
5376 for (i = 0; i < adapter->num_rx_queues; i++) {
5377 struct igb_ring *ring = adapter->rx_ring[i];
5378 u32 rqdpc = rd32(E1000_RQDPC(i));
5379 if (hw->mac.type >= e1000_i210)
5380 wr32(E1000_RQDPC(i), 0);
5381
5382 if (rqdpc) {
5383 ring->rx_stats.drops += rqdpc;
5384 net_stats->rx_fifo_errors += rqdpc;
5385 }
5386
5387 do {
5388 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5389 _bytes = ring->rx_stats.bytes;
5390 _packets = ring->rx_stats.packets;
5391 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5392 bytes += _bytes;
5393 packets += _packets;
5394 }
5395
5396 net_stats->rx_bytes = bytes;
5397 net_stats->rx_packets = packets;
5398
5399 bytes = 0;
5400 packets = 0;
5401 for (i = 0; i < adapter->num_tx_queues; i++) {
5402 struct igb_ring *ring = adapter->tx_ring[i];
5403 do {
5404 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5405 _bytes = ring->tx_stats.bytes;
5406 _packets = ring->tx_stats.packets;
5407 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5408 bytes += _bytes;
5409 packets += _packets;
5410 }
5411 net_stats->tx_bytes = bytes;
5412 net_stats->tx_packets = packets;
5413 rcu_read_unlock();
5414
5415 /* read stats registers */
5416 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5417 adapter->stats.gprc += rd32(E1000_GPRC);
5418 adapter->stats.gorc += rd32(E1000_GORCL);
5419 rd32(E1000_GORCH); /* clear GORCL */
5420 adapter->stats.bprc += rd32(E1000_BPRC);
5421 adapter->stats.mprc += rd32(E1000_MPRC);
5422 adapter->stats.roc += rd32(E1000_ROC);
5423
5424 adapter->stats.prc64 += rd32(E1000_PRC64);
5425 adapter->stats.prc127 += rd32(E1000_PRC127);
5426 adapter->stats.prc255 += rd32(E1000_PRC255);
5427 adapter->stats.prc511 += rd32(E1000_PRC511);
5428 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5429 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5430 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5431 adapter->stats.sec += rd32(E1000_SEC);
5432
5433 mpc = rd32(E1000_MPC);
5434 adapter->stats.mpc += mpc;
5435 net_stats->rx_fifo_errors += mpc;
5436 adapter->stats.scc += rd32(E1000_SCC);
5437 adapter->stats.ecol += rd32(E1000_ECOL);
5438 adapter->stats.mcc += rd32(E1000_MCC);
5439 adapter->stats.latecol += rd32(E1000_LATECOL);
5440 adapter->stats.dc += rd32(E1000_DC);
5441 adapter->stats.rlec += rd32(E1000_RLEC);
5442 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5443 adapter->stats.xontxc += rd32(E1000_XONTXC);
5444 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5445 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5446 adapter->stats.fcruc += rd32(E1000_FCRUC);
5447 adapter->stats.gptc += rd32(E1000_GPTC);
5448 adapter->stats.gotc += rd32(E1000_GOTCL);
5449 rd32(E1000_GOTCH); /* clear GOTCL */
5450 adapter->stats.rnbc += rd32(E1000_RNBC);
5451 adapter->stats.ruc += rd32(E1000_RUC);
5452 adapter->stats.rfc += rd32(E1000_RFC);
5453 adapter->stats.rjc += rd32(E1000_RJC);
5454 adapter->stats.tor += rd32(E1000_TORH);
5455 adapter->stats.tot += rd32(E1000_TOTH);
5456 adapter->stats.tpr += rd32(E1000_TPR);
5457
5458 adapter->stats.ptc64 += rd32(E1000_PTC64);
5459 adapter->stats.ptc127 += rd32(E1000_PTC127);
5460 adapter->stats.ptc255 += rd32(E1000_PTC255);
5461 adapter->stats.ptc511 += rd32(E1000_PTC511);
5462 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5463 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5464
5465 adapter->stats.mptc += rd32(E1000_MPTC);
5466 adapter->stats.bptc += rd32(E1000_BPTC);
5467
5468 adapter->stats.tpt += rd32(E1000_TPT);
5469 adapter->stats.colc += rd32(E1000_COLC);
5470
5471 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5472 /* read internal phy specific stats */
5473 reg = rd32(E1000_CTRL_EXT);
5474 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5475 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5476
5477 /* this stat has invalid values on i210/i211 */
5478 if ((hw->mac.type != e1000_i210) &&
5479 (hw->mac.type != e1000_i211))
5480 adapter->stats.tncrs += rd32(E1000_TNCRS);
5481 }
5482
5483 adapter->stats.tsctc += rd32(E1000_TSCTC);
5484 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5485
5486 adapter->stats.iac += rd32(E1000_IAC);
5487 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5488 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5489 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5490 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5491 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5492 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5493 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5494 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5495
5496 /* Fill out the OS statistics structure */
5497 net_stats->multicast = adapter->stats.mprc;
5498 net_stats->collisions = adapter->stats.colc;
5499
5500 /* Rx Errors */
5501
5502 /* RLEC on some newer hardware can be incorrect so build
5503 * our own version based on RUC and ROC
5504 */
5505 net_stats->rx_errors = adapter->stats.rxerrc +
5506 adapter->stats.crcerrs + adapter->stats.algnerrc +
5507 adapter->stats.ruc + adapter->stats.roc +
5508 adapter->stats.cexterr;
5509 net_stats->rx_length_errors = adapter->stats.ruc +
5510 adapter->stats.roc;
5511 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5512 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5513 net_stats->rx_missed_errors = adapter->stats.mpc;
5514
5515 /* Tx Errors */
5516 net_stats->tx_errors = adapter->stats.ecol +
5517 adapter->stats.latecol;
5518 net_stats->tx_aborted_errors = adapter->stats.ecol;
5519 net_stats->tx_window_errors = adapter->stats.latecol;
5520 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5521
5522 /* Tx Dropped needs to be maintained elsewhere */
5523
5524 /* Management Stats */
5525 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5526 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5527 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5528
5529 /* OS2BMC Stats */
5530 reg = rd32(E1000_MANC);
5531 if (reg & E1000_MANC_EN_BMC2OS) {
5532 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5533 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5534 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5535 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5536 }
5537 }
5538
5539 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5540 {
5541 struct e1000_hw *hw = &adapter->hw;
5542 struct ptp_clock_event event;
5543 struct timespec64 ts;
5544 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5545
5546 if (tsicr & TSINTR_SYS_WRAP) {
5547 event.type = PTP_CLOCK_PPS;
5548 if (adapter->ptp_caps.pps)
5549 ptp_clock_event(adapter->ptp_clock, &event);
5550 else
5551 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5552 ack |= TSINTR_SYS_WRAP;
5553 }
5554
5555 if (tsicr & E1000_TSICR_TXTS) {
5556 /* retrieve hardware timestamp */
5557 schedule_work(&adapter->ptp_tx_work);
5558 ack |= E1000_TSICR_TXTS;
5559 }
5560
5561 if (tsicr & TSINTR_TT0) {
5562 spin_lock(&adapter->tmreg_lock);
5563 ts = timespec64_add(adapter->perout[0].start,
5564 adapter->perout[0].period);
5565 /* u32 conversion of tv_sec is safe until y2106 */
5566 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5567 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
5568 tsauxc = rd32(E1000_TSAUXC);
5569 tsauxc |= TSAUXC_EN_TT0;
5570 wr32(E1000_TSAUXC, tsauxc);
5571 adapter->perout[0].start = ts;
5572 spin_unlock(&adapter->tmreg_lock);
5573 ack |= TSINTR_TT0;
5574 }
5575
5576 if (tsicr & TSINTR_TT1) {
5577 spin_lock(&adapter->tmreg_lock);
5578 ts = timespec64_add(adapter->perout[1].start,
5579 adapter->perout[1].period);
5580 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5581 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
5582 tsauxc = rd32(E1000_TSAUXC);
5583 tsauxc |= TSAUXC_EN_TT1;
5584 wr32(E1000_TSAUXC, tsauxc);
5585 adapter->perout[1].start = ts;
5586 spin_unlock(&adapter->tmreg_lock);
5587 ack |= TSINTR_TT1;
5588 }
5589
5590 if (tsicr & TSINTR_AUTT0) {
5591 nsec = rd32(E1000_AUXSTMPL0);
5592 sec = rd32(E1000_AUXSTMPH0);
5593 event.type = PTP_CLOCK_EXTTS;
5594 event.index = 0;
5595 event.timestamp = sec * 1000000000ULL + nsec;
5596 ptp_clock_event(adapter->ptp_clock, &event);
5597 ack |= TSINTR_AUTT0;
5598 }
5599
5600 if (tsicr & TSINTR_AUTT1) {
5601 nsec = rd32(E1000_AUXSTMPL1);
5602 sec = rd32(E1000_AUXSTMPH1);
5603 event.type = PTP_CLOCK_EXTTS;
5604 event.index = 1;
5605 event.timestamp = sec * 1000000000ULL + nsec;
5606 ptp_clock_event(adapter->ptp_clock, &event);
5607 ack |= TSINTR_AUTT1;
5608 }
5609
5610 /* acknowledge the interrupts */
5611 wr32(E1000_TSICR, ack);
5612 }
5613
5614 static irqreturn_t igb_msix_other(int irq, void *data)
5615 {
5616 struct igb_adapter *adapter = data;
5617 struct e1000_hw *hw = &adapter->hw;
5618 u32 icr = rd32(E1000_ICR);
5619 /* reading ICR causes bit 31 of EICR to be cleared */
5620
5621 if (icr & E1000_ICR_DRSTA)
5622 schedule_work(&adapter->reset_task);
5623
5624 if (icr & E1000_ICR_DOUTSYNC) {
5625 /* HW is reporting DMA is out of sync */
5626 adapter->stats.doosync++;
5627 /* The DMA Out of Sync is also indication of a spoof event
5628 * in IOV mode. Check the Wrong VM Behavior register to
5629 * see if it is really a spoof event.
5630 */
5631 igb_check_wvbr(adapter);
5632 }
5633
5634 /* Check for a mailbox event */
5635 if (icr & E1000_ICR_VMMB)
5636 igb_msg_task(adapter);
5637
5638 if (icr & E1000_ICR_LSC) {
5639 hw->mac.get_link_status = 1;
5640 /* guard against interrupt when we're going down */
5641 if (!test_bit(__IGB_DOWN, &adapter->state))
5642 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5643 }
5644
5645 if (icr & E1000_ICR_TS)
5646 igb_tsync_interrupt(adapter);
5647
5648 wr32(E1000_EIMS, adapter->eims_other);
5649
5650 return IRQ_HANDLED;
5651 }
5652
5653 static void igb_write_itr(struct igb_q_vector *q_vector)
5654 {
5655 struct igb_adapter *adapter = q_vector->adapter;
5656 u32 itr_val = q_vector->itr_val & 0x7FFC;
5657
5658 if (!q_vector->set_itr)
5659 return;
5660
5661 if (!itr_val)
5662 itr_val = 0x4;
5663
5664 if (adapter->hw.mac.type == e1000_82575)
5665 itr_val |= itr_val << 16;
5666 else
5667 itr_val |= E1000_EITR_CNT_IGNR;
5668
5669 writel(itr_val, q_vector->itr_register);
5670 q_vector->set_itr = 0;
5671 }
5672
5673 static irqreturn_t igb_msix_ring(int irq, void *data)
5674 {
5675 struct igb_q_vector *q_vector = data;
5676
5677 /* Write the ITR value calculated from the previous interrupt. */
5678 igb_write_itr(q_vector);
5679
5680 napi_schedule(&q_vector->napi);
5681
5682 return IRQ_HANDLED;
5683 }
5684
5685 #ifdef CONFIG_IGB_DCA
5686 static void igb_update_tx_dca(struct igb_adapter *adapter,
5687 struct igb_ring *tx_ring,
5688 int cpu)
5689 {
5690 struct e1000_hw *hw = &adapter->hw;
5691 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5692
5693 if (hw->mac.type != e1000_82575)
5694 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5695
5696 /* We can enable relaxed ordering for reads, but not writes when
5697 * DCA is enabled. This is due to a known issue in some chipsets
5698 * which will cause the DCA tag to be cleared.
5699 */
5700 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5701 E1000_DCA_TXCTRL_DATA_RRO_EN |
5702 E1000_DCA_TXCTRL_DESC_DCA_EN;
5703
5704 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5705 }
5706
5707 static void igb_update_rx_dca(struct igb_adapter *adapter,
5708 struct igb_ring *rx_ring,
5709 int cpu)
5710 {
5711 struct e1000_hw *hw = &adapter->hw;
5712 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5713
5714 if (hw->mac.type != e1000_82575)
5715 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5716
5717 /* We can enable relaxed ordering for reads, but not writes when
5718 * DCA is enabled. This is due to a known issue in some chipsets
5719 * which will cause the DCA tag to be cleared.
5720 */
5721 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5722 E1000_DCA_RXCTRL_DESC_DCA_EN;
5723
5724 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5725 }
5726
5727 static void igb_update_dca(struct igb_q_vector *q_vector)
5728 {
5729 struct igb_adapter *adapter = q_vector->adapter;
5730 int cpu = get_cpu();
5731
5732 if (q_vector->cpu == cpu)
5733 goto out_no_update;
5734
5735 if (q_vector->tx.ring)
5736 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5737
5738 if (q_vector->rx.ring)
5739 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5740
5741 q_vector->cpu = cpu;
5742 out_no_update:
5743 put_cpu();
5744 }
5745
5746 static void igb_setup_dca(struct igb_adapter *adapter)
5747 {
5748 struct e1000_hw *hw = &adapter->hw;
5749 int i;
5750
5751 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5752 return;
5753
5754 /* Always use CB2 mode, difference is masked in the CB driver. */
5755 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5756
5757 for (i = 0; i < adapter->num_q_vectors; i++) {
5758 adapter->q_vector[i]->cpu = -1;
5759 igb_update_dca(adapter->q_vector[i]);
5760 }
5761 }
5762
5763 static int __igb_notify_dca(struct device *dev, void *data)
5764 {
5765 struct net_device *netdev = dev_get_drvdata(dev);
5766 struct igb_adapter *adapter = netdev_priv(netdev);
5767 struct pci_dev *pdev = adapter->pdev;
5768 struct e1000_hw *hw = &adapter->hw;
5769 unsigned long event = *(unsigned long *)data;
5770
5771 switch (event) {
5772 case DCA_PROVIDER_ADD:
5773 /* if already enabled, don't do it again */
5774 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5775 break;
5776 if (dca_add_requester(dev) == 0) {
5777 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5778 dev_info(&pdev->dev, "DCA enabled\n");
5779 igb_setup_dca(adapter);
5780 break;
5781 }
5782 /* Fall Through since DCA is disabled. */
5783 case DCA_PROVIDER_REMOVE:
5784 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5785 /* without this a class_device is left
5786 * hanging around in the sysfs model
5787 */
5788 dca_remove_requester(dev);
5789 dev_info(&pdev->dev, "DCA disabled\n");
5790 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5791 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5792 }
5793 break;
5794 }
5795
5796 return 0;
5797 }
5798
5799 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5800 void *p)
5801 {
5802 int ret_val;
5803
5804 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5805 __igb_notify_dca);
5806
5807 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5808 }
5809 #endif /* CONFIG_IGB_DCA */
5810
5811 #ifdef CONFIG_PCI_IOV
5812 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5813 {
5814 unsigned char mac_addr[ETH_ALEN];
5815
5816 eth_zero_addr(mac_addr);
5817 igb_set_vf_mac(adapter, vf, mac_addr);
5818
5819 /* By default spoof check is enabled for all VFs */
5820 adapter->vf_data[vf].spoofchk_enabled = true;
5821
5822 return 0;
5823 }
5824
5825 #endif
5826 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5827 {
5828 struct e1000_hw *hw = &adapter->hw;
5829 u32 ping;
5830 int i;
5831
5832 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5833 ping = E1000_PF_CONTROL_MSG;
5834 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5835 ping |= E1000_VT_MSGTYPE_CTS;
5836 igb_write_mbx(hw, &ping, 1, i);
5837 }
5838 }
5839
5840 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5841 {
5842 struct e1000_hw *hw = &adapter->hw;
5843 u32 vmolr = rd32(E1000_VMOLR(vf));
5844 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5845
5846 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5847 IGB_VF_FLAG_MULTI_PROMISC);
5848 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5849
5850 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5851 vmolr |= E1000_VMOLR_MPME;
5852 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5853 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5854 } else {
5855 /* if we have hashes and we are clearing a multicast promisc
5856 * flag we need to write the hashes to the MTA as this step
5857 * was previously skipped
5858 */
5859 if (vf_data->num_vf_mc_hashes > 30) {
5860 vmolr |= E1000_VMOLR_MPME;
5861 } else if (vf_data->num_vf_mc_hashes) {
5862 int j;
5863
5864 vmolr |= E1000_VMOLR_ROMPE;
5865 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5866 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5867 }
5868 }
5869
5870 wr32(E1000_VMOLR(vf), vmolr);
5871
5872 /* there are flags left unprocessed, likely not supported */
5873 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5874 return -EINVAL;
5875
5876 return 0;
5877 }
5878
5879 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5880 u32 *msgbuf, u32 vf)
5881 {
5882 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5883 u16 *hash_list = (u16 *)&msgbuf[1];
5884 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5885 int i;
5886
5887 /* salt away the number of multicast addresses assigned
5888 * to this VF for later use to restore when the PF multi cast
5889 * list changes
5890 */
5891 vf_data->num_vf_mc_hashes = n;
5892
5893 /* only up to 30 hash values supported */
5894 if (n > 30)
5895 n = 30;
5896
5897 /* store the hashes for later use */
5898 for (i = 0; i < n; i++)
5899 vf_data->vf_mc_hashes[i] = hash_list[i];
5900
5901 /* Flush and reset the mta with the new values */
5902 igb_set_rx_mode(adapter->netdev);
5903
5904 return 0;
5905 }
5906
5907 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5908 {
5909 struct e1000_hw *hw = &adapter->hw;
5910 struct vf_data_storage *vf_data;
5911 int i, j;
5912
5913 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5914 u32 vmolr = rd32(E1000_VMOLR(i));
5915
5916 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5917
5918 vf_data = &adapter->vf_data[i];
5919
5920 if ((vf_data->num_vf_mc_hashes > 30) ||
5921 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5922 vmolr |= E1000_VMOLR_MPME;
5923 } else if (vf_data->num_vf_mc_hashes) {
5924 vmolr |= E1000_VMOLR_ROMPE;
5925 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5926 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5927 }
5928 wr32(E1000_VMOLR(i), vmolr);
5929 }
5930 }
5931
5932 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5933 {
5934 struct e1000_hw *hw = &adapter->hw;
5935 u32 pool_mask, vlvf_mask, i;
5936
5937 /* create mask for VF and other pools */
5938 pool_mask = E1000_VLVF_POOLSEL_MASK;
5939 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5940
5941 /* drop PF from pool bits */
5942 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT +
5943 adapter->vfs_allocated_count));
5944
5945 /* Find the vlan filter for this id */
5946 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
5947 u32 vlvf = rd32(E1000_VLVF(i));
5948 u32 vfta_mask, vid, vfta;
5949
5950 /* remove the vf from the pool */
5951 if (!(vlvf & vlvf_mask))
5952 continue;
5953
5954 /* clear out bit from VLVF */
5955 vlvf ^= vlvf_mask;
5956
5957 /* if other pools are present, just remove ourselves */
5958 if (vlvf & pool_mask)
5959 goto update_vlvfb;
5960
5961 /* if PF is present, leave VFTA */
5962 if (vlvf & E1000_VLVF_POOLSEL_MASK)
5963 goto update_vlvf;
5964
5965 vid = vlvf & E1000_VLVF_VLANID_MASK;
5966 vfta_mask = 1 << (vid % 32);
5967
5968 /* clear bit from VFTA */
5969 vfta = adapter->shadow_vfta[vid / 32];
5970 if (vfta & vfta_mask)
5971 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
5972 update_vlvf:
5973 /* clear pool selection enable */
5974 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5975 vlvf &= E1000_VLVF_POOLSEL_MASK;
5976 else
5977 vlvf = 0;
5978 update_vlvfb:
5979 /* clear pool bits */
5980 wr32(E1000_VLVF(i), vlvf);
5981 }
5982 }
5983
5984 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
5985 {
5986 u32 vlvf;
5987 int idx;
5988
5989 /* short cut the special case */
5990 if (vlan == 0)
5991 return 0;
5992
5993 /* Search for the VLAN id in the VLVF entries */
5994 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
5995 vlvf = rd32(E1000_VLVF(idx));
5996 if ((vlvf & VLAN_VID_MASK) == vlan)
5997 break;
5998 }
5999
6000 return idx;
6001 }
6002
6003 void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6004 {
6005 struct e1000_hw *hw = &adapter->hw;
6006 u32 bits, pf_id;
6007 int idx;
6008
6009 idx = igb_find_vlvf_entry(hw, vid);
6010 if (!idx)
6011 return;
6012
6013 /* See if any other pools are set for this VLAN filter
6014 * entry other than the PF.
6015 */
6016 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6017 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK;
6018 bits &= rd32(E1000_VLVF(idx));
6019
6020 /* Disable the filter so this falls into the default pool. */
6021 if (!bits) {
6022 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6023 wr32(E1000_VLVF(idx), 1 << pf_id);
6024 else
6025 wr32(E1000_VLVF(idx), 0);
6026 }
6027 }
6028
6029 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6030 bool add, u32 vf)
6031 {
6032 int pf_id = adapter->vfs_allocated_count;
6033 struct e1000_hw *hw = &adapter->hw;
6034 int err;
6035
6036 /* If VLAN overlaps with one the PF is currently monitoring make
6037 * sure that we are able to allocate a VLVF entry. This may be
6038 * redundant but it guarantees PF will maintain visibility to
6039 * the VLAN.
6040 */
6041 if (add && test_bit(vid, adapter->active_vlans)) {
6042 err = igb_vfta_set(hw, vid, pf_id, true, false);
6043 if (err)
6044 return err;
6045 }
6046
6047 err = igb_vfta_set(hw, vid, vf, add, false);
6048
6049 if (add && !err)
6050 return err;
6051
6052 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6053 * we may need to drop the PF pool bit in order to allow us to free
6054 * up the VLVF resources.
6055 */
6056 if (test_bit(vid, adapter->active_vlans) ||
6057 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6058 igb_update_pf_vlvf(adapter, vid);
6059
6060 return err;
6061 }
6062
6063 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6064 {
6065 struct e1000_hw *hw = &adapter->hw;
6066
6067 if (vid)
6068 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6069 else
6070 wr32(E1000_VMVIR(vf), 0);
6071 }
6072
6073 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6074 u16 vlan, u8 qos)
6075 {
6076 int err;
6077
6078 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6079 if (err)
6080 return err;
6081
6082 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6083 igb_set_vmolr(adapter, vf, !vlan);
6084
6085 /* revoke access to previous VLAN */
6086 if (vlan != adapter->vf_data[vf].pf_vlan)
6087 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6088 false, vf);
6089
6090 adapter->vf_data[vf].pf_vlan = vlan;
6091 adapter->vf_data[vf].pf_qos = qos;
6092 dev_info(&adapter->pdev->dev,
6093 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6094 if (test_bit(__IGB_DOWN, &adapter->state)) {
6095 dev_warn(&adapter->pdev->dev,
6096 "The VF VLAN has been set, but the PF device is not up.\n");
6097 dev_warn(&adapter->pdev->dev,
6098 "Bring the PF device up before attempting to use the VF device.\n");
6099 }
6100
6101 return err;
6102 }
6103
6104 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6105 {
6106 /* Restore tagless access via VLAN 0 */
6107 igb_set_vf_vlan(adapter, 0, true, vf);
6108
6109 igb_set_vmvir(adapter, 0, vf);
6110 igb_set_vmolr(adapter, vf, true);
6111
6112 /* Remove any PF assigned VLAN */
6113 if (adapter->vf_data[vf].pf_vlan)
6114 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6115 false, vf);
6116
6117 adapter->vf_data[vf].pf_vlan = 0;
6118 adapter->vf_data[vf].pf_qos = 0;
6119
6120 return 0;
6121 }
6122
6123 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6124 int vf, u16 vlan, u8 qos)
6125 {
6126 struct igb_adapter *adapter = netdev_priv(netdev);
6127
6128 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6129 return -EINVAL;
6130
6131 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6132 igb_disable_port_vlan(adapter, vf);
6133 }
6134
6135 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6136 {
6137 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6138 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6139
6140 if (adapter->vf_data[vf].pf_vlan)
6141 return -1;
6142
6143 /* VLAN 0 is a special case, don't allow it to be removed */
6144 if (!vid && !add)
6145 return 0;
6146
6147 return igb_set_vf_vlan(adapter, vid, !!add, vf);
6148 }
6149
6150 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6151 {
6152 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6153
6154 /* clear flags - except flag that indicates PF has set the MAC */
6155 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6156 vf_data->last_nack = jiffies;
6157
6158 /* reset vlans for device */
6159 igb_clear_vf_vfta(adapter, vf);
6160 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6161 igb_set_vmvir(adapter, vf_data->pf_vlan |
6162 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6163 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
6164
6165 /* reset multicast table array for vf */
6166 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6167
6168 /* Flush and reset the mta with the new values */
6169 igb_set_rx_mode(adapter->netdev);
6170 }
6171
6172 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6173 {
6174 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6175
6176 /* clear mac address as we were hotplug removed/added */
6177 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6178 eth_zero_addr(vf_mac);
6179
6180 /* process remaining reset events */
6181 igb_vf_reset(adapter, vf);
6182 }
6183
6184 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6185 {
6186 struct e1000_hw *hw = &adapter->hw;
6187 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6188 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6189 u32 reg, msgbuf[3];
6190 u8 *addr = (u8 *)(&msgbuf[1]);
6191
6192 /* process all the same items cleared in a function level reset */
6193 igb_vf_reset(adapter, vf);
6194
6195 /* set vf mac address */
6196 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6197
6198 /* enable transmit and receive for vf */
6199 reg = rd32(E1000_VFTE);
6200 wr32(E1000_VFTE, reg | (1 << vf));
6201 reg = rd32(E1000_VFRE);
6202 wr32(E1000_VFRE, reg | (1 << vf));
6203
6204 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6205
6206 /* reply to reset with ack and vf mac address */
6207 if (!is_zero_ether_addr(vf_mac)) {
6208 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6209 memcpy(addr, vf_mac, ETH_ALEN);
6210 } else {
6211 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6212 }
6213 igb_write_mbx(hw, msgbuf, 3, vf);
6214 }
6215
6216 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6217 {
6218 /* The VF MAC Address is stored in a packed array of bytes
6219 * starting at the second 32 bit word of the msg array
6220 */
6221 unsigned char *addr = (char *)&msg[1];
6222 int err = -1;
6223
6224 if (is_valid_ether_addr(addr))
6225 err = igb_set_vf_mac(adapter, vf, addr);
6226
6227 return err;
6228 }
6229
6230 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6231 {
6232 struct e1000_hw *hw = &adapter->hw;
6233 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6234 u32 msg = E1000_VT_MSGTYPE_NACK;
6235
6236 /* if device isn't clear to send it shouldn't be reading either */
6237 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6238 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6239 igb_write_mbx(hw, &msg, 1, vf);
6240 vf_data->last_nack = jiffies;
6241 }
6242 }
6243
6244 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6245 {
6246 struct pci_dev *pdev = adapter->pdev;
6247 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6248 struct e1000_hw *hw = &adapter->hw;
6249 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6250 s32 retval;
6251
6252 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6253
6254 if (retval) {
6255 /* if receive failed revoke VF CTS stats and restart init */
6256 dev_err(&pdev->dev, "Error receiving message from VF\n");
6257 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6258 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6259 return;
6260 goto out;
6261 }
6262
6263 /* this is a message we already processed, do nothing */
6264 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6265 return;
6266
6267 /* until the vf completes a reset it should not be
6268 * allowed to start any configuration.
6269 */
6270 if (msgbuf[0] == E1000_VF_RESET) {
6271 igb_vf_reset_msg(adapter, vf);
6272 return;
6273 }
6274
6275 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6276 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6277 return;
6278 retval = -1;
6279 goto out;
6280 }
6281
6282 switch ((msgbuf[0] & 0xFFFF)) {
6283 case E1000_VF_SET_MAC_ADDR:
6284 retval = -EINVAL;
6285 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6286 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6287 else
6288 dev_warn(&pdev->dev,
6289 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6290 vf);
6291 break;
6292 case E1000_VF_SET_PROMISC:
6293 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6294 break;
6295 case E1000_VF_SET_MULTICAST:
6296 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6297 break;
6298 case E1000_VF_SET_LPE:
6299 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6300 break;
6301 case E1000_VF_SET_VLAN:
6302 retval = -1;
6303 if (vf_data->pf_vlan)
6304 dev_warn(&pdev->dev,
6305 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6306 vf);
6307 else
6308 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
6309 break;
6310 default:
6311 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6312 retval = -1;
6313 break;
6314 }
6315
6316 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6317 out:
6318 /* notify the VF of the results of what it sent us */
6319 if (retval)
6320 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6321 else
6322 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6323
6324 igb_write_mbx(hw, msgbuf, 1, vf);
6325 }
6326
6327 static void igb_msg_task(struct igb_adapter *adapter)
6328 {
6329 struct e1000_hw *hw = &adapter->hw;
6330 u32 vf;
6331
6332 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6333 /* process any reset requests */
6334 if (!igb_check_for_rst(hw, vf))
6335 igb_vf_reset_event(adapter, vf);
6336
6337 /* process any messages pending */
6338 if (!igb_check_for_msg(hw, vf))
6339 igb_rcv_msg_from_vf(adapter, vf);
6340
6341 /* process any acks */
6342 if (!igb_check_for_ack(hw, vf))
6343 igb_rcv_ack_from_vf(adapter, vf);
6344 }
6345 }
6346
6347 /**
6348 * igb_set_uta - Set unicast filter table address
6349 * @adapter: board private structure
6350 * @set: boolean indicating if we are setting or clearing bits
6351 *
6352 * The unicast table address is a register array of 32-bit registers.
6353 * The table is meant to be used in a way similar to how the MTA is used
6354 * however due to certain limitations in the hardware it is necessary to
6355 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6356 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6357 **/
6358 static void igb_set_uta(struct igb_adapter *adapter, bool set)
6359 {
6360 struct e1000_hw *hw = &adapter->hw;
6361 u32 uta = set ? ~0 : 0;
6362 int i;
6363
6364 /* we only need to do this if VMDq is enabled */
6365 if (!adapter->vfs_allocated_count)
6366 return;
6367
6368 for (i = hw->mac.uta_reg_count; i--;)
6369 array_wr32(E1000_UTA, i, uta);
6370 }
6371
6372 /**
6373 * igb_intr_msi - Interrupt Handler
6374 * @irq: interrupt number
6375 * @data: pointer to a network interface device structure
6376 **/
6377 static irqreturn_t igb_intr_msi(int irq, void *data)
6378 {
6379 struct igb_adapter *adapter = data;
6380 struct igb_q_vector *q_vector = adapter->q_vector[0];
6381 struct e1000_hw *hw = &adapter->hw;
6382 /* read ICR disables interrupts using IAM */
6383 u32 icr = rd32(E1000_ICR);
6384
6385 igb_write_itr(q_vector);
6386
6387 if (icr & E1000_ICR_DRSTA)
6388 schedule_work(&adapter->reset_task);
6389
6390 if (icr & E1000_ICR_DOUTSYNC) {
6391 /* HW is reporting DMA is out of sync */
6392 adapter->stats.doosync++;
6393 }
6394
6395 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6396 hw->mac.get_link_status = 1;
6397 if (!test_bit(__IGB_DOWN, &adapter->state))
6398 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6399 }
6400
6401 if (icr & E1000_ICR_TS)
6402 igb_tsync_interrupt(adapter);
6403
6404 napi_schedule(&q_vector->napi);
6405
6406 return IRQ_HANDLED;
6407 }
6408
6409 /**
6410 * igb_intr - Legacy Interrupt Handler
6411 * @irq: interrupt number
6412 * @data: pointer to a network interface device structure
6413 **/
6414 static irqreturn_t igb_intr(int irq, void *data)
6415 {
6416 struct igb_adapter *adapter = data;
6417 struct igb_q_vector *q_vector = adapter->q_vector[0];
6418 struct e1000_hw *hw = &adapter->hw;
6419 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6420 * need for the IMC write
6421 */
6422 u32 icr = rd32(E1000_ICR);
6423
6424 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6425 * not set, then the adapter didn't send an interrupt
6426 */
6427 if (!(icr & E1000_ICR_INT_ASSERTED))
6428 return IRQ_NONE;
6429
6430 igb_write_itr(q_vector);
6431
6432 if (icr & E1000_ICR_DRSTA)
6433 schedule_work(&adapter->reset_task);
6434
6435 if (icr & E1000_ICR_DOUTSYNC) {
6436 /* HW is reporting DMA is out of sync */
6437 adapter->stats.doosync++;
6438 }
6439
6440 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6441 hw->mac.get_link_status = 1;
6442 /* guard against interrupt when we're going down */
6443 if (!test_bit(__IGB_DOWN, &adapter->state))
6444 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6445 }
6446
6447 if (icr & E1000_ICR_TS)
6448 igb_tsync_interrupt(adapter);
6449
6450 napi_schedule(&q_vector->napi);
6451
6452 return IRQ_HANDLED;
6453 }
6454
6455 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6456 {
6457 struct igb_adapter *adapter = q_vector->adapter;
6458 struct e1000_hw *hw = &adapter->hw;
6459
6460 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6461 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6462 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6463 igb_set_itr(q_vector);
6464 else
6465 igb_update_ring_itr(q_vector);
6466 }
6467
6468 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6469 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6470 wr32(E1000_EIMS, q_vector->eims_value);
6471 else
6472 igb_irq_enable(adapter);
6473 }
6474 }
6475
6476 /**
6477 * igb_poll - NAPI Rx polling callback
6478 * @napi: napi polling structure
6479 * @budget: count of how many packets we should handle
6480 **/
6481 static int igb_poll(struct napi_struct *napi, int budget)
6482 {
6483 struct igb_q_vector *q_vector = container_of(napi,
6484 struct igb_q_vector,
6485 napi);
6486 bool clean_complete = true;
6487 int work_done = 0;
6488
6489 #ifdef CONFIG_IGB_DCA
6490 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6491 igb_update_dca(q_vector);
6492 #endif
6493 if (q_vector->tx.ring)
6494 clean_complete = igb_clean_tx_irq(q_vector);
6495
6496 if (q_vector->rx.ring) {
6497 int cleaned = igb_clean_rx_irq(q_vector, budget);
6498
6499 work_done += cleaned;
6500 clean_complete &= (cleaned < budget);
6501 }
6502
6503 /* If all work not completed, return budget and keep polling */
6504 if (!clean_complete)
6505 return budget;
6506
6507 /* If not enough Rx work done, exit the polling mode */
6508 napi_complete_done(napi, work_done);
6509 igb_ring_irq_enable(q_vector);
6510
6511 return 0;
6512 }
6513
6514 /**
6515 * igb_clean_tx_irq - Reclaim resources after transmit completes
6516 * @q_vector: pointer to q_vector containing needed info
6517 *
6518 * returns true if ring is completely cleaned
6519 **/
6520 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6521 {
6522 struct igb_adapter *adapter = q_vector->adapter;
6523 struct igb_ring *tx_ring = q_vector->tx.ring;
6524 struct igb_tx_buffer *tx_buffer;
6525 union e1000_adv_tx_desc *tx_desc;
6526 unsigned int total_bytes = 0, total_packets = 0;
6527 unsigned int budget = q_vector->tx.work_limit;
6528 unsigned int i = tx_ring->next_to_clean;
6529
6530 if (test_bit(__IGB_DOWN, &adapter->state))
6531 return true;
6532
6533 tx_buffer = &tx_ring->tx_buffer_info[i];
6534 tx_desc = IGB_TX_DESC(tx_ring, i);
6535 i -= tx_ring->count;
6536
6537 do {
6538 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6539
6540 /* if next_to_watch is not set then there is no work pending */
6541 if (!eop_desc)
6542 break;
6543
6544 /* prevent any other reads prior to eop_desc */
6545 read_barrier_depends();
6546
6547 /* if DD is not set pending work has not been completed */
6548 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6549 break;
6550
6551 /* clear next_to_watch to prevent false hangs */
6552 tx_buffer->next_to_watch = NULL;
6553
6554 /* update the statistics for this packet */
6555 total_bytes += tx_buffer->bytecount;
6556 total_packets += tx_buffer->gso_segs;
6557
6558 /* free the skb */
6559 dev_consume_skb_any(tx_buffer->skb);
6560
6561 /* unmap skb header data */
6562 dma_unmap_single(tx_ring->dev,
6563 dma_unmap_addr(tx_buffer, dma),
6564 dma_unmap_len(tx_buffer, len),
6565 DMA_TO_DEVICE);
6566
6567 /* clear tx_buffer data */
6568 tx_buffer->skb = NULL;
6569 dma_unmap_len_set(tx_buffer, len, 0);
6570
6571 /* clear last DMA location and unmap remaining buffers */
6572 while (tx_desc != eop_desc) {
6573 tx_buffer++;
6574 tx_desc++;
6575 i++;
6576 if (unlikely(!i)) {
6577 i -= tx_ring->count;
6578 tx_buffer = tx_ring->tx_buffer_info;
6579 tx_desc = IGB_TX_DESC(tx_ring, 0);
6580 }
6581
6582 /* unmap any remaining paged data */
6583 if (dma_unmap_len(tx_buffer, len)) {
6584 dma_unmap_page(tx_ring->dev,
6585 dma_unmap_addr(tx_buffer, dma),
6586 dma_unmap_len(tx_buffer, len),
6587 DMA_TO_DEVICE);
6588 dma_unmap_len_set(tx_buffer, len, 0);
6589 }
6590 }
6591
6592 /* move us one more past the eop_desc for start of next pkt */
6593 tx_buffer++;
6594 tx_desc++;
6595 i++;
6596 if (unlikely(!i)) {
6597 i -= tx_ring->count;
6598 tx_buffer = tx_ring->tx_buffer_info;
6599 tx_desc = IGB_TX_DESC(tx_ring, 0);
6600 }
6601
6602 /* issue prefetch for next Tx descriptor */
6603 prefetch(tx_desc);
6604
6605 /* update budget accounting */
6606 budget--;
6607 } while (likely(budget));
6608
6609 netdev_tx_completed_queue(txring_txq(tx_ring),
6610 total_packets, total_bytes);
6611 i += tx_ring->count;
6612 tx_ring->next_to_clean = i;
6613 u64_stats_update_begin(&tx_ring->tx_syncp);
6614 tx_ring->tx_stats.bytes += total_bytes;
6615 tx_ring->tx_stats.packets += total_packets;
6616 u64_stats_update_end(&tx_ring->tx_syncp);
6617 q_vector->tx.total_bytes += total_bytes;
6618 q_vector->tx.total_packets += total_packets;
6619
6620 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6621 struct e1000_hw *hw = &adapter->hw;
6622
6623 /* Detect a transmit hang in hardware, this serializes the
6624 * check with the clearing of time_stamp and movement of i
6625 */
6626 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6627 if (tx_buffer->next_to_watch &&
6628 time_after(jiffies, tx_buffer->time_stamp +
6629 (adapter->tx_timeout_factor * HZ)) &&
6630 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6631
6632 /* detected Tx unit hang */
6633 dev_err(tx_ring->dev,
6634 "Detected Tx Unit Hang\n"
6635 " Tx Queue <%d>\n"
6636 " TDH <%x>\n"
6637 " TDT <%x>\n"
6638 " next_to_use <%x>\n"
6639 " next_to_clean <%x>\n"
6640 "buffer_info[next_to_clean]\n"
6641 " time_stamp <%lx>\n"
6642 " next_to_watch <%p>\n"
6643 " jiffies <%lx>\n"
6644 " desc.status <%x>\n",
6645 tx_ring->queue_index,
6646 rd32(E1000_TDH(tx_ring->reg_idx)),
6647 readl(tx_ring->tail),
6648 tx_ring->next_to_use,
6649 tx_ring->next_to_clean,
6650 tx_buffer->time_stamp,
6651 tx_buffer->next_to_watch,
6652 jiffies,
6653 tx_buffer->next_to_watch->wb.status);
6654 netif_stop_subqueue(tx_ring->netdev,
6655 tx_ring->queue_index);
6656
6657 /* we are about to reset, no point in enabling stuff */
6658 return true;
6659 }
6660 }
6661
6662 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6663 if (unlikely(total_packets &&
6664 netif_carrier_ok(tx_ring->netdev) &&
6665 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6666 /* Make sure that anybody stopping the queue after this
6667 * sees the new next_to_clean.
6668 */
6669 smp_mb();
6670 if (__netif_subqueue_stopped(tx_ring->netdev,
6671 tx_ring->queue_index) &&
6672 !(test_bit(__IGB_DOWN, &adapter->state))) {
6673 netif_wake_subqueue(tx_ring->netdev,
6674 tx_ring->queue_index);
6675
6676 u64_stats_update_begin(&tx_ring->tx_syncp);
6677 tx_ring->tx_stats.restart_queue++;
6678 u64_stats_update_end(&tx_ring->tx_syncp);
6679 }
6680 }
6681
6682 return !!budget;
6683 }
6684
6685 /**
6686 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6687 * @rx_ring: rx descriptor ring to store buffers on
6688 * @old_buff: donor buffer to have page reused
6689 *
6690 * Synchronizes page for reuse by the adapter
6691 **/
6692 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6693 struct igb_rx_buffer *old_buff)
6694 {
6695 struct igb_rx_buffer *new_buff;
6696 u16 nta = rx_ring->next_to_alloc;
6697
6698 new_buff = &rx_ring->rx_buffer_info[nta];
6699
6700 /* update, and store next to alloc */
6701 nta++;
6702 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6703
6704 /* transfer page from old buffer to new buffer */
6705 *new_buff = *old_buff;
6706
6707 /* sync the buffer for use by the device */
6708 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6709 old_buff->page_offset,
6710 IGB_RX_BUFSZ,
6711 DMA_FROM_DEVICE);
6712 }
6713
6714 static inline bool igb_page_is_reserved(struct page *page)
6715 {
6716 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6717 }
6718
6719 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6720 struct page *page,
6721 unsigned int truesize)
6722 {
6723 /* avoid re-using remote pages */
6724 if (unlikely(igb_page_is_reserved(page)))
6725 return false;
6726
6727 #if (PAGE_SIZE < 8192)
6728 /* if we are only owner of page we can reuse it */
6729 if (unlikely(page_count(page) != 1))
6730 return false;
6731
6732 /* flip page offset to other buffer */
6733 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6734 #else
6735 /* move offset up to the next cache line */
6736 rx_buffer->page_offset += truesize;
6737
6738 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6739 return false;
6740 #endif
6741
6742 /* Even if we own the page, we are not allowed to use atomic_set()
6743 * This would break get_page_unless_zero() users.
6744 */
6745 atomic_inc(&page->_count);
6746
6747 return true;
6748 }
6749
6750 /**
6751 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6752 * @rx_ring: rx descriptor ring to transact packets on
6753 * @rx_buffer: buffer containing page to add
6754 * @rx_desc: descriptor containing length of buffer written by hardware
6755 * @skb: sk_buff to place the data into
6756 *
6757 * This function will add the data contained in rx_buffer->page to the skb.
6758 * This is done either through a direct copy if the data in the buffer is
6759 * less than the skb header size, otherwise it will just attach the page as
6760 * a frag to the skb.
6761 *
6762 * The function will then update the page offset if necessary and return
6763 * true if the buffer can be reused by the adapter.
6764 **/
6765 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6766 struct igb_rx_buffer *rx_buffer,
6767 union e1000_adv_rx_desc *rx_desc,
6768 struct sk_buff *skb)
6769 {
6770 struct page *page = rx_buffer->page;
6771 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6772 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6773 #if (PAGE_SIZE < 8192)
6774 unsigned int truesize = IGB_RX_BUFSZ;
6775 #else
6776 unsigned int truesize = SKB_DATA_ALIGN(size);
6777 #endif
6778 unsigned int pull_len;
6779
6780 if (unlikely(skb_is_nonlinear(skb)))
6781 goto add_tail_frag;
6782
6783 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6784 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6785 va += IGB_TS_HDR_LEN;
6786 size -= IGB_TS_HDR_LEN;
6787 }
6788
6789 if (likely(size <= IGB_RX_HDR_LEN)) {
6790 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6791
6792 /* page is not reserved, we can reuse buffer as-is */
6793 if (likely(!igb_page_is_reserved(page)))
6794 return true;
6795
6796 /* this page cannot be reused so discard it */
6797 __free_page(page);
6798 return false;
6799 }
6800
6801 /* we need the header to contain the greater of either ETH_HLEN or
6802 * 60 bytes if the skb->len is less than 60 for skb_pad.
6803 */
6804 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6805
6806 /* align pull length to size of long to optimize memcpy performance */
6807 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6808
6809 /* update all of the pointers */
6810 va += pull_len;
6811 size -= pull_len;
6812
6813 add_tail_frag:
6814 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6815 (unsigned long)va & ~PAGE_MASK, size, truesize);
6816
6817 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6818 }
6819
6820 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6821 union e1000_adv_rx_desc *rx_desc,
6822 struct sk_buff *skb)
6823 {
6824 struct igb_rx_buffer *rx_buffer;
6825 struct page *page;
6826
6827 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6828 page = rx_buffer->page;
6829 prefetchw(page);
6830
6831 if (likely(!skb)) {
6832 void *page_addr = page_address(page) +
6833 rx_buffer->page_offset;
6834
6835 /* prefetch first cache line of first page */
6836 prefetch(page_addr);
6837 #if L1_CACHE_BYTES < 128
6838 prefetch(page_addr + L1_CACHE_BYTES);
6839 #endif
6840
6841 /* allocate a skb to store the frags */
6842 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6843 if (unlikely(!skb)) {
6844 rx_ring->rx_stats.alloc_failed++;
6845 return NULL;
6846 }
6847
6848 /* we will be copying header into skb->data in
6849 * pskb_may_pull so it is in our interest to prefetch
6850 * it now to avoid a possible cache miss
6851 */
6852 prefetchw(skb->data);
6853 }
6854
6855 /* we are reusing so sync this buffer for CPU use */
6856 dma_sync_single_range_for_cpu(rx_ring->dev,
6857 rx_buffer->dma,
6858 rx_buffer->page_offset,
6859 IGB_RX_BUFSZ,
6860 DMA_FROM_DEVICE);
6861
6862 /* pull page into skb */
6863 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6864 /* hand second half of page back to the ring */
6865 igb_reuse_rx_page(rx_ring, rx_buffer);
6866 } else {
6867 /* we are not reusing the buffer so unmap it */
6868 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6869 PAGE_SIZE, DMA_FROM_DEVICE);
6870 }
6871
6872 /* clear contents of rx_buffer */
6873 rx_buffer->page = NULL;
6874
6875 return skb;
6876 }
6877
6878 static inline void igb_rx_checksum(struct igb_ring *ring,
6879 union e1000_adv_rx_desc *rx_desc,
6880 struct sk_buff *skb)
6881 {
6882 skb_checksum_none_assert(skb);
6883
6884 /* Ignore Checksum bit is set */
6885 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6886 return;
6887
6888 /* Rx checksum disabled via ethtool */
6889 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6890 return;
6891
6892 /* TCP/UDP checksum error bit is set */
6893 if (igb_test_staterr(rx_desc,
6894 E1000_RXDEXT_STATERR_TCPE |
6895 E1000_RXDEXT_STATERR_IPE)) {
6896 /* work around errata with sctp packets where the TCPE aka
6897 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6898 * packets, (aka let the stack check the crc32c)
6899 */
6900 if (!((skb->len == 60) &&
6901 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6902 u64_stats_update_begin(&ring->rx_syncp);
6903 ring->rx_stats.csum_err++;
6904 u64_stats_update_end(&ring->rx_syncp);
6905 }
6906 /* let the stack verify checksum errors */
6907 return;
6908 }
6909 /* It must be a TCP or UDP packet with a valid checksum */
6910 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6911 E1000_RXD_STAT_UDPCS))
6912 skb->ip_summed = CHECKSUM_UNNECESSARY;
6913
6914 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6915 le32_to_cpu(rx_desc->wb.upper.status_error));
6916 }
6917
6918 static inline void igb_rx_hash(struct igb_ring *ring,
6919 union e1000_adv_rx_desc *rx_desc,
6920 struct sk_buff *skb)
6921 {
6922 if (ring->netdev->features & NETIF_F_RXHASH)
6923 skb_set_hash(skb,
6924 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6925 PKT_HASH_TYPE_L3);
6926 }
6927
6928 /**
6929 * igb_is_non_eop - process handling of non-EOP buffers
6930 * @rx_ring: Rx ring being processed
6931 * @rx_desc: Rx descriptor for current buffer
6932 * @skb: current socket buffer containing buffer in progress
6933 *
6934 * This function updates next to clean. If the buffer is an EOP buffer
6935 * this function exits returning false, otherwise it will place the
6936 * sk_buff in the next buffer to be chained and return true indicating
6937 * that this is in fact a non-EOP buffer.
6938 **/
6939 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6940 union e1000_adv_rx_desc *rx_desc)
6941 {
6942 u32 ntc = rx_ring->next_to_clean + 1;
6943
6944 /* fetch, update, and store next to clean */
6945 ntc = (ntc < rx_ring->count) ? ntc : 0;
6946 rx_ring->next_to_clean = ntc;
6947
6948 prefetch(IGB_RX_DESC(rx_ring, ntc));
6949
6950 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6951 return false;
6952
6953 return true;
6954 }
6955
6956 /**
6957 * igb_cleanup_headers - Correct corrupted or empty headers
6958 * @rx_ring: rx descriptor ring packet is being transacted on
6959 * @rx_desc: pointer to the EOP Rx descriptor
6960 * @skb: pointer to current skb being fixed
6961 *
6962 * Address the case where we are pulling data in on pages only
6963 * and as such no data is present in the skb header.
6964 *
6965 * In addition if skb is not at least 60 bytes we need to pad it so that
6966 * it is large enough to qualify as a valid Ethernet frame.
6967 *
6968 * Returns true if an error was encountered and skb was freed.
6969 **/
6970 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6971 union e1000_adv_rx_desc *rx_desc,
6972 struct sk_buff *skb)
6973 {
6974 if (unlikely((igb_test_staterr(rx_desc,
6975 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6976 struct net_device *netdev = rx_ring->netdev;
6977 if (!(netdev->features & NETIF_F_RXALL)) {
6978 dev_kfree_skb_any(skb);
6979 return true;
6980 }
6981 }
6982
6983 /* if eth_skb_pad returns an error the skb was freed */
6984 if (eth_skb_pad(skb))
6985 return true;
6986
6987 return false;
6988 }
6989
6990 /**
6991 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6992 * @rx_ring: rx descriptor ring packet is being transacted on
6993 * @rx_desc: pointer to the EOP Rx descriptor
6994 * @skb: pointer to current skb being populated
6995 *
6996 * This function checks the ring, descriptor, and packet information in
6997 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6998 * other fields within the skb.
6999 **/
7000 static void igb_process_skb_fields(struct igb_ring *rx_ring,
7001 union e1000_adv_rx_desc *rx_desc,
7002 struct sk_buff *skb)
7003 {
7004 struct net_device *dev = rx_ring->netdev;
7005
7006 igb_rx_hash(rx_ring, rx_desc, skb);
7007
7008 igb_rx_checksum(rx_ring, rx_desc, skb);
7009
7010 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7011 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7012 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
7013
7014 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
7015 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7016 u16 vid;
7017
7018 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7019 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7020 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7021 else
7022 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7023
7024 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
7025 }
7026
7027 skb_record_rx_queue(skb, rx_ring->queue_index);
7028
7029 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7030 }
7031
7032 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
7033 {
7034 struct igb_ring *rx_ring = q_vector->rx.ring;
7035 struct sk_buff *skb = rx_ring->skb;
7036 unsigned int total_bytes = 0, total_packets = 0;
7037 u16 cleaned_count = igb_desc_unused(rx_ring);
7038
7039 while (likely(total_packets < budget)) {
7040 union e1000_adv_rx_desc *rx_desc;
7041
7042 /* return some buffers to hardware, one at a time is too slow */
7043 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7044 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7045 cleaned_count = 0;
7046 }
7047
7048 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
7049
7050 if (!rx_desc->wb.upper.status_error)
7051 break;
7052
7053 /* This memory barrier is needed to keep us from reading
7054 * any other fields out of the rx_desc until we know the
7055 * descriptor has been written back
7056 */
7057 dma_rmb();
7058
7059 /* retrieve a buffer from the ring */
7060 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
7061
7062 /* exit if we failed to retrieve a buffer */
7063 if (!skb)
7064 break;
7065
7066 cleaned_count++;
7067
7068 /* fetch next buffer in frame if non-eop */
7069 if (igb_is_non_eop(rx_ring, rx_desc))
7070 continue;
7071
7072 /* verify the packet layout is correct */
7073 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7074 skb = NULL;
7075 continue;
7076 }
7077
7078 /* probably a little skewed due to removing CRC */
7079 total_bytes += skb->len;
7080
7081 /* populate checksum, timestamp, VLAN, and protocol */
7082 igb_process_skb_fields(rx_ring, rx_desc, skb);
7083
7084 napi_gro_receive(&q_vector->napi, skb);
7085
7086 /* reset skb pointer */
7087 skb = NULL;
7088
7089 /* update budget accounting */
7090 total_packets++;
7091 }
7092
7093 /* place incomplete frames back on ring for completion */
7094 rx_ring->skb = skb;
7095
7096 u64_stats_update_begin(&rx_ring->rx_syncp);
7097 rx_ring->rx_stats.packets += total_packets;
7098 rx_ring->rx_stats.bytes += total_bytes;
7099 u64_stats_update_end(&rx_ring->rx_syncp);
7100 q_vector->rx.total_packets += total_packets;
7101 q_vector->rx.total_bytes += total_bytes;
7102
7103 if (cleaned_count)
7104 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7105
7106 return total_packets;
7107 }
7108
7109 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7110 struct igb_rx_buffer *bi)
7111 {
7112 struct page *page = bi->page;
7113 dma_addr_t dma;
7114
7115 /* since we are recycling buffers we should seldom need to alloc */
7116 if (likely(page))
7117 return true;
7118
7119 /* alloc new page for storage */
7120 page = dev_alloc_page();
7121 if (unlikely(!page)) {
7122 rx_ring->rx_stats.alloc_failed++;
7123 return false;
7124 }
7125
7126 /* map page for use */
7127 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7128
7129 /* if mapping failed free memory back to system since
7130 * there isn't much point in holding memory we can't use
7131 */
7132 if (dma_mapping_error(rx_ring->dev, dma)) {
7133 __free_page(page);
7134
7135 rx_ring->rx_stats.alloc_failed++;
7136 return false;
7137 }
7138
7139 bi->dma = dma;
7140 bi->page = page;
7141 bi->page_offset = 0;
7142
7143 return true;
7144 }
7145
7146 /**
7147 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7148 * @adapter: address of board private structure
7149 **/
7150 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7151 {
7152 union e1000_adv_rx_desc *rx_desc;
7153 struct igb_rx_buffer *bi;
7154 u16 i = rx_ring->next_to_use;
7155
7156 /* nothing to do */
7157 if (!cleaned_count)
7158 return;
7159
7160 rx_desc = IGB_RX_DESC(rx_ring, i);
7161 bi = &rx_ring->rx_buffer_info[i];
7162 i -= rx_ring->count;
7163
7164 do {
7165 if (!igb_alloc_mapped_page(rx_ring, bi))
7166 break;
7167
7168 /* Refresh the desc even if buffer_addrs didn't change
7169 * because each write-back erases this info.
7170 */
7171 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7172
7173 rx_desc++;
7174 bi++;
7175 i++;
7176 if (unlikely(!i)) {
7177 rx_desc = IGB_RX_DESC(rx_ring, 0);
7178 bi = rx_ring->rx_buffer_info;
7179 i -= rx_ring->count;
7180 }
7181
7182 /* clear the status bits for the next_to_use descriptor */
7183 rx_desc->wb.upper.status_error = 0;
7184
7185 cleaned_count--;
7186 } while (cleaned_count);
7187
7188 i += rx_ring->count;
7189
7190 if (rx_ring->next_to_use != i) {
7191 /* record the next descriptor to use */
7192 rx_ring->next_to_use = i;
7193
7194 /* update next to alloc since we have filled the ring */
7195 rx_ring->next_to_alloc = i;
7196
7197 /* Force memory writes to complete before letting h/w
7198 * know there are new descriptors to fetch. (Only
7199 * applicable for weak-ordered memory model archs,
7200 * such as IA-64).
7201 */
7202 wmb();
7203 writel(i, rx_ring->tail);
7204 }
7205 }
7206
7207 /**
7208 * igb_mii_ioctl -
7209 * @netdev:
7210 * @ifreq:
7211 * @cmd:
7212 **/
7213 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7214 {
7215 struct igb_adapter *adapter = netdev_priv(netdev);
7216 struct mii_ioctl_data *data = if_mii(ifr);
7217
7218 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7219 return -EOPNOTSUPP;
7220
7221 switch (cmd) {
7222 case SIOCGMIIPHY:
7223 data->phy_id = adapter->hw.phy.addr;
7224 break;
7225 case SIOCGMIIREG:
7226 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7227 &data->val_out))
7228 return -EIO;
7229 break;
7230 case SIOCSMIIREG:
7231 default:
7232 return -EOPNOTSUPP;
7233 }
7234 return 0;
7235 }
7236
7237 /**
7238 * igb_ioctl -
7239 * @netdev:
7240 * @ifreq:
7241 * @cmd:
7242 **/
7243 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7244 {
7245 switch (cmd) {
7246 case SIOCGMIIPHY:
7247 case SIOCGMIIREG:
7248 case SIOCSMIIREG:
7249 return igb_mii_ioctl(netdev, ifr, cmd);
7250 case SIOCGHWTSTAMP:
7251 return igb_ptp_get_ts_config(netdev, ifr);
7252 case SIOCSHWTSTAMP:
7253 return igb_ptp_set_ts_config(netdev, ifr);
7254 default:
7255 return -EOPNOTSUPP;
7256 }
7257 }
7258
7259 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7260 {
7261 struct igb_adapter *adapter = hw->back;
7262
7263 pci_read_config_word(adapter->pdev, reg, value);
7264 }
7265
7266 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7267 {
7268 struct igb_adapter *adapter = hw->back;
7269
7270 pci_write_config_word(adapter->pdev, reg, *value);
7271 }
7272
7273 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7274 {
7275 struct igb_adapter *adapter = hw->back;
7276
7277 if (pcie_capability_read_word(adapter->pdev, reg, value))
7278 return -E1000_ERR_CONFIG;
7279
7280 return 0;
7281 }
7282
7283 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7284 {
7285 struct igb_adapter *adapter = hw->back;
7286
7287 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7288 return -E1000_ERR_CONFIG;
7289
7290 return 0;
7291 }
7292
7293 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7294 {
7295 struct igb_adapter *adapter = netdev_priv(netdev);
7296 struct e1000_hw *hw = &adapter->hw;
7297 u32 ctrl, rctl;
7298 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7299
7300 if (enable) {
7301 /* enable VLAN tag insert/strip */
7302 ctrl = rd32(E1000_CTRL);
7303 ctrl |= E1000_CTRL_VME;
7304 wr32(E1000_CTRL, ctrl);
7305
7306 /* Disable CFI check */
7307 rctl = rd32(E1000_RCTL);
7308 rctl &= ~E1000_RCTL_CFIEN;
7309 wr32(E1000_RCTL, rctl);
7310 } else {
7311 /* disable VLAN tag insert/strip */
7312 ctrl = rd32(E1000_CTRL);
7313 ctrl &= ~E1000_CTRL_VME;
7314 wr32(E1000_CTRL, ctrl);
7315 }
7316 }
7317
7318 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7319 __be16 proto, u16 vid)
7320 {
7321 struct igb_adapter *adapter = netdev_priv(netdev);
7322 struct e1000_hw *hw = &adapter->hw;
7323 int pf_id = adapter->vfs_allocated_count;
7324
7325 /* add the filter since PF can receive vlans w/o entry in vlvf */
7326 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7327 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7328
7329 set_bit(vid, adapter->active_vlans);
7330
7331 return 0;
7332 }
7333
7334 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7335 __be16 proto, u16 vid)
7336 {
7337 struct igb_adapter *adapter = netdev_priv(netdev);
7338 int pf_id = adapter->vfs_allocated_count;
7339 struct e1000_hw *hw = &adapter->hw;
7340
7341 /* remove VID from filter table */
7342 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7343 igb_vfta_set(hw, vid, pf_id, false, true);
7344
7345 clear_bit(vid, adapter->active_vlans);
7346
7347 return 0;
7348 }
7349
7350 static void igb_restore_vlan(struct igb_adapter *adapter)
7351 {
7352 u16 vid = 1;
7353
7354 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7355 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
7356
7357 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
7358 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7359 }
7360
7361 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7362 {
7363 struct pci_dev *pdev = adapter->pdev;
7364 struct e1000_mac_info *mac = &adapter->hw.mac;
7365
7366 mac->autoneg = 0;
7367
7368 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7369 * for the switch() below to work
7370 */
7371 if ((spd & 1) || (dplx & ~1))
7372 goto err_inval;
7373
7374 /* Fiber NIC's only allow 1000 gbps Full duplex
7375 * and 100Mbps Full duplex for 100baseFx sfp
7376 */
7377 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7378 switch (spd + dplx) {
7379 case SPEED_10 + DUPLEX_HALF:
7380 case SPEED_10 + DUPLEX_FULL:
7381 case SPEED_100 + DUPLEX_HALF:
7382 goto err_inval;
7383 default:
7384 break;
7385 }
7386 }
7387
7388 switch (spd + dplx) {
7389 case SPEED_10 + DUPLEX_HALF:
7390 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7391 break;
7392 case SPEED_10 + DUPLEX_FULL:
7393 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7394 break;
7395 case SPEED_100 + DUPLEX_HALF:
7396 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7397 break;
7398 case SPEED_100 + DUPLEX_FULL:
7399 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7400 break;
7401 case SPEED_1000 + DUPLEX_FULL:
7402 mac->autoneg = 1;
7403 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7404 break;
7405 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7406 default:
7407 goto err_inval;
7408 }
7409
7410 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7411 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7412
7413 return 0;
7414
7415 err_inval:
7416 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7417 return -EINVAL;
7418 }
7419
7420 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7421 bool runtime)
7422 {
7423 struct net_device *netdev = pci_get_drvdata(pdev);
7424 struct igb_adapter *adapter = netdev_priv(netdev);
7425 struct e1000_hw *hw = &adapter->hw;
7426 u32 ctrl, rctl, status;
7427 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7428 #ifdef CONFIG_PM
7429 int retval = 0;
7430 #endif
7431
7432 netif_device_detach(netdev);
7433
7434 if (netif_running(netdev))
7435 __igb_close(netdev, true);
7436
7437 igb_clear_interrupt_scheme(adapter);
7438
7439 #ifdef CONFIG_PM
7440 retval = pci_save_state(pdev);
7441 if (retval)
7442 return retval;
7443 #endif
7444
7445 status = rd32(E1000_STATUS);
7446 if (status & E1000_STATUS_LU)
7447 wufc &= ~E1000_WUFC_LNKC;
7448
7449 if (wufc) {
7450 igb_setup_rctl(adapter);
7451 igb_set_rx_mode(netdev);
7452
7453 /* turn on all-multi mode if wake on multicast is enabled */
7454 if (wufc & E1000_WUFC_MC) {
7455 rctl = rd32(E1000_RCTL);
7456 rctl |= E1000_RCTL_MPE;
7457 wr32(E1000_RCTL, rctl);
7458 }
7459
7460 ctrl = rd32(E1000_CTRL);
7461 /* advertise wake from D3Cold */
7462 #define E1000_CTRL_ADVD3WUC 0x00100000
7463 /* phy power management enable */
7464 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7465 ctrl |= E1000_CTRL_ADVD3WUC;
7466 wr32(E1000_CTRL, ctrl);
7467
7468 /* Allow time for pending master requests to run */
7469 igb_disable_pcie_master(hw);
7470
7471 wr32(E1000_WUC, E1000_WUC_PME_EN);
7472 wr32(E1000_WUFC, wufc);
7473 } else {
7474 wr32(E1000_WUC, 0);
7475 wr32(E1000_WUFC, 0);
7476 }
7477
7478 *enable_wake = wufc || adapter->en_mng_pt;
7479 if (!*enable_wake)
7480 igb_power_down_link(adapter);
7481 else
7482 igb_power_up_link(adapter);
7483
7484 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7485 * would have already happened in close and is redundant.
7486 */
7487 igb_release_hw_control(adapter);
7488
7489 pci_disable_device(pdev);
7490
7491 return 0;
7492 }
7493
7494 #ifdef CONFIG_PM
7495 #ifdef CONFIG_PM_SLEEP
7496 static int igb_suspend(struct device *dev)
7497 {
7498 int retval;
7499 bool wake;
7500 struct pci_dev *pdev = to_pci_dev(dev);
7501
7502 retval = __igb_shutdown(pdev, &wake, 0);
7503 if (retval)
7504 return retval;
7505
7506 if (wake) {
7507 pci_prepare_to_sleep(pdev);
7508 } else {
7509 pci_wake_from_d3(pdev, false);
7510 pci_set_power_state(pdev, PCI_D3hot);
7511 }
7512
7513 return 0;
7514 }
7515 #endif /* CONFIG_PM_SLEEP */
7516
7517 static int igb_resume(struct device *dev)
7518 {
7519 struct pci_dev *pdev = to_pci_dev(dev);
7520 struct net_device *netdev = pci_get_drvdata(pdev);
7521 struct igb_adapter *adapter = netdev_priv(netdev);
7522 struct e1000_hw *hw = &adapter->hw;
7523 u32 err;
7524
7525 pci_set_power_state(pdev, PCI_D0);
7526 pci_restore_state(pdev);
7527 pci_save_state(pdev);
7528
7529 if (!pci_device_is_present(pdev))
7530 return -ENODEV;
7531 err = pci_enable_device_mem(pdev);
7532 if (err) {
7533 dev_err(&pdev->dev,
7534 "igb: Cannot enable PCI device from suspend\n");
7535 return err;
7536 }
7537 pci_set_master(pdev);
7538
7539 pci_enable_wake(pdev, PCI_D3hot, 0);
7540 pci_enable_wake(pdev, PCI_D3cold, 0);
7541
7542 if (igb_init_interrupt_scheme(adapter, true)) {
7543 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7544 rtnl_unlock();
7545 return -ENOMEM;
7546 }
7547
7548 igb_reset(adapter);
7549
7550 /* let the f/w know that the h/w is now under the control of the
7551 * driver.
7552 */
7553 igb_get_hw_control(adapter);
7554
7555 wr32(E1000_WUS, ~0);
7556
7557 if (netdev->flags & IFF_UP) {
7558 rtnl_lock();
7559 err = __igb_open(netdev, true);
7560 rtnl_unlock();
7561 if (err)
7562 return err;
7563 }
7564
7565 netif_device_attach(netdev);
7566 return 0;
7567 }
7568
7569 static int igb_runtime_idle(struct device *dev)
7570 {
7571 struct pci_dev *pdev = to_pci_dev(dev);
7572 struct net_device *netdev = pci_get_drvdata(pdev);
7573 struct igb_adapter *adapter = netdev_priv(netdev);
7574
7575 if (!igb_has_link(adapter))
7576 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7577
7578 return -EBUSY;
7579 }
7580
7581 static int igb_runtime_suspend(struct device *dev)
7582 {
7583 struct pci_dev *pdev = to_pci_dev(dev);
7584 int retval;
7585 bool wake;
7586
7587 retval = __igb_shutdown(pdev, &wake, 1);
7588 if (retval)
7589 return retval;
7590
7591 if (wake) {
7592 pci_prepare_to_sleep(pdev);
7593 } else {
7594 pci_wake_from_d3(pdev, false);
7595 pci_set_power_state(pdev, PCI_D3hot);
7596 }
7597
7598 return 0;
7599 }
7600
7601 static int igb_runtime_resume(struct device *dev)
7602 {
7603 return igb_resume(dev);
7604 }
7605 #endif /* CONFIG_PM */
7606
7607 static void igb_shutdown(struct pci_dev *pdev)
7608 {
7609 bool wake;
7610
7611 __igb_shutdown(pdev, &wake, 0);
7612
7613 if (system_state == SYSTEM_POWER_OFF) {
7614 pci_wake_from_d3(pdev, wake);
7615 pci_set_power_state(pdev, PCI_D3hot);
7616 }
7617 }
7618
7619 #ifdef CONFIG_PCI_IOV
7620 static int igb_sriov_reinit(struct pci_dev *dev)
7621 {
7622 struct net_device *netdev = pci_get_drvdata(dev);
7623 struct igb_adapter *adapter = netdev_priv(netdev);
7624 struct pci_dev *pdev = adapter->pdev;
7625
7626 rtnl_lock();
7627
7628 if (netif_running(netdev))
7629 igb_close(netdev);
7630 else
7631 igb_reset(adapter);
7632
7633 igb_clear_interrupt_scheme(adapter);
7634
7635 igb_init_queue_configuration(adapter);
7636
7637 if (igb_init_interrupt_scheme(adapter, true)) {
7638 rtnl_unlock();
7639 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7640 return -ENOMEM;
7641 }
7642
7643 if (netif_running(netdev))
7644 igb_open(netdev);
7645
7646 rtnl_unlock();
7647
7648 return 0;
7649 }
7650
7651 static int igb_pci_disable_sriov(struct pci_dev *dev)
7652 {
7653 int err = igb_disable_sriov(dev);
7654
7655 if (!err)
7656 err = igb_sriov_reinit(dev);
7657
7658 return err;
7659 }
7660
7661 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7662 {
7663 int err = igb_enable_sriov(dev, num_vfs);
7664
7665 if (err)
7666 goto out;
7667
7668 err = igb_sriov_reinit(dev);
7669 if (!err)
7670 return num_vfs;
7671
7672 out:
7673 return err;
7674 }
7675
7676 #endif
7677 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7678 {
7679 #ifdef CONFIG_PCI_IOV
7680 if (num_vfs == 0)
7681 return igb_pci_disable_sriov(dev);
7682 else
7683 return igb_pci_enable_sriov(dev, num_vfs);
7684 #endif
7685 return 0;
7686 }
7687
7688 #ifdef CONFIG_NET_POLL_CONTROLLER
7689 /* Polling 'interrupt' - used by things like netconsole to send skbs
7690 * without having to re-enable interrupts. It's not called while
7691 * the interrupt routine is executing.
7692 */
7693 static void igb_netpoll(struct net_device *netdev)
7694 {
7695 struct igb_adapter *adapter = netdev_priv(netdev);
7696 struct e1000_hw *hw = &adapter->hw;
7697 struct igb_q_vector *q_vector;
7698 int i;
7699
7700 for (i = 0; i < adapter->num_q_vectors; i++) {
7701 q_vector = adapter->q_vector[i];
7702 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7703 wr32(E1000_EIMC, q_vector->eims_value);
7704 else
7705 igb_irq_disable(adapter);
7706 napi_schedule(&q_vector->napi);
7707 }
7708 }
7709 #endif /* CONFIG_NET_POLL_CONTROLLER */
7710
7711 /**
7712 * igb_io_error_detected - called when PCI error is detected
7713 * @pdev: Pointer to PCI device
7714 * @state: The current pci connection state
7715 *
7716 * This function is called after a PCI bus error affecting
7717 * this device has been detected.
7718 **/
7719 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7720 pci_channel_state_t state)
7721 {
7722 struct net_device *netdev = pci_get_drvdata(pdev);
7723 struct igb_adapter *adapter = netdev_priv(netdev);
7724
7725 netif_device_detach(netdev);
7726
7727 if (state == pci_channel_io_perm_failure)
7728 return PCI_ERS_RESULT_DISCONNECT;
7729
7730 if (netif_running(netdev))
7731 igb_down(adapter);
7732 pci_disable_device(pdev);
7733
7734 /* Request a slot slot reset. */
7735 return PCI_ERS_RESULT_NEED_RESET;
7736 }
7737
7738 /**
7739 * igb_io_slot_reset - called after the pci bus has been reset.
7740 * @pdev: Pointer to PCI device
7741 *
7742 * Restart the card from scratch, as if from a cold-boot. Implementation
7743 * resembles the first-half of the igb_resume routine.
7744 **/
7745 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7746 {
7747 struct net_device *netdev = pci_get_drvdata(pdev);
7748 struct igb_adapter *adapter = netdev_priv(netdev);
7749 struct e1000_hw *hw = &adapter->hw;
7750 pci_ers_result_t result;
7751 int err;
7752
7753 if (pci_enable_device_mem(pdev)) {
7754 dev_err(&pdev->dev,
7755 "Cannot re-enable PCI device after reset.\n");
7756 result = PCI_ERS_RESULT_DISCONNECT;
7757 } else {
7758 pci_set_master(pdev);
7759 pci_restore_state(pdev);
7760 pci_save_state(pdev);
7761
7762 pci_enable_wake(pdev, PCI_D3hot, 0);
7763 pci_enable_wake(pdev, PCI_D3cold, 0);
7764
7765 igb_reset(adapter);
7766 wr32(E1000_WUS, ~0);
7767 result = PCI_ERS_RESULT_RECOVERED;
7768 }
7769
7770 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7771 if (err) {
7772 dev_err(&pdev->dev,
7773 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7774 err);
7775 /* non-fatal, continue */
7776 }
7777
7778 return result;
7779 }
7780
7781 /**
7782 * igb_io_resume - called when traffic can start flowing again.
7783 * @pdev: Pointer to PCI device
7784 *
7785 * This callback is called when the error recovery driver tells us that
7786 * its OK to resume normal operation. Implementation resembles the
7787 * second-half of the igb_resume routine.
7788 */
7789 static void igb_io_resume(struct pci_dev *pdev)
7790 {
7791 struct net_device *netdev = pci_get_drvdata(pdev);
7792 struct igb_adapter *adapter = netdev_priv(netdev);
7793
7794 if (netif_running(netdev)) {
7795 if (igb_up(adapter)) {
7796 dev_err(&pdev->dev, "igb_up failed after reset\n");
7797 return;
7798 }
7799 }
7800
7801 netif_device_attach(netdev);
7802
7803 /* let the f/w know that the h/w is now under the control of the
7804 * driver.
7805 */
7806 igb_get_hw_control(adapter);
7807 }
7808
7809 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7810 u8 qsel)
7811 {
7812 struct e1000_hw *hw = &adapter->hw;
7813 u32 rar_low, rar_high;
7814
7815 /* HW expects these in little endian so we reverse the byte order
7816 * from network order (big endian) to CPU endian
7817 */
7818 rar_low = le32_to_cpup((__be32 *)(addr));
7819 rar_high = le16_to_cpup((__be16 *)(addr + 4));
7820
7821 /* Indicate to hardware the Address is Valid. */
7822 rar_high |= E1000_RAH_AV;
7823
7824 if (hw->mac.type == e1000_82575)
7825 rar_high |= E1000_RAH_POOL_1 * qsel;
7826 else
7827 rar_high |= E1000_RAH_POOL_1 << qsel;
7828
7829 wr32(E1000_RAL(index), rar_low);
7830 wrfl();
7831 wr32(E1000_RAH(index), rar_high);
7832 wrfl();
7833 }
7834
7835 static int igb_set_vf_mac(struct igb_adapter *adapter,
7836 int vf, unsigned char *mac_addr)
7837 {
7838 struct e1000_hw *hw = &adapter->hw;
7839 /* VF MAC addresses start at end of receive addresses and moves
7840 * towards the first, as a result a collision should not be possible
7841 */
7842 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7843
7844 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7845
7846 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7847
7848 return 0;
7849 }
7850
7851 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7852 {
7853 struct igb_adapter *adapter = netdev_priv(netdev);
7854 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7855 return -EINVAL;
7856 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7857 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7858 dev_info(&adapter->pdev->dev,
7859 "Reload the VF driver to make this change effective.");
7860 if (test_bit(__IGB_DOWN, &adapter->state)) {
7861 dev_warn(&adapter->pdev->dev,
7862 "The VF MAC address has been set, but the PF device is not up.\n");
7863 dev_warn(&adapter->pdev->dev,
7864 "Bring the PF device up before attempting to use the VF device.\n");
7865 }
7866 return igb_set_vf_mac(adapter, vf, mac);
7867 }
7868
7869 static int igb_link_mbps(int internal_link_speed)
7870 {
7871 switch (internal_link_speed) {
7872 case SPEED_100:
7873 return 100;
7874 case SPEED_1000:
7875 return 1000;
7876 default:
7877 return 0;
7878 }
7879 }
7880
7881 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7882 int link_speed)
7883 {
7884 int rf_dec, rf_int;
7885 u32 bcnrc_val;
7886
7887 if (tx_rate != 0) {
7888 /* Calculate the rate factor values to set */
7889 rf_int = link_speed / tx_rate;
7890 rf_dec = (link_speed - (rf_int * tx_rate));
7891 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7892 tx_rate;
7893
7894 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7895 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7896 E1000_RTTBCNRC_RF_INT_MASK);
7897 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7898 } else {
7899 bcnrc_val = 0;
7900 }
7901
7902 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7903 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7904 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7905 */
7906 wr32(E1000_RTTBCNRM, 0x14);
7907 wr32(E1000_RTTBCNRC, bcnrc_val);
7908 }
7909
7910 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7911 {
7912 int actual_link_speed, i;
7913 bool reset_rate = false;
7914
7915 /* VF TX rate limit was not set or not supported */
7916 if ((adapter->vf_rate_link_speed == 0) ||
7917 (adapter->hw.mac.type != e1000_82576))
7918 return;
7919
7920 actual_link_speed = igb_link_mbps(adapter->link_speed);
7921 if (actual_link_speed != adapter->vf_rate_link_speed) {
7922 reset_rate = true;
7923 adapter->vf_rate_link_speed = 0;
7924 dev_info(&adapter->pdev->dev,
7925 "Link speed has been changed. VF Transmit rate is disabled\n");
7926 }
7927
7928 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7929 if (reset_rate)
7930 adapter->vf_data[i].tx_rate = 0;
7931
7932 igb_set_vf_rate_limit(&adapter->hw, i,
7933 adapter->vf_data[i].tx_rate,
7934 actual_link_speed);
7935 }
7936 }
7937
7938 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7939 int min_tx_rate, int max_tx_rate)
7940 {
7941 struct igb_adapter *adapter = netdev_priv(netdev);
7942 struct e1000_hw *hw = &adapter->hw;
7943 int actual_link_speed;
7944
7945 if (hw->mac.type != e1000_82576)
7946 return -EOPNOTSUPP;
7947
7948 if (min_tx_rate)
7949 return -EINVAL;
7950
7951 actual_link_speed = igb_link_mbps(adapter->link_speed);
7952 if ((vf >= adapter->vfs_allocated_count) ||
7953 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7954 (max_tx_rate < 0) ||
7955 (max_tx_rate > actual_link_speed))
7956 return -EINVAL;
7957
7958 adapter->vf_rate_link_speed = actual_link_speed;
7959 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7960 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7961
7962 return 0;
7963 }
7964
7965 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7966 bool setting)
7967 {
7968 struct igb_adapter *adapter = netdev_priv(netdev);
7969 struct e1000_hw *hw = &adapter->hw;
7970 u32 reg_val, reg_offset;
7971
7972 if (!adapter->vfs_allocated_count)
7973 return -EOPNOTSUPP;
7974
7975 if (vf >= adapter->vfs_allocated_count)
7976 return -EINVAL;
7977
7978 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7979 reg_val = rd32(reg_offset);
7980 if (setting)
7981 reg_val |= ((1 << vf) |
7982 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7983 else
7984 reg_val &= ~((1 << vf) |
7985 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7986 wr32(reg_offset, reg_val);
7987
7988 adapter->vf_data[vf].spoofchk_enabled = setting;
7989 return 0;
7990 }
7991
7992 static int igb_ndo_get_vf_config(struct net_device *netdev,
7993 int vf, struct ifla_vf_info *ivi)
7994 {
7995 struct igb_adapter *adapter = netdev_priv(netdev);
7996 if (vf >= adapter->vfs_allocated_count)
7997 return -EINVAL;
7998 ivi->vf = vf;
7999 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
8000 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8001 ivi->min_tx_rate = 0;
8002 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8003 ivi->qos = adapter->vf_data[vf].pf_qos;
8004 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8005 return 0;
8006 }
8007
8008 static void igb_vmm_control(struct igb_adapter *adapter)
8009 {
8010 struct e1000_hw *hw = &adapter->hw;
8011 u32 reg;
8012
8013 switch (hw->mac.type) {
8014 case e1000_82575:
8015 case e1000_i210:
8016 case e1000_i211:
8017 case e1000_i354:
8018 default:
8019 /* replication is not supported for 82575 */
8020 return;
8021 case e1000_82576:
8022 /* notify HW that the MAC is adding vlan tags */
8023 reg = rd32(E1000_DTXCTL);
8024 reg |= E1000_DTXCTL_VLAN_ADDED;
8025 wr32(E1000_DTXCTL, reg);
8026 /* Fall through */
8027 case e1000_82580:
8028 /* enable replication vlan tag stripping */
8029 reg = rd32(E1000_RPLOLR);
8030 reg |= E1000_RPLOLR_STRVLAN;
8031 wr32(E1000_RPLOLR, reg);
8032 /* Fall through */
8033 case e1000_i350:
8034 /* none of the above registers are supported by i350 */
8035 break;
8036 }
8037
8038 if (adapter->vfs_allocated_count) {
8039 igb_vmdq_set_loopback_pf(hw, true);
8040 igb_vmdq_set_replication_pf(hw, true);
8041 igb_vmdq_set_anti_spoofing_pf(hw, true,
8042 adapter->vfs_allocated_count);
8043 } else {
8044 igb_vmdq_set_loopback_pf(hw, false);
8045 igb_vmdq_set_replication_pf(hw, false);
8046 }
8047 }
8048
8049 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8050 {
8051 struct e1000_hw *hw = &adapter->hw;
8052 u32 dmac_thr;
8053 u16 hwm;
8054
8055 if (hw->mac.type > e1000_82580) {
8056 if (adapter->flags & IGB_FLAG_DMAC) {
8057 u32 reg;
8058
8059 /* force threshold to 0. */
8060 wr32(E1000_DMCTXTH, 0);
8061
8062 /* DMA Coalescing high water mark needs to be greater
8063 * than the Rx threshold. Set hwm to PBA - max frame
8064 * size in 16B units, capping it at PBA - 6KB.
8065 */
8066 hwm = 64 * (pba - 6);
8067 reg = rd32(E1000_FCRTC);
8068 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8069 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8070 & E1000_FCRTC_RTH_COAL_MASK);
8071 wr32(E1000_FCRTC, reg);
8072
8073 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
8074 * frame size, capping it at PBA - 10KB.
8075 */
8076 dmac_thr = pba - 10;
8077 reg = rd32(E1000_DMACR);
8078 reg &= ~E1000_DMACR_DMACTHR_MASK;
8079 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8080 & E1000_DMACR_DMACTHR_MASK);
8081
8082 /* transition to L0x or L1 if available..*/
8083 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8084
8085 /* watchdog timer= +-1000 usec in 32usec intervals */
8086 reg |= (1000 >> 5);
8087
8088 /* Disable BMC-to-OS Watchdog Enable */
8089 if (hw->mac.type != e1000_i354)
8090 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8091
8092 wr32(E1000_DMACR, reg);
8093
8094 /* no lower threshold to disable
8095 * coalescing(smart fifb)-UTRESH=0
8096 */
8097 wr32(E1000_DMCRTRH, 0);
8098
8099 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8100
8101 wr32(E1000_DMCTLX, reg);
8102
8103 /* free space in tx packet buffer to wake from
8104 * DMA coal
8105 */
8106 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8107 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8108
8109 /* make low power state decision controlled
8110 * by DMA coal
8111 */
8112 reg = rd32(E1000_PCIEMISC);
8113 reg &= ~E1000_PCIEMISC_LX_DECISION;
8114 wr32(E1000_PCIEMISC, reg);
8115 } /* endif adapter->dmac is not disabled */
8116 } else if (hw->mac.type == e1000_82580) {
8117 u32 reg = rd32(E1000_PCIEMISC);
8118
8119 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8120 wr32(E1000_DMACR, 0);
8121 }
8122 }
8123
8124 /**
8125 * igb_read_i2c_byte - Reads 8 bit word over I2C
8126 * @hw: pointer to hardware structure
8127 * @byte_offset: byte offset to read
8128 * @dev_addr: device address
8129 * @data: value read
8130 *
8131 * Performs byte read operation over I2C interface at
8132 * a specified device address.
8133 **/
8134 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8135 u8 dev_addr, u8 *data)
8136 {
8137 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8138 struct i2c_client *this_client = adapter->i2c_client;
8139 s32 status;
8140 u16 swfw_mask = 0;
8141
8142 if (!this_client)
8143 return E1000_ERR_I2C;
8144
8145 swfw_mask = E1000_SWFW_PHY0_SM;
8146
8147 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8148 return E1000_ERR_SWFW_SYNC;
8149
8150 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8151 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8152
8153 if (status < 0)
8154 return E1000_ERR_I2C;
8155 else {
8156 *data = status;
8157 return 0;
8158 }
8159 }
8160
8161 /**
8162 * igb_write_i2c_byte - Writes 8 bit word over I2C
8163 * @hw: pointer to hardware structure
8164 * @byte_offset: byte offset to write
8165 * @dev_addr: device address
8166 * @data: value to write
8167 *
8168 * Performs byte write operation over I2C interface at
8169 * a specified device address.
8170 **/
8171 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8172 u8 dev_addr, u8 data)
8173 {
8174 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8175 struct i2c_client *this_client = adapter->i2c_client;
8176 s32 status;
8177 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8178
8179 if (!this_client)
8180 return E1000_ERR_I2C;
8181
8182 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8183 return E1000_ERR_SWFW_SYNC;
8184 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8185 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8186
8187 if (status)
8188 return E1000_ERR_I2C;
8189 else
8190 return 0;
8191
8192 }
8193
8194 int igb_reinit_queues(struct igb_adapter *adapter)
8195 {
8196 struct net_device *netdev = adapter->netdev;
8197 struct pci_dev *pdev = adapter->pdev;
8198 int err = 0;
8199
8200 if (netif_running(netdev))
8201 igb_close(netdev);
8202
8203 igb_reset_interrupt_capability(adapter);
8204
8205 if (igb_init_interrupt_scheme(adapter, true)) {
8206 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8207 return -ENOMEM;
8208 }
8209
8210 if (netif_running(netdev))
8211 err = igb_open(netdev);
8212
8213 return err;
8214 }
8215 /* igb_main.c */
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