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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/init.h>
33 #include <linux/bitops.h>
34 #include <linux/vmalloc.h>
35 #include <linux/pagemap.h>
36 #include <linux/netdevice.h>
37 #include <linux/ipv6.h>
38 #include <linux/slab.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/mii.h>
43 #include <linux/ethtool.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/pci.h>
47 #include <linux/pci-aspm.h>
48 #include <linux/delay.h>
49 #include <linux/interrupt.h>
50 #include <linux/ip.h>
51 #include <linux/tcp.h>
52 #include <linux/sctp.h>
53 #include <linux/if_ether.h>
54 #include <linux/aer.h>
55 #include <linux/prefetch.h>
56 #include <linux/pm_runtime.h>
57 #ifdef CONFIG_IGB_DCA
58 #include <linux/dca.h>
59 #endif
60 #include "igb.h"
61
62 #define MAJ 4
63 #define MIN 0
64 #define BUILD 17
65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
66 __stringify(BUILD) "-k"
67 char igb_driver_name[] = "igb";
68 char igb_driver_version[] = DRV_VERSION;
69 static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
71 static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
72
73 static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75 };
76
77 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110 };
111
112 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114 void igb_reset(struct igb_adapter *);
115 static int igb_setup_all_tx_resources(struct igb_adapter *);
116 static int igb_setup_all_rx_resources(struct igb_adapter *);
117 static void igb_free_all_tx_resources(struct igb_adapter *);
118 static void igb_free_all_rx_resources(struct igb_adapter *);
119 static void igb_setup_mrqc(struct igb_adapter *);
120 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
121 static void __devexit igb_remove(struct pci_dev *pdev);
122 static int igb_sw_init(struct igb_adapter *);
123 static int igb_open(struct net_device *);
124 static int igb_close(struct net_device *);
125 static void igb_configure_tx(struct igb_adapter *);
126 static void igb_configure_rx(struct igb_adapter *);
127 static void igb_clean_all_tx_rings(struct igb_adapter *);
128 static void igb_clean_all_rx_rings(struct igb_adapter *);
129 static void igb_clean_tx_ring(struct igb_ring *);
130 static void igb_clean_rx_ring(struct igb_ring *);
131 static void igb_set_rx_mode(struct net_device *);
132 static void igb_update_phy_info(unsigned long);
133 static void igb_watchdog(unsigned long);
134 static void igb_watchdog_task(struct work_struct *);
135 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
136 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
137 struct rtnl_link_stats64 *stats);
138 static int igb_change_mtu(struct net_device *, int);
139 static int igb_set_mac(struct net_device *, void *);
140 static void igb_set_uta(struct igb_adapter *adapter);
141 static irqreturn_t igb_intr(int irq, void *);
142 static irqreturn_t igb_intr_msi(int irq, void *);
143 static irqreturn_t igb_msix_other(int irq, void *);
144 static irqreturn_t igb_msix_ring(int irq, void *);
145 #ifdef CONFIG_IGB_DCA
146 static void igb_update_dca(struct igb_q_vector *);
147 static void igb_setup_dca(struct igb_adapter *);
148 #endif /* CONFIG_IGB_DCA */
149 static int igb_poll(struct napi_struct *, int);
150 static bool igb_clean_tx_irq(struct igb_q_vector *);
151 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
152 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
153 static void igb_tx_timeout(struct net_device *);
154 static void igb_reset_task(struct work_struct *);
155 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
156 static int igb_vlan_rx_add_vid(struct net_device *, u16);
157 static int igb_vlan_rx_kill_vid(struct net_device *, u16);
158 static void igb_restore_vlan(struct igb_adapter *);
159 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
160 static void igb_ping_all_vfs(struct igb_adapter *);
161 static void igb_msg_task(struct igb_adapter *);
162 static void igb_vmm_control(struct igb_adapter *);
163 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
164 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
165 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
166 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
167 int vf, u16 vlan, u8 qos);
168 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
169 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
170 struct ifla_vf_info *ivi);
171 static void igb_check_vf_rate_limit(struct igb_adapter *);
172
173 #ifdef CONFIG_PCI_IOV
174 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
175 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
176 #endif
177
178 #ifdef CONFIG_PM
179 #ifdef CONFIG_PM_SLEEP
180 static int igb_suspend(struct device *);
181 #endif
182 static int igb_resume(struct device *);
183 #ifdef CONFIG_PM_RUNTIME
184 static int igb_runtime_suspend(struct device *dev);
185 static int igb_runtime_resume(struct device *dev);
186 static int igb_runtime_idle(struct device *dev);
187 #endif
188 static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 igb_runtime_idle)
192 };
193 #endif
194 static void igb_shutdown(struct pci_dev *);
195 #ifdef CONFIG_IGB_DCA
196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197 static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201 };
202 #endif
203 #ifdef CONFIG_NET_POLL_CONTROLLER
204 /* for netdump / net console */
205 static void igb_netpoll(struct net_device *);
206 #endif
207 #ifdef CONFIG_PCI_IOV
208 static unsigned int max_vfs = 0;
209 module_param(max_vfs, uint, 0);
210 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
211 "per physical function");
212 #endif /* CONFIG_PCI_IOV */
213
214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
215 pci_channel_state_t);
216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
217 static void igb_io_resume(struct pci_dev *);
218
219 static const struct pci_error_handlers igb_err_handler = {
220 .error_detected = igb_io_error_detected,
221 .slot_reset = igb_io_slot_reset,
222 .resume = igb_io_resume,
223 };
224
225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
226
227 static struct pci_driver igb_driver = {
228 .name = igb_driver_name,
229 .id_table = igb_pci_tbl,
230 .probe = igb_probe,
231 .remove = __devexit_p(igb_remove),
232 #ifdef CONFIG_PM
233 .driver.pm = &igb_pm_ops,
234 #endif
235 .shutdown = igb_shutdown,
236 .err_handler = &igb_err_handler
237 };
238
239 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
240 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
241 MODULE_LICENSE("GPL");
242 MODULE_VERSION(DRV_VERSION);
243
244 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
245 static int debug = -1;
246 module_param(debug, int, 0);
247 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
248
249 struct igb_reg_info {
250 u32 ofs;
251 char *name;
252 };
253
254 static const struct igb_reg_info igb_reg_info_tbl[] = {
255
256 /* General Registers */
257 {E1000_CTRL, "CTRL"},
258 {E1000_STATUS, "STATUS"},
259 {E1000_CTRL_EXT, "CTRL_EXT"},
260
261 /* Interrupt Registers */
262 {E1000_ICR, "ICR"},
263
264 /* RX Registers */
265 {E1000_RCTL, "RCTL"},
266 {E1000_RDLEN(0), "RDLEN"},
267 {E1000_RDH(0), "RDH"},
268 {E1000_RDT(0), "RDT"},
269 {E1000_RXDCTL(0), "RXDCTL"},
270 {E1000_RDBAL(0), "RDBAL"},
271 {E1000_RDBAH(0), "RDBAH"},
272
273 /* TX Registers */
274 {E1000_TCTL, "TCTL"},
275 {E1000_TDBAL(0), "TDBAL"},
276 {E1000_TDBAH(0), "TDBAH"},
277 {E1000_TDLEN(0), "TDLEN"},
278 {E1000_TDH(0), "TDH"},
279 {E1000_TDT(0), "TDT"},
280 {E1000_TXDCTL(0), "TXDCTL"},
281 {E1000_TDFH, "TDFH"},
282 {E1000_TDFT, "TDFT"},
283 {E1000_TDFHS, "TDFHS"},
284 {E1000_TDFPC, "TDFPC"},
285
286 /* List Terminator */
287 {}
288 };
289
290 /*
291 * igb_regdump - register printout routine
292 */
293 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
294 {
295 int n = 0;
296 char rname[16];
297 u32 regs[8];
298
299 switch (reginfo->ofs) {
300 case E1000_RDLEN(0):
301 for (n = 0; n < 4; n++)
302 regs[n] = rd32(E1000_RDLEN(n));
303 break;
304 case E1000_RDH(0):
305 for (n = 0; n < 4; n++)
306 regs[n] = rd32(E1000_RDH(n));
307 break;
308 case E1000_RDT(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_RDT(n));
311 break;
312 case E1000_RXDCTL(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_RXDCTL(n));
315 break;
316 case E1000_RDBAL(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_RDBAL(n));
319 break;
320 case E1000_RDBAH(0):
321 for (n = 0; n < 4; n++)
322 regs[n] = rd32(E1000_RDBAH(n));
323 break;
324 case E1000_TDBAL(0):
325 for (n = 0; n < 4; n++)
326 regs[n] = rd32(E1000_RDBAL(n));
327 break;
328 case E1000_TDBAH(0):
329 for (n = 0; n < 4; n++)
330 regs[n] = rd32(E1000_TDBAH(n));
331 break;
332 case E1000_TDLEN(0):
333 for (n = 0; n < 4; n++)
334 regs[n] = rd32(E1000_TDLEN(n));
335 break;
336 case E1000_TDH(0):
337 for (n = 0; n < 4; n++)
338 regs[n] = rd32(E1000_TDH(n));
339 break;
340 case E1000_TDT(0):
341 for (n = 0; n < 4; n++)
342 regs[n] = rd32(E1000_TDT(n));
343 break;
344 case E1000_TXDCTL(0):
345 for (n = 0; n < 4; n++)
346 regs[n] = rd32(E1000_TXDCTL(n));
347 break;
348 default:
349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
350 return;
351 }
352
353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
355 regs[2], regs[3]);
356 }
357
358 /*
359 * igb_dump - Print registers, tx-rings and rx-rings
360 */
361 static void igb_dump(struct igb_adapter *adapter)
362 {
363 struct net_device *netdev = adapter->netdev;
364 struct e1000_hw *hw = &adapter->hw;
365 struct igb_reg_info *reginfo;
366 struct igb_ring *tx_ring;
367 union e1000_adv_tx_desc *tx_desc;
368 struct my_u0 { u64 a; u64 b; } *u0;
369 struct igb_ring *rx_ring;
370 union e1000_adv_rx_desc *rx_desc;
371 u32 staterr;
372 u16 i, n;
373
374 if (!netif_msg_hw(adapter))
375 return;
376
377 /* Print netdevice Info */
378 if (netdev) {
379 dev_info(&adapter->pdev->dev, "Net device Info\n");
380 pr_info("Device Name state trans_start "
381 "last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
388 pr_info(" Register Name Value\n");
389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
400 for (n = 0; n < adapter->num_tx_queues; n++) {
401 struct igb_tx_buffer *buffer_info;
402 tx_ring = adapter->tx_ring[n];
403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
435 "[bi->dma ] leng ntw timestamp "
436 "bi->skb\n");
437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX"
455 " %04X %p %016llX %p%s\n", i,
456 le64_to_cpu(u0->a),
457 le64_to_cpu(u0->b),
458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
462 buffer_info->skb, next_desc);
463
464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
467 16, 1, buffer_info->skb->data,
468 dma_unmap_len(buffer_info, len),
469 true);
470 }
471 }
472
473 /* Print RX Rings Summary */
474 rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
476 pr_info("Queue [NTU] [NTC]\n");
477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
519
520 for (i = 0; i < rx_ring->count; i++) {
521 const char *next_desc;
522 struct igb_rx_buffer *buffer_info;
523 buffer_info = &rx_ring->rx_buffer_info[i];
524 rx_desc = IGB_RX_DESC(rx_ring, i);
525 u0 = (struct my_u0 *)rx_desc;
526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
527
528 if (i == rx_ring->next_to_use)
529 next_desc = " NTU";
530 else if (i == rx_ring->next_to_clean)
531 next_desc = " NTC";
532 else
533 next_desc = "";
534
535 if (staterr & E1000_RXD_STAT_DD) {
536 /* Descriptor Done */
537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
538 "RWB", i,
539 le64_to_cpu(u0->a),
540 le64_to_cpu(u0->b),
541 next_desc);
542 } else {
543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
544 "R ", i,
545 le64_to_cpu(u0->a),
546 le64_to_cpu(u0->b),
547 (u64)buffer_info->dma,
548 next_desc);
549
550 if (netif_msg_pktdata(adapter) &&
551 buffer_info->dma && buffer_info->page) {
552 print_hex_dump(KERN_INFO, "",
553 DUMP_PREFIX_ADDRESS,
554 16, 1,
555 page_address(buffer_info->page) +
556 buffer_info->page_offset,
557 IGB_RX_BUFSZ, true);
558 }
559 }
560 }
561 }
562
563 exit:
564 return;
565 }
566
567 /**
568 * igb_get_hw_dev - return device
569 * used by hardware layer to print debugging information
570 **/
571 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
572 {
573 struct igb_adapter *adapter = hw->back;
574 return adapter->netdev;
575 }
576
577 /**
578 * igb_init_module - Driver Registration Routine
579 *
580 * igb_init_module is the first routine called when the driver is
581 * loaded. All it does is register with the PCI subsystem.
582 **/
583 static int __init igb_init_module(void)
584 {
585 int ret;
586 pr_info("%s - version %s\n",
587 igb_driver_string, igb_driver_version);
588
589 pr_info("%s\n", igb_copyright);
590
591 #ifdef CONFIG_IGB_DCA
592 dca_register_notify(&dca_notifier);
593 #endif
594 ret = pci_register_driver(&igb_driver);
595 return ret;
596 }
597
598 module_init(igb_init_module);
599
600 /**
601 * igb_exit_module - Driver Exit Cleanup Routine
602 *
603 * igb_exit_module is called just before the driver is removed
604 * from memory.
605 **/
606 static void __exit igb_exit_module(void)
607 {
608 #ifdef CONFIG_IGB_DCA
609 dca_unregister_notify(&dca_notifier);
610 #endif
611 pci_unregister_driver(&igb_driver);
612 }
613
614 module_exit(igb_exit_module);
615
616 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
617 /**
618 * igb_cache_ring_register - Descriptor ring to register mapping
619 * @adapter: board private structure to initialize
620 *
621 * Once we know the feature-set enabled for the device, we'll cache
622 * the register offset the descriptor ring is assigned to.
623 **/
624 static void igb_cache_ring_register(struct igb_adapter *adapter)
625 {
626 int i = 0, j = 0;
627 u32 rbase_offset = adapter->vfs_allocated_count;
628
629 switch (adapter->hw.mac.type) {
630 case e1000_82576:
631 /* The queues are allocated for virtualization such that VF 0
632 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
633 * In order to avoid collision we start at the first free queue
634 * and continue consuming queues in the same sequence
635 */
636 if (adapter->vfs_allocated_count) {
637 for (; i < adapter->rss_queues; i++)
638 adapter->rx_ring[i]->reg_idx = rbase_offset +
639 Q_IDX_82576(i);
640 }
641 case e1000_82575:
642 case e1000_82580:
643 case e1000_i350:
644 case e1000_i210:
645 case e1000_i211:
646 default:
647 for (; i < adapter->num_rx_queues; i++)
648 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
649 for (; j < adapter->num_tx_queues; j++)
650 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
651 break;
652 }
653 }
654
655 /**
656 * igb_write_ivar - configure ivar for given MSI-X vector
657 * @hw: pointer to the HW structure
658 * @msix_vector: vector number we are allocating to a given ring
659 * @index: row index of IVAR register to write within IVAR table
660 * @offset: column offset of in IVAR, should be multiple of 8
661 *
662 * This function is intended to handle the writing of the IVAR register
663 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
664 * each containing an cause allocation for an Rx and Tx ring, and a
665 * variable number of rows depending on the number of queues supported.
666 **/
667 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
668 int index, int offset)
669 {
670 u32 ivar = array_rd32(E1000_IVAR0, index);
671
672 /* clear any bits that are currently set */
673 ivar &= ~((u32)0xFF << offset);
674
675 /* write vector and valid bit */
676 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
677
678 array_wr32(E1000_IVAR0, index, ivar);
679 }
680
681 #define IGB_N0_QUEUE -1
682 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
683 {
684 struct igb_adapter *adapter = q_vector->adapter;
685 struct e1000_hw *hw = &adapter->hw;
686 int rx_queue = IGB_N0_QUEUE;
687 int tx_queue = IGB_N0_QUEUE;
688 u32 msixbm = 0;
689
690 if (q_vector->rx.ring)
691 rx_queue = q_vector->rx.ring->reg_idx;
692 if (q_vector->tx.ring)
693 tx_queue = q_vector->tx.ring->reg_idx;
694
695 switch (hw->mac.type) {
696 case e1000_82575:
697 /* The 82575 assigns vectors using a bitmask, which matches the
698 bitmask for the EICR/EIMS/EIMC registers. To assign one
699 or more queues to a vector, we write the appropriate bits
700 into the MSIXBM register for that vector. */
701 if (rx_queue > IGB_N0_QUEUE)
702 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
703 if (tx_queue > IGB_N0_QUEUE)
704 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
705 if (!adapter->msix_entries && msix_vector == 0)
706 msixbm |= E1000_EIMS_OTHER;
707 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
708 q_vector->eims_value = msixbm;
709 break;
710 case e1000_82576:
711 /*
712 * 82576 uses a table that essentially consists of 2 columns
713 * with 8 rows. The ordering is column-major so we use the
714 * lower 3 bits as the row index, and the 4th bit as the
715 * column offset.
716 */
717 if (rx_queue > IGB_N0_QUEUE)
718 igb_write_ivar(hw, msix_vector,
719 rx_queue & 0x7,
720 (rx_queue & 0x8) << 1);
721 if (tx_queue > IGB_N0_QUEUE)
722 igb_write_ivar(hw, msix_vector,
723 tx_queue & 0x7,
724 ((tx_queue & 0x8) << 1) + 8);
725 q_vector->eims_value = 1 << msix_vector;
726 break;
727 case e1000_82580:
728 case e1000_i350:
729 case e1000_i210:
730 case e1000_i211:
731 /*
732 * On 82580 and newer adapters the scheme is similar to 82576
733 * however instead of ordering column-major we have things
734 * ordered row-major. So we traverse the table by using
735 * bit 0 as the column offset, and the remaining bits as the
736 * row index.
737 */
738 if (rx_queue > IGB_N0_QUEUE)
739 igb_write_ivar(hw, msix_vector,
740 rx_queue >> 1,
741 (rx_queue & 0x1) << 4);
742 if (tx_queue > IGB_N0_QUEUE)
743 igb_write_ivar(hw, msix_vector,
744 tx_queue >> 1,
745 ((tx_queue & 0x1) << 4) + 8);
746 q_vector->eims_value = 1 << msix_vector;
747 break;
748 default:
749 BUG();
750 break;
751 }
752
753 /* add q_vector eims value to global eims_enable_mask */
754 adapter->eims_enable_mask |= q_vector->eims_value;
755
756 /* configure q_vector to set itr on first interrupt */
757 q_vector->set_itr = 1;
758 }
759
760 /**
761 * igb_configure_msix - Configure MSI-X hardware
762 *
763 * igb_configure_msix sets up the hardware to properly
764 * generate MSI-X interrupts.
765 **/
766 static void igb_configure_msix(struct igb_adapter *adapter)
767 {
768 u32 tmp;
769 int i, vector = 0;
770 struct e1000_hw *hw = &adapter->hw;
771
772 adapter->eims_enable_mask = 0;
773
774 /* set vector for other causes, i.e. link changes */
775 switch (hw->mac.type) {
776 case e1000_82575:
777 tmp = rd32(E1000_CTRL_EXT);
778 /* enable MSI-X PBA support*/
779 tmp |= E1000_CTRL_EXT_PBA_CLR;
780
781 /* Auto-Mask interrupts upon ICR read. */
782 tmp |= E1000_CTRL_EXT_EIAME;
783 tmp |= E1000_CTRL_EXT_IRCA;
784
785 wr32(E1000_CTRL_EXT, tmp);
786
787 /* enable msix_other interrupt */
788 array_wr32(E1000_MSIXBM(0), vector++,
789 E1000_EIMS_OTHER);
790 adapter->eims_other = E1000_EIMS_OTHER;
791
792 break;
793
794 case e1000_82576:
795 case e1000_82580:
796 case e1000_i350:
797 case e1000_i210:
798 case e1000_i211:
799 /* Turn on MSI-X capability first, or our settings
800 * won't stick. And it will take days to debug. */
801 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
802 E1000_GPIE_PBA | E1000_GPIE_EIAME |
803 E1000_GPIE_NSICR);
804
805 /* enable msix_other interrupt */
806 adapter->eims_other = 1 << vector;
807 tmp = (vector++ | E1000_IVAR_VALID) << 8;
808
809 wr32(E1000_IVAR_MISC, tmp);
810 break;
811 default:
812 /* do nothing, since nothing else supports MSI-X */
813 break;
814 } /* switch (hw->mac.type) */
815
816 adapter->eims_enable_mask |= adapter->eims_other;
817
818 for (i = 0; i < adapter->num_q_vectors; i++)
819 igb_assign_vector(adapter->q_vector[i], vector++);
820
821 wrfl();
822 }
823
824 /**
825 * igb_request_msix - Initialize MSI-X interrupts
826 *
827 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
828 * kernel.
829 **/
830 static int igb_request_msix(struct igb_adapter *adapter)
831 {
832 struct net_device *netdev = adapter->netdev;
833 struct e1000_hw *hw = &adapter->hw;
834 int i, err = 0, vector = 0;
835
836 err = request_irq(adapter->msix_entries[vector].vector,
837 igb_msix_other, 0, netdev->name, adapter);
838 if (err)
839 goto out;
840 vector++;
841
842 for (i = 0; i < adapter->num_q_vectors; i++) {
843 struct igb_q_vector *q_vector = adapter->q_vector[i];
844
845 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
846
847 if (q_vector->rx.ring && q_vector->tx.ring)
848 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
849 q_vector->rx.ring->queue_index);
850 else if (q_vector->tx.ring)
851 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
852 q_vector->tx.ring->queue_index);
853 else if (q_vector->rx.ring)
854 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
855 q_vector->rx.ring->queue_index);
856 else
857 sprintf(q_vector->name, "%s-unused", netdev->name);
858
859 err = request_irq(adapter->msix_entries[vector].vector,
860 igb_msix_ring, 0, q_vector->name,
861 q_vector);
862 if (err)
863 goto out;
864 vector++;
865 }
866
867 igb_configure_msix(adapter);
868 return 0;
869 out:
870 return err;
871 }
872
873 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
874 {
875 if (adapter->msix_entries) {
876 pci_disable_msix(adapter->pdev);
877 kfree(adapter->msix_entries);
878 adapter->msix_entries = NULL;
879 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
880 pci_disable_msi(adapter->pdev);
881 }
882 }
883
884 /**
885 * igb_free_q_vector - Free memory allocated for specific interrupt vector
886 * @adapter: board private structure to initialize
887 * @v_idx: Index of vector to be freed
888 *
889 * This function frees the memory allocated to the q_vector. In addition if
890 * NAPI is enabled it will delete any references to the NAPI struct prior
891 * to freeing the q_vector.
892 **/
893 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
894 {
895 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
896
897 if (q_vector->tx.ring)
898 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
899
900 if (q_vector->rx.ring)
901 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
902
903 adapter->q_vector[v_idx] = NULL;
904 netif_napi_del(&q_vector->napi);
905
906 /*
907 * ixgbe_get_stats64() might access the rings on this vector,
908 * we must wait a grace period before freeing it.
909 */
910 kfree_rcu(q_vector, rcu);
911 }
912
913 /**
914 * igb_free_q_vectors - Free memory allocated for interrupt vectors
915 * @adapter: board private structure to initialize
916 *
917 * This function frees the memory allocated to the q_vectors. In addition if
918 * NAPI is enabled it will delete any references to the NAPI struct prior
919 * to freeing the q_vector.
920 **/
921 static void igb_free_q_vectors(struct igb_adapter *adapter)
922 {
923 int v_idx = adapter->num_q_vectors;
924
925 adapter->num_tx_queues = 0;
926 adapter->num_rx_queues = 0;
927 adapter->num_q_vectors = 0;
928
929 while (v_idx--)
930 igb_free_q_vector(adapter, v_idx);
931 }
932
933 /**
934 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
935 *
936 * This function resets the device so that it has 0 rx queues, tx queues, and
937 * MSI-X interrupts allocated.
938 */
939 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
940 {
941 igb_free_q_vectors(adapter);
942 igb_reset_interrupt_capability(adapter);
943 }
944
945 /**
946 * igb_set_interrupt_capability - set MSI or MSI-X if supported
947 *
948 * Attempt to configure interrupts using the best available
949 * capabilities of the hardware and kernel.
950 **/
951 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
952 {
953 int err;
954 int numvecs, i;
955
956 /* Number of supported queues. */
957 adapter->num_rx_queues = adapter->rss_queues;
958 if (adapter->vfs_allocated_count)
959 adapter->num_tx_queues = 1;
960 else
961 adapter->num_tx_queues = adapter->rss_queues;
962
963 /* start with one vector for every rx queue */
964 numvecs = adapter->num_rx_queues;
965
966 /* if tx handler is separate add 1 for every tx queue */
967 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
968 numvecs += adapter->num_tx_queues;
969
970 /* store the number of vectors reserved for queues */
971 adapter->num_q_vectors = numvecs;
972
973 /* add 1 vector for link status interrupts */
974 numvecs++;
975 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
976 GFP_KERNEL);
977
978 if (!adapter->msix_entries)
979 goto msi_only;
980
981 for (i = 0; i < numvecs; i++)
982 adapter->msix_entries[i].entry = i;
983
984 err = pci_enable_msix(adapter->pdev,
985 adapter->msix_entries,
986 numvecs);
987 if (err == 0)
988 return;
989
990 igb_reset_interrupt_capability(adapter);
991
992 /* If we can't do MSI-X, try MSI */
993 msi_only:
994 #ifdef CONFIG_PCI_IOV
995 /* disable SR-IOV for non MSI-X configurations */
996 if (adapter->vf_data) {
997 struct e1000_hw *hw = &adapter->hw;
998 /* disable iov and allow time for transactions to clear */
999 pci_disable_sriov(adapter->pdev);
1000 msleep(500);
1001
1002 kfree(adapter->vf_data);
1003 adapter->vf_data = NULL;
1004 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1005 wrfl();
1006 msleep(100);
1007 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1008 }
1009 #endif
1010 adapter->vfs_allocated_count = 0;
1011 adapter->rss_queues = 1;
1012 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1013 adapter->num_rx_queues = 1;
1014 adapter->num_tx_queues = 1;
1015 adapter->num_q_vectors = 1;
1016 if (!pci_enable_msi(adapter->pdev))
1017 adapter->flags |= IGB_FLAG_HAS_MSI;
1018 }
1019
1020 static void igb_add_ring(struct igb_ring *ring,
1021 struct igb_ring_container *head)
1022 {
1023 head->ring = ring;
1024 head->count++;
1025 }
1026
1027 /**
1028 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1029 * @adapter: board private structure to initialize
1030 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1031 * @v_idx: index of vector in adapter struct
1032 * @txr_count: total number of Tx rings to allocate
1033 * @txr_idx: index of first Tx ring to allocate
1034 * @rxr_count: total number of Rx rings to allocate
1035 * @rxr_idx: index of first Rx ring to allocate
1036 *
1037 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1038 **/
1039 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1040 int v_count, int v_idx,
1041 int txr_count, int txr_idx,
1042 int rxr_count, int rxr_idx)
1043 {
1044 struct igb_q_vector *q_vector;
1045 struct igb_ring *ring;
1046 int ring_count, size;
1047
1048 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1049 if (txr_count > 1 || rxr_count > 1)
1050 return -ENOMEM;
1051
1052 ring_count = txr_count + rxr_count;
1053 size = sizeof(struct igb_q_vector) +
1054 (sizeof(struct igb_ring) * ring_count);
1055
1056 /* allocate q_vector and rings */
1057 q_vector = kzalloc(size, GFP_KERNEL);
1058 if (!q_vector)
1059 return -ENOMEM;
1060
1061 /* initialize NAPI */
1062 netif_napi_add(adapter->netdev, &q_vector->napi,
1063 igb_poll, 64);
1064
1065 /* tie q_vector and adapter together */
1066 adapter->q_vector[v_idx] = q_vector;
1067 q_vector->adapter = adapter;
1068
1069 /* initialize work limits */
1070 q_vector->tx.work_limit = adapter->tx_work_limit;
1071
1072 /* initialize ITR configuration */
1073 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1074 q_vector->itr_val = IGB_START_ITR;
1075
1076 /* initialize pointer to rings */
1077 ring = q_vector->ring;
1078
1079 if (txr_count) {
1080 /* assign generic ring traits */
1081 ring->dev = &adapter->pdev->dev;
1082 ring->netdev = adapter->netdev;
1083
1084 /* configure backlink on ring */
1085 ring->q_vector = q_vector;
1086
1087 /* update q_vector Tx values */
1088 igb_add_ring(ring, &q_vector->tx);
1089
1090 /* For 82575, context index must be unique per ring. */
1091 if (adapter->hw.mac.type == e1000_82575)
1092 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1093
1094 /* apply Tx specific ring traits */
1095 ring->count = adapter->tx_ring_count;
1096 ring->queue_index = txr_idx;
1097
1098 /* assign ring to adapter */
1099 adapter->tx_ring[txr_idx] = ring;
1100
1101 /* push pointer to next ring */
1102 ring++;
1103 }
1104
1105 if (rxr_count) {
1106 /* assign generic ring traits */
1107 ring->dev = &adapter->pdev->dev;
1108 ring->netdev = adapter->netdev;
1109
1110 /* configure backlink on ring */
1111 ring->q_vector = q_vector;
1112
1113 /* update q_vector Rx values */
1114 igb_add_ring(ring, &q_vector->rx);
1115
1116 /* set flag indicating ring supports SCTP checksum offload */
1117 if (adapter->hw.mac.type >= e1000_82576)
1118 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1119
1120 /*
1121 * On i350, i210, and i211, loopback VLAN packets
1122 * have the tag byte-swapped.
1123 * */
1124 if (adapter->hw.mac.type >= e1000_i350)
1125 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1126
1127 /* apply Rx specific ring traits */
1128 ring->count = adapter->rx_ring_count;
1129 ring->queue_index = rxr_idx;
1130
1131 /* assign ring to adapter */
1132 adapter->rx_ring[rxr_idx] = ring;
1133 }
1134
1135 return 0;
1136 }
1137
1138
1139 /**
1140 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1141 * @adapter: board private structure to initialize
1142 *
1143 * We allocate one q_vector per queue interrupt. If allocation fails we
1144 * return -ENOMEM.
1145 **/
1146 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1147 {
1148 int q_vectors = adapter->num_q_vectors;
1149 int rxr_remaining = adapter->num_rx_queues;
1150 int txr_remaining = adapter->num_tx_queues;
1151 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1152 int err;
1153
1154 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1155 for (; rxr_remaining; v_idx++) {
1156 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1157 0, 0, 1, rxr_idx);
1158
1159 if (err)
1160 goto err_out;
1161
1162 /* update counts and index */
1163 rxr_remaining--;
1164 rxr_idx++;
1165 }
1166 }
1167
1168 for (; v_idx < q_vectors; v_idx++) {
1169 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1170 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1171 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1172 tqpv, txr_idx, rqpv, rxr_idx);
1173
1174 if (err)
1175 goto err_out;
1176
1177 /* update counts and index */
1178 rxr_remaining -= rqpv;
1179 txr_remaining -= tqpv;
1180 rxr_idx++;
1181 txr_idx++;
1182 }
1183
1184 return 0;
1185
1186 err_out:
1187 adapter->num_tx_queues = 0;
1188 adapter->num_rx_queues = 0;
1189 adapter->num_q_vectors = 0;
1190
1191 while (v_idx--)
1192 igb_free_q_vector(adapter, v_idx);
1193
1194 return -ENOMEM;
1195 }
1196
1197 /**
1198 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1199 *
1200 * This function initializes the interrupts and allocates all of the queues.
1201 **/
1202 static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1203 {
1204 struct pci_dev *pdev = adapter->pdev;
1205 int err;
1206
1207 igb_set_interrupt_capability(adapter);
1208
1209 err = igb_alloc_q_vectors(adapter);
1210 if (err) {
1211 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1212 goto err_alloc_q_vectors;
1213 }
1214
1215 igb_cache_ring_register(adapter);
1216
1217 return 0;
1218
1219 err_alloc_q_vectors:
1220 igb_reset_interrupt_capability(adapter);
1221 return err;
1222 }
1223
1224 /**
1225 * igb_request_irq - initialize interrupts
1226 *
1227 * Attempts to configure interrupts using the best available
1228 * capabilities of the hardware and kernel.
1229 **/
1230 static int igb_request_irq(struct igb_adapter *adapter)
1231 {
1232 struct net_device *netdev = adapter->netdev;
1233 struct pci_dev *pdev = adapter->pdev;
1234 int err = 0;
1235
1236 if (adapter->msix_entries) {
1237 err = igb_request_msix(adapter);
1238 if (!err)
1239 goto request_done;
1240 /* fall back to MSI */
1241 igb_free_all_tx_resources(adapter);
1242 igb_free_all_rx_resources(adapter);
1243 igb_clear_interrupt_scheme(adapter);
1244 if (!pci_enable_msi(pdev))
1245 adapter->flags |= IGB_FLAG_HAS_MSI;
1246 adapter->num_tx_queues = 1;
1247 adapter->num_rx_queues = 1;
1248 adapter->num_q_vectors = 1;
1249 err = igb_alloc_q_vectors(adapter);
1250 if (err) {
1251 dev_err(&pdev->dev,
1252 "Unable to allocate memory for vectors\n");
1253 goto request_done;
1254 }
1255 igb_setup_all_tx_resources(adapter);
1256 igb_setup_all_rx_resources(adapter);
1257 }
1258
1259 igb_assign_vector(adapter->q_vector[0], 0);
1260
1261 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1262 err = request_irq(pdev->irq, igb_intr_msi, 0,
1263 netdev->name, adapter);
1264 if (!err)
1265 goto request_done;
1266
1267 /* fall back to legacy interrupts */
1268 igb_reset_interrupt_capability(adapter);
1269 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1270 }
1271
1272 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1273 netdev->name, adapter);
1274
1275 if (err)
1276 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1277 err);
1278
1279 request_done:
1280 return err;
1281 }
1282
1283 static void igb_free_irq(struct igb_adapter *adapter)
1284 {
1285 if (adapter->msix_entries) {
1286 int vector = 0, i;
1287
1288 free_irq(adapter->msix_entries[vector++].vector, adapter);
1289
1290 for (i = 0; i < adapter->num_q_vectors; i++)
1291 free_irq(adapter->msix_entries[vector++].vector,
1292 adapter->q_vector[i]);
1293 } else {
1294 free_irq(adapter->pdev->irq, adapter);
1295 }
1296 }
1297
1298 /**
1299 * igb_irq_disable - Mask off interrupt generation on the NIC
1300 * @adapter: board private structure
1301 **/
1302 static void igb_irq_disable(struct igb_adapter *adapter)
1303 {
1304 struct e1000_hw *hw = &adapter->hw;
1305
1306 /*
1307 * we need to be careful when disabling interrupts. The VFs are also
1308 * mapped into these registers and so clearing the bits can cause
1309 * issues on the VF drivers so we only need to clear what we set
1310 */
1311 if (adapter->msix_entries) {
1312 u32 regval = rd32(E1000_EIAM);
1313 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1314 wr32(E1000_EIMC, adapter->eims_enable_mask);
1315 regval = rd32(E1000_EIAC);
1316 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1317 }
1318
1319 wr32(E1000_IAM, 0);
1320 wr32(E1000_IMC, ~0);
1321 wrfl();
1322 if (adapter->msix_entries) {
1323 int i;
1324 for (i = 0; i < adapter->num_q_vectors; i++)
1325 synchronize_irq(adapter->msix_entries[i].vector);
1326 } else {
1327 synchronize_irq(adapter->pdev->irq);
1328 }
1329 }
1330
1331 /**
1332 * igb_irq_enable - Enable default interrupt generation settings
1333 * @adapter: board private structure
1334 **/
1335 static void igb_irq_enable(struct igb_adapter *adapter)
1336 {
1337 struct e1000_hw *hw = &adapter->hw;
1338
1339 if (adapter->msix_entries) {
1340 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1341 u32 regval = rd32(E1000_EIAC);
1342 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1343 regval = rd32(E1000_EIAM);
1344 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1345 wr32(E1000_EIMS, adapter->eims_enable_mask);
1346 if (adapter->vfs_allocated_count) {
1347 wr32(E1000_MBVFIMR, 0xFF);
1348 ims |= E1000_IMS_VMMB;
1349 }
1350 wr32(E1000_IMS, ims);
1351 } else {
1352 wr32(E1000_IMS, IMS_ENABLE_MASK |
1353 E1000_IMS_DRSTA);
1354 wr32(E1000_IAM, IMS_ENABLE_MASK |
1355 E1000_IMS_DRSTA);
1356 }
1357 }
1358
1359 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1360 {
1361 struct e1000_hw *hw = &adapter->hw;
1362 u16 vid = adapter->hw.mng_cookie.vlan_id;
1363 u16 old_vid = adapter->mng_vlan_id;
1364
1365 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1366 /* add VID to filter table */
1367 igb_vfta_set(hw, vid, true);
1368 adapter->mng_vlan_id = vid;
1369 } else {
1370 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1371 }
1372
1373 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1374 (vid != old_vid) &&
1375 !test_bit(old_vid, adapter->active_vlans)) {
1376 /* remove VID from filter table */
1377 igb_vfta_set(hw, old_vid, false);
1378 }
1379 }
1380
1381 /**
1382 * igb_release_hw_control - release control of the h/w to f/w
1383 * @adapter: address of board private structure
1384 *
1385 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1386 * For ASF and Pass Through versions of f/w this means that the
1387 * driver is no longer loaded.
1388 *
1389 **/
1390 static void igb_release_hw_control(struct igb_adapter *adapter)
1391 {
1392 struct e1000_hw *hw = &adapter->hw;
1393 u32 ctrl_ext;
1394
1395 /* Let firmware take over control of h/w */
1396 ctrl_ext = rd32(E1000_CTRL_EXT);
1397 wr32(E1000_CTRL_EXT,
1398 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1399 }
1400
1401 /**
1402 * igb_get_hw_control - get control of the h/w from f/w
1403 * @adapter: address of board private structure
1404 *
1405 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1406 * For ASF and Pass Through versions of f/w this means that
1407 * the driver is loaded.
1408 *
1409 **/
1410 static void igb_get_hw_control(struct igb_adapter *adapter)
1411 {
1412 struct e1000_hw *hw = &adapter->hw;
1413 u32 ctrl_ext;
1414
1415 /* Let firmware know the driver has taken over */
1416 ctrl_ext = rd32(E1000_CTRL_EXT);
1417 wr32(E1000_CTRL_EXT,
1418 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1419 }
1420
1421 /**
1422 * igb_configure - configure the hardware for RX and TX
1423 * @adapter: private board structure
1424 **/
1425 static void igb_configure(struct igb_adapter *adapter)
1426 {
1427 struct net_device *netdev = adapter->netdev;
1428 int i;
1429
1430 igb_get_hw_control(adapter);
1431 igb_set_rx_mode(netdev);
1432
1433 igb_restore_vlan(adapter);
1434
1435 igb_setup_tctl(adapter);
1436 igb_setup_mrqc(adapter);
1437 igb_setup_rctl(adapter);
1438
1439 igb_configure_tx(adapter);
1440 igb_configure_rx(adapter);
1441
1442 igb_rx_fifo_flush_82575(&adapter->hw);
1443
1444 /* call igb_desc_unused which always leaves
1445 * at least 1 descriptor unused to make sure
1446 * next_to_use != next_to_clean */
1447 for (i = 0; i < adapter->num_rx_queues; i++) {
1448 struct igb_ring *ring = adapter->rx_ring[i];
1449 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1450 }
1451 }
1452
1453 /**
1454 * igb_power_up_link - Power up the phy/serdes link
1455 * @adapter: address of board private structure
1456 **/
1457 void igb_power_up_link(struct igb_adapter *adapter)
1458 {
1459 igb_reset_phy(&adapter->hw);
1460
1461 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462 igb_power_up_phy_copper(&adapter->hw);
1463 else
1464 igb_power_up_serdes_link_82575(&adapter->hw);
1465 }
1466
1467 /**
1468 * igb_power_down_link - Power down the phy/serdes link
1469 * @adapter: address of board private structure
1470 */
1471 static void igb_power_down_link(struct igb_adapter *adapter)
1472 {
1473 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1474 igb_power_down_phy_copper_82575(&adapter->hw);
1475 else
1476 igb_shutdown_serdes_link_82575(&adapter->hw);
1477 }
1478
1479 /**
1480 * igb_up - Open the interface and prepare it to handle traffic
1481 * @adapter: board private structure
1482 **/
1483 int igb_up(struct igb_adapter *adapter)
1484 {
1485 struct e1000_hw *hw = &adapter->hw;
1486 int i;
1487
1488 /* hardware has been reset, we need to reload some things */
1489 igb_configure(adapter);
1490
1491 clear_bit(__IGB_DOWN, &adapter->state);
1492
1493 for (i = 0; i < adapter->num_q_vectors; i++)
1494 napi_enable(&(adapter->q_vector[i]->napi));
1495
1496 if (adapter->msix_entries)
1497 igb_configure_msix(adapter);
1498 else
1499 igb_assign_vector(adapter->q_vector[0], 0);
1500
1501 /* Clear any pending interrupts. */
1502 rd32(E1000_ICR);
1503 igb_irq_enable(adapter);
1504
1505 /* notify VFs that reset has been completed */
1506 if (adapter->vfs_allocated_count) {
1507 u32 reg_data = rd32(E1000_CTRL_EXT);
1508 reg_data |= E1000_CTRL_EXT_PFRSTD;
1509 wr32(E1000_CTRL_EXT, reg_data);
1510 }
1511
1512 netif_tx_start_all_queues(adapter->netdev);
1513
1514 /* start the watchdog. */
1515 hw->mac.get_link_status = 1;
1516 schedule_work(&adapter->watchdog_task);
1517
1518 return 0;
1519 }
1520
1521 void igb_down(struct igb_adapter *adapter)
1522 {
1523 struct net_device *netdev = adapter->netdev;
1524 struct e1000_hw *hw = &adapter->hw;
1525 u32 tctl, rctl;
1526 int i;
1527
1528 /* signal that we're down so the interrupt handler does not
1529 * reschedule our watchdog timer */
1530 set_bit(__IGB_DOWN, &adapter->state);
1531
1532 /* disable receives in the hardware */
1533 rctl = rd32(E1000_RCTL);
1534 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1535 /* flush and sleep below */
1536
1537 netif_tx_stop_all_queues(netdev);
1538
1539 /* disable transmits in the hardware */
1540 tctl = rd32(E1000_TCTL);
1541 tctl &= ~E1000_TCTL_EN;
1542 wr32(E1000_TCTL, tctl);
1543 /* flush both disables and wait for them to finish */
1544 wrfl();
1545 msleep(10);
1546
1547 for (i = 0; i < adapter->num_q_vectors; i++)
1548 napi_disable(&(adapter->q_vector[i]->napi));
1549
1550 igb_irq_disable(adapter);
1551
1552 del_timer_sync(&adapter->watchdog_timer);
1553 del_timer_sync(&adapter->phy_info_timer);
1554
1555 netif_carrier_off(netdev);
1556
1557 /* record the stats before reset*/
1558 spin_lock(&adapter->stats64_lock);
1559 igb_update_stats(adapter, &adapter->stats64);
1560 spin_unlock(&adapter->stats64_lock);
1561
1562 adapter->link_speed = 0;
1563 adapter->link_duplex = 0;
1564
1565 if (!pci_channel_offline(adapter->pdev))
1566 igb_reset(adapter);
1567 igb_clean_all_tx_rings(adapter);
1568 igb_clean_all_rx_rings(adapter);
1569 #ifdef CONFIG_IGB_DCA
1570
1571 /* since we reset the hardware DCA settings were cleared */
1572 igb_setup_dca(adapter);
1573 #endif
1574 }
1575
1576 void igb_reinit_locked(struct igb_adapter *adapter)
1577 {
1578 WARN_ON(in_interrupt());
1579 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1580 msleep(1);
1581 igb_down(adapter);
1582 igb_up(adapter);
1583 clear_bit(__IGB_RESETTING, &adapter->state);
1584 }
1585
1586 void igb_reset(struct igb_adapter *adapter)
1587 {
1588 struct pci_dev *pdev = adapter->pdev;
1589 struct e1000_hw *hw = &adapter->hw;
1590 struct e1000_mac_info *mac = &hw->mac;
1591 struct e1000_fc_info *fc = &hw->fc;
1592 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1593 u16 hwm;
1594
1595 /* Repartition Pba for greater than 9k mtu
1596 * To take effect CTRL.RST is required.
1597 */
1598 switch (mac->type) {
1599 case e1000_i350:
1600 case e1000_82580:
1601 pba = rd32(E1000_RXPBS);
1602 pba = igb_rxpbs_adjust_82580(pba);
1603 break;
1604 case e1000_82576:
1605 pba = rd32(E1000_RXPBS);
1606 pba &= E1000_RXPBS_SIZE_MASK_82576;
1607 break;
1608 case e1000_82575:
1609 case e1000_i210:
1610 case e1000_i211:
1611 default:
1612 pba = E1000_PBA_34K;
1613 break;
1614 }
1615
1616 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1617 (mac->type < e1000_82576)) {
1618 /* adjust PBA for jumbo frames */
1619 wr32(E1000_PBA, pba);
1620
1621 /* To maintain wire speed transmits, the Tx FIFO should be
1622 * large enough to accommodate two full transmit packets,
1623 * rounded up to the next 1KB and expressed in KB. Likewise,
1624 * the Rx FIFO should be large enough to accommodate at least
1625 * one full receive packet and is similarly rounded up and
1626 * expressed in KB. */
1627 pba = rd32(E1000_PBA);
1628 /* upper 16 bits has Tx packet buffer allocation size in KB */
1629 tx_space = pba >> 16;
1630 /* lower 16 bits has Rx packet buffer allocation size in KB */
1631 pba &= 0xffff;
1632 /* the tx fifo also stores 16 bytes of information about the tx
1633 * but don't include ethernet FCS because hardware appends it */
1634 min_tx_space = (adapter->max_frame_size +
1635 sizeof(union e1000_adv_tx_desc) -
1636 ETH_FCS_LEN) * 2;
1637 min_tx_space = ALIGN(min_tx_space, 1024);
1638 min_tx_space >>= 10;
1639 /* software strips receive CRC, so leave room for it */
1640 min_rx_space = adapter->max_frame_size;
1641 min_rx_space = ALIGN(min_rx_space, 1024);
1642 min_rx_space >>= 10;
1643
1644 /* If current Tx allocation is less than the min Tx FIFO size,
1645 * and the min Tx FIFO size is less than the current Rx FIFO
1646 * allocation, take space away from current Rx allocation */
1647 if (tx_space < min_tx_space &&
1648 ((min_tx_space - tx_space) < pba)) {
1649 pba = pba - (min_tx_space - tx_space);
1650
1651 /* if short on rx space, rx wins and must trump tx
1652 * adjustment */
1653 if (pba < min_rx_space)
1654 pba = min_rx_space;
1655 }
1656 wr32(E1000_PBA, pba);
1657 }
1658
1659 /* flow control settings */
1660 /* The high water mark must be low enough to fit one full frame
1661 * (or the size used for early receive) above it in the Rx FIFO.
1662 * Set it to the lower of:
1663 * - 90% of the Rx FIFO size, or
1664 * - the full Rx FIFO size minus one full frame */
1665 hwm = min(((pba << 10) * 9 / 10),
1666 ((pba << 10) - 2 * adapter->max_frame_size));
1667
1668 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1669 fc->low_water = fc->high_water - 16;
1670 fc->pause_time = 0xFFFF;
1671 fc->send_xon = 1;
1672 fc->current_mode = fc->requested_mode;
1673
1674 /* disable receive for all VFs and wait one second */
1675 if (adapter->vfs_allocated_count) {
1676 int i;
1677 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1678 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1679
1680 /* ping all the active vfs to let them know we are going down */
1681 igb_ping_all_vfs(adapter);
1682
1683 /* disable transmits and receives */
1684 wr32(E1000_VFRE, 0);
1685 wr32(E1000_VFTE, 0);
1686 }
1687
1688 /* Allow time for pending master requests to run */
1689 hw->mac.ops.reset_hw(hw);
1690 wr32(E1000_WUC, 0);
1691
1692 if (hw->mac.ops.init_hw(hw))
1693 dev_err(&pdev->dev, "Hardware Error\n");
1694
1695 /*
1696 * Flow control settings reset on hardware reset, so guarantee flow
1697 * control is off when forcing speed.
1698 */
1699 if (!hw->mac.autoneg)
1700 igb_force_mac_fc(hw);
1701
1702 igb_init_dmac(adapter, pba);
1703 if (!netif_running(adapter->netdev))
1704 igb_power_down_link(adapter);
1705
1706 igb_update_mng_vlan(adapter);
1707
1708 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1709 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1710
1711 #ifdef CONFIG_IGB_PTP
1712 /* Re-enable PTP, where applicable. */
1713 igb_ptp_reset(adapter);
1714 #endif /* CONFIG_IGB_PTP */
1715
1716 igb_get_phy_info(hw);
1717 }
1718
1719 static netdev_features_t igb_fix_features(struct net_device *netdev,
1720 netdev_features_t features)
1721 {
1722 /*
1723 * Since there is no support for separate rx/tx vlan accel
1724 * enable/disable make sure tx flag is always in same state as rx.
1725 */
1726 if (features & NETIF_F_HW_VLAN_RX)
1727 features |= NETIF_F_HW_VLAN_TX;
1728 else
1729 features &= ~NETIF_F_HW_VLAN_TX;
1730
1731 return features;
1732 }
1733
1734 static int igb_set_features(struct net_device *netdev,
1735 netdev_features_t features)
1736 {
1737 netdev_features_t changed = netdev->features ^ features;
1738 struct igb_adapter *adapter = netdev_priv(netdev);
1739
1740 if (changed & NETIF_F_HW_VLAN_RX)
1741 igb_vlan_mode(netdev, features);
1742
1743 if (!(changed & NETIF_F_RXALL))
1744 return 0;
1745
1746 netdev->features = features;
1747
1748 if (netif_running(netdev))
1749 igb_reinit_locked(adapter);
1750 else
1751 igb_reset(adapter);
1752
1753 return 0;
1754 }
1755
1756 static const struct net_device_ops igb_netdev_ops = {
1757 .ndo_open = igb_open,
1758 .ndo_stop = igb_close,
1759 .ndo_start_xmit = igb_xmit_frame,
1760 .ndo_get_stats64 = igb_get_stats64,
1761 .ndo_set_rx_mode = igb_set_rx_mode,
1762 .ndo_set_mac_address = igb_set_mac,
1763 .ndo_change_mtu = igb_change_mtu,
1764 .ndo_do_ioctl = igb_ioctl,
1765 .ndo_tx_timeout = igb_tx_timeout,
1766 .ndo_validate_addr = eth_validate_addr,
1767 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1768 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1769 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1770 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1771 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1772 .ndo_get_vf_config = igb_ndo_get_vf_config,
1773 #ifdef CONFIG_NET_POLL_CONTROLLER
1774 .ndo_poll_controller = igb_netpoll,
1775 #endif
1776 .ndo_fix_features = igb_fix_features,
1777 .ndo_set_features = igb_set_features,
1778 };
1779
1780 /**
1781 * igb_set_fw_version - Configure version string for ethtool
1782 * @adapter: adapter struct
1783 *
1784 **/
1785 void igb_set_fw_version(struct igb_adapter *adapter)
1786 {
1787 struct e1000_hw *hw = &adapter->hw;
1788 u16 eeprom_verh, eeprom_verl, comb_verh, comb_verl, comb_offset;
1789 u16 major, build, patch, fw_version;
1790 u32 etrack_id;
1791
1792 hw->nvm.ops.read(hw, 5, 1, &fw_version);
1793 if (adapter->hw.mac.type != e1000_i211) {
1794 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1795 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1796 etrack_id = (eeprom_verh << IGB_ETRACK_SHIFT) | eeprom_verl;
1797
1798 /* combo image version needs to be found */
1799 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1800 if ((comb_offset != 0x0) &&
1801 (comb_offset != IGB_NVM_VER_INVALID)) {
1802 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1803 + 1), 1, &comb_verh);
1804 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1805 1, &comb_verl);
1806
1807 /* Only display Option Rom if it exists and is valid */
1808 if ((comb_verh && comb_verl) &&
1809 ((comb_verh != IGB_NVM_VER_INVALID) &&
1810 (comb_verl != IGB_NVM_VER_INVALID))) {
1811 major = comb_verl >> IGB_COMB_VER_SHFT;
1812 build = (comb_verl << IGB_COMB_VER_SHFT) |
1813 (comb_verh >> IGB_COMB_VER_SHFT);
1814 patch = comb_verh & IGB_COMB_VER_MASK;
1815 snprintf(adapter->fw_version,
1816 sizeof(adapter->fw_version),
1817 "%d.%d%d, 0x%08x, %d.%d.%d",
1818 (fw_version & IGB_MAJOR_MASK) >>
1819 IGB_MAJOR_SHIFT,
1820 (fw_version & IGB_MINOR_MASK) >>
1821 IGB_MINOR_SHIFT,
1822 (fw_version & IGB_BUILD_MASK),
1823 etrack_id, major, build, patch);
1824 goto out;
1825 }
1826 }
1827 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1828 "%d.%d%d, 0x%08x",
1829 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT,
1830 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT,
1831 (fw_version & IGB_BUILD_MASK), etrack_id);
1832 } else {
1833 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1834 "%d.%d%d",
1835 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT,
1836 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT,
1837 (fw_version & IGB_BUILD_MASK));
1838 }
1839 out:
1840 return;
1841 }
1842
1843 /**
1844 * igb_probe - Device Initialization Routine
1845 * @pdev: PCI device information struct
1846 * @ent: entry in igb_pci_tbl
1847 *
1848 * Returns 0 on success, negative on failure
1849 *
1850 * igb_probe initializes an adapter identified by a pci_dev structure.
1851 * The OS initialization, configuring of the adapter private structure,
1852 * and a hardware reset occur.
1853 **/
1854 static int __devinit igb_probe(struct pci_dev *pdev,
1855 const struct pci_device_id *ent)
1856 {
1857 struct net_device *netdev;
1858 struct igb_adapter *adapter;
1859 struct e1000_hw *hw;
1860 u16 eeprom_data = 0;
1861 s32 ret_val;
1862 static int global_quad_port_a; /* global quad port a indication */
1863 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1864 unsigned long mmio_start, mmio_len;
1865 int err, pci_using_dac;
1866 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1867 u8 part_str[E1000_PBANUM_LENGTH];
1868
1869 /* Catch broken hardware that put the wrong VF device ID in
1870 * the PCIe SR-IOV capability.
1871 */
1872 if (pdev->is_virtfn) {
1873 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1874 pci_name(pdev), pdev->vendor, pdev->device);
1875 return -EINVAL;
1876 }
1877
1878 err = pci_enable_device_mem(pdev);
1879 if (err)
1880 return err;
1881
1882 pci_using_dac = 0;
1883 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1884 if (!err) {
1885 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1886 if (!err)
1887 pci_using_dac = 1;
1888 } else {
1889 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1890 if (err) {
1891 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1892 if (err) {
1893 dev_err(&pdev->dev, "No usable DMA "
1894 "configuration, aborting\n");
1895 goto err_dma;
1896 }
1897 }
1898 }
1899
1900 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1901 IORESOURCE_MEM),
1902 igb_driver_name);
1903 if (err)
1904 goto err_pci_reg;
1905
1906 pci_enable_pcie_error_reporting(pdev);
1907
1908 pci_set_master(pdev);
1909 pci_save_state(pdev);
1910
1911 err = -ENOMEM;
1912 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1913 IGB_MAX_TX_QUEUES);
1914 if (!netdev)
1915 goto err_alloc_etherdev;
1916
1917 SET_NETDEV_DEV(netdev, &pdev->dev);
1918
1919 pci_set_drvdata(pdev, netdev);
1920 adapter = netdev_priv(netdev);
1921 adapter->netdev = netdev;
1922 adapter->pdev = pdev;
1923 hw = &adapter->hw;
1924 hw->back = adapter;
1925 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1926
1927 mmio_start = pci_resource_start(pdev, 0);
1928 mmio_len = pci_resource_len(pdev, 0);
1929
1930 err = -EIO;
1931 hw->hw_addr = ioremap(mmio_start, mmio_len);
1932 if (!hw->hw_addr)
1933 goto err_ioremap;
1934
1935 netdev->netdev_ops = &igb_netdev_ops;
1936 igb_set_ethtool_ops(netdev);
1937 netdev->watchdog_timeo = 5 * HZ;
1938
1939 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1940
1941 netdev->mem_start = mmio_start;
1942 netdev->mem_end = mmio_start + mmio_len;
1943
1944 /* PCI config space info */
1945 hw->vendor_id = pdev->vendor;
1946 hw->device_id = pdev->device;
1947 hw->revision_id = pdev->revision;
1948 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1949 hw->subsystem_device_id = pdev->subsystem_device;
1950
1951 /* Copy the default MAC, PHY and NVM function pointers */
1952 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1953 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1954 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1955 /* Initialize skew-specific constants */
1956 err = ei->get_invariants(hw);
1957 if (err)
1958 goto err_sw_init;
1959
1960 /* setup the private structure */
1961 err = igb_sw_init(adapter);
1962 if (err)
1963 goto err_sw_init;
1964
1965 igb_get_bus_info_pcie(hw);
1966
1967 hw->phy.autoneg_wait_to_complete = false;
1968
1969 /* Copper options */
1970 if (hw->phy.media_type == e1000_media_type_copper) {
1971 hw->phy.mdix = AUTO_ALL_MODES;
1972 hw->phy.disable_polarity_correction = false;
1973 hw->phy.ms_type = e1000_ms_hw_default;
1974 }
1975
1976 if (igb_check_reset_block(hw))
1977 dev_info(&pdev->dev,
1978 "PHY reset is blocked due to SOL/IDER session.\n");
1979
1980 /*
1981 * features is initialized to 0 in allocation, it might have bits
1982 * set by igb_sw_init so we should use an or instead of an
1983 * assignment.
1984 */
1985 netdev->features |= NETIF_F_SG |
1986 NETIF_F_IP_CSUM |
1987 NETIF_F_IPV6_CSUM |
1988 NETIF_F_TSO |
1989 NETIF_F_TSO6 |
1990 NETIF_F_RXHASH |
1991 NETIF_F_RXCSUM |
1992 NETIF_F_HW_VLAN_RX |
1993 NETIF_F_HW_VLAN_TX;
1994
1995 /* copy netdev features into list of user selectable features */
1996 netdev->hw_features |= netdev->features;
1997 netdev->hw_features |= NETIF_F_RXALL;
1998
1999 /* set this bit last since it cannot be part of hw_features */
2000 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2001
2002 netdev->vlan_features |= NETIF_F_TSO |
2003 NETIF_F_TSO6 |
2004 NETIF_F_IP_CSUM |
2005 NETIF_F_IPV6_CSUM |
2006 NETIF_F_SG;
2007
2008 netdev->priv_flags |= IFF_SUPP_NOFCS;
2009
2010 if (pci_using_dac) {
2011 netdev->features |= NETIF_F_HIGHDMA;
2012 netdev->vlan_features |= NETIF_F_HIGHDMA;
2013 }
2014
2015 if (hw->mac.type >= e1000_82576) {
2016 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2017 netdev->features |= NETIF_F_SCTP_CSUM;
2018 }
2019
2020 netdev->priv_flags |= IFF_UNICAST_FLT;
2021
2022 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2023
2024 /* before reading the NVM, reset the controller to put the device in a
2025 * known good starting state */
2026 hw->mac.ops.reset_hw(hw);
2027
2028 /*
2029 * make sure the NVM is good , i211 parts have special NVM that
2030 * doesn't contain a checksum
2031 */
2032 if (hw->mac.type != e1000_i211) {
2033 if (hw->nvm.ops.validate(hw) < 0) {
2034 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2035 err = -EIO;
2036 goto err_eeprom;
2037 }
2038 }
2039
2040 /* copy the MAC address out of the NVM */
2041 if (hw->mac.ops.read_mac_addr(hw))
2042 dev_err(&pdev->dev, "NVM Read Error\n");
2043
2044 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2045 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2046
2047 if (!is_valid_ether_addr(netdev->perm_addr)) {
2048 dev_err(&pdev->dev, "Invalid MAC Address\n");
2049 err = -EIO;
2050 goto err_eeprom;
2051 }
2052
2053 /* get firmware version for ethtool -i */
2054 igb_set_fw_version(adapter);
2055
2056 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2057 (unsigned long) adapter);
2058 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2059 (unsigned long) adapter);
2060
2061 INIT_WORK(&adapter->reset_task, igb_reset_task);
2062 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2063
2064 /* Initialize link properties that are user-changeable */
2065 adapter->fc_autoneg = true;
2066 hw->mac.autoneg = true;
2067 hw->phy.autoneg_advertised = 0x2f;
2068
2069 hw->fc.requested_mode = e1000_fc_default;
2070 hw->fc.current_mode = e1000_fc_default;
2071
2072 igb_validate_mdi_setting(hw);
2073
2074 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2075 * enable the ACPI Magic Packet filter
2076 */
2077
2078 if (hw->bus.func == 0)
2079 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
2080 else if (hw->mac.type >= e1000_82580)
2081 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2082 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2083 &eeprom_data);
2084 else if (hw->bus.func == 1)
2085 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2086
2087 if (eeprom_data & eeprom_apme_mask)
2088 adapter->eeprom_wol |= E1000_WUFC_MAG;
2089
2090 /* now that we have the eeprom settings, apply the special cases where
2091 * the eeprom may be wrong or the board simply won't support wake on
2092 * lan on a particular port */
2093 switch (pdev->device) {
2094 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2095 adapter->eeprom_wol = 0;
2096 break;
2097 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2098 case E1000_DEV_ID_82576_FIBER:
2099 case E1000_DEV_ID_82576_SERDES:
2100 /* Wake events only supported on port A for dual fiber
2101 * regardless of eeprom setting */
2102 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2103 adapter->eeprom_wol = 0;
2104 break;
2105 case E1000_DEV_ID_82576_QUAD_COPPER:
2106 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2107 /* if quad port adapter, disable WoL on all but port A */
2108 if (global_quad_port_a != 0)
2109 adapter->eeprom_wol = 0;
2110 else
2111 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2112 /* Reset for multiple quad port adapters */
2113 if (++global_quad_port_a == 4)
2114 global_quad_port_a = 0;
2115 break;
2116 }
2117
2118 /* initialize the wol settings based on the eeprom settings */
2119 adapter->wol = adapter->eeprom_wol;
2120 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2121
2122 /* reset the hardware with the new settings */
2123 igb_reset(adapter);
2124
2125 /* let the f/w know that the h/w is now under the control of the
2126 * driver. */
2127 igb_get_hw_control(adapter);
2128
2129 strcpy(netdev->name, "eth%d");
2130 err = register_netdev(netdev);
2131 if (err)
2132 goto err_register;
2133
2134 /* carrier off reporting is important to ethtool even BEFORE open */
2135 netif_carrier_off(netdev);
2136
2137 #ifdef CONFIG_IGB_DCA
2138 if (dca_add_requester(&pdev->dev) == 0) {
2139 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2140 dev_info(&pdev->dev, "DCA enabled\n");
2141 igb_setup_dca(adapter);
2142 }
2143
2144 #endif
2145
2146 #ifdef CONFIG_IGB_PTP
2147 /* do hw tstamp init after resetting */
2148 igb_ptp_init(adapter);
2149 #endif /* CONFIG_IGB_PTP */
2150
2151 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2152 /* print bus type/speed/width info */
2153 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2154 netdev->name,
2155 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2156 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2157 "unknown"),
2158 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2159 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2160 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2161 "unknown"),
2162 netdev->dev_addr);
2163
2164 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2165 if (ret_val)
2166 strcpy(part_str, "Unknown");
2167 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2168 dev_info(&pdev->dev,
2169 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2170 adapter->msix_entries ? "MSI-X" :
2171 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2172 adapter->num_rx_queues, adapter->num_tx_queues);
2173 switch (hw->mac.type) {
2174 case e1000_i350:
2175 case e1000_i210:
2176 case e1000_i211:
2177 igb_set_eee_i350(hw);
2178 break;
2179 default:
2180 break;
2181 }
2182
2183 pm_runtime_put_noidle(&pdev->dev);
2184 return 0;
2185
2186 err_register:
2187 igb_release_hw_control(adapter);
2188 err_eeprom:
2189 if (!igb_check_reset_block(hw))
2190 igb_reset_phy(hw);
2191
2192 if (hw->flash_address)
2193 iounmap(hw->flash_address);
2194 err_sw_init:
2195 igb_clear_interrupt_scheme(adapter);
2196 iounmap(hw->hw_addr);
2197 err_ioremap:
2198 free_netdev(netdev);
2199 err_alloc_etherdev:
2200 pci_release_selected_regions(pdev,
2201 pci_select_bars(pdev, IORESOURCE_MEM));
2202 err_pci_reg:
2203 err_dma:
2204 pci_disable_device(pdev);
2205 return err;
2206 }
2207
2208 /**
2209 * igb_remove - Device Removal Routine
2210 * @pdev: PCI device information struct
2211 *
2212 * igb_remove is called by the PCI subsystem to alert the driver
2213 * that it should release a PCI device. The could be caused by a
2214 * Hot-Plug event, or because the driver is going to be removed from
2215 * memory.
2216 **/
2217 static void __devexit igb_remove(struct pci_dev *pdev)
2218 {
2219 struct net_device *netdev = pci_get_drvdata(pdev);
2220 struct igb_adapter *adapter = netdev_priv(netdev);
2221 struct e1000_hw *hw = &adapter->hw;
2222
2223 pm_runtime_get_noresume(&pdev->dev);
2224 #ifdef CONFIG_IGB_PTP
2225 igb_ptp_stop(adapter);
2226 #endif /* CONFIG_IGB_PTP */
2227
2228 /*
2229 * The watchdog timer may be rescheduled, so explicitly
2230 * disable watchdog from being rescheduled.
2231 */
2232 set_bit(__IGB_DOWN, &adapter->state);
2233 del_timer_sync(&adapter->watchdog_timer);
2234 del_timer_sync(&adapter->phy_info_timer);
2235
2236 cancel_work_sync(&adapter->reset_task);
2237 cancel_work_sync(&adapter->watchdog_task);
2238
2239 #ifdef CONFIG_IGB_DCA
2240 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2241 dev_info(&pdev->dev, "DCA disabled\n");
2242 dca_remove_requester(&pdev->dev);
2243 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2244 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2245 }
2246 #endif
2247
2248 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2249 * would have already happened in close and is redundant. */
2250 igb_release_hw_control(adapter);
2251
2252 unregister_netdev(netdev);
2253
2254 igb_clear_interrupt_scheme(adapter);
2255
2256 #ifdef CONFIG_PCI_IOV
2257 /* reclaim resources allocated to VFs */
2258 if (adapter->vf_data) {
2259 /* disable iov and allow time for transactions to clear */
2260 if (igb_vfs_are_assigned(adapter)) {
2261 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2262 } else {
2263 pci_disable_sriov(pdev);
2264 msleep(500);
2265 }
2266
2267 kfree(adapter->vf_data);
2268 adapter->vf_data = NULL;
2269 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2270 wrfl();
2271 msleep(100);
2272 dev_info(&pdev->dev, "IOV Disabled\n");
2273 }
2274 #endif
2275
2276 iounmap(hw->hw_addr);
2277 if (hw->flash_address)
2278 iounmap(hw->flash_address);
2279 pci_release_selected_regions(pdev,
2280 pci_select_bars(pdev, IORESOURCE_MEM));
2281
2282 kfree(adapter->shadow_vfta);
2283 free_netdev(netdev);
2284
2285 pci_disable_pcie_error_reporting(pdev);
2286
2287 pci_disable_device(pdev);
2288 }
2289
2290 /**
2291 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2292 * @adapter: board private structure to initialize
2293 *
2294 * This function initializes the vf specific data storage and then attempts to
2295 * allocate the VFs. The reason for ordering it this way is because it is much
2296 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2297 * the memory for the VFs.
2298 **/
2299 static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2300 {
2301 #ifdef CONFIG_PCI_IOV
2302 struct pci_dev *pdev = adapter->pdev;
2303 struct e1000_hw *hw = &adapter->hw;
2304 int old_vfs = pci_num_vf(adapter->pdev);
2305 int i;
2306
2307 /* Virtualization features not supported on i210 family. */
2308 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2309 return;
2310
2311 if (old_vfs) {
2312 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2313 "max_vfs setting of %d\n", old_vfs, max_vfs);
2314 adapter->vfs_allocated_count = old_vfs;
2315 }
2316
2317 if (!adapter->vfs_allocated_count)
2318 return;
2319
2320 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2321 sizeof(struct vf_data_storage), GFP_KERNEL);
2322
2323 /* if allocation failed then we do not support SR-IOV */
2324 if (!adapter->vf_data) {
2325 adapter->vfs_allocated_count = 0;
2326 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2327 "Data Storage\n");
2328 goto out;
2329 }
2330
2331 if (!old_vfs) {
2332 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2333 goto err_out;
2334 }
2335 dev_info(&pdev->dev, "%d VFs allocated\n",
2336 adapter->vfs_allocated_count);
2337 for (i = 0; i < adapter->vfs_allocated_count; i++)
2338 igb_vf_configure(adapter, i);
2339
2340 /* DMA Coalescing is not supported in IOV mode. */
2341 adapter->flags &= ~IGB_FLAG_DMAC;
2342 goto out;
2343 err_out:
2344 kfree(adapter->vf_data);
2345 adapter->vf_data = NULL;
2346 adapter->vfs_allocated_count = 0;
2347 out:
2348 return;
2349 #endif /* CONFIG_PCI_IOV */
2350 }
2351
2352 /**
2353 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2354 * @adapter: board private structure to initialize
2355 *
2356 * igb_sw_init initializes the Adapter private data structure.
2357 * Fields are initialized based on PCI device information and
2358 * OS network device settings (MTU size).
2359 **/
2360 static int __devinit igb_sw_init(struct igb_adapter *adapter)
2361 {
2362 struct e1000_hw *hw = &adapter->hw;
2363 struct net_device *netdev = adapter->netdev;
2364 struct pci_dev *pdev = adapter->pdev;
2365 u32 max_rss_queues;
2366
2367 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2368
2369 /* set default ring sizes */
2370 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2371 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2372
2373 /* set default ITR values */
2374 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2375 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2376
2377 /* set default work limits */
2378 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2379
2380 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2381 VLAN_HLEN;
2382 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2383
2384 spin_lock_init(&adapter->stats64_lock);
2385 #ifdef CONFIG_PCI_IOV
2386 switch (hw->mac.type) {
2387 case e1000_82576:
2388 case e1000_i350:
2389 if (max_vfs > 7) {
2390 dev_warn(&pdev->dev,
2391 "Maximum of 7 VFs per PF, using max\n");
2392 adapter->vfs_allocated_count = 7;
2393 } else
2394 adapter->vfs_allocated_count = max_vfs;
2395 break;
2396 default:
2397 break;
2398 }
2399 #endif /* CONFIG_PCI_IOV */
2400
2401 /* Determine the maximum number of RSS queues supported. */
2402 switch (hw->mac.type) {
2403 case e1000_i211:
2404 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2405 break;
2406 case e1000_82575:
2407 case e1000_i210:
2408 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2409 break;
2410 case e1000_i350:
2411 /* I350 cannot do RSS and SR-IOV at the same time */
2412 if (!!adapter->vfs_allocated_count) {
2413 max_rss_queues = 1;
2414 break;
2415 }
2416 /* fall through */
2417 case e1000_82576:
2418 if (!!adapter->vfs_allocated_count) {
2419 max_rss_queues = 2;
2420 break;
2421 }
2422 /* fall through */
2423 case e1000_82580:
2424 default:
2425 max_rss_queues = IGB_MAX_RX_QUEUES;
2426 break;
2427 }
2428
2429 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2430
2431 /* Determine if we need to pair queues. */
2432 switch (hw->mac.type) {
2433 case e1000_82575:
2434 case e1000_i211:
2435 /* Device supports enough interrupts without queue pairing. */
2436 break;
2437 case e1000_82576:
2438 /*
2439 * If VFs are going to be allocated with RSS queues then we
2440 * should pair the queues in order to conserve interrupts due
2441 * to limited supply.
2442 */
2443 if ((adapter->rss_queues > 1) &&
2444 (adapter->vfs_allocated_count > 6))
2445 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2446 /* fall through */
2447 case e1000_82580:
2448 case e1000_i350:
2449 case e1000_i210:
2450 default:
2451 /*
2452 * If rss_queues > half of max_rss_queues, pair the queues in
2453 * order to conserve interrupts due to limited supply.
2454 */
2455 if (adapter->rss_queues > (max_rss_queues / 2))
2456 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2457 break;
2458 }
2459
2460 /* Setup and initialize a copy of the hw vlan table array */
2461 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2462 E1000_VLAN_FILTER_TBL_SIZE,
2463 GFP_ATOMIC);
2464
2465 /* This call may decrease the number of queues */
2466 if (igb_init_interrupt_scheme(adapter)) {
2467 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2468 return -ENOMEM;
2469 }
2470
2471 igb_probe_vfs(adapter);
2472
2473 /* Explicitly disable IRQ since the NIC can be in any state. */
2474 igb_irq_disable(adapter);
2475
2476 if (hw->mac.type >= e1000_i350)
2477 adapter->flags &= ~IGB_FLAG_DMAC;
2478
2479 set_bit(__IGB_DOWN, &adapter->state);
2480 return 0;
2481 }
2482
2483 /**
2484 * igb_open - Called when a network interface is made active
2485 * @netdev: network interface device structure
2486 *
2487 * Returns 0 on success, negative value on failure
2488 *
2489 * The open entry point is called when a network interface is made
2490 * active by the system (IFF_UP). At this point all resources needed
2491 * for transmit and receive operations are allocated, the interrupt
2492 * handler is registered with the OS, the watchdog timer is started,
2493 * and the stack is notified that the interface is ready.
2494 **/
2495 static int __igb_open(struct net_device *netdev, bool resuming)
2496 {
2497 struct igb_adapter *adapter = netdev_priv(netdev);
2498 struct e1000_hw *hw = &adapter->hw;
2499 struct pci_dev *pdev = adapter->pdev;
2500 int err;
2501 int i;
2502
2503 /* disallow open during test */
2504 if (test_bit(__IGB_TESTING, &adapter->state)) {
2505 WARN_ON(resuming);
2506 return -EBUSY;
2507 }
2508
2509 if (!resuming)
2510 pm_runtime_get_sync(&pdev->dev);
2511
2512 netif_carrier_off(netdev);
2513
2514 /* allocate transmit descriptors */
2515 err = igb_setup_all_tx_resources(adapter);
2516 if (err)
2517 goto err_setup_tx;
2518
2519 /* allocate receive descriptors */
2520 err = igb_setup_all_rx_resources(adapter);
2521 if (err)
2522 goto err_setup_rx;
2523
2524 igb_power_up_link(adapter);
2525
2526 /* before we allocate an interrupt, we must be ready to handle it.
2527 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2528 * as soon as we call pci_request_irq, so we have to setup our
2529 * clean_rx handler before we do so. */
2530 igb_configure(adapter);
2531
2532 err = igb_request_irq(adapter);
2533 if (err)
2534 goto err_req_irq;
2535
2536 /* Notify the stack of the actual queue counts. */
2537 err = netif_set_real_num_tx_queues(adapter->netdev,
2538 adapter->num_tx_queues);
2539 if (err)
2540 goto err_set_queues;
2541
2542 err = netif_set_real_num_rx_queues(adapter->netdev,
2543 adapter->num_rx_queues);
2544 if (err)
2545 goto err_set_queues;
2546
2547 /* From here on the code is the same as igb_up() */
2548 clear_bit(__IGB_DOWN, &adapter->state);
2549
2550 for (i = 0; i < adapter->num_q_vectors; i++)
2551 napi_enable(&(adapter->q_vector[i]->napi));
2552
2553 /* Clear any pending interrupts. */
2554 rd32(E1000_ICR);
2555
2556 igb_irq_enable(adapter);
2557
2558 /* notify VFs that reset has been completed */
2559 if (adapter->vfs_allocated_count) {
2560 u32 reg_data = rd32(E1000_CTRL_EXT);
2561 reg_data |= E1000_CTRL_EXT_PFRSTD;
2562 wr32(E1000_CTRL_EXT, reg_data);
2563 }
2564
2565 netif_tx_start_all_queues(netdev);
2566
2567 if (!resuming)
2568 pm_runtime_put(&pdev->dev);
2569
2570 /* start the watchdog. */
2571 hw->mac.get_link_status = 1;
2572 schedule_work(&adapter->watchdog_task);
2573
2574 return 0;
2575
2576 err_set_queues:
2577 igb_free_irq(adapter);
2578 err_req_irq:
2579 igb_release_hw_control(adapter);
2580 igb_power_down_link(adapter);
2581 igb_free_all_rx_resources(adapter);
2582 err_setup_rx:
2583 igb_free_all_tx_resources(adapter);
2584 err_setup_tx:
2585 igb_reset(adapter);
2586 if (!resuming)
2587 pm_runtime_put(&pdev->dev);
2588
2589 return err;
2590 }
2591
2592 static int igb_open(struct net_device *netdev)
2593 {
2594 return __igb_open(netdev, false);
2595 }
2596
2597 /**
2598 * igb_close - Disables a network interface
2599 * @netdev: network interface device structure
2600 *
2601 * Returns 0, this is not allowed to fail
2602 *
2603 * The close entry point is called when an interface is de-activated
2604 * by the OS. The hardware is still under the driver's control, but
2605 * needs to be disabled. A global MAC reset is issued to stop the
2606 * hardware, and all transmit and receive resources are freed.
2607 **/
2608 static int __igb_close(struct net_device *netdev, bool suspending)
2609 {
2610 struct igb_adapter *adapter = netdev_priv(netdev);
2611 struct pci_dev *pdev = adapter->pdev;
2612
2613 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2614
2615 if (!suspending)
2616 pm_runtime_get_sync(&pdev->dev);
2617
2618 igb_down(adapter);
2619 igb_free_irq(adapter);
2620
2621 igb_free_all_tx_resources(adapter);
2622 igb_free_all_rx_resources(adapter);
2623
2624 if (!suspending)
2625 pm_runtime_put_sync(&pdev->dev);
2626 return 0;
2627 }
2628
2629 static int igb_close(struct net_device *netdev)
2630 {
2631 return __igb_close(netdev, false);
2632 }
2633
2634 /**
2635 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2636 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2637 *
2638 * Return 0 on success, negative on failure
2639 **/
2640 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2641 {
2642 struct device *dev = tx_ring->dev;
2643 int size;
2644
2645 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2646
2647 tx_ring->tx_buffer_info = vzalloc(size);
2648 if (!tx_ring->tx_buffer_info)
2649 goto err;
2650
2651 /* round up to nearest 4K */
2652 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2653 tx_ring->size = ALIGN(tx_ring->size, 4096);
2654
2655 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2656 &tx_ring->dma, GFP_KERNEL);
2657 if (!tx_ring->desc)
2658 goto err;
2659
2660 tx_ring->next_to_use = 0;
2661 tx_ring->next_to_clean = 0;
2662
2663 return 0;
2664
2665 err:
2666 vfree(tx_ring->tx_buffer_info);
2667 tx_ring->tx_buffer_info = NULL;
2668 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2669 return -ENOMEM;
2670 }
2671
2672 /**
2673 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2674 * (Descriptors) for all queues
2675 * @adapter: board private structure
2676 *
2677 * Return 0 on success, negative on failure
2678 **/
2679 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2680 {
2681 struct pci_dev *pdev = adapter->pdev;
2682 int i, err = 0;
2683
2684 for (i = 0; i < adapter->num_tx_queues; i++) {
2685 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2686 if (err) {
2687 dev_err(&pdev->dev,
2688 "Allocation for Tx Queue %u failed\n", i);
2689 for (i--; i >= 0; i--)
2690 igb_free_tx_resources(adapter->tx_ring[i]);
2691 break;
2692 }
2693 }
2694
2695 return err;
2696 }
2697
2698 /**
2699 * igb_setup_tctl - configure the transmit control registers
2700 * @adapter: Board private structure
2701 **/
2702 void igb_setup_tctl(struct igb_adapter *adapter)
2703 {
2704 struct e1000_hw *hw = &adapter->hw;
2705 u32 tctl;
2706
2707 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2708 wr32(E1000_TXDCTL(0), 0);
2709
2710 /* Program the Transmit Control Register */
2711 tctl = rd32(E1000_TCTL);
2712 tctl &= ~E1000_TCTL_CT;
2713 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2714 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2715
2716 igb_config_collision_dist(hw);
2717
2718 /* Enable transmits */
2719 tctl |= E1000_TCTL_EN;
2720
2721 wr32(E1000_TCTL, tctl);
2722 }
2723
2724 /**
2725 * igb_configure_tx_ring - Configure transmit ring after Reset
2726 * @adapter: board private structure
2727 * @ring: tx ring to configure
2728 *
2729 * Configure a transmit ring after a reset.
2730 **/
2731 void igb_configure_tx_ring(struct igb_adapter *adapter,
2732 struct igb_ring *ring)
2733 {
2734 struct e1000_hw *hw = &adapter->hw;
2735 u32 txdctl = 0;
2736 u64 tdba = ring->dma;
2737 int reg_idx = ring->reg_idx;
2738
2739 /* disable the queue */
2740 wr32(E1000_TXDCTL(reg_idx), 0);
2741 wrfl();
2742 mdelay(10);
2743
2744 wr32(E1000_TDLEN(reg_idx),
2745 ring->count * sizeof(union e1000_adv_tx_desc));
2746 wr32(E1000_TDBAL(reg_idx),
2747 tdba & 0x00000000ffffffffULL);
2748 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2749
2750 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2751 wr32(E1000_TDH(reg_idx), 0);
2752 writel(0, ring->tail);
2753
2754 txdctl |= IGB_TX_PTHRESH;
2755 txdctl |= IGB_TX_HTHRESH << 8;
2756 txdctl |= IGB_TX_WTHRESH << 16;
2757
2758 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2759 wr32(E1000_TXDCTL(reg_idx), txdctl);
2760 }
2761
2762 /**
2763 * igb_configure_tx - Configure transmit Unit after Reset
2764 * @adapter: board private structure
2765 *
2766 * Configure the Tx unit of the MAC after a reset.
2767 **/
2768 static void igb_configure_tx(struct igb_adapter *adapter)
2769 {
2770 int i;
2771
2772 for (i = 0; i < adapter->num_tx_queues; i++)
2773 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2774 }
2775
2776 /**
2777 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2778 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2779 *
2780 * Returns 0 on success, negative on failure
2781 **/
2782 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2783 {
2784 struct device *dev = rx_ring->dev;
2785 int size;
2786
2787 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2788
2789 rx_ring->rx_buffer_info = vzalloc(size);
2790 if (!rx_ring->rx_buffer_info)
2791 goto err;
2792
2793 /* Round up to nearest 4K */
2794 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
2795 rx_ring->size = ALIGN(rx_ring->size, 4096);
2796
2797 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2798 &rx_ring->dma, GFP_KERNEL);
2799 if (!rx_ring->desc)
2800 goto err;
2801
2802 rx_ring->next_to_alloc = 0;
2803 rx_ring->next_to_clean = 0;
2804 rx_ring->next_to_use = 0;
2805
2806 return 0;
2807
2808 err:
2809 vfree(rx_ring->rx_buffer_info);
2810 rx_ring->rx_buffer_info = NULL;
2811 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2812 return -ENOMEM;
2813 }
2814
2815 /**
2816 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2817 * (Descriptors) for all queues
2818 * @adapter: board private structure
2819 *
2820 * Return 0 on success, negative on failure
2821 **/
2822 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2823 {
2824 struct pci_dev *pdev = adapter->pdev;
2825 int i, err = 0;
2826
2827 for (i = 0; i < adapter->num_rx_queues; i++) {
2828 err = igb_setup_rx_resources(adapter->rx_ring[i]);
2829 if (err) {
2830 dev_err(&pdev->dev,
2831 "Allocation for Rx Queue %u failed\n", i);
2832 for (i--; i >= 0; i--)
2833 igb_free_rx_resources(adapter->rx_ring[i]);
2834 break;
2835 }
2836 }
2837
2838 return err;
2839 }
2840
2841 /**
2842 * igb_setup_mrqc - configure the multiple receive queue control registers
2843 * @adapter: Board private structure
2844 **/
2845 static void igb_setup_mrqc(struct igb_adapter *adapter)
2846 {
2847 struct e1000_hw *hw = &adapter->hw;
2848 u32 mrqc, rxcsum;
2849 u32 j, num_rx_queues, shift = 0;
2850 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2851 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2852 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2853 0xFA01ACBE };
2854
2855 /* Fill out hash function seeds */
2856 for (j = 0; j < 10; j++)
2857 wr32(E1000_RSSRK(j), rsskey[j]);
2858
2859 num_rx_queues = adapter->rss_queues;
2860
2861 switch (hw->mac.type) {
2862 case e1000_82575:
2863 shift = 6;
2864 break;
2865 case e1000_82576:
2866 /* 82576 supports 2 RSS queues for SR-IOV */
2867 if (adapter->vfs_allocated_count) {
2868 shift = 3;
2869 num_rx_queues = 2;
2870 }
2871 break;
2872 default:
2873 break;
2874 }
2875
2876 /*
2877 * Populate the indirection table 4 entries at a time. To do this
2878 * we are generating the results for n and n+2 and then interleaving
2879 * those with the results with n+1 and n+3.
2880 */
2881 for (j = 0; j < 32; j++) {
2882 /* first pass generates n and n+2 */
2883 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2884 u32 reta = (base & 0x07800780) >> (7 - shift);
2885
2886 /* second pass generates n+1 and n+3 */
2887 base += 0x00010001 * num_rx_queues;
2888 reta |= (base & 0x07800780) << (1 + shift);
2889
2890 wr32(E1000_RETA(j), reta);
2891 }
2892
2893 /*
2894 * Disable raw packet checksumming so that RSS hash is placed in
2895 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2896 * offloads as they are enabled by default
2897 */
2898 rxcsum = rd32(E1000_RXCSUM);
2899 rxcsum |= E1000_RXCSUM_PCSD;
2900
2901 if (adapter->hw.mac.type >= e1000_82576)
2902 /* Enable Receive Checksum Offload for SCTP */
2903 rxcsum |= E1000_RXCSUM_CRCOFL;
2904
2905 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2906 wr32(E1000_RXCSUM, rxcsum);
2907 /*
2908 * Generate RSS hash based on TCP port numbers and/or
2909 * IPv4/v6 src and dst addresses since UDP cannot be
2910 * hashed reliably due to IP fragmentation
2911 */
2912
2913 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2914 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2915 E1000_MRQC_RSS_FIELD_IPV6 |
2916 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2917 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2918
2919 /* If VMDq is enabled then we set the appropriate mode for that, else
2920 * we default to RSS so that an RSS hash is calculated per packet even
2921 * if we are only using one queue */
2922 if (adapter->vfs_allocated_count) {
2923 if (hw->mac.type > e1000_82575) {
2924 /* Set the default pool for the PF's first queue */
2925 u32 vtctl = rd32(E1000_VT_CTL);
2926 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2927 E1000_VT_CTL_DISABLE_DEF_POOL);
2928 vtctl |= adapter->vfs_allocated_count <<
2929 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2930 wr32(E1000_VT_CTL, vtctl);
2931 }
2932 if (adapter->rss_queues > 1)
2933 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2934 else
2935 mrqc |= E1000_MRQC_ENABLE_VMDQ;
2936 } else {
2937 if (hw->mac.type != e1000_i211)
2938 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
2939 }
2940 igb_vmm_control(adapter);
2941
2942 wr32(E1000_MRQC, mrqc);
2943 }
2944
2945 /**
2946 * igb_setup_rctl - configure the receive control registers
2947 * @adapter: Board private structure
2948 **/
2949 void igb_setup_rctl(struct igb_adapter *adapter)
2950 {
2951 struct e1000_hw *hw = &adapter->hw;
2952 u32 rctl;
2953
2954 rctl = rd32(E1000_RCTL);
2955
2956 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2957 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2958
2959 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2960 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2961
2962 /*
2963 * enable stripping of CRC. It's unlikely this will break BMC
2964 * redirection as it did with e1000. Newer features require
2965 * that the HW strips the CRC.
2966 */
2967 rctl |= E1000_RCTL_SECRC;
2968
2969 /* disable store bad packets and clear size bits. */
2970 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2971
2972 /* enable LPE to prevent packets larger than max_frame_size */
2973 rctl |= E1000_RCTL_LPE;
2974
2975 /* disable queue 0 to prevent tail write w/o re-config */
2976 wr32(E1000_RXDCTL(0), 0);
2977
2978 /* Attention!!! For SR-IOV PF driver operations you must enable
2979 * queue drop for all VF and PF queues to prevent head of line blocking
2980 * if an un-trusted VF does not provide descriptors to hardware.
2981 */
2982 if (adapter->vfs_allocated_count) {
2983 /* set all queue drop enable bits */
2984 wr32(E1000_QDE, ALL_QUEUES);
2985 }
2986
2987 /* This is useful for sniffing bad packets. */
2988 if (adapter->netdev->features & NETIF_F_RXALL) {
2989 /* UPE and MPE will be handled by normal PROMISC logic
2990 * in e1000e_set_rx_mode */
2991 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2992 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2993 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2994
2995 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2996 E1000_RCTL_DPF | /* Allow filtered pause */
2997 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2998 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2999 * and that breaks VLANs.
3000 */
3001 }
3002
3003 wr32(E1000_RCTL, rctl);
3004 }
3005
3006 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3007 int vfn)
3008 {
3009 struct e1000_hw *hw = &adapter->hw;
3010 u32 vmolr;
3011
3012 /* if it isn't the PF check to see if VFs are enabled and
3013 * increase the size to support vlan tags */
3014 if (vfn < adapter->vfs_allocated_count &&
3015 adapter->vf_data[vfn].vlans_enabled)
3016 size += VLAN_TAG_SIZE;
3017
3018 vmolr = rd32(E1000_VMOLR(vfn));
3019 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3020 vmolr |= size | E1000_VMOLR_LPE;
3021 wr32(E1000_VMOLR(vfn), vmolr);
3022
3023 return 0;
3024 }
3025
3026 /**
3027 * igb_rlpml_set - set maximum receive packet size
3028 * @adapter: board private structure
3029 *
3030 * Configure maximum receivable packet size.
3031 **/
3032 static void igb_rlpml_set(struct igb_adapter *adapter)
3033 {
3034 u32 max_frame_size = adapter->max_frame_size;
3035 struct e1000_hw *hw = &adapter->hw;
3036 u16 pf_id = adapter->vfs_allocated_count;
3037
3038 if (pf_id) {
3039 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3040 /*
3041 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3042 * to our max jumbo frame size, in case we need to enable
3043 * jumbo frames on one of the rings later.
3044 * This will not pass over-length frames into the default
3045 * queue because it's gated by the VMOLR.RLPML.
3046 */
3047 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3048 }
3049
3050 wr32(E1000_RLPML, max_frame_size);
3051 }
3052
3053 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3054 int vfn, bool aupe)
3055 {
3056 struct e1000_hw *hw = &adapter->hw;
3057 u32 vmolr;
3058
3059 /*
3060 * This register exists only on 82576 and newer so if we are older then
3061 * we should exit and do nothing
3062 */
3063 if (hw->mac.type < e1000_82576)
3064 return;
3065
3066 vmolr = rd32(E1000_VMOLR(vfn));
3067 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3068 if (aupe)
3069 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3070 else
3071 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3072
3073 /* clear all bits that might not be set */
3074 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3075
3076 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3077 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3078 /*
3079 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3080 * multicast packets
3081 */
3082 if (vfn <= adapter->vfs_allocated_count)
3083 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3084
3085 wr32(E1000_VMOLR(vfn), vmolr);
3086 }
3087
3088 /**
3089 * igb_configure_rx_ring - Configure a receive ring after Reset
3090 * @adapter: board private structure
3091 * @ring: receive ring to be configured
3092 *
3093 * Configure the Rx unit of the MAC after a reset.
3094 **/
3095 void igb_configure_rx_ring(struct igb_adapter *adapter,
3096 struct igb_ring *ring)
3097 {
3098 struct e1000_hw *hw = &adapter->hw;
3099 u64 rdba = ring->dma;
3100 int reg_idx = ring->reg_idx;
3101 u32 srrctl = 0, rxdctl = 0;
3102
3103 /* disable the queue */
3104 wr32(E1000_RXDCTL(reg_idx), 0);
3105
3106 /* Set DMA base address registers */
3107 wr32(E1000_RDBAL(reg_idx),
3108 rdba & 0x00000000ffffffffULL);
3109 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3110 wr32(E1000_RDLEN(reg_idx),
3111 ring->count * sizeof(union e1000_adv_rx_desc));
3112
3113 /* initialize head and tail */
3114 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3115 wr32(E1000_RDH(reg_idx), 0);
3116 writel(0, ring->tail);
3117
3118 /* set descriptor configuration */
3119 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3120 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3121 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3122 #ifdef CONFIG_IGB_PTP
3123 if (hw->mac.type >= e1000_82580)
3124 srrctl |= E1000_SRRCTL_TIMESTAMP;
3125 #endif /* CONFIG_IGB_PTP */
3126 /* Only set Drop Enable if we are supporting multiple queues */
3127 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3128 srrctl |= E1000_SRRCTL_DROP_EN;
3129
3130 wr32(E1000_SRRCTL(reg_idx), srrctl);
3131
3132 /* set filtering for VMDQ pools */
3133 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3134
3135 rxdctl |= IGB_RX_PTHRESH;
3136 rxdctl |= IGB_RX_HTHRESH << 8;
3137 rxdctl |= IGB_RX_WTHRESH << 16;
3138
3139 /* enable receive descriptor fetching */
3140 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3141 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3142 }
3143
3144 /**
3145 * igb_configure_rx - Configure receive Unit after Reset
3146 * @adapter: board private structure
3147 *
3148 * Configure the Rx unit of the MAC after a reset.
3149 **/
3150 static void igb_configure_rx(struct igb_adapter *adapter)
3151 {
3152 int i;
3153
3154 /* set UTA to appropriate mode */
3155 igb_set_uta(adapter);
3156
3157 /* set the correct pool for the PF default MAC address in entry 0 */
3158 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3159 adapter->vfs_allocated_count);
3160
3161 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3162 * the Base and Length of the Rx Descriptor Ring */
3163 for (i = 0; i < adapter->num_rx_queues; i++)
3164 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3165 }
3166
3167 /**
3168 * igb_free_tx_resources - Free Tx Resources per Queue
3169 * @tx_ring: Tx descriptor ring for a specific queue
3170 *
3171 * Free all transmit software resources
3172 **/
3173 void igb_free_tx_resources(struct igb_ring *tx_ring)
3174 {
3175 igb_clean_tx_ring(tx_ring);
3176
3177 vfree(tx_ring->tx_buffer_info);
3178 tx_ring->tx_buffer_info = NULL;
3179
3180 /* if not set, then don't free */
3181 if (!tx_ring->desc)
3182 return;
3183
3184 dma_free_coherent(tx_ring->dev, tx_ring->size,
3185 tx_ring->desc, tx_ring->dma);
3186
3187 tx_ring->desc = NULL;
3188 }
3189
3190 /**
3191 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3192 * @adapter: board private structure
3193 *
3194 * Free all transmit software resources
3195 **/
3196 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3197 {
3198 int i;
3199
3200 for (i = 0; i < adapter->num_tx_queues; i++)
3201 igb_free_tx_resources(adapter->tx_ring[i]);
3202 }
3203
3204 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3205 struct igb_tx_buffer *tx_buffer)
3206 {
3207 if (tx_buffer->skb) {
3208 dev_kfree_skb_any(tx_buffer->skb);
3209 if (dma_unmap_len(tx_buffer, len))
3210 dma_unmap_single(ring->dev,
3211 dma_unmap_addr(tx_buffer, dma),
3212 dma_unmap_len(tx_buffer, len),
3213 DMA_TO_DEVICE);
3214 } else if (dma_unmap_len(tx_buffer, len)) {
3215 dma_unmap_page(ring->dev,
3216 dma_unmap_addr(tx_buffer, dma),
3217 dma_unmap_len(tx_buffer, len),
3218 DMA_TO_DEVICE);
3219 }
3220 tx_buffer->next_to_watch = NULL;
3221 tx_buffer->skb = NULL;
3222 dma_unmap_len_set(tx_buffer, len, 0);
3223 /* buffer_info must be completely set up in the transmit path */
3224 }
3225
3226 /**
3227 * igb_clean_tx_ring - Free Tx Buffers
3228 * @tx_ring: ring to be cleaned
3229 **/
3230 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3231 {
3232 struct igb_tx_buffer *buffer_info;
3233 unsigned long size;
3234 u16 i;
3235
3236 if (!tx_ring->tx_buffer_info)
3237 return;
3238 /* Free all the Tx ring sk_buffs */
3239
3240 for (i = 0; i < tx_ring->count; i++) {
3241 buffer_info = &tx_ring->tx_buffer_info[i];
3242 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3243 }
3244
3245 netdev_tx_reset_queue(txring_txq(tx_ring));
3246
3247 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3248 memset(tx_ring->tx_buffer_info, 0, size);
3249
3250 /* Zero out the descriptor ring */
3251 memset(tx_ring->desc, 0, tx_ring->size);
3252
3253 tx_ring->next_to_use = 0;
3254 tx_ring->next_to_clean = 0;
3255 }
3256
3257 /**
3258 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3259 * @adapter: board private structure
3260 **/
3261 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3262 {
3263 int i;
3264
3265 for (i = 0; i < adapter->num_tx_queues; i++)
3266 igb_clean_tx_ring(adapter->tx_ring[i]);
3267 }
3268
3269 /**
3270 * igb_free_rx_resources - Free Rx Resources
3271 * @rx_ring: ring to clean the resources from
3272 *
3273 * Free all receive software resources
3274 **/
3275 void igb_free_rx_resources(struct igb_ring *rx_ring)
3276 {
3277 igb_clean_rx_ring(rx_ring);
3278
3279 vfree(rx_ring->rx_buffer_info);
3280 rx_ring->rx_buffer_info = NULL;
3281
3282 /* if not set, then don't free */
3283 if (!rx_ring->desc)
3284 return;
3285
3286 dma_free_coherent(rx_ring->dev, rx_ring->size,
3287 rx_ring->desc, rx_ring->dma);
3288
3289 rx_ring->desc = NULL;
3290 }
3291
3292 /**
3293 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3294 * @adapter: board private structure
3295 *
3296 * Free all receive software resources
3297 **/
3298 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3299 {
3300 int i;
3301
3302 for (i = 0; i < adapter->num_rx_queues; i++)
3303 igb_free_rx_resources(adapter->rx_ring[i]);
3304 }
3305
3306 /**
3307 * igb_clean_rx_ring - Free Rx Buffers per Queue
3308 * @rx_ring: ring to free buffers from
3309 **/
3310 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3311 {
3312 unsigned long size;
3313 u16 i;
3314
3315 if (rx_ring->skb)
3316 dev_kfree_skb(rx_ring->skb);
3317 rx_ring->skb = NULL;
3318
3319 if (!rx_ring->rx_buffer_info)
3320 return;
3321
3322 /* Free all the Rx ring sk_buffs */
3323 for (i = 0; i < rx_ring->count; i++) {
3324 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3325
3326 if (!buffer_info->page)
3327 continue;
3328
3329 dma_unmap_page(rx_ring->dev,
3330 buffer_info->dma,
3331 PAGE_SIZE,
3332 DMA_FROM_DEVICE);
3333 __free_page(buffer_info->page);
3334
3335 buffer_info->page = NULL;
3336 }
3337
3338 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3339 memset(rx_ring->rx_buffer_info, 0, size);
3340
3341 /* Zero out the descriptor ring */
3342 memset(rx_ring->desc, 0, rx_ring->size);
3343
3344 rx_ring->next_to_alloc = 0;
3345 rx_ring->next_to_clean = 0;
3346 rx_ring->next_to_use = 0;
3347 }
3348
3349 /**
3350 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3351 * @adapter: board private structure
3352 **/
3353 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3354 {
3355 int i;
3356
3357 for (i = 0; i < adapter->num_rx_queues; i++)
3358 igb_clean_rx_ring(adapter->rx_ring[i]);
3359 }
3360
3361 /**
3362 * igb_set_mac - Change the Ethernet Address of the NIC
3363 * @netdev: network interface device structure
3364 * @p: pointer to an address structure
3365 *
3366 * Returns 0 on success, negative on failure
3367 **/
3368 static int igb_set_mac(struct net_device *netdev, void *p)
3369 {
3370 struct igb_adapter *adapter = netdev_priv(netdev);
3371 struct e1000_hw *hw = &adapter->hw;
3372 struct sockaddr *addr = p;
3373
3374 if (!is_valid_ether_addr(addr->sa_data))
3375 return -EADDRNOTAVAIL;
3376
3377 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3378 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3379
3380 /* set the correct pool for the new PF MAC address in entry 0 */
3381 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3382 adapter->vfs_allocated_count);
3383
3384 return 0;
3385 }
3386
3387 /**
3388 * igb_write_mc_addr_list - write multicast addresses to MTA
3389 * @netdev: network interface device structure
3390 *
3391 * Writes multicast address list to the MTA hash table.
3392 * Returns: -ENOMEM on failure
3393 * 0 on no addresses written
3394 * X on writing X addresses to MTA
3395 **/
3396 static int igb_write_mc_addr_list(struct net_device *netdev)
3397 {
3398 struct igb_adapter *adapter = netdev_priv(netdev);
3399 struct e1000_hw *hw = &adapter->hw;
3400 struct netdev_hw_addr *ha;
3401 u8 *mta_list;
3402 int i;
3403
3404 if (netdev_mc_empty(netdev)) {
3405 /* nothing to program, so clear mc list */
3406 igb_update_mc_addr_list(hw, NULL, 0);
3407 igb_restore_vf_multicasts(adapter);
3408 return 0;
3409 }
3410
3411 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3412 if (!mta_list)
3413 return -ENOMEM;
3414
3415 /* The shared function expects a packed array of only addresses. */
3416 i = 0;
3417 netdev_for_each_mc_addr(ha, netdev)
3418 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3419
3420 igb_update_mc_addr_list(hw, mta_list, i);
3421 kfree(mta_list);
3422
3423 return netdev_mc_count(netdev);
3424 }
3425
3426 /**
3427 * igb_write_uc_addr_list - write unicast addresses to RAR table
3428 * @netdev: network interface device structure
3429 *
3430 * Writes unicast address list to the RAR table.
3431 * Returns: -ENOMEM on failure/insufficient address space
3432 * 0 on no addresses written
3433 * X on writing X addresses to the RAR table
3434 **/
3435 static int igb_write_uc_addr_list(struct net_device *netdev)
3436 {
3437 struct igb_adapter *adapter = netdev_priv(netdev);
3438 struct e1000_hw *hw = &adapter->hw;
3439 unsigned int vfn = adapter->vfs_allocated_count;
3440 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3441 int count = 0;
3442
3443 /* return ENOMEM indicating insufficient memory for addresses */
3444 if (netdev_uc_count(netdev) > rar_entries)
3445 return -ENOMEM;
3446
3447 if (!netdev_uc_empty(netdev) && rar_entries) {
3448 struct netdev_hw_addr *ha;
3449
3450 netdev_for_each_uc_addr(ha, netdev) {
3451 if (!rar_entries)
3452 break;
3453 igb_rar_set_qsel(adapter, ha->addr,
3454 rar_entries--,
3455 vfn);
3456 count++;
3457 }
3458 }
3459 /* write the addresses in reverse order to avoid write combining */
3460 for (; rar_entries > 0 ; rar_entries--) {
3461 wr32(E1000_RAH(rar_entries), 0);
3462 wr32(E1000_RAL(rar_entries), 0);
3463 }
3464 wrfl();
3465
3466 return count;
3467 }
3468
3469 /**
3470 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3471 * @netdev: network interface device structure
3472 *
3473 * The set_rx_mode entry point is called whenever the unicast or multicast
3474 * address lists or the network interface flags are updated. This routine is
3475 * responsible for configuring the hardware for proper unicast, multicast,
3476 * promiscuous mode, and all-multi behavior.
3477 **/
3478 static void igb_set_rx_mode(struct net_device *netdev)
3479 {
3480 struct igb_adapter *adapter = netdev_priv(netdev);
3481 struct e1000_hw *hw = &adapter->hw;
3482 unsigned int vfn = adapter->vfs_allocated_count;
3483 u32 rctl, vmolr = 0;
3484 int count;
3485
3486 /* Check for Promiscuous and All Multicast modes */
3487 rctl = rd32(E1000_RCTL);
3488
3489 /* clear the effected bits */
3490 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3491
3492 if (netdev->flags & IFF_PROMISC) {
3493 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3494 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3495 } else {
3496 if (netdev->flags & IFF_ALLMULTI) {
3497 rctl |= E1000_RCTL_MPE;
3498 vmolr |= E1000_VMOLR_MPME;
3499 } else {
3500 /*
3501 * Write addresses to the MTA, if the attempt fails
3502 * then we should just turn on promiscuous mode so
3503 * that we can at least receive multicast traffic
3504 */
3505 count = igb_write_mc_addr_list(netdev);
3506 if (count < 0) {
3507 rctl |= E1000_RCTL_MPE;
3508 vmolr |= E1000_VMOLR_MPME;
3509 } else if (count) {
3510 vmolr |= E1000_VMOLR_ROMPE;
3511 }
3512 }
3513 /*
3514 * Write addresses to available RAR registers, if there is not
3515 * sufficient space to store all the addresses then enable
3516 * unicast promiscuous mode
3517 */
3518 count = igb_write_uc_addr_list(netdev);
3519 if (count < 0) {
3520 rctl |= E1000_RCTL_UPE;
3521 vmolr |= E1000_VMOLR_ROPE;
3522 }
3523 rctl |= E1000_RCTL_VFE;
3524 }
3525 wr32(E1000_RCTL, rctl);
3526
3527 /*
3528 * In order to support SR-IOV and eventually VMDq it is necessary to set
3529 * the VMOLR to enable the appropriate modes. Without this workaround
3530 * we will have issues with VLAN tag stripping not being done for frames
3531 * that are only arriving because we are the default pool
3532 */
3533 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3534 return;
3535
3536 vmolr |= rd32(E1000_VMOLR(vfn)) &
3537 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3538 wr32(E1000_VMOLR(vfn), vmolr);
3539 igb_restore_vf_multicasts(adapter);
3540 }
3541
3542 static void igb_check_wvbr(struct igb_adapter *adapter)
3543 {
3544 struct e1000_hw *hw = &adapter->hw;
3545 u32 wvbr = 0;
3546
3547 switch (hw->mac.type) {
3548 case e1000_82576:
3549 case e1000_i350:
3550 if (!(wvbr = rd32(E1000_WVBR)))
3551 return;
3552 break;
3553 default:
3554 break;
3555 }
3556
3557 adapter->wvbr |= wvbr;
3558 }
3559
3560 #define IGB_STAGGERED_QUEUE_OFFSET 8
3561
3562 static void igb_spoof_check(struct igb_adapter *adapter)
3563 {
3564 int j;
3565
3566 if (!adapter->wvbr)
3567 return;
3568
3569 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3570 if (adapter->wvbr & (1 << j) ||
3571 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3572 dev_warn(&adapter->pdev->dev,
3573 "Spoof event(s) detected on VF %d\n", j);
3574 adapter->wvbr &=
3575 ~((1 << j) |
3576 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3577 }
3578 }
3579 }
3580
3581 /* Need to wait a few seconds after link up to get diagnostic information from
3582 * the phy */
3583 static void igb_update_phy_info(unsigned long data)
3584 {
3585 struct igb_adapter *adapter = (struct igb_adapter *) data;
3586 igb_get_phy_info(&adapter->hw);
3587 }
3588
3589 /**
3590 * igb_has_link - check shared code for link and determine up/down
3591 * @adapter: pointer to driver private info
3592 **/
3593 bool igb_has_link(struct igb_adapter *adapter)
3594 {
3595 struct e1000_hw *hw = &adapter->hw;
3596 bool link_active = false;
3597 s32 ret_val = 0;
3598
3599 /* get_link_status is set on LSC (link status) interrupt or
3600 * rx sequence error interrupt. get_link_status will stay
3601 * false until the e1000_check_for_link establishes link
3602 * for copper adapters ONLY
3603 */
3604 switch (hw->phy.media_type) {
3605 case e1000_media_type_copper:
3606 if (hw->mac.get_link_status) {
3607 ret_val = hw->mac.ops.check_for_link(hw);
3608 link_active = !hw->mac.get_link_status;
3609 } else {
3610 link_active = true;
3611 }
3612 break;
3613 case e1000_media_type_internal_serdes:
3614 ret_val = hw->mac.ops.check_for_link(hw);
3615 link_active = hw->mac.serdes_has_link;
3616 break;
3617 default:
3618 case e1000_media_type_unknown:
3619 break;
3620 }
3621
3622 return link_active;
3623 }
3624
3625 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3626 {
3627 bool ret = false;
3628 u32 ctrl_ext, thstat;
3629
3630 /* check for thermal sensor event on i350 copper only */
3631 if (hw->mac.type == e1000_i350) {
3632 thstat = rd32(E1000_THSTAT);
3633 ctrl_ext = rd32(E1000_CTRL_EXT);
3634
3635 if ((hw->phy.media_type == e1000_media_type_copper) &&
3636 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3637 ret = !!(thstat & event);
3638 }
3639 }
3640
3641 return ret;
3642 }
3643
3644 /**
3645 * igb_watchdog - Timer Call-back
3646 * @data: pointer to adapter cast into an unsigned long
3647 **/
3648 static void igb_watchdog(unsigned long data)
3649 {
3650 struct igb_adapter *adapter = (struct igb_adapter *)data;
3651 /* Do the rest outside of interrupt context */
3652 schedule_work(&adapter->watchdog_task);
3653 }
3654
3655 static void igb_watchdog_task(struct work_struct *work)
3656 {
3657 struct igb_adapter *adapter = container_of(work,
3658 struct igb_adapter,
3659 watchdog_task);
3660 struct e1000_hw *hw = &adapter->hw;
3661 struct net_device *netdev = adapter->netdev;
3662 u32 link;
3663 int i;
3664
3665 link = igb_has_link(adapter);
3666 if (link) {
3667 /* Cancel scheduled suspend requests. */
3668 pm_runtime_resume(netdev->dev.parent);
3669
3670 if (!netif_carrier_ok(netdev)) {
3671 u32 ctrl;
3672 hw->mac.ops.get_speed_and_duplex(hw,
3673 &adapter->link_speed,
3674 &adapter->link_duplex);
3675
3676 ctrl = rd32(E1000_CTRL);
3677 /* Links status message must follow this format */
3678 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3679 "Duplex, Flow Control: %s\n",
3680 netdev->name,
3681 adapter->link_speed,
3682 adapter->link_duplex == FULL_DUPLEX ?
3683 "Full" : "Half",
3684 (ctrl & E1000_CTRL_TFCE) &&
3685 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3686 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3687 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
3688
3689 /* check for thermal sensor event */
3690 if (igb_thermal_sensor_event(hw,
3691 E1000_THSTAT_LINK_THROTTLE)) {
3692 netdev_info(netdev, "The network adapter link "
3693 "speed was downshifted because it "
3694 "overheated\n");
3695 }
3696
3697 /* adjust timeout factor according to speed/duplex */
3698 adapter->tx_timeout_factor = 1;
3699 switch (adapter->link_speed) {
3700 case SPEED_10:
3701 adapter->tx_timeout_factor = 14;
3702 break;
3703 case SPEED_100:
3704 /* maybe add some timeout factor ? */
3705 break;
3706 }
3707
3708 netif_carrier_on(netdev);
3709
3710 igb_ping_all_vfs(adapter);
3711 igb_check_vf_rate_limit(adapter);
3712
3713 /* link state has changed, schedule phy info update */
3714 if (!test_bit(__IGB_DOWN, &adapter->state))
3715 mod_timer(&adapter->phy_info_timer,
3716 round_jiffies(jiffies + 2 * HZ));
3717 }
3718 } else {
3719 if (netif_carrier_ok(netdev)) {
3720 adapter->link_speed = 0;
3721 adapter->link_duplex = 0;
3722
3723 /* check for thermal sensor event */
3724 if (igb_thermal_sensor_event(hw,
3725 E1000_THSTAT_PWR_DOWN)) {
3726 netdev_err(netdev, "The network adapter was "
3727 "stopped because it overheated\n");
3728 }
3729
3730 /* Links status message must follow this format */
3731 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3732 netdev->name);
3733 netif_carrier_off(netdev);
3734
3735 igb_ping_all_vfs(adapter);
3736
3737 /* link state has changed, schedule phy info update */
3738 if (!test_bit(__IGB_DOWN, &adapter->state))
3739 mod_timer(&adapter->phy_info_timer,
3740 round_jiffies(jiffies + 2 * HZ));
3741
3742 pm_schedule_suspend(netdev->dev.parent,
3743 MSEC_PER_SEC * 5);
3744 }
3745 }
3746
3747 spin_lock(&adapter->stats64_lock);
3748 igb_update_stats(adapter, &adapter->stats64);
3749 spin_unlock(&adapter->stats64_lock);
3750
3751 for (i = 0; i < adapter->num_tx_queues; i++) {
3752 struct igb_ring *tx_ring = adapter->tx_ring[i];
3753 if (!netif_carrier_ok(netdev)) {
3754 /* We've lost link, so the controller stops DMA,
3755 * but we've got queued Tx work that's never going
3756 * to get done, so reset controller to flush Tx.
3757 * (Do the reset outside of interrupt context). */
3758 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3759 adapter->tx_timeout_count++;
3760 schedule_work(&adapter->reset_task);
3761 /* return immediately since reset is imminent */
3762 return;
3763 }
3764 }
3765
3766 /* Force detection of hung controller every watchdog period */
3767 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3768 }
3769
3770 /* Cause software interrupt to ensure rx ring is cleaned */
3771 if (adapter->msix_entries) {
3772 u32 eics = 0;
3773 for (i = 0; i < adapter->num_q_vectors; i++)
3774 eics |= adapter->q_vector[i]->eims_value;
3775 wr32(E1000_EICS, eics);
3776 } else {
3777 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3778 }
3779
3780 igb_spoof_check(adapter);
3781
3782 /* Reset the timer */
3783 if (!test_bit(__IGB_DOWN, &adapter->state))
3784 mod_timer(&adapter->watchdog_timer,
3785 round_jiffies(jiffies + 2 * HZ));
3786 }
3787
3788 enum latency_range {
3789 lowest_latency = 0,
3790 low_latency = 1,
3791 bulk_latency = 2,
3792 latency_invalid = 255
3793 };
3794
3795 /**
3796 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3797 *
3798 * Stores a new ITR value based on strictly on packet size. This
3799 * algorithm is less sophisticated than that used in igb_update_itr,
3800 * due to the difficulty of synchronizing statistics across multiple
3801 * receive rings. The divisors and thresholds used by this function
3802 * were determined based on theoretical maximum wire speed and testing
3803 * data, in order to minimize response time while increasing bulk
3804 * throughput.
3805 * This functionality is controlled by the InterruptThrottleRate module
3806 * parameter (see igb_param.c)
3807 * NOTE: This function is called only when operating in a multiqueue
3808 * receive environment.
3809 * @q_vector: pointer to q_vector
3810 **/
3811 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3812 {
3813 int new_val = q_vector->itr_val;
3814 int avg_wire_size = 0;
3815 struct igb_adapter *adapter = q_vector->adapter;
3816 unsigned int packets;
3817
3818 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3819 * ints/sec - ITR timer value of 120 ticks.
3820 */
3821 if (adapter->link_speed != SPEED_1000) {
3822 new_val = IGB_4K_ITR;
3823 goto set_itr_val;
3824 }
3825
3826 packets = q_vector->rx.total_packets;
3827 if (packets)
3828 avg_wire_size = q_vector->rx.total_bytes / packets;
3829
3830 packets = q_vector->tx.total_packets;
3831 if (packets)
3832 avg_wire_size = max_t(u32, avg_wire_size,
3833 q_vector->tx.total_bytes / packets);
3834
3835 /* if avg_wire_size isn't set no work was done */
3836 if (!avg_wire_size)
3837 goto clear_counts;
3838
3839 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3840 avg_wire_size += 24;
3841
3842 /* Don't starve jumbo frames */
3843 avg_wire_size = min(avg_wire_size, 3000);
3844
3845 /* Give a little boost to mid-size frames */
3846 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3847 new_val = avg_wire_size / 3;
3848 else
3849 new_val = avg_wire_size / 2;
3850
3851 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3852 if (new_val < IGB_20K_ITR &&
3853 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3854 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3855 new_val = IGB_20K_ITR;
3856
3857 set_itr_val:
3858 if (new_val != q_vector->itr_val) {
3859 q_vector->itr_val = new_val;
3860 q_vector->set_itr = 1;
3861 }
3862 clear_counts:
3863 q_vector->rx.total_bytes = 0;
3864 q_vector->rx.total_packets = 0;
3865 q_vector->tx.total_bytes = 0;
3866 q_vector->tx.total_packets = 0;
3867 }
3868
3869 /**
3870 * igb_update_itr - update the dynamic ITR value based on statistics
3871 * Stores a new ITR value based on packets and byte
3872 * counts during the last interrupt. The advantage of per interrupt
3873 * computation is faster updates and more accurate ITR for the current
3874 * traffic pattern. Constants in this function were computed
3875 * based on theoretical maximum wire speed and thresholds were set based
3876 * on testing data as well as attempting to minimize response time
3877 * while increasing bulk throughput.
3878 * this functionality is controlled by the InterruptThrottleRate module
3879 * parameter (see igb_param.c)
3880 * NOTE: These calculations are only valid when operating in a single-
3881 * queue environment.
3882 * @q_vector: pointer to q_vector
3883 * @ring_container: ring info to update the itr for
3884 **/
3885 static void igb_update_itr(struct igb_q_vector *q_vector,
3886 struct igb_ring_container *ring_container)
3887 {
3888 unsigned int packets = ring_container->total_packets;
3889 unsigned int bytes = ring_container->total_bytes;
3890 u8 itrval = ring_container->itr;
3891
3892 /* no packets, exit with status unchanged */
3893 if (packets == 0)
3894 return;
3895
3896 switch (itrval) {
3897 case lowest_latency:
3898 /* handle TSO and jumbo frames */
3899 if (bytes/packets > 8000)
3900 itrval = bulk_latency;
3901 else if ((packets < 5) && (bytes > 512))
3902 itrval = low_latency;
3903 break;
3904 case low_latency: /* 50 usec aka 20000 ints/s */
3905 if (bytes > 10000) {
3906 /* this if handles the TSO accounting */
3907 if (bytes/packets > 8000) {
3908 itrval = bulk_latency;
3909 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3910 itrval = bulk_latency;
3911 } else if ((packets > 35)) {
3912 itrval = lowest_latency;
3913 }
3914 } else if (bytes/packets > 2000) {
3915 itrval = bulk_latency;
3916 } else if (packets <= 2 && bytes < 512) {
3917 itrval = lowest_latency;
3918 }
3919 break;
3920 case bulk_latency: /* 250 usec aka 4000 ints/s */
3921 if (bytes > 25000) {
3922 if (packets > 35)
3923 itrval = low_latency;
3924 } else if (bytes < 1500) {
3925 itrval = low_latency;
3926 }
3927 break;
3928 }
3929
3930 /* clear work counters since we have the values we need */
3931 ring_container->total_bytes = 0;
3932 ring_container->total_packets = 0;
3933
3934 /* write updated itr to ring container */
3935 ring_container->itr = itrval;
3936 }
3937
3938 static void igb_set_itr(struct igb_q_vector *q_vector)
3939 {
3940 struct igb_adapter *adapter = q_vector->adapter;
3941 u32 new_itr = q_vector->itr_val;
3942 u8 current_itr = 0;
3943
3944 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3945 if (adapter->link_speed != SPEED_1000) {
3946 current_itr = 0;
3947 new_itr = IGB_4K_ITR;
3948 goto set_itr_now;
3949 }
3950
3951 igb_update_itr(q_vector, &q_vector->tx);
3952 igb_update_itr(q_vector, &q_vector->rx);
3953
3954 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3955
3956 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3957 if (current_itr == lowest_latency &&
3958 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3959 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3960 current_itr = low_latency;
3961
3962 switch (current_itr) {
3963 /* counts and packets in update_itr are dependent on these numbers */
3964 case lowest_latency:
3965 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
3966 break;
3967 case low_latency:
3968 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
3969 break;
3970 case bulk_latency:
3971 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
3972 break;
3973 default:
3974 break;
3975 }
3976
3977 set_itr_now:
3978 if (new_itr != q_vector->itr_val) {
3979 /* this attempts to bias the interrupt rate towards Bulk
3980 * by adding intermediate steps when interrupt rate is
3981 * increasing */
3982 new_itr = new_itr > q_vector->itr_val ?
3983 max((new_itr * q_vector->itr_val) /
3984 (new_itr + (q_vector->itr_val >> 2)),
3985 new_itr) :
3986 new_itr;
3987 /* Don't write the value here; it resets the adapter's
3988 * internal timer, and causes us to delay far longer than
3989 * we should between interrupts. Instead, we write the ITR
3990 * value at the beginning of the next interrupt so the timing
3991 * ends up being correct.
3992 */
3993 q_vector->itr_val = new_itr;
3994 q_vector->set_itr = 1;
3995 }
3996 }
3997
3998 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3999 u32 type_tucmd, u32 mss_l4len_idx)
4000 {
4001 struct e1000_adv_tx_context_desc *context_desc;
4002 u16 i = tx_ring->next_to_use;
4003
4004 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4005
4006 i++;
4007 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4008
4009 /* set bits to identify this as an advanced context descriptor */
4010 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4011
4012 /* For 82575, context index must be unique per ring. */
4013 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4014 mss_l4len_idx |= tx_ring->reg_idx << 4;
4015
4016 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4017 context_desc->seqnum_seed = 0;
4018 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4019 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4020 }
4021
4022 static int igb_tso(struct igb_ring *tx_ring,
4023 struct igb_tx_buffer *first,
4024 u8 *hdr_len)
4025 {
4026 struct sk_buff *skb = first->skb;
4027 u32 vlan_macip_lens, type_tucmd;
4028 u32 mss_l4len_idx, l4len;
4029
4030 if (!skb_is_gso(skb))
4031 return 0;
4032
4033 if (skb_header_cloned(skb)) {
4034 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4035 if (err)
4036 return err;
4037 }
4038
4039 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4040 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4041
4042 if (first->protocol == __constant_htons(ETH_P_IP)) {
4043 struct iphdr *iph = ip_hdr(skb);
4044 iph->tot_len = 0;
4045 iph->check = 0;
4046 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4047 iph->daddr, 0,
4048 IPPROTO_TCP,
4049 0);
4050 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4051 first->tx_flags |= IGB_TX_FLAGS_TSO |
4052 IGB_TX_FLAGS_CSUM |
4053 IGB_TX_FLAGS_IPV4;
4054 } else if (skb_is_gso_v6(skb)) {
4055 ipv6_hdr(skb)->payload_len = 0;
4056 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4057 &ipv6_hdr(skb)->daddr,
4058 0, IPPROTO_TCP, 0);
4059 first->tx_flags |= IGB_TX_FLAGS_TSO |
4060 IGB_TX_FLAGS_CSUM;
4061 }
4062
4063 /* compute header lengths */
4064 l4len = tcp_hdrlen(skb);
4065 *hdr_len = skb_transport_offset(skb) + l4len;
4066
4067 /* update gso size and bytecount with header size */
4068 first->gso_segs = skb_shinfo(skb)->gso_segs;
4069 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4070
4071 /* MSS L4LEN IDX */
4072 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4073 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4074
4075 /* VLAN MACLEN IPLEN */
4076 vlan_macip_lens = skb_network_header_len(skb);
4077 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4078 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4079
4080 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4081
4082 return 1;
4083 }
4084
4085 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4086 {
4087 struct sk_buff *skb = first->skb;
4088 u32 vlan_macip_lens = 0;
4089 u32 mss_l4len_idx = 0;
4090 u32 type_tucmd = 0;
4091
4092 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4093 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4094 return;
4095 } else {
4096 u8 l4_hdr = 0;
4097 switch (first->protocol) {
4098 case __constant_htons(ETH_P_IP):
4099 vlan_macip_lens |= skb_network_header_len(skb);
4100 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4101 l4_hdr = ip_hdr(skb)->protocol;
4102 break;
4103 case __constant_htons(ETH_P_IPV6):
4104 vlan_macip_lens |= skb_network_header_len(skb);
4105 l4_hdr = ipv6_hdr(skb)->nexthdr;
4106 break;
4107 default:
4108 if (unlikely(net_ratelimit())) {
4109 dev_warn(tx_ring->dev,
4110 "partial checksum but proto=%x!\n",
4111 first->protocol);
4112 }
4113 break;
4114 }
4115
4116 switch (l4_hdr) {
4117 case IPPROTO_TCP:
4118 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4119 mss_l4len_idx = tcp_hdrlen(skb) <<
4120 E1000_ADVTXD_L4LEN_SHIFT;
4121 break;
4122 case IPPROTO_SCTP:
4123 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4124 mss_l4len_idx = sizeof(struct sctphdr) <<
4125 E1000_ADVTXD_L4LEN_SHIFT;
4126 break;
4127 case IPPROTO_UDP:
4128 mss_l4len_idx = sizeof(struct udphdr) <<
4129 E1000_ADVTXD_L4LEN_SHIFT;
4130 break;
4131 default:
4132 if (unlikely(net_ratelimit())) {
4133 dev_warn(tx_ring->dev,
4134 "partial checksum but l4 proto=%x!\n",
4135 l4_hdr);
4136 }
4137 break;
4138 }
4139
4140 /* update TX checksum flag */
4141 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4142 }
4143
4144 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4145 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4146
4147 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4148 }
4149
4150 static __le32 igb_tx_cmd_type(u32 tx_flags)
4151 {
4152 /* set type for advanced descriptor with frame checksum insertion */
4153 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA |
4154 E1000_ADVTXD_DCMD_IFCS |
4155 E1000_ADVTXD_DCMD_DEXT);
4156
4157 /* set HW vlan bit if vlan is present */
4158 if (tx_flags & IGB_TX_FLAGS_VLAN)
4159 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE);
4160
4161 #ifdef CONFIG_IGB_PTP
4162 /* set timestamp bit if present */
4163 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP))
4164 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP);
4165 #endif /* CONFIG_IGB_PTP */
4166
4167 /* set segmentation bits for TSO */
4168 if (tx_flags & IGB_TX_FLAGS_TSO)
4169 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE);
4170
4171 return cmd_type;
4172 }
4173
4174 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4175 union e1000_adv_tx_desc *tx_desc,
4176 u32 tx_flags, unsigned int paylen)
4177 {
4178 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4179
4180 /* 82575 requires a unique index per ring if any offload is enabled */
4181 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) &&
4182 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4183 olinfo_status |= tx_ring->reg_idx << 4;
4184
4185 /* insert L4 checksum */
4186 if (tx_flags & IGB_TX_FLAGS_CSUM) {
4187 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4188
4189 /* insert IPv4 checksum */
4190 if (tx_flags & IGB_TX_FLAGS_IPV4)
4191 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4192 }
4193
4194 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4195 }
4196
4197 /*
4198 * The largest size we can write to the descriptor is 65535. In order to
4199 * maintain a power of two alignment we have to limit ourselves to 32K.
4200 */
4201 #define IGB_MAX_TXD_PWR 15
4202 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
4203
4204 static void igb_tx_map(struct igb_ring *tx_ring,
4205 struct igb_tx_buffer *first,
4206 const u8 hdr_len)
4207 {
4208 struct sk_buff *skb = first->skb;
4209 struct igb_tx_buffer *tx_buffer;
4210 union e1000_adv_tx_desc *tx_desc;
4211 dma_addr_t dma;
4212 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
4213 unsigned int data_len = skb->data_len;
4214 unsigned int size = skb_headlen(skb);
4215 unsigned int paylen = skb->len - hdr_len;
4216 __le32 cmd_type;
4217 u32 tx_flags = first->tx_flags;
4218 u16 i = tx_ring->next_to_use;
4219
4220 tx_desc = IGB_TX_DESC(tx_ring, i);
4221
4222 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen);
4223 cmd_type = igb_tx_cmd_type(tx_flags);
4224
4225 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4226 if (dma_mapping_error(tx_ring->dev, dma))
4227 goto dma_error;
4228
4229 /* record length, and DMA address */
4230 dma_unmap_len_set(first, len, size);
4231 dma_unmap_addr_set(first, dma, dma);
4232 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4233
4234 for (;;) {
4235 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4236 tx_desc->read.cmd_type_len =
4237 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD);
4238
4239 i++;
4240 tx_desc++;
4241 if (i == tx_ring->count) {
4242 tx_desc = IGB_TX_DESC(tx_ring, 0);
4243 i = 0;
4244 }
4245
4246 dma += IGB_MAX_DATA_PER_TXD;
4247 size -= IGB_MAX_DATA_PER_TXD;
4248
4249 tx_desc->read.olinfo_status = 0;
4250 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4251 }
4252
4253 if (likely(!data_len))
4254 break;
4255
4256 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
4257
4258 i++;
4259 tx_desc++;
4260 if (i == tx_ring->count) {
4261 tx_desc = IGB_TX_DESC(tx_ring, 0);
4262 i = 0;
4263 }
4264
4265 size = skb_frag_size(frag);
4266 data_len -= size;
4267
4268 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4269 size, DMA_TO_DEVICE);
4270 if (dma_mapping_error(tx_ring->dev, dma))
4271 goto dma_error;
4272
4273 tx_buffer = &tx_ring->tx_buffer_info[i];
4274 dma_unmap_len_set(tx_buffer, len, size);
4275 dma_unmap_addr_set(tx_buffer, dma, dma);
4276
4277 tx_desc->read.olinfo_status = 0;
4278 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4279
4280 frag++;
4281 }
4282
4283 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4284
4285 /* write last descriptor with RS and EOP bits */
4286 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD);
4287 if (unlikely(skb->no_fcs))
4288 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS));
4289 tx_desc->read.cmd_type_len = cmd_type;
4290
4291 /* set the timestamp */
4292 first->time_stamp = jiffies;
4293
4294 /*
4295 * Force memory writes to complete before letting h/w know there
4296 * are new descriptors to fetch. (Only applicable for weak-ordered
4297 * memory model archs, such as IA-64).
4298 *
4299 * We also need this memory barrier to make certain all of the
4300 * status bits have been updated before next_to_watch is written.
4301 */
4302 wmb();
4303
4304 /* set next_to_watch value indicating a packet is present */
4305 first->next_to_watch = tx_desc;
4306
4307 i++;
4308 if (i == tx_ring->count)
4309 i = 0;
4310
4311 tx_ring->next_to_use = i;
4312
4313 writel(i, tx_ring->tail);
4314
4315 /* we need this if more than one processor can write to our tail
4316 * at a time, it syncronizes IO on IA64/Altix systems */
4317 mmiowb();
4318
4319 return;
4320
4321 dma_error:
4322 dev_err(tx_ring->dev, "TX DMA map failed\n");
4323
4324 /* clear dma mappings for failed tx_buffer_info map */
4325 for (;;) {
4326 tx_buffer = &tx_ring->tx_buffer_info[i];
4327 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4328 if (tx_buffer == first)
4329 break;
4330 if (i == 0)
4331 i = tx_ring->count;
4332 i--;
4333 }
4334
4335 tx_ring->next_to_use = i;
4336 }
4337
4338 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4339 {
4340 struct net_device *netdev = tx_ring->netdev;
4341
4342 netif_stop_subqueue(netdev, tx_ring->queue_index);
4343
4344 /* Herbert's original patch had:
4345 * smp_mb__after_netif_stop_queue();
4346 * but since that doesn't exist yet, just open code it. */
4347 smp_mb();
4348
4349 /* We need to check again in a case another CPU has just
4350 * made room available. */
4351 if (igb_desc_unused(tx_ring) < size)
4352 return -EBUSY;
4353
4354 /* A reprieve! */
4355 netif_wake_subqueue(netdev, tx_ring->queue_index);
4356
4357 u64_stats_update_begin(&tx_ring->tx_syncp2);
4358 tx_ring->tx_stats.restart_queue2++;
4359 u64_stats_update_end(&tx_ring->tx_syncp2);
4360
4361 return 0;
4362 }
4363
4364 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4365 {
4366 if (igb_desc_unused(tx_ring) >= size)
4367 return 0;
4368 return __igb_maybe_stop_tx(tx_ring, size);
4369 }
4370
4371 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4372 struct igb_ring *tx_ring)
4373 {
4374 #ifdef CONFIG_IGB_PTP
4375 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4376 #endif /* CONFIG_IGB_PTP */
4377 struct igb_tx_buffer *first;
4378 int tso;
4379 u32 tx_flags = 0;
4380 __be16 protocol = vlan_get_protocol(skb);
4381 u8 hdr_len = 0;
4382
4383 /* need: 1 descriptor per page,
4384 * + 2 desc gap to keep tail from touching head,
4385 * + 1 desc for skb->data,
4386 * + 1 desc for context descriptor,
4387 * otherwise try next time */
4388 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4389 /* this is a hard error */
4390 return NETDEV_TX_BUSY;
4391 }
4392
4393 /* record the location of the first descriptor for this packet */
4394 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4395 first->skb = skb;
4396 first->bytecount = skb->len;
4397 first->gso_segs = 1;
4398
4399 #ifdef CONFIG_IGB_PTP
4400 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4401 !(adapter->ptp_tx_skb))) {
4402 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4403 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4404
4405 adapter->ptp_tx_skb = skb_get(skb);
4406 if (adapter->hw.mac.type == e1000_82576)
4407 schedule_work(&adapter->ptp_tx_work);
4408 }
4409 #endif /* CONFIG_IGB_PTP */
4410
4411 if (vlan_tx_tag_present(skb)) {
4412 tx_flags |= IGB_TX_FLAGS_VLAN;
4413 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4414 }
4415
4416 /* record initial flags and protocol */
4417 first->tx_flags = tx_flags;
4418 first->protocol = protocol;
4419
4420 tso = igb_tso(tx_ring, first, &hdr_len);
4421 if (tso < 0)
4422 goto out_drop;
4423 else if (!tso)
4424 igb_tx_csum(tx_ring, first);
4425
4426 igb_tx_map(tx_ring, first, hdr_len);
4427
4428 /* Make sure there is space in the ring for the next send. */
4429 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4430
4431 return NETDEV_TX_OK;
4432
4433 out_drop:
4434 igb_unmap_and_free_tx_resource(tx_ring, first);
4435
4436 return NETDEV_TX_OK;
4437 }
4438
4439 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4440 struct sk_buff *skb)
4441 {
4442 unsigned int r_idx = skb->queue_mapping;
4443
4444 if (r_idx >= adapter->num_tx_queues)
4445 r_idx = r_idx % adapter->num_tx_queues;
4446
4447 return adapter->tx_ring[r_idx];
4448 }
4449
4450 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4451 struct net_device *netdev)
4452 {
4453 struct igb_adapter *adapter = netdev_priv(netdev);
4454
4455 if (test_bit(__IGB_DOWN, &adapter->state)) {
4456 dev_kfree_skb_any(skb);
4457 return NETDEV_TX_OK;
4458 }
4459
4460 if (skb->len <= 0) {
4461 dev_kfree_skb_any(skb);
4462 return NETDEV_TX_OK;
4463 }
4464
4465 /*
4466 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4467 * in order to meet this minimum size requirement.
4468 */
4469 if (unlikely(skb->len < 17)) {
4470 if (skb_pad(skb, 17 - skb->len))
4471 return NETDEV_TX_OK;
4472 skb->len = 17;
4473 skb_set_tail_pointer(skb, 17);
4474 }
4475
4476 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4477 }
4478
4479 /**
4480 * igb_tx_timeout - Respond to a Tx Hang
4481 * @netdev: network interface device structure
4482 **/
4483 static void igb_tx_timeout(struct net_device *netdev)
4484 {
4485 struct igb_adapter *adapter = netdev_priv(netdev);
4486 struct e1000_hw *hw = &adapter->hw;
4487
4488 /* Do the reset outside of interrupt context */
4489 adapter->tx_timeout_count++;
4490
4491 if (hw->mac.type >= e1000_82580)
4492 hw->dev_spec._82575.global_device_reset = true;
4493
4494 schedule_work(&adapter->reset_task);
4495 wr32(E1000_EICS,
4496 (adapter->eims_enable_mask & ~adapter->eims_other));
4497 }
4498
4499 static void igb_reset_task(struct work_struct *work)
4500 {
4501 struct igb_adapter *adapter;
4502 adapter = container_of(work, struct igb_adapter, reset_task);
4503
4504 igb_dump(adapter);
4505 netdev_err(adapter->netdev, "Reset adapter\n");
4506 igb_reinit_locked(adapter);
4507 }
4508
4509 /**
4510 * igb_get_stats64 - Get System Network Statistics
4511 * @netdev: network interface device structure
4512 * @stats: rtnl_link_stats64 pointer
4513 *
4514 **/
4515 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4516 struct rtnl_link_stats64 *stats)
4517 {
4518 struct igb_adapter *adapter = netdev_priv(netdev);
4519
4520 spin_lock(&adapter->stats64_lock);
4521 igb_update_stats(adapter, &adapter->stats64);
4522 memcpy(stats, &adapter->stats64, sizeof(*stats));
4523 spin_unlock(&adapter->stats64_lock);
4524
4525 return stats;
4526 }
4527
4528 /**
4529 * igb_change_mtu - Change the Maximum Transfer Unit
4530 * @netdev: network interface device structure
4531 * @new_mtu: new value for maximum frame size
4532 *
4533 * Returns 0 on success, negative on failure
4534 **/
4535 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4536 {
4537 struct igb_adapter *adapter = netdev_priv(netdev);
4538 struct pci_dev *pdev = adapter->pdev;
4539 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4540
4541 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4542 dev_err(&pdev->dev, "Invalid MTU setting\n");
4543 return -EINVAL;
4544 }
4545
4546 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4547 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4548 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4549 return -EINVAL;
4550 }
4551
4552 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4553 msleep(1);
4554
4555 /* igb_down has a dependency on max_frame_size */
4556 adapter->max_frame_size = max_frame;
4557
4558 if (netif_running(netdev))
4559 igb_down(adapter);
4560
4561 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4562 netdev->mtu, new_mtu);
4563 netdev->mtu = new_mtu;
4564
4565 if (netif_running(netdev))
4566 igb_up(adapter);
4567 else
4568 igb_reset(adapter);
4569
4570 clear_bit(__IGB_RESETTING, &adapter->state);
4571
4572 return 0;
4573 }
4574
4575 /**
4576 * igb_update_stats - Update the board statistics counters
4577 * @adapter: board private structure
4578 **/
4579
4580 void igb_update_stats(struct igb_adapter *adapter,
4581 struct rtnl_link_stats64 *net_stats)
4582 {
4583 struct e1000_hw *hw = &adapter->hw;
4584 struct pci_dev *pdev = adapter->pdev;
4585 u32 reg, mpc;
4586 u16 phy_tmp;
4587 int i;
4588 u64 bytes, packets;
4589 unsigned int start;
4590 u64 _bytes, _packets;
4591
4592 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4593
4594 /*
4595 * Prevent stats update while adapter is being reset, or if the pci
4596 * connection is down.
4597 */
4598 if (adapter->link_speed == 0)
4599 return;
4600 if (pci_channel_offline(pdev))
4601 return;
4602
4603 bytes = 0;
4604 packets = 0;
4605 for (i = 0; i < adapter->num_rx_queues; i++) {
4606 u32 rqdpc = rd32(E1000_RQDPC(i));
4607 struct igb_ring *ring = adapter->rx_ring[i];
4608
4609 if (rqdpc) {
4610 ring->rx_stats.drops += rqdpc;
4611 net_stats->rx_fifo_errors += rqdpc;
4612 }
4613
4614 do {
4615 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4616 _bytes = ring->rx_stats.bytes;
4617 _packets = ring->rx_stats.packets;
4618 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4619 bytes += _bytes;
4620 packets += _packets;
4621 }
4622
4623 net_stats->rx_bytes = bytes;
4624 net_stats->rx_packets = packets;
4625
4626 bytes = 0;
4627 packets = 0;
4628 for (i = 0; i < adapter->num_tx_queues; i++) {
4629 struct igb_ring *ring = adapter->tx_ring[i];
4630 do {
4631 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4632 _bytes = ring->tx_stats.bytes;
4633 _packets = ring->tx_stats.packets;
4634 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4635 bytes += _bytes;
4636 packets += _packets;
4637 }
4638 net_stats->tx_bytes = bytes;
4639 net_stats->tx_packets = packets;
4640
4641 /* read stats registers */
4642 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4643 adapter->stats.gprc += rd32(E1000_GPRC);
4644 adapter->stats.gorc += rd32(E1000_GORCL);
4645 rd32(E1000_GORCH); /* clear GORCL */
4646 adapter->stats.bprc += rd32(E1000_BPRC);
4647 adapter->stats.mprc += rd32(E1000_MPRC);
4648 adapter->stats.roc += rd32(E1000_ROC);
4649
4650 adapter->stats.prc64 += rd32(E1000_PRC64);
4651 adapter->stats.prc127 += rd32(E1000_PRC127);
4652 adapter->stats.prc255 += rd32(E1000_PRC255);
4653 adapter->stats.prc511 += rd32(E1000_PRC511);
4654 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4655 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4656 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4657 adapter->stats.sec += rd32(E1000_SEC);
4658
4659 mpc = rd32(E1000_MPC);
4660 adapter->stats.mpc += mpc;
4661 net_stats->rx_fifo_errors += mpc;
4662 adapter->stats.scc += rd32(E1000_SCC);
4663 adapter->stats.ecol += rd32(E1000_ECOL);
4664 adapter->stats.mcc += rd32(E1000_MCC);
4665 adapter->stats.latecol += rd32(E1000_LATECOL);
4666 adapter->stats.dc += rd32(E1000_DC);
4667 adapter->stats.rlec += rd32(E1000_RLEC);
4668 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4669 adapter->stats.xontxc += rd32(E1000_XONTXC);
4670 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4671 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4672 adapter->stats.fcruc += rd32(E1000_FCRUC);
4673 adapter->stats.gptc += rd32(E1000_GPTC);
4674 adapter->stats.gotc += rd32(E1000_GOTCL);
4675 rd32(E1000_GOTCH); /* clear GOTCL */
4676 adapter->stats.rnbc += rd32(E1000_RNBC);
4677 adapter->stats.ruc += rd32(E1000_RUC);
4678 adapter->stats.rfc += rd32(E1000_RFC);
4679 adapter->stats.rjc += rd32(E1000_RJC);
4680 adapter->stats.tor += rd32(E1000_TORH);
4681 adapter->stats.tot += rd32(E1000_TOTH);
4682 adapter->stats.tpr += rd32(E1000_TPR);
4683
4684 adapter->stats.ptc64 += rd32(E1000_PTC64);
4685 adapter->stats.ptc127 += rd32(E1000_PTC127);
4686 adapter->stats.ptc255 += rd32(E1000_PTC255);
4687 adapter->stats.ptc511 += rd32(E1000_PTC511);
4688 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4689 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4690
4691 adapter->stats.mptc += rd32(E1000_MPTC);
4692 adapter->stats.bptc += rd32(E1000_BPTC);
4693
4694 adapter->stats.tpt += rd32(E1000_TPT);
4695 adapter->stats.colc += rd32(E1000_COLC);
4696
4697 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4698 /* read internal phy specific stats */
4699 reg = rd32(E1000_CTRL_EXT);
4700 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4701 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4702
4703 /* this stat has invalid values on i210/i211 */
4704 if ((hw->mac.type != e1000_i210) &&
4705 (hw->mac.type != e1000_i211))
4706 adapter->stats.tncrs += rd32(E1000_TNCRS);
4707 }
4708
4709 adapter->stats.tsctc += rd32(E1000_TSCTC);
4710 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4711
4712 adapter->stats.iac += rd32(E1000_IAC);
4713 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4714 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4715 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4716 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4717 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4718 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4719 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4720 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4721
4722 /* Fill out the OS statistics structure */
4723 net_stats->multicast = adapter->stats.mprc;
4724 net_stats->collisions = adapter->stats.colc;
4725
4726 /* Rx Errors */
4727
4728 /* RLEC on some newer hardware can be incorrect so build
4729 * our own version based on RUC and ROC */
4730 net_stats->rx_errors = adapter->stats.rxerrc +
4731 adapter->stats.crcerrs + adapter->stats.algnerrc +
4732 adapter->stats.ruc + adapter->stats.roc +
4733 adapter->stats.cexterr;
4734 net_stats->rx_length_errors = adapter->stats.ruc +
4735 adapter->stats.roc;
4736 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4737 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4738 net_stats->rx_missed_errors = adapter->stats.mpc;
4739
4740 /* Tx Errors */
4741 net_stats->tx_errors = adapter->stats.ecol +
4742 adapter->stats.latecol;
4743 net_stats->tx_aborted_errors = adapter->stats.ecol;
4744 net_stats->tx_window_errors = adapter->stats.latecol;
4745 net_stats->tx_carrier_errors = adapter->stats.tncrs;
4746
4747 /* Tx Dropped needs to be maintained elsewhere */
4748
4749 /* Phy Stats */
4750 if (hw->phy.media_type == e1000_media_type_copper) {
4751 if ((adapter->link_speed == SPEED_1000) &&
4752 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4753 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4754 adapter->phy_stats.idle_errors += phy_tmp;
4755 }
4756 }
4757
4758 /* Management Stats */
4759 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4760 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4761 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4762
4763 /* OS2BMC Stats */
4764 reg = rd32(E1000_MANC);
4765 if (reg & E1000_MANC_EN_BMC2OS) {
4766 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4767 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4768 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4769 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4770 }
4771 }
4772
4773 static irqreturn_t igb_msix_other(int irq, void *data)
4774 {
4775 struct igb_adapter *adapter = data;
4776 struct e1000_hw *hw = &adapter->hw;
4777 u32 icr = rd32(E1000_ICR);
4778 /* reading ICR causes bit 31 of EICR to be cleared */
4779
4780 if (icr & E1000_ICR_DRSTA)
4781 schedule_work(&adapter->reset_task);
4782
4783 if (icr & E1000_ICR_DOUTSYNC) {
4784 /* HW is reporting DMA is out of sync */
4785 adapter->stats.doosync++;
4786 /* The DMA Out of Sync is also indication of a spoof event
4787 * in IOV mode. Check the Wrong VM Behavior register to
4788 * see if it is really a spoof event. */
4789 igb_check_wvbr(adapter);
4790 }
4791
4792 /* Check for a mailbox event */
4793 if (icr & E1000_ICR_VMMB)
4794 igb_msg_task(adapter);
4795
4796 if (icr & E1000_ICR_LSC) {
4797 hw->mac.get_link_status = 1;
4798 /* guard against interrupt when we're going down */
4799 if (!test_bit(__IGB_DOWN, &adapter->state))
4800 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4801 }
4802
4803 #ifdef CONFIG_IGB_PTP
4804 if (icr & E1000_ICR_TS) {
4805 u32 tsicr = rd32(E1000_TSICR);
4806
4807 if (tsicr & E1000_TSICR_TXTS) {
4808 /* acknowledge the interrupt */
4809 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4810 /* retrieve hardware timestamp */
4811 schedule_work(&adapter->ptp_tx_work);
4812 }
4813 }
4814 #endif /* CONFIG_IGB_PTP */
4815
4816 wr32(E1000_EIMS, adapter->eims_other);
4817
4818 return IRQ_HANDLED;
4819 }
4820
4821 static void igb_write_itr(struct igb_q_vector *q_vector)
4822 {
4823 struct igb_adapter *adapter = q_vector->adapter;
4824 u32 itr_val = q_vector->itr_val & 0x7FFC;
4825
4826 if (!q_vector->set_itr)
4827 return;
4828
4829 if (!itr_val)
4830 itr_val = 0x4;
4831
4832 if (adapter->hw.mac.type == e1000_82575)
4833 itr_val |= itr_val << 16;
4834 else
4835 itr_val |= E1000_EITR_CNT_IGNR;
4836
4837 writel(itr_val, q_vector->itr_register);
4838 q_vector->set_itr = 0;
4839 }
4840
4841 static irqreturn_t igb_msix_ring(int irq, void *data)
4842 {
4843 struct igb_q_vector *q_vector = data;
4844
4845 /* Write the ITR value calculated from the previous interrupt. */
4846 igb_write_itr(q_vector);
4847
4848 napi_schedule(&q_vector->napi);
4849
4850 return IRQ_HANDLED;
4851 }
4852
4853 #ifdef CONFIG_IGB_DCA
4854 static void igb_update_tx_dca(struct igb_adapter *adapter,
4855 struct igb_ring *tx_ring,
4856 int cpu)
4857 {
4858 struct e1000_hw *hw = &adapter->hw;
4859 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4860
4861 if (hw->mac.type != e1000_82575)
4862 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4863
4864 /*
4865 * We can enable relaxed ordering for reads, but not writes when
4866 * DCA is enabled. This is due to a known issue in some chipsets
4867 * which will cause the DCA tag to be cleared.
4868 */
4869 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4870 E1000_DCA_TXCTRL_DATA_RRO_EN |
4871 E1000_DCA_TXCTRL_DESC_DCA_EN;
4872
4873 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4874 }
4875
4876 static void igb_update_rx_dca(struct igb_adapter *adapter,
4877 struct igb_ring *rx_ring,
4878 int cpu)
4879 {
4880 struct e1000_hw *hw = &adapter->hw;
4881 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4882
4883 if (hw->mac.type != e1000_82575)
4884 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4885
4886 /*
4887 * We can enable relaxed ordering for reads, but not writes when
4888 * DCA is enabled. This is due to a known issue in some chipsets
4889 * which will cause the DCA tag to be cleared.
4890 */
4891 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4892 E1000_DCA_RXCTRL_DESC_DCA_EN;
4893
4894 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4895 }
4896
4897 static void igb_update_dca(struct igb_q_vector *q_vector)
4898 {
4899 struct igb_adapter *adapter = q_vector->adapter;
4900 int cpu = get_cpu();
4901
4902 if (q_vector->cpu == cpu)
4903 goto out_no_update;
4904
4905 if (q_vector->tx.ring)
4906 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4907
4908 if (q_vector->rx.ring)
4909 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4910
4911 q_vector->cpu = cpu;
4912 out_no_update:
4913 put_cpu();
4914 }
4915
4916 static void igb_setup_dca(struct igb_adapter *adapter)
4917 {
4918 struct e1000_hw *hw = &adapter->hw;
4919 int i;
4920
4921 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4922 return;
4923
4924 /* Always use CB2 mode, difference is masked in the CB driver. */
4925 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4926
4927 for (i = 0; i < adapter->num_q_vectors; i++) {
4928 adapter->q_vector[i]->cpu = -1;
4929 igb_update_dca(adapter->q_vector[i]);
4930 }
4931 }
4932
4933 static int __igb_notify_dca(struct device *dev, void *data)
4934 {
4935 struct net_device *netdev = dev_get_drvdata(dev);
4936 struct igb_adapter *adapter = netdev_priv(netdev);
4937 struct pci_dev *pdev = adapter->pdev;
4938 struct e1000_hw *hw = &adapter->hw;
4939 unsigned long event = *(unsigned long *)data;
4940
4941 switch (event) {
4942 case DCA_PROVIDER_ADD:
4943 /* if already enabled, don't do it again */
4944 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4945 break;
4946 if (dca_add_requester(dev) == 0) {
4947 adapter->flags |= IGB_FLAG_DCA_ENABLED;
4948 dev_info(&pdev->dev, "DCA enabled\n");
4949 igb_setup_dca(adapter);
4950 break;
4951 }
4952 /* Fall Through since DCA is disabled. */
4953 case DCA_PROVIDER_REMOVE:
4954 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4955 /* without this a class_device is left
4956 * hanging around in the sysfs model */
4957 dca_remove_requester(dev);
4958 dev_info(&pdev->dev, "DCA disabled\n");
4959 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4960 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4961 }
4962 break;
4963 }
4964
4965 return 0;
4966 }
4967
4968 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4969 void *p)
4970 {
4971 int ret_val;
4972
4973 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4974 __igb_notify_dca);
4975
4976 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4977 }
4978 #endif /* CONFIG_IGB_DCA */
4979
4980 #ifdef CONFIG_PCI_IOV
4981 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4982 {
4983 unsigned char mac_addr[ETH_ALEN];
4984
4985 eth_random_addr(mac_addr);
4986 igb_set_vf_mac(adapter, vf, mac_addr);
4987
4988 return 0;
4989 }
4990
4991 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
4992 {
4993 struct pci_dev *pdev = adapter->pdev;
4994 struct pci_dev *vfdev;
4995 int dev_id;
4996
4997 switch (adapter->hw.mac.type) {
4998 case e1000_82576:
4999 dev_id = IGB_82576_VF_DEV_ID;
5000 break;
5001 case e1000_i350:
5002 dev_id = IGB_I350_VF_DEV_ID;
5003 break;
5004 default:
5005 return false;
5006 }
5007
5008 /* loop through all the VFs to see if we own any that are assigned */
5009 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5010 while (vfdev) {
5011 /* if we don't own it we don't care */
5012 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5013 /* if it is assigned we cannot release it */
5014 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
5015 return true;
5016 }
5017
5018 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
5019 }
5020
5021 return false;
5022 }
5023
5024 #endif
5025 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5026 {
5027 struct e1000_hw *hw = &adapter->hw;
5028 u32 ping;
5029 int i;
5030
5031 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5032 ping = E1000_PF_CONTROL_MSG;
5033 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5034 ping |= E1000_VT_MSGTYPE_CTS;
5035 igb_write_mbx(hw, &ping, 1, i);
5036 }
5037 }
5038
5039 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5040 {
5041 struct e1000_hw *hw = &adapter->hw;
5042 u32 vmolr = rd32(E1000_VMOLR(vf));
5043 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5044
5045 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5046 IGB_VF_FLAG_MULTI_PROMISC);
5047 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5048
5049 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5050 vmolr |= E1000_VMOLR_MPME;
5051 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5052 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5053 } else {
5054 /*
5055 * if we have hashes and we are clearing a multicast promisc
5056 * flag we need to write the hashes to the MTA as this step
5057 * was previously skipped
5058 */
5059 if (vf_data->num_vf_mc_hashes > 30) {
5060 vmolr |= E1000_VMOLR_MPME;
5061 } else if (vf_data->num_vf_mc_hashes) {
5062 int j;
5063 vmolr |= E1000_VMOLR_ROMPE;
5064 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5065 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5066 }
5067 }
5068
5069 wr32(E1000_VMOLR(vf), vmolr);
5070
5071 /* there are flags left unprocessed, likely not supported */
5072 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5073 return -EINVAL;
5074
5075 return 0;
5076
5077 }
5078
5079 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5080 u32 *msgbuf, u32 vf)
5081 {
5082 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5083 u16 *hash_list = (u16 *)&msgbuf[1];
5084 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5085 int i;
5086
5087 /* salt away the number of multicast addresses assigned
5088 * to this VF for later use to restore when the PF multi cast
5089 * list changes
5090 */
5091 vf_data->num_vf_mc_hashes = n;
5092
5093 /* only up to 30 hash values supported */
5094 if (n > 30)
5095 n = 30;
5096
5097 /* store the hashes for later use */
5098 for (i = 0; i < n; i++)
5099 vf_data->vf_mc_hashes[i] = hash_list[i];
5100
5101 /* Flush and reset the mta with the new values */
5102 igb_set_rx_mode(adapter->netdev);
5103
5104 return 0;
5105 }
5106
5107 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5108 {
5109 struct e1000_hw *hw = &adapter->hw;
5110 struct vf_data_storage *vf_data;
5111 int i, j;
5112
5113 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5114 u32 vmolr = rd32(E1000_VMOLR(i));
5115 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5116
5117 vf_data = &adapter->vf_data[i];
5118
5119 if ((vf_data->num_vf_mc_hashes > 30) ||
5120 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5121 vmolr |= E1000_VMOLR_MPME;
5122 } else if (vf_data->num_vf_mc_hashes) {
5123 vmolr |= E1000_VMOLR_ROMPE;
5124 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5125 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5126 }
5127 wr32(E1000_VMOLR(i), vmolr);
5128 }
5129 }
5130
5131 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5132 {
5133 struct e1000_hw *hw = &adapter->hw;
5134 u32 pool_mask, reg, vid;
5135 int i;
5136
5137 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5138
5139 /* Find the vlan filter for this id */
5140 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5141 reg = rd32(E1000_VLVF(i));
5142
5143 /* remove the vf from the pool */
5144 reg &= ~pool_mask;
5145
5146 /* if pool is empty then remove entry from vfta */
5147 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5148 (reg & E1000_VLVF_VLANID_ENABLE)) {
5149 reg = 0;
5150 vid = reg & E1000_VLVF_VLANID_MASK;
5151 igb_vfta_set(hw, vid, false);
5152 }
5153
5154 wr32(E1000_VLVF(i), reg);
5155 }
5156
5157 adapter->vf_data[vf].vlans_enabled = 0;
5158 }
5159
5160 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5161 {
5162 struct e1000_hw *hw = &adapter->hw;
5163 u32 reg, i;
5164
5165 /* The vlvf table only exists on 82576 hardware and newer */
5166 if (hw->mac.type < e1000_82576)
5167 return -1;
5168
5169 /* we only need to do this if VMDq is enabled */
5170 if (!adapter->vfs_allocated_count)
5171 return -1;
5172
5173 /* Find the vlan filter for this id */
5174 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5175 reg = rd32(E1000_VLVF(i));
5176 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5177 vid == (reg & E1000_VLVF_VLANID_MASK))
5178 break;
5179 }
5180
5181 if (add) {
5182 if (i == E1000_VLVF_ARRAY_SIZE) {
5183 /* Did not find a matching VLAN ID entry that was
5184 * enabled. Search for a free filter entry, i.e.
5185 * one without the enable bit set
5186 */
5187 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5188 reg = rd32(E1000_VLVF(i));
5189 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5190 break;
5191 }
5192 }
5193 if (i < E1000_VLVF_ARRAY_SIZE) {
5194 /* Found an enabled/available entry */
5195 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5196
5197 /* if !enabled we need to set this up in vfta */
5198 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5199 /* add VID to filter table */
5200 igb_vfta_set(hw, vid, true);
5201 reg |= E1000_VLVF_VLANID_ENABLE;
5202 }
5203 reg &= ~E1000_VLVF_VLANID_MASK;
5204 reg |= vid;
5205 wr32(E1000_VLVF(i), reg);
5206
5207 /* do not modify RLPML for PF devices */
5208 if (vf >= adapter->vfs_allocated_count)
5209 return 0;
5210
5211 if (!adapter->vf_data[vf].vlans_enabled) {
5212 u32 size;
5213 reg = rd32(E1000_VMOLR(vf));
5214 size = reg & E1000_VMOLR_RLPML_MASK;
5215 size += 4;
5216 reg &= ~E1000_VMOLR_RLPML_MASK;
5217 reg |= size;
5218 wr32(E1000_VMOLR(vf), reg);
5219 }
5220
5221 adapter->vf_data[vf].vlans_enabled++;
5222 }
5223 } else {
5224 if (i < E1000_VLVF_ARRAY_SIZE) {
5225 /* remove vf from the pool */
5226 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5227 /* if pool is empty then remove entry from vfta */
5228 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5229 reg = 0;
5230 igb_vfta_set(hw, vid, false);
5231 }
5232 wr32(E1000_VLVF(i), reg);
5233
5234 /* do not modify RLPML for PF devices */
5235 if (vf >= adapter->vfs_allocated_count)
5236 return 0;
5237
5238 adapter->vf_data[vf].vlans_enabled--;
5239 if (!adapter->vf_data[vf].vlans_enabled) {
5240 u32 size;
5241 reg = rd32(E1000_VMOLR(vf));
5242 size = reg & E1000_VMOLR_RLPML_MASK;
5243 size -= 4;
5244 reg &= ~E1000_VMOLR_RLPML_MASK;
5245 reg |= size;
5246 wr32(E1000_VMOLR(vf), reg);
5247 }
5248 }
5249 }
5250 return 0;
5251 }
5252
5253 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5254 {
5255 struct e1000_hw *hw = &adapter->hw;
5256
5257 if (vid)
5258 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5259 else
5260 wr32(E1000_VMVIR(vf), 0);
5261 }
5262
5263 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5264 int vf, u16 vlan, u8 qos)
5265 {
5266 int err = 0;
5267 struct igb_adapter *adapter = netdev_priv(netdev);
5268
5269 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5270 return -EINVAL;
5271 if (vlan || qos) {
5272 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5273 if (err)
5274 goto out;
5275 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5276 igb_set_vmolr(adapter, vf, !vlan);
5277 adapter->vf_data[vf].pf_vlan = vlan;
5278 adapter->vf_data[vf].pf_qos = qos;
5279 dev_info(&adapter->pdev->dev,
5280 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5281 if (test_bit(__IGB_DOWN, &adapter->state)) {
5282 dev_warn(&adapter->pdev->dev,
5283 "The VF VLAN has been set,"
5284 " but the PF device is not up.\n");
5285 dev_warn(&adapter->pdev->dev,
5286 "Bring the PF device up before"
5287 " attempting to use the VF device.\n");
5288 }
5289 } else {
5290 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5291 false, vf);
5292 igb_set_vmvir(adapter, vlan, vf);
5293 igb_set_vmolr(adapter, vf, true);
5294 adapter->vf_data[vf].pf_vlan = 0;
5295 adapter->vf_data[vf].pf_qos = 0;
5296 }
5297 out:
5298 return err;
5299 }
5300
5301 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5302 {
5303 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5304 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5305
5306 return igb_vlvf_set(adapter, vid, add, vf);
5307 }
5308
5309 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5310 {
5311 /* clear flags - except flag that indicates PF has set the MAC */
5312 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5313 adapter->vf_data[vf].last_nack = jiffies;
5314
5315 /* reset offloads to defaults */
5316 igb_set_vmolr(adapter, vf, true);
5317
5318 /* reset vlans for device */
5319 igb_clear_vf_vfta(adapter, vf);
5320 if (adapter->vf_data[vf].pf_vlan)
5321 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5322 adapter->vf_data[vf].pf_vlan,
5323 adapter->vf_data[vf].pf_qos);
5324 else
5325 igb_clear_vf_vfta(adapter, vf);
5326
5327 /* reset multicast table array for vf */
5328 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5329
5330 /* Flush and reset the mta with the new values */
5331 igb_set_rx_mode(adapter->netdev);
5332 }
5333
5334 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5335 {
5336 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5337
5338 /* generate a new mac address as we were hotplug removed/added */
5339 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5340 eth_random_addr(vf_mac);
5341
5342 /* process remaining reset events */
5343 igb_vf_reset(adapter, vf);
5344 }
5345
5346 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5347 {
5348 struct e1000_hw *hw = &adapter->hw;
5349 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5350 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5351 u32 reg, msgbuf[3];
5352 u8 *addr = (u8 *)(&msgbuf[1]);
5353
5354 /* process all the same items cleared in a function level reset */
5355 igb_vf_reset(adapter, vf);
5356
5357 /* set vf mac address */
5358 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5359
5360 /* enable transmit and receive for vf */
5361 reg = rd32(E1000_VFTE);
5362 wr32(E1000_VFTE, reg | (1 << vf));
5363 reg = rd32(E1000_VFRE);
5364 wr32(E1000_VFRE, reg | (1 << vf));
5365
5366 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5367
5368 /* reply to reset with ack and vf mac address */
5369 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5370 memcpy(addr, vf_mac, 6);
5371 igb_write_mbx(hw, msgbuf, 3, vf);
5372 }
5373
5374 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5375 {
5376 /*
5377 * The VF MAC Address is stored in a packed array of bytes
5378 * starting at the second 32 bit word of the msg array
5379 */
5380 unsigned char *addr = (char *)&msg[1];
5381 int err = -1;
5382
5383 if (is_valid_ether_addr(addr))
5384 err = igb_set_vf_mac(adapter, vf, addr);
5385
5386 return err;
5387 }
5388
5389 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5390 {
5391 struct e1000_hw *hw = &adapter->hw;
5392 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5393 u32 msg = E1000_VT_MSGTYPE_NACK;
5394
5395 /* if device isn't clear to send it shouldn't be reading either */
5396 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5397 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5398 igb_write_mbx(hw, &msg, 1, vf);
5399 vf_data->last_nack = jiffies;
5400 }
5401 }
5402
5403 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5404 {
5405 struct pci_dev *pdev = adapter->pdev;
5406 u32 msgbuf[E1000_VFMAILBOX_SIZE];
5407 struct e1000_hw *hw = &adapter->hw;
5408 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5409 s32 retval;
5410
5411 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5412
5413 if (retval) {
5414 /* if receive failed revoke VF CTS stats and restart init */
5415 dev_err(&pdev->dev, "Error receiving message from VF\n");
5416 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5417 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5418 return;
5419 goto out;
5420 }
5421
5422 /* this is a message we already processed, do nothing */
5423 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5424 return;
5425
5426 /*
5427 * until the vf completes a reset it should not be
5428 * allowed to start any configuration.
5429 */
5430
5431 if (msgbuf[0] == E1000_VF_RESET) {
5432 igb_vf_reset_msg(adapter, vf);
5433 return;
5434 }
5435
5436 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5437 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5438 return;
5439 retval = -1;
5440 goto out;
5441 }
5442
5443 switch ((msgbuf[0] & 0xFFFF)) {
5444 case E1000_VF_SET_MAC_ADDR:
5445 retval = -EINVAL;
5446 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5447 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5448 else
5449 dev_warn(&pdev->dev,
5450 "VF %d attempted to override administratively "
5451 "set MAC address\nReload the VF driver to "
5452 "resume operations\n", vf);
5453 break;
5454 case E1000_VF_SET_PROMISC:
5455 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5456 break;
5457 case E1000_VF_SET_MULTICAST:
5458 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5459 break;
5460 case E1000_VF_SET_LPE:
5461 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5462 break;
5463 case E1000_VF_SET_VLAN:
5464 retval = -1;
5465 if (vf_data->pf_vlan)
5466 dev_warn(&pdev->dev,
5467 "VF %d attempted to override administratively "
5468 "set VLAN tag\nReload the VF driver to "
5469 "resume operations\n", vf);
5470 else
5471 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5472 break;
5473 default:
5474 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5475 retval = -1;
5476 break;
5477 }
5478
5479 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5480 out:
5481 /* notify the VF of the results of what it sent us */
5482 if (retval)
5483 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5484 else
5485 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5486
5487 igb_write_mbx(hw, msgbuf, 1, vf);
5488 }
5489
5490 static void igb_msg_task(struct igb_adapter *adapter)
5491 {
5492 struct e1000_hw *hw = &adapter->hw;
5493 u32 vf;
5494
5495 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5496 /* process any reset requests */
5497 if (!igb_check_for_rst(hw, vf))
5498 igb_vf_reset_event(adapter, vf);
5499
5500 /* process any messages pending */
5501 if (!igb_check_for_msg(hw, vf))
5502 igb_rcv_msg_from_vf(adapter, vf);
5503
5504 /* process any acks */
5505 if (!igb_check_for_ack(hw, vf))
5506 igb_rcv_ack_from_vf(adapter, vf);
5507 }
5508 }
5509
5510 /**
5511 * igb_set_uta - Set unicast filter table address
5512 * @adapter: board private structure
5513 *
5514 * The unicast table address is a register array of 32-bit registers.
5515 * The table is meant to be used in a way similar to how the MTA is used
5516 * however due to certain limitations in the hardware it is necessary to
5517 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5518 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5519 **/
5520 static void igb_set_uta(struct igb_adapter *adapter)
5521 {
5522 struct e1000_hw *hw = &adapter->hw;
5523 int i;
5524
5525 /* The UTA table only exists on 82576 hardware and newer */
5526 if (hw->mac.type < e1000_82576)
5527 return;
5528
5529 /* we only need to do this if VMDq is enabled */
5530 if (!adapter->vfs_allocated_count)
5531 return;
5532
5533 for (i = 0; i < hw->mac.uta_reg_count; i++)
5534 array_wr32(E1000_UTA, i, ~0);
5535 }
5536
5537 /**
5538 * igb_intr_msi - Interrupt Handler
5539 * @irq: interrupt number
5540 * @data: pointer to a network interface device structure
5541 **/
5542 static irqreturn_t igb_intr_msi(int irq, void *data)
5543 {
5544 struct igb_adapter *adapter = data;
5545 struct igb_q_vector *q_vector = adapter->q_vector[0];
5546 struct e1000_hw *hw = &adapter->hw;
5547 /* read ICR disables interrupts using IAM */
5548 u32 icr = rd32(E1000_ICR);
5549
5550 igb_write_itr(q_vector);
5551
5552 if (icr & E1000_ICR_DRSTA)
5553 schedule_work(&adapter->reset_task);
5554
5555 if (icr & E1000_ICR_DOUTSYNC) {
5556 /* HW is reporting DMA is out of sync */
5557 adapter->stats.doosync++;
5558 }
5559
5560 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5561 hw->mac.get_link_status = 1;
5562 if (!test_bit(__IGB_DOWN, &adapter->state))
5563 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5564 }
5565
5566 #ifdef CONFIG_IGB_PTP
5567 if (icr & E1000_ICR_TS) {
5568 u32 tsicr = rd32(E1000_TSICR);
5569
5570 if (tsicr & E1000_TSICR_TXTS) {
5571 /* acknowledge the interrupt */
5572 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5573 /* retrieve hardware timestamp */
5574 schedule_work(&adapter->ptp_tx_work);
5575 }
5576 }
5577 #endif /* CONFIG_IGB_PTP */
5578
5579 napi_schedule(&q_vector->napi);
5580
5581 return IRQ_HANDLED;
5582 }
5583
5584 /**
5585 * igb_intr - Legacy Interrupt Handler
5586 * @irq: interrupt number
5587 * @data: pointer to a network interface device structure
5588 **/
5589 static irqreturn_t igb_intr(int irq, void *data)
5590 {
5591 struct igb_adapter *adapter = data;
5592 struct igb_q_vector *q_vector = adapter->q_vector[0];
5593 struct e1000_hw *hw = &adapter->hw;
5594 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5595 * need for the IMC write */
5596 u32 icr = rd32(E1000_ICR);
5597
5598 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5599 * not set, then the adapter didn't send an interrupt */
5600 if (!(icr & E1000_ICR_INT_ASSERTED))
5601 return IRQ_NONE;
5602
5603 igb_write_itr(q_vector);
5604
5605 if (icr & E1000_ICR_DRSTA)
5606 schedule_work(&adapter->reset_task);
5607
5608 if (icr & E1000_ICR_DOUTSYNC) {
5609 /* HW is reporting DMA is out of sync */
5610 adapter->stats.doosync++;
5611 }
5612
5613 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5614 hw->mac.get_link_status = 1;
5615 /* guard against interrupt when we're going down */
5616 if (!test_bit(__IGB_DOWN, &adapter->state))
5617 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5618 }
5619
5620 #ifdef CONFIG_IGB_PTP
5621 if (icr & E1000_ICR_TS) {
5622 u32 tsicr = rd32(E1000_TSICR);
5623
5624 if (tsicr & E1000_TSICR_TXTS) {
5625 /* acknowledge the interrupt */
5626 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5627 /* retrieve hardware timestamp */
5628 schedule_work(&adapter->ptp_tx_work);
5629 }
5630 }
5631 #endif /* CONFIG_IGB_PTP */
5632
5633 napi_schedule(&q_vector->napi);
5634
5635 return IRQ_HANDLED;
5636 }
5637
5638 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5639 {
5640 struct igb_adapter *adapter = q_vector->adapter;
5641 struct e1000_hw *hw = &adapter->hw;
5642
5643 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5644 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5645 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5646 igb_set_itr(q_vector);
5647 else
5648 igb_update_ring_itr(q_vector);
5649 }
5650
5651 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5652 if (adapter->msix_entries)
5653 wr32(E1000_EIMS, q_vector->eims_value);
5654 else
5655 igb_irq_enable(adapter);
5656 }
5657 }
5658
5659 /**
5660 * igb_poll - NAPI Rx polling callback
5661 * @napi: napi polling structure
5662 * @budget: count of how many packets we should handle
5663 **/
5664 static int igb_poll(struct napi_struct *napi, int budget)
5665 {
5666 struct igb_q_vector *q_vector = container_of(napi,
5667 struct igb_q_vector,
5668 napi);
5669 bool clean_complete = true;
5670
5671 #ifdef CONFIG_IGB_DCA
5672 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5673 igb_update_dca(q_vector);
5674 #endif
5675 if (q_vector->tx.ring)
5676 clean_complete = igb_clean_tx_irq(q_vector);
5677
5678 if (q_vector->rx.ring)
5679 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5680
5681 /* If all work not completed, return budget and keep polling */
5682 if (!clean_complete)
5683 return budget;
5684
5685 /* If not enough Rx work done, exit the polling mode */
5686 napi_complete(napi);
5687 igb_ring_irq_enable(q_vector);
5688
5689 return 0;
5690 }
5691
5692 /**
5693 * igb_clean_tx_irq - Reclaim resources after transmit completes
5694 * @q_vector: pointer to q_vector containing needed info
5695 *
5696 * returns true if ring is completely cleaned
5697 **/
5698 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5699 {
5700 struct igb_adapter *adapter = q_vector->adapter;
5701 struct igb_ring *tx_ring = q_vector->tx.ring;
5702 struct igb_tx_buffer *tx_buffer;
5703 union e1000_adv_tx_desc *tx_desc;
5704 unsigned int total_bytes = 0, total_packets = 0;
5705 unsigned int budget = q_vector->tx.work_limit;
5706 unsigned int i = tx_ring->next_to_clean;
5707
5708 if (test_bit(__IGB_DOWN, &adapter->state))
5709 return true;
5710
5711 tx_buffer = &tx_ring->tx_buffer_info[i];
5712 tx_desc = IGB_TX_DESC(tx_ring, i);
5713 i -= tx_ring->count;
5714
5715 do {
5716 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5717
5718 /* if next_to_watch is not set then there is no work pending */
5719 if (!eop_desc)
5720 break;
5721
5722 /* prevent any other reads prior to eop_desc */
5723 rmb();
5724
5725 /* if DD is not set pending work has not been completed */
5726 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5727 break;
5728
5729 /* clear next_to_watch to prevent false hangs */
5730 tx_buffer->next_to_watch = NULL;
5731
5732 /* update the statistics for this packet */
5733 total_bytes += tx_buffer->bytecount;
5734 total_packets += tx_buffer->gso_segs;
5735
5736 /* free the skb */
5737 dev_kfree_skb_any(tx_buffer->skb);
5738
5739 /* unmap skb header data */
5740 dma_unmap_single(tx_ring->dev,
5741 dma_unmap_addr(tx_buffer, dma),
5742 dma_unmap_len(tx_buffer, len),
5743 DMA_TO_DEVICE);
5744
5745 /* clear tx_buffer data */
5746 tx_buffer->skb = NULL;
5747 dma_unmap_len_set(tx_buffer, len, 0);
5748
5749 /* clear last DMA location and unmap remaining buffers */
5750 while (tx_desc != eop_desc) {
5751 tx_buffer++;
5752 tx_desc++;
5753 i++;
5754 if (unlikely(!i)) {
5755 i -= tx_ring->count;
5756 tx_buffer = tx_ring->tx_buffer_info;
5757 tx_desc = IGB_TX_DESC(tx_ring, 0);
5758 }
5759
5760 /* unmap any remaining paged data */
5761 if (dma_unmap_len(tx_buffer, len)) {
5762 dma_unmap_page(tx_ring->dev,
5763 dma_unmap_addr(tx_buffer, dma),
5764 dma_unmap_len(tx_buffer, len),
5765 DMA_TO_DEVICE);
5766 dma_unmap_len_set(tx_buffer, len, 0);
5767 }
5768 }
5769
5770 /* move us one more past the eop_desc for start of next pkt */
5771 tx_buffer++;
5772 tx_desc++;
5773 i++;
5774 if (unlikely(!i)) {
5775 i -= tx_ring->count;
5776 tx_buffer = tx_ring->tx_buffer_info;
5777 tx_desc = IGB_TX_DESC(tx_ring, 0);
5778 }
5779
5780 /* issue prefetch for next Tx descriptor */
5781 prefetch(tx_desc);
5782
5783 /* update budget accounting */
5784 budget--;
5785 } while (likely(budget));
5786
5787 netdev_tx_completed_queue(txring_txq(tx_ring),
5788 total_packets, total_bytes);
5789 i += tx_ring->count;
5790 tx_ring->next_to_clean = i;
5791 u64_stats_update_begin(&tx_ring->tx_syncp);
5792 tx_ring->tx_stats.bytes += total_bytes;
5793 tx_ring->tx_stats.packets += total_packets;
5794 u64_stats_update_end(&tx_ring->tx_syncp);
5795 q_vector->tx.total_bytes += total_bytes;
5796 q_vector->tx.total_packets += total_packets;
5797
5798 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
5799 struct e1000_hw *hw = &adapter->hw;
5800
5801 /* Detect a transmit hang in hardware, this serializes the
5802 * check with the clearing of time_stamp and movement of i */
5803 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5804 if (tx_buffer->next_to_watch &&
5805 time_after(jiffies, tx_buffer->time_stamp +
5806 (adapter->tx_timeout_factor * HZ)) &&
5807 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5808
5809 /* detected Tx unit hang */
5810 dev_err(tx_ring->dev,
5811 "Detected Tx Unit Hang\n"
5812 " Tx Queue <%d>\n"
5813 " TDH <%x>\n"
5814 " TDT <%x>\n"
5815 " next_to_use <%x>\n"
5816 " next_to_clean <%x>\n"
5817 "buffer_info[next_to_clean]\n"
5818 " time_stamp <%lx>\n"
5819 " next_to_watch <%p>\n"
5820 " jiffies <%lx>\n"
5821 " desc.status <%x>\n",
5822 tx_ring->queue_index,
5823 rd32(E1000_TDH(tx_ring->reg_idx)),
5824 readl(tx_ring->tail),
5825 tx_ring->next_to_use,
5826 tx_ring->next_to_clean,
5827 tx_buffer->time_stamp,
5828 tx_buffer->next_to_watch,
5829 jiffies,
5830 tx_buffer->next_to_watch->wb.status);
5831 netif_stop_subqueue(tx_ring->netdev,
5832 tx_ring->queue_index);
5833
5834 /* we are about to reset, no point in enabling stuff */
5835 return true;
5836 }
5837 }
5838
5839 if (unlikely(total_packets &&
5840 netif_carrier_ok(tx_ring->netdev) &&
5841 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5842 /* Make sure that anybody stopping the queue after this
5843 * sees the new next_to_clean.
5844 */
5845 smp_mb();
5846 if (__netif_subqueue_stopped(tx_ring->netdev,
5847 tx_ring->queue_index) &&
5848 !(test_bit(__IGB_DOWN, &adapter->state))) {
5849 netif_wake_subqueue(tx_ring->netdev,
5850 tx_ring->queue_index);
5851
5852 u64_stats_update_begin(&tx_ring->tx_syncp);
5853 tx_ring->tx_stats.restart_queue++;
5854 u64_stats_update_end(&tx_ring->tx_syncp);
5855 }
5856 }
5857
5858 return !!budget;
5859 }
5860
5861 /**
5862 * igb_reuse_rx_page - page flip buffer and store it back on the ring
5863 * @rx_ring: rx descriptor ring to store buffers on
5864 * @old_buff: donor buffer to have page reused
5865 *
5866 * Synchronizes page for reuse by the adapter
5867 **/
5868 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5869 struct igb_rx_buffer *old_buff)
5870 {
5871 struct igb_rx_buffer *new_buff;
5872 u16 nta = rx_ring->next_to_alloc;
5873
5874 new_buff = &rx_ring->rx_buffer_info[nta];
5875
5876 /* update, and store next to alloc */
5877 nta++;
5878 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5879
5880 /* transfer page from old buffer to new buffer */
5881 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5882
5883 /* sync the buffer for use by the device */
5884 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5885 old_buff->page_offset,
5886 IGB_RX_BUFSZ,
5887 DMA_FROM_DEVICE);
5888 }
5889
5890 /**
5891 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5892 * @rx_ring: rx descriptor ring to transact packets on
5893 * @rx_buffer: buffer containing page to add
5894 * @rx_desc: descriptor containing length of buffer written by hardware
5895 * @skb: sk_buff to place the data into
5896 *
5897 * This function will add the data contained in rx_buffer->page to the skb.
5898 * This is done either through a direct copy if the data in the buffer is
5899 * less than the skb header size, otherwise it will just attach the page as
5900 * a frag to the skb.
5901 *
5902 * The function will then update the page offset if necessary and return
5903 * true if the buffer can be reused by the adapter.
5904 **/
5905 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5906 struct igb_rx_buffer *rx_buffer,
5907 union e1000_adv_rx_desc *rx_desc,
5908 struct sk_buff *skb)
5909 {
5910 struct page *page = rx_buffer->page;
5911 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5912
5913 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5914 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5915
5916 #ifdef CONFIG_IGB_PTP
5917 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5918 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5919 va += IGB_TS_HDR_LEN;
5920 size -= IGB_TS_HDR_LEN;
5921 }
5922
5923 #endif
5924 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5925
5926 /* we can reuse buffer as-is, just make sure it is local */
5927 if (likely(page_to_nid(page) == numa_node_id()))
5928 return true;
5929
5930 /* this page cannot be reused so discard it */
5931 put_page(page);
5932 return false;
5933 }
5934
5935 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
5936 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
5937
5938 /* avoid re-using remote pages */
5939 if (unlikely(page_to_nid(page) != numa_node_id()))
5940 return false;
5941
5942 #if (PAGE_SIZE < 8192)
5943 /* if we are only owner of page we can reuse it */
5944 if (unlikely(page_count(page) != 1))
5945 return false;
5946
5947 /* flip page offset to other buffer */
5948 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
5949
5950 /*
5951 * since we are the only owner of the page and we need to
5952 * increment it, just set the value to 2 in order to avoid
5953 * an unnecessary locked operation
5954 */
5955 atomic_set(&page->_count, 2);
5956 #else
5957 /* move offset up to the next cache line */
5958 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5959
5960 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5961 return false;
5962
5963 /* bump ref count on page before it is given to the stack */
5964 get_page(page);
5965 #endif
5966
5967 return true;
5968 }
5969
5970 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5971 union e1000_adv_rx_desc *rx_desc,
5972 struct sk_buff *skb)
5973 {
5974 struct igb_rx_buffer *rx_buffer;
5975 struct page *page;
5976
5977 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5978
5979 /*
5980 * This memory barrier is needed to keep us from reading
5981 * any other fields out of the rx_desc until we know the
5982 * RXD_STAT_DD bit is set
5983 */
5984 rmb();
5985
5986 page = rx_buffer->page;
5987 prefetchw(page);
5988
5989 if (likely(!skb)) {
5990 void *page_addr = page_address(page) +
5991 rx_buffer->page_offset;
5992
5993 /* prefetch first cache line of first page */
5994 prefetch(page_addr);
5995 #if L1_CACHE_BYTES < 128
5996 prefetch(page_addr + L1_CACHE_BYTES);
5997 #endif
5998
5999 /* allocate a skb to store the frags */
6000 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6001 IGB_RX_HDR_LEN);
6002 if (unlikely(!skb)) {
6003 rx_ring->rx_stats.alloc_failed++;
6004 return NULL;
6005 }
6006
6007 /*
6008 * we will be copying header into skb->data in
6009 * pskb_may_pull so it is in our interest to prefetch
6010 * it now to avoid a possible cache miss
6011 */
6012 prefetchw(skb->data);
6013 }
6014
6015 /* we are reusing so sync this buffer for CPU use */
6016 dma_sync_single_range_for_cpu(rx_ring->dev,
6017 rx_buffer->dma,
6018 rx_buffer->page_offset,
6019 IGB_RX_BUFSZ,
6020 DMA_FROM_DEVICE);
6021
6022 /* pull page into skb */
6023 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6024 /* hand second half of page back to the ring */
6025 igb_reuse_rx_page(rx_ring, rx_buffer);
6026 } else {
6027 /* we are not reusing the buffer so unmap it */
6028 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6029 PAGE_SIZE, DMA_FROM_DEVICE);
6030 }
6031
6032 /* clear contents of rx_buffer */
6033 rx_buffer->page = NULL;
6034
6035 return skb;
6036 }
6037
6038 static inline void igb_rx_checksum(struct igb_ring *ring,
6039 union e1000_adv_rx_desc *rx_desc,
6040 struct sk_buff *skb)
6041 {
6042 skb_checksum_none_assert(skb);
6043
6044 /* Ignore Checksum bit is set */
6045 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6046 return;
6047
6048 /* Rx checksum disabled via ethtool */
6049 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6050 return;
6051
6052 /* TCP/UDP checksum error bit is set */
6053 if (igb_test_staterr(rx_desc,
6054 E1000_RXDEXT_STATERR_TCPE |
6055 E1000_RXDEXT_STATERR_IPE)) {
6056 /*
6057 * work around errata with sctp packets where the TCPE aka
6058 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6059 * packets, (aka let the stack check the crc32c)
6060 */
6061 if (!((skb->len == 60) &&
6062 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6063 u64_stats_update_begin(&ring->rx_syncp);
6064 ring->rx_stats.csum_err++;
6065 u64_stats_update_end(&ring->rx_syncp);
6066 }
6067 /* let the stack verify checksum errors */
6068 return;
6069 }
6070 /* It must be a TCP or UDP packet with a valid checksum */
6071 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6072 E1000_RXD_STAT_UDPCS))
6073 skb->ip_summed = CHECKSUM_UNNECESSARY;
6074
6075 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6076 le32_to_cpu(rx_desc->wb.upper.status_error));
6077 }
6078
6079 static inline void igb_rx_hash(struct igb_ring *ring,
6080 union e1000_adv_rx_desc *rx_desc,
6081 struct sk_buff *skb)
6082 {
6083 if (ring->netdev->features & NETIF_F_RXHASH)
6084 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6085 }
6086
6087 /**
6088 * igb_is_non_eop - process handling of non-EOP buffers
6089 * @rx_ring: Rx ring being processed
6090 * @rx_desc: Rx descriptor for current buffer
6091 * @skb: current socket buffer containing buffer in progress
6092 *
6093 * This function updates next to clean. If the buffer is an EOP buffer
6094 * this function exits returning false, otherwise it will place the
6095 * sk_buff in the next buffer to be chained and return true indicating
6096 * that this is in fact a non-EOP buffer.
6097 **/
6098 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6099 union e1000_adv_rx_desc *rx_desc)
6100 {
6101 u32 ntc = rx_ring->next_to_clean + 1;
6102
6103 /* fetch, update, and store next to clean */
6104 ntc = (ntc < rx_ring->count) ? ntc : 0;
6105 rx_ring->next_to_clean = ntc;
6106
6107 prefetch(IGB_RX_DESC(rx_ring, ntc));
6108
6109 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6110 return false;
6111
6112 return true;
6113 }
6114
6115 /**
6116 * igb_get_headlen - determine size of header for LRO/GRO
6117 * @data: pointer to the start of the headers
6118 * @max_len: total length of section to find headers in
6119 *
6120 * This function is meant to determine the length of headers that will
6121 * be recognized by hardware for LRO, and GRO offloads. The main
6122 * motivation of doing this is to only perform one pull for IPv4 TCP
6123 * packets so that we can do basic things like calculating the gso_size
6124 * based on the average data per packet.
6125 **/
6126 static unsigned int igb_get_headlen(unsigned char *data,
6127 unsigned int max_len)
6128 {
6129 union {
6130 unsigned char *network;
6131 /* l2 headers */
6132 struct ethhdr *eth;
6133 struct vlan_hdr *vlan;
6134 /* l3 headers */
6135 struct iphdr *ipv4;
6136 struct ipv6hdr *ipv6;
6137 } hdr;
6138 __be16 protocol;
6139 u8 nexthdr = 0; /* default to not TCP */
6140 u8 hlen;
6141
6142 /* this should never happen, but better safe than sorry */
6143 if (max_len < ETH_HLEN)
6144 return max_len;
6145
6146 /* initialize network frame pointer */
6147 hdr.network = data;
6148
6149 /* set first protocol and move network header forward */
6150 protocol = hdr.eth->h_proto;
6151 hdr.network += ETH_HLEN;
6152
6153 /* handle any vlan tag if present */
6154 if (protocol == __constant_htons(ETH_P_8021Q)) {
6155 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6156 return max_len;
6157
6158 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6159 hdr.network += VLAN_HLEN;
6160 }
6161
6162 /* handle L3 protocols */
6163 if (protocol == __constant_htons(ETH_P_IP)) {
6164 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6165 return max_len;
6166
6167 /* access ihl as a u8 to avoid unaligned access on ia64 */
6168 hlen = (hdr.network[0] & 0x0F) << 2;
6169
6170 /* verify hlen meets minimum size requirements */
6171 if (hlen < sizeof(struct iphdr))
6172 return hdr.network - data;
6173
6174 /* record next protocol */
6175 nexthdr = hdr.ipv4->protocol;
6176 hdr.network += hlen;
6177 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6178 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6179 return max_len;
6180
6181 /* record next protocol */
6182 nexthdr = hdr.ipv6->nexthdr;
6183 hdr.network += sizeof(struct ipv6hdr);
6184 } else {
6185 return hdr.network - data;
6186 }
6187
6188 /* finally sort out TCP */
6189 if (nexthdr == IPPROTO_TCP) {
6190 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6191 return max_len;
6192
6193 /* access doff as a u8 to avoid unaligned access on ia64 */
6194 hlen = (hdr.network[12] & 0xF0) >> 2;
6195
6196 /* verify hlen meets minimum size requirements */
6197 if (hlen < sizeof(struct tcphdr))
6198 return hdr.network - data;
6199
6200 hdr.network += hlen;
6201 } else if (nexthdr == IPPROTO_UDP) {
6202 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6203 return max_len;
6204
6205 hdr.network += sizeof(struct udphdr);
6206 }
6207
6208 /*
6209 * If everything has gone correctly hdr.network should be the
6210 * data section of the packet and will be the end of the header.
6211 * If not then it probably represents the end of the last recognized
6212 * header.
6213 */
6214 if ((hdr.network - data) < max_len)
6215 return hdr.network - data;
6216 else
6217 return max_len;
6218 }
6219
6220 /**
6221 * igb_pull_tail - igb specific version of skb_pull_tail
6222 * @rx_ring: rx descriptor ring packet is being transacted on
6223 * @rx_desc: pointer to the EOP Rx descriptor
6224 * @skb: pointer to current skb being adjusted
6225 *
6226 * This function is an igb specific version of __pskb_pull_tail. The
6227 * main difference between this version and the original function is that
6228 * this function can make several assumptions about the state of things
6229 * that allow for significant optimizations versus the standard function.
6230 * As a result we can do things like drop a frag and maintain an accurate
6231 * truesize for the skb.
6232 */
6233 static void igb_pull_tail(struct igb_ring *rx_ring,
6234 union e1000_adv_rx_desc *rx_desc,
6235 struct sk_buff *skb)
6236 {
6237 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6238 unsigned char *va;
6239 unsigned int pull_len;
6240
6241 /*
6242 * it is valid to use page_address instead of kmap since we are
6243 * working with pages allocated out of the lomem pool per
6244 * alloc_page(GFP_ATOMIC)
6245 */
6246 va = skb_frag_address(frag);
6247
6248 #ifdef CONFIG_IGB_PTP
6249 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6250 /* retrieve timestamp from buffer */
6251 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6252
6253 /* update pointers to remove timestamp header */
6254 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6255 frag->page_offset += IGB_TS_HDR_LEN;
6256 skb->data_len -= IGB_TS_HDR_LEN;
6257 skb->len -= IGB_TS_HDR_LEN;
6258
6259 /* move va to start of packet data */
6260 va += IGB_TS_HDR_LEN;
6261 }
6262
6263 #endif
6264 /*
6265 * we need the header to contain the greater of either ETH_HLEN or
6266 * 60 bytes if the skb->len is less than 60 for skb_pad.
6267 */
6268 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6269
6270 /* align pull length to size of long to optimize memcpy performance */
6271 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6272
6273 /* update all of the pointers */
6274 skb_frag_size_sub(frag, pull_len);
6275 frag->page_offset += pull_len;
6276 skb->data_len -= pull_len;
6277 skb->tail += pull_len;
6278 }
6279
6280 /**
6281 * igb_cleanup_headers - Correct corrupted or empty headers
6282 * @rx_ring: rx descriptor ring packet is being transacted on
6283 * @rx_desc: pointer to the EOP Rx descriptor
6284 * @skb: pointer to current skb being fixed
6285 *
6286 * Address the case where we are pulling data in on pages only
6287 * and as such no data is present in the skb header.
6288 *
6289 * In addition if skb is not at least 60 bytes we need to pad it so that
6290 * it is large enough to qualify as a valid Ethernet frame.
6291 *
6292 * Returns true if an error was encountered and skb was freed.
6293 **/
6294 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6295 union e1000_adv_rx_desc *rx_desc,
6296 struct sk_buff *skb)
6297 {
6298
6299 if (unlikely((igb_test_staterr(rx_desc,
6300 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6301 struct net_device *netdev = rx_ring->netdev;
6302 if (!(netdev->features & NETIF_F_RXALL)) {
6303 dev_kfree_skb_any(skb);
6304 return true;
6305 }
6306 }
6307
6308 /* place header in linear portion of buffer */
6309 if (skb_is_nonlinear(skb))
6310 igb_pull_tail(rx_ring, rx_desc, skb);
6311
6312 /* if skb_pad returns an error the skb was freed */
6313 if (unlikely(skb->len < 60)) {
6314 int pad_len = 60 - skb->len;
6315
6316 if (skb_pad(skb, pad_len))
6317 return true;
6318 __skb_put(skb, pad_len);
6319 }
6320
6321 return false;
6322 }
6323
6324 /**
6325 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6326 * @rx_ring: rx descriptor ring packet is being transacted on
6327 * @rx_desc: pointer to the EOP Rx descriptor
6328 * @skb: pointer to current skb being populated
6329 *
6330 * This function checks the ring, descriptor, and packet information in
6331 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6332 * other fields within the skb.
6333 **/
6334 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6335 union e1000_adv_rx_desc *rx_desc,
6336 struct sk_buff *skb)
6337 {
6338 struct net_device *dev = rx_ring->netdev;
6339
6340 igb_rx_hash(rx_ring, rx_desc, skb);
6341
6342 igb_rx_checksum(rx_ring, rx_desc, skb);
6343
6344 #ifdef CONFIG_IGB_PTP
6345 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6346 #endif /* CONFIG_IGB_PTP */
6347
6348 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6349 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6350 u16 vid;
6351 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6352 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6353 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6354 else
6355 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6356
6357 __vlan_hwaccel_put_tag(skb, vid);
6358 }
6359
6360 skb_record_rx_queue(skb, rx_ring->queue_index);
6361
6362 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6363 }
6364
6365 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6366 {
6367 struct igb_ring *rx_ring = q_vector->rx.ring;
6368 struct sk_buff *skb = rx_ring->skb;
6369 unsigned int total_bytes = 0, total_packets = 0;
6370 u16 cleaned_count = igb_desc_unused(rx_ring);
6371
6372 do {
6373 union e1000_adv_rx_desc *rx_desc;
6374
6375 /* return some buffers to hardware, one at a time is too slow */
6376 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6377 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6378 cleaned_count = 0;
6379 }
6380
6381 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6382
6383 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6384 break;
6385
6386 /* retrieve a buffer from the ring */
6387 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6388
6389 /* exit if we failed to retrieve a buffer */
6390 if (!skb)
6391 break;
6392
6393 cleaned_count++;
6394
6395 /* fetch next buffer in frame if non-eop */
6396 if (igb_is_non_eop(rx_ring, rx_desc))
6397 continue;
6398
6399 /* verify the packet layout is correct */
6400 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6401 skb = NULL;
6402 continue;
6403 }
6404
6405 /* probably a little skewed due to removing CRC */
6406 total_bytes += skb->len;
6407
6408 /* populate checksum, timestamp, VLAN, and protocol */
6409 igb_process_skb_fields(rx_ring, rx_desc, skb);
6410
6411 napi_gro_receive(&q_vector->napi, skb);
6412
6413 /* reset skb pointer */
6414 skb = NULL;
6415
6416 /* update budget accounting */
6417 total_packets++;
6418 } while (likely(total_packets < budget));
6419
6420 /* place incomplete frames back on ring for completion */
6421 rx_ring->skb = skb;
6422
6423 u64_stats_update_begin(&rx_ring->rx_syncp);
6424 rx_ring->rx_stats.packets += total_packets;
6425 rx_ring->rx_stats.bytes += total_bytes;
6426 u64_stats_update_end(&rx_ring->rx_syncp);
6427 q_vector->rx.total_packets += total_packets;
6428 q_vector->rx.total_bytes += total_bytes;
6429
6430 if (cleaned_count)
6431 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6432
6433 return (total_packets < budget);
6434 }
6435
6436 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6437 struct igb_rx_buffer *bi)
6438 {
6439 struct page *page = bi->page;
6440 dma_addr_t dma;
6441
6442 /* since we are recycling buffers we should seldom need to alloc */
6443 if (likely(page))
6444 return true;
6445
6446 /* alloc new page for storage */
6447 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6448 if (unlikely(!page)) {
6449 rx_ring->rx_stats.alloc_failed++;
6450 return false;
6451 }
6452
6453 /* map page for use */
6454 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6455
6456 /*
6457 * if mapping failed free memory back to system since
6458 * there isn't much point in holding memory we can't use
6459 */
6460 if (dma_mapping_error(rx_ring->dev, dma)) {
6461 __free_page(page);
6462
6463 rx_ring->rx_stats.alloc_failed++;
6464 return false;
6465 }
6466
6467 bi->dma = dma;
6468 bi->page = page;
6469 bi->page_offset = 0;
6470
6471 return true;
6472 }
6473
6474 /**
6475 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6476 * @adapter: address of board private structure
6477 **/
6478 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6479 {
6480 union e1000_adv_rx_desc *rx_desc;
6481 struct igb_rx_buffer *bi;
6482 u16 i = rx_ring->next_to_use;
6483
6484 /* nothing to do */
6485 if (!cleaned_count)
6486 return;
6487
6488 rx_desc = IGB_RX_DESC(rx_ring, i);
6489 bi = &rx_ring->rx_buffer_info[i];
6490 i -= rx_ring->count;
6491
6492 do {
6493 if (!igb_alloc_mapped_page(rx_ring, bi))
6494 break;
6495
6496 /*
6497 * Refresh the desc even if buffer_addrs didn't change
6498 * because each write-back erases this info.
6499 */
6500 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6501
6502 rx_desc++;
6503 bi++;
6504 i++;
6505 if (unlikely(!i)) {
6506 rx_desc = IGB_RX_DESC(rx_ring, 0);
6507 bi = rx_ring->rx_buffer_info;
6508 i -= rx_ring->count;
6509 }
6510
6511 /* clear the hdr_addr for the next_to_use descriptor */
6512 rx_desc->read.hdr_addr = 0;
6513
6514 cleaned_count--;
6515 } while (cleaned_count);
6516
6517 i += rx_ring->count;
6518
6519 if (rx_ring->next_to_use != i) {
6520 /* record the next descriptor to use */
6521 rx_ring->next_to_use = i;
6522
6523 /* update next to alloc since we have filled the ring */
6524 rx_ring->next_to_alloc = i;
6525
6526 /*
6527 * Force memory writes to complete before letting h/w
6528 * know there are new descriptors to fetch. (Only
6529 * applicable for weak-ordered memory model archs,
6530 * such as IA-64).
6531 */
6532 wmb();
6533 writel(i, rx_ring->tail);
6534 }
6535 }
6536
6537 /**
6538 * igb_mii_ioctl -
6539 * @netdev:
6540 * @ifreq:
6541 * @cmd:
6542 **/
6543 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6544 {
6545 struct igb_adapter *adapter = netdev_priv(netdev);
6546 struct mii_ioctl_data *data = if_mii(ifr);
6547
6548 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6549 return -EOPNOTSUPP;
6550
6551 switch (cmd) {
6552 case SIOCGMIIPHY:
6553 data->phy_id = adapter->hw.phy.addr;
6554 break;
6555 case SIOCGMIIREG:
6556 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6557 &data->val_out))
6558 return -EIO;
6559 break;
6560 case SIOCSMIIREG:
6561 default:
6562 return -EOPNOTSUPP;
6563 }
6564 return 0;
6565 }
6566
6567 /**
6568 * igb_ioctl -
6569 * @netdev:
6570 * @ifreq:
6571 * @cmd:
6572 **/
6573 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6574 {
6575 switch (cmd) {
6576 case SIOCGMIIPHY:
6577 case SIOCGMIIREG:
6578 case SIOCSMIIREG:
6579 return igb_mii_ioctl(netdev, ifr, cmd);
6580 #ifdef CONFIG_IGB_PTP
6581 case SIOCSHWTSTAMP:
6582 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6583 #endif /* CONFIG_IGB_PTP */
6584 default:
6585 return -EOPNOTSUPP;
6586 }
6587 }
6588
6589 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6590 {
6591 struct igb_adapter *adapter = hw->back;
6592
6593 if (pcie_capability_read_word(adapter->pdev, reg, value))
6594 return -E1000_ERR_CONFIG;
6595
6596 return 0;
6597 }
6598
6599 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6600 {
6601 struct igb_adapter *adapter = hw->back;
6602
6603 if (pcie_capability_write_word(adapter->pdev, reg, *value))
6604 return -E1000_ERR_CONFIG;
6605
6606 return 0;
6607 }
6608
6609 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6610 {
6611 struct igb_adapter *adapter = netdev_priv(netdev);
6612 struct e1000_hw *hw = &adapter->hw;
6613 u32 ctrl, rctl;
6614 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6615
6616 if (enable) {
6617 /* enable VLAN tag insert/strip */
6618 ctrl = rd32(E1000_CTRL);
6619 ctrl |= E1000_CTRL_VME;
6620 wr32(E1000_CTRL, ctrl);
6621
6622 /* Disable CFI check */
6623 rctl = rd32(E1000_RCTL);
6624 rctl &= ~E1000_RCTL_CFIEN;
6625 wr32(E1000_RCTL, rctl);
6626 } else {
6627 /* disable VLAN tag insert/strip */
6628 ctrl = rd32(E1000_CTRL);
6629 ctrl &= ~E1000_CTRL_VME;
6630 wr32(E1000_CTRL, ctrl);
6631 }
6632
6633 igb_rlpml_set(adapter);
6634 }
6635
6636 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6637 {
6638 struct igb_adapter *adapter = netdev_priv(netdev);
6639 struct e1000_hw *hw = &adapter->hw;
6640 int pf_id = adapter->vfs_allocated_count;
6641
6642 /* attempt to add filter to vlvf array */
6643 igb_vlvf_set(adapter, vid, true, pf_id);
6644
6645 /* add the filter since PF can receive vlans w/o entry in vlvf */
6646 igb_vfta_set(hw, vid, true);
6647
6648 set_bit(vid, adapter->active_vlans);
6649
6650 return 0;
6651 }
6652
6653 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6654 {
6655 struct igb_adapter *adapter = netdev_priv(netdev);
6656 struct e1000_hw *hw = &adapter->hw;
6657 int pf_id = adapter->vfs_allocated_count;
6658 s32 err;
6659
6660 /* remove vlan from VLVF table array */
6661 err = igb_vlvf_set(adapter, vid, false, pf_id);
6662
6663 /* if vid was not present in VLVF just remove it from table */
6664 if (err)
6665 igb_vfta_set(hw, vid, false);
6666
6667 clear_bit(vid, adapter->active_vlans);
6668
6669 return 0;
6670 }
6671
6672 static void igb_restore_vlan(struct igb_adapter *adapter)
6673 {
6674 u16 vid;
6675
6676 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6677
6678 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6679 igb_vlan_rx_add_vid(adapter->netdev, vid);
6680 }
6681
6682 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6683 {
6684 struct pci_dev *pdev = adapter->pdev;
6685 struct e1000_mac_info *mac = &adapter->hw.mac;
6686
6687 mac->autoneg = 0;
6688
6689 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6690 * for the switch() below to work */
6691 if ((spd & 1) || (dplx & ~1))
6692 goto err_inval;
6693
6694 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6695 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6696 spd != SPEED_1000 &&
6697 dplx != DUPLEX_FULL)
6698 goto err_inval;
6699
6700 switch (spd + dplx) {
6701 case SPEED_10 + DUPLEX_HALF:
6702 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6703 break;
6704 case SPEED_10 + DUPLEX_FULL:
6705 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6706 break;
6707 case SPEED_100 + DUPLEX_HALF:
6708 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6709 break;
6710 case SPEED_100 + DUPLEX_FULL:
6711 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6712 break;
6713 case SPEED_1000 + DUPLEX_FULL:
6714 mac->autoneg = 1;
6715 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6716 break;
6717 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6718 default:
6719 goto err_inval;
6720 }
6721
6722 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6723 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6724
6725 return 0;
6726
6727 err_inval:
6728 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6729 return -EINVAL;
6730 }
6731
6732 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6733 bool runtime)
6734 {
6735 struct net_device *netdev = pci_get_drvdata(pdev);
6736 struct igb_adapter *adapter = netdev_priv(netdev);
6737 struct e1000_hw *hw = &adapter->hw;
6738 u32 ctrl, rctl, status;
6739 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6740 #ifdef CONFIG_PM
6741 int retval = 0;
6742 #endif
6743
6744 netif_device_detach(netdev);
6745
6746 if (netif_running(netdev))
6747 __igb_close(netdev, true);
6748
6749 igb_clear_interrupt_scheme(adapter);
6750
6751 #ifdef CONFIG_PM
6752 retval = pci_save_state(pdev);
6753 if (retval)
6754 return retval;
6755 #endif
6756
6757 status = rd32(E1000_STATUS);
6758 if (status & E1000_STATUS_LU)
6759 wufc &= ~E1000_WUFC_LNKC;
6760
6761 if (wufc) {
6762 igb_setup_rctl(adapter);
6763 igb_set_rx_mode(netdev);
6764
6765 /* turn on all-multi mode if wake on multicast is enabled */
6766 if (wufc & E1000_WUFC_MC) {
6767 rctl = rd32(E1000_RCTL);
6768 rctl |= E1000_RCTL_MPE;
6769 wr32(E1000_RCTL, rctl);
6770 }
6771
6772 ctrl = rd32(E1000_CTRL);
6773 /* advertise wake from D3Cold */
6774 #define E1000_CTRL_ADVD3WUC 0x00100000
6775 /* phy power management enable */
6776 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6777 ctrl |= E1000_CTRL_ADVD3WUC;
6778 wr32(E1000_CTRL, ctrl);
6779
6780 /* Allow time for pending master requests to run */
6781 igb_disable_pcie_master(hw);
6782
6783 wr32(E1000_WUC, E1000_WUC_PME_EN);
6784 wr32(E1000_WUFC, wufc);
6785 } else {
6786 wr32(E1000_WUC, 0);
6787 wr32(E1000_WUFC, 0);
6788 }
6789
6790 *enable_wake = wufc || adapter->en_mng_pt;
6791 if (!*enable_wake)
6792 igb_power_down_link(adapter);
6793 else
6794 igb_power_up_link(adapter);
6795
6796 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6797 * would have already happened in close and is redundant. */
6798 igb_release_hw_control(adapter);
6799
6800 pci_disable_device(pdev);
6801
6802 return 0;
6803 }
6804
6805 #ifdef CONFIG_PM
6806 #ifdef CONFIG_PM_SLEEP
6807 static int igb_suspend(struct device *dev)
6808 {
6809 int retval;
6810 bool wake;
6811 struct pci_dev *pdev = to_pci_dev(dev);
6812
6813 retval = __igb_shutdown(pdev, &wake, 0);
6814 if (retval)
6815 return retval;
6816
6817 if (wake) {
6818 pci_prepare_to_sleep(pdev);
6819 } else {
6820 pci_wake_from_d3(pdev, false);
6821 pci_set_power_state(pdev, PCI_D3hot);
6822 }
6823
6824 return 0;
6825 }
6826 #endif /* CONFIG_PM_SLEEP */
6827
6828 static int igb_resume(struct device *dev)
6829 {
6830 struct pci_dev *pdev = to_pci_dev(dev);
6831 struct net_device *netdev = pci_get_drvdata(pdev);
6832 struct igb_adapter *adapter = netdev_priv(netdev);
6833 struct e1000_hw *hw = &adapter->hw;
6834 u32 err;
6835
6836 pci_set_power_state(pdev, PCI_D0);
6837 pci_restore_state(pdev);
6838 pci_save_state(pdev);
6839
6840 err = pci_enable_device_mem(pdev);
6841 if (err) {
6842 dev_err(&pdev->dev,
6843 "igb: Cannot enable PCI device from suspend\n");
6844 return err;
6845 }
6846 pci_set_master(pdev);
6847
6848 pci_enable_wake(pdev, PCI_D3hot, 0);
6849 pci_enable_wake(pdev, PCI_D3cold, 0);
6850
6851 if (igb_init_interrupt_scheme(adapter)) {
6852 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6853 return -ENOMEM;
6854 }
6855
6856 igb_reset(adapter);
6857
6858 /* let the f/w know that the h/w is now under the control of the
6859 * driver. */
6860 igb_get_hw_control(adapter);
6861
6862 wr32(E1000_WUS, ~0);
6863
6864 if (netdev->flags & IFF_UP) {
6865 rtnl_lock();
6866 err = __igb_open(netdev, true);
6867 rtnl_unlock();
6868 if (err)
6869 return err;
6870 }
6871
6872 netif_device_attach(netdev);
6873 return 0;
6874 }
6875
6876 #ifdef CONFIG_PM_RUNTIME
6877 static int igb_runtime_idle(struct device *dev)
6878 {
6879 struct pci_dev *pdev = to_pci_dev(dev);
6880 struct net_device *netdev = pci_get_drvdata(pdev);
6881 struct igb_adapter *adapter = netdev_priv(netdev);
6882
6883 if (!igb_has_link(adapter))
6884 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6885
6886 return -EBUSY;
6887 }
6888
6889 static int igb_runtime_suspend(struct device *dev)
6890 {
6891 struct pci_dev *pdev = to_pci_dev(dev);
6892 int retval;
6893 bool wake;
6894
6895 retval = __igb_shutdown(pdev, &wake, 1);
6896 if (retval)
6897 return retval;
6898
6899 if (wake) {
6900 pci_prepare_to_sleep(pdev);
6901 } else {
6902 pci_wake_from_d3(pdev, false);
6903 pci_set_power_state(pdev, PCI_D3hot);
6904 }
6905
6906 return 0;
6907 }
6908
6909 static int igb_runtime_resume(struct device *dev)
6910 {
6911 return igb_resume(dev);
6912 }
6913 #endif /* CONFIG_PM_RUNTIME */
6914 #endif
6915
6916 static void igb_shutdown(struct pci_dev *pdev)
6917 {
6918 bool wake;
6919
6920 __igb_shutdown(pdev, &wake, 0);
6921
6922 if (system_state == SYSTEM_POWER_OFF) {
6923 pci_wake_from_d3(pdev, wake);
6924 pci_set_power_state(pdev, PCI_D3hot);
6925 }
6926 }
6927
6928 #ifdef CONFIG_NET_POLL_CONTROLLER
6929 /*
6930 * Polling 'interrupt' - used by things like netconsole to send skbs
6931 * without having to re-enable interrupts. It's not called while
6932 * the interrupt routine is executing.
6933 */
6934 static void igb_netpoll(struct net_device *netdev)
6935 {
6936 struct igb_adapter *adapter = netdev_priv(netdev);
6937 struct e1000_hw *hw = &adapter->hw;
6938 struct igb_q_vector *q_vector;
6939 int i;
6940
6941 for (i = 0; i < adapter->num_q_vectors; i++) {
6942 q_vector = adapter->q_vector[i];
6943 if (adapter->msix_entries)
6944 wr32(E1000_EIMC, q_vector->eims_value);
6945 else
6946 igb_irq_disable(adapter);
6947 napi_schedule(&q_vector->napi);
6948 }
6949 }
6950 #endif /* CONFIG_NET_POLL_CONTROLLER */
6951
6952 /**
6953 * igb_io_error_detected - called when PCI error is detected
6954 * @pdev: Pointer to PCI device
6955 * @state: The current pci connection state
6956 *
6957 * This function is called after a PCI bus error affecting
6958 * this device has been detected.
6959 */
6960 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6961 pci_channel_state_t state)
6962 {
6963 struct net_device *netdev = pci_get_drvdata(pdev);
6964 struct igb_adapter *adapter = netdev_priv(netdev);
6965
6966 netif_device_detach(netdev);
6967
6968 if (state == pci_channel_io_perm_failure)
6969 return PCI_ERS_RESULT_DISCONNECT;
6970
6971 if (netif_running(netdev))
6972 igb_down(adapter);
6973 pci_disable_device(pdev);
6974
6975 /* Request a slot slot reset. */
6976 return PCI_ERS_RESULT_NEED_RESET;
6977 }
6978
6979 /**
6980 * igb_io_slot_reset - called after the pci bus has been reset.
6981 * @pdev: Pointer to PCI device
6982 *
6983 * Restart the card from scratch, as if from a cold-boot. Implementation
6984 * resembles the first-half of the igb_resume routine.
6985 */
6986 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6987 {
6988 struct net_device *netdev = pci_get_drvdata(pdev);
6989 struct igb_adapter *adapter = netdev_priv(netdev);
6990 struct e1000_hw *hw = &adapter->hw;
6991 pci_ers_result_t result;
6992 int err;
6993
6994 if (pci_enable_device_mem(pdev)) {
6995 dev_err(&pdev->dev,
6996 "Cannot re-enable PCI device after reset.\n");
6997 result = PCI_ERS_RESULT_DISCONNECT;
6998 } else {
6999 pci_set_master(pdev);
7000 pci_restore_state(pdev);
7001 pci_save_state(pdev);
7002
7003 pci_enable_wake(pdev, PCI_D3hot, 0);
7004 pci_enable_wake(pdev, PCI_D3cold, 0);
7005
7006 igb_reset(adapter);
7007 wr32(E1000_WUS, ~0);
7008 result = PCI_ERS_RESULT_RECOVERED;
7009 }
7010
7011 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7012 if (err) {
7013 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7014 "failed 0x%0x\n", err);
7015 /* non-fatal, continue */
7016 }
7017
7018 return result;
7019 }
7020
7021 /**
7022 * igb_io_resume - called when traffic can start flowing again.
7023 * @pdev: Pointer to PCI device
7024 *
7025 * This callback is called when the error recovery driver tells us that
7026 * its OK to resume normal operation. Implementation resembles the
7027 * second-half of the igb_resume routine.
7028 */
7029 static void igb_io_resume(struct pci_dev *pdev)
7030 {
7031 struct net_device *netdev = pci_get_drvdata(pdev);
7032 struct igb_adapter *adapter = netdev_priv(netdev);
7033
7034 if (netif_running(netdev)) {
7035 if (igb_up(adapter)) {
7036 dev_err(&pdev->dev, "igb_up failed after reset\n");
7037 return;
7038 }
7039 }
7040
7041 netif_device_attach(netdev);
7042
7043 /* let the f/w know that the h/w is now under the control of the
7044 * driver. */
7045 igb_get_hw_control(adapter);
7046 }
7047
7048 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7049 u8 qsel)
7050 {
7051 u32 rar_low, rar_high;
7052 struct e1000_hw *hw = &adapter->hw;
7053
7054 /* HW expects these in little endian so we reverse the byte order
7055 * from network order (big endian) to little endian
7056 */
7057 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7058 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7059 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7060
7061 /* Indicate to hardware the Address is Valid. */
7062 rar_high |= E1000_RAH_AV;
7063
7064 if (hw->mac.type == e1000_82575)
7065 rar_high |= E1000_RAH_POOL_1 * qsel;
7066 else
7067 rar_high |= E1000_RAH_POOL_1 << qsel;
7068
7069 wr32(E1000_RAL(index), rar_low);
7070 wrfl();
7071 wr32(E1000_RAH(index), rar_high);
7072 wrfl();
7073 }
7074
7075 static int igb_set_vf_mac(struct igb_adapter *adapter,
7076 int vf, unsigned char *mac_addr)
7077 {
7078 struct e1000_hw *hw = &adapter->hw;
7079 /* VF MAC addresses start at end of receive addresses and moves
7080 * torwards the first, as a result a collision should not be possible */
7081 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7082
7083 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7084
7085 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7086
7087 return 0;
7088 }
7089
7090 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7091 {
7092 struct igb_adapter *adapter = netdev_priv(netdev);
7093 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7094 return -EINVAL;
7095 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7096 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7097 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7098 " change effective.");
7099 if (test_bit(__IGB_DOWN, &adapter->state)) {
7100 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7101 " but the PF device is not up.\n");
7102 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7103 " attempting to use the VF device.\n");
7104 }
7105 return igb_set_vf_mac(adapter, vf, mac);
7106 }
7107
7108 static int igb_link_mbps(int internal_link_speed)
7109 {
7110 switch (internal_link_speed) {
7111 case SPEED_100:
7112 return 100;
7113 case SPEED_1000:
7114 return 1000;
7115 default:
7116 return 0;
7117 }
7118 }
7119
7120 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7121 int link_speed)
7122 {
7123 int rf_dec, rf_int;
7124 u32 bcnrc_val;
7125
7126 if (tx_rate != 0) {
7127 /* Calculate the rate factor values to set */
7128 rf_int = link_speed / tx_rate;
7129 rf_dec = (link_speed - (rf_int * tx_rate));
7130 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7131
7132 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7133 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7134 E1000_RTTBCNRC_RF_INT_MASK);
7135 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7136 } else {
7137 bcnrc_val = 0;
7138 }
7139
7140 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7141 /*
7142 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7143 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7144 */
7145 wr32(E1000_RTTBCNRM, 0x14);
7146 wr32(E1000_RTTBCNRC, bcnrc_val);
7147 }
7148
7149 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7150 {
7151 int actual_link_speed, i;
7152 bool reset_rate = false;
7153
7154 /* VF TX rate limit was not set or not supported */
7155 if ((adapter->vf_rate_link_speed == 0) ||
7156 (adapter->hw.mac.type != e1000_82576))
7157 return;
7158
7159 actual_link_speed = igb_link_mbps(adapter->link_speed);
7160 if (actual_link_speed != adapter->vf_rate_link_speed) {
7161 reset_rate = true;
7162 adapter->vf_rate_link_speed = 0;
7163 dev_info(&adapter->pdev->dev,
7164 "Link speed has been changed. VF Transmit "
7165 "rate is disabled\n");
7166 }
7167
7168 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7169 if (reset_rate)
7170 adapter->vf_data[i].tx_rate = 0;
7171
7172 igb_set_vf_rate_limit(&adapter->hw, i,
7173 adapter->vf_data[i].tx_rate,
7174 actual_link_speed);
7175 }
7176 }
7177
7178 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7179 {
7180 struct igb_adapter *adapter = netdev_priv(netdev);
7181 struct e1000_hw *hw = &adapter->hw;
7182 int actual_link_speed;
7183
7184 if (hw->mac.type != e1000_82576)
7185 return -EOPNOTSUPP;
7186
7187 actual_link_speed = igb_link_mbps(adapter->link_speed);
7188 if ((vf >= adapter->vfs_allocated_count) ||
7189 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7190 (tx_rate < 0) || (tx_rate > actual_link_speed))
7191 return -EINVAL;
7192
7193 adapter->vf_rate_link_speed = actual_link_speed;
7194 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7195 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7196
7197 return 0;
7198 }
7199
7200 static int igb_ndo_get_vf_config(struct net_device *netdev,
7201 int vf, struct ifla_vf_info *ivi)
7202 {
7203 struct igb_adapter *adapter = netdev_priv(netdev);
7204 if (vf >= adapter->vfs_allocated_count)
7205 return -EINVAL;
7206 ivi->vf = vf;
7207 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7208 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7209 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7210 ivi->qos = adapter->vf_data[vf].pf_qos;
7211 return 0;
7212 }
7213
7214 static void igb_vmm_control(struct igb_adapter *adapter)
7215 {
7216 struct e1000_hw *hw = &adapter->hw;
7217 u32 reg;
7218
7219 switch (hw->mac.type) {
7220 case e1000_82575:
7221 case e1000_i210:
7222 case e1000_i211:
7223 default:
7224 /* replication is not supported for 82575 */
7225 return;
7226 case e1000_82576:
7227 /* notify HW that the MAC is adding vlan tags */
7228 reg = rd32(E1000_DTXCTL);
7229 reg |= E1000_DTXCTL_VLAN_ADDED;
7230 wr32(E1000_DTXCTL, reg);
7231 case e1000_82580:
7232 /* enable replication vlan tag stripping */
7233 reg = rd32(E1000_RPLOLR);
7234 reg |= E1000_RPLOLR_STRVLAN;
7235 wr32(E1000_RPLOLR, reg);
7236 case e1000_i350:
7237 /* none of the above registers are supported by i350 */
7238 break;
7239 }
7240
7241 if (adapter->vfs_allocated_count) {
7242 igb_vmdq_set_loopback_pf(hw, true);
7243 igb_vmdq_set_replication_pf(hw, true);
7244 igb_vmdq_set_anti_spoofing_pf(hw, true,
7245 adapter->vfs_allocated_count);
7246 } else {
7247 igb_vmdq_set_loopback_pf(hw, false);
7248 igb_vmdq_set_replication_pf(hw, false);
7249 }
7250 }
7251
7252 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7253 {
7254 struct e1000_hw *hw = &adapter->hw;
7255 u32 dmac_thr;
7256 u16 hwm;
7257
7258 if (hw->mac.type > e1000_82580) {
7259 if (adapter->flags & IGB_FLAG_DMAC) {
7260 u32 reg;
7261
7262 /* force threshold to 0. */
7263 wr32(E1000_DMCTXTH, 0);
7264
7265 /*
7266 * DMA Coalescing high water mark needs to be greater
7267 * than the Rx threshold. Set hwm to PBA - max frame
7268 * size in 16B units, capping it at PBA - 6KB.
7269 */
7270 hwm = 64 * pba - adapter->max_frame_size / 16;
7271 if (hwm < 64 * (pba - 6))
7272 hwm = 64 * (pba - 6);
7273 reg = rd32(E1000_FCRTC);
7274 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7275 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7276 & E1000_FCRTC_RTH_COAL_MASK);
7277 wr32(E1000_FCRTC, reg);
7278
7279 /*
7280 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7281 * frame size, capping it at PBA - 10KB.
7282 */
7283 dmac_thr = pba - adapter->max_frame_size / 512;
7284 if (dmac_thr < pba - 10)
7285 dmac_thr = pba - 10;
7286 reg = rd32(E1000_DMACR);
7287 reg &= ~E1000_DMACR_DMACTHR_MASK;
7288 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7289 & E1000_DMACR_DMACTHR_MASK);
7290
7291 /* transition to L0x or L1 if available..*/
7292 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7293
7294 /* watchdog timer= +-1000 usec in 32usec intervals */
7295 reg |= (1000 >> 5);
7296
7297 /* Disable BMC-to-OS Watchdog Enable */
7298 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7299 wr32(E1000_DMACR, reg);
7300
7301 /*
7302 * no lower threshold to disable
7303 * coalescing(smart fifb)-UTRESH=0
7304 */
7305 wr32(E1000_DMCRTRH, 0);
7306
7307 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7308
7309 wr32(E1000_DMCTLX, reg);
7310
7311 /*
7312 * free space in tx packet buffer to wake from
7313 * DMA coal
7314 */
7315 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7316 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7317
7318 /*
7319 * make low power state decision controlled
7320 * by DMA coal
7321 */
7322 reg = rd32(E1000_PCIEMISC);
7323 reg &= ~E1000_PCIEMISC_LX_DECISION;
7324 wr32(E1000_PCIEMISC, reg);
7325 } /* endif adapter->dmac is not disabled */
7326 } else if (hw->mac.type == e1000_82580) {
7327 u32 reg = rd32(E1000_PCIEMISC);
7328 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7329 wr32(E1000_DMACR, 0);
7330 }
7331 }
7332
7333 /* igb_main.c */
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