1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not availible. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
72 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
73 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
75 #define IGB_NBITS_82580 40
77 static void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
);
79 /* SYSTIM read access for the 82576 */
80 static cycle_t
igb_ptp_read_82576(const struct cyclecounter
*cc
)
82 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
83 struct e1000_hw
*hw
= &igb
->hw
;
87 lo
= rd32(E1000_SYSTIML
);
88 hi
= rd32(E1000_SYSTIMH
);
90 val
= ((u64
) hi
) << 32;
96 /* SYSTIM read access for the 82580 */
97 static cycle_t
igb_ptp_read_82580(const struct cyclecounter
*cc
)
99 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
100 struct e1000_hw
*hw
= &igb
->hw
;
104 /* The timestamp latches on lowest register read. For the 82580
105 * the lowest register is SYSTIMR instead of SYSTIML. However we only
106 * need to provide nanosecond resolution, so we just ignore it.
109 lo
= rd32(E1000_SYSTIML
);
110 hi
= rd32(E1000_SYSTIMH
);
112 val
= ((u64
) hi
) << 32;
118 /* SYSTIM read access for I210/I211 */
119 static void igb_ptp_read_i210(struct igb_adapter
*adapter
, struct timespec
*ts
)
121 struct e1000_hw
*hw
= &adapter
->hw
;
124 /* The timestamp latches on lowest register read. For I210/I211, the
125 * lowest register is SYSTIMR. Since we only need to provide nanosecond
126 * resolution, we can ignore it.
129 nsec
= rd32(E1000_SYSTIML
);
130 sec
= rd32(E1000_SYSTIMH
);
136 static void igb_ptp_write_i210(struct igb_adapter
*adapter
,
137 const struct timespec
*ts
)
139 struct e1000_hw
*hw
= &adapter
->hw
;
141 /* Writing the SYSTIMR register is not necessary as it only provides
142 * sub-nanosecond resolution.
144 wr32(E1000_SYSTIML
, ts
->tv_nsec
);
145 wr32(E1000_SYSTIMH
, ts
->tv_sec
);
149 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
150 * @adapter: board private structure
151 * @hwtstamps: timestamp structure to update
152 * @systim: unsigned 64bit system time value.
154 * We need to convert the system time value stored in the RX/TXSTMP registers
155 * into a hwtstamp which can be used by the upper level timestamping functions.
157 * The 'tmreg_lock' spinlock is used to protect the consistency of the
158 * system time value. This is needed because reading the 64 bit time
159 * value involves reading two (or three) 32 bit registers. The first
160 * read latches the value. Ditto for writing.
162 * In addition, here have extended the system time with an overflow
163 * counter in software.
165 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter
*adapter
,
166 struct skb_shared_hwtstamps
*hwtstamps
,
172 switch (adapter
->hw
.mac
.type
) {
177 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
179 ns
= timecounter_cyc2time(&adapter
->tc
, systim
);
181 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
183 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
184 hwtstamps
->hwtstamp
= ns_to_ktime(ns
);
188 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
189 /* Upper 32 bits contain s, lower 32 bits contain ns. */
190 hwtstamps
->hwtstamp
= ktime_set(systim
>> 32,
191 systim
& 0xFFFFFFFF);
198 /* PTP clock operations */
199 static int igb_ptp_adjfreq_82576(struct ptp_clock_info
*ptp
, s32 ppb
)
201 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
203 struct e1000_hw
*hw
= &igb
->hw
;
214 rate
= div_u64(rate
, 1953125);
216 incvalue
= 16 << IGB_82576_TSYNC_SHIFT
;
223 wr32(E1000_TIMINCA
, INCPERIOD_82576
| (incvalue
& INCVALUE_82576_MASK
));
228 static int igb_ptp_adjfreq_82580(struct ptp_clock_info
*ptp
, s32 ppb
)
230 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
232 struct e1000_hw
*hw
= &igb
->hw
;
243 rate
= div_u64(rate
, 1953125);
245 inca
= rate
& INCVALUE_MASK
;
249 wr32(E1000_TIMINCA
, inca
);
254 static int igb_ptp_adjtime_82576(struct ptp_clock_info
*ptp
, s64 delta
)
256 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
260 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
261 timecounter_adjtime(&igb
->tc
, delta
);
262 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
267 static int igb_ptp_adjtime_i210(struct ptp_clock_info
*ptp
, s64 delta
)
269 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
272 struct timespec now
, then
= ns_to_timespec(delta
);
274 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
276 igb_ptp_read_i210(igb
, &now
);
277 now
= timespec_add(now
, then
);
278 igb_ptp_write_i210(igb
, (const struct timespec
*)&now
);
280 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
285 static int igb_ptp_gettime_82576(struct ptp_clock_info
*ptp
,
288 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
294 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
296 ns
= timecounter_read(&igb
->tc
);
298 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
300 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
301 ts
->tv_nsec
= remainder
;
306 static int igb_ptp_gettime_i210(struct ptp_clock_info
*ptp
,
309 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
313 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
315 igb_ptp_read_i210(igb
, ts
);
317 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
322 static int igb_ptp_settime_82576(struct ptp_clock_info
*ptp
,
323 const struct timespec
*ts
)
325 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
330 ns
= ts
->tv_sec
* 1000000000ULL;
333 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
335 timecounter_init(&igb
->tc
, &igb
->cc
, ns
);
337 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
342 static int igb_ptp_settime_i210(struct ptp_clock_info
*ptp
,
343 const struct timespec
*ts
)
345 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
349 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
351 igb_ptp_write_i210(igb
, ts
);
353 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
358 static void igb_pin_direction(int pin
, int input
, u32
*ctrl
, u32
*ctrl_ext
)
360 u32
*ptr
= pin
< 2 ? ctrl
: ctrl_ext
;
361 u32 mask
[IGB_N_SDP
] = {
364 E1000_CTRL_EXT_SDP2_DIR
,
365 E1000_CTRL_EXT_SDP3_DIR
,
374 static void igb_pin_extts(struct igb_adapter
*igb
, int chan
, int pin
)
376 struct e1000_hw
*hw
= &igb
->hw
;
377 u32 aux0_sel_sdp
[IGB_N_SDP
] = {
378 AUX0_SEL_SDP0
, AUX0_SEL_SDP1
, AUX0_SEL_SDP2
, AUX0_SEL_SDP3
,
380 u32 aux1_sel_sdp
[IGB_N_SDP
] = {
381 AUX1_SEL_SDP0
, AUX1_SEL_SDP1
, AUX1_SEL_SDP2
, AUX1_SEL_SDP3
,
383 u32 ts_sdp_en
[IGB_N_SDP
] = {
384 TS_SDP0_EN
, TS_SDP1_EN
, TS_SDP2_EN
, TS_SDP3_EN
,
386 u32 ctrl
, ctrl_ext
, tssdp
= 0;
388 ctrl
= rd32(E1000_CTRL
);
389 ctrl_ext
= rd32(E1000_CTRL_EXT
);
390 tssdp
= rd32(E1000_TSSDP
);
392 igb_pin_direction(pin
, 1, &ctrl
, &ctrl_ext
);
394 /* Make sure this pin is not enabled as an output. */
395 tssdp
&= ~ts_sdp_en
[pin
];
398 tssdp
&= ~AUX1_SEL_SDP3
;
399 tssdp
|= aux1_sel_sdp
[pin
] | AUX1_TS_SDP_EN
;
401 tssdp
&= ~AUX0_SEL_SDP3
;
402 tssdp
|= aux0_sel_sdp
[pin
] | AUX0_TS_SDP_EN
;
405 wr32(E1000_TSSDP
, tssdp
);
406 wr32(E1000_CTRL
, ctrl
);
407 wr32(E1000_CTRL_EXT
, ctrl_ext
);
410 static void igb_pin_perout(struct igb_adapter
*igb
, int chan
, int pin
)
412 struct e1000_hw
*hw
= &igb
->hw
;
413 u32 aux0_sel_sdp
[IGB_N_SDP
] = {
414 AUX0_SEL_SDP0
, AUX0_SEL_SDP1
, AUX0_SEL_SDP2
, AUX0_SEL_SDP3
,
416 u32 aux1_sel_sdp
[IGB_N_SDP
] = {
417 AUX1_SEL_SDP0
, AUX1_SEL_SDP1
, AUX1_SEL_SDP2
, AUX1_SEL_SDP3
,
419 u32 ts_sdp_en
[IGB_N_SDP
] = {
420 TS_SDP0_EN
, TS_SDP1_EN
, TS_SDP2_EN
, TS_SDP3_EN
,
422 u32 ts_sdp_sel_tt0
[IGB_N_SDP
] = {
423 TS_SDP0_SEL_TT0
, TS_SDP1_SEL_TT0
,
424 TS_SDP2_SEL_TT0
, TS_SDP3_SEL_TT0
,
426 u32 ts_sdp_sel_tt1
[IGB_N_SDP
] = {
427 TS_SDP0_SEL_TT1
, TS_SDP1_SEL_TT1
,
428 TS_SDP2_SEL_TT1
, TS_SDP3_SEL_TT1
,
430 u32 ts_sdp_sel_clr
[IGB_N_SDP
] = {
431 TS_SDP0_SEL_FC1
, TS_SDP1_SEL_FC1
,
432 TS_SDP2_SEL_FC1
, TS_SDP3_SEL_FC1
,
434 u32 ctrl
, ctrl_ext
, tssdp
= 0;
436 ctrl
= rd32(E1000_CTRL
);
437 ctrl_ext
= rd32(E1000_CTRL_EXT
);
438 tssdp
= rd32(E1000_TSSDP
);
440 igb_pin_direction(pin
, 0, &ctrl
, &ctrl_ext
);
442 /* Make sure this pin is not enabled as an input. */
443 if ((tssdp
& AUX0_SEL_SDP3
) == aux0_sel_sdp
[pin
])
444 tssdp
&= ~AUX0_TS_SDP_EN
;
446 if ((tssdp
& AUX1_SEL_SDP3
) == aux1_sel_sdp
[pin
])
447 tssdp
&= ~AUX1_TS_SDP_EN
;
449 tssdp
&= ~ts_sdp_sel_clr
[pin
];
451 tssdp
|= ts_sdp_sel_tt1
[pin
];
453 tssdp
|= ts_sdp_sel_tt0
[pin
];
455 tssdp
|= ts_sdp_en
[pin
];
457 wr32(E1000_TSSDP
, tssdp
);
458 wr32(E1000_CTRL
, ctrl
);
459 wr32(E1000_CTRL_EXT
, ctrl_ext
);
462 static int igb_ptp_feature_enable_i210(struct ptp_clock_info
*ptp
,
463 struct ptp_clock_request
*rq
, int on
)
465 struct igb_adapter
*igb
=
466 container_of(ptp
, struct igb_adapter
, ptp_caps
);
467 struct e1000_hw
*hw
= &igb
->hw
;
468 u32 tsauxc
, tsim
, tsauxc_mask
, tsim_mask
, trgttiml
, trgttimh
;
475 case PTP_CLK_REQ_EXTTS
:
477 pin
= ptp_find_pin(igb
->ptp_clock
, PTP_PF_EXTTS
,
482 if (rq
->extts
.index
== 1) {
483 tsauxc_mask
= TSAUXC_EN_TS1
;
484 tsim_mask
= TSINTR_AUTT1
;
486 tsauxc_mask
= TSAUXC_EN_TS0
;
487 tsim_mask
= TSINTR_AUTT0
;
489 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
490 tsauxc
= rd32(E1000_TSAUXC
);
491 tsim
= rd32(E1000_TSIM
);
493 igb_pin_extts(igb
, rq
->extts
.index
, pin
);
494 tsauxc
|= tsauxc_mask
;
497 tsauxc
&= ~tsauxc_mask
;
500 wr32(E1000_TSAUXC
, tsauxc
);
501 wr32(E1000_TSIM
, tsim
);
502 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
505 case PTP_CLK_REQ_PEROUT
:
507 pin
= ptp_find_pin(igb
->ptp_clock
, PTP_PF_PEROUT
,
512 ts
.tv_sec
= rq
->perout
.period
.sec
;
513 ts
.tv_nsec
= rq
->perout
.period
.nsec
;
514 ns
= timespec_to_ns(&ts
);
516 if (on
&& ns
< 500000LL) {
517 /* 2k interrupts per second is an awful lot. */
520 ts
= ns_to_timespec(ns
);
521 if (rq
->perout
.index
== 1) {
522 tsauxc_mask
= TSAUXC_EN_TT1
;
523 tsim_mask
= TSINTR_TT1
;
524 trgttiml
= E1000_TRGTTIML1
;
525 trgttimh
= E1000_TRGTTIMH1
;
527 tsauxc_mask
= TSAUXC_EN_TT0
;
528 tsim_mask
= TSINTR_TT0
;
529 trgttiml
= E1000_TRGTTIML0
;
530 trgttimh
= E1000_TRGTTIMH0
;
532 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
533 tsauxc
= rd32(E1000_TSAUXC
);
534 tsim
= rd32(E1000_TSIM
);
536 int i
= rq
->perout
.index
;
538 igb_pin_perout(igb
, i
, pin
);
539 igb
->perout
[i
].start
.tv_sec
= rq
->perout
.start
.sec
;
540 igb
->perout
[i
].start
.tv_nsec
= rq
->perout
.start
.nsec
;
541 igb
->perout
[i
].period
.tv_sec
= ts
.tv_sec
;
542 igb
->perout
[i
].period
.tv_nsec
= ts
.tv_nsec
;
543 wr32(trgttiml
, rq
->perout
.start
.sec
);
544 wr32(trgttimh
, rq
->perout
.start
.nsec
);
545 tsauxc
|= tsauxc_mask
;
548 tsauxc
&= ~tsauxc_mask
;
551 wr32(E1000_TSAUXC
, tsauxc
);
552 wr32(E1000_TSIM
, tsim
);
553 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
556 case PTP_CLK_REQ_PPS
:
557 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
558 tsim
= rd32(E1000_TSIM
);
560 tsim
|= TSINTR_SYS_WRAP
;
562 tsim
&= ~TSINTR_SYS_WRAP
;
563 wr32(E1000_TSIM
, tsim
);
564 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
571 static int igb_ptp_feature_enable(struct ptp_clock_info
*ptp
,
572 struct ptp_clock_request
*rq
, int on
)
577 static int igb_ptp_verify_pin(struct ptp_clock_info
*ptp
, unsigned int pin
,
578 enum ptp_pin_function func
, unsigned int chan
)
593 * @work: pointer to work struct
595 * This work function polls the TSYNCTXCTL valid bit to determine when a
596 * timestamp has been taken for the current stored skb.
598 static void igb_ptp_tx_work(struct work_struct
*work
)
600 struct igb_adapter
*adapter
= container_of(work
, struct igb_adapter
,
602 struct e1000_hw
*hw
= &adapter
->hw
;
605 if (!adapter
->ptp_tx_skb
)
608 if (time_is_before_jiffies(adapter
->ptp_tx_start
+
609 IGB_PTP_TX_TIMEOUT
)) {
610 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
611 adapter
->ptp_tx_skb
= NULL
;
612 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS
, &adapter
->state
);
613 adapter
->tx_hwtstamp_timeouts
++;
614 dev_warn(&adapter
->pdev
->dev
, "clearing Tx timestamp hang\n");
618 tsynctxctl
= rd32(E1000_TSYNCTXCTL
);
619 if (tsynctxctl
& E1000_TSYNCTXCTL_VALID
)
620 igb_ptp_tx_hwtstamp(adapter
);
622 /* reschedule to check later */
623 schedule_work(&adapter
->ptp_tx_work
);
626 static void igb_ptp_overflow_check(struct work_struct
*work
)
628 struct igb_adapter
*igb
=
629 container_of(work
, struct igb_adapter
, ptp_overflow_work
.work
);
632 igb
->ptp_caps
.gettime(&igb
->ptp_caps
, &ts
);
634 pr_debug("igb overflow check at %ld.%09lu\n", ts
.tv_sec
, ts
.tv_nsec
);
636 schedule_delayed_work(&igb
->ptp_overflow_work
,
637 IGB_SYSTIM_OVERFLOW_PERIOD
);
641 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
642 * @adapter: private network adapter structure
644 * This watchdog task is scheduled to detect error case where hardware has
645 * dropped an Rx packet that was timestamped when the ring is full. The
646 * particular error is rare but leaves the device in a state unable to timestamp
647 * any future packets.
649 void igb_ptp_rx_hang(struct igb_adapter
*adapter
)
651 struct e1000_hw
*hw
= &adapter
->hw
;
652 u32 tsyncrxctl
= rd32(E1000_TSYNCRXCTL
);
653 unsigned long rx_event
;
655 if (hw
->mac
.type
!= e1000_82576
)
658 /* If we don't have a valid timestamp in the registers, just update the
659 * timeout counter and exit
661 if (!(tsyncrxctl
& E1000_TSYNCRXCTL_VALID
)) {
662 adapter
->last_rx_ptp_check
= jiffies
;
666 /* Determine the most recent watchdog or rx_timestamp event */
667 rx_event
= adapter
->last_rx_ptp_check
;
668 if (time_after(adapter
->last_rx_timestamp
, rx_event
))
669 rx_event
= adapter
->last_rx_timestamp
;
671 /* Only need to read the high RXSTMP register to clear the lock */
672 if (time_is_before_jiffies(rx_event
+ 5 * HZ
)) {
674 adapter
->last_rx_ptp_check
= jiffies
;
675 adapter
->rx_hwtstamp_cleared
++;
676 dev_warn(&adapter
->pdev
->dev
, "clearing Rx timestamp hang\n");
681 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
682 * @adapter: Board private structure.
684 * If we were asked to do hardware stamping and such a time stamp is
685 * available, then it must have been for this skb here because we only
686 * allow only one such packet into the queue.
688 static void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
)
690 struct e1000_hw
*hw
= &adapter
->hw
;
691 struct skb_shared_hwtstamps shhwtstamps
;
694 regval
= rd32(E1000_TXSTMPL
);
695 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
697 igb_ptp_systim_to_hwtstamp(adapter
, &shhwtstamps
, regval
);
698 skb_tstamp_tx(adapter
->ptp_tx_skb
, &shhwtstamps
);
699 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
700 adapter
->ptp_tx_skb
= NULL
;
701 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS
, &adapter
->state
);
705 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
706 * @q_vector: Pointer to interrupt specific structure
707 * @va: Pointer to address containing Rx buffer
708 * @skb: Buffer containing timestamp and packet
710 * This function is meant to retrieve a timestamp from the first buffer of an
711 * incoming frame. The value is stored in little endian format starting on
714 void igb_ptp_rx_pktstamp(struct igb_q_vector
*q_vector
,
718 __le64
*regval
= (__le64
*)va
;
720 /* The timestamp is recorded in little endian format.
722 * Field: Reserved Reserved SYSTIML SYSTIMH
724 igb_ptp_systim_to_hwtstamp(q_vector
->adapter
, skb_hwtstamps(skb
),
725 le64_to_cpu(regval
[1]));
729 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
730 * @q_vector: Pointer to interrupt specific structure
731 * @skb: Buffer containing timestamp and packet
733 * This function is meant to retrieve a timestamp from the internal registers
734 * of the adapter and store it in the skb.
736 void igb_ptp_rx_rgtstamp(struct igb_q_vector
*q_vector
,
739 struct igb_adapter
*adapter
= q_vector
->adapter
;
740 struct e1000_hw
*hw
= &adapter
->hw
;
743 /* If this bit is set, then the RX registers contain the time stamp. No
744 * other packet will be time stamped until we read these registers, so
745 * read the registers to make them available again. Because only one
746 * packet can be time stamped at a time, we know that the register
747 * values must belong to this one here and therefore we don't need to
748 * compare any of the additional attributes stored for it.
750 * If nothing went wrong, then it should have a shared tx_flags that we
751 * can turn into a skb_shared_hwtstamps.
753 if (!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
))
756 regval
= rd32(E1000_RXSTMPL
);
757 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
759 igb_ptp_systim_to_hwtstamp(adapter
, skb_hwtstamps(skb
), regval
);
761 /* Update the last_rx_timestamp timer in order to enable watchdog check
762 * for error case of latched timestamp on a dropped packet.
764 adapter
->last_rx_timestamp
= jiffies
;
768 * igb_ptp_get_ts_config - get hardware time stamping config
772 * Get the hwtstamp_config settings to return to the user. Rather than attempt
773 * to deconstruct the settings from the registers, just return a shadow copy
774 * of the last known settings.
776 int igb_ptp_get_ts_config(struct net_device
*netdev
, struct ifreq
*ifr
)
778 struct igb_adapter
*adapter
= netdev_priv(netdev
);
779 struct hwtstamp_config
*config
= &adapter
->tstamp_config
;
781 return copy_to_user(ifr
->ifr_data
, config
, sizeof(*config
)) ?
786 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
787 * @adapter: networking device structure
788 * @config: hwtstamp configuration
790 * Outgoing time stamping can be enabled and disabled. Play nice and
791 * disable it when requested, although it shouldn't case any overhead
792 * when no packet needs it. At most one packet in the queue may be
793 * marked for time stamping, otherwise it would be impossible to tell
794 * for sure to which packet the hardware time stamp belongs.
796 * Incoming time stamping has to be configured via the hardware
797 * filters. Not all combinations are supported, in particular event
798 * type has to be specified. Matching the kind of event packet is
799 * not supported, with the exception of "all V2 events regardless of
802 static int igb_ptp_set_timestamp_mode(struct igb_adapter
*adapter
,
803 struct hwtstamp_config
*config
)
805 struct e1000_hw
*hw
= &adapter
->hw
;
806 u32 tsync_tx_ctl
= E1000_TSYNCTXCTL_ENABLED
;
807 u32 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
808 u32 tsync_rx_cfg
= 0;
813 /* reserved for future extensions */
817 switch (config
->tx_type
) {
818 case HWTSTAMP_TX_OFF
:
826 switch (config
->rx_filter
) {
827 case HWTSTAMP_FILTER_NONE
:
830 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
831 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
832 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
835 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
836 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
837 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
840 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
841 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
842 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
843 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
844 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
845 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
846 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
847 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
848 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
849 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
850 config
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
854 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
855 case HWTSTAMP_FILTER_ALL
:
856 /* 82576 cannot timestamp all packets, which it needs to do to
857 * support both V1 Sync and Delay_Req messages
859 if (hw
->mac
.type
!= e1000_82576
) {
860 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
861 config
->rx_filter
= HWTSTAMP_FILTER_ALL
;
866 config
->rx_filter
= HWTSTAMP_FILTER_NONE
;
870 if (hw
->mac
.type
== e1000_82575
) {
871 if (tsync_rx_ctl
| tsync_tx_ctl
)
876 /* Per-packet timestamping only works if all packets are
877 * timestamped, so enable timestamping in all packets as
878 * long as one Rx filter was configured.
880 if ((hw
->mac
.type
>= e1000_82580
) && tsync_rx_ctl
) {
881 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
882 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
883 config
->rx_filter
= HWTSTAMP_FILTER_ALL
;
887 if ((hw
->mac
.type
== e1000_i210
) ||
888 (hw
->mac
.type
== e1000_i211
)) {
889 regval
= rd32(E1000_RXPBS
);
890 regval
|= E1000_RXPBS_CFG_TS_EN
;
891 wr32(E1000_RXPBS
, regval
);
895 /* enable/disable TX */
896 regval
= rd32(E1000_TSYNCTXCTL
);
897 regval
&= ~E1000_TSYNCTXCTL_ENABLED
;
898 regval
|= tsync_tx_ctl
;
899 wr32(E1000_TSYNCTXCTL
, regval
);
901 /* enable/disable RX */
902 regval
= rd32(E1000_TSYNCRXCTL
);
903 regval
&= ~(E1000_TSYNCRXCTL_ENABLED
| E1000_TSYNCRXCTL_TYPE_MASK
);
904 regval
|= tsync_rx_ctl
;
905 wr32(E1000_TSYNCRXCTL
, regval
);
907 /* define which PTP packets are time stamped */
908 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
910 /* define ethertype filter for timestamped packets */
913 (E1000_ETQF_FILTER_ENABLE
| /* enable filter */
914 E1000_ETQF_1588
| /* enable timestamping */
915 ETH_P_1588
)); /* 1588 eth protocol type */
917 wr32(E1000_ETQF(3), 0);
919 /* L4 Queue Filter[3]: filter by destination port and protocol */
921 u32 ftqf
= (IPPROTO_UDP
/* UDP */
922 | E1000_FTQF_VF_BP
/* VF not compared */
923 | E1000_FTQF_1588_TIME_STAMP
/* Enable Timestamping */
924 | E1000_FTQF_MASK
); /* mask all inputs */
925 ftqf
&= ~E1000_FTQF_MASK_PROTO_BP
; /* enable protocol check */
927 wr32(E1000_IMIR(3), htons(PTP_EV_PORT
));
928 wr32(E1000_IMIREXT(3),
929 (E1000_IMIREXT_SIZE_BP
| E1000_IMIREXT_CTRL_BP
));
930 if (hw
->mac
.type
== e1000_82576
) {
931 /* enable source port check */
932 wr32(E1000_SPQF(3), htons(PTP_EV_PORT
));
933 ftqf
&= ~E1000_FTQF_MASK_SOURCE_PORT_BP
;
935 wr32(E1000_FTQF(3), ftqf
);
937 wr32(E1000_FTQF(3), E1000_FTQF_MASK
);
941 /* clear TX/RX time stamp registers, just to be sure */
942 regval
= rd32(E1000_TXSTMPL
);
943 regval
= rd32(E1000_TXSTMPH
);
944 regval
= rd32(E1000_RXSTMPL
);
945 regval
= rd32(E1000_RXSTMPH
);
951 * igb_ptp_set_ts_config - set hardware time stamping config
956 int igb_ptp_set_ts_config(struct net_device
*netdev
, struct ifreq
*ifr
)
958 struct igb_adapter
*adapter
= netdev_priv(netdev
);
959 struct hwtstamp_config config
;
962 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
965 err
= igb_ptp_set_timestamp_mode(adapter
, &config
);
969 /* save these settings for future reference */
970 memcpy(&adapter
->tstamp_config
, &config
,
971 sizeof(adapter
->tstamp_config
));
973 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
977 void igb_ptp_init(struct igb_adapter
*adapter
)
979 struct e1000_hw
*hw
= &adapter
->hw
;
980 struct net_device
*netdev
= adapter
->netdev
;
983 switch (hw
->mac
.type
) {
985 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
986 adapter
->ptp_caps
.owner
= THIS_MODULE
;
987 adapter
->ptp_caps
.max_adj
= 999999881;
988 adapter
->ptp_caps
.n_ext_ts
= 0;
989 adapter
->ptp_caps
.pps
= 0;
990 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82576
;
991 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
992 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_82576
;
993 adapter
->ptp_caps
.settime
= igb_ptp_settime_82576
;
994 adapter
->ptp_caps
.enable
= igb_ptp_feature_enable
;
995 adapter
->cc
.read
= igb_ptp_read_82576
;
996 adapter
->cc
.mask
= CYCLECOUNTER_MASK(64);
997 adapter
->cc
.mult
= 1;
998 adapter
->cc
.shift
= IGB_82576_TSYNC_SHIFT
;
999 /* Dial the nominal frequency. */
1000 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
1005 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
1006 adapter
->ptp_caps
.owner
= THIS_MODULE
;
1007 adapter
->ptp_caps
.max_adj
= 62499999;
1008 adapter
->ptp_caps
.n_ext_ts
= 0;
1009 adapter
->ptp_caps
.pps
= 0;
1010 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
1011 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
1012 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_82576
;
1013 adapter
->ptp_caps
.settime
= igb_ptp_settime_82576
;
1014 adapter
->ptp_caps
.enable
= igb_ptp_feature_enable
;
1015 adapter
->cc
.read
= igb_ptp_read_82580
;
1016 adapter
->cc
.mask
= CYCLECOUNTER_MASK(IGB_NBITS_82580
);
1017 adapter
->cc
.mult
= 1;
1018 adapter
->cc
.shift
= 0;
1019 /* Enable the timer functions by clearing bit 31. */
1020 wr32(E1000_TSAUXC
, 0x0);
1024 for (i
= 0; i
< IGB_N_SDP
; i
++) {
1025 struct ptp_pin_desc
*ppd
= &adapter
->sdp_config
[i
];
1027 snprintf(ppd
->name
, sizeof(ppd
->name
), "SDP%d", i
);
1029 ppd
->func
= PTP_PF_NONE
;
1031 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
1032 adapter
->ptp_caps
.owner
= THIS_MODULE
;
1033 adapter
->ptp_caps
.max_adj
= 62499999;
1034 adapter
->ptp_caps
.n_ext_ts
= IGB_N_EXTTS
;
1035 adapter
->ptp_caps
.n_per_out
= IGB_N_PEROUT
;
1036 adapter
->ptp_caps
.n_pins
= IGB_N_SDP
;
1037 adapter
->ptp_caps
.pps
= 1;
1038 adapter
->ptp_caps
.pin_config
= adapter
->sdp_config
;
1039 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
1040 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_i210
;
1041 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_i210
;
1042 adapter
->ptp_caps
.settime
= igb_ptp_settime_i210
;
1043 adapter
->ptp_caps
.enable
= igb_ptp_feature_enable_i210
;
1044 adapter
->ptp_caps
.verify
= igb_ptp_verify_pin
;
1045 /* Enable the timer functions by clearing bit 31. */
1046 wr32(E1000_TSAUXC
, 0x0);
1049 adapter
->ptp_clock
= NULL
;
1055 spin_lock_init(&adapter
->tmreg_lock
);
1056 INIT_WORK(&adapter
->ptp_tx_work
, igb_ptp_tx_work
);
1058 /* Initialize the clock and overflow work for devices that need it. */
1059 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
1060 struct timespec ts
= ktime_to_timespec(ktime_get_real());
1062 igb_ptp_settime_i210(&adapter
->ptp_caps
, &ts
);
1064 timecounter_init(&adapter
->tc
, &adapter
->cc
,
1065 ktime_to_ns(ktime_get_real()));
1067 INIT_DELAYED_WORK(&adapter
->ptp_overflow_work
,
1068 igb_ptp_overflow_check
);
1070 schedule_delayed_work(&adapter
->ptp_overflow_work
,
1071 IGB_SYSTIM_OVERFLOW_PERIOD
);
1074 /* Initialize the time sync interrupts for devices that support it. */
1075 if (hw
->mac
.type
>= e1000_82580
) {
1076 wr32(E1000_TSIM
, TSYNC_INTERRUPTS
);
1077 wr32(E1000_IMS
, E1000_IMS_TS
);
1080 adapter
->tstamp_config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
1081 adapter
->tstamp_config
.tx_type
= HWTSTAMP_TX_OFF
;
1083 adapter
->ptp_clock
= ptp_clock_register(&adapter
->ptp_caps
,
1084 &adapter
->pdev
->dev
);
1085 if (IS_ERR(adapter
->ptp_clock
)) {
1086 adapter
->ptp_clock
= NULL
;
1087 dev_err(&adapter
->pdev
->dev
, "ptp_clock_register failed\n");
1089 dev_info(&adapter
->pdev
->dev
, "added PHC on %s\n",
1090 adapter
->netdev
->name
);
1091 adapter
->flags
|= IGB_FLAG_PTP
;
1096 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1097 * @adapter: Board private structure.
1099 * This function stops the PTP support and cancels the delayed work.
1101 void igb_ptp_stop(struct igb_adapter
*adapter
)
1103 switch (adapter
->hw
.mac
.type
) {
1108 cancel_delayed_work_sync(&adapter
->ptp_overflow_work
);
1112 /* No delayed work to cancel. */
1118 cancel_work_sync(&adapter
->ptp_tx_work
);
1119 if (adapter
->ptp_tx_skb
) {
1120 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
1121 adapter
->ptp_tx_skb
= NULL
;
1122 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS
, &adapter
->state
);
1125 if (adapter
->ptp_clock
) {
1126 ptp_clock_unregister(adapter
->ptp_clock
);
1127 dev_info(&adapter
->pdev
->dev
, "removed PHC on %s\n",
1128 adapter
->netdev
->name
);
1129 adapter
->flags
&= ~IGB_FLAG_PTP
;
1134 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1135 * @adapter: Board private structure.
1137 * This function handles the reset work required to re-enable the PTP device.
1139 void igb_ptp_reset(struct igb_adapter
*adapter
)
1141 struct e1000_hw
*hw
= &adapter
->hw
;
1142 unsigned long flags
;
1144 if (!(adapter
->flags
& IGB_FLAG_PTP
))
1147 /* reset the tstamp_config */
1148 igb_ptp_set_timestamp_mode(adapter
, &adapter
->tstamp_config
);
1150 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
1152 switch (adapter
->hw
.mac
.type
) {
1154 /* Dial the nominal frequency. */
1155 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
1162 wr32(E1000_TSAUXC
, 0x0);
1163 wr32(E1000_TSSDP
, 0x0);
1164 wr32(E1000_TSIM
, TSYNC_INTERRUPTS
);
1165 wr32(E1000_IMS
, E1000_IMS_TS
);
1168 /* No work to do. */
1172 /* Re-initialize the timer. */
1173 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
1174 struct timespec ts
= ktime_to_timespec(ktime_get_real());
1176 igb_ptp_write_i210(adapter
, &ts
);
1178 timecounter_init(&adapter
->tc
, &adapter
->cc
,
1179 ktime_to_ns(ktime_get_real()));
1182 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);