1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/types.h>
8 #include <linux/if_ether.h>
9 #include <linux/netdevice.h>
12 #include "igc_defines.h"
19 #define IGC_DEV_ID_I225_LM 0x15F2
20 #define IGC_DEV_ID_I225_V 0x15F3
21 #define IGC_DEV_ID_I225_I 0x15F8
22 #define IGC_DEV_ID_I220_V 0x15F7
23 #define IGC_DEV_ID_I225_K 0x3100
25 /* Function pointers for the MAC. */
26 struct igc_mac_operations
{
27 s32 (*check_for_link
)(struct igc_hw
*hw
);
28 s32 (*reset_hw
)(struct igc_hw
*hw
);
29 s32 (*init_hw
)(struct igc_hw
*hw
);
30 s32 (*setup_physical_interface
)(struct igc_hw
*hw
);
31 void (*rar_set
)(struct igc_hw
*hw
, u8
*address
, u32 index
);
32 s32 (*read_mac_addr
)(struct igc_hw
*hw
);
33 s32 (*get_speed_and_duplex
)(struct igc_hw
*hw
, u16
*speed
,
35 s32 (*acquire_swfw_sync
)(struct igc_hw
*hw
, u16 mask
);
36 void (*release_swfw_sync
)(struct igc_hw
*hw
, u16 mask
);
42 igc_num_macs
/* List is 1-based, so subtract 1 for true count. */
52 igc_media_type_unknown
= 0,
53 igc_media_type_copper
= 1,
65 s32 (*get_invariants
)(struct igc_hw
*hw
);
66 struct igc_mac_operations
*mac_ops
;
67 const struct igc_phy_operations
*phy_ops
;
68 struct igc_nvm_operations
*nvm_ops
;
71 extern const struct igc_info igc_base_info
;
74 struct igc_mac_operations ops
;
77 u8 perm_addr
[ETH_ALEN
];
79 enum igc_mac_type type
;
92 u32 mta_shadow
[MAX_MTA_REG
];
95 u8 forced_speed_duplex
;
99 bool asf_firmware_present
;
100 bool arc_subsystem_valid
;
104 bool get_link_status
;
107 struct igc_nvm_operations
{
108 s32 (*acquire
)(struct igc_hw
*hw
);
109 s32 (*read
)(struct igc_hw
*hw
, u16 offset
, u16 i
, u16
*data
);
110 void (*release
)(struct igc_hw
*hw
);
111 s32 (*write
)(struct igc_hw
*hw
, u16 offset
, u16 i
, u16
*data
);
112 s32 (*update
)(struct igc_hw
*hw
);
113 s32 (*validate
)(struct igc_hw
*hw
);
114 s32 (*valid_led_default
)(struct igc_hw
*hw
, u16
*data
);
117 struct igc_phy_operations
{
118 s32 (*acquire
)(struct igc_hw
*hw
);
119 s32 (*check_reset_block
)(struct igc_hw
*hw
);
120 s32 (*force_speed_duplex
)(struct igc_hw
*hw
);
121 s32 (*get_phy_info
)(struct igc_hw
*hw
);
122 s32 (*read_reg
)(struct igc_hw
*hw
, u32 address
, u16
*data
);
123 void (*release
)(struct igc_hw
*hw
);
124 s32 (*reset
)(struct igc_hw
*hw
);
125 s32 (*write_reg
)(struct igc_hw
*hw
, u32 address
, u16 data
);
128 struct igc_nvm_info
{
129 struct igc_nvm_operations ops
;
130 enum igc_nvm_type type
;
142 struct igc_phy_info
{
143 struct igc_phy_operations ops
;
145 enum igc_phy_type type
;
149 u32 reset_delay_us
; /* in usec */
152 enum igc_media_type media_type
;
154 u16 autoneg_advertised
;
161 bool speed_downgraded
;
162 bool autoneg_wait_to_complete
;
165 struct igc_bus_info
{
175 igc_fc_default
= 0xFF
179 u32 high_water
; /* Flow control high-water mark */
180 u32 low_water
; /* Flow control low-water mark */
181 u16 pause_time
; /* Flow control pause timer */
182 bool send_xon
; /* Flow control send XON */
183 bool strict_ieee
; /* Strict IEEE mode */
184 enum igc_fc_mode current_mode
; /* Type of flow control */
185 enum igc_fc_mode requested_mode
;
188 struct igc_dev_spec_base
{
189 bool clear_semaphore_once
;
196 unsigned long io_base
;
198 struct igc_mac_info mac
;
199 struct igc_fc_info fc
;
200 struct igc_nvm_info nvm
;
201 struct igc_phy_info phy
;
203 struct igc_bus_info bus
;
206 struct igc_dev_spec_base _base
;
210 u16 subsystem_vendor_id
;
211 u16 subsystem_device_id
;
217 /* Statistics counters collected by the MAC */
218 struct igc_hw_stats
{
301 struct net_device
*igc_get_hw_dev(struct igc_hw
*hw
);
302 #define hw_dbg(format, arg...) \
303 netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
305 s32
igc_read_pcie_cap_reg(struct igc_hw
*hw
, u32 reg
, u16
*value
);
306 s32
igc_write_pcie_cap_reg(struct igc_hw
*hw
, u32 reg
, u16
*value
);
307 void igc_read_pci_cfg(struct igc_hw
*hw
, u32 reg
, u16
*value
);
308 void igc_write_pci_cfg(struct igc_hw
*hw
, u32 reg
, u16
*value
);
310 #endif /* _IGC_HW_H_ */