drivers/net/ethernet/intel/igc/igc_hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c)  2018 Intel Corporation */
   3
   4 #ifndef _IGC_HW_H_
   5 #define _IGC_HW_H_
   6
   7 #include <linux/types.h>
   8 #include <linux/if_ether.h>
   9 #include <linux/netdevice.h>
  10
  11 #include "igc_regs.h"
  12 #include "igc_defines.h"
  13 #include "igc_mac.h"
  14 #include "igc_phy.h"
  15 #include "igc_nvm.h"
  16 #include "igc_i225.h"
  17 #include "igc_base.h"
  18
  19 #define IGC_DEV_ID_I225_LM                      0x15F2
  20 #define IGC_DEV_ID_I225_V                       0x15F3
  21 #define IGC_DEV_ID_I225_I                       0x15F8
  22 #define IGC_DEV_ID_I220_V                       0x15F7
  23 #define IGC_DEV_ID_I225_K                       0x3100
  24
  25 #define IGC_FUNC_0                              0
  26
  27 /* Function pointers for the MAC. */
  28 struct igc_mac_operations {
  29         s32 (*check_for_link)(struct igc_hw *hw);
  30         s32 (*reset_hw)(struct igc_hw *hw);
  31         s32 (*init_hw)(struct igc_hw *hw);
  32         s32 (*setup_physical_interface)(struct igc_hw *hw);
  33         void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
  34         s32 (*read_mac_addr)(struct igc_hw *hw);
  35         s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
  36                                     u16 *duplex);
  37         s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
  38         void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
  39 };
  40
  41 enum igc_mac_type {
  42         igc_undefined = 0,
  43         igc_i225,
  44         igc_num_macs  /* List is 1-based, so subtract 1 for true count. */
  45 };
  46
  47 enum igc_phy_type {
  48         igc_phy_unknown = 0,
  49         igc_phy_none,
  50         igc_phy_i225,
  51 };
  52
  53 enum igc_media_type {
  54         igc_media_type_unknown = 0,
  55         igc_media_type_copper = 1,
  56         igc_num_media_types
  57 };
  58
  59 enum igc_nvm_type {
  60         igc_nvm_unknown = 0,
  61         igc_nvm_eeprom_spi,
  62         igc_nvm_flash_hw,
  63         igc_nvm_invm,
  64 };
  65
  66 struct igc_info {
  67         s32 (*get_invariants)(struct igc_hw *hw);
  68         struct igc_mac_operations *mac_ops;
  69         const struct igc_phy_operations *phy_ops;
  70         struct igc_nvm_operations *nvm_ops;
  71 };
  72
  73 extern const struct igc_info igc_base_info;
  74
  75 struct igc_mac_info {
  76         struct igc_mac_operations ops;
  77
  78         u8 addr[ETH_ALEN];
  79         u8 perm_addr[ETH_ALEN];
  80
  81         enum igc_mac_type type;
  82
  83         u32 collision_delta;
  84         u32 ledctl_default;
  85         u32 ledctl_mode1;
  86         u32 ledctl_mode2;
  87         u32 mc_filter_type;
  88         u32 tx_packet_delta;
  89         u32 txcw;
  90
  91         u16 mta_reg_count;
  92         u16 uta_reg_count;
  93
  94         u32 mta_shadow[MAX_MTA_REG];
  95         u16 rar_entry_count;
  96
  97         u8 forced_speed_duplex;
  98
  99         bool adaptive_ifs;
 100         bool has_fwsm;
 101         bool asf_firmware_present;
 102         bool arc_subsystem_valid;
 103
 104         bool autoneg;
 105         bool autoneg_failed;
 106         bool get_link_status;
 107 };
 108
 109 struct igc_nvm_operations {
 110         s32 (*acquire)(struct igc_hw *hw);
 111         s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
 112         void (*release)(struct igc_hw *hw);
 113         s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
 114         s32 (*update)(struct igc_hw *hw);
 115         s32 (*validate)(struct igc_hw *hw);
 116         s32 (*valid_led_default)(struct igc_hw *hw, u16 *data);
 117 };
 118
 119 struct igc_phy_operations {
 120         s32 (*acquire)(struct igc_hw *hw);
 121         s32 (*check_reset_block)(struct igc_hw *hw);
 122         s32 (*force_speed_duplex)(struct igc_hw *hw);
 123         s32 (*get_phy_info)(struct igc_hw *hw);
 124         s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data);
 125         void (*release)(struct igc_hw *hw);
 126         s32 (*reset)(struct igc_hw *hw);
 127         s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data);
 128 };
 129
 130 struct igc_nvm_info {
 131         struct igc_nvm_operations ops;
 132         enum igc_nvm_type type;
 133
 134         u32 flash_bank_size;
 135         u32 flash_base_addr;
 136
 137         u16 word_size;
 138         u16 delay_usec;
 139         u16 address_bits;
 140         u16 opcode_bits;
 141         u16 page_size;
 142 };
 143
 144 struct igc_phy_info {
 145         struct igc_phy_operations ops;
 146
 147         enum igc_phy_type type;
 148
 149         u32 addr;
 150         u32 id;
 151         u32 reset_delay_us; /* in usec */
 152         u32 revision;
 153
 154         enum igc_media_type media_type;
 155
 156         u16 autoneg_advertised;
 157         u16 autoneg_mask;
 158
 159         u8 mdix;
 160
 161         bool is_mdix;
 162         bool reset_disable;
 163         bool speed_downgraded;
 164         bool autoneg_wait_to_complete;
 165 };
 166
 167 struct igc_bus_info {
 168         u16 func;
 169         u16 pci_cmd_word;
 170 };
 171
 172 enum igc_fc_mode {
 173         igc_fc_none = 0,
 174         igc_fc_rx_pause,
 175         igc_fc_tx_pause,
 176         igc_fc_full,
 177         igc_fc_default = 0xFF
 178 };
 179
 180 struct igc_fc_info {
 181         u32 high_water;     /* Flow control high-water mark */
 182         u32 low_water;      /* Flow control low-water mark */
 183         u16 pause_time;     /* Flow control pause timer */
 184         bool send_xon;      /* Flow control send XON */
 185         bool strict_ieee;   /* Strict IEEE mode */
 186         enum igc_fc_mode current_mode; /* Type of flow control */
 187         enum igc_fc_mode requested_mode;
 188 };
 189
 190 struct igc_dev_spec_base {
 191         bool clear_semaphore_once;
 192 };
 193
 194 struct igc_hw {
 195         void *back;
 196
 197         u8 __iomem *hw_addr;
 198         unsigned long io_base;
 199
 200         struct igc_mac_info  mac;
 201         struct igc_fc_info   fc;
 202         struct igc_nvm_info  nvm;
 203         struct igc_phy_info  phy;
 204
 205         struct igc_bus_info bus;
 206
 207         union {
 208                 struct igc_dev_spec_base        _base;
 209         } dev_spec;
 210
 211         u16 device_id;
 212         u16 subsystem_vendor_id;
 213         u16 subsystem_device_id;
 214         u16 vendor_id;
 215
 216         u8 revision_id;
 217 };
 218
 219 /* Statistics counters collected by the MAC */
 220 struct igc_hw_stats {
 221         u64 crcerrs;
 222         u64 algnerrc;
 223         u64 symerrs;
 224         u64 rxerrc;
 225         u64 mpc;
 226         u64 scc;
 227         u64 ecol;
 228         u64 mcc;
 229         u64 latecol;
 230         u64 colc;
 231         u64 dc;
 232         u64 tncrs;
 233         u64 sec;
 234         u64 cexterr;
 235         u64 rlec;
 236         u64 xonrxc;
 237         u64 xontxc;
 238         u64 xoffrxc;
 239         u64 xofftxc;
 240         u64 fcruc;
 241         u64 prc64;
 242         u64 prc127;
 243         u64 prc255;
 244         u64 prc511;
 245         u64 prc1023;
 246         u64 prc1522;
 247         u64 gprc;
 248         u64 bprc;
 249         u64 mprc;
 250         u64 gptc;
 251         u64 gorc;
 252         u64 gotc;
 253         u64 rnbc;
 254         u64 ruc;
 255         u64 rfc;
 256         u64 roc;
 257         u64 rjc;
 258         u64 mgprc;
 259         u64 mgpdc;
 260         u64 mgptc;
 261         u64 tor;
 262         u64 tot;
 263         u64 tpr;
 264         u64 tpt;
 265         u64 ptc64;
 266         u64 ptc127;
 267         u64 ptc255;
 268         u64 ptc511;
 269         u64 ptc1023;
 270         u64 ptc1522;
 271         u64 mptc;
 272         u64 bptc;
 273         u64 tsctc;
 274         u64 tsctfc;
 275         u64 iac;
 276         u64 icrxptc;
 277         u64 icrxatc;
 278         u64 ictxptc;
 279         u64 ictxatc;
 280         u64 ictxqec;
 281         u64 ictxqmtc;
 282         u64 icrxdmtc;
 283         u64 icrxoc;
 284         u64 cbtmpc;
 285         u64 htdpmc;
 286         u64 cbrdpc;
 287         u64 cbrmpc;
 288         u64 rpthc;
 289         u64 hgptc;
 290         u64 htcbdpc;
 291         u64 hgorc;
 292         u64 hgotc;
 293         u64 lenerrs;
 294         u64 scvpc;
 295         u64 hrmpc;
 296         u64 doosync;
 297         u64 o2bgptc;
 298         u64 o2bspc;
 299         u64 b2ospc;
 300         u64 b2ogprc;
 301 };
 302
 303 struct net_device *igc_get_hw_dev(struct igc_hw *hw);
 304 #define hw_dbg(format, arg...) \
 305         netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
 306
 307 s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
 308 s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
 309 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
 310 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
 311
 312 #endif /* _IGC_HW_H_ */