drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGBE_H_
  30 #define _IXGBE_H_
  31
  32 #include <linux/bitops.h>
  33 #include <linux/types.h>
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/cpumask.h>
  37 #include <linux/aer.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/jiffies.h>
  40
  41 #include <linux/timecounter.h>
  42 #include <linux/net_tstamp.h>
  43 #include <linux/ptp_clock_kernel.h>
  44
  45 #include "ixgbe_type.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb.h"
  48 #if IS_ENABLED(CONFIG_FCOE)
  49 #define IXGBE_FCOE
  50 #include "ixgbe_fcoe.h"
  51 #endif /* IS_ENABLED(CONFIG_FCOE) */
  52 #ifdef CONFIG_IXGBE_DCA
  53 #include <linux/dca.h>
  54 #endif
  55
  56 #include <net/busy_poll.h>
  57
  58 /* common prefix used by pr_<> macros */
  59 #undef pr_fmt
  60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  61
  62 /* TX/RX descriptor defines */
  63 #define IXGBE_DEFAULT_TXD                   512
  64 #define IXGBE_DEFAULT_TX_WORK               256
  65 #define IXGBE_MAX_TXD                      4096
  66 #define IXGBE_MIN_TXD                        64
  67
  68 #if (PAGE_SIZE < 8192)
  69 #define IXGBE_DEFAULT_RXD                   512
  70 #else
  71 #define IXGBE_DEFAULT_RXD                   128
  72 #endif
  73 #define IXGBE_MAX_RXD                      4096
  74 #define IXGBE_MIN_RXD                        64
  75
  76 #define IXGBE_ETH_P_LLDP                 0x88CC
  77
  78 /* flow control */
  79 #define IXGBE_MIN_FCRTL                    0x40
  80 #define IXGBE_MAX_FCRTL                 0x7FF80
  81 #define IXGBE_MIN_FCRTH                   0x600
  82 #define IXGBE_MAX_FCRTH                 0x7FFF0
  83 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  84 #define IXGBE_MIN_FCPAUSE                     0
  85 #define IXGBE_MAX_FCPAUSE                0xFFFF
  86
  87 /* Supported Rx Buffer Sizes */
  88 #define IXGBE_RXBUFFER_256    256  /* Used for skb receive header */
  89 #define IXGBE_RXBUFFER_2K    2048
  90 #define IXGBE_RXBUFFER_3K    3072
  91 #define IXGBE_RXBUFFER_4K    4096
  92 #define IXGBE_MAX_RXBUFFER  16384  /* largest size for a single descriptor */
  93
  94 #define IXGBE_SKB_PAD           (NET_SKB_PAD + NET_IP_ALIGN)
  95 #if (PAGE_SIZE < 8192)
  96 #define IXGBE_MAX_FRAME_BUILD_SKB \
  97         (SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K) - IXGBE_SKB_PAD)
  98 #else
  99 #define IGB_MAX_FRAME_BUILD_SKB IXGBE_RXBUFFER_2K
 100 #endif
 101
 102 /*
 103  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
 104  * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
 105  * this adds up to 448 bytes of extra data.
 106  *
 107  * Since netdev_alloc_skb now allocates a page fragment we can use a value
 108  * of 256 and the resultant skb will have a truesize of 960 or less.
 109  */
 110 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
 111
 112 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 113 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
 114
 115 #define IXGBE_RX_DMA_ATTR \
 116         (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
 117
 118 enum ixgbe_tx_flags {
 119         /* cmd_type flags */
 120         IXGBE_TX_FLAGS_HW_VLAN  = 0x01,
 121         IXGBE_TX_FLAGS_TSO      = 0x02,
 122         IXGBE_TX_FLAGS_TSTAMP   = 0x04,
 123
 124         /* olinfo flags */
 125         IXGBE_TX_FLAGS_CC       = 0x08,
 126         IXGBE_TX_FLAGS_IPV4     = 0x10,
 127         IXGBE_TX_FLAGS_CSUM     = 0x20,
 128
 129         /* software defined flags */
 130         IXGBE_TX_FLAGS_SW_VLAN  = 0x40,
 131         IXGBE_TX_FLAGS_FCOE     = 0x80,
 132 };
 133
 134 /* VLAN info */
 135 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 136 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 137 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 138 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 139
 140 #define IXGBE_MAX_VF_MC_ENTRIES         30
 141 #define IXGBE_MAX_VF_FUNCTIONS          64
 142 #define IXGBE_MAX_VFTA_ENTRIES          128
 143 #define MAX_EMULATION_MAC_ADDRS         16
 144 #define IXGBE_MAX_PF_MACVLANS           15
 145 #define VMDQ_P(p)   ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
 146 #define IXGBE_82599_VF_DEVICE_ID        0x10ED
 147 #define IXGBE_X540_VF_DEVICE_ID         0x1515
 148
 149 struct vf_data_storage {
 150         struct pci_dev *vfdev;
 151         unsigned char vf_mac_addresses[ETH_ALEN];
 152         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 153         u16 num_vf_mc_hashes;
 154         bool clear_to_send;
 155         bool pf_set_mac;
 156         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 157         u16 pf_qos;
 158         u16 tx_rate;
 159         u8 spoofchk_enabled;
 160         bool rss_query_enabled;
 161         u8 trusted;
 162         int xcast_mode;
 163         unsigned int vf_api;
 164 };
 165
 166 enum ixgbevf_xcast_modes {
 167         IXGBEVF_XCAST_MODE_NONE = 0,
 168         IXGBEVF_XCAST_MODE_MULTI,
 169         IXGBEVF_XCAST_MODE_ALLMULTI,
 170         IXGBEVF_XCAST_MODE_PROMISC,
 171 };
 172
 173 struct vf_macvlans {
 174         struct list_head l;
 175         int vf;
 176         bool free;
 177         bool is_macvlan;
 178         u8 vf_macvlan[ETH_ALEN];
 179 };
 180
 181 #define IXGBE_MAX_TXD_PWR       14
 182 #define IXGBE_MAX_DATA_PER_TXD  (1u << IXGBE_MAX_TXD_PWR)
 183
 184 /* Tx Descriptors needed, worst case */
 185 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 186 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 187
 188 /* wrapper around a pointer to a socket buffer,
 189  * so a DMA handle can be stored along with the buffer */
 190 struct ixgbe_tx_buffer {
 191         union ixgbe_adv_tx_desc *next_to_watch;
 192         unsigned long time_stamp;
 193         struct sk_buff *skb;
 194         unsigned int bytecount;
 195         unsigned short gso_segs;
 196         __be16 protocol;
 197         DEFINE_DMA_UNMAP_ADDR(dma);
 198         DEFINE_DMA_UNMAP_LEN(len);
 199         u32 tx_flags;
 200 };
 201
 202 struct ixgbe_rx_buffer {
 203         struct sk_buff *skb;
 204         dma_addr_t dma;
 205         struct page *page;
 206 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
 207         __u32 page_offset;
 208 #else
 209         __u16 page_offset;
 210 #endif
 211         __u16 pagecnt_bias;
 212 };
 213
 214 struct ixgbe_queue_stats {
 215         u64 packets;
 216         u64 bytes;
 217 };
 218
 219 struct ixgbe_tx_queue_stats {
 220         u64 restart_queue;
 221         u64 tx_busy;
 222         u64 tx_done_old;
 223 };
 224
 225 struct ixgbe_rx_queue_stats {
 226         u64 rsc_count;
 227         u64 rsc_flush;
 228         u64 non_eop_descs;
 229         u64 alloc_rx_page_failed;
 230         u64 alloc_rx_buff_failed;
 231         u64 csum_err;
 232 };
 233
 234 #define IXGBE_TS_HDR_LEN 8
 235
 236 enum ixgbe_ring_state_t {
 237         __IXGBE_RX_3K_BUFFER,
 238         __IXGBE_RX_BUILD_SKB_ENABLED,
 239         __IXGBE_RX_RSC_ENABLED,
 240         __IXGBE_RX_CSUM_UDP_ZERO_ERR,
 241         __IXGBE_RX_FCOE,
 242         __IXGBE_TX_FDIR_INIT_DONE,
 243         __IXGBE_TX_XPS_INIT_DONE,
 244         __IXGBE_TX_DETECT_HANG,
 245         __IXGBE_HANG_CHECK_ARMED,
 246 };
 247
 248 #define ring_uses_build_skb(ring) \
 249         test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state)
 250
 251 struct ixgbe_fwd_adapter {
 252         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 253         struct net_device *netdev;
 254         struct ixgbe_adapter *real_adapter;
 255         unsigned int tx_base_queue;
 256         unsigned int rx_base_queue;
 257         int pool;
 258 };
 259
 260 #define check_for_tx_hang(ring) \
 261         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 262 #define set_check_for_tx_hang(ring) \
 263         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 264 #define clear_check_for_tx_hang(ring) \
 265         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 266 #define ring_is_rsc_enabled(ring) \
 267         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 268 #define set_ring_rsc_enabled(ring) \
 269         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 270 #define clear_ring_rsc_enabled(ring) \
 271         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 272 struct ixgbe_ring {
 273         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 274         struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
 275         struct net_device *netdev;      /* netdev ring belongs to */
 276         struct device *dev;             /* device for DMA mapping */
 277         struct ixgbe_fwd_adapter *l2_accel_priv;
 278         void *desc;                     /* descriptor ring memory */
 279         union {
 280                 struct ixgbe_tx_buffer *tx_buffer_info;
 281                 struct ixgbe_rx_buffer *rx_buffer_info;
 282         };
 283         unsigned long state;
 284         u8 __iomem *tail;
 285         dma_addr_t dma;                 /* phys. address of descriptor ring */
 286         unsigned int size;              /* length in bytes */
 287
 288         u16 count;                      /* amount of descriptors */
 289
 290         u8 queue_index; /* needed for multiqueue queue management */
 291         u8 reg_idx;                     /* holds the special value that gets
 292                                          * the hardware register offset
 293                                          * associated with this ring, which is
 294                                          * different for DCB and RSS modes
 295                                          */
 296         u16 next_to_use;
 297         u16 next_to_clean;
 298
 299         unsigned long last_rx_timestamp;
 300
 301         union {
 302                 u16 next_to_alloc;
 303                 struct {
 304                         u8 atr_sample_rate;
 305                         u8 atr_count;
 306                 };
 307         };
 308
 309         u8 dcb_tc;
 310         struct ixgbe_queue_stats stats;
 311         struct u64_stats_sync syncp;
 312         union {
 313                 struct ixgbe_tx_queue_stats tx_stats;
 314                 struct ixgbe_rx_queue_stats rx_stats;
 315         };
 316 } ____cacheline_internodealigned_in_smp;
 317
 318 enum ixgbe_ring_f_enum {
 319         RING_F_NONE = 0,
 320         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 321         RING_F_RSS,
 322         RING_F_FDIR,
 323 #ifdef IXGBE_FCOE
 324         RING_F_FCOE,
 325 #endif /* IXGBE_FCOE */
 326
 327         RING_F_ARRAY_SIZE      /* must be last in enum set */
 328 };
 329
 330 #define IXGBE_MAX_RSS_INDICES           16
 331 #define IXGBE_MAX_RSS_INDICES_X550      63
 332 #define IXGBE_MAX_VMDQ_INDICES          64
 333 #define IXGBE_MAX_FDIR_INDICES          63      /* based on q_vector limit */
 334 #define IXGBE_MAX_FCOE_INDICES          8
 335 #define MAX_RX_QUEUES                   (IXGBE_MAX_FDIR_INDICES + 1)
 336 #define MAX_TX_QUEUES                   (IXGBE_MAX_FDIR_INDICES + 1)
 337 #define IXGBE_MAX_L2A_QUEUES            4
 338 #define IXGBE_BAD_L2A_QUEUE             3
 339 #define IXGBE_MAX_MACVLANS              31
 340 #define IXGBE_MAX_DCBMACVLANS           8
 341
 342 struct ixgbe_ring_feature {
 343         u16 limit;      /* upper limit on feature indices */
 344         u16 indices;    /* current value of indices */
 345         u16 mask;       /* Mask used for feature to ring mapping */
 346         u16 offset;     /* offset to start of feature */
 347 } ____cacheline_internodealigned_in_smp;
 348
 349 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
 350 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
 351 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
 352
 353 /*
 354  * FCoE requires that all Rx buffers be over 2200 bytes in length.  Since
 355  * this is twice the size of a half page we need to double the page order
 356  * for FCoE enabled Rx queues.
 357  */
 358 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
 359 {
 360         if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
 361                 return IXGBE_RXBUFFER_3K;
 362 #if (PAGE_SIZE < 8192)
 363         if (ring_uses_build_skb(ring))
 364                 return IXGBE_MAX_FRAME_BUILD_SKB;
 365 #endif
 366         return IXGBE_RXBUFFER_2K;
 367 }
 368
 369 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
 370 {
 371 #if (PAGE_SIZE < 8192)
 372         if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
 373                 return 1;
 374 #endif
 375         return 0;
 376 }
 377 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
 378
 379 struct ixgbe_ring_container {
 380         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 381         unsigned int total_bytes;       /* total bytes processed this int */
 382         unsigned int total_packets;     /* total packets processed this int */
 383         u16 work_limit;                 /* total work allowed per interrupt */
 384         u8 count;                       /* total number of rings in vector */
 385         u8 itr;                         /* current ITR setting for ring */
 386 };
 387
 388 /* iterator for handling rings in ring container */
 389 #define ixgbe_for_each_ring(pos, head) \
 390         for (pos = (head).ring; pos != NULL; pos = pos->next)
 391
 392 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 393                               ? 8 : 1)
 394 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 395
 396 /* MAX_Q_VECTORS of these are allocated,
 397  * but we only use one per queue-specific vector.
 398  */
 399 struct ixgbe_q_vector {
 400         struct ixgbe_adapter *adapter;
 401 #ifdef CONFIG_IXGBE_DCA
 402         int cpu;            /* CPU for DCA */
 403 #endif
 404         u16 v_idx;              /* index of q_vector within array, also used for
 405                                  * finding the bit in EICR and friends that
 406                                  * represents the vector for this ring */
 407         u16 itr;                /* Interrupt throttle rate written to EITR */
 408         struct ixgbe_ring_container rx, tx;
 409
 410         struct napi_struct napi;
 411         cpumask_t affinity_mask;
 412         int numa_node;
 413         struct rcu_head rcu;    /* to avoid race with update stats on free */
 414         char name[IFNAMSIZ + 9];
 415
 416         /* for dynamic allocation of rings associated with this q_vector */
 417         struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
 418 };
 419
 420 #ifdef CONFIG_IXGBE_HWMON
 421
 422 #define IXGBE_HWMON_TYPE_LOC            0
 423 #define IXGBE_HWMON_TYPE_TEMP           1
 424 #define IXGBE_HWMON_TYPE_CAUTION        2
 425 #define IXGBE_HWMON_TYPE_MAX            3
 426
 427 struct hwmon_attr {
 428         struct device_attribute dev_attr;
 429         struct ixgbe_hw *hw;
 430         struct ixgbe_thermal_diode_data *sensor;
 431         char name[12];
 432 };
 433
 434 struct hwmon_buff {
 435         struct attribute_group group;
 436         const struct attribute_group *groups[2];
 437         struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
 438         struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
 439         unsigned int n_hwmon;
 440 };
 441 #endif /* CONFIG_IXGBE_HWMON */
 442
 443 /*
 444  * microsecond values for various ITR rates shifted by 2 to fit itr register
 445  * with the first 3 bits reserved 0
 446  */
 447 #define IXGBE_MIN_RSC_ITR       24
 448 #define IXGBE_100K_ITR          40
 449 #define IXGBE_20K_ITR           200
 450 #define IXGBE_12K_ITR           336
 451
 452 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
 453 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
 454                                         const u32 stat_err_bits)
 455 {
 456         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 457 }
 458
 459 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 460 {
 461         u16 ntc = ring->next_to_clean;
 462         u16 ntu = ring->next_to_use;
 463
 464         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 465 }
 466
 467 #define IXGBE_RX_DESC(R, i)         \
 468         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 469 #define IXGBE_TX_DESC(R, i)         \
 470         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 471 #define IXGBE_TX_CTXTDESC(R, i)     \
 472         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 473
 474 #define IXGBE_MAX_JUMBO_FRAME_SIZE      9728 /* Maximum Supported Size 9.5KB */
 475 #ifdef IXGBE_FCOE
 476 /* Use 3K as the baby jumbo frame size for FCoE */
 477 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 478 #endif /* IXGBE_FCOE */
 479
 480 #define OTHER_VECTOR 1
 481 #define NON_Q_VECTORS (OTHER_VECTOR)
 482
 483 #define MAX_MSIX_VECTORS_82599 64
 484 #define MAX_Q_VECTORS_82599 64
 485 #define MAX_MSIX_VECTORS_82598 18
 486 #define MAX_Q_VECTORS_82598 16
 487
 488 struct ixgbe_mac_addr {
 489         u8 addr[ETH_ALEN];
 490         u16 pool;
 491         u16 state; /* bitmask */
 492 };
 493
 494 #define IXGBE_MAC_STATE_DEFAULT         0x1
 495 #define IXGBE_MAC_STATE_MODIFIED        0x2
 496 #define IXGBE_MAC_STATE_IN_USE          0x4
 497
 498 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
 499 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 500
 501 #define MIN_MSIX_Q_VECTORS 1
 502 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 503
 504 /* default to trying for four seconds */
 505 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 506 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
 507
 508 /* board specific private data structure */
 509 struct ixgbe_adapter {
 510         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 511         /* OS defined structs */
 512         struct net_device *netdev;
 513         struct pci_dev *pdev;
 514
 515         unsigned long state;
 516
 517         /* Some features need tri-state capability,
 518          * thus the additional *_CAPABLE flags.
 519          */
 520         u32 flags;
 521 #define IXGBE_FLAG_MSI_ENABLED                  BIT(1)
 522 #define IXGBE_FLAG_MSIX_ENABLED                 BIT(3)
 523 #define IXGBE_FLAG_RX_1BUF_CAPABLE              BIT(4)
 524 #define IXGBE_FLAG_RX_PS_CAPABLE                BIT(5)
 525 #define IXGBE_FLAG_RX_PS_ENABLED                BIT(6)
 526 #define IXGBE_FLAG_DCA_ENABLED                  BIT(8)
 527 #define IXGBE_FLAG_DCA_CAPABLE                  BIT(9)
 528 #define IXGBE_FLAG_IMIR_ENABLED                 BIT(10)
 529 #define IXGBE_FLAG_MQ_CAPABLE                   BIT(11)
 530 #define IXGBE_FLAG_DCB_ENABLED                  BIT(12)
 531 #define IXGBE_FLAG_VMDQ_CAPABLE                 BIT(13)
 532 #define IXGBE_FLAG_VMDQ_ENABLED                 BIT(14)
 533 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             BIT(15)
 534 #define IXGBE_FLAG_NEED_LINK_UPDATE             BIT(16)
 535 #define IXGBE_FLAG_NEED_LINK_CONFIG             BIT(17)
 536 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            BIT(18)
 537 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         BIT(19)
 538 #define IXGBE_FLAG_FCOE_CAPABLE                 BIT(20)
 539 #define IXGBE_FLAG_FCOE_ENABLED                 BIT(21)
 540 #define IXGBE_FLAG_SRIOV_CAPABLE                BIT(22)
 541 #define IXGBE_FLAG_SRIOV_ENABLED                BIT(23)
 542 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE        BIT(24)
 543 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED          BIT(25)
 544 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER      BIT(26)
 545 #define IXGBE_FLAG_DCB_CAPABLE                  BIT(27)
 546 #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE       BIT(28)
 547
 548         u32 flags2;
 549 #define IXGBE_FLAG2_RSC_CAPABLE                 BIT(0)
 550 #define IXGBE_FLAG2_RSC_ENABLED                 BIT(1)
 551 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         BIT(2)
 552 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           BIT(3)
 553 #define IXGBE_FLAG2_SEARCH_FOR_SFP              BIT(4)
 554 #define IXGBE_FLAG2_SFP_NEEDS_RESET             BIT(5)
 555 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        BIT(7)
 556 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP          BIT(8)
 557 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP          BIT(9)
 558 #define IXGBE_FLAG2_PTP_PPS_ENABLED             BIT(10)
 559 #define IXGBE_FLAG2_PHY_INTERRUPT               BIT(11)
 560 #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED        BIT(12)
 561 #define IXGBE_FLAG2_VLAN_PROMISC                BIT(13)
 562 #define IXGBE_FLAG2_EEE_CAPABLE                 BIT(14)
 563 #define IXGBE_FLAG2_EEE_ENABLED                 BIT(15)
 564 #define IXGBE_FLAG2_RX_LEGACY                   BIT(16)
 565
 566         /* Tx fast path data */
 567         int num_tx_queues;
 568         u16 tx_itr_setting;
 569         u16 tx_work_limit;
 570
 571         /* Rx fast path data */
 572         int num_rx_queues;
 573         u16 rx_itr_setting;
 574
 575         /* Port number used to identify VXLAN traffic */
 576         __be16 vxlan_port;
 577         __be16 geneve_port;
 578
 579         /* TX */
 580         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 581
 582         u64 restart_queue;
 583         u64 lsc_int;
 584         u32 tx_timeout_count;
 585
 586         /* RX */
 587         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
 588         int num_rx_pools;               /* == num_rx_queues in 82598 */
 589         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 590         u64 hw_csum_rx_error;
 591         u64 hw_rx_no_dma_resources;
 592         u64 rsc_total_count;
 593         u64 rsc_total_flush;
 594         u64 non_eop_descs;
 595         u32 alloc_rx_page_failed;
 596         u32 alloc_rx_buff_failed;
 597
 598         struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
 599
 600         /* DCB parameters */
 601         struct ieee_pfc *ixgbe_ieee_pfc;
 602         struct ieee_ets *ixgbe_ieee_ets;
 603         struct ixgbe_dcb_config dcb_cfg;
 604         struct ixgbe_dcb_config temp_dcb_cfg;
 605         u8 dcb_set_bitmap;
 606         u8 dcbx_cap;
 607         enum ixgbe_fc_mode last_lfc_mode;
 608
 609         int num_q_vectors;      /* current number of q_vectors for device */
 610         int max_q_vectors;      /* true count of q_vectors for device */
 611         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 612         struct msix_entry *msix_entries;
 613
 614         u32 test_icr;
 615         struct ixgbe_ring test_tx_ring;
 616         struct ixgbe_ring test_rx_ring;
 617
 618         /* structs defined in ixgbe_hw.h */
 619         struct ixgbe_hw hw;
 620         u16 msg_enable;
 621         struct ixgbe_hw_stats stats;
 622
 623         u64 tx_busy;
 624         unsigned int tx_ring_count;
 625         unsigned int rx_ring_count;
 626
 627         u32 link_speed;
 628         bool link_up;
 629         unsigned long sfp_poll_time;
 630         unsigned long link_check_timeout;
 631
 632         struct timer_list service_timer;
 633         struct work_struct service_task;
 634
 635         struct hlist_head fdir_filter_list;
 636         unsigned long fdir_overflow; /* number of times ATR was backed off */
 637         union ixgbe_atr_input fdir_mask;
 638         int fdir_filter_count;
 639         u32 fdir_pballoc;
 640         u32 atr_sample_rate;
 641         spinlock_t fdir_perfect_lock;
 642
 643 #ifdef IXGBE_FCOE
 644         struct ixgbe_fcoe fcoe;
 645 #endif /* IXGBE_FCOE */
 646         u8 __iomem *io_addr; /* Mainly for iounmap use */
 647         u32 wol;
 648
 649         u16 bridge_mode;
 650
 651         u16 eeprom_verh;
 652         u16 eeprom_verl;
 653         u16 eeprom_cap;
 654
 655         u32 interrupt_event;
 656         u32 led_reg;
 657
 658         struct ptp_clock *ptp_clock;
 659         struct ptp_clock_info ptp_caps;
 660         struct work_struct ptp_tx_work;
 661         struct sk_buff *ptp_tx_skb;
 662         struct hwtstamp_config tstamp_config;
 663         unsigned long ptp_tx_start;
 664         unsigned long last_overflow_check;
 665         unsigned long last_rx_ptp_check;
 666         unsigned long last_rx_timestamp;
 667         spinlock_t tmreg_lock;
 668         struct cyclecounter hw_cc;
 669         struct timecounter hw_tc;
 670         u32 base_incval;
 671         u32 tx_hwtstamp_timeouts;
 672         u32 rx_hwtstamp_cleared;
 673         void (*ptp_setup_sdp)(struct ixgbe_adapter *);
 674
 675         /* SR-IOV */
 676         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 677         unsigned int num_vfs;
 678         struct vf_data_storage *vfinfo;
 679         int vf_rate_link_speed;
 680         struct vf_macvlans vf_mvs;
 681         struct vf_macvlans *mv_list;
 682
 683         u32 timer_event_accumulator;
 684         u32 vferr_refcount;
 685         struct ixgbe_mac_addr *mac_table;
 686         struct kobject *info_kobj;
 687 #ifdef CONFIG_IXGBE_HWMON
 688         struct hwmon_buff *ixgbe_hwmon_buff;
 689 #endif /* CONFIG_IXGBE_HWMON */
 690 #ifdef CONFIG_DEBUG_FS
 691         struct dentry *ixgbe_dbg_adapter;
 692 #endif /*CONFIG_DEBUG_FS*/
 693
 694         u8 default_up;
 695         unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
 696
 697 #define IXGBE_MAX_LINK_HANDLE 10
 698         struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
 699         unsigned long tables;
 700
 701 /* maximum number of RETA entries among all devices supported by ixgbe
 702  * driver: currently it's x550 device in non-SRIOV mode
 703  */
 704 #define IXGBE_MAX_RETA_ENTRIES 512
 705         u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
 706
 707 #define IXGBE_RSS_KEY_SIZE     40  /* size of RSS Hash Key in bytes */
 708         u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)];
 709 };
 710
 711 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
 712 {
 713         switch (adapter->hw.mac.type) {
 714         case ixgbe_mac_82598EB:
 715         case ixgbe_mac_82599EB:
 716         case ixgbe_mac_X540:
 717                 return IXGBE_MAX_RSS_INDICES;
 718         case ixgbe_mac_X550:
 719         case ixgbe_mac_X550EM_x:
 720         case ixgbe_mac_x550em_a:
 721                 return IXGBE_MAX_RSS_INDICES_X550;
 722         default:
 723                 return 0;
 724         }
 725 }
 726
 727 struct ixgbe_fdir_filter {
 728         struct hlist_node fdir_node;
 729         union ixgbe_atr_input filter;
 730         u16 sw_idx;
 731         u64 action;
 732 };
 733
 734 enum ixgbe_state_t {
 735         __IXGBE_TESTING,
 736         __IXGBE_RESETTING,
 737         __IXGBE_DOWN,
 738         __IXGBE_DISABLED,
 739         __IXGBE_REMOVING,
 740         __IXGBE_SERVICE_SCHED,
 741         __IXGBE_SERVICE_INITED,
 742         __IXGBE_IN_SFP_INIT,
 743         __IXGBE_PTP_RUNNING,
 744         __IXGBE_PTP_TX_IN_PROGRESS,
 745         __IXGBE_RESET_REQUESTED,
 746 };
 747
 748 struct ixgbe_cb {
 749         union {                         /* Union defining head/tail partner */
 750                 struct sk_buff *head;
 751                 struct sk_buff *tail;
 752         };
 753         dma_addr_t dma;
 754         u16 append_cnt;
 755         bool page_released;
 756 };
 757 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
 758
 759 enum ixgbe_boards {
 760         board_82598,
 761         board_82599,
 762         board_X540,
 763         board_X550,
 764         board_X550EM_x,
 765         board_x550em_a,
 766         board_x550em_a_fw,
 767 };
 768
 769 extern const struct ixgbe_info ixgbe_82598_info;
 770 extern const struct ixgbe_info ixgbe_82599_info;
 771 extern const struct ixgbe_info ixgbe_X540_info;
 772 extern const struct ixgbe_info ixgbe_X550_info;
 773 extern const struct ixgbe_info ixgbe_X550EM_x_info;
 774 extern const struct ixgbe_info ixgbe_x550em_a_info;
 775 extern const struct ixgbe_info ixgbe_x550em_a_fw_info;
 776 #ifdef CONFIG_IXGBE_DCB
 777 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops;
 778 #endif
 779
 780 extern char ixgbe_driver_name[];
 781 extern const char ixgbe_driver_version[];
 782 #ifdef IXGBE_FCOE
 783 extern char ixgbe_default_device_descr[];
 784 #endif /* IXGBE_FCOE */
 785
 786 int ixgbe_open(struct net_device *netdev);
 787 int ixgbe_close(struct net_device *netdev);
 788 void ixgbe_up(struct ixgbe_adapter *adapter);
 789 void ixgbe_down(struct ixgbe_adapter *adapter);
 790 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 791 void ixgbe_reset(struct ixgbe_adapter *adapter);
 792 void ixgbe_set_ethtool_ops(struct net_device *netdev);
 793 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 794 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 795 void ixgbe_free_rx_resources(struct ixgbe_ring *);
 796 void ixgbe_free_tx_resources(struct ixgbe_ring *);
 797 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
 798 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
 799 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
 800 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 801 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 802 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
 803                          u16 subdevice_id);
 804 #ifdef CONFIG_PCI_IOV
 805 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
 806 #endif
 807 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
 808                          const u8 *addr, u16 queue);
 809 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
 810                          const u8 *addr, u16 queue);
 811 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
 812 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 813 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
 814                                   struct ixgbe_ring *);
 815 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 816                                       struct ixgbe_tx_buffer *);
 817 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 818 void ixgbe_write_eitr(struct ixgbe_q_vector *);
 819 int ixgbe_poll(struct napi_struct *napi, int budget);
 820 int ethtool_ioctl(struct ifreq *ifr);
 821 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 822 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 823 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 824 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 825                                           union ixgbe_atr_hash_dword input,
 826                                           union ixgbe_atr_hash_dword common,
 827                                           u8 queue);
 828 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 829                                     union ixgbe_atr_input *input_mask);
 830 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 831                                           union ixgbe_atr_input *input,
 832                                           u16 soft_id, u8 queue);
 833 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 834                                           union ixgbe_atr_input *input,
 835                                           u16 soft_id);
 836 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 837                                           union ixgbe_atr_input *mask);
 838 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
 839                                     struct ixgbe_fdir_filter *input,
 840                                     u16 sw_idx);
 841 void ixgbe_set_rx_mode(struct net_device *netdev);
 842 #ifdef CONFIG_IXGBE_DCB
 843 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
 844 #endif
 845 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 846 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 847 void ixgbe_do_reset(struct net_device *netdev);
 848 #ifdef CONFIG_IXGBE_HWMON
 849 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
 850 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
 851 #endif /* CONFIG_IXGBE_HWMON */
 852 #ifdef IXGBE_FCOE
 853 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 854 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
 855               u8 *hdr_len);
 856 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 857                    union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
 858 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 859                        struct scatterlist *sgl, unsigned int sgc);
 860 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 861                           struct scatterlist *sgl, unsigned int sgc);
 862 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 863 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
 864 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
 865 int ixgbe_fcoe_enable(struct net_device *netdev);
 866 int ixgbe_fcoe_disable(struct net_device *netdev);
 867 #ifdef CONFIG_IXGBE_DCB
 868 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 869 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 870 #endif /* CONFIG_IXGBE_DCB */
 871 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 872 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
 873                            struct netdev_fcoe_hbainfo *info);
 874 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
 875 #endif /* IXGBE_FCOE */
 876 #ifdef CONFIG_DEBUG_FS
 877 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
 878 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
 879 void ixgbe_dbg_init(void);
 880 void ixgbe_dbg_exit(void);
 881 #else
 882 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
 883 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
 884 static inline void ixgbe_dbg_init(void) {}
 885 static inline void ixgbe_dbg_exit(void) {}
 886 #endif /* CONFIG_DEBUG_FS */
 887 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
 888 {
 889         return netdev_get_tx_queue(ring->netdev, ring->queue_index);
 890 }
 891
 892 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
 893 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
 894 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
 895 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
 896 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
 897 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
 898 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
 899 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
 900                                          union ixgbe_adv_rx_desc *rx_desc,
 901                                          struct sk_buff *skb)
 902 {
 903         if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
 904                 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
 905                 return;
 906         }
 907
 908         if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
 909                 return;
 910
 911         ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
 912
 913         /* Update the last_rx_timestamp timer in order to enable watchdog check
 914          * for error case of latched timestamp on a dropped packet.
 915          */
 916         rx_ring->last_rx_timestamp = jiffies;
 917 }
 918
 919 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
 920 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
 921 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
 922 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
 923 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
 924 #ifdef CONFIG_PCI_IOV
 925 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
 926 #endif
 927
 928 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
 929                                   struct ixgbe_adapter *adapter,
 930                                   struct ixgbe_ring *tx_ring);
 931 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
 932 void ixgbe_store_reta(struct ixgbe_adapter *adapter);
 933 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
 934                        u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
 935 #endif /* _IXGBE_H_ */