drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_DEFAULT_TX_WORK               256
  57 #define IXGBE_MAX_TXD                      4096
  58 #define IXGBE_MIN_TXD                        64
  59
  60 #define IXGBE_DEFAULT_RXD                   512
  61 #define IXGBE_MAX_RXD                      4096
  62 #define IXGBE_MIN_RXD                        64
  63
  64 /* flow control */
  65 #define IXGBE_MIN_FCRTL                    0x40
  66 #define IXGBE_MAX_FCRTL                 0x7FF80
  67 #define IXGBE_MIN_FCRTH                   0x600
  68 #define IXGBE_MAX_FCRTH                 0x7FFF0
  69 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  70 #define IXGBE_MIN_FCPAUSE                     0
  71 #define IXGBE_MAX_FCPAUSE                0xFFFF
  72
  73 /* Supported Rx Buffer Sizes */
  74 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  75 #define IXGBE_RXBUFFER_2K   2048
  76 #define IXGBE_RXBUFFER_3K   3072
  77 #define IXGBE_RXBUFFER_4K   4096
  78 #define IXGBE_RXBUFFER_7K   7168
  79 #define IXGBE_RXBUFFER_8K   8192
  80 #define IXGBE_RXBUFFER_15K  15360
  81 #define IXGBE_MAX_RXBUFFER  16384  /* largest size for a single descriptor */
  82
  83 /*
  84  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  85  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  86  * this adds up to 512 bytes of extra data meaning the smallest allocation
  87  * we could have is 1K.
  88  * i.e. RXBUFFER_512 --> size-1024 slab
  89  */
  90 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  91
  92 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  93
  94 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  95 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  96
  97 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  98 #define IXGBE_TX_FLAGS_HW_VLAN          (u32)(1 << 1)
  99 #define IXGBE_TX_FLAGS_SW_VLAN          (u32)(1 << 2)
 100 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 3)
 101 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 4)
 102 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 5)
 103 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 6)
 104 #define IXGBE_TX_FLAGS_TXSW             (u32)(1 << 7)
 105 #define IXGBE_TX_FLAGS_MAPPED_AS_PAGE   (u32)(1 << 8)
 106 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 107 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 108 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 109 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 110
 111 #define IXGBE_MAX_RSC_INT_RATE          162760
 112
 113 #define IXGBE_MAX_VF_MC_ENTRIES         30
 114 #define IXGBE_MAX_VF_FUNCTIONS          64
 115 #define IXGBE_MAX_VFTA_ENTRIES          128
 116 #define MAX_EMULATION_MAC_ADDRS         16
 117 #define IXGBE_MAX_PF_MACVLANS           15
 118 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 119
 120 struct vf_data_storage {
 121         unsigned char vf_mac_addresses[ETH_ALEN];
 122         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 123         u16 num_vf_mc_hashes;
 124         u16 default_vf_vlan_id;
 125         u16 vlans_enabled;
 126         bool clear_to_send;
 127         bool pf_set_mac;
 128         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 129         u16 pf_qos;
 130         u16 tx_rate;
 131         struct pci_dev *vfdev;
 132 };
 133
 134 struct vf_macvlans {
 135         struct list_head l;
 136         int vf;
 137         int rar_entry;
 138         bool free;
 139         bool is_macvlan;
 140         u8 vf_macvlan[ETH_ALEN];
 141 };
 142
 143 #define IXGBE_MAX_TXD_PWR       14
 144 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 145
 146 /* Tx Descriptors needed, worst case */
 147 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 148 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
 149
 150 /* wrapper around a pointer to a socket buffer,
 151  * so a DMA handle can be stored along with the buffer */
 152 struct ixgbe_tx_buffer {
 153         union ixgbe_adv_tx_desc *next_to_watch;
 154         unsigned long time_stamp;
 155         dma_addr_t dma;
 156         u32 length;
 157         u32 tx_flags;
 158         struct sk_buff *skb;
 159         u32 bytecount;
 160         u16 gso_segs;
 161 };
 162
 163 struct ixgbe_rx_buffer {
 164         struct sk_buff *skb;
 165         dma_addr_t dma;
 166         struct page *page;
 167         dma_addr_t page_dma;
 168         unsigned int page_offset;
 169 };
 170
 171 struct ixgbe_queue_stats {
 172         u64 packets;
 173         u64 bytes;
 174 };
 175
 176 struct ixgbe_tx_queue_stats {
 177         u64 restart_queue;
 178         u64 tx_busy;
 179         u64 completed;
 180         u64 tx_done_old;
 181 };
 182
 183 struct ixgbe_rx_queue_stats {
 184         u64 rsc_count;
 185         u64 rsc_flush;
 186         u64 non_eop_descs;
 187         u64 alloc_rx_page_failed;
 188         u64 alloc_rx_buff_failed;
 189 };
 190
 191 enum ixbge_ring_state_t {
 192         __IXGBE_TX_FDIR_INIT_DONE,
 193         __IXGBE_TX_DETECT_HANG,
 194         __IXGBE_HANG_CHECK_ARMED,
 195         __IXGBE_RX_PS_ENABLED,
 196         __IXGBE_RX_RSC_ENABLED,
 197 };
 198
 199 #define ring_is_ps_enabled(ring) \
 200         test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 201 #define set_ring_ps_enabled(ring) \
 202         set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 203 #define clear_ring_ps_enabled(ring) \
 204         clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 205 #define check_for_tx_hang(ring) \
 206         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 207 #define set_check_for_tx_hang(ring) \
 208         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 209 #define clear_check_for_tx_hang(ring) \
 210         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 211 #define ring_is_rsc_enabled(ring) \
 212         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 213 #define set_ring_rsc_enabled(ring) \
 214         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 215 #define clear_ring_rsc_enabled(ring) \
 216         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 217 struct ixgbe_ring {
 218         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 219         void *desc;                     /* descriptor ring memory */
 220         struct device *dev;             /* device for DMA mapping */
 221         struct net_device *netdev;      /* netdev ring belongs to */
 222         union {
 223                 struct ixgbe_tx_buffer *tx_buffer_info;
 224                 struct ixgbe_rx_buffer *rx_buffer_info;
 225         };
 226         unsigned long state;
 227         u8 __iomem *tail;
 228
 229         u16 count;                      /* amount of descriptors */
 230         u16 rx_buf_len;
 231
 232         u8 queue_index; /* needed for multiqueue queue management */
 233         u8 reg_idx;                     /* holds the special value that gets
 234                                          * the hardware register offset
 235                                          * associated with this ring, which is
 236                                          * different for DCB and RSS modes
 237                                          */
 238         u8 atr_sample_rate;
 239         u8 atr_count;
 240
 241         u16 next_to_use;
 242         u16 next_to_clean;
 243
 244         u8 dcb_tc;
 245         struct ixgbe_queue_stats stats;
 246         struct u64_stats_sync syncp;
 247         union {
 248                 struct ixgbe_tx_queue_stats tx_stats;
 249                 struct ixgbe_rx_queue_stats rx_stats;
 250         };
 251         int numa_node;
 252         unsigned int size;              /* length in bytes */
 253         dma_addr_t dma;                 /* phys. address of descriptor ring */
 254         struct rcu_head rcu;
 255         struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 256 } ____cacheline_internodealigned_in_smp;
 257
 258 enum ixgbe_ring_f_enum {
 259         RING_F_NONE = 0,
 260         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 261         RING_F_RSS,
 262         RING_F_FDIR,
 263 #ifdef IXGBE_FCOE
 264         RING_F_FCOE,
 265 #endif /* IXGBE_FCOE */
 266
 267         RING_F_ARRAY_SIZE      /* must be last in enum set */
 268 };
 269
 270 #define IXGBE_MAX_RSS_INDICES  16
 271 #define IXGBE_MAX_VMDQ_INDICES 64
 272 #define IXGBE_MAX_FDIR_INDICES 64
 273 #ifdef IXGBE_FCOE
 274 #define IXGBE_MAX_FCOE_INDICES  8
 275 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 276 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 277 #else
 278 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 279 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 280 #endif /* IXGBE_FCOE */
 281 struct ixgbe_ring_feature {
 282         int indices;
 283         int mask;
 284 } ____cacheline_internodealigned_in_smp;
 285
 286 struct ixgbe_ring_container {
 287         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 288         unsigned int total_bytes;       /* total bytes processed this int */
 289         unsigned int total_packets;     /* total packets processed this int */
 290         u16 work_limit;                 /* total work allowed per interrupt */
 291         u8 count;                       /* total number of rings in vector */
 292         u8 itr;                         /* current ITR setting for ring */
 293 };
 294
 295 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 296                               ? 8 : 1)
 297 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 298
 299 /* MAX_MSIX_Q_VECTORS of these are allocated,
 300  * but we only use one per queue-specific vector.
 301  */
 302 struct ixgbe_q_vector {
 303         struct ixgbe_adapter *adapter;
 304         unsigned int v_idx; /* index of q_vector within array, also used for
 305                              * finding the bit in EICR and friends that
 306                              * represents the vector for this ring */
 307 #ifdef CONFIG_IXGBE_DCA
 308         int cpu;            /* CPU for DCA */
 309 #endif
 310         struct napi_struct napi;
 311         struct ixgbe_ring_container rx, tx;
 312         u32 eitr;
 313         cpumask_var_t affinity_mask;
 314         char name[IFNAMSIZ + 9];
 315 };
 316
 317 /* Helper macros to switch between ints/sec and what the register uses.
 318  * And yes, it's the same math going both ways.  The lowest value
 319  * supported by all of the ixgbe hardware is 8.
 320  */
 321 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
 322         ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
 323 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
 324
 325 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 326 {
 327         u16 ntc = ring->next_to_clean;
 328         u16 ntu = ring->next_to_use;
 329
 330         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 331 }
 332
 333 #define IXGBE_RX_DESC_ADV(R, i)     \
 334         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 335 #define IXGBE_TX_DESC_ADV(R, i)     \
 336         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 337 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 338         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 339
 340 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 341 #ifdef IXGBE_FCOE
 342 /* Use 3K as the baby jumbo frame size for FCoE */
 343 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 344 #endif /* IXGBE_FCOE */
 345
 346 #define OTHER_VECTOR 1
 347 #define NON_Q_VECTORS (OTHER_VECTOR)
 348
 349 #define MAX_MSIX_VECTORS_82599 64
 350 #define MAX_MSIX_Q_VECTORS_82599 64
 351 #define MAX_MSIX_VECTORS_82598 18
 352 #define MAX_MSIX_Q_VECTORS_82598 16
 353
 354 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 355 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 356
 357 #define MIN_MSIX_Q_VECTORS 2
 358 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 359
 360 /* board specific private data structure */
 361 struct ixgbe_adapter {
 362         unsigned long state;
 363
 364         /* Some features need tri-state capability,
 365          * thus the additional *_CAPABLE flags.
 366          */
 367         u32 flags;
 368 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 369 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 370 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 371 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 372 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 373 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 374 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 375 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 376 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 377 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 378 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 379 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 380 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 381 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 382 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 383 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 384 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 385 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 386 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 387 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 388 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 23)
 389 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 24)
 390 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 25)
 391 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 26)
 392 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 27)
 393 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 28)
 394 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 29)
 395
 396         u32 flags2;
 397 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 398 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 399 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 400 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 401 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 402 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 403 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 404 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 405
 406         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 407         u16 bd_number;
 408         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 409
 410         /* DCB parameters */
 411         struct ieee_pfc *ixgbe_ieee_pfc;
 412         struct ieee_ets *ixgbe_ieee_ets;
 413         struct ixgbe_dcb_config dcb_cfg;
 414         struct ixgbe_dcb_config temp_dcb_cfg;
 415         u8 dcb_set_bitmap;
 416         u8 dcbx_cap;
 417         enum ixgbe_fc_mode last_lfc_mode;
 418
 419         /* Interrupt Throttle Rate */
 420         u32 rx_itr_setting;
 421         u32 tx_itr_setting;
 422         u16 eitr_low;
 423         u16 eitr_high;
 424
 425         /* Work limits */
 426         u16 tx_work_limit;
 427
 428         /* TX */
 429         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 430         int num_tx_queues;
 431         u32 tx_timeout_count;
 432         bool detect_tx_hung;
 433
 434         u64 restart_queue;
 435         u64 lsc_int;
 436
 437         /* RX */
 438         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
 439         int num_rx_queues;
 440         int num_rx_pools;               /* == num_rx_queues in 82598 */
 441         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 442         u64 hw_csum_rx_error;
 443         u64 hw_rx_no_dma_resources;
 444         u64 non_eop_descs;
 445         int num_msix_vectors;
 446         int max_msix_q_vectors;         /* true count of q_vectors for device */
 447         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 448         struct msix_entry *msix_entries;
 449
 450         u32 alloc_rx_page_failed;
 451         u32 alloc_rx_buff_failed;
 452
 453 /* default to trying for four seconds */
 454 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 455
 456         /* OS defined structs */
 457         struct net_device *netdev;
 458         struct pci_dev *pdev;
 459
 460         u32 test_icr;
 461         struct ixgbe_ring test_tx_ring;
 462         struct ixgbe_ring test_rx_ring;
 463
 464         /* structs defined in ixgbe_hw.h */
 465         struct ixgbe_hw hw;
 466         u16 msg_enable;
 467         struct ixgbe_hw_stats stats;
 468
 469         /* Interrupt Throttle Rate */
 470         u32 rx_eitr_param;
 471         u32 tx_eitr_param;
 472
 473         u64 tx_busy;
 474         unsigned int tx_ring_count;
 475         unsigned int rx_ring_count;
 476
 477         u32 link_speed;
 478         bool link_up;
 479         unsigned long link_check_timeout;
 480
 481         struct work_struct service_task;
 482         struct timer_list service_timer;
 483         u32 fdir_pballoc;
 484         u32 atr_sample_rate;
 485         unsigned long fdir_overflow; /* number of times ATR was backed off */
 486         spinlock_t fdir_perfect_lock;
 487 #ifdef IXGBE_FCOE
 488         struct ixgbe_fcoe fcoe;
 489 #endif /* IXGBE_FCOE */
 490         u64 rsc_total_count;
 491         u64 rsc_total_flush;
 492         u32 wol;
 493         u16 eeprom_version;
 494
 495         int node;
 496         u32 led_reg;
 497         u32 interrupt_event;
 498
 499         /* SR-IOV */
 500         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 501         unsigned int num_vfs;
 502         struct vf_data_storage *vfinfo;
 503         int vf_rate_link_speed;
 504         struct vf_macvlans vf_mvs;
 505         struct vf_macvlans *mv_list;
 506         bool antispoofing_enabled;
 507
 508         struct hlist_head fdir_filter_list;
 509         union ixgbe_atr_input fdir_mask;
 510         int fdir_filter_count;
 511 };
 512
 513 struct ixgbe_fdir_filter {
 514         struct hlist_node fdir_node;
 515         union ixgbe_atr_input filter;
 516         u16 sw_idx;
 517         u16 action;
 518 };
 519
 520 enum ixbge_state_t {
 521         __IXGBE_TESTING,
 522         __IXGBE_RESETTING,
 523         __IXGBE_DOWN,
 524         __IXGBE_SERVICE_SCHED,
 525         __IXGBE_IN_SFP_INIT,
 526 };
 527
 528 struct ixgbe_rsc_cb {
 529         dma_addr_t dma;
 530         u16 skb_cnt;
 531         bool delay_unmap;
 532 };
 533 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
 534
 535 enum ixgbe_boards {
 536         board_82598,
 537         board_82599,
 538         board_X540,
 539 };
 540
 541 extern struct ixgbe_info ixgbe_82598_info;
 542 extern struct ixgbe_info ixgbe_82599_info;
 543 extern struct ixgbe_info ixgbe_X540_info;
 544 #ifdef CONFIG_IXGBE_DCB
 545 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 546 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 547                               struct ixgbe_dcb_config *dst_dcb_cfg,
 548                               int tc_max);
 549 #endif
 550
 551 extern char ixgbe_driver_name[];
 552 extern const char ixgbe_driver_version[];
 553
 554 extern void ixgbe_up(struct ixgbe_adapter *adapter);
 555 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 556 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 557 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 558 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 559 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 560 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 561 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 562 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 563 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 564 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 565 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 566                                    struct ixgbe_ring *);
 567 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 568 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 569 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 570 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 571                                          struct ixgbe_adapter *,
 572                                          struct ixgbe_ring *);
 573 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 574                                              struct ixgbe_tx_buffer *);
 575 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 576 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 577 extern int ethtool_ioctl(struct ifreq *ifr);
 578 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 579 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 580 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 581 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 582                                                  union ixgbe_atr_hash_dword input,
 583                                                  union ixgbe_atr_hash_dword common,
 584                                                  u8 queue);
 585 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 586                                            union ixgbe_atr_input *input_mask);
 587 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 588                                                  union ixgbe_atr_input *input,
 589                                                  u16 soft_id, u8 queue);
 590 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 591                                                  union ixgbe_atr_input *input,
 592                                                  u16 soft_id);
 593 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 594                                                  union ixgbe_atr_input *mask);
 595 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 596 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 597 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 598 extern void ixgbe_do_reset(struct net_device *netdev);
 599 #ifdef IXGBE_FCOE
 600 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 601 extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 602                      u32 tx_flags, u8 *hdr_len);
 603 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 604 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 605                           union ixgbe_adv_rx_desc *rx_desc,
 606                           struct sk_buff *skb,
 607                           u32 staterr);
 608 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 609                               struct scatterlist *sgl, unsigned int sgc);
 610 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 611                                  struct scatterlist *sgl, unsigned int sgc);
 612 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 613 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 614 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 615 #ifdef CONFIG_IXGBE_DCB
 616 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 617 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 618 #endif /* CONFIG_IXGBE_DCB */
 619 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 620 #endif /* IXGBE_FCOE */
 621
 622 #endif /* _IXGBE_H_ */