1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
39 #include "ixgbe_type.h"
40 #include "ixgbe_common.h"
41 #include "ixgbe_dcb.h"
42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
44 #include "ixgbe_fcoe.h"
45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
46 #ifdef CONFIG_IXGBE_DCA
47 #include <linux/dca.h>
50 /* common prefix used by pr_<> macros */
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 /* TX/RX descriptor defines */
55 #define IXGBE_DEFAULT_TXD 512
56 #define IXGBE_DEFAULT_TX_WORK 256
57 #define IXGBE_MAX_TXD 4096
58 #define IXGBE_MIN_TXD 64
60 #define IXGBE_DEFAULT_RXD 512
61 #define IXGBE_MAX_RXD 4096
62 #define IXGBE_MIN_RXD 64
65 #define IXGBE_MIN_FCRTL 0x40
66 #define IXGBE_MAX_FCRTL 0x7FF80
67 #define IXGBE_MIN_FCRTH 0x600
68 #define IXGBE_MAX_FCRTH 0x7FFF0
69 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70 #define IXGBE_MIN_FCPAUSE 0
71 #define IXGBE_MAX_FCPAUSE 0xFFFF
73 /* Supported Rx Buffer Sizes */
74 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
75 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
78 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
79 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
80 * this adds up to 512 bytes of extra data meaning the smallest allocation
81 * we could have is 1K.
82 * i.e. RXBUFFER_512 --> size-1024 slab
84 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
86 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
88 /* How many Rx Buffers do we bundle into one write to the hardware ? */
89 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
91 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
92 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
93 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
94 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
95 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
96 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
97 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
98 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
99 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
101 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
102 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
104 #define IXGBE_MAX_VF_MC_ENTRIES 30
105 #define IXGBE_MAX_VF_FUNCTIONS 64
106 #define IXGBE_MAX_VFTA_ENTRIES 128
107 #define MAX_EMULATION_MAC_ADDRS 16
108 #define IXGBE_MAX_PF_MACVLANS 15
109 #define VMDQ_P(p) ((p) + adapter->num_vfs)
110 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
111 #define IXGBE_X540_VF_DEVICE_ID 0x1515
113 struct vf_data_storage
{
114 unsigned char vf_mac_addresses
[ETH_ALEN
];
115 u16 vf_mc_hashes
[IXGBE_MAX_VF_MC_ENTRIES
];
116 u16 num_vf_mc_hashes
;
117 u16 default_vf_vlan_id
;
121 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
126 struct pci_dev
*vfdev
;
135 u8 vf_macvlan
[ETH_ALEN
];
138 #define IXGBE_MAX_TXD_PWR 14
139 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
141 /* Tx Descriptors needed, worst case */
142 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
143 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
145 /* wrapper around a pointer to a socket buffer,
146 * so a DMA handle can be stored along with the buffer */
147 struct ixgbe_tx_buffer
{
148 union ixgbe_adv_tx_desc
*next_to_watch
;
149 unsigned long time_stamp
;
151 unsigned int bytecount
;
152 unsigned short gso_segs
;
154 DEFINE_DMA_UNMAP_ADDR(dma
);
155 DEFINE_DMA_UNMAP_LEN(len
);
159 struct ixgbe_rx_buffer
{
163 unsigned int page_offset
;
166 struct ixgbe_queue_stats
{
171 struct ixgbe_tx_queue_stats
{
177 struct ixgbe_rx_queue_stats
{
181 u64 alloc_rx_page_failed
;
182 u64 alloc_rx_buff_failed
;
186 enum ixgbe_ring_state_t
{
187 __IXGBE_TX_FDIR_INIT_DONE
,
188 __IXGBE_TX_DETECT_HANG
,
189 __IXGBE_HANG_CHECK_ARMED
,
190 __IXGBE_RX_RSC_ENABLED
,
191 __IXGBE_RX_CSUM_UDP_ZERO_ERR
,
192 __IXGBE_RX_FCOE_BUFSZ
,
195 #define check_for_tx_hang(ring) \
196 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
197 #define set_check_for_tx_hang(ring) \
198 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
199 #define clear_check_for_tx_hang(ring) \
200 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
201 #define ring_is_rsc_enabled(ring) \
202 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
203 #define set_ring_rsc_enabled(ring) \
204 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
205 #define clear_ring_rsc_enabled(ring) \
206 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
208 struct ixgbe_ring
*next
; /* pointer to next ring in q_vector */
209 struct ixgbe_q_vector
*q_vector
; /* backpointer to host q_vector */
210 struct net_device
*netdev
; /* netdev ring belongs to */
211 struct device
*dev
; /* device for DMA mapping */
212 void *desc
; /* descriptor ring memory */
214 struct ixgbe_tx_buffer
*tx_buffer_info
;
215 struct ixgbe_rx_buffer
*rx_buffer_info
;
219 dma_addr_t dma
; /* phys. address of descriptor ring */
220 unsigned int size
; /* length in bytes */
222 u16 count
; /* amount of descriptors */
224 u8 queue_index
; /* needed for multiqueue queue management */
225 u8 reg_idx
; /* holds the special value that gets
226 * the hardware register offset
227 * associated with this ring, which is
228 * different for DCB and RSS modes
242 struct ixgbe_queue_stats stats
;
243 struct u64_stats_sync syncp
;
245 struct ixgbe_tx_queue_stats tx_stats
;
246 struct ixgbe_rx_queue_stats rx_stats
;
248 } ____cacheline_internodealigned_in_smp
;
250 enum ixgbe_ring_f_enum
{
252 RING_F_VMDQ
, /* SR-IOV uses the same ring feature */
257 #endif /* IXGBE_FCOE */
259 RING_F_ARRAY_SIZE
/* must be last in enum set */
262 #define IXGBE_MAX_RSS_INDICES 16
263 #define IXGBE_MAX_VMDQ_INDICES 64
264 #define IXGBE_MAX_FDIR_INDICES 64
266 #define IXGBE_MAX_FCOE_INDICES 8
267 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
268 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
270 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
271 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
272 #endif /* IXGBE_FCOE */
273 struct ixgbe_ring_feature
{
276 } ____cacheline_internodealigned_in_smp
;
279 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
280 * this is twice the size of a half page we need to double the page order
281 * for FCoE enabled Rx queues.
283 #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
284 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring
*ring
)
286 return test_bit(__IXGBE_RX_FCOE_BUFSZ
, &ring
->state
) ? 1 : 0;
289 #define ixgbe_rx_pg_order(_ring) 0
291 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
292 #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
294 struct ixgbe_ring_container
{
295 struct ixgbe_ring
*ring
; /* pointer to linked list of rings */
296 unsigned int total_bytes
; /* total bytes processed this int */
297 unsigned int total_packets
; /* total packets processed this int */
298 u16 work_limit
; /* total work allowed per interrupt */
299 u8 count
; /* total number of rings in vector */
300 u8 itr
; /* current ITR setting for ring */
303 /* iterator for handling rings in ring container */
304 #define ixgbe_for_each_ring(pos, head) \
305 for (pos = (head).ring; pos != NULL; pos = pos->next)
307 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
309 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
311 /* MAX_MSIX_Q_VECTORS of these are allocated,
312 * but we only use one per queue-specific vector.
314 struct ixgbe_q_vector
{
315 struct ixgbe_adapter
*adapter
;
316 #ifdef CONFIG_IXGBE_DCA
317 int cpu
; /* CPU for DCA */
319 u16 v_idx
; /* index of q_vector within array, also used for
320 * finding the bit in EICR and friends that
321 * represents the vector for this ring */
322 u16 itr
; /* Interrupt throttle rate written to EITR */
323 struct ixgbe_ring_container rx
, tx
;
325 struct napi_struct napi
;
326 cpumask_t affinity_mask
;
328 struct rcu_head rcu
; /* to avoid race with update stats on free */
329 char name
[IFNAMSIZ
+ 9];
331 /* for dynamic allocation of rings associated with this q_vector */
332 struct ixgbe_ring ring
[0] ____cacheline_internodealigned_in_smp
;
336 * microsecond values for various ITR rates shifted by 2 to fit itr register
337 * with the first 3 bits reserved 0
339 #define IXGBE_MIN_RSC_ITR 24
340 #define IXGBE_100K_ITR 40
341 #define IXGBE_20K_ITR 200
342 #define IXGBE_10K_ITR 400
343 #define IXGBE_8K_ITR 500
345 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
346 static inline __le32
ixgbe_test_staterr(union ixgbe_adv_rx_desc
*rx_desc
,
347 const u32 stat_err_bits
)
349 return rx_desc
->wb
.upper
.status_error
& cpu_to_le32(stat_err_bits
);
352 static inline u16
ixgbe_desc_unused(struct ixgbe_ring
*ring
)
354 u16 ntc
= ring
->next_to_clean
;
355 u16 ntu
= ring
->next_to_use
;
357 return ((ntc
> ntu
) ? 0 : ring
->count
) + ntc
- ntu
- 1;
360 #define IXGBE_RX_DESC(R, i) \
361 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
362 #define IXGBE_TX_DESC(R, i) \
363 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
364 #define IXGBE_TX_CTXTDESC(R, i) \
365 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
367 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
369 /* Use 3K as the baby jumbo frame size for FCoE */
370 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
371 #endif /* IXGBE_FCOE */
373 #define OTHER_VECTOR 1
374 #define NON_Q_VECTORS (OTHER_VECTOR)
376 #define MAX_MSIX_VECTORS_82599 64
377 #define MAX_MSIX_Q_VECTORS_82599 64
378 #define MAX_MSIX_VECTORS_82598 18
379 #define MAX_MSIX_Q_VECTORS_82598 16
381 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
382 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
384 #define MIN_MSIX_Q_VECTORS 1
385 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
387 /* default to trying for four seconds */
388 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
390 /* board specific private data structure */
391 struct ixgbe_adapter
{
392 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
393 /* OS defined structs */
394 struct net_device
*netdev
;
395 struct pci_dev
*pdev
;
399 /* Some features need tri-state capability,
400 * thus the additional *_CAPABLE flags.
403 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
404 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
405 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
406 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
407 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
408 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
409 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
410 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
411 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
412 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
413 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
414 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
415 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
416 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
417 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
418 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
419 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
420 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
421 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
422 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
423 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
424 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
425 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
426 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
427 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
428 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
431 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
432 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
433 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
434 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
435 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
436 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
437 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
438 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
439 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
440 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
442 /* Tx fast path data */
447 /* Rx fast path data */
452 struct ixgbe_ring
*tx_ring
[MAX_TX_QUEUES
] ____cacheline_aligned_in_smp
;
456 u32 tx_timeout_count
;
459 struct ixgbe_ring
*rx_ring
[MAX_RX_QUEUES
];
460 int num_rx_pools
; /* == num_rx_queues in 82598 */
461 int num_rx_queues_per_pool
; /* 1 if 82598, can be many if 82599 */
462 u64 hw_csum_rx_error
;
463 u64 hw_rx_no_dma_resources
;
467 u32 alloc_rx_page_failed
;
468 u32 alloc_rx_buff_failed
;
470 struct ixgbe_q_vector
*q_vector
[MAX_MSIX_Q_VECTORS
];
473 struct ieee_pfc
*ixgbe_ieee_pfc
;
474 struct ieee_ets
*ixgbe_ieee_ets
;
475 struct ixgbe_dcb_config dcb_cfg
;
476 struct ixgbe_dcb_config temp_dcb_cfg
;
479 enum ixgbe_fc_mode last_lfc_mode
;
481 int num_msix_vectors
;
482 int max_msix_q_vectors
; /* true count of q_vectors for device */
483 struct ixgbe_ring_feature ring_feature
[RING_F_ARRAY_SIZE
];
484 struct msix_entry
*msix_entries
;
487 struct ixgbe_ring test_tx_ring
;
488 struct ixgbe_ring test_rx_ring
;
490 /* structs defined in ixgbe_hw.h */
493 struct ixgbe_hw_stats stats
;
496 unsigned int tx_ring_count
;
497 unsigned int rx_ring_count
;
501 unsigned long link_check_timeout
;
503 struct timer_list service_timer
;
504 struct work_struct service_task
;
506 struct hlist_head fdir_filter_list
;
507 unsigned long fdir_overflow
; /* number of times ATR was backed off */
508 union ixgbe_atr_input fdir_mask
;
509 int fdir_filter_count
;
512 spinlock_t fdir_perfect_lock
;
515 struct ixgbe_fcoe fcoe
;
516 #endif /* IXGBE_FCOE */
529 DECLARE_BITMAP(active_vfs
, IXGBE_MAX_VF_FUNCTIONS
);
530 unsigned int num_vfs
;
531 struct vf_data_storage
*vfinfo
;
532 int vf_rate_link_speed
;
533 struct vf_macvlans vf_mvs
;
534 struct vf_macvlans
*mv_list
;
536 u32 timer_event_accumulator
;
540 struct ixgbe_fdir_filter
{
541 struct hlist_node fdir_node
;
542 union ixgbe_atr_input filter
;
551 __IXGBE_SERVICE_SCHED
,
556 union { /* Union defining head/tail partner */
557 struct sk_buff
*head
;
558 struct sk_buff
*tail
;
564 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
572 extern struct ixgbe_info ixgbe_82598_info
;
573 extern struct ixgbe_info ixgbe_82599_info
;
574 extern struct ixgbe_info ixgbe_X540_info
;
575 #ifdef CONFIG_IXGBE_DCB
576 extern const struct dcbnl_rtnl_ops dcbnl_ops
;
577 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config
*src_dcb_cfg
,
578 struct ixgbe_dcb_config
*dst_dcb_cfg
,
582 extern char ixgbe_driver_name
[];
583 extern const char ixgbe_driver_version
[];
585 extern char ixgbe_default_device_descr
[];
586 #endif /* IXGBE_FCOE */
588 extern void ixgbe_up(struct ixgbe_adapter
*adapter
);
589 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
590 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
591 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
592 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
593 extern int ixgbe_setup_rx_resources(struct ixgbe_ring
*);
594 extern int ixgbe_setup_tx_resources(struct ixgbe_ring
*);
595 extern void ixgbe_free_rx_resources(struct ixgbe_ring
*);
596 extern void ixgbe_free_tx_resources(struct ixgbe_ring
*);
597 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
598 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
599 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
600 struct ixgbe_ring
*);
601 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
602 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
603 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
);
604 extern netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*,
605 struct ixgbe_adapter
*,
606 struct ixgbe_ring
*);
607 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*,
608 struct ixgbe_tx_buffer
*);
609 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*, u16
);
610 extern void ixgbe_write_eitr(struct ixgbe_q_vector
*);
611 extern int ixgbe_poll(struct napi_struct
*napi
, int budget
);
612 extern int ethtool_ioctl(struct ifreq
*ifr
);
613 extern s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
);
614 extern s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
615 extern s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
616 extern s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
617 union ixgbe_atr_hash_dword input
,
618 union ixgbe_atr_hash_dword common
,
620 extern s32
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw
*hw
,
621 union ixgbe_atr_input
*input_mask
);
622 extern s32
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw
*hw
,
623 union ixgbe_atr_input
*input
,
624 u16 soft_id
, u8 queue
);
625 extern s32
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw
*hw
,
626 union ixgbe_atr_input
*input
,
628 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input
*input
,
629 union ixgbe_atr_input
*mask
);
630 extern void ixgbe_set_rx_mode(struct net_device
*netdev
);
631 #ifdef CONFIG_IXGBE_DCB
632 extern int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
);
634 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring
*, u32
, u32
, u32
, u32
);
635 extern void ixgbe_do_reset(struct net_device
*netdev
);
637 extern void ixgbe_configure_fcoe(struct ixgbe_adapter
*adapter
);
638 extern int ixgbe_fso(struct ixgbe_ring
*tx_ring
,
639 struct ixgbe_tx_buffer
*first
,
641 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter
*adapter
);
642 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter
*adapter
,
643 union ixgbe_adv_rx_desc
*rx_desc
,
644 struct sk_buff
*skb
);
645 extern int ixgbe_fcoe_ddp_get(struct net_device
*netdev
, u16 xid
,
646 struct scatterlist
*sgl
, unsigned int sgc
);
647 extern int ixgbe_fcoe_ddp_target(struct net_device
*netdev
, u16 xid
,
648 struct scatterlist
*sgl
, unsigned int sgc
);
649 extern int ixgbe_fcoe_ddp_put(struct net_device
*netdev
, u16 xid
);
650 extern int ixgbe_fcoe_enable(struct net_device
*netdev
);
651 extern int ixgbe_fcoe_disable(struct net_device
*netdev
);
652 #ifdef CONFIG_IXGBE_DCB
653 extern u8
ixgbe_fcoe_getapp(struct ixgbe_adapter
*adapter
);
654 extern u8
ixgbe_fcoe_setapp(struct ixgbe_adapter
*adapter
, u8 up
);
655 #endif /* CONFIG_IXGBE_DCB */
656 extern int ixgbe_fcoe_get_wwn(struct net_device
*netdev
, u64
*wwn
, int type
);
657 extern int ixgbe_fcoe_get_hbainfo(struct net_device
*netdev
,
658 struct netdev_fcoe_hbainfo
*info
);
659 #endif /* IXGBE_FCOE */
661 static inline struct netdev_queue
*txring_txq(const struct ixgbe_ring
*ring
)
663 return netdev_get_tx_queue(ring
->netdev
, ring
->queue_index
);
666 #endif /* _IXGBE_H_ */