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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define MAJ 3
67 #define MIN 9
68 #define BUILD 15
69 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
70 __stringify(BUILD) "-k"
71 const char ixgbe_driver_version[] = DRV_VERSION;
72 static const char ixgbe_copyright[] =
73 "Copyright (c) 1999-2012 Intel Corporation.";
74
75 static const struct ixgbe_info *ixgbe_info_tbl[] = {
76 [board_82598] = &ixgbe_82598_info,
77 [board_82599] = &ixgbe_82599_info,
78 [board_X540] = &ixgbe_X540_info,
79 };
80
81 /* ixgbe_pci_tbl - PCI Device ID Table
82 *
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
85 *
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
88 */
89 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
119 /* required last entry */
120 {0, }
121 };
122 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
123
124 #ifdef CONFIG_IXGBE_DCA
125 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
126 void *p);
127 static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
129 .next = NULL,
130 .priority = 0
131 };
132 #endif
133
134 #ifdef CONFIG_PCI_IOV
135 static unsigned int max_vfs;
136 module_param(max_vfs, uint, 0);
137 MODULE_PARM_DESC(max_vfs,
138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
139 #endif /* CONFIG_PCI_IOV */
140
141 static unsigned int allow_unsupported_sfp;
142 module_param(allow_unsupported_sfp, uint, 0);
143 MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
145
146 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147 static int debug = -1;
148 module_param(debug, int, 0);
149 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
150
151 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153 MODULE_LICENSE("GPL");
154 MODULE_VERSION(DRV_VERSION);
155
156 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
157 {
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
161 }
162
163 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
164 {
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
166
167 /* flush memory to make sure state is correct before next watchdog */
168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
170 }
171
172 struct ixgbe_reg_info {
173 u32 ofs;
174 char *name;
175 };
176
177 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
178
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
183
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
186
187 /* RX Registers */
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
196
197 /* TX Registers */
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
204
205 /* List Terminator */
206 {}
207 };
208
209
210 /*
211 * ixgbe_regdump - register printout routine
212 */
213 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
214 {
215 int i = 0, j = 0;
216 char rname[16];
217 u32 regs[64];
218
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
223 break;
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
227 break;
228 case IXGBE_RDLEN(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
231 break;
232 case IXGBE_RDH(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
235 break;
236 case IXGBE_RDT(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
239 break;
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
243 break;
244 case IXGBE_RDBAL(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
247 break;
248 case IXGBE_RDBAH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
251 break;
252 case IXGBE_TDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
255 break;
256 case IXGBE_TDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
259 break;
260 case IXGBE_TDLEN(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
263 break;
264 case IXGBE_TDH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
267 break;
268 case IXGBE_TDT(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
271 break;
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
275 break;
276 default:
277 pr_info("%-15s %08x\n", reginfo->name,
278 IXGBE_READ_REG(hw, reginfo->ofs));
279 return;
280 }
281
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
284 pr_err("%-15s", rname);
285 for (j = 0; j < 8; j++)
286 pr_cont(" %08x", regs[i*8+j]);
287 pr_cont("\n");
288 }
289
290 }
291
292 /*
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
294 */
295 static void ixgbe_dump(struct ixgbe_adapter *adapter)
296 {
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
300 int n = 0;
301 struct ixgbe_ring *tx_ring;
302 struct ixgbe_tx_buffer *tx_buffer;
303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
308 u32 staterr;
309 int i = 0;
310
311 if (!netif_msg_hw(adapter))
312 return;
313
314 /* Print netdevice Info */
315 if (netdev) {
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
317 pr_info("Device Name state "
318 "trans_start last_rx\n");
319 pr_info("%-15s %016lX %016lX %016lX\n",
320 netdev->name,
321 netdev->state,
322 netdev->trans_start,
323 netdev->last_rx);
324 }
325
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
328 pr_info(" Register Name Value\n");
329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
332 }
333
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
336 goto exit;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
339 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
340 for (n = 0; n < adapter->num_tx_queues; n++) {
341 tx_ring = adapter->tx_ring[n];
342 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
343 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
344 n, tx_ring->next_to_use, tx_ring->next_to_clean,
345 (u64)dma_unmap_addr(tx_buffer, dma),
346 dma_unmap_len(tx_buffer, len),
347 tx_buffer->next_to_watch,
348 (u64)tx_buffer->time_stamp);
349 }
350
351 /* Print TX Rings */
352 if (!netif_msg_tx_done(adapter))
353 goto rx_ring_summary;
354
355 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
356
357 /* Transmit Descriptor Formats
358 *
359 * 82598 Advanced Transmit Descriptor
360 * +--------------------------------------------------------------+
361 * 0 | Buffer Address [63:0] |
362 * +--------------------------------------------------------------+
363 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
364 * +--------------------------------------------------------------+
365 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
366 *
367 * 82598 Advanced Transmit Descriptor (Write-Back Format)
368 * +--------------------------------------------------------------+
369 * 0 | RSV [63:0] |
370 * +--------------------------------------------------------------+
371 * 8 | RSV | STA | NXTSEQ |
372 * +--------------------------------------------------------------+
373 * 63 36 35 32 31 0
374 *
375 * 82599+ Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
382 *
383 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
384 * +--------------------------------------------------------------+
385 * 0 | RSV [63:0] |
386 * +--------------------------------------------------------------+
387 * 8 | RSV | STA | RSV |
388 * +--------------------------------------------------------------+
389 * 63 36 35 32 31 0
390 */
391
392 for (n = 0; n < adapter->num_tx_queues; n++) {
393 tx_ring = adapter->tx_ring[n];
394 pr_info("------------------------------------\n");
395 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
396 pr_info("------------------------------------\n");
397 pr_info("T [desc] [address 63:0 ] "
398 "[PlPOIdStDDt Ln] [bi->dma ] "
399 "leng ntw timestamp bi->skb\n");
400
401 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
402 tx_desc = IXGBE_TX_DESC(tx_ring, i);
403 tx_buffer = &tx_ring->tx_buffer_info[i];
404 u0 = (struct my_u0 *)tx_desc;
405 pr_info("T [0x%03X] %016llX %016llX %016llX"
406 " %04X %p %016llX %p", i,
407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
409 (u64)dma_unmap_addr(tx_buffer, dma),
410 dma_unmap_len(tx_buffer, len),
411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
416 pr_cont(" NTC/U\n");
417 else if (i == tx_ring->next_to_use)
418 pr_cont(" NTU\n");
419 else if (i == tx_ring->next_to_clean)
420 pr_cont(" NTC\n");
421 else
422 pr_cont("\n");
423
424 if (netif_msg_pktdata(adapter) &&
425 tx_buffer->skb)
426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
428 tx_buffer->skb->data,
429 dma_unmap_len(tx_buffer, len),
430 true);
431 }
432 }
433
434 /* Print RX Rings Summary */
435 rx_ring_summary:
436 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
437 pr_info("Queue [NTU] [NTC]\n");
438 for (n = 0; n < adapter->num_rx_queues; n++) {
439 rx_ring = adapter->rx_ring[n];
440 pr_info("%5d %5X %5X\n",
441 n, rx_ring->next_to_use, rx_ring->next_to_clean);
442 }
443
444 /* Print RX Rings */
445 if (!netif_msg_rx_status(adapter))
446 goto exit;
447
448 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
449
450 /* Receive Descriptor Formats
451 *
452 * 82598 Advanced Receive Descriptor (Read) Format
453 * 63 1 0
454 * +-----------------------------------------------------+
455 * 0 | Packet Buffer Address [63:1] |A0/NSE|
456 * +----------------------------------------------+------+
457 * 8 | Header Buffer Address [63:1] | DD |
458 * +-----------------------------------------------------+
459 *
460 *
461 * 82598 Advanced Receive Descriptor (Write-Back) Format
462 *
463 * 63 48 47 32 31 30 21 20 16 15 4 3 0
464 * +------------------------------------------------------+
465 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
466 * | Packet | IP | | | | Type | Type |
467 * | Checksum | Ident | | | | | |
468 * +------------------------------------------------------+
469 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
470 * +------------------------------------------------------+
471 * 63 48 47 32 31 20 19 0
472 *
473 * 82599+ Advanced Receive Descriptor (Read) Format
474 * 63 1 0
475 * +-----------------------------------------------------+
476 * 0 | Packet Buffer Address [63:1] |A0/NSE|
477 * +----------------------------------------------+------+
478 * 8 | Header Buffer Address [63:1] | DD |
479 * +-----------------------------------------------------+
480 *
481 *
482 * 82599+ Advanced Receive Descriptor (Write-Back) Format
483 *
484 * 63 48 47 32 31 30 21 20 17 16 4 3 0
485 * +------------------------------------------------------+
486 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
487 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
488 * |/ Flow Dir Flt ID | | | | | |
489 * +------------------------------------------------------+
490 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
491 * +------------------------------------------------------+
492 * 63 48 47 32 31 20 19 0
493 */
494
495 for (n = 0; n < adapter->num_rx_queues; n++) {
496 rx_ring = adapter->rx_ring[n];
497 pr_info("------------------------------------\n");
498 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
499 pr_info("------------------------------------\n");
500 pr_info("R [desc] [ PktBuf A0] "
501 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
502 "<-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
504 "[vl er S cks ln] ---------------- [bi->skb] "
505 "<-- Adv Rx Write-Back format\n");
506
507 for (i = 0; i < rx_ring->count; i++) {
508 rx_buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IXGBE_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 if (staterr & IXGBE_RXD_STAT_DD) {
513 /* Descriptor Done */
514 pr_info("RWB[0x%03X] %016llX "
515 "%016llX ---------------- %p", i,
516 le64_to_cpu(u0->a),
517 le64_to_cpu(u0->b),
518 rx_buffer_info->skb);
519 } else {
520 pr_info("R [0x%03X] %016llX "
521 "%016llX %016llX %p", i,
522 le64_to_cpu(u0->a),
523 le64_to_cpu(u0->b),
524 (u64)rx_buffer_info->dma,
525 rx_buffer_info->skb);
526
527 if (netif_msg_pktdata(adapter) &&
528 rx_buffer_info->dma) {
529 print_hex_dump(KERN_INFO, "",
530 DUMP_PREFIX_ADDRESS, 16, 1,
531 page_address(rx_buffer_info->page) +
532 rx_buffer_info->page_offset,
533 ixgbe_rx_bufsz(rx_ring), true);
534 }
535 }
536
537 if (i == rx_ring->next_to_use)
538 pr_cont(" NTU\n");
539 else if (i == rx_ring->next_to_clean)
540 pr_cont(" NTC\n");
541 else
542 pr_cont("\n");
543
544 }
545 }
546
547 exit:
548 return;
549 }
550
551 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
552 {
553 u32 ctrl_ext;
554
555 /* Let firmware take over control of h/w */
556 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
558 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
559 }
560
561 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
562 {
563 u32 ctrl_ext;
564
565 /* Let firmware know the driver has taken over */
566 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
568 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
569 }
570
571 /**
572 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
573 * @adapter: pointer to adapter struct
574 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
575 * @queue: queue to map the corresponding interrupt to
576 * @msix_vector: the vector to map to the corresponding queue
577 *
578 */
579 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
580 u8 queue, u8 msix_vector)
581 {
582 u32 ivar, index;
583 struct ixgbe_hw *hw = &adapter->hw;
584 switch (hw->mac.type) {
585 case ixgbe_mac_82598EB:
586 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
587 if (direction == -1)
588 direction = 0;
589 index = (((direction * 64) + queue) >> 2) & 0x1F;
590 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
591 ivar &= ~(0xFF << (8 * (queue & 0x3)));
592 ivar |= (msix_vector << (8 * (queue & 0x3)));
593 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
594 break;
595 case ixgbe_mac_82599EB:
596 case ixgbe_mac_X540:
597 if (direction == -1) {
598 /* other causes */
599 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
600 index = ((queue & 1) * 8);
601 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
602 ivar &= ~(0xFF << index);
603 ivar |= (msix_vector << index);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
605 break;
606 } else {
607 /* tx or rx causes */
608 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
609 index = ((16 * (queue & 1)) + (8 * direction));
610 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
611 ivar &= ~(0xFF << index);
612 ivar |= (msix_vector << index);
613 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
614 break;
615 }
616 default:
617 break;
618 }
619 }
620
621 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
622 u64 qmask)
623 {
624 u32 mask;
625
626 switch (adapter->hw.mac.type) {
627 case ixgbe_mac_82598EB:
628 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
630 break;
631 case ixgbe_mac_82599EB:
632 case ixgbe_mac_X540:
633 mask = (qmask & 0xFFFFFFFF);
634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
635 mask = (qmask >> 32);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
637 break;
638 default:
639 break;
640 }
641 }
642
643 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
644 struct ixgbe_tx_buffer *tx_buffer)
645 {
646 if (tx_buffer->skb) {
647 dev_kfree_skb_any(tx_buffer->skb);
648 if (dma_unmap_len(tx_buffer, len))
649 dma_unmap_single(ring->dev,
650 dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 DMA_TO_DEVICE);
653 } else if (dma_unmap_len(tx_buffer, len)) {
654 dma_unmap_page(ring->dev,
655 dma_unmap_addr(tx_buffer, dma),
656 dma_unmap_len(tx_buffer, len),
657 DMA_TO_DEVICE);
658 }
659 tx_buffer->next_to_watch = NULL;
660 tx_buffer->skb = NULL;
661 dma_unmap_len_set(tx_buffer, len, 0);
662 /* tx_buffer must be completely set up in the transmit path */
663 }
664
665 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
666 {
667 struct ixgbe_hw *hw = &adapter->hw;
668 struct ixgbe_hw_stats *hwstats = &adapter->stats;
669 int i;
670 u32 data;
671
672 if ((hw->fc.current_mode != ixgbe_fc_full) &&
673 (hw->fc.current_mode != ixgbe_fc_rx_pause))
674 return;
675
676 switch (hw->mac.type) {
677 case ixgbe_mac_82598EB:
678 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
679 break;
680 default:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
682 }
683 hwstats->lxoffrxc += data;
684
685 /* refill credits (no tx hang) if we received xoff */
686 if (!data)
687 return;
688
689 for (i = 0; i < adapter->num_tx_queues; i++)
690 clear_bit(__IXGBE_HANG_CHECK_ARMED,
691 &adapter->tx_ring[i]->state);
692 }
693
694 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
695 {
696 struct ixgbe_hw *hw = &adapter->hw;
697 struct ixgbe_hw_stats *hwstats = &adapter->stats;
698 u32 xoff[8] = {0};
699 int i;
700 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
701
702 if (adapter->ixgbe_ieee_pfc)
703 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
704
705 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
706 ixgbe_update_xoff_rx_lfc(adapter);
707 return;
708 }
709
710 /* update stats for each tc, only valid with PFC enabled */
711 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
715 break;
716 default:
717 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
718 }
719 hwstats->pxoffrxc[i] += xoff[i];
720 }
721
722 /* disarm tx queues that have received xoff frames */
723 for (i = 0; i < adapter->num_tx_queues; i++) {
724 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
725 u8 tc = tx_ring->dcb_tc;
726
727 if (xoff[tc])
728 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
729 }
730 }
731
732 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
733 {
734 return ring->stats.packets;
735 }
736
737 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
738 {
739 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
740 struct ixgbe_hw *hw = &adapter->hw;
741
742 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
743 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
744
745 if (head != tail)
746 return (head < tail) ?
747 tail - head : (tail + ring->count - head);
748
749 return 0;
750 }
751
752 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
753 {
754 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
755 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
756 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
757 bool ret = false;
758
759 clear_check_for_tx_hang(tx_ring);
760
761 /*
762 * Check for a hung queue, but be thorough. This verifies
763 * that a transmit has been completed since the previous
764 * check AND there is at least one packet pending. The
765 * ARMED bit is set to indicate a potential hang. The
766 * bit is cleared if a pause frame is received to remove
767 * false hang detection due to PFC or 802.3x frames. By
768 * requiring this to fail twice we avoid races with
769 * pfc clearing the ARMED bit and conditions where we
770 * run the check_tx_hang logic with a transmit completion
771 * pending but without time to complete it yet.
772 */
773 if ((tx_done_old == tx_done) && tx_pending) {
774 /* make sure it is true for two checks in a row */
775 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
776 &tx_ring->state);
777 } else {
778 /* update completed stats and continue */
779 tx_ring->tx_stats.tx_done_old = tx_done;
780 /* reset the countdown */
781 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
782 }
783
784 return ret;
785 }
786
787 /**
788 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
789 * @adapter: driver private struct
790 **/
791 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
792 {
793
794 /* Do the reset outside of interrupt context */
795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
796 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
797 ixgbe_service_event_schedule(adapter);
798 }
799 }
800
801 /**
802 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
803 * @q_vector: structure containing interrupt and ring information
804 * @tx_ring: tx ring to clean
805 **/
806 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
807 struct ixgbe_ring *tx_ring)
808 {
809 struct ixgbe_adapter *adapter = q_vector->adapter;
810 struct ixgbe_tx_buffer *tx_buffer;
811 union ixgbe_adv_tx_desc *tx_desc;
812 unsigned int total_bytes = 0, total_packets = 0;
813 unsigned int budget = q_vector->tx.work_limit;
814 unsigned int i = tx_ring->next_to_clean;
815
816 if (test_bit(__IXGBE_DOWN, &adapter->state))
817 return true;
818
819 tx_buffer = &tx_ring->tx_buffer_info[i];
820 tx_desc = IXGBE_TX_DESC(tx_ring, i);
821 i -= tx_ring->count;
822
823 do {
824 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
825
826 /* if next_to_watch is not set then there is no work pending */
827 if (!eop_desc)
828 break;
829
830 /* prevent any other reads prior to eop_desc */
831 rmb();
832
833 /* if DD is not set pending work has not been completed */
834 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
835 break;
836
837 /* clear next_to_watch to prevent false hangs */
838 tx_buffer->next_to_watch = NULL;
839
840 /* update the statistics for this packet */
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
843
844 #ifdef CONFIG_IXGBE_PTP
845 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
846 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
847 #endif
848
849 /* free the skb */
850 dev_kfree_skb_any(tx_buffer->skb);
851
852 /* unmap skb header data */
853 dma_unmap_single(tx_ring->dev,
854 dma_unmap_addr(tx_buffer, dma),
855 dma_unmap_len(tx_buffer, len),
856 DMA_TO_DEVICE);
857
858 /* clear tx_buffer data */
859 tx_buffer->skb = NULL;
860 dma_unmap_len_set(tx_buffer, len, 0);
861
862 /* unmap remaining buffers */
863 while (tx_desc != eop_desc) {
864 tx_buffer++;
865 tx_desc++;
866 i++;
867 if (unlikely(!i)) {
868 i -= tx_ring->count;
869 tx_buffer = tx_ring->tx_buffer_info;
870 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
871 }
872
873 /* unmap any remaining paged data */
874 if (dma_unmap_len(tx_buffer, len)) {
875 dma_unmap_page(tx_ring->dev,
876 dma_unmap_addr(tx_buffer, dma),
877 dma_unmap_len(tx_buffer, len),
878 DMA_TO_DEVICE);
879 dma_unmap_len_set(tx_buffer, len, 0);
880 }
881 }
882
883 /* move us one more past the eop_desc for start of next pkt */
884 tx_buffer++;
885 tx_desc++;
886 i++;
887 if (unlikely(!i)) {
888 i -= tx_ring->count;
889 tx_buffer = tx_ring->tx_buffer_info;
890 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
891 }
892
893 /* issue prefetch for next Tx descriptor */
894 prefetch(tx_desc);
895
896 /* update budget accounting */
897 budget--;
898 } while (likely(budget));
899
900 i += tx_ring->count;
901 tx_ring->next_to_clean = i;
902 u64_stats_update_begin(&tx_ring->syncp);
903 tx_ring->stats.bytes += total_bytes;
904 tx_ring->stats.packets += total_packets;
905 u64_stats_update_end(&tx_ring->syncp);
906 q_vector->tx.total_bytes += total_bytes;
907 q_vector->tx.total_packets += total_packets;
908
909 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
910 /* schedule immediate reset if we believe we hung */
911 struct ixgbe_hw *hw = &adapter->hw;
912 e_err(drv, "Detected Tx Unit Hang\n"
913 " Tx Queue <%d>\n"
914 " TDH, TDT <%x>, <%x>\n"
915 " next_to_use <%x>\n"
916 " next_to_clean <%x>\n"
917 "tx_buffer_info[next_to_clean]\n"
918 " time_stamp <%lx>\n"
919 " jiffies <%lx>\n",
920 tx_ring->queue_index,
921 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
922 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
923 tx_ring->next_to_use, i,
924 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
925
926 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
927
928 e_info(probe,
929 "tx hang %d detected on queue %d, resetting adapter\n",
930 adapter->tx_timeout_count + 1, tx_ring->queue_index);
931
932 /* schedule immediate reset if we believe we hung */
933 ixgbe_tx_timeout_reset(adapter);
934
935 /* the adapter is about to reset, no point in enabling stuff */
936 return true;
937 }
938
939 netdev_tx_completed_queue(txring_txq(tx_ring),
940 total_packets, total_bytes);
941
942 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
943 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
944 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
945 /* Make sure that anybody stopping the queue after this
946 * sees the new next_to_clean.
947 */
948 smp_mb();
949 if (__netif_subqueue_stopped(tx_ring->netdev,
950 tx_ring->queue_index)
951 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
952 netif_wake_subqueue(tx_ring->netdev,
953 tx_ring->queue_index);
954 ++tx_ring->tx_stats.restart_queue;
955 }
956 }
957
958 return !!budget;
959 }
960
961 #ifdef CONFIG_IXGBE_DCA
962 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
963 struct ixgbe_ring *tx_ring,
964 int cpu)
965 {
966 struct ixgbe_hw *hw = &adapter->hw;
967 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
968 u16 reg_offset;
969
970 switch (hw->mac.type) {
971 case ixgbe_mac_82598EB:
972 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
973 break;
974 case ixgbe_mac_82599EB:
975 case ixgbe_mac_X540:
976 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
977 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
978 break;
979 default:
980 /* for unknown hardware do not write register */
981 return;
982 }
983
984 /*
985 * We can enable relaxed ordering for reads, but not writes when
986 * DCA is enabled. This is due to a known issue in some chipsets
987 * which will cause the DCA tag to be cleared.
988 */
989 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
990 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
991 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
992
993 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
994 }
995
996 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
997 struct ixgbe_ring *rx_ring,
998 int cpu)
999 {
1000 struct ixgbe_hw *hw = &adapter->hw;
1001 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1002 u8 reg_idx = rx_ring->reg_idx;
1003
1004
1005 switch (hw->mac.type) {
1006 case ixgbe_mac_82599EB:
1007 case ixgbe_mac_X540:
1008 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1009 break;
1010 default:
1011 break;
1012 }
1013
1014 /*
1015 * We can enable relaxed ordering for reads, but not writes when
1016 * DCA is enabled. This is due to a known issue in some chipsets
1017 * which will cause the DCA tag to be cleared.
1018 */
1019 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1020 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1021 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1022
1023 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1024 }
1025
1026 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1027 {
1028 struct ixgbe_adapter *adapter = q_vector->adapter;
1029 struct ixgbe_ring *ring;
1030 int cpu = get_cpu();
1031
1032 if (q_vector->cpu == cpu)
1033 goto out_no_update;
1034
1035 ixgbe_for_each_ring(ring, q_vector->tx)
1036 ixgbe_update_tx_dca(adapter, ring, cpu);
1037
1038 ixgbe_for_each_ring(ring, q_vector->rx)
1039 ixgbe_update_rx_dca(adapter, ring, cpu);
1040
1041 q_vector->cpu = cpu;
1042 out_no_update:
1043 put_cpu();
1044 }
1045
1046 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1047 {
1048 int i;
1049
1050 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1051 return;
1052
1053 /* always use CB2 mode, difference is masked in the CB driver */
1054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1055
1056 for (i = 0; i < adapter->num_q_vectors; i++) {
1057 adapter->q_vector[i]->cpu = -1;
1058 ixgbe_update_dca(adapter->q_vector[i]);
1059 }
1060 }
1061
1062 static int __ixgbe_notify_dca(struct device *dev, void *data)
1063 {
1064 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1065 unsigned long event = *(unsigned long *)data;
1066
1067 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1068 return 0;
1069
1070 switch (event) {
1071 case DCA_PROVIDER_ADD:
1072 /* if we're already enabled, don't do it again */
1073 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1074 break;
1075 if (dca_add_requester(dev) == 0) {
1076 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1077 ixgbe_setup_dca(adapter);
1078 break;
1079 }
1080 /* Fall Through since DCA is disabled. */
1081 case DCA_PROVIDER_REMOVE:
1082 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1083 dca_remove_requester(dev);
1084 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1085 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1086 }
1087 break;
1088 }
1089
1090 return 0;
1091 }
1092
1093 #endif /* CONFIG_IXGBE_DCA */
1094 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1095 union ixgbe_adv_rx_desc *rx_desc,
1096 struct sk_buff *skb)
1097 {
1098 if (ring->netdev->features & NETIF_F_RXHASH)
1099 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1100 }
1101
1102 #ifdef IXGBE_FCOE
1103 /**
1104 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1105 * @ring: structure containing ring specific data
1106 * @rx_desc: advanced rx descriptor
1107 *
1108 * Returns : true if it is FCoE pkt
1109 */
1110 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1111 union ixgbe_adv_rx_desc *rx_desc)
1112 {
1113 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1114
1115 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1116 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1117 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1118 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1119 }
1120
1121 #endif /* IXGBE_FCOE */
1122 /**
1123 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1124 * @ring: structure containing ring specific data
1125 * @rx_desc: current Rx descriptor being processed
1126 * @skb: skb currently being received and modified
1127 **/
1128 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1129 union ixgbe_adv_rx_desc *rx_desc,
1130 struct sk_buff *skb)
1131 {
1132 skb_checksum_none_assert(skb);
1133
1134 /* Rx csum disabled */
1135 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1136 return;
1137
1138 /* if IP and error */
1139 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1140 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1141 ring->rx_stats.csum_err++;
1142 return;
1143 }
1144
1145 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1146 return;
1147
1148 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1149 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1150
1151 /*
1152 * 82599 errata, UDP frames with a 0 checksum can be marked as
1153 * checksum errors.
1154 */
1155 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1156 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1157 return;
1158
1159 ring->rx_stats.csum_err++;
1160 return;
1161 }
1162
1163 /* It must be a TCP or UDP packet with a valid checksum */
1164 skb->ip_summed = CHECKSUM_UNNECESSARY;
1165 }
1166
1167 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1168 {
1169 rx_ring->next_to_use = val;
1170
1171 /* update next to alloc since we have filled the ring */
1172 rx_ring->next_to_alloc = val;
1173 /*
1174 * Force memory writes to complete before letting h/w
1175 * know there are new descriptors to fetch. (Only
1176 * applicable for weak-ordered memory model archs,
1177 * such as IA-64).
1178 */
1179 wmb();
1180 writel(val, rx_ring->tail);
1181 }
1182
1183 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1184 struct ixgbe_rx_buffer *bi)
1185 {
1186 struct page *page = bi->page;
1187 dma_addr_t dma = bi->dma;
1188
1189 /* since we are recycling buffers we should seldom need to alloc */
1190 if (likely(dma))
1191 return true;
1192
1193 /* alloc new page for storage */
1194 if (likely(!page)) {
1195 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1196 bi->skb, ixgbe_rx_pg_order(rx_ring));
1197 if (unlikely(!page)) {
1198 rx_ring->rx_stats.alloc_rx_page_failed++;
1199 return false;
1200 }
1201 bi->page = page;
1202 }
1203
1204 /* map page for use */
1205 dma = dma_map_page(rx_ring->dev, page, 0,
1206 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1207
1208 /*
1209 * if mapping failed free memory back to system since
1210 * there isn't much point in holding memory we can't use
1211 */
1212 if (dma_mapping_error(rx_ring->dev, dma)) {
1213 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1214 bi->page = NULL;
1215
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1217 return false;
1218 }
1219
1220 bi->dma = dma;
1221 bi->page_offset = 0;
1222
1223 return true;
1224 }
1225
1226 /**
1227 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1228 * @rx_ring: ring to place buffers on
1229 * @cleaned_count: number of buffers to replace
1230 **/
1231 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1232 {
1233 union ixgbe_adv_rx_desc *rx_desc;
1234 struct ixgbe_rx_buffer *bi;
1235 u16 i = rx_ring->next_to_use;
1236
1237 /* nothing to do */
1238 if (!cleaned_count)
1239 return;
1240
1241 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1242 bi = &rx_ring->rx_buffer_info[i];
1243 i -= rx_ring->count;
1244
1245 do {
1246 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1247 break;
1248
1249 /*
1250 * Refresh the desc even if buffer_addrs didn't change
1251 * because each write-back erases this info.
1252 */
1253 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1254
1255 rx_desc++;
1256 bi++;
1257 i++;
1258 if (unlikely(!i)) {
1259 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1260 bi = rx_ring->rx_buffer_info;
1261 i -= rx_ring->count;
1262 }
1263
1264 /* clear the hdr_addr for the next_to_use descriptor */
1265 rx_desc->read.hdr_addr = 0;
1266
1267 cleaned_count--;
1268 } while (cleaned_count);
1269
1270 i += rx_ring->count;
1271
1272 if (rx_ring->next_to_use != i)
1273 ixgbe_release_rx_desc(rx_ring, i);
1274 }
1275
1276 /**
1277 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1278 * @data: pointer to the start of the headers
1279 * @max_len: total length of section to find headers in
1280 *
1281 * This function is meant to determine the length of headers that will
1282 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1283 * motivation of doing this is to only perform one pull for IPv4 TCP
1284 * packets so that we can do basic things like calculating the gso_size
1285 * based on the average data per packet.
1286 **/
1287 static unsigned int ixgbe_get_headlen(unsigned char *data,
1288 unsigned int max_len)
1289 {
1290 union {
1291 unsigned char *network;
1292 /* l2 headers */
1293 struct ethhdr *eth;
1294 struct vlan_hdr *vlan;
1295 /* l3 headers */
1296 struct iphdr *ipv4;
1297 struct ipv6hdr *ipv6;
1298 } hdr;
1299 __be16 protocol;
1300 u8 nexthdr = 0; /* default to not TCP */
1301 u8 hlen;
1302
1303 /* this should never happen, but better safe than sorry */
1304 if (max_len < ETH_HLEN)
1305 return max_len;
1306
1307 /* initialize network frame pointer */
1308 hdr.network = data;
1309
1310 /* set first protocol and move network header forward */
1311 protocol = hdr.eth->h_proto;
1312 hdr.network += ETH_HLEN;
1313
1314 /* handle any vlan tag if present */
1315 if (protocol == __constant_htons(ETH_P_8021Q)) {
1316 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1317 return max_len;
1318
1319 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1320 hdr.network += VLAN_HLEN;
1321 }
1322
1323 /* handle L3 protocols */
1324 if (protocol == __constant_htons(ETH_P_IP)) {
1325 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1326 return max_len;
1327
1328 /* access ihl as a u8 to avoid unaligned access on ia64 */
1329 hlen = (hdr.network[0] & 0x0F) << 2;
1330
1331 /* verify hlen meets minimum size requirements */
1332 if (hlen < sizeof(struct iphdr))
1333 return hdr.network - data;
1334
1335 /* record next protocol */
1336 nexthdr = hdr.ipv4->protocol;
1337 hdr.network += hlen;
1338 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1339 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1340 return max_len;
1341
1342 /* record next protocol */
1343 nexthdr = hdr.ipv6->nexthdr;
1344 hdr.network += sizeof(struct ipv6hdr);
1345 #ifdef IXGBE_FCOE
1346 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1347 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1348 return max_len;
1349 hdr.network += FCOE_HEADER_LEN;
1350 #endif
1351 } else {
1352 return hdr.network - data;
1353 }
1354
1355 /* finally sort out TCP/UDP */
1356 if (nexthdr == IPPROTO_TCP) {
1357 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1358 return max_len;
1359
1360 /* access doff as a u8 to avoid unaligned access on ia64 */
1361 hlen = (hdr.network[12] & 0xF0) >> 2;
1362
1363 /* verify hlen meets minimum size requirements */
1364 if (hlen < sizeof(struct tcphdr))
1365 return hdr.network - data;
1366
1367 hdr.network += hlen;
1368 } else if (nexthdr == IPPROTO_UDP) {
1369 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1370 return max_len;
1371
1372 hdr.network += sizeof(struct udphdr);
1373 }
1374
1375 /*
1376 * If everything has gone correctly hdr.network should be the
1377 * data section of the packet and will be the end of the header.
1378 * If not then it probably represents the end of the last recognized
1379 * header.
1380 */
1381 if ((hdr.network - data) < max_len)
1382 return hdr.network - data;
1383 else
1384 return max_len;
1385 }
1386
1387 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1388 struct sk_buff *skb)
1389 {
1390 u16 hdr_len = skb_headlen(skb);
1391
1392 /* set gso_size to avoid messing up TCP MSS */
1393 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1394 IXGBE_CB(skb)->append_cnt);
1395 }
1396
1397 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1398 struct sk_buff *skb)
1399 {
1400 /* if append_cnt is 0 then frame is not RSC */
1401 if (!IXGBE_CB(skb)->append_cnt)
1402 return;
1403
1404 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1405 rx_ring->rx_stats.rsc_flush++;
1406
1407 ixgbe_set_rsc_gso_size(rx_ring, skb);
1408
1409 /* gso_size is computed using append_cnt so always clear it last */
1410 IXGBE_CB(skb)->append_cnt = 0;
1411 }
1412
1413 /**
1414 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1415 * @rx_ring: rx descriptor ring packet is being transacted on
1416 * @rx_desc: pointer to the EOP Rx descriptor
1417 * @skb: pointer to current skb being populated
1418 *
1419 * This function checks the ring, descriptor, and packet information in
1420 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1421 * other fields within the skb.
1422 **/
1423 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1424 union ixgbe_adv_rx_desc *rx_desc,
1425 struct sk_buff *skb)
1426 {
1427 struct net_device *dev = rx_ring->netdev;
1428
1429 ixgbe_update_rsc_stats(rx_ring, skb);
1430
1431 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1432
1433 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1434
1435 #ifdef CONFIG_IXGBE_PTP
1436 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1437 #endif
1438
1439 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1440 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1441 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1442 __vlan_hwaccel_put_tag(skb, vid);
1443 }
1444
1445 skb_record_rx_queue(skb, rx_ring->queue_index);
1446
1447 skb->protocol = eth_type_trans(skb, dev);
1448 }
1449
1450 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1451 struct sk_buff *skb)
1452 {
1453 struct ixgbe_adapter *adapter = q_vector->adapter;
1454
1455 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1456 napi_gro_receive(&q_vector->napi, skb);
1457 else
1458 netif_rx(skb);
1459 }
1460
1461 /**
1462 * ixgbe_is_non_eop - process handling of non-EOP buffers
1463 * @rx_ring: Rx ring being processed
1464 * @rx_desc: Rx descriptor for current buffer
1465 * @skb: Current socket buffer containing buffer in progress
1466 *
1467 * This function updates next to clean. If the buffer is an EOP buffer
1468 * this function exits returning false, otherwise it will place the
1469 * sk_buff in the next buffer to be chained and return true indicating
1470 * that this is in fact a non-EOP buffer.
1471 **/
1472 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1473 union ixgbe_adv_rx_desc *rx_desc,
1474 struct sk_buff *skb)
1475 {
1476 u32 ntc = rx_ring->next_to_clean + 1;
1477
1478 /* fetch, update, and store next to clean */
1479 ntc = (ntc < rx_ring->count) ? ntc : 0;
1480 rx_ring->next_to_clean = ntc;
1481
1482 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1483
1484 /* update RSC append count if present */
1485 if (ring_is_rsc_enabled(rx_ring)) {
1486 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1487 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1488
1489 if (unlikely(rsc_enabled)) {
1490 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1491
1492 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1493 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1494
1495 /* update ntc based on RSC value */
1496 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1497 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1498 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1499 }
1500 }
1501
1502 /* if we are the last buffer then there is nothing else to do */
1503 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1504 return false;
1505
1506 /* place skb in next buffer to be received */
1507 rx_ring->rx_buffer_info[ntc].skb = skb;
1508 rx_ring->rx_stats.non_eop_descs++;
1509
1510 return true;
1511 }
1512
1513 /**
1514 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1515 * @rx_ring: rx descriptor ring packet is being transacted on
1516 * @skb: pointer to current skb being adjusted
1517 *
1518 * This function is an ixgbe specific version of __pskb_pull_tail. The
1519 * main difference between this version and the original function is that
1520 * this function can make several assumptions about the state of things
1521 * that allow for significant optimizations versus the standard function.
1522 * As a result we can do things like drop a frag and maintain an accurate
1523 * truesize for the skb.
1524 */
1525 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1526 struct sk_buff *skb)
1527 {
1528 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1529 unsigned char *va;
1530 unsigned int pull_len;
1531
1532 /*
1533 * it is valid to use page_address instead of kmap since we are
1534 * working with pages allocated out of the lomem pool per
1535 * alloc_page(GFP_ATOMIC)
1536 */
1537 va = skb_frag_address(frag);
1538
1539 /*
1540 * we need the header to contain the greater of either ETH_HLEN or
1541 * 60 bytes if the skb->len is less than 60 for skb_pad.
1542 */
1543 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1544
1545 /* align pull length to size of long to optimize memcpy performance */
1546 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1547
1548 /* update all of the pointers */
1549 skb_frag_size_sub(frag, pull_len);
1550 frag->page_offset += pull_len;
1551 skb->data_len -= pull_len;
1552 skb->tail += pull_len;
1553 }
1554
1555 /**
1556 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1557 * @rx_ring: rx descriptor ring packet is being transacted on
1558 * @skb: pointer to current skb being updated
1559 *
1560 * This function provides a basic DMA sync up for the first fragment of an
1561 * skb. The reason for doing this is that the first fragment cannot be
1562 * unmapped until we have reached the end of packet descriptor for a buffer
1563 * chain.
1564 */
1565 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1566 struct sk_buff *skb)
1567 {
1568 /* if the page was released unmap it, else just sync our portion */
1569 if (unlikely(IXGBE_CB(skb)->page_released)) {
1570 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1571 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1572 IXGBE_CB(skb)->page_released = false;
1573 } else {
1574 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1575
1576 dma_sync_single_range_for_cpu(rx_ring->dev,
1577 IXGBE_CB(skb)->dma,
1578 frag->page_offset,
1579 ixgbe_rx_bufsz(rx_ring),
1580 DMA_FROM_DEVICE);
1581 }
1582 IXGBE_CB(skb)->dma = 0;
1583 }
1584
1585 /**
1586 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1587 * @rx_ring: rx descriptor ring packet is being transacted on
1588 * @rx_desc: pointer to the EOP Rx descriptor
1589 * @skb: pointer to current skb being fixed
1590 *
1591 * Check for corrupted packet headers caused by senders on the local L2
1592 * embedded NIC switch not setting up their Tx Descriptors right. These
1593 * should be very rare.
1594 *
1595 * Also address the case where we are pulling data in on pages only
1596 * and as such no data is present in the skb header.
1597 *
1598 * In addition if skb is not at least 60 bytes we need to pad it so that
1599 * it is large enough to qualify as a valid Ethernet frame.
1600 *
1601 * Returns true if an error was encountered and skb was freed.
1602 **/
1603 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1604 union ixgbe_adv_rx_desc *rx_desc,
1605 struct sk_buff *skb)
1606 {
1607 struct net_device *netdev = rx_ring->netdev;
1608
1609 /* verify that the packet does not have any known errors */
1610 if (unlikely(ixgbe_test_staterr(rx_desc,
1611 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1612 !(netdev->features & NETIF_F_RXALL))) {
1613 dev_kfree_skb_any(skb);
1614 return true;
1615 }
1616
1617 /* place header in linear portion of buffer */
1618 if (skb_is_nonlinear(skb))
1619 ixgbe_pull_tail(rx_ring, skb);
1620
1621 #ifdef IXGBE_FCOE
1622 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1623 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1624 return false;
1625
1626 #endif
1627 /* if skb_pad returns an error the skb was freed */
1628 if (unlikely(skb->len < 60)) {
1629 int pad_len = 60 - skb->len;
1630
1631 if (skb_pad(skb, pad_len))
1632 return true;
1633 __skb_put(skb, pad_len);
1634 }
1635
1636 return false;
1637 }
1638
1639 /**
1640 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1641 * @rx_ring: rx descriptor ring to store buffers on
1642 * @old_buff: donor buffer to have page reused
1643 *
1644 * Synchronizes page for reuse by the adapter
1645 **/
1646 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1647 struct ixgbe_rx_buffer *old_buff)
1648 {
1649 struct ixgbe_rx_buffer *new_buff;
1650 u16 nta = rx_ring->next_to_alloc;
1651
1652 new_buff = &rx_ring->rx_buffer_info[nta];
1653
1654 /* update, and store next to alloc */
1655 nta++;
1656 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1657
1658 /* transfer page from old buffer to new buffer */
1659 new_buff->page = old_buff->page;
1660 new_buff->dma = old_buff->dma;
1661 new_buff->page_offset = old_buff->page_offset;
1662
1663 /* sync the buffer for use by the device */
1664 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1665 new_buff->page_offset,
1666 ixgbe_rx_bufsz(rx_ring),
1667 DMA_FROM_DEVICE);
1668 }
1669
1670 /**
1671 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1672 * @rx_ring: rx descriptor ring to transact packets on
1673 * @rx_buffer: buffer containing page to add
1674 * @rx_desc: descriptor containing length of buffer written by hardware
1675 * @skb: sk_buff to place the data into
1676 *
1677 * This function will add the data contained in rx_buffer->page to the skb.
1678 * This is done either through a direct copy if the data in the buffer is
1679 * less than the skb header size, otherwise it will just attach the page as
1680 * a frag to the skb.
1681 *
1682 * The function will then update the page offset if necessary and return
1683 * true if the buffer can be reused by the adapter.
1684 **/
1685 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1686 struct ixgbe_rx_buffer *rx_buffer,
1687 union ixgbe_adv_rx_desc *rx_desc,
1688 struct sk_buff *skb)
1689 {
1690 struct page *page = rx_buffer->page;
1691 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1692 #if (PAGE_SIZE < 8192)
1693 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1694 #else
1695 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1696 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1697 ixgbe_rx_bufsz(rx_ring);
1698 #endif
1699
1700 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1701 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1702
1703 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1704
1705 /* we can reuse buffer as-is, just make sure it is local */
1706 if (likely(page_to_nid(page) == numa_node_id()))
1707 return true;
1708
1709 /* this page cannot be reused so discard it */
1710 put_page(page);
1711 return false;
1712 }
1713
1714 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1715 rx_buffer->page_offset, size, truesize);
1716
1717 /* avoid re-using remote pages */
1718 if (unlikely(page_to_nid(page) != numa_node_id()))
1719 return false;
1720
1721 #if (PAGE_SIZE < 8192)
1722 /* if we are only owner of page we can reuse it */
1723 if (unlikely(page_count(page) != 1))
1724 return false;
1725
1726 /* flip page offset to other buffer */
1727 rx_buffer->page_offset ^= truesize;
1728
1729 /*
1730 * since we are the only owner of the page and we need to
1731 * increment it, just set the value to 2 in order to avoid
1732 * an unecessary locked operation
1733 */
1734 atomic_set(&page->_count, 2);
1735 #else
1736 /* move offset up to the next cache line */
1737 rx_buffer->page_offset += truesize;
1738
1739 if (rx_buffer->page_offset > last_offset)
1740 return false;
1741
1742 /* bump ref count on page before it is given to the stack */
1743 get_page(page);
1744 #endif
1745
1746 return true;
1747 }
1748
1749 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1750 union ixgbe_adv_rx_desc *rx_desc)
1751 {
1752 struct ixgbe_rx_buffer *rx_buffer;
1753 struct sk_buff *skb;
1754 struct page *page;
1755
1756 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1757 page = rx_buffer->page;
1758 prefetchw(page);
1759
1760 skb = rx_buffer->skb;
1761
1762 if (likely(!skb)) {
1763 void *page_addr = page_address(page) +
1764 rx_buffer->page_offset;
1765
1766 /* prefetch first cache line of first page */
1767 prefetch(page_addr);
1768 #if L1_CACHE_BYTES < 128
1769 prefetch(page_addr + L1_CACHE_BYTES);
1770 #endif
1771
1772 /* allocate a skb to store the frags */
1773 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1774 IXGBE_RX_HDR_SIZE);
1775 if (unlikely(!skb)) {
1776 rx_ring->rx_stats.alloc_rx_buff_failed++;
1777 return NULL;
1778 }
1779
1780 /*
1781 * we will be copying header into skb->data in
1782 * pskb_may_pull so it is in our interest to prefetch
1783 * it now to avoid a possible cache miss
1784 */
1785 prefetchw(skb->data);
1786
1787 /*
1788 * Delay unmapping of the first packet. It carries the
1789 * header information, HW may still access the header
1790 * after the writeback. Only unmap it when EOP is
1791 * reached
1792 */
1793 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1794 goto dma_sync;
1795
1796 IXGBE_CB(skb)->dma = rx_buffer->dma;
1797 } else {
1798 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1799 ixgbe_dma_sync_frag(rx_ring, skb);
1800
1801 dma_sync:
1802 /* we are reusing so sync this buffer for CPU use */
1803 dma_sync_single_range_for_cpu(rx_ring->dev,
1804 rx_buffer->dma,
1805 rx_buffer->page_offset,
1806 ixgbe_rx_bufsz(rx_ring),
1807 DMA_FROM_DEVICE);
1808 }
1809
1810 /* pull page into skb */
1811 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1812 /* hand second half of page back to the ring */
1813 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1814 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1815 /* the page has been released from the ring */
1816 IXGBE_CB(skb)->page_released = true;
1817 } else {
1818 /* we are not reusing the buffer so unmap it */
1819 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1820 ixgbe_rx_pg_size(rx_ring),
1821 DMA_FROM_DEVICE);
1822 }
1823
1824 /* clear contents of buffer_info */
1825 rx_buffer->skb = NULL;
1826 rx_buffer->dma = 0;
1827 rx_buffer->page = NULL;
1828
1829 return skb;
1830 }
1831
1832 /**
1833 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1834 * @q_vector: structure containing interrupt and ring information
1835 * @rx_ring: rx descriptor ring to transact packets on
1836 * @budget: Total limit on number of packets to process
1837 *
1838 * This function provides a "bounce buffer" approach to Rx interrupt
1839 * processing. The advantage to this is that on systems that have
1840 * expensive overhead for IOMMU access this provides a means of avoiding
1841 * it by maintaining the mapping of the page to the syste.
1842 *
1843 * Returns true if all work is completed without reaching budget
1844 **/
1845 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1846 struct ixgbe_ring *rx_ring,
1847 const int budget)
1848 {
1849 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1850 #ifdef IXGBE_FCOE
1851 struct ixgbe_adapter *adapter = q_vector->adapter;
1852 int ddp_bytes;
1853 unsigned int mss = 0;
1854 #endif /* IXGBE_FCOE */
1855 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1856
1857 do {
1858 union ixgbe_adv_rx_desc *rx_desc;
1859 struct sk_buff *skb;
1860
1861 /* return some buffers to hardware, one at a time is too slow */
1862 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1863 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1864 cleaned_count = 0;
1865 }
1866
1867 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1868
1869 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1870 break;
1871
1872 /*
1873 * This memory barrier is needed to keep us from reading
1874 * any other fields out of the rx_desc until we know the
1875 * RXD_STAT_DD bit is set
1876 */
1877 rmb();
1878
1879 /* retrieve a buffer from the ring */
1880 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1881
1882 /* exit if we failed to retrieve a buffer */
1883 if (!skb)
1884 break;
1885
1886 cleaned_count++;
1887
1888 /* place incomplete frames back on ring for completion */
1889 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1890 continue;
1891
1892 /* verify the packet layout is correct */
1893 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1894 continue;
1895
1896 /* probably a little skewed due to removing CRC */
1897 total_rx_bytes += skb->len;
1898
1899 /* populate checksum, timestamp, VLAN, and protocol */
1900 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1901
1902 #ifdef IXGBE_FCOE
1903 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1904 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1905 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1906 /* include DDPed FCoE data */
1907 if (ddp_bytes > 0) {
1908 if (!mss) {
1909 mss = rx_ring->netdev->mtu -
1910 sizeof(struct fcoe_hdr) -
1911 sizeof(struct fc_frame_header) -
1912 sizeof(struct fcoe_crc_eof);
1913 if (mss > 512)
1914 mss &= ~511;
1915 }
1916 total_rx_bytes += ddp_bytes;
1917 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1918 mss);
1919 }
1920 if (!ddp_bytes) {
1921 dev_kfree_skb_any(skb);
1922 continue;
1923 }
1924 }
1925
1926 #endif /* IXGBE_FCOE */
1927 ixgbe_rx_skb(q_vector, skb);
1928
1929 /* update budget accounting */
1930 total_rx_packets++;
1931 } while (likely(total_rx_packets < budget));
1932
1933 u64_stats_update_begin(&rx_ring->syncp);
1934 rx_ring->stats.packets += total_rx_packets;
1935 rx_ring->stats.bytes += total_rx_bytes;
1936 u64_stats_update_end(&rx_ring->syncp);
1937 q_vector->rx.total_packets += total_rx_packets;
1938 q_vector->rx.total_bytes += total_rx_bytes;
1939
1940 if (cleaned_count)
1941 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1942
1943 return (total_rx_packets < budget);
1944 }
1945
1946 /**
1947 * ixgbe_configure_msix - Configure MSI-X hardware
1948 * @adapter: board private structure
1949 *
1950 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1951 * interrupts.
1952 **/
1953 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1954 {
1955 struct ixgbe_q_vector *q_vector;
1956 int v_idx;
1957 u32 mask;
1958
1959 /* Populate MSIX to EITR Select */
1960 if (adapter->num_vfs > 32) {
1961 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1963 }
1964
1965 /*
1966 * Populate the IVAR table and set the ITR values to the
1967 * corresponding register.
1968 */
1969 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1970 struct ixgbe_ring *ring;
1971 q_vector = adapter->q_vector[v_idx];
1972
1973 ixgbe_for_each_ring(ring, q_vector->rx)
1974 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1975
1976 ixgbe_for_each_ring(ring, q_vector->tx)
1977 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1978
1979 if (q_vector->tx.ring && !q_vector->rx.ring) {
1980 /* tx only vector */
1981 if (adapter->tx_itr_setting == 1)
1982 q_vector->itr = IXGBE_10K_ITR;
1983 else
1984 q_vector->itr = adapter->tx_itr_setting;
1985 } else {
1986 /* rx or rx/tx vector */
1987 if (adapter->rx_itr_setting == 1)
1988 q_vector->itr = IXGBE_20K_ITR;
1989 else
1990 q_vector->itr = adapter->rx_itr_setting;
1991 }
1992
1993 ixgbe_write_eitr(q_vector);
1994 }
1995
1996 switch (adapter->hw.mac.type) {
1997 case ixgbe_mac_82598EB:
1998 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1999 v_idx);
2000 break;
2001 case ixgbe_mac_82599EB:
2002 case ixgbe_mac_X540:
2003 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2004 break;
2005 default:
2006 break;
2007 }
2008 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2009
2010 /* set up to autoclear timer, and the vectors */
2011 mask = IXGBE_EIMS_ENABLE_MASK;
2012 mask &= ~(IXGBE_EIMS_OTHER |
2013 IXGBE_EIMS_MAILBOX |
2014 IXGBE_EIMS_LSC);
2015
2016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2017 }
2018
2019 enum latency_range {
2020 lowest_latency = 0,
2021 low_latency = 1,
2022 bulk_latency = 2,
2023 latency_invalid = 255
2024 };
2025
2026 /**
2027 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2028 * @q_vector: structure containing interrupt and ring information
2029 * @ring_container: structure containing ring performance data
2030 *
2031 * Stores a new ITR value based on packets and byte
2032 * counts during the last interrupt. The advantage of per interrupt
2033 * computation is faster updates and more accurate ITR for the current
2034 * traffic pattern. Constants in this function were computed
2035 * based on theoretical maximum wire speed and thresholds were set based
2036 * on testing data as well as attempting to minimize response time
2037 * while increasing bulk throughput.
2038 * this functionality is controlled by the InterruptThrottleRate module
2039 * parameter (see ixgbe_param.c)
2040 **/
2041 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2042 struct ixgbe_ring_container *ring_container)
2043 {
2044 int bytes = ring_container->total_bytes;
2045 int packets = ring_container->total_packets;
2046 u32 timepassed_us;
2047 u64 bytes_perint;
2048 u8 itr_setting = ring_container->itr;
2049
2050 if (packets == 0)
2051 return;
2052
2053 /* simple throttlerate management
2054 * 0-10MB/s lowest (100000 ints/s)
2055 * 10-20MB/s low (20000 ints/s)
2056 * 20-1249MB/s bulk (8000 ints/s)
2057 */
2058 /* what was last interrupt timeslice? */
2059 timepassed_us = q_vector->itr >> 2;
2060 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2061
2062 switch (itr_setting) {
2063 case lowest_latency:
2064 if (bytes_perint > 10)
2065 itr_setting = low_latency;
2066 break;
2067 case low_latency:
2068 if (bytes_perint > 20)
2069 itr_setting = bulk_latency;
2070 else if (bytes_perint <= 10)
2071 itr_setting = lowest_latency;
2072 break;
2073 case bulk_latency:
2074 if (bytes_perint <= 20)
2075 itr_setting = low_latency;
2076 break;
2077 }
2078
2079 /* clear work counters since we have the values we need */
2080 ring_container->total_bytes = 0;
2081 ring_container->total_packets = 0;
2082
2083 /* write updated itr to ring container */
2084 ring_container->itr = itr_setting;
2085 }
2086
2087 /**
2088 * ixgbe_write_eitr - write EITR register in hardware specific way
2089 * @q_vector: structure containing interrupt and ring information
2090 *
2091 * This function is made to be called by ethtool and by the driver
2092 * when it needs to update EITR registers at runtime. Hardware
2093 * specific quirks/differences are taken care of here.
2094 */
2095 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2096 {
2097 struct ixgbe_adapter *adapter = q_vector->adapter;
2098 struct ixgbe_hw *hw = &adapter->hw;
2099 int v_idx = q_vector->v_idx;
2100 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2101
2102 switch (adapter->hw.mac.type) {
2103 case ixgbe_mac_82598EB:
2104 /* must write high and low 16 bits to reset counter */
2105 itr_reg |= (itr_reg << 16);
2106 break;
2107 case ixgbe_mac_82599EB:
2108 case ixgbe_mac_X540:
2109 /*
2110 * set the WDIS bit to not clear the timer bits and cause an
2111 * immediate assertion of the interrupt
2112 */
2113 itr_reg |= IXGBE_EITR_CNT_WDIS;
2114 break;
2115 default:
2116 break;
2117 }
2118 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2119 }
2120
2121 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2122 {
2123 u32 new_itr = q_vector->itr;
2124 u8 current_itr;
2125
2126 ixgbe_update_itr(q_vector, &q_vector->tx);
2127 ixgbe_update_itr(q_vector, &q_vector->rx);
2128
2129 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2130
2131 switch (current_itr) {
2132 /* counts and packets in update_itr are dependent on these numbers */
2133 case lowest_latency:
2134 new_itr = IXGBE_100K_ITR;
2135 break;
2136 case low_latency:
2137 new_itr = IXGBE_20K_ITR;
2138 break;
2139 case bulk_latency:
2140 new_itr = IXGBE_8K_ITR;
2141 break;
2142 default:
2143 break;
2144 }
2145
2146 if (new_itr != q_vector->itr) {
2147 /* do an exponential smoothing */
2148 new_itr = (10 * new_itr * q_vector->itr) /
2149 ((9 * new_itr) + q_vector->itr);
2150
2151 /* save the algorithm value here */
2152 q_vector->itr = new_itr;
2153
2154 ixgbe_write_eitr(q_vector);
2155 }
2156 }
2157
2158 /**
2159 * ixgbe_check_overtemp_subtask - check for over temperature
2160 * @adapter: pointer to adapter
2161 **/
2162 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2163 {
2164 struct ixgbe_hw *hw = &adapter->hw;
2165 u32 eicr = adapter->interrupt_event;
2166
2167 if (test_bit(__IXGBE_DOWN, &adapter->state))
2168 return;
2169
2170 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2171 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2172 return;
2173
2174 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2175
2176 switch (hw->device_id) {
2177 case IXGBE_DEV_ID_82599_T3_LOM:
2178 /*
2179 * Since the warning interrupt is for both ports
2180 * we don't have to check if:
2181 * - This interrupt wasn't for our port.
2182 * - We may have missed the interrupt so always have to
2183 * check if we got a LSC
2184 */
2185 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2186 !(eicr & IXGBE_EICR_LSC))
2187 return;
2188
2189 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2190 u32 autoneg;
2191 bool link_up = false;
2192
2193 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2194
2195 if (link_up)
2196 return;
2197 }
2198
2199 /* Check if this is not due to overtemp */
2200 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2201 return;
2202
2203 break;
2204 default:
2205 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2206 return;
2207 break;
2208 }
2209 e_crit(drv,
2210 "Network adapter has been stopped because it has over heated. "
2211 "Restart the computer. If the problem persists, "
2212 "power off the system and replace the adapter\n");
2213
2214 adapter->interrupt_event = 0;
2215 }
2216
2217 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2218 {
2219 struct ixgbe_hw *hw = &adapter->hw;
2220
2221 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2222 (eicr & IXGBE_EICR_GPI_SDP1)) {
2223 e_crit(probe, "Fan has stopped, replace the adapter\n");
2224 /* write to clear the interrupt */
2225 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2226 }
2227 }
2228
2229 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2230 {
2231 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2232 return;
2233
2234 switch (adapter->hw.mac.type) {
2235 case ixgbe_mac_82599EB:
2236 /*
2237 * Need to check link state so complete overtemp check
2238 * on service task
2239 */
2240 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2241 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2242 adapter->interrupt_event = eicr;
2243 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2244 ixgbe_service_event_schedule(adapter);
2245 return;
2246 }
2247 return;
2248 case ixgbe_mac_X540:
2249 if (!(eicr & IXGBE_EICR_TS))
2250 return;
2251 break;
2252 default:
2253 return;
2254 }
2255
2256 e_crit(drv,
2257 "Network adapter has been stopped because it has over heated. "
2258 "Restart the computer. If the problem persists, "
2259 "power off the system and replace the adapter\n");
2260 }
2261
2262 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2263 {
2264 struct ixgbe_hw *hw = &adapter->hw;
2265
2266 if (eicr & IXGBE_EICR_GPI_SDP2) {
2267 /* Clear the interrupt */
2268 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2269 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2270 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2271 ixgbe_service_event_schedule(adapter);
2272 }
2273 }
2274
2275 if (eicr & IXGBE_EICR_GPI_SDP1) {
2276 /* Clear the interrupt */
2277 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2278 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2279 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2280 ixgbe_service_event_schedule(adapter);
2281 }
2282 }
2283 }
2284
2285 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2286 {
2287 struct ixgbe_hw *hw = &adapter->hw;
2288
2289 adapter->lsc_int++;
2290 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2291 adapter->link_check_timeout = jiffies;
2292 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2293 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2294 IXGBE_WRITE_FLUSH(hw);
2295 ixgbe_service_event_schedule(adapter);
2296 }
2297 }
2298
2299 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2300 u64 qmask)
2301 {
2302 u32 mask;
2303 struct ixgbe_hw *hw = &adapter->hw;
2304
2305 switch (hw->mac.type) {
2306 case ixgbe_mac_82598EB:
2307 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2308 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2309 break;
2310 case ixgbe_mac_82599EB:
2311 case ixgbe_mac_X540:
2312 mask = (qmask & 0xFFFFFFFF);
2313 if (mask)
2314 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2315 mask = (qmask >> 32);
2316 if (mask)
2317 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2318 break;
2319 default:
2320 break;
2321 }
2322 /* skip the flush */
2323 }
2324
2325 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2326 u64 qmask)
2327 {
2328 u32 mask;
2329 struct ixgbe_hw *hw = &adapter->hw;
2330
2331 switch (hw->mac.type) {
2332 case ixgbe_mac_82598EB:
2333 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2334 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2335 break;
2336 case ixgbe_mac_82599EB:
2337 case ixgbe_mac_X540:
2338 mask = (qmask & 0xFFFFFFFF);
2339 if (mask)
2340 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2341 mask = (qmask >> 32);
2342 if (mask)
2343 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2344 break;
2345 default:
2346 break;
2347 }
2348 /* skip the flush */
2349 }
2350
2351 /**
2352 * ixgbe_irq_enable - Enable default interrupt generation settings
2353 * @adapter: board private structure
2354 **/
2355 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2356 bool flush)
2357 {
2358 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2359
2360 /* don't reenable LSC while waiting for link */
2361 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2362 mask &= ~IXGBE_EIMS_LSC;
2363
2364 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2365 switch (adapter->hw.mac.type) {
2366 case ixgbe_mac_82599EB:
2367 mask |= IXGBE_EIMS_GPI_SDP0;
2368 break;
2369 case ixgbe_mac_X540:
2370 mask |= IXGBE_EIMS_TS;
2371 break;
2372 default:
2373 break;
2374 }
2375 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2376 mask |= IXGBE_EIMS_GPI_SDP1;
2377 switch (adapter->hw.mac.type) {
2378 case ixgbe_mac_82599EB:
2379 mask |= IXGBE_EIMS_GPI_SDP1;
2380 mask |= IXGBE_EIMS_GPI_SDP2;
2381 case ixgbe_mac_X540:
2382 mask |= IXGBE_EIMS_ECC;
2383 mask |= IXGBE_EIMS_MAILBOX;
2384 break;
2385 default:
2386 break;
2387 }
2388
2389 #ifdef CONFIG_IXGBE_PTP
2390 if (adapter->hw.mac.type == ixgbe_mac_X540)
2391 mask |= IXGBE_EIMS_TIMESYNC;
2392 #endif
2393
2394 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2395 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2396 mask |= IXGBE_EIMS_FLOW_DIR;
2397
2398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2399 if (queues)
2400 ixgbe_irq_enable_queues(adapter, ~0);
2401 if (flush)
2402 IXGBE_WRITE_FLUSH(&adapter->hw);
2403 }
2404
2405 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2406 {
2407 struct ixgbe_adapter *adapter = data;
2408 struct ixgbe_hw *hw = &adapter->hw;
2409 u32 eicr;
2410
2411 /*
2412 * Workaround for Silicon errata. Use clear-by-write instead
2413 * of clear-by-read. Reading with EICS will return the
2414 * interrupt causes without clearing, which later be done
2415 * with the write to EICR.
2416 */
2417 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2418 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2419
2420 if (eicr & IXGBE_EICR_LSC)
2421 ixgbe_check_lsc(adapter);
2422
2423 if (eicr & IXGBE_EICR_MAILBOX)
2424 ixgbe_msg_task(adapter);
2425
2426 switch (hw->mac.type) {
2427 case ixgbe_mac_82599EB:
2428 case ixgbe_mac_X540:
2429 if (eicr & IXGBE_EICR_ECC)
2430 e_info(link, "Received unrecoverable ECC Err, please "
2431 "reboot\n");
2432 /* Handle Flow Director Full threshold interrupt */
2433 if (eicr & IXGBE_EICR_FLOW_DIR) {
2434 int reinit_count = 0;
2435 int i;
2436 for (i = 0; i < adapter->num_tx_queues; i++) {
2437 struct ixgbe_ring *ring = adapter->tx_ring[i];
2438 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2439 &ring->state))
2440 reinit_count++;
2441 }
2442 if (reinit_count) {
2443 /* no more flow director interrupts until after init */
2444 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2445 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2446 ixgbe_service_event_schedule(adapter);
2447 }
2448 }
2449 ixgbe_check_sfp_event(adapter, eicr);
2450 ixgbe_check_overtemp_event(adapter, eicr);
2451 break;
2452 default:
2453 break;
2454 }
2455
2456 ixgbe_check_fan_failure(adapter, eicr);
2457
2458 #ifdef CONFIG_IXGBE_PTP
2459 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2460 ixgbe_ptp_check_pps_event(adapter, eicr);
2461 #endif
2462
2463 /* re-enable the original interrupt state, no lsc, no queues */
2464 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2465 ixgbe_irq_enable(adapter, false, false);
2466
2467 return IRQ_HANDLED;
2468 }
2469
2470 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2471 {
2472 struct ixgbe_q_vector *q_vector = data;
2473
2474 /* EIAM disabled interrupts (on this vector) for us */
2475
2476 if (q_vector->rx.ring || q_vector->tx.ring)
2477 napi_schedule(&q_vector->napi);
2478
2479 return IRQ_HANDLED;
2480 }
2481
2482 /**
2483 * ixgbe_poll - NAPI Rx polling callback
2484 * @napi: structure for representing this polling device
2485 * @budget: how many packets driver is allowed to clean
2486 *
2487 * This function is used for legacy and MSI, NAPI mode
2488 **/
2489 int ixgbe_poll(struct napi_struct *napi, int budget)
2490 {
2491 struct ixgbe_q_vector *q_vector =
2492 container_of(napi, struct ixgbe_q_vector, napi);
2493 struct ixgbe_adapter *adapter = q_vector->adapter;
2494 struct ixgbe_ring *ring;
2495 int per_ring_budget;
2496 bool clean_complete = true;
2497
2498 #ifdef CONFIG_IXGBE_DCA
2499 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2500 ixgbe_update_dca(q_vector);
2501 #endif
2502
2503 ixgbe_for_each_ring(ring, q_vector->tx)
2504 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2505
2506 /* attempt to distribute budget to each queue fairly, but don't allow
2507 * the budget to go below 1 because we'll exit polling */
2508 if (q_vector->rx.count > 1)
2509 per_ring_budget = max(budget/q_vector->rx.count, 1);
2510 else
2511 per_ring_budget = budget;
2512
2513 ixgbe_for_each_ring(ring, q_vector->rx)
2514 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2515 per_ring_budget);
2516
2517 /* If all work not completed, return budget and keep polling */
2518 if (!clean_complete)
2519 return budget;
2520
2521 /* all work done, exit the polling mode */
2522 napi_complete(napi);
2523 if (adapter->rx_itr_setting & 1)
2524 ixgbe_set_itr(q_vector);
2525 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2526 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2527
2528 return 0;
2529 }
2530
2531 /**
2532 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2533 * @adapter: board private structure
2534 *
2535 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2536 * interrupts from the kernel.
2537 **/
2538 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2539 {
2540 struct net_device *netdev = adapter->netdev;
2541 int vector, err;
2542 int ri = 0, ti = 0;
2543
2544 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2545 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2546 struct msix_entry *entry = &adapter->msix_entries[vector];
2547
2548 if (q_vector->tx.ring && q_vector->rx.ring) {
2549 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2550 "%s-%s-%d", netdev->name, "TxRx", ri++);
2551 ti++;
2552 } else if (q_vector->rx.ring) {
2553 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2554 "%s-%s-%d", netdev->name, "rx", ri++);
2555 } else if (q_vector->tx.ring) {
2556 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2557 "%s-%s-%d", netdev->name, "tx", ti++);
2558 } else {
2559 /* skip this unused q_vector */
2560 continue;
2561 }
2562 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2563 q_vector->name, q_vector);
2564 if (err) {
2565 e_err(probe, "request_irq failed for MSIX interrupt "
2566 "Error: %d\n", err);
2567 goto free_queue_irqs;
2568 }
2569 /* If Flow Director is enabled, set interrupt affinity */
2570 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2571 /* assign the mask for this irq */
2572 irq_set_affinity_hint(entry->vector,
2573 &q_vector->affinity_mask);
2574 }
2575 }
2576
2577 err = request_irq(adapter->msix_entries[vector].vector,
2578 ixgbe_msix_other, 0, netdev->name, adapter);
2579 if (err) {
2580 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2581 goto free_queue_irqs;
2582 }
2583
2584 return 0;
2585
2586 free_queue_irqs:
2587 while (vector) {
2588 vector--;
2589 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2590 NULL);
2591 free_irq(adapter->msix_entries[vector].vector,
2592 adapter->q_vector[vector]);
2593 }
2594 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2595 pci_disable_msix(adapter->pdev);
2596 kfree(adapter->msix_entries);
2597 adapter->msix_entries = NULL;
2598 return err;
2599 }
2600
2601 /**
2602 * ixgbe_intr - legacy mode Interrupt Handler
2603 * @irq: interrupt number
2604 * @data: pointer to a network interface device structure
2605 **/
2606 static irqreturn_t ixgbe_intr(int irq, void *data)
2607 {
2608 struct ixgbe_adapter *adapter = data;
2609 struct ixgbe_hw *hw = &adapter->hw;
2610 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2611 u32 eicr;
2612
2613 /*
2614 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2615 * before the read of EICR.
2616 */
2617 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2618
2619 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2620 * therefore no explicit interrupt disable is necessary */
2621 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2622 if (!eicr) {
2623 /*
2624 * shared interrupt alert!
2625 * make sure interrupts are enabled because the read will
2626 * have disabled interrupts due to EIAM
2627 * finish the workaround of silicon errata on 82598. Unmask
2628 * the interrupt that we masked before the EICR read.
2629 */
2630 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2631 ixgbe_irq_enable(adapter, true, true);
2632 return IRQ_NONE; /* Not our interrupt */
2633 }
2634
2635 if (eicr & IXGBE_EICR_LSC)
2636 ixgbe_check_lsc(adapter);
2637
2638 switch (hw->mac.type) {
2639 case ixgbe_mac_82599EB:
2640 ixgbe_check_sfp_event(adapter, eicr);
2641 /* Fall through */
2642 case ixgbe_mac_X540:
2643 if (eicr & IXGBE_EICR_ECC)
2644 e_info(link, "Received unrecoverable ECC err, please "
2645 "reboot\n");
2646 ixgbe_check_overtemp_event(adapter, eicr);
2647 break;
2648 default:
2649 break;
2650 }
2651
2652 ixgbe_check_fan_failure(adapter, eicr);
2653 #ifdef CONFIG_IXGBE_PTP
2654 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2655 ixgbe_ptp_check_pps_event(adapter, eicr);
2656 #endif
2657
2658 /* would disable interrupts here but EIAM disabled it */
2659 napi_schedule(&q_vector->napi);
2660
2661 /*
2662 * re-enable link(maybe) and non-queue interrupts, no flush.
2663 * ixgbe_poll will re-enable the queue interrupts
2664 */
2665 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2666 ixgbe_irq_enable(adapter, false, false);
2667
2668 return IRQ_HANDLED;
2669 }
2670
2671 /**
2672 * ixgbe_request_irq - initialize interrupts
2673 * @adapter: board private structure
2674 *
2675 * Attempts to configure interrupts using the best available
2676 * capabilities of the hardware and kernel.
2677 **/
2678 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2679 {
2680 struct net_device *netdev = adapter->netdev;
2681 int err;
2682
2683 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2684 err = ixgbe_request_msix_irqs(adapter);
2685 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2686 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2687 netdev->name, adapter);
2688 else
2689 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2690 netdev->name, adapter);
2691
2692 if (err)
2693 e_err(probe, "request_irq failed, Error %d\n", err);
2694
2695 return err;
2696 }
2697
2698 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2699 {
2700 int vector;
2701
2702 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2703 free_irq(adapter->pdev->irq, adapter);
2704 return;
2705 }
2706
2707 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2708 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2709 struct msix_entry *entry = &adapter->msix_entries[vector];
2710
2711 /* free only the irqs that were actually requested */
2712 if (!q_vector->rx.ring && !q_vector->tx.ring)
2713 continue;
2714
2715 /* clear the affinity_mask in the IRQ descriptor */
2716 irq_set_affinity_hint(entry->vector, NULL);
2717
2718 free_irq(entry->vector, q_vector);
2719 }
2720
2721 free_irq(adapter->msix_entries[vector++].vector, adapter);
2722 }
2723
2724 /**
2725 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2726 * @adapter: board private structure
2727 **/
2728 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2729 {
2730 switch (adapter->hw.mac.type) {
2731 case ixgbe_mac_82598EB:
2732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2733 break;
2734 case ixgbe_mac_82599EB:
2735 case ixgbe_mac_X540:
2736 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2737 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2738 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2739 break;
2740 default:
2741 break;
2742 }
2743 IXGBE_WRITE_FLUSH(&adapter->hw);
2744 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2745 int vector;
2746
2747 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2748 synchronize_irq(adapter->msix_entries[vector].vector);
2749
2750 synchronize_irq(adapter->msix_entries[vector++].vector);
2751 } else {
2752 synchronize_irq(adapter->pdev->irq);
2753 }
2754 }
2755
2756 /**
2757 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2758 *
2759 **/
2760 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2761 {
2762 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2763
2764 /* rx/tx vector */
2765 if (adapter->rx_itr_setting == 1)
2766 q_vector->itr = IXGBE_20K_ITR;
2767 else
2768 q_vector->itr = adapter->rx_itr_setting;
2769
2770 ixgbe_write_eitr(q_vector);
2771
2772 ixgbe_set_ivar(adapter, 0, 0, 0);
2773 ixgbe_set_ivar(adapter, 1, 0, 0);
2774
2775 e_info(hw, "Legacy interrupt IVAR setup done\n");
2776 }
2777
2778 /**
2779 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2780 * @adapter: board private structure
2781 * @ring: structure containing ring specific data
2782 *
2783 * Configure the Tx descriptor ring after a reset.
2784 **/
2785 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2786 struct ixgbe_ring *ring)
2787 {
2788 struct ixgbe_hw *hw = &adapter->hw;
2789 u64 tdba = ring->dma;
2790 int wait_loop = 10;
2791 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2792 u8 reg_idx = ring->reg_idx;
2793
2794 /* disable queue to avoid issues while updating state */
2795 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2796 IXGBE_WRITE_FLUSH(hw);
2797
2798 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2799 (tdba & DMA_BIT_MASK(32)));
2800 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2801 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2802 ring->count * sizeof(union ixgbe_adv_tx_desc));
2803 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2804 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2805 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2806
2807 /*
2808 * set WTHRESH to encourage burst writeback, it should not be set
2809 * higher than 1 when ITR is 0 as it could cause false TX hangs
2810 *
2811 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2812 * to or less than the number of on chip descriptors, which is
2813 * currently 40.
2814 */
2815 if (!ring->q_vector || (ring->q_vector->itr < 8))
2816 txdctl |= (1 << 16); /* WTHRESH = 1 */
2817 else
2818 txdctl |= (8 << 16); /* WTHRESH = 8 */
2819
2820 /*
2821 * Setting PTHRESH to 32 both improves performance
2822 * and avoids a TX hang with DFP enabled
2823 */
2824 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2825 32; /* PTHRESH = 32 */
2826
2827 /* reinitialize flowdirector state */
2828 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2829 ring->atr_sample_rate = adapter->atr_sample_rate;
2830 ring->atr_count = 0;
2831 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2832 } else {
2833 ring->atr_sample_rate = 0;
2834 }
2835
2836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2837
2838 /* enable queue */
2839 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2840
2841 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2842 if (hw->mac.type == ixgbe_mac_82598EB &&
2843 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2844 return;
2845
2846 /* poll to verify queue is enabled */
2847 do {
2848 usleep_range(1000, 2000);
2849 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2850 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2851 if (!wait_loop)
2852 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2853 }
2854
2855 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2856 {
2857 struct ixgbe_hw *hw = &adapter->hw;
2858 u32 rttdcs, mtqc;
2859 u8 tcs = netdev_get_num_tc(adapter->netdev);
2860
2861 if (hw->mac.type == ixgbe_mac_82598EB)
2862 return;
2863
2864 /* disable the arbiter while setting MTQC */
2865 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2866 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2867 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2868
2869 /* set transmit pool layout */
2870 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2871 mtqc = IXGBE_MTQC_VT_ENA;
2872 if (tcs > 4)
2873 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2874 else if (tcs > 1)
2875 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2876 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2877 mtqc |= IXGBE_MTQC_32VF;
2878 else
2879 mtqc |= IXGBE_MTQC_64VF;
2880 } else {
2881 if (tcs > 4)
2882 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2883 else if (tcs > 1)
2884 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2885 else
2886 mtqc = IXGBE_MTQC_64Q_1PB;
2887 }
2888
2889 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2890
2891 /* Enable Security TX Buffer IFG for multiple pb */
2892 if (tcs) {
2893 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2894 sectx |= IXGBE_SECTX_DCB;
2895 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2896 }
2897
2898 /* re-enable the arbiter */
2899 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2900 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2901 }
2902
2903 /**
2904 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2905 * @adapter: board private structure
2906 *
2907 * Configure the Tx unit of the MAC after a reset.
2908 **/
2909 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2910 {
2911 struct ixgbe_hw *hw = &adapter->hw;
2912 u32 dmatxctl;
2913 u32 i;
2914
2915 ixgbe_setup_mtqc(adapter);
2916
2917 if (hw->mac.type != ixgbe_mac_82598EB) {
2918 /* DMATXCTL.EN must be before Tx queues are enabled */
2919 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2920 dmatxctl |= IXGBE_DMATXCTL_TE;
2921 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2922 }
2923
2924 /* Setup the HW Tx Head and Tail descriptor pointers */
2925 for (i = 0; i < adapter->num_tx_queues; i++)
2926 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2927 }
2928
2929 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2930 struct ixgbe_ring *ring)
2931 {
2932 struct ixgbe_hw *hw = &adapter->hw;
2933 u8 reg_idx = ring->reg_idx;
2934 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2935
2936 srrctl |= IXGBE_SRRCTL_DROP_EN;
2937
2938 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2939 }
2940
2941 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2942 struct ixgbe_ring *ring)
2943 {
2944 struct ixgbe_hw *hw = &adapter->hw;
2945 u8 reg_idx = ring->reg_idx;
2946 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2947
2948 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2949
2950 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2951 }
2952
2953 #ifdef CONFIG_IXGBE_DCB
2954 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2955 #else
2956 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2957 #endif
2958 {
2959 int i;
2960 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2961
2962 if (adapter->ixgbe_ieee_pfc)
2963 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2964
2965 /*
2966 * We should set the drop enable bit if:
2967 * SR-IOV is enabled
2968 * or
2969 * Number of Rx queues > 1 and flow control is disabled
2970 *
2971 * This allows us to avoid head of line blocking for security
2972 * and performance reasons.
2973 */
2974 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2975 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2976 for (i = 0; i < adapter->num_rx_queues; i++)
2977 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2978 } else {
2979 for (i = 0; i < adapter->num_rx_queues; i++)
2980 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2981 }
2982 }
2983
2984 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2985
2986 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2987 struct ixgbe_ring *rx_ring)
2988 {
2989 struct ixgbe_hw *hw = &adapter->hw;
2990 u32 srrctl;
2991 u8 reg_idx = rx_ring->reg_idx;
2992
2993 if (hw->mac.type == ixgbe_mac_82598EB) {
2994 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2995
2996 /*
2997 * if VMDq is not active we must program one srrctl register
2998 * per RSS queue since we have enabled RDRXCTL.MVMEN
2999 */
3000 reg_idx &= mask;
3001 }
3002
3003 /* configure header buffer length, needed for RSC */
3004 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3005
3006 /* configure the packet buffer length */
3007 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3008
3009 /* configure descriptor type */
3010 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3011
3012 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3013 }
3014
3015 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3016 {
3017 struct ixgbe_hw *hw = &adapter->hw;
3018 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3019 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3020 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3021 u32 mrqc = 0, reta = 0;
3022 u32 rxcsum;
3023 int i, j;
3024 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3025
3026 /*
3027 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3028 * make full use of any rings they may have. We will use the
3029 * PSRTYPE register to control how many rings we use within the PF.
3030 */
3031 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3032 rss_i = 2;
3033
3034 /* Fill out hash function seeds */
3035 for (i = 0; i < 10; i++)
3036 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3037
3038 /* Fill out redirection table */
3039 for (i = 0, j = 0; i < 128; i++, j++) {
3040 if (j == rss_i)
3041 j = 0;
3042 /* reta = 4-byte sliding window of
3043 * 0x00..(indices-1)(indices-1)00..etc. */
3044 reta = (reta << 8) | (j * 0x11);
3045 if ((i & 3) == 3)
3046 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3047 }
3048
3049 /* Disable indicating checksum in descriptor, enables RSS hash */
3050 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3051 rxcsum |= IXGBE_RXCSUM_PCSD;
3052 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3053
3054 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3055 if (adapter->ring_feature[RING_F_RSS].mask)
3056 mrqc = IXGBE_MRQC_RSSEN;
3057 } else {
3058 u8 tcs = netdev_get_num_tc(adapter->netdev);
3059
3060 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3061 if (tcs > 4)
3062 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3063 else if (tcs > 1)
3064 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3065 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3066 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3067 else
3068 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3069 } else {
3070 if (tcs > 4)
3071 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3072 else if (tcs > 1)
3073 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3074 else
3075 mrqc = IXGBE_MRQC_RSSEN;
3076 }
3077 }
3078
3079 /* Perform hash on these packet types */
3080 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3081 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3082 IXGBE_MRQC_RSS_FIELD_IPV6 |
3083 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3084
3085 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3086 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3087 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3088 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3089
3090 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3091 }
3092
3093 /**
3094 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3095 * @adapter: address of board private structure
3096 * @index: index of ring to set
3097 **/
3098 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3099 struct ixgbe_ring *ring)
3100 {
3101 struct ixgbe_hw *hw = &adapter->hw;
3102 u32 rscctrl;
3103 u8 reg_idx = ring->reg_idx;
3104
3105 if (!ring_is_rsc_enabled(ring))
3106 return;
3107
3108 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3109 rscctrl |= IXGBE_RSCCTL_RSCEN;
3110 /*
3111 * we must limit the number of descriptors so that the
3112 * total size of max desc * buf_len is not greater
3113 * than 65536
3114 */
3115 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3116 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3117 }
3118
3119 #define IXGBE_MAX_RX_DESC_POLL 10
3120 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3121 struct ixgbe_ring *ring)
3122 {
3123 struct ixgbe_hw *hw = &adapter->hw;
3124 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3125 u32 rxdctl;
3126 u8 reg_idx = ring->reg_idx;
3127
3128 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3129 if (hw->mac.type == ixgbe_mac_82598EB &&
3130 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3131 return;
3132
3133 do {
3134 usleep_range(1000, 2000);
3135 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3136 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3137
3138 if (!wait_loop) {
3139 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3140 "the polling period\n", reg_idx);
3141 }
3142 }
3143
3144 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3145 struct ixgbe_ring *ring)
3146 {
3147 struct ixgbe_hw *hw = &adapter->hw;
3148 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3149 u32 rxdctl;
3150 u8 reg_idx = ring->reg_idx;
3151
3152 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3153 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3154
3155 /* write value back with RXDCTL.ENABLE bit cleared */
3156 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3157
3158 if (hw->mac.type == ixgbe_mac_82598EB &&
3159 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3160 return;
3161
3162 /* the hardware may take up to 100us to really disable the rx queue */
3163 do {
3164 udelay(10);
3165 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3166 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3167
3168 if (!wait_loop) {
3169 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3170 "the polling period\n", reg_idx);
3171 }
3172 }
3173
3174 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3175 struct ixgbe_ring *ring)
3176 {
3177 struct ixgbe_hw *hw = &adapter->hw;
3178 u64 rdba = ring->dma;
3179 u32 rxdctl;
3180 u8 reg_idx = ring->reg_idx;
3181
3182 /* disable queue to avoid issues while updating state */
3183 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3184 ixgbe_disable_rx_queue(adapter, ring);
3185
3186 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3187 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3188 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3189 ring->count * sizeof(union ixgbe_adv_rx_desc));
3190 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3191 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3192 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3193
3194 ixgbe_configure_srrctl(adapter, ring);
3195 ixgbe_configure_rscctl(adapter, ring);
3196
3197 /* If operating in IOV mode set RLPML for X540 */
3198 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3199 hw->mac.type == ixgbe_mac_X540) {
3200 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3201 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3202 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3203 }
3204
3205 if (hw->mac.type == ixgbe_mac_82598EB) {
3206 /*
3207 * enable cache line friendly hardware writes:
3208 * PTHRESH=32 descriptors (half the internal cache),
3209 * this also removes ugly rx_no_buffer_count increment
3210 * HTHRESH=4 descriptors (to minimize latency on fetch)
3211 * WTHRESH=8 burst writeback up to two cache lines
3212 */
3213 rxdctl &= ~0x3FFFFF;
3214 rxdctl |= 0x080420;
3215 }
3216
3217 /* enable receive descriptor ring */
3218 rxdctl |= IXGBE_RXDCTL_ENABLE;
3219 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3220
3221 ixgbe_rx_desc_queue_enable(adapter, ring);
3222 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3223 }
3224
3225 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3226 {
3227 struct ixgbe_hw *hw = &adapter->hw;
3228 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3229 int p;
3230
3231 /* PSRTYPE must be initialized in non 82598 adapters */
3232 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3233 IXGBE_PSRTYPE_UDPHDR |
3234 IXGBE_PSRTYPE_IPV4HDR |
3235 IXGBE_PSRTYPE_L2HDR |
3236 IXGBE_PSRTYPE_IPV6HDR;
3237
3238 if (hw->mac.type == ixgbe_mac_82598EB)
3239 return;
3240
3241 if (rss_i > 3)
3242 psrtype |= 2 << 29;
3243 else if (rss_i > 1)
3244 psrtype |= 1 << 29;
3245
3246 for (p = 0; p < adapter->num_rx_pools; p++)
3247 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3248 psrtype);
3249 }
3250
3251 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3252 {
3253 struct ixgbe_hw *hw = &adapter->hw;
3254 u32 reg_offset, vf_shift;
3255 u32 gcr_ext, vmdctl;
3256 int i;
3257
3258 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3259 return;
3260
3261 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3262 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3263 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3264 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3265 vmdctl |= IXGBE_VT_CTL_REPLEN;
3266 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3267
3268 vf_shift = VMDQ_P(0) % 32;
3269 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3270
3271 /* Enable only the PF's pool for Tx/Rx */
3272 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3273 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3274 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3275 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3276
3277 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3278 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3279
3280 /*
3281 * Set up VF register offsets for selected VT Mode,
3282 * i.e. 32 or 64 VFs for SR-IOV
3283 */
3284 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3285 case IXGBE_82599_VMDQ_8Q_MASK:
3286 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3287 break;
3288 case IXGBE_82599_VMDQ_4Q_MASK:
3289 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3290 break;
3291 default:
3292 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3293 break;
3294 }
3295
3296 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3297
3298
3299 /* Enable MAC Anti-Spoofing */
3300 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3301 adapter->num_vfs);
3302 /* For VFs that have spoof checking turned off */
3303 for (i = 0; i < adapter->num_vfs; i++) {
3304 if (!adapter->vfinfo[i].spoofchk_enabled)
3305 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3306 }
3307 }
3308
3309 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3310 {
3311 struct ixgbe_hw *hw = &adapter->hw;
3312 struct net_device *netdev = adapter->netdev;
3313 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3314 struct ixgbe_ring *rx_ring;
3315 int i;
3316 u32 mhadd, hlreg0;
3317
3318 #ifdef IXGBE_FCOE
3319 /* adjust max frame to be able to do baby jumbo for FCoE */
3320 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3321 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3322 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3323
3324 #endif /* IXGBE_FCOE */
3325
3326 /* adjust max frame to be at least the size of a standard frame */
3327 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3328 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3329
3330 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3331 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3332 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3333 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3334
3335 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3336 }
3337
3338 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3339 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3340 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3341 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3342
3343 /*
3344 * Setup the HW Rx Head and Tail Descriptor Pointers and
3345 * the Base and Length of the Rx Descriptor Ring
3346 */
3347 for (i = 0; i < adapter->num_rx_queues; i++) {
3348 rx_ring = adapter->rx_ring[i];
3349 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3350 set_ring_rsc_enabled(rx_ring);
3351 else
3352 clear_ring_rsc_enabled(rx_ring);
3353 }
3354 }
3355
3356 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3357 {
3358 struct ixgbe_hw *hw = &adapter->hw;
3359 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3360
3361 switch (hw->mac.type) {
3362 case ixgbe_mac_82598EB:
3363 /*
3364 * For VMDq support of different descriptor types or
3365 * buffer sizes through the use of multiple SRRCTL
3366 * registers, RDRXCTL.MVMEN must be set to 1
3367 *
3368 * also, the manual doesn't mention it clearly but DCA hints
3369 * will only use queue 0's tags unless this bit is set. Side
3370 * effects of setting this bit are only that SRRCTL must be
3371 * fully programmed [0..15]
3372 */
3373 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3374 break;
3375 case ixgbe_mac_82599EB:
3376 case ixgbe_mac_X540:
3377 /* Disable RSC for ACK packets */
3378 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3379 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3380 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3381 /* hardware requires some bits to be set by default */
3382 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3383 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3384 break;
3385 default:
3386 /* We should do nothing since we don't know this hardware */
3387 return;
3388 }
3389
3390 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3391 }
3392
3393 /**
3394 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3395 * @adapter: board private structure
3396 *
3397 * Configure the Rx unit of the MAC after a reset.
3398 **/
3399 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3400 {
3401 struct ixgbe_hw *hw = &adapter->hw;
3402 int i;
3403 u32 rxctrl;
3404
3405 /* disable receives while setting up the descriptors */
3406 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3407 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3408
3409 ixgbe_setup_psrtype(adapter);
3410 ixgbe_setup_rdrxctl(adapter);
3411
3412 /* Program registers for the distribution of queues */
3413 ixgbe_setup_mrqc(adapter);
3414
3415 /* set_rx_buffer_len must be called before ring initialization */
3416 ixgbe_set_rx_buffer_len(adapter);
3417
3418 /*
3419 * Setup the HW Rx Head and Tail Descriptor Pointers and
3420 * the Base and Length of the Rx Descriptor Ring
3421 */
3422 for (i = 0; i < adapter->num_rx_queues; i++)
3423 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3424
3425 /* disable drop enable for 82598 parts */
3426 if (hw->mac.type == ixgbe_mac_82598EB)
3427 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3428
3429 /* enable all receives */
3430 rxctrl |= IXGBE_RXCTRL_RXEN;
3431 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3432 }
3433
3434 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3435 {
3436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3437 struct ixgbe_hw *hw = &adapter->hw;
3438
3439 /* add VID to filter table */
3440 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3441 set_bit(vid, adapter->active_vlans);
3442
3443 return 0;
3444 }
3445
3446 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3447 {
3448 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3449 struct ixgbe_hw *hw = &adapter->hw;
3450
3451 /* remove VID from filter table */
3452 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3453 clear_bit(vid, adapter->active_vlans);
3454
3455 return 0;
3456 }
3457
3458 /**
3459 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3460 * @adapter: driver data
3461 */
3462 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3463 {
3464 struct ixgbe_hw *hw = &adapter->hw;
3465 u32 vlnctrl;
3466
3467 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3468 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3469 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3470 }
3471
3472 /**
3473 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3474 * @adapter: driver data
3475 */
3476 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3477 {
3478 struct ixgbe_hw *hw = &adapter->hw;
3479 u32 vlnctrl;
3480
3481 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3482 vlnctrl |= IXGBE_VLNCTRL_VFE;
3483 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3484 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3485 }
3486
3487 /**
3488 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3489 * @adapter: driver data
3490 */
3491 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3492 {
3493 struct ixgbe_hw *hw = &adapter->hw;
3494 u32 vlnctrl;
3495 int i, j;
3496
3497 switch (hw->mac.type) {
3498 case ixgbe_mac_82598EB:
3499 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3500 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3501 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3502 break;
3503 case ixgbe_mac_82599EB:
3504 case ixgbe_mac_X540:
3505 for (i = 0; i < adapter->num_rx_queues; i++) {
3506 j = adapter->rx_ring[i]->reg_idx;
3507 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3508 vlnctrl &= ~IXGBE_RXDCTL_VME;
3509 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3510 }
3511 break;
3512 default:
3513 break;
3514 }
3515 }
3516
3517 /**
3518 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3519 * @adapter: driver data
3520 */
3521 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3522 {
3523 struct ixgbe_hw *hw = &adapter->hw;
3524 u32 vlnctrl;
3525 int i, j;
3526
3527 switch (hw->mac.type) {
3528 case ixgbe_mac_82598EB:
3529 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3530 vlnctrl |= IXGBE_VLNCTRL_VME;
3531 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3532 break;
3533 case ixgbe_mac_82599EB:
3534 case ixgbe_mac_X540:
3535 for (i = 0; i < adapter->num_rx_queues; i++) {
3536 j = adapter->rx_ring[i]->reg_idx;
3537 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3538 vlnctrl |= IXGBE_RXDCTL_VME;
3539 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3540 }
3541 break;
3542 default:
3543 break;
3544 }
3545 }
3546
3547 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3548 {
3549 u16 vid;
3550
3551 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3552
3553 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3554 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3555 }
3556
3557 /**
3558 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3559 * @netdev: network interface device structure
3560 *
3561 * Writes unicast address list to the RAR table.
3562 * Returns: -ENOMEM on failure/insufficient address space
3563 * 0 on no addresses written
3564 * X on writing X addresses to the RAR table
3565 **/
3566 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3567 {
3568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3569 struct ixgbe_hw *hw = &adapter->hw;
3570 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3571 int count = 0;
3572
3573 /* In SR-IOV mode significantly less RAR entries are available */
3574 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3575 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3576
3577 /* return ENOMEM indicating insufficient memory for addresses */
3578 if (netdev_uc_count(netdev) > rar_entries)
3579 return -ENOMEM;
3580
3581 if (!netdev_uc_empty(netdev)) {
3582 struct netdev_hw_addr *ha;
3583 /* return error if we do not support writing to RAR table */
3584 if (!hw->mac.ops.set_rar)
3585 return -ENOMEM;
3586
3587 netdev_for_each_uc_addr(ha, netdev) {
3588 if (!rar_entries)
3589 break;
3590 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3591 VMDQ_P(0), IXGBE_RAH_AV);
3592 count++;
3593 }
3594 }
3595 /* write the addresses in reverse order to avoid write combining */
3596 for (; rar_entries > 0 ; rar_entries--)
3597 hw->mac.ops.clear_rar(hw, rar_entries);
3598
3599 return count;
3600 }
3601
3602 /**
3603 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3604 * @netdev: network interface device structure
3605 *
3606 * The set_rx_method entry point is called whenever the unicast/multicast
3607 * address list or the network interface flags are updated. This routine is
3608 * responsible for configuring the hardware for proper unicast, multicast and
3609 * promiscuous mode.
3610 **/
3611 void ixgbe_set_rx_mode(struct net_device *netdev)
3612 {
3613 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3614 struct ixgbe_hw *hw = &adapter->hw;
3615 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3616 int count;
3617
3618 /* Check for Promiscuous and All Multicast modes */
3619
3620 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3621
3622 /* set all bits that we expect to always be set */
3623 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3624 fctrl |= IXGBE_FCTRL_BAM;
3625 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3626 fctrl |= IXGBE_FCTRL_PMCF;
3627
3628 /* clear the bits we are changing the status of */
3629 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3630
3631 if (netdev->flags & IFF_PROMISC) {
3632 hw->addr_ctrl.user_set_promisc = true;
3633 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3634 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3635 /* don't hardware filter vlans in promisc mode */
3636 ixgbe_vlan_filter_disable(adapter);
3637 } else {
3638 if (netdev->flags & IFF_ALLMULTI) {
3639 fctrl |= IXGBE_FCTRL_MPE;
3640 vmolr |= IXGBE_VMOLR_MPE;
3641 } else {
3642 /*
3643 * Write addresses to the MTA, if the attempt fails
3644 * then we should just turn on promiscuous mode so
3645 * that we can at least receive multicast traffic
3646 */
3647 hw->mac.ops.update_mc_addr_list(hw, netdev);
3648 vmolr |= IXGBE_VMOLR_ROMPE;
3649 }
3650 ixgbe_vlan_filter_enable(adapter);
3651 hw->addr_ctrl.user_set_promisc = false;
3652 }
3653
3654 /*
3655 * Write addresses to available RAR registers, if there is not
3656 * sufficient space to store all the addresses then enable
3657 * unicast promiscuous mode
3658 */
3659 count = ixgbe_write_uc_addr_list(netdev);
3660 if (count < 0) {
3661 fctrl |= IXGBE_FCTRL_UPE;
3662 vmolr |= IXGBE_VMOLR_ROPE;
3663 }
3664
3665 if (adapter->num_vfs)
3666 ixgbe_restore_vf_multicasts(adapter);
3667
3668 if (hw->mac.type != ixgbe_mac_82598EB) {
3669 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3670 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3671 IXGBE_VMOLR_ROPE);
3672 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3673 }
3674
3675 /* This is useful for sniffing bad packets. */
3676 if (adapter->netdev->features & NETIF_F_RXALL) {
3677 /* UPE and MPE will be handled by normal PROMISC logic
3678 * in e1000e_set_rx_mode */
3679 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3680 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3681 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3682
3683 fctrl &= ~(IXGBE_FCTRL_DPF);
3684 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3685 }
3686
3687 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3688
3689 if (netdev->features & NETIF_F_HW_VLAN_RX)
3690 ixgbe_vlan_strip_enable(adapter);
3691 else
3692 ixgbe_vlan_strip_disable(adapter);
3693 }
3694
3695 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3696 {
3697 int q_idx;
3698
3699 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3700 napi_enable(&adapter->q_vector[q_idx]->napi);
3701 }
3702
3703 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3704 {
3705 int q_idx;
3706
3707 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3708 napi_disable(&adapter->q_vector[q_idx]->napi);
3709 }
3710
3711 #ifdef CONFIG_IXGBE_DCB
3712 /**
3713 * ixgbe_configure_dcb - Configure DCB hardware
3714 * @adapter: ixgbe adapter struct
3715 *
3716 * This is called by the driver on open to configure the DCB hardware.
3717 * This is also called by the gennetlink interface when reconfiguring
3718 * the DCB state.
3719 */
3720 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3721 {
3722 struct ixgbe_hw *hw = &adapter->hw;
3723 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3724
3725 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3726 if (hw->mac.type == ixgbe_mac_82598EB)
3727 netif_set_gso_max_size(adapter->netdev, 65536);
3728 return;
3729 }
3730
3731 if (hw->mac.type == ixgbe_mac_82598EB)
3732 netif_set_gso_max_size(adapter->netdev, 32768);
3733
3734 #ifdef IXGBE_FCOE
3735 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3736 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3737 #endif
3738
3739 /* reconfigure the hardware */
3740 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3741 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3742 DCB_TX_CONFIG);
3743 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3744 DCB_RX_CONFIG);
3745 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3746 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3747 ixgbe_dcb_hw_ets(&adapter->hw,
3748 adapter->ixgbe_ieee_ets,
3749 max_frame);
3750 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3751 adapter->ixgbe_ieee_pfc->pfc_en,
3752 adapter->ixgbe_ieee_ets->prio_tc);
3753 }
3754
3755 /* Enable RSS Hash per TC */
3756 if (hw->mac.type != ixgbe_mac_82598EB) {
3757 u32 msb = 0;
3758 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3759
3760 while (rss_i) {
3761 msb++;
3762 rss_i >>= 1;
3763 }
3764
3765 /* write msb to all 8 TCs in one write */
3766 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3767 }
3768 }
3769 #endif
3770
3771 /* Additional bittime to account for IXGBE framing */
3772 #define IXGBE_ETH_FRAMING 20
3773
3774 /**
3775 * ixgbe_hpbthresh - calculate high water mark for flow control
3776 *
3777 * @adapter: board private structure to calculate for
3778 * @pb: packet buffer to calculate
3779 */
3780 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3781 {
3782 struct ixgbe_hw *hw = &adapter->hw;
3783 struct net_device *dev = adapter->netdev;
3784 int link, tc, kb, marker;
3785 u32 dv_id, rx_pba;
3786
3787 /* Calculate max LAN frame size */
3788 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3789
3790 #ifdef IXGBE_FCOE
3791 /* FCoE traffic class uses FCOE jumbo frames */
3792 if ((dev->features & NETIF_F_FCOE_MTU) &&
3793 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3794 (pb == ixgbe_fcoe_get_tc(adapter)))
3795 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3796
3797 #endif
3798 /* Calculate delay value for device */
3799 switch (hw->mac.type) {
3800 case ixgbe_mac_X540:
3801 dv_id = IXGBE_DV_X540(link, tc);
3802 break;
3803 default:
3804 dv_id = IXGBE_DV(link, tc);
3805 break;
3806 }
3807
3808 /* Loopback switch introduces additional latency */
3809 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3810 dv_id += IXGBE_B2BT(tc);
3811
3812 /* Delay value is calculated in bit times convert to KB */
3813 kb = IXGBE_BT2KB(dv_id);
3814 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3815
3816 marker = rx_pba - kb;
3817
3818 /* It is possible that the packet buffer is not large enough
3819 * to provide required headroom. In this case throw an error
3820 * to user and a do the best we can.
3821 */
3822 if (marker < 0) {
3823 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3824 "headroom to support flow control."
3825 "Decrease MTU or number of traffic classes\n", pb);
3826 marker = tc + 1;
3827 }
3828
3829 return marker;
3830 }
3831
3832 /**
3833 * ixgbe_lpbthresh - calculate low water mark for for flow control
3834 *
3835 * @adapter: board private structure to calculate for
3836 * @pb: packet buffer to calculate
3837 */
3838 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3839 {
3840 struct ixgbe_hw *hw = &adapter->hw;
3841 struct net_device *dev = adapter->netdev;
3842 int tc;
3843 u32 dv_id;
3844
3845 /* Calculate max LAN frame size */
3846 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3847
3848 /* Calculate delay value for device */
3849 switch (hw->mac.type) {
3850 case ixgbe_mac_X540:
3851 dv_id = IXGBE_LOW_DV_X540(tc);
3852 break;
3853 default:
3854 dv_id = IXGBE_LOW_DV(tc);
3855 break;
3856 }
3857
3858 /* Delay value is calculated in bit times convert to KB */
3859 return IXGBE_BT2KB(dv_id);
3860 }
3861
3862 /*
3863 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3864 */
3865 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3866 {
3867 struct ixgbe_hw *hw = &adapter->hw;
3868 int num_tc = netdev_get_num_tc(adapter->netdev);
3869 int i;
3870
3871 if (!num_tc)
3872 num_tc = 1;
3873
3874 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3875
3876 for (i = 0; i < num_tc; i++) {
3877 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3878
3879 /* Low water marks must not be larger than high water marks */
3880 if (hw->fc.low_water > hw->fc.high_water[i])
3881 hw->fc.low_water = 0;
3882 }
3883 }
3884
3885 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3886 {
3887 struct ixgbe_hw *hw = &adapter->hw;
3888 int hdrm;
3889 u8 tc = netdev_get_num_tc(adapter->netdev);
3890
3891 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3892 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3893 hdrm = 32 << adapter->fdir_pballoc;
3894 else
3895 hdrm = 0;
3896
3897 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3898 ixgbe_pbthresh_setup(adapter);
3899 }
3900
3901 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3902 {
3903 struct ixgbe_hw *hw = &adapter->hw;
3904 struct hlist_node *node, *node2;
3905 struct ixgbe_fdir_filter *filter;
3906
3907 spin_lock(&adapter->fdir_perfect_lock);
3908
3909 if (!hlist_empty(&adapter->fdir_filter_list))
3910 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3911
3912 hlist_for_each_entry_safe(filter, node, node2,
3913 &adapter->fdir_filter_list, fdir_node) {
3914 ixgbe_fdir_write_perfect_filter_82599(hw,
3915 &filter->filter,
3916 filter->sw_idx,
3917 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3918 IXGBE_FDIR_DROP_QUEUE :
3919 adapter->rx_ring[filter->action]->reg_idx);
3920 }
3921
3922 spin_unlock(&adapter->fdir_perfect_lock);
3923 }
3924
3925 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3926 {
3927 struct ixgbe_hw *hw = &adapter->hw;
3928
3929 ixgbe_configure_pb(adapter);
3930 #ifdef CONFIG_IXGBE_DCB
3931 ixgbe_configure_dcb(adapter);
3932 #endif
3933 /*
3934 * We must restore virtualization before VLANs or else
3935 * the VLVF registers will not be populated
3936 */
3937 ixgbe_configure_virtualization(adapter);
3938
3939 ixgbe_set_rx_mode(adapter->netdev);
3940 ixgbe_restore_vlan(adapter);
3941
3942 switch (hw->mac.type) {
3943 case ixgbe_mac_82599EB:
3944 case ixgbe_mac_X540:
3945 hw->mac.ops.disable_rx_buff(hw);
3946 break;
3947 default:
3948 break;
3949 }
3950
3951 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3952 ixgbe_init_fdir_signature_82599(&adapter->hw,
3953 adapter->fdir_pballoc);
3954 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3955 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3956 adapter->fdir_pballoc);
3957 ixgbe_fdir_filter_restore(adapter);
3958 }
3959
3960 switch (hw->mac.type) {
3961 case ixgbe_mac_82599EB:
3962 case ixgbe_mac_X540:
3963 hw->mac.ops.enable_rx_buff(hw);
3964 break;
3965 default:
3966 break;
3967 }
3968
3969 #ifdef IXGBE_FCOE
3970 /* configure FCoE L2 filters, redirection table, and Rx control */
3971 ixgbe_configure_fcoe(adapter);
3972
3973 #endif /* IXGBE_FCOE */
3974 ixgbe_configure_tx(adapter);
3975 ixgbe_configure_rx(adapter);
3976 }
3977
3978 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3979 {
3980 switch (hw->phy.type) {
3981 case ixgbe_phy_sfp_avago:
3982 case ixgbe_phy_sfp_ftl:
3983 case ixgbe_phy_sfp_intel:
3984 case ixgbe_phy_sfp_unknown:
3985 case ixgbe_phy_sfp_passive_tyco:
3986 case ixgbe_phy_sfp_passive_unknown:
3987 case ixgbe_phy_sfp_active_unknown:
3988 case ixgbe_phy_sfp_ftl_active:
3989 return true;
3990 case ixgbe_phy_nl:
3991 if (hw->mac.type == ixgbe_mac_82598EB)
3992 return true;
3993 default:
3994 return false;
3995 }
3996 }
3997
3998 /**
3999 * ixgbe_sfp_link_config - set up SFP+ link
4000 * @adapter: pointer to private adapter struct
4001 **/
4002 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4003 {
4004 /*
4005 * We are assuming the worst case scenario here, and that
4006 * is that an SFP was inserted/removed after the reset
4007 * but before SFP detection was enabled. As such the best
4008 * solution is to just start searching as soon as we start
4009 */
4010 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4011 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4012
4013 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4014 }
4015
4016 /**
4017 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4018 * @hw: pointer to private hardware struct
4019 *
4020 * Returns 0 on success, negative on failure
4021 **/
4022 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4023 {
4024 u32 autoneg;
4025 bool negotiation, link_up = false;
4026 u32 ret = IXGBE_ERR_LINK_SETUP;
4027
4028 if (hw->mac.ops.check_link)
4029 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
4030
4031 if (ret)
4032 goto link_cfg_out;
4033
4034 autoneg = hw->phy.autoneg_advertised;
4035 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4036 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4037 &negotiation);
4038 if (ret)
4039 goto link_cfg_out;
4040
4041 if (hw->mac.ops.setup_link)
4042 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
4043 link_cfg_out:
4044 return ret;
4045 }
4046
4047 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4048 {
4049 struct ixgbe_hw *hw = &adapter->hw;
4050 u32 gpie = 0;
4051
4052 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4053 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4054 IXGBE_GPIE_OCD;
4055 gpie |= IXGBE_GPIE_EIAME;
4056 /*
4057 * use EIAM to auto-mask when MSI-X interrupt is asserted
4058 * this saves a register write for every interrupt
4059 */
4060 switch (hw->mac.type) {
4061 case ixgbe_mac_82598EB:
4062 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4063 break;
4064 case ixgbe_mac_82599EB:
4065 case ixgbe_mac_X540:
4066 default:
4067 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4068 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4069 break;
4070 }
4071 } else {
4072 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4073 * specifically only auto mask tx and rx interrupts */
4074 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4075 }
4076
4077 /* XXX: to interrupt immediately for EICS writes, enable this */
4078 /* gpie |= IXGBE_GPIE_EIMEN; */
4079
4080 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4081 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4082
4083 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4084 case IXGBE_82599_VMDQ_8Q_MASK:
4085 gpie |= IXGBE_GPIE_VTMODE_16;
4086 break;
4087 case IXGBE_82599_VMDQ_4Q_MASK:
4088 gpie |= IXGBE_GPIE_VTMODE_32;
4089 break;
4090 default:
4091 gpie |= IXGBE_GPIE_VTMODE_64;
4092 break;
4093 }
4094 }
4095
4096 /* Enable Thermal over heat sensor interrupt */
4097 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4098 switch (adapter->hw.mac.type) {
4099 case ixgbe_mac_82599EB:
4100 gpie |= IXGBE_SDP0_GPIEN;
4101 break;
4102 case ixgbe_mac_X540:
4103 gpie |= IXGBE_EIMS_TS;
4104 break;
4105 default:
4106 break;
4107 }
4108 }
4109
4110 /* Enable fan failure interrupt */
4111 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4112 gpie |= IXGBE_SDP1_GPIEN;
4113
4114 if (hw->mac.type == ixgbe_mac_82599EB) {
4115 gpie |= IXGBE_SDP1_GPIEN;
4116 gpie |= IXGBE_SDP2_GPIEN;
4117 }
4118
4119 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4120 }
4121
4122 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4123 {
4124 struct ixgbe_hw *hw = &adapter->hw;
4125 int err;
4126 u32 ctrl_ext;
4127
4128 ixgbe_get_hw_control(adapter);
4129 ixgbe_setup_gpie(adapter);
4130
4131 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4132 ixgbe_configure_msix(adapter);
4133 else
4134 ixgbe_configure_msi_and_legacy(adapter);
4135
4136 /* enable the optics for 82599 SFP+ fiber */
4137 if (hw->mac.ops.enable_tx_laser)
4138 hw->mac.ops.enable_tx_laser(hw);
4139
4140 clear_bit(__IXGBE_DOWN, &adapter->state);
4141 ixgbe_napi_enable_all(adapter);
4142
4143 if (ixgbe_is_sfp(hw)) {
4144 ixgbe_sfp_link_config(adapter);
4145 } else {
4146 err = ixgbe_non_sfp_link_config(hw);
4147 if (err)
4148 e_err(probe, "link_config FAILED %d\n", err);
4149 }
4150
4151 /* clear any pending interrupts, may auto mask */
4152 IXGBE_READ_REG(hw, IXGBE_EICR);
4153 ixgbe_irq_enable(adapter, true, true);
4154
4155 /*
4156 * If this adapter has a fan, check to see if we had a failure
4157 * before we enabled the interrupt.
4158 */
4159 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4160 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4161 if (esdp & IXGBE_ESDP_SDP1)
4162 e_crit(drv, "Fan has stopped, replace the adapter\n");
4163 }
4164
4165 /* enable transmits */
4166 netif_tx_start_all_queues(adapter->netdev);
4167
4168 /* bring the link up in the watchdog, this could race with our first
4169 * link up interrupt but shouldn't be a problem */
4170 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4171 adapter->link_check_timeout = jiffies;
4172 mod_timer(&adapter->service_timer, jiffies);
4173
4174 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4175 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4176 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4177 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4178 }
4179
4180 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4181 {
4182 WARN_ON(in_interrupt());
4183 /* put off any impending NetWatchDogTimeout */
4184 adapter->netdev->trans_start = jiffies;
4185
4186 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4187 usleep_range(1000, 2000);
4188 ixgbe_down(adapter);
4189 /*
4190 * If SR-IOV enabled then wait a bit before bringing the adapter
4191 * back up to give the VFs time to respond to the reset. The
4192 * two second wait is based upon the watchdog timer cycle in
4193 * the VF driver.
4194 */
4195 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4196 msleep(2000);
4197 ixgbe_up(adapter);
4198 clear_bit(__IXGBE_RESETTING, &adapter->state);
4199 }
4200
4201 void ixgbe_up(struct ixgbe_adapter *adapter)
4202 {
4203 /* hardware has been reset, we need to reload some things */
4204 ixgbe_configure(adapter);
4205
4206 ixgbe_up_complete(adapter);
4207 }
4208
4209 void ixgbe_reset(struct ixgbe_adapter *adapter)
4210 {
4211 struct ixgbe_hw *hw = &adapter->hw;
4212 int err;
4213
4214 /* lock SFP init bit to prevent race conditions with the watchdog */
4215 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4216 usleep_range(1000, 2000);
4217
4218 /* clear all SFP and link config related flags while holding SFP_INIT */
4219 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4220 IXGBE_FLAG2_SFP_NEEDS_RESET);
4221 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4222
4223 err = hw->mac.ops.init_hw(hw);
4224 switch (err) {
4225 case 0:
4226 case IXGBE_ERR_SFP_NOT_PRESENT:
4227 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4228 break;
4229 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4230 e_dev_err("master disable timed out\n");
4231 break;
4232 case IXGBE_ERR_EEPROM_VERSION:
4233 /* We are running on a pre-production device, log a warning */
4234 e_dev_warn("This device is a pre-production adapter/LOM. "
4235 "Please be aware there may be issues associated with "
4236 "your hardware. If you are experiencing problems "
4237 "please contact your Intel or hardware "
4238 "representative who provided you with this "
4239 "hardware.\n");
4240 break;
4241 default:
4242 e_dev_err("Hardware Error: %d\n", err);
4243 }
4244
4245 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4246
4247 /* reprogram the RAR[0] in case user changed it. */
4248 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4249
4250 /* update SAN MAC vmdq pool selection */
4251 if (hw->mac.san_mac_rar_index)
4252 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4253
4254 #ifdef CONFIG_IXGBE_PTP
4255 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4256 ixgbe_ptp_reset(adapter);
4257 #endif
4258 }
4259
4260 /**
4261 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4262 * @rx_ring: ring to free buffers from
4263 **/
4264 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4265 {
4266 struct device *dev = rx_ring->dev;
4267 unsigned long size;
4268 u16 i;
4269
4270 /* ring already cleared, nothing to do */
4271 if (!rx_ring->rx_buffer_info)
4272 return;
4273
4274 /* Free all the Rx ring sk_buffs */
4275 for (i = 0; i < rx_ring->count; i++) {
4276 struct ixgbe_rx_buffer *rx_buffer;
4277
4278 rx_buffer = &rx_ring->rx_buffer_info[i];
4279 if (rx_buffer->skb) {
4280 struct sk_buff *skb = rx_buffer->skb;
4281 if (IXGBE_CB(skb)->page_released) {
4282 dma_unmap_page(dev,
4283 IXGBE_CB(skb)->dma,
4284 ixgbe_rx_bufsz(rx_ring),
4285 DMA_FROM_DEVICE);
4286 IXGBE_CB(skb)->page_released = false;
4287 }
4288 dev_kfree_skb(skb);
4289 }
4290 rx_buffer->skb = NULL;
4291 if (rx_buffer->dma)
4292 dma_unmap_page(dev, rx_buffer->dma,
4293 ixgbe_rx_pg_size(rx_ring),
4294 DMA_FROM_DEVICE);
4295 rx_buffer->dma = 0;
4296 if (rx_buffer->page)
4297 __free_pages(rx_buffer->page,
4298 ixgbe_rx_pg_order(rx_ring));
4299 rx_buffer->page = NULL;
4300 }
4301
4302 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4303 memset(rx_ring->rx_buffer_info, 0, size);
4304
4305 /* Zero out the descriptor ring */
4306 memset(rx_ring->desc, 0, rx_ring->size);
4307
4308 rx_ring->next_to_alloc = 0;
4309 rx_ring->next_to_clean = 0;
4310 rx_ring->next_to_use = 0;
4311 }
4312
4313 /**
4314 * ixgbe_clean_tx_ring - Free Tx Buffers
4315 * @tx_ring: ring to be cleaned
4316 **/
4317 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4318 {
4319 struct ixgbe_tx_buffer *tx_buffer_info;
4320 unsigned long size;
4321 u16 i;
4322
4323 /* ring already cleared, nothing to do */
4324 if (!tx_ring->tx_buffer_info)
4325 return;
4326
4327 /* Free all the Tx ring sk_buffs */
4328 for (i = 0; i < tx_ring->count; i++) {
4329 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4330 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4331 }
4332
4333 netdev_tx_reset_queue(txring_txq(tx_ring));
4334
4335 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4336 memset(tx_ring->tx_buffer_info, 0, size);
4337
4338 /* Zero out the descriptor ring */
4339 memset(tx_ring->desc, 0, tx_ring->size);
4340
4341 tx_ring->next_to_use = 0;
4342 tx_ring->next_to_clean = 0;
4343 }
4344
4345 /**
4346 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4347 * @adapter: board private structure
4348 **/
4349 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4350 {
4351 int i;
4352
4353 for (i = 0; i < adapter->num_rx_queues; i++)
4354 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4355 }
4356
4357 /**
4358 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4359 * @adapter: board private structure
4360 **/
4361 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4362 {
4363 int i;
4364
4365 for (i = 0; i < adapter->num_tx_queues; i++)
4366 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4367 }
4368
4369 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4370 {
4371 struct hlist_node *node, *node2;
4372 struct ixgbe_fdir_filter *filter;
4373
4374 spin_lock(&adapter->fdir_perfect_lock);
4375
4376 hlist_for_each_entry_safe(filter, node, node2,
4377 &adapter->fdir_filter_list, fdir_node) {
4378 hlist_del(&filter->fdir_node);
4379 kfree(filter);
4380 }
4381 adapter->fdir_filter_count = 0;
4382
4383 spin_unlock(&adapter->fdir_perfect_lock);
4384 }
4385
4386 void ixgbe_down(struct ixgbe_adapter *adapter)
4387 {
4388 struct net_device *netdev = adapter->netdev;
4389 struct ixgbe_hw *hw = &adapter->hw;
4390 u32 rxctrl;
4391 int i;
4392
4393 /* signal that we are down to the interrupt handler */
4394 set_bit(__IXGBE_DOWN, &adapter->state);
4395
4396 /* disable receives */
4397 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4398 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4399
4400 /* disable all enabled rx queues */
4401 for (i = 0; i < adapter->num_rx_queues; i++)
4402 /* this call also flushes the previous write */
4403 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4404
4405 usleep_range(10000, 20000);
4406
4407 netif_tx_stop_all_queues(netdev);
4408
4409 /* call carrier off first to avoid false dev_watchdog timeouts */
4410 netif_carrier_off(netdev);
4411 netif_tx_disable(netdev);
4412
4413 ixgbe_irq_disable(adapter);
4414
4415 ixgbe_napi_disable_all(adapter);
4416
4417 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4418 IXGBE_FLAG2_RESET_REQUESTED);
4419 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4420
4421 del_timer_sync(&adapter->service_timer);
4422
4423 if (adapter->num_vfs) {
4424 /* Clear EITR Select mapping */
4425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4426
4427 /* Mark all the VFs as inactive */
4428 for (i = 0 ; i < adapter->num_vfs; i++)
4429 adapter->vfinfo[i].clear_to_send = false;
4430
4431 /* ping all the active vfs to let them know we are going down */
4432 ixgbe_ping_all_vfs(adapter);
4433
4434 /* Disable all VFTE/VFRE TX/RX */
4435 ixgbe_disable_tx_rx(adapter);
4436 }
4437
4438 /* disable transmits in the hardware now that interrupts are off */
4439 for (i = 0; i < adapter->num_tx_queues; i++) {
4440 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4441 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4442 }
4443
4444 /* Disable the Tx DMA engine on 82599 and X540 */
4445 switch (hw->mac.type) {
4446 case ixgbe_mac_82599EB:
4447 case ixgbe_mac_X540:
4448 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4449 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4450 ~IXGBE_DMATXCTL_TE));
4451 break;
4452 default:
4453 break;
4454 }
4455
4456 if (!pci_channel_offline(adapter->pdev))
4457 ixgbe_reset(adapter);
4458
4459 /* power down the optics for 82599 SFP+ fiber */
4460 if (hw->mac.ops.disable_tx_laser)
4461 hw->mac.ops.disable_tx_laser(hw);
4462
4463 ixgbe_clean_all_tx_rings(adapter);
4464 ixgbe_clean_all_rx_rings(adapter);
4465
4466 #ifdef CONFIG_IXGBE_DCA
4467 /* since we reset the hardware DCA settings were cleared */
4468 ixgbe_setup_dca(adapter);
4469 #endif
4470 }
4471
4472 /**
4473 * ixgbe_tx_timeout - Respond to a Tx Hang
4474 * @netdev: network interface device structure
4475 **/
4476 static void ixgbe_tx_timeout(struct net_device *netdev)
4477 {
4478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4479
4480 /* Do the reset outside of interrupt context */
4481 ixgbe_tx_timeout_reset(adapter);
4482 }
4483
4484 /**
4485 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4486 * @adapter: board private structure to initialize
4487 *
4488 * ixgbe_sw_init initializes the Adapter private data structure.
4489 * Fields are initialized based on PCI device information and
4490 * OS network device settings (MTU size).
4491 **/
4492 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4493 {
4494 struct ixgbe_hw *hw = &adapter->hw;
4495 struct pci_dev *pdev = adapter->pdev;
4496 unsigned int rss;
4497 #ifdef CONFIG_IXGBE_DCB
4498 int j;
4499 struct tc_configuration *tc;
4500 #endif
4501
4502 /* PCI config space info */
4503
4504 hw->vendor_id = pdev->vendor;
4505 hw->device_id = pdev->device;
4506 hw->revision_id = pdev->revision;
4507 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4508 hw->subsystem_device_id = pdev->subsystem_device;
4509
4510 /* Set capability flags */
4511 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4512 adapter->ring_feature[RING_F_RSS].limit = rss;
4513 switch (hw->mac.type) {
4514 case ixgbe_mac_82598EB:
4515 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4516 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4517 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4518 break;
4519 case ixgbe_mac_X540:
4520 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4521 case ixgbe_mac_82599EB:
4522 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4523 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4524 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4525 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4526 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4527 /* Flow Director hash filters enabled */
4528 adapter->atr_sample_rate = 20;
4529 adapter->ring_feature[RING_F_FDIR].limit =
4530 IXGBE_MAX_FDIR_INDICES;
4531 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4532 #ifdef IXGBE_FCOE
4533 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4534 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4535 #ifdef CONFIG_IXGBE_DCB
4536 /* Default traffic class to use for FCoE */
4537 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4538 #endif
4539 #endif /* IXGBE_FCOE */
4540 break;
4541 default:
4542 break;
4543 }
4544
4545 #ifdef IXGBE_FCOE
4546 /* FCoE support exists, always init the FCoE lock */
4547 spin_lock_init(&adapter->fcoe.lock);
4548
4549 #endif
4550 /* n-tuple support exists, always init our spinlock */
4551 spin_lock_init(&adapter->fdir_perfect_lock);
4552
4553 #ifdef CONFIG_IXGBE_DCB
4554 switch (hw->mac.type) {
4555 case ixgbe_mac_X540:
4556 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4557 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4558 break;
4559 default:
4560 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4561 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4562 break;
4563 }
4564
4565 /* Configure DCB traffic classes */
4566 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4567 tc = &adapter->dcb_cfg.tc_config[j];
4568 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4569 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4570 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4571 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4572 tc->dcb_pfc = pfc_disabled;
4573 }
4574
4575 /* Initialize default user to priority mapping, UPx->TC0 */
4576 tc = &adapter->dcb_cfg.tc_config[0];
4577 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4578 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4579
4580 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4581 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4582 adapter->dcb_cfg.pfc_mode_enable = false;
4583 adapter->dcb_set_bitmap = 0x00;
4584 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4585 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4586 sizeof(adapter->temp_dcb_cfg));
4587
4588 #endif
4589
4590 /* default flow control settings */
4591 hw->fc.requested_mode = ixgbe_fc_full;
4592 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4593 ixgbe_pbthresh_setup(adapter);
4594 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4595 hw->fc.send_xon = true;
4596 hw->fc.disable_fc_autoneg = false;
4597
4598 #ifdef CONFIG_PCI_IOV
4599 /* assign number of SR-IOV VFs */
4600 if (hw->mac.type != ixgbe_mac_82598EB)
4601 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4602
4603 #endif
4604 /* enable itr by default in dynamic mode */
4605 adapter->rx_itr_setting = 1;
4606 adapter->tx_itr_setting = 1;
4607
4608 /* set default ring sizes */
4609 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4610 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4611
4612 /* set default work limits */
4613 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4614
4615 /* initialize eeprom parameters */
4616 if (ixgbe_init_eeprom_params_generic(hw)) {
4617 e_dev_err("EEPROM initialization failed\n");
4618 return -EIO;
4619 }
4620
4621 set_bit(__IXGBE_DOWN, &adapter->state);
4622
4623 return 0;
4624 }
4625
4626 /**
4627 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4628 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4629 *
4630 * Return 0 on success, negative on failure
4631 **/
4632 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4633 {
4634 struct device *dev = tx_ring->dev;
4635 int orig_node = dev_to_node(dev);
4636 int numa_node = -1;
4637 int size;
4638
4639 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4640
4641 if (tx_ring->q_vector)
4642 numa_node = tx_ring->q_vector->numa_node;
4643
4644 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4645 if (!tx_ring->tx_buffer_info)
4646 tx_ring->tx_buffer_info = vzalloc(size);
4647 if (!tx_ring->tx_buffer_info)
4648 goto err;
4649
4650 /* round up to nearest 4K */
4651 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4652 tx_ring->size = ALIGN(tx_ring->size, 4096);
4653
4654 set_dev_node(dev, numa_node);
4655 tx_ring->desc = dma_alloc_coherent(dev,
4656 tx_ring->size,
4657 &tx_ring->dma,
4658 GFP_KERNEL);
4659 set_dev_node(dev, orig_node);
4660 if (!tx_ring->desc)
4661 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4662 &tx_ring->dma, GFP_KERNEL);
4663 if (!tx_ring->desc)
4664 goto err;
4665
4666 tx_ring->next_to_use = 0;
4667 tx_ring->next_to_clean = 0;
4668 return 0;
4669
4670 err:
4671 vfree(tx_ring->tx_buffer_info);
4672 tx_ring->tx_buffer_info = NULL;
4673 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4674 return -ENOMEM;
4675 }
4676
4677 /**
4678 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4679 * @adapter: board private structure
4680 *
4681 * If this function returns with an error, then it's possible one or
4682 * more of the rings is populated (while the rest are not). It is the
4683 * callers duty to clean those orphaned rings.
4684 *
4685 * Return 0 on success, negative on failure
4686 **/
4687 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4688 {
4689 int i, err = 0;
4690
4691 for (i = 0; i < adapter->num_tx_queues; i++) {
4692 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4693 if (!err)
4694 continue;
4695
4696 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4697 goto err_setup_tx;
4698 }
4699
4700 return 0;
4701 err_setup_tx:
4702 /* rewind the index freeing the rings as we go */
4703 while (i--)
4704 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4705 return err;
4706 }
4707
4708 /**
4709 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4710 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4711 *
4712 * Returns 0 on success, negative on failure
4713 **/
4714 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4715 {
4716 struct device *dev = rx_ring->dev;
4717 int orig_node = dev_to_node(dev);
4718 int numa_node = -1;
4719 int size;
4720
4721 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4722
4723 if (rx_ring->q_vector)
4724 numa_node = rx_ring->q_vector->numa_node;
4725
4726 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4727 if (!rx_ring->rx_buffer_info)
4728 rx_ring->rx_buffer_info = vzalloc(size);
4729 if (!rx_ring->rx_buffer_info)
4730 goto err;
4731
4732 /* Round up to nearest 4K */
4733 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4734 rx_ring->size = ALIGN(rx_ring->size, 4096);
4735
4736 set_dev_node(dev, numa_node);
4737 rx_ring->desc = dma_alloc_coherent(dev,
4738 rx_ring->size,
4739 &rx_ring->dma,
4740 GFP_KERNEL);
4741 set_dev_node(dev, orig_node);
4742 if (!rx_ring->desc)
4743 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4744 &rx_ring->dma, GFP_KERNEL);
4745 if (!rx_ring->desc)
4746 goto err;
4747
4748 rx_ring->next_to_clean = 0;
4749 rx_ring->next_to_use = 0;
4750
4751 return 0;
4752 err:
4753 vfree(rx_ring->rx_buffer_info);
4754 rx_ring->rx_buffer_info = NULL;
4755 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4756 return -ENOMEM;
4757 }
4758
4759 /**
4760 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4761 * @adapter: board private structure
4762 *
4763 * If this function returns with an error, then it's possible one or
4764 * more of the rings is populated (while the rest are not). It is the
4765 * callers duty to clean those orphaned rings.
4766 *
4767 * Return 0 on success, negative on failure
4768 **/
4769 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4770 {
4771 int i, err = 0;
4772
4773 for (i = 0; i < adapter->num_rx_queues; i++) {
4774 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4775 if (!err)
4776 continue;
4777
4778 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4779 goto err_setup_rx;
4780 }
4781
4782 #ifdef IXGBE_FCOE
4783 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4784 if (!err)
4785 #endif
4786 return 0;
4787 err_setup_rx:
4788 /* rewind the index freeing the rings as we go */
4789 while (i--)
4790 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4791 return err;
4792 }
4793
4794 /**
4795 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4796 * @tx_ring: Tx descriptor ring for a specific queue
4797 *
4798 * Free all transmit software resources
4799 **/
4800 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4801 {
4802 ixgbe_clean_tx_ring(tx_ring);
4803
4804 vfree(tx_ring->tx_buffer_info);
4805 tx_ring->tx_buffer_info = NULL;
4806
4807 /* if not set, then don't free */
4808 if (!tx_ring->desc)
4809 return;
4810
4811 dma_free_coherent(tx_ring->dev, tx_ring->size,
4812 tx_ring->desc, tx_ring->dma);
4813
4814 tx_ring->desc = NULL;
4815 }
4816
4817 /**
4818 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4819 * @adapter: board private structure
4820 *
4821 * Free all transmit software resources
4822 **/
4823 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4824 {
4825 int i;
4826
4827 for (i = 0; i < adapter->num_tx_queues; i++)
4828 if (adapter->tx_ring[i]->desc)
4829 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4830 }
4831
4832 /**
4833 * ixgbe_free_rx_resources - Free Rx Resources
4834 * @rx_ring: ring to clean the resources from
4835 *
4836 * Free all receive software resources
4837 **/
4838 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4839 {
4840 ixgbe_clean_rx_ring(rx_ring);
4841
4842 vfree(rx_ring->rx_buffer_info);
4843 rx_ring->rx_buffer_info = NULL;
4844
4845 /* if not set, then don't free */
4846 if (!rx_ring->desc)
4847 return;
4848
4849 dma_free_coherent(rx_ring->dev, rx_ring->size,
4850 rx_ring->desc, rx_ring->dma);
4851
4852 rx_ring->desc = NULL;
4853 }
4854
4855 /**
4856 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4857 * @adapter: board private structure
4858 *
4859 * Free all receive software resources
4860 **/
4861 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4862 {
4863 int i;
4864
4865 #ifdef IXGBE_FCOE
4866 ixgbe_free_fcoe_ddp_resources(adapter);
4867
4868 #endif
4869 for (i = 0; i < adapter->num_rx_queues; i++)
4870 if (adapter->rx_ring[i]->desc)
4871 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4872 }
4873
4874 /**
4875 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4876 * @netdev: network interface device structure
4877 * @new_mtu: new value for maximum frame size
4878 *
4879 * Returns 0 on success, negative on failure
4880 **/
4881 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4882 {
4883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4884 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4885
4886 /* MTU < 68 is an error and causes problems on some kernels */
4887 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4888 return -EINVAL;
4889
4890 /*
4891 * For 82599EB we cannot allow legacy VFs to enable their receive
4892 * paths when MTU greater than 1500 is configured. So display a
4893 * warning that legacy VFs will be disabled.
4894 */
4895 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4896 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4897 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4898 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4899
4900 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4901
4902 /* must set new MTU before calling down or up */
4903 netdev->mtu = new_mtu;
4904
4905 if (netif_running(netdev))
4906 ixgbe_reinit_locked(adapter);
4907
4908 return 0;
4909 }
4910
4911 /**
4912 * ixgbe_open - Called when a network interface is made active
4913 * @netdev: network interface device structure
4914 *
4915 * Returns 0 on success, negative value on failure
4916 *
4917 * The open entry point is called when a network interface is made
4918 * active by the system (IFF_UP). At this point all resources needed
4919 * for transmit and receive operations are allocated, the interrupt
4920 * handler is registered with the OS, the watchdog timer is started,
4921 * and the stack is notified that the interface is ready.
4922 **/
4923 static int ixgbe_open(struct net_device *netdev)
4924 {
4925 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4926 int err;
4927
4928 /* disallow open during test */
4929 if (test_bit(__IXGBE_TESTING, &adapter->state))
4930 return -EBUSY;
4931
4932 netif_carrier_off(netdev);
4933
4934 /* allocate transmit descriptors */
4935 err = ixgbe_setup_all_tx_resources(adapter);
4936 if (err)
4937 goto err_setup_tx;
4938
4939 /* allocate receive descriptors */
4940 err = ixgbe_setup_all_rx_resources(adapter);
4941 if (err)
4942 goto err_setup_rx;
4943
4944 ixgbe_configure(adapter);
4945
4946 err = ixgbe_request_irq(adapter);
4947 if (err)
4948 goto err_req_irq;
4949
4950 /* Notify the stack of the actual queue counts. */
4951 err = netif_set_real_num_tx_queues(netdev,
4952 adapter->num_rx_pools > 1 ? 1 :
4953 adapter->num_tx_queues);
4954 if (err)
4955 goto err_set_queues;
4956
4957
4958 err = netif_set_real_num_rx_queues(netdev,
4959 adapter->num_rx_pools > 1 ? 1 :
4960 adapter->num_rx_queues);
4961 if (err)
4962 goto err_set_queues;
4963
4964 #ifdef CONFIG_IXGBE_PTP
4965 ixgbe_ptp_init(adapter);
4966 #endif /* CONFIG_IXGBE_PTP*/
4967
4968 ixgbe_up_complete(adapter);
4969
4970 return 0;
4971
4972 err_set_queues:
4973 ixgbe_free_irq(adapter);
4974 err_req_irq:
4975 ixgbe_free_all_rx_resources(adapter);
4976 err_setup_rx:
4977 ixgbe_free_all_tx_resources(adapter);
4978 err_setup_tx:
4979 ixgbe_reset(adapter);
4980
4981 return err;
4982 }
4983
4984 /**
4985 * ixgbe_close - Disables a network interface
4986 * @netdev: network interface device structure
4987 *
4988 * Returns 0, this is not allowed to fail
4989 *
4990 * The close entry point is called when an interface is de-activated
4991 * by the OS. The hardware is still under the drivers control, but
4992 * needs to be disabled. A global MAC reset is issued to stop the
4993 * hardware, and all transmit and receive resources are freed.
4994 **/
4995 static int ixgbe_close(struct net_device *netdev)
4996 {
4997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4998
4999 #ifdef CONFIG_IXGBE_PTP
5000 ixgbe_ptp_stop(adapter);
5001 #endif
5002
5003 ixgbe_down(adapter);
5004 ixgbe_free_irq(adapter);
5005
5006 ixgbe_fdir_filter_exit(adapter);
5007
5008 ixgbe_free_all_tx_resources(adapter);
5009 ixgbe_free_all_rx_resources(adapter);
5010
5011 ixgbe_release_hw_control(adapter);
5012
5013 return 0;
5014 }
5015
5016 #ifdef CONFIG_PM
5017 static int ixgbe_resume(struct pci_dev *pdev)
5018 {
5019 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5020 struct net_device *netdev = adapter->netdev;
5021 u32 err;
5022
5023 pci_set_power_state(pdev, PCI_D0);
5024 pci_restore_state(pdev);
5025 /*
5026 * pci_restore_state clears dev->state_saved so call
5027 * pci_save_state to restore it.
5028 */
5029 pci_save_state(pdev);
5030
5031 err = pci_enable_device_mem(pdev);
5032 if (err) {
5033 e_dev_err("Cannot enable PCI device from suspend\n");
5034 return err;
5035 }
5036 pci_set_master(pdev);
5037
5038 pci_wake_from_d3(pdev, false);
5039
5040 ixgbe_reset(adapter);
5041
5042 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5043
5044 rtnl_lock();
5045 err = ixgbe_init_interrupt_scheme(adapter);
5046 if (!err && netif_running(netdev))
5047 err = ixgbe_open(netdev);
5048
5049 rtnl_unlock();
5050
5051 if (err)
5052 return err;
5053
5054 netif_device_attach(netdev);
5055
5056 return 0;
5057 }
5058 #endif /* CONFIG_PM */
5059
5060 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5061 {
5062 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5063 struct net_device *netdev = adapter->netdev;
5064 struct ixgbe_hw *hw = &adapter->hw;
5065 u32 ctrl, fctrl;
5066 u32 wufc = adapter->wol;
5067 #ifdef CONFIG_PM
5068 int retval = 0;
5069 #endif
5070
5071 netif_device_detach(netdev);
5072
5073 if (netif_running(netdev)) {
5074 rtnl_lock();
5075 ixgbe_down(adapter);
5076 ixgbe_free_irq(adapter);
5077 ixgbe_free_all_tx_resources(adapter);
5078 ixgbe_free_all_rx_resources(adapter);
5079 rtnl_unlock();
5080 }
5081
5082 ixgbe_clear_interrupt_scheme(adapter);
5083
5084 #ifdef CONFIG_PM
5085 retval = pci_save_state(pdev);
5086 if (retval)
5087 return retval;
5088
5089 #endif
5090 if (wufc) {
5091 ixgbe_set_rx_mode(netdev);
5092
5093 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5094 if (hw->mac.ops.enable_tx_laser)
5095 hw->mac.ops.enable_tx_laser(hw);
5096
5097 /* turn on all-multi mode if wake on multicast is enabled */
5098 if (wufc & IXGBE_WUFC_MC) {
5099 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5100 fctrl |= IXGBE_FCTRL_MPE;
5101 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5102 }
5103
5104 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5105 ctrl |= IXGBE_CTRL_GIO_DIS;
5106 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5107
5108 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5109 } else {
5110 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5111 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5112 }
5113
5114 switch (hw->mac.type) {
5115 case ixgbe_mac_82598EB:
5116 pci_wake_from_d3(pdev, false);
5117 break;
5118 case ixgbe_mac_82599EB:
5119 case ixgbe_mac_X540:
5120 pci_wake_from_d3(pdev, !!wufc);
5121 break;
5122 default:
5123 break;
5124 }
5125
5126 *enable_wake = !!wufc;
5127
5128 ixgbe_release_hw_control(adapter);
5129
5130 pci_disable_device(pdev);
5131
5132 return 0;
5133 }
5134
5135 #ifdef CONFIG_PM
5136 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5137 {
5138 int retval;
5139 bool wake;
5140
5141 retval = __ixgbe_shutdown(pdev, &wake);
5142 if (retval)
5143 return retval;
5144
5145 if (wake) {
5146 pci_prepare_to_sleep(pdev);
5147 } else {
5148 pci_wake_from_d3(pdev, false);
5149 pci_set_power_state(pdev, PCI_D3hot);
5150 }
5151
5152 return 0;
5153 }
5154 #endif /* CONFIG_PM */
5155
5156 static void ixgbe_shutdown(struct pci_dev *pdev)
5157 {
5158 bool wake;
5159
5160 __ixgbe_shutdown(pdev, &wake);
5161
5162 if (system_state == SYSTEM_POWER_OFF) {
5163 pci_wake_from_d3(pdev, wake);
5164 pci_set_power_state(pdev, PCI_D3hot);
5165 }
5166 }
5167
5168 /**
5169 * ixgbe_update_stats - Update the board statistics counters.
5170 * @adapter: board private structure
5171 **/
5172 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5173 {
5174 struct net_device *netdev = adapter->netdev;
5175 struct ixgbe_hw *hw = &adapter->hw;
5176 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5177 u64 total_mpc = 0;
5178 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5179 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5180 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5181 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5182
5183 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5184 test_bit(__IXGBE_RESETTING, &adapter->state))
5185 return;
5186
5187 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5188 u64 rsc_count = 0;
5189 u64 rsc_flush = 0;
5190 for (i = 0; i < adapter->num_rx_queues; i++) {
5191 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5192 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5193 }
5194 adapter->rsc_total_count = rsc_count;
5195 adapter->rsc_total_flush = rsc_flush;
5196 }
5197
5198 for (i = 0; i < adapter->num_rx_queues; i++) {
5199 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5200 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5201 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5202 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5203 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5204 bytes += rx_ring->stats.bytes;
5205 packets += rx_ring->stats.packets;
5206 }
5207 adapter->non_eop_descs = non_eop_descs;
5208 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5209 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5210 adapter->hw_csum_rx_error = hw_csum_rx_error;
5211 netdev->stats.rx_bytes = bytes;
5212 netdev->stats.rx_packets = packets;
5213
5214 bytes = 0;
5215 packets = 0;
5216 /* gather some stats to the adapter struct that are per queue */
5217 for (i = 0; i < adapter->num_tx_queues; i++) {
5218 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5219 restart_queue += tx_ring->tx_stats.restart_queue;
5220 tx_busy += tx_ring->tx_stats.tx_busy;
5221 bytes += tx_ring->stats.bytes;
5222 packets += tx_ring->stats.packets;
5223 }
5224 adapter->restart_queue = restart_queue;
5225 adapter->tx_busy = tx_busy;
5226 netdev->stats.tx_bytes = bytes;
5227 netdev->stats.tx_packets = packets;
5228
5229 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5230
5231 /* 8 register reads */
5232 for (i = 0; i < 8; i++) {
5233 /* for packet buffers not used, the register should read 0 */
5234 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5235 missed_rx += mpc;
5236 hwstats->mpc[i] += mpc;
5237 total_mpc += hwstats->mpc[i];
5238 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5239 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5240 switch (hw->mac.type) {
5241 case ixgbe_mac_82598EB:
5242 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5243 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5244 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5245 hwstats->pxonrxc[i] +=
5246 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5247 break;
5248 case ixgbe_mac_82599EB:
5249 case ixgbe_mac_X540:
5250 hwstats->pxonrxc[i] +=
5251 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5252 break;
5253 default:
5254 break;
5255 }
5256 }
5257
5258 /*16 register reads */
5259 for (i = 0; i < 16; i++) {
5260 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5261 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5262 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5263 (hw->mac.type == ixgbe_mac_X540)) {
5264 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5265 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5266 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5267 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5268 }
5269 }
5270
5271 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5272 /* work around hardware counting issue */
5273 hwstats->gprc -= missed_rx;
5274
5275 ixgbe_update_xoff_received(adapter);
5276
5277 /* 82598 hardware only has a 32 bit counter in the high register */
5278 switch (hw->mac.type) {
5279 case ixgbe_mac_82598EB:
5280 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5281 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5282 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5283 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5284 break;
5285 case ixgbe_mac_X540:
5286 /* OS2BMC stats are X540 only*/
5287 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5288 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5289 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5290 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5291 case ixgbe_mac_82599EB:
5292 for (i = 0; i < 16; i++)
5293 adapter->hw_rx_no_dma_resources +=
5294 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5295 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5296 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5297 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5298 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5299 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5300 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5301 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5302 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5303 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5304 #ifdef IXGBE_FCOE
5305 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5306 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5307 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5308 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5309 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5310 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5311 /* Add up per cpu counters for total ddp aloc fail */
5312 if (adapter->fcoe.ddp_pool) {
5313 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5314 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5315 unsigned int cpu;
5316 u64 noddp = 0, noddp_ext_buff = 0;
5317 for_each_possible_cpu(cpu) {
5318 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5319 noddp += ddp_pool->noddp;
5320 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5321 }
5322 hwstats->fcoe_noddp = noddp;
5323 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5324 }
5325 #endif /* IXGBE_FCOE */
5326 break;
5327 default:
5328 break;
5329 }
5330 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5331 hwstats->bprc += bprc;
5332 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5333 if (hw->mac.type == ixgbe_mac_82598EB)
5334 hwstats->mprc -= bprc;
5335 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5336 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5337 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5338 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5339 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5340 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5341 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5342 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5343 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5344 hwstats->lxontxc += lxon;
5345 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5346 hwstats->lxofftxc += lxoff;
5347 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5348 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5349 /*
5350 * 82598 errata - tx of flow control packets is included in tx counters
5351 */
5352 xon_off_tot = lxon + lxoff;
5353 hwstats->gptc -= xon_off_tot;
5354 hwstats->mptc -= xon_off_tot;
5355 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5356 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5357 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5358 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5359 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5360 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5361 hwstats->ptc64 -= xon_off_tot;
5362 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5363 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5364 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5365 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5366 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5367 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5368
5369 /* Fill out the OS statistics structure */
5370 netdev->stats.multicast = hwstats->mprc;
5371
5372 /* Rx Errors */
5373 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5374 netdev->stats.rx_dropped = 0;
5375 netdev->stats.rx_length_errors = hwstats->rlec;
5376 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5377 netdev->stats.rx_missed_errors = total_mpc;
5378 }
5379
5380 /**
5381 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5382 * @adapter: pointer to the device adapter structure
5383 **/
5384 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5385 {
5386 struct ixgbe_hw *hw = &adapter->hw;
5387 int i;
5388
5389 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5390 return;
5391
5392 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5393
5394 /* if interface is down do nothing */
5395 if (test_bit(__IXGBE_DOWN, &adapter->state))
5396 return;
5397
5398 /* do nothing if we are not using signature filters */
5399 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5400 return;
5401
5402 adapter->fdir_overflow++;
5403
5404 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5405 for (i = 0; i < adapter->num_tx_queues; i++)
5406 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5407 &(adapter->tx_ring[i]->state));
5408 /* re-enable flow director interrupts */
5409 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5410 } else {
5411 e_err(probe, "failed to finish FDIR re-initialization, "
5412 "ignored adding FDIR ATR filters\n");
5413 }
5414 }
5415
5416 /**
5417 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5418 * @adapter: pointer to the device adapter structure
5419 *
5420 * This function serves two purposes. First it strobes the interrupt lines
5421 * in order to make certain interrupts are occurring. Secondly it sets the
5422 * bits needed to check for TX hangs. As a result we should immediately
5423 * determine if a hang has occurred.
5424 */
5425 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5426 {
5427 struct ixgbe_hw *hw = &adapter->hw;
5428 u64 eics = 0;
5429 int i;
5430
5431 /* If we're down or resetting, just bail */
5432 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5433 test_bit(__IXGBE_RESETTING, &adapter->state))
5434 return;
5435
5436 /* Force detection of hung controller */
5437 if (netif_carrier_ok(adapter->netdev)) {
5438 for (i = 0; i < adapter->num_tx_queues; i++)
5439 set_check_for_tx_hang(adapter->tx_ring[i]);
5440 }
5441
5442 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5443 /*
5444 * for legacy and MSI interrupts don't set any bits
5445 * that are enabled for EIAM, because this operation
5446 * would set *both* EIMS and EICS for any bit in EIAM
5447 */
5448 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5449 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5450 } else {
5451 /* get one bit for every active tx/rx interrupt vector */
5452 for (i = 0; i < adapter->num_q_vectors; i++) {
5453 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5454 if (qv->rx.ring || qv->tx.ring)
5455 eics |= ((u64)1 << i);
5456 }
5457 }
5458
5459 /* Cause software interrupt to ensure rings are cleaned */
5460 ixgbe_irq_rearm_queues(adapter, eics);
5461
5462 }
5463
5464 /**
5465 * ixgbe_watchdog_update_link - update the link status
5466 * @adapter: pointer to the device adapter structure
5467 * @link_speed: pointer to a u32 to store the link_speed
5468 **/
5469 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5470 {
5471 struct ixgbe_hw *hw = &adapter->hw;
5472 u32 link_speed = adapter->link_speed;
5473 bool link_up = adapter->link_up;
5474 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5475
5476 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5477 return;
5478
5479 if (hw->mac.ops.check_link) {
5480 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5481 } else {
5482 /* always assume link is up, if no check link function */
5483 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5484 link_up = true;
5485 }
5486
5487 if (adapter->ixgbe_ieee_pfc)
5488 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5489
5490 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5491 hw->mac.ops.fc_enable(hw);
5492 ixgbe_set_rx_drop_en(adapter);
5493 }
5494
5495 if (link_up ||
5496 time_after(jiffies, (adapter->link_check_timeout +
5497 IXGBE_TRY_LINK_TIMEOUT))) {
5498 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5499 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5500 IXGBE_WRITE_FLUSH(hw);
5501 }
5502
5503 adapter->link_up = link_up;
5504 adapter->link_speed = link_speed;
5505 }
5506
5507 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5508 {
5509 #ifdef CONFIG_IXGBE_DCB
5510 struct net_device *netdev = adapter->netdev;
5511 struct dcb_app app = {
5512 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5513 .protocol = 0,
5514 };
5515 u8 up = 0;
5516
5517 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5518 up = dcb_ieee_getapp_mask(netdev, &app);
5519
5520 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5521 #endif
5522 }
5523
5524 /**
5525 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5526 * print link up message
5527 * @adapter: pointer to the device adapter structure
5528 **/
5529 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5530 {
5531 struct net_device *netdev = adapter->netdev;
5532 struct ixgbe_hw *hw = &adapter->hw;
5533 u32 link_speed = adapter->link_speed;
5534 bool flow_rx, flow_tx;
5535
5536 /* only continue if link was previously down */
5537 if (netif_carrier_ok(netdev))
5538 return;
5539
5540 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5541
5542 switch (hw->mac.type) {
5543 case ixgbe_mac_82598EB: {
5544 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5545 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5546 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5547 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5548 }
5549 break;
5550 case ixgbe_mac_X540:
5551 case ixgbe_mac_82599EB: {
5552 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5553 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5554 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5555 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5556 }
5557 break;
5558 default:
5559 flow_tx = false;
5560 flow_rx = false;
5561 break;
5562 }
5563
5564 #ifdef CONFIG_IXGBE_PTP
5565 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5566 ixgbe_ptp_start_cyclecounter(adapter);
5567 #endif
5568
5569 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5570 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5571 "10 Gbps" :
5572 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5573 "1 Gbps" :
5574 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5575 "100 Mbps" :
5576 "unknown speed"))),
5577 ((flow_rx && flow_tx) ? "RX/TX" :
5578 (flow_rx ? "RX" :
5579 (flow_tx ? "TX" : "None"))));
5580
5581 netif_carrier_on(netdev);
5582 ixgbe_check_vf_rate_limit(adapter);
5583
5584 /* update the default user priority for VFs */
5585 ixgbe_update_default_up(adapter);
5586
5587 /* ping all the active vfs to let them know link has changed */
5588 ixgbe_ping_all_vfs(adapter);
5589 }
5590
5591 /**
5592 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5593 * print link down message
5594 * @adapter: pointer to the adapter structure
5595 **/
5596 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5597 {
5598 struct net_device *netdev = adapter->netdev;
5599 struct ixgbe_hw *hw = &adapter->hw;
5600
5601 adapter->link_up = false;
5602 adapter->link_speed = 0;
5603
5604 /* only continue if link was up previously */
5605 if (!netif_carrier_ok(netdev))
5606 return;
5607
5608 /* poll for SFP+ cable when link is down */
5609 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5610 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5611
5612 #ifdef CONFIG_IXGBE_PTP
5613 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5614 ixgbe_ptp_start_cyclecounter(adapter);
5615 #endif
5616
5617 e_info(drv, "NIC Link is Down\n");
5618 netif_carrier_off(netdev);
5619
5620 /* ping all the active vfs to let them know link has changed */
5621 ixgbe_ping_all_vfs(adapter);
5622 }
5623
5624 /**
5625 * ixgbe_watchdog_flush_tx - flush queues on link down
5626 * @adapter: pointer to the device adapter structure
5627 **/
5628 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5629 {
5630 int i;
5631 int some_tx_pending = 0;
5632
5633 if (!netif_carrier_ok(adapter->netdev)) {
5634 for (i = 0; i < adapter->num_tx_queues; i++) {
5635 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5636 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5637 some_tx_pending = 1;
5638 break;
5639 }
5640 }
5641
5642 if (some_tx_pending) {
5643 /* We've lost link, so the controller stops DMA,
5644 * but we've got queued Tx work that's never going
5645 * to get done, so reset controller to flush Tx.
5646 * (Do the reset outside of interrupt context).
5647 */
5648 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5649 }
5650 }
5651 }
5652
5653 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5654 {
5655 u32 ssvpc;
5656
5657 /* Do not perform spoof check for 82598 or if not in IOV mode */
5658 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5659 adapter->num_vfs == 0)
5660 return;
5661
5662 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5663
5664 /*
5665 * ssvpc register is cleared on read, if zero then no
5666 * spoofed packets in the last interval.
5667 */
5668 if (!ssvpc)
5669 return;
5670
5671 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5672 }
5673
5674 /**
5675 * ixgbe_watchdog_subtask - check and bring link up
5676 * @adapter: pointer to the device adapter structure
5677 **/
5678 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5679 {
5680 /* if interface is down do nothing */
5681 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5682 test_bit(__IXGBE_RESETTING, &adapter->state))
5683 return;
5684
5685 ixgbe_watchdog_update_link(adapter);
5686
5687 if (adapter->link_up)
5688 ixgbe_watchdog_link_is_up(adapter);
5689 else
5690 ixgbe_watchdog_link_is_down(adapter);
5691
5692 ixgbe_spoof_check(adapter);
5693 ixgbe_update_stats(adapter);
5694
5695 ixgbe_watchdog_flush_tx(adapter);
5696 }
5697
5698 /**
5699 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5700 * @adapter: the ixgbe adapter structure
5701 **/
5702 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5703 {
5704 struct ixgbe_hw *hw = &adapter->hw;
5705 s32 err;
5706
5707 /* not searching for SFP so there is nothing to do here */
5708 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5709 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5710 return;
5711
5712 /* someone else is in init, wait until next service event */
5713 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5714 return;
5715
5716 err = hw->phy.ops.identify_sfp(hw);
5717 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5718 goto sfp_out;
5719
5720 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5721 /* If no cable is present, then we need to reset
5722 * the next time we find a good cable. */
5723 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5724 }
5725
5726 /* exit on error */
5727 if (err)
5728 goto sfp_out;
5729
5730 /* exit if reset not needed */
5731 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5732 goto sfp_out;
5733
5734 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5735
5736 /*
5737 * A module may be identified correctly, but the EEPROM may not have
5738 * support for that module. setup_sfp() will fail in that case, so
5739 * we should not allow that module to load.
5740 */
5741 if (hw->mac.type == ixgbe_mac_82598EB)
5742 err = hw->phy.ops.reset(hw);
5743 else
5744 err = hw->mac.ops.setup_sfp(hw);
5745
5746 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5747 goto sfp_out;
5748
5749 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5750 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5751
5752 sfp_out:
5753 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5754
5755 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5756 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5757 e_dev_err("failed to initialize because an unsupported "
5758 "SFP+ module type was detected.\n");
5759 e_dev_err("Reload the driver after installing a "
5760 "supported module.\n");
5761 unregister_netdev(adapter->netdev);
5762 }
5763 }
5764
5765 /**
5766 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5767 * @adapter: the ixgbe adapter structure
5768 **/
5769 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5770 {
5771 struct ixgbe_hw *hw = &adapter->hw;
5772 u32 autoneg;
5773 bool negotiation;
5774
5775 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5776 return;
5777
5778 /* someone else is in init, wait until next service event */
5779 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5780 return;
5781
5782 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5783
5784 autoneg = hw->phy.autoneg_advertised;
5785 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5786 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5787 if (hw->mac.ops.setup_link)
5788 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5789
5790 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5791 adapter->link_check_timeout = jiffies;
5792 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5793 }
5794
5795 #ifdef CONFIG_PCI_IOV
5796 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5797 {
5798 int vf;
5799 struct ixgbe_hw *hw = &adapter->hw;
5800 struct net_device *netdev = adapter->netdev;
5801 u32 gpc;
5802 u32 ciaa, ciad;
5803
5804 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5805 if (gpc) /* If incrementing then no need for the check below */
5806 return;
5807 /*
5808 * Check to see if a bad DMA write target from an errant or
5809 * malicious VF has caused a PCIe error. If so then we can
5810 * issue a VFLR to the offending VF(s) and then resume without
5811 * requesting a full slot reset.
5812 */
5813
5814 for (vf = 0; vf < adapter->num_vfs; vf++) {
5815 ciaa = (vf << 16) | 0x80000000;
5816 /* 32 bit read so align, we really want status at offset 6 */
5817 ciaa |= PCI_COMMAND;
5818 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5819 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5820 ciaa &= 0x7FFFFFFF;
5821 /* disable debug mode asap after reading data */
5822 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5823 /* Get the upper 16 bits which will be the PCI status reg */
5824 ciad >>= 16;
5825 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5826 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5827 /* Issue VFLR */
5828 ciaa = (vf << 16) | 0x80000000;
5829 ciaa |= 0xA8;
5830 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5831 ciad = 0x00008000; /* VFLR */
5832 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5833 ciaa &= 0x7FFFFFFF;
5834 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5835 }
5836 }
5837 }
5838
5839 #endif
5840 /**
5841 * ixgbe_service_timer - Timer Call-back
5842 * @data: pointer to adapter cast into an unsigned long
5843 **/
5844 static void ixgbe_service_timer(unsigned long data)
5845 {
5846 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5847 unsigned long next_event_offset;
5848 bool ready = true;
5849
5850 /* poll faster when waiting for link */
5851 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5852 next_event_offset = HZ / 10;
5853 else
5854 next_event_offset = HZ * 2;
5855
5856 #ifdef CONFIG_PCI_IOV
5857 /*
5858 * don't bother with SR-IOV VF DMA hang check if there are
5859 * no VFs or the link is down
5860 */
5861 if (!adapter->num_vfs ||
5862 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5863 goto normal_timer_service;
5864
5865 /* If we have VFs allocated then we must check for DMA hangs */
5866 ixgbe_check_for_bad_vf(adapter);
5867 next_event_offset = HZ / 50;
5868 adapter->timer_event_accumulator++;
5869
5870 if (adapter->timer_event_accumulator >= 100)
5871 adapter->timer_event_accumulator = 0;
5872 else
5873 ready = false;
5874
5875 normal_timer_service:
5876 #endif
5877 /* Reset the timer */
5878 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5879
5880 if (ready)
5881 ixgbe_service_event_schedule(adapter);
5882 }
5883
5884 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5885 {
5886 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5887 return;
5888
5889 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5890
5891 /* If we're already down or resetting, just bail */
5892 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5893 test_bit(__IXGBE_RESETTING, &adapter->state))
5894 return;
5895
5896 ixgbe_dump(adapter);
5897 netdev_err(adapter->netdev, "Reset adapter\n");
5898 adapter->tx_timeout_count++;
5899
5900 ixgbe_reinit_locked(adapter);
5901 }
5902
5903 /**
5904 * ixgbe_service_task - manages and runs subtasks
5905 * @work: pointer to work_struct containing our data
5906 **/
5907 static void ixgbe_service_task(struct work_struct *work)
5908 {
5909 struct ixgbe_adapter *adapter = container_of(work,
5910 struct ixgbe_adapter,
5911 service_task);
5912
5913 ixgbe_reset_subtask(adapter);
5914 ixgbe_sfp_detection_subtask(adapter);
5915 ixgbe_sfp_link_config_subtask(adapter);
5916 ixgbe_check_overtemp_subtask(adapter);
5917 ixgbe_watchdog_subtask(adapter);
5918 ixgbe_fdir_reinit_subtask(adapter);
5919 ixgbe_check_hang_subtask(adapter);
5920 #ifdef CONFIG_IXGBE_PTP
5921 ixgbe_ptp_overflow_check(adapter);
5922 #endif
5923
5924 ixgbe_service_event_complete(adapter);
5925 }
5926
5927 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5928 struct ixgbe_tx_buffer *first,
5929 u8 *hdr_len)
5930 {
5931 struct sk_buff *skb = first->skb;
5932 u32 vlan_macip_lens, type_tucmd;
5933 u32 mss_l4len_idx, l4len;
5934
5935 if (!skb_is_gso(skb))
5936 return 0;
5937
5938 if (skb_header_cloned(skb)) {
5939 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5940 if (err)
5941 return err;
5942 }
5943
5944 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5945 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5946
5947 if (first->protocol == __constant_htons(ETH_P_IP)) {
5948 struct iphdr *iph = ip_hdr(skb);
5949 iph->tot_len = 0;
5950 iph->check = 0;
5951 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5952 iph->daddr, 0,
5953 IPPROTO_TCP,
5954 0);
5955 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5956 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5957 IXGBE_TX_FLAGS_CSUM |
5958 IXGBE_TX_FLAGS_IPV4;
5959 } else if (skb_is_gso_v6(skb)) {
5960 ipv6_hdr(skb)->payload_len = 0;
5961 tcp_hdr(skb)->check =
5962 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5963 &ipv6_hdr(skb)->daddr,
5964 0, IPPROTO_TCP, 0);
5965 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5966 IXGBE_TX_FLAGS_CSUM;
5967 }
5968
5969 /* compute header lengths */
5970 l4len = tcp_hdrlen(skb);
5971 *hdr_len = skb_transport_offset(skb) + l4len;
5972
5973 /* update gso size and bytecount with header size */
5974 first->gso_segs = skb_shinfo(skb)->gso_segs;
5975 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5976
5977 /* mss_l4len_id: use 1 as index for TSO */
5978 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5979 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5980 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5981
5982 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5983 vlan_macip_lens = skb_network_header_len(skb);
5984 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5985 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5986
5987 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5988 mss_l4len_idx);
5989
5990 return 1;
5991 }
5992
5993 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5994 struct ixgbe_tx_buffer *first)
5995 {
5996 struct sk_buff *skb = first->skb;
5997 u32 vlan_macip_lens = 0;
5998 u32 mss_l4len_idx = 0;
5999 u32 type_tucmd = 0;
6000
6001 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6002 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
6003 if (unlikely(skb->no_fcs))
6004 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
6005 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
6006 return;
6007 }
6008 } else {
6009 u8 l4_hdr = 0;
6010 switch (first->protocol) {
6011 case __constant_htons(ETH_P_IP):
6012 vlan_macip_lens |= skb_network_header_len(skb);
6013 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6014 l4_hdr = ip_hdr(skb)->protocol;
6015 break;
6016 case __constant_htons(ETH_P_IPV6):
6017 vlan_macip_lens |= skb_network_header_len(skb);
6018 l4_hdr = ipv6_hdr(skb)->nexthdr;
6019 break;
6020 default:
6021 if (unlikely(net_ratelimit())) {
6022 dev_warn(tx_ring->dev,
6023 "partial checksum but proto=%x!\n",
6024 first->protocol);
6025 }
6026 break;
6027 }
6028
6029 switch (l4_hdr) {
6030 case IPPROTO_TCP:
6031 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6032 mss_l4len_idx = tcp_hdrlen(skb) <<
6033 IXGBE_ADVTXD_L4LEN_SHIFT;
6034 break;
6035 case IPPROTO_SCTP:
6036 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6037 mss_l4len_idx = sizeof(struct sctphdr) <<
6038 IXGBE_ADVTXD_L4LEN_SHIFT;
6039 break;
6040 case IPPROTO_UDP:
6041 mss_l4len_idx = sizeof(struct udphdr) <<
6042 IXGBE_ADVTXD_L4LEN_SHIFT;
6043 break;
6044 default:
6045 if (unlikely(net_ratelimit())) {
6046 dev_warn(tx_ring->dev,
6047 "partial checksum but l4 proto=%x!\n",
6048 l4_hdr);
6049 }
6050 break;
6051 }
6052
6053 /* update TX checksum flag */
6054 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6055 }
6056
6057 /* vlan_macip_lens: MACLEN, VLAN tag */
6058 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6059 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6060
6061 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6062 type_tucmd, mss_l4len_idx);
6063 }
6064
6065 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6066 {
6067 /* set type for advanced descriptor with frame checksum insertion */
6068 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6069 IXGBE_ADVTXD_DCMD_DEXT);
6070
6071 /* set HW vlan bit if vlan is present */
6072 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6073 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6074
6075 #ifdef CONFIG_IXGBE_PTP
6076 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6077 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
6078 #endif
6079
6080 /* set segmentation enable bits for TSO/FSO */
6081 #ifdef IXGBE_FCOE
6082 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
6083 #else
6084 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6085 #endif
6086 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6087
6088 /* insert frame checksum */
6089 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6090 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6091
6092 return cmd_type;
6093 }
6094
6095 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6096 u32 tx_flags, unsigned int paylen)
6097 {
6098 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6099
6100 /* enable L4 checksum for TSO and TX checksum offload */
6101 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6102 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6103
6104 /* enble IPv4 checksum for TSO */
6105 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6106 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6107
6108 /* use index 1 context for TSO/FSO/FCOE */
6109 #ifdef IXGBE_FCOE
6110 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6111 #else
6112 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6113 #endif
6114 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6115
6116 /*
6117 * Check Context must be set if Tx switch is enabled, which it
6118 * always is for case where virtual functions are running
6119 */
6120 #ifdef IXGBE_FCOE
6121 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6122 #else
6123 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6124 #endif
6125 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6126
6127 tx_desc->read.olinfo_status = olinfo_status;
6128 }
6129
6130 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6131 IXGBE_TXD_CMD_RS)
6132
6133 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6134 struct ixgbe_tx_buffer *first,
6135 const u8 hdr_len)
6136 {
6137 dma_addr_t dma;
6138 struct sk_buff *skb = first->skb;
6139 struct ixgbe_tx_buffer *tx_buffer;
6140 union ixgbe_adv_tx_desc *tx_desc;
6141 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6142 unsigned int data_len = skb->data_len;
6143 unsigned int size = skb_headlen(skb);
6144 unsigned int paylen = skb->len - hdr_len;
6145 u32 tx_flags = first->tx_flags;
6146 __le32 cmd_type;
6147 u16 i = tx_ring->next_to_use;
6148
6149 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6150
6151 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6152 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6153
6154 #ifdef IXGBE_FCOE
6155 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6156 if (data_len < sizeof(struct fcoe_crc_eof)) {
6157 size -= sizeof(struct fcoe_crc_eof) - data_len;
6158 data_len = 0;
6159 } else {
6160 data_len -= sizeof(struct fcoe_crc_eof);
6161 }
6162 }
6163
6164 #endif
6165 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6166 if (dma_mapping_error(tx_ring->dev, dma))
6167 goto dma_error;
6168
6169 /* record length, and DMA address */
6170 dma_unmap_len_set(first, len, size);
6171 dma_unmap_addr_set(first, dma, dma);
6172
6173 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6174
6175 for (;;) {
6176 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6177 tx_desc->read.cmd_type_len =
6178 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6179
6180 i++;
6181 tx_desc++;
6182 if (i == tx_ring->count) {
6183 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6184 i = 0;
6185 }
6186
6187 dma += IXGBE_MAX_DATA_PER_TXD;
6188 size -= IXGBE_MAX_DATA_PER_TXD;
6189
6190 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6191 tx_desc->read.olinfo_status = 0;
6192 }
6193
6194 if (likely(!data_len))
6195 break;
6196
6197 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6198
6199 i++;
6200 tx_desc++;
6201 if (i == tx_ring->count) {
6202 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6203 i = 0;
6204 }
6205
6206 #ifdef IXGBE_FCOE
6207 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6208 #else
6209 size = skb_frag_size(frag);
6210 #endif
6211 data_len -= size;
6212
6213 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6214 DMA_TO_DEVICE);
6215 if (dma_mapping_error(tx_ring->dev, dma))
6216 goto dma_error;
6217
6218 tx_buffer = &tx_ring->tx_buffer_info[i];
6219 dma_unmap_len_set(tx_buffer, len, size);
6220 dma_unmap_addr_set(tx_buffer, dma, dma);
6221
6222 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6223 tx_desc->read.olinfo_status = 0;
6224
6225 frag++;
6226 }
6227
6228 /* write last descriptor with RS and EOP bits */
6229 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6230 tx_desc->read.cmd_type_len = cmd_type;
6231
6232 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6233
6234 /* set the timestamp */
6235 first->time_stamp = jiffies;
6236
6237 /*
6238 * Force memory writes to complete before letting h/w know there
6239 * are new descriptors to fetch. (Only applicable for weak-ordered
6240 * memory model archs, such as IA-64).
6241 *
6242 * We also need this memory barrier to make certain all of the
6243 * status bits have been updated before next_to_watch is written.
6244 */
6245 wmb();
6246
6247 /* set next_to_watch value indicating a packet is present */
6248 first->next_to_watch = tx_desc;
6249
6250 i++;
6251 if (i == tx_ring->count)
6252 i = 0;
6253
6254 tx_ring->next_to_use = i;
6255
6256 /* notify HW of packet */
6257 writel(i, tx_ring->tail);
6258
6259 return;
6260 dma_error:
6261 dev_err(tx_ring->dev, "TX DMA map failed\n");
6262
6263 /* clear dma mappings for failed tx_buffer_info map */
6264 for (;;) {
6265 tx_buffer = &tx_ring->tx_buffer_info[i];
6266 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6267 if (tx_buffer == first)
6268 break;
6269 if (i == 0)
6270 i = tx_ring->count;
6271 i--;
6272 }
6273
6274 tx_ring->next_to_use = i;
6275 }
6276
6277 static void ixgbe_atr(struct ixgbe_ring *ring,
6278 struct ixgbe_tx_buffer *first)
6279 {
6280 struct ixgbe_q_vector *q_vector = ring->q_vector;
6281 union ixgbe_atr_hash_dword input = { .dword = 0 };
6282 union ixgbe_atr_hash_dword common = { .dword = 0 };
6283 union {
6284 unsigned char *network;
6285 struct iphdr *ipv4;
6286 struct ipv6hdr *ipv6;
6287 } hdr;
6288 struct tcphdr *th;
6289 __be16 vlan_id;
6290
6291 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6292 if (!q_vector)
6293 return;
6294
6295 /* do nothing if sampling is disabled */
6296 if (!ring->atr_sample_rate)
6297 return;
6298
6299 ring->atr_count++;
6300
6301 /* snag network header to get L4 type and address */
6302 hdr.network = skb_network_header(first->skb);
6303
6304 /* Currently only IPv4/IPv6 with TCP is supported */
6305 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6306 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6307 (first->protocol != __constant_htons(ETH_P_IP) ||
6308 hdr.ipv4->protocol != IPPROTO_TCP))
6309 return;
6310
6311 th = tcp_hdr(first->skb);
6312
6313 /* skip this packet since it is invalid or the socket is closing */
6314 if (!th || th->fin)
6315 return;
6316
6317 /* sample on all syn packets or once every atr sample count */
6318 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6319 return;
6320
6321 /* reset sample count */
6322 ring->atr_count = 0;
6323
6324 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6325
6326 /*
6327 * src and dst are inverted, think how the receiver sees them
6328 *
6329 * The input is broken into two sections, a non-compressed section
6330 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6331 * is XORed together and stored in the compressed dword.
6332 */
6333 input.formatted.vlan_id = vlan_id;
6334
6335 /*
6336 * since src port and flex bytes occupy the same word XOR them together
6337 * and write the value to source port portion of compressed dword
6338 */
6339 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6340 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6341 else
6342 common.port.src ^= th->dest ^ first->protocol;
6343 common.port.dst ^= th->source;
6344
6345 if (first->protocol == __constant_htons(ETH_P_IP)) {
6346 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6347 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6348 } else {
6349 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6350 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6351 hdr.ipv6->saddr.s6_addr32[1] ^
6352 hdr.ipv6->saddr.s6_addr32[2] ^
6353 hdr.ipv6->saddr.s6_addr32[3] ^
6354 hdr.ipv6->daddr.s6_addr32[0] ^
6355 hdr.ipv6->daddr.s6_addr32[1] ^
6356 hdr.ipv6->daddr.s6_addr32[2] ^
6357 hdr.ipv6->daddr.s6_addr32[3];
6358 }
6359
6360 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6361 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6362 input, common, ring->queue_index);
6363 }
6364
6365 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6366 {
6367 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6368 /* Herbert's original patch had:
6369 * smp_mb__after_netif_stop_queue();
6370 * but since that doesn't exist yet, just open code it. */
6371 smp_mb();
6372
6373 /* We need to check again in a case another CPU has just
6374 * made room available. */
6375 if (likely(ixgbe_desc_unused(tx_ring) < size))
6376 return -EBUSY;
6377
6378 /* A reprieve! - use start_queue because it doesn't call schedule */
6379 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6380 ++tx_ring->tx_stats.restart_queue;
6381 return 0;
6382 }
6383
6384 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6385 {
6386 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6387 return 0;
6388 return __ixgbe_maybe_stop_tx(tx_ring, size);
6389 }
6390
6391 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6392 {
6393 struct ixgbe_adapter *adapter = netdev_priv(dev);
6394 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6395 smp_processor_id();
6396 #ifdef IXGBE_FCOE
6397 __be16 protocol = vlan_get_protocol(skb);
6398
6399 if (((protocol == htons(ETH_P_FCOE)) ||
6400 (protocol == htons(ETH_P_FIP))) &&
6401 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6402 struct ixgbe_ring_feature *f;
6403
6404 f = &adapter->ring_feature[RING_F_FCOE];
6405
6406 while (txq >= f->indices)
6407 txq -= f->indices;
6408 txq += adapter->ring_feature[RING_F_FCOE].offset;
6409
6410 return txq;
6411 }
6412 #endif
6413
6414 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6415 while (unlikely(txq >= dev->real_num_tx_queues))
6416 txq -= dev->real_num_tx_queues;
6417 return txq;
6418 }
6419
6420 return skb_tx_hash(dev, skb);
6421 }
6422
6423 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6424 struct ixgbe_adapter *adapter,
6425 struct ixgbe_ring *tx_ring)
6426 {
6427 struct ixgbe_tx_buffer *first;
6428 int tso;
6429 u32 tx_flags = 0;
6430 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6431 unsigned short f;
6432 #endif
6433 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6434 __be16 protocol = skb->protocol;
6435 u8 hdr_len = 0;
6436
6437 /*
6438 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6439 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6440 * + 2 desc gap to keep tail from touching head,
6441 * + 1 desc for context descriptor,
6442 * otherwise try next time
6443 */
6444 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6445 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6446 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6447 #else
6448 count += skb_shinfo(skb)->nr_frags;
6449 #endif
6450 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6451 tx_ring->tx_stats.tx_busy++;
6452 return NETDEV_TX_BUSY;
6453 }
6454
6455 /* record the location of the first descriptor for this packet */
6456 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6457 first->skb = skb;
6458 first->bytecount = skb->len;
6459 first->gso_segs = 1;
6460
6461 /* if we have a HW VLAN tag being added default to the HW one */
6462 if (vlan_tx_tag_present(skb)) {
6463 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6464 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6465 /* else if it is a SW VLAN check the next protocol and store the tag */
6466 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6467 struct vlan_hdr *vhdr, _vhdr;
6468 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6469 if (!vhdr)
6470 goto out_drop;
6471
6472 protocol = vhdr->h_vlan_encapsulated_proto;
6473 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6474 IXGBE_TX_FLAGS_VLAN_SHIFT;
6475 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6476 }
6477
6478 skb_tx_timestamp(skb);
6479
6480 #ifdef CONFIG_IXGBE_PTP
6481 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6482 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6483 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6484 }
6485 #endif
6486
6487 #ifdef CONFIG_PCI_IOV
6488 /*
6489 * Use the l2switch_enable flag - would be false if the DMA
6490 * Tx switch had been disabled.
6491 */
6492 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6493 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6494
6495 #endif
6496 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6497 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6498 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6499 (skb->priority != TC_PRIO_CONTROL))) {
6500 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6501 tx_flags |= (skb->priority & 0x7) <<
6502 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6503 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6504 struct vlan_ethhdr *vhdr;
6505 if (skb_header_cloned(skb) &&
6506 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6507 goto out_drop;
6508 vhdr = (struct vlan_ethhdr *)skb->data;
6509 vhdr->h_vlan_TCI = htons(tx_flags >>
6510 IXGBE_TX_FLAGS_VLAN_SHIFT);
6511 } else {
6512 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6513 }
6514 }
6515
6516 /* record initial flags and protocol */
6517 first->tx_flags = tx_flags;
6518 first->protocol = protocol;
6519
6520 #ifdef IXGBE_FCOE
6521 /* setup tx offload for FCoE */
6522 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6523 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6524 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6525 if (tso < 0)
6526 goto out_drop;
6527
6528 goto xmit_fcoe;
6529 }
6530
6531 #endif /* IXGBE_FCOE */
6532 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6533 if (tso < 0)
6534 goto out_drop;
6535 else if (!tso)
6536 ixgbe_tx_csum(tx_ring, first);
6537
6538 /* add the ATR filter if ATR is on */
6539 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6540 ixgbe_atr(tx_ring, first);
6541
6542 #ifdef IXGBE_FCOE
6543 xmit_fcoe:
6544 #endif /* IXGBE_FCOE */
6545 ixgbe_tx_map(tx_ring, first, hdr_len);
6546
6547 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6548
6549 return NETDEV_TX_OK;
6550
6551 out_drop:
6552 dev_kfree_skb_any(first->skb);
6553 first->skb = NULL;
6554
6555 return NETDEV_TX_OK;
6556 }
6557
6558 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6559 struct net_device *netdev)
6560 {
6561 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6562 struct ixgbe_ring *tx_ring;
6563
6564 /*
6565 * The minimum packet size for olinfo paylen is 17 so pad the skb
6566 * in order to meet this minimum size requirement.
6567 */
6568 if (unlikely(skb->len < 17)) {
6569 if (skb_pad(skb, 17 - skb->len))
6570 return NETDEV_TX_OK;
6571 skb->len = 17;
6572 skb_set_tail_pointer(skb, 17);
6573 }
6574
6575 tx_ring = adapter->tx_ring[skb->queue_mapping];
6576 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6577 }
6578
6579 /**
6580 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6581 * @netdev: network interface device structure
6582 * @p: pointer to an address structure
6583 *
6584 * Returns 0 on success, negative on failure
6585 **/
6586 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6587 {
6588 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6589 struct ixgbe_hw *hw = &adapter->hw;
6590 struct sockaddr *addr = p;
6591
6592 if (!is_valid_ether_addr(addr->sa_data))
6593 return -EADDRNOTAVAIL;
6594
6595 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6596 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6597
6598 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6599
6600 return 0;
6601 }
6602
6603 static int
6604 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6605 {
6606 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6607 struct ixgbe_hw *hw = &adapter->hw;
6608 u16 value;
6609 int rc;
6610
6611 if (prtad != hw->phy.mdio.prtad)
6612 return -EINVAL;
6613 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6614 if (!rc)
6615 rc = value;
6616 return rc;
6617 }
6618
6619 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6620 u16 addr, u16 value)
6621 {
6622 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6623 struct ixgbe_hw *hw = &adapter->hw;
6624
6625 if (prtad != hw->phy.mdio.prtad)
6626 return -EINVAL;
6627 return hw->phy.ops.write_reg(hw, addr, devad, value);
6628 }
6629
6630 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6631 {
6632 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6633
6634 switch (cmd) {
6635 #ifdef CONFIG_IXGBE_PTP
6636 case SIOCSHWTSTAMP:
6637 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6638 #endif
6639 default:
6640 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6641 }
6642 }
6643
6644 /**
6645 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6646 * netdev->dev_addrs
6647 * @netdev: network interface device structure
6648 *
6649 * Returns non-zero on failure
6650 **/
6651 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6652 {
6653 int err = 0;
6654 struct ixgbe_adapter *adapter = netdev_priv(dev);
6655 struct ixgbe_hw *hw = &adapter->hw;
6656
6657 if (is_valid_ether_addr(hw->mac.san_addr)) {
6658 rtnl_lock();
6659 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6660 rtnl_unlock();
6661
6662 /* update SAN MAC vmdq pool selection */
6663 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6664 }
6665 return err;
6666 }
6667
6668 /**
6669 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6670 * netdev->dev_addrs
6671 * @netdev: network interface device structure
6672 *
6673 * Returns non-zero on failure
6674 **/
6675 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6676 {
6677 int err = 0;
6678 struct ixgbe_adapter *adapter = netdev_priv(dev);
6679 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6680
6681 if (is_valid_ether_addr(mac->san_addr)) {
6682 rtnl_lock();
6683 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6684 rtnl_unlock();
6685 }
6686 return err;
6687 }
6688
6689 #ifdef CONFIG_NET_POLL_CONTROLLER
6690 /*
6691 * Polling 'interrupt' - used by things like netconsole to send skbs
6692 * without having to re-enable interrupts. It's not called while
6693 * the interrupt routine is executing.
6694 */
6695 static void ixgbe_netpoll(struct net_device *netdev)
6696 {
6697 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6698 int i;
6699
6700 /* if interface is down do nothing */
6701 if (test_bit(__IXGBE_DOWN, &adapter->state))
6702 return;
6703
6704 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6705 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6706 for (i = 0; i < adapter->num_q_vectors; i++)
6707 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6708 } else {
6709 ixgbe_intr(adapter->pdev->irq, netdev);
6710 }
6711 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6712 }
6713
6714 #endif
6715 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6716 struct rtnl_link_stats64 *stats)
6717 {
6718 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6719 int i;
6720
6721 rcu_read_lock();
6722 for (i = 0; i < adapter->num_rx_queues; i++) {
6723 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6724 u64 bytes, packets;
6725 unsigned int start;
6726
6727 if (ring) {
6728 do {
6729 start = u64_stats_fetch_begin_bh(&ring->syncp);
6730 packets = ring->stats.packets;
6731 bytes = ring->stats.bytes;
6732 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6733 stats->rx_packets += packets;
6734 stats->rx_bytes += bytes;
6735 }
6736 }
6737
6738 for (i = 0; i < adapter->num_tx_queues; i++) {
6739 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6740 u64 bytes, packets;
6741 unsigned int start;
6742
6743 if (ring) {
6744 do {
6745 start = u64_stats_fetch_begin_bh(&ring->syncp);
6746 packets = ring->stats.packets;
6747 bytes = ring->stats.bytes;
6748 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6749 stats->tx_packets += packets;
6750 stats->tx_bytes += bytes;
6751 }
6752 }
6753 rcu_read_unlock();
6754 /* following stats updated by ixgbe_watchdog_task() */
6755 stats->multicast = netdev->stats.multicast;
6756 stats->rx_errors = netdev->stats.rx_errors;
6757 stats->rx_length_errors = netdev->stats.rx_length_errors;
6758 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6759 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6760 return stats;
6761 }
6762
6763 #ifdef CONFIG_IXGBE_DCB
6764 /**
6765 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6766 * @adapter: pointer to ixgbe_adapter
6767 * @tc: number of traffic classes currently enabled
6768 *
6769 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6770 * 802.1Q priority maps to a packet buffer that exists.
6771 */
6772 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6773 {
6774 struct ixgbe_hw *hw = &adapter->hw;
6775 u32 reg, rsave;
6776 int i;
6777
6778 /* 82598 have a static priority to TC mapping that can not
6779 * be changed so no validation is needed.
6780 */
6781 if (hw->mac.type == ixgbe_mac_82598EB)
6782 return;
6783
6784 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6785 rsave = reg;
6786
6787 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6788 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6789
6790 /* If up2tc is out of bounds default to zero */
6791 if (up2tc > tc)
6792 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6793 }
6794
6795 if (reg != rsave)
6796 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6797
6798 return;
6799 }
6800
6801 /**
6802 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6803 * @adapter: Pointer to adapter struct
6804 *
6805 * Populate the netdev user priority to tc map
6806 */
6807 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6808 {
6809 struct net_device *dev = adapter->netdev;
6810 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6811 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6812 u8 prio;
6813
6814 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6815 u8 tc = 0;
6816
6817 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6818 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6819 else if (ets)
6820 tc = ets->prio_tc[prio];
6821
6822 netdev_set_prio_tc_map(dev, prio, tc);
6823 }
6824 }
6825
6826 /**
6827 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6828 *
6829 * @netdev: net device to configure
6830 * @tc: number of traffic classes to enable
6831 */
6832 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6833 {
6834 struct ixgbe_adapter *adapter = netdev_priv(dev);
6835 struct ixgbe_hw *hw = &adapter->hw;
6836
6837 /* Hardware supports up to 8 traffic classes */
6838 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6839 (hw->mac.type == ixgbe_mac_82598EB &&
6840 tc < MAX_TRAFFIC_CLASS))
6841 return -EINVAL;
6842
6843 /* Hardware has to reinitialize queues and interrupts to
6844 * match packet buffer alignment. Unfortunately, the
6845 * hardware is not flexible enough to do this dynamically.
6846 */
6847 if (netif_running(dev))
6848 ixgbe_close(dev);
6849 ixgbe_clear_interrupt_scheme(adapter);
6850
6851 if (tc) {
6852 netdev_set_num_tc(dev, tc);
6853 ixgbe_set_prio_tc_map(adapter);
6854
6855 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6856
6857 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6858 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6859 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6860 }
6861 } else {
6862 netdev_reset_tc(dev);
6863
6864 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6865 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6866
6867 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6868
6869 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6870 adapter->dcb_cfg.pfc_mode_enable = false;
6871 }
6872
6873 ixgbe_init_interrupt_scheme(adapter);
6874 ixgbe_validate_rtr(adapter, tc);
6875 if (netif_running(dev))
6876 ixgbe_open(dev);
6877
6878 return 0;
6879 }
6880
6881 #endif /* CONFIG_IXGBE_DCB */
6882 void ixgbe_do_reset(struct net_device *netdev)
6883 {
6884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6885
6886 if (netif_running(netdev))
6887 ixgbe_reinit_locked(adapter);
6888 else
6889 ixgbe_reset(adapter);
6890 }
6891
6892 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6893 netdev_features_t features)
6894 {
6895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6896
6897 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6898 if (!(features & NETIF_F_RXCSUM))
6899 features &= ~NETIF_F_LRO;
6900
6901 /* Turn off LRO if not RSC capable */
6902 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6903 features &= ~NETIF_F_LRO;
6904
6905 return features;
6906 }
6907
6908 static int ixgbe_set_features(struct net_device *netdev,
6909 netdev_features_t features)
6910 {
6911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6912 netdev_features_t changed = netdev->features ^ features;
6913 bool need_reset = false;
6914
6915 /* Make sure RSC matches LRO, reset if change */
6916 if (!(features & NETIF_F_LRO)) {
6917 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6918 need_reset = true;
6919 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6920 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6921 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6922 if (adapter->rx_itr_setting == 1 ||
6923 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6924 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6925 need_reset = true;
6926 } else if ((changed ^ features) & NETIF_F_LRO) {
6927 e_info(probe, "rx-usecs set too low, "
6928 "disabling RSC\n");
6929 }
6930 }
6931
6932 /*
6933 * Check if Flow Director n-tuple support was enabled or disabled. If
6934 * the state changed, we need to reset.
6935 */
6936 switch (features & NETIF_F_NTUPLE) {
6937 case NETIF_F_NTUPLE:
6938 /* turn off ATR, enable perfect filters and reset */
6939 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6940 need_reset = true;
6941
6942 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6943 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6944 break;
6945 default:
6946 /* turn off perfect filters, enable ATR and reset */
6947 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6948 need_reset = true;
6949
6950 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6951
6952 /* We cannot enable ATR if SR-IOV is enabled */
6953 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6954 break;
6955
6956 /* We cannot enable ATR if we have 2 or more traffic classes */
6957 if (netdev_get_num_tc(netdev) > 1)
6958 break;
6959
6960 /* We cannot enable ATR if RSS is disabled */
6961 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6962 break;
6963
6964 /* A sample rate of 0 indicates ATR disabled */
6965 if (!adapter->atr_sample_rate)
6966 break;
6967
6968 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6969 break;
6970 }
6971
6972 if (features & NETIF_F_HW_VLAN_RX)
6973 ixgbe_vlan_strip_enable(adapter);
6974 else
6975 ixgbe_vlan_strip_disable(adapter);
6976
6977 if (changed & NETIF_F_RXALL)
6978 need_reset = true;
6979
6980 netdev->features = features;
6981 if (need_reset)
6982 ixgbe_do_reset(netdev);
6983
6984 return 0;
6985 }
6986
6987 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6988 struct net_device *dev,
6989 const unsigned char *addr,
6990 u16 flags)
6991 {
6992 struct ixgbe_adapter *adapter = netdev_priv(dev);
6993 int err;
6994
6995 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6996 return -EOPNOTSUPP;
6997
6998 if (ndm->ndm_state & NUD_PERMANENT) {
6999 pr_info("%s: FDB only supports static addresses\n",
7000 ixgbe_driver_name);
7001 return -EINVAL;
7002 }
7003
7004 if (is_unicast_ether_addr(addr) || is_link_local(addr)) {
7005 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7006
7007 if (netdev_uc_count(dev) < rar_uc_entries)
7008 err = dev_uc_add_excl(dev, addr);
7009 else
7010 err = -ENOMEM;
7011 } else if (is_multicast_ether_addr(addr)) {
7012 err = dev_mc_add_excl(dev, addr);
7013 } else {
7014 err = -EINVAL;
7015 }
7016
7017 /* Only return duplicate errors if NLM_F_EXCL is set */
7018 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7019 err = 0;
7020
7021 return err;
7022 }
7023
7024 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
7025 struct net_device *dev,
7026 const unsigned char *addr)
7027 {
7028 struct ixgbe_adapter *adapter = netdev_priv(dev);
7029 int err = -EOPNOTSUPP;
7030
7031 if (ndm->ndm_state & NUD_PERMANENT) {
7032 pr_info("%s: FDB only supports static addresses\n",
7033 ixgbe_driver_name);
7034 return -EINVAL;
7035 }
7036
7037 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7038 if (is_unicast_ether_addr(addr))
7039 err = dev_uc_del(dev, addr);
7040 else if (is_multicast_ether_addr(addr))
7041 err = dev_mc_del(dev, addr);
7042 else
7043 err = -EINVAL;
7044 }
7045
7046 return err;
7047 }
7048
7049 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7050 struct netlink_callback *cb,
7051 struct net_device *dev,
7052 int idx)
7053 {
7054 struct ixgbe_adapter *adapter = netdev_priv(dev);
7055
7056 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7057 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7058
7059 return idx;
7060 }
7061
7062 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7063 struct nlmsghdr *nlh)
7064 {
7065 struct ixgbe_adapter *adapter = netdev_priv(dev);
7066 struct nlattr *attr, *br_spec;
7067 int rem;
7068
7069 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7070 return -EOPNOTSUPP;
7071
7072 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7073
7074 nla_for_each_nested(attr, br_spec, rem) {
7075 __u16 mode;
7076 u32 reg = 0;
7077
7078 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7079 continue;
7080
7081 mode = nla_get_u16(attr);
7082 if (mode == BRIDGE_MODE_VEPA)
7083 reg = 0;
7084 else if (mode == BRIDGE_MODE_VEB)
7085 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7086 else
7087 return -EINVAL;
7088
7089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7090
7091 e_info(drv, "enabling bridge mode: %s\n",
7092 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7093 }
7094
7095 return 0;
7096 }
7097
7098 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7099 struct net_device *dev)
7100 {
7101 struct ixgbe_adapter *adapter = netdev_priv(dev);
7102 u16 mode;
7103
7104 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7105 return 0;
7106
7107 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7108 mode = BRIDGE_MODE_VEB;
7109 else
7110 mode = BRIDGE_MODE_VEPA;
7111
7112 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7113 }
7114
7115 static const struct net_device_ops ixgbe_netdev_ops = {
7116 .ndo_open = ixgbe_open,
7117 .ndo_stop = ixgbe_close,
7118 .ndo_start_xmit = ixgbe_xmit_frame,
7119 .ndo_select_queue = ixgbe_select_queue,
7120 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7121 .ndo_validate_addr = eth_validate_addr,
7122 .ndo_set_mac_address = ixgbe_set_mac,
7123 .ndo_change_mtu = ixgbe_change_mtu,
7124 .ndo_tx_timeout = ixgbe_tx_timeout,
7125 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7126 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7127 .ndo_do_ioctl = ixgbe_ioctl,
7128 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7129 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7130 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7131 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7132 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7133 .ndo_get_stats64 = ixgbe_get_stats64,
7134 #ifdef CONFIG_IXGBE_DCB
7135 .ndo_setup_tc = ixgbe_setup_tc,
7136 #endif
7137 #ifdef CONFIG_NET_POLL_CONTROLLER
7138 .ndo_poll_controller = ixgbe_netpoll,
7139 #endif
7140 #ifdef IXGBE_FCOE
7141 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7142 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7143 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7144 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7145 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7146 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7147 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7148 #endif /* IXGBE_FCOE */
7149 .ndo_set_features = ixgbe_set_features,
7150 .ndo_fix_features = ixgbe_fix_features,
7151 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7152 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7153 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7154 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7155 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7156 };
7157
7158 /**
7159 * ixgbe_wol_supported - Check whether device supports WoL
7160 * @hw: hw specific details
7161 * @device_id: the device ID
7162 * @subdev_id: the subsystem device ID
7163 *
7164 * This function is used by probe and ethtool to determine
7165 * which devices have WoL support
7166 *
7167 **/
7168 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7169 u16 subdevice_id)
7170 {
7171 struct ixgbe_hw *hw = &adapter->hw;
7172 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7173 int is_wol_supported = 0;
7174
7175 switch (device_id) {
7176 case IXGBE_DEV_ID_82599_SFP:
7177 /* Only these subdevices could supports WOL */
7178 switch (subdevice_id) {
7179 case IXGBE_SUBDEV_ID_82599_560FLR:
7180 /* only support first port */
7181 if (hw->bus.func != 0)
7182 break;
7183 case IXGBE_SUBDEV_ID_82599_SFP:
7184 case IXGBE_SUBDEV_ID_82599_RNDC:
7185 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7186 is_wol_supported = 1;
7187 break;
7188 }
7189 break;
7190 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7191 /* All except this subdevice support WOL */
7192 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7193 is_wol_supported = 1;
7194 break;
7195 case IXGBE_DEV_ID_82599_KX4:
7196 is_wol_supported = 1;
7197 break;
7198 case IXGBE_DEV_ID_X540T:
7199 case IXGBE_DEV_ID_X540T1:
7200 /* check eeprom to see if enabled wol */
7201 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7202 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7203 (hw->bus.func == 0))) {
7204 is_wol_supported = 1;
7205 }
7206 break;
7207 }
7208
7209 return is_wol_supported;
7210 }
7211
7212 /**
7213 * ixgbe_probe - Device Initialization Routine
7214 * @pdev: PCI device information struct
7215 * @ent: entry in ixgbe_pci_tbl
7216 *
7217 * Returns 0 on success, negative on failure
7218 *
7219 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7220 * The OS initialization, configuring of the adapter private structure,
7221 * and a hardware reset occur.
7222 **/
7223 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7224 const struct pci_device_id *ent)
7225 {
7226 struct net_device *netdev;
7227 struct ixgbe_adapter *adapter = NULL;
7228 struct ixgbe_hw *hw;
7229 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7230 static int cards_found;
7231 int i, err, pci_using_dac;
7232 u8 part_str[IXGBE_PBANUM_LENGTH];
7233 unsigned int indices = num_possible_cpus();
7234 unsigned int dcb_max = 0;
7235 #ifdef IXGBE_FCOE
7236 u16 device_caps;
7237 #endif
7238 u32 eec;
7239
7240 /* Catch broken hardware that put the wrong VF device ID in
7241 * the PCIe SR-IOV capability.
7242 */
7243 if (pdev->is_virtfn) {
7244 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7245 pci_name(pdev), pdev->vendor, pdev->device);
7246 return -EINVAL;
7247 }
7248
7249 err = pci_enable_device_mem(pdev);
7250 if (err)
7251 return err;
7252
7253 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7254 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7255 pci_using_dac = 1;
7256 } else {
7257 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7258 if (err) {
7259 err = dma_set_coherent_mask(&pdev->dev,
7260 DMA_BIT_MASK(32));
7261 if (err) {
7262 dev_err(&pdev->dev,
7263 "No usable DMA configuration, aborting\n");
7264 goto err_dma;
7265 }
7266 }
7267 pci_using_dac = 0;
7268 }
7269
7270 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7271 IORESOURCE_MEM), ixgbe_driver_name);
7272 if (err) {
7273 dev_err(&pdev->dev,
7274 "pci_request_selected_regions failed 0x%x\n", err);
7275 goto err_pci_reg;
7276 }
7277
7278 pci_enable_pcie_error_reporting(pdev);
7279
7280 pci_set_master(pdev);
7281 pci_save_state(pdev);
7282
7283 #ifdef CONFIG_IXGBE_DCB
7284 if (ii->mac == ixgbe_mac_82598EB)
7285 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7286 IXGBE_MAX_RSS_INDICES);
7287 else
7288 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7289 IXGBE_MAX_FDIR_INDICES);
7290 #endif
7291
7292 if (ii->mac == ixgbe_mac_82598EB)
7293 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7294 else
7295 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7296
7297 #ifdef IXGBE_FCOE
7298 indices += min_t(unsigned int, num_possible_cpus(),
7299 IXGBE_MAX_FCOE_INDICES);
7300 #endif
7301 indices = max_t(unsigned int, dcb_max, indices);
7302 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7303 if (!netdev) {
7304 err = -ENOMEM;
7305 goto err_alloc_etherdev;
7306 }
7307
7308 SET_NETDEV_DEV(netdev, &pdev->dev);
7309
7310 adapter = netdev_priv(netdev);
7311 pci_set_drvdata(pdev, adapter);
7312
7313 adapter->netdev = netdev;
7314 adapter->pdev = pdev;
7315 hw = &adapter->hw;
7316 hw->back = adapter;
7317 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7318
7319 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7320 pci_resource_len(pdev, 0));
7321 if (!hw->hw_addr) {
7322 err = -EIO;
7323 goto err_ioremap;
7324 }
7325
7326 netdev->netdev_ops = &ixgbe_netdev_ops;
7327 ixgbe_set_ethtool_ops(netdev);
7328 netdev->watchdog_timeo = 5 * HZ;
7329 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7330
7331 adapter->bd_number = cards_found;
7332
7333 /* Setup hw api */
7334 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7335 hw->mac.type = ii->mac;
7336
7337 /* EEPROM */
7338 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7339 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7340 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7341 if (!(eec & (1 << 8)))
7342 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7343
7344 /* PHY */
7345 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7346 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7347 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7348 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7349 hw->phy.mdio.mmds = 0;
7350 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7351 hw->phy.mdio.dev = netdev;
7352 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7353 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7354
7355 ii->get_invariants(hw);
7356
7357 /* setup the private structure */
7358 err = ixgbe_sw_init(adapter);
7359 if (err)
7360 goto err_sw_init;
7361
7362 /* Make it possible the adapter to be woken up via WOL */
7363 switch (adapter->hw.mac.type) {
7364 case ixgbe_mac_82599EB:
7365 case ixgbe_mac_X540:
7366 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7367 break;
7368 default:
7369 break;
7370 }
7371
7372 /*
7373 * If there is a fan on this device and it has failed log the
7374 * failure.
7375 */
7376 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7377 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7378 if (esdp & IXGBE_ESDP_SDP1)
7379 e_crit(probe, "Fan has stopped, replace the adapter\n");
7380 }
7381
7382 if (allow_unsupported_sfp)
7383 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7384
7385 /* reset_hw fills in the perm_addr as well */
7386 hw->phy.reset_if_overtemp = true;
7387 err = hw->mac.ops.reset_hw(hw);
7388 hw->phy.reset_if_overtemp = false;
7389 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7390 hw->mac.type == ixgbe_mac_82598EB) {
7391 err = 0;
7392 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7393 e_dev_err("failed to load because an unsupported SFP+ "
7394 "module type was detected.\n");
7395 e_dev_err("Reload the driver after installing a supported "
7396 "module.\n");
7397 goto err_sw_init;
7398 } else if (err) {
7399 e_dev_err("HW Init failed: %d\n", err);
7400 goto err_sw_init;
7401 }
7402
7403 #ifdef CONFIG_PCI_IOV
7404 ixgbe_enable_sriov(adapter, ii);
7405
7406 #endif
7407 netdev->features = NETIF_F_SG |
7408 NETIF_F_IP_CSUM |
7409 NETIF_F_IPV6_CSUM |
7410 NETIF_F_HW_VLAN_TX |
7411 NETIF_F_HW_VLAN_RX |
7412 NETIF_F_HW_VLAN_FILTER |
7413 NETIF_F_TSO |
7414 NETIF_F_TSO6 |
7415 NETIF_F_RXHASH |
7416 NETIF_F_RXCSUM;
7417
7418 netdev->hw_features = netdev->features;
7419
7420 switch (adapter->hw.mac.type) {
7421 case ixgbe_mac_82599EB:
7422 case ixgbe_mac_X540:
7423 netdev->features |= NETIF_F_SCTP_CSUM;
7424 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7425 NETIF_F_NTUPLE;
7426 break;
7427 default:
7428 break;
7429 }
7430
7431 netdev->hw_features |= NETIF_F_RXALL;
7432
7433 netdev->vlan_features |= NETIF_F_TSO;
7434 netdev->vlan_features |= NETIF_F_TSO6;
7435 netdev->vlan_features |= NETIF_F_IP_CSUM;
7436 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7437 netdev->vlan_features |= NETIF_F_SG;
7438
7439 netdev->priv_flags |= IFF_UNICAST_FLT;
7440 netdev->priv_flags |= IFF_SUPP_NOFCS;
7441
7442 #ifdef CONFIG_IXGBE_DCB
7443 netdev->dcbnl_ops = &dcbnl_ops;
7444 #endif
7445
7446 #ifdef IXGBE_FCOE
7447 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7448 if (hw->mac.ops.get_device_caps) {
7449 hw->mac.ops.get_device_caps(hw, &device_caps);
7450 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7451 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7452 }
7453
7454 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7455
7456 netdev->features |= NETIF_F_FSO |
7457 NETIF_F_FCOE_CRC;
7458
7459 netdev->vlan_features |= NETIF_F_FSO |
7460 NETIF_F_FCOE_CRC |
7461 NETIF_F_FCOE_MTU;
7462 }
7463 #endif /* IXGBE_FCOE */
7464 if (pci_using_dac) {
7465 netdev->features |= NETIF_F_HIGHDMA;
7466 netdev->vlan_features |= NETIF_F_HIGHDMA;
7467 }
7468
7469 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7470 netdev->hw_features |= NETIF_F_LRO;
7471 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7472 netdev->features |= NETIF_F_LRO;
7473
7474 /* make sure the EEPROM is good */
7475 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7476 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7477 err = -EIO;
7478 goto err_sw_init;
7479 }
7480
7481 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7482 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7483
7484 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7485 e_dev_err("invalid MAC address\n");
7486 err = -EIO;
7487 goto err_sw_init;
7488 }
7489
7490 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7491 (unsigned long) adapter);
7492
7493 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7494 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7495
7496 err = ixgbe_init_interrupt_scheme(adapter);
7497 if (err)
7498 goto err_sw_init;
7499
7500 /* WOL not supported for all devices */
7501 adapter->wol = 0;
7502 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7503 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7504 adapter->wol = IXGBE_WUFC_MAG;
7505
7506 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7507
7508 /* save off EEPROM version number */
7509 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7510 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7511
7512 /* pick up the PCI bus settings for reporting later */
7513 hw->mac.ops.get_bus_info(hw);
7514
7515 /* print bus type/speed/width info */
7516 e_dev_info("(PCI Express:%s:%s) %pM\n",
7517 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7518 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7519 "Unknown"),
7520 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7521 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7522 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7523 "Unknown"),
7524 netdev->dev_addr);
7525
7526 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7527 if (err)
7528 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7529 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7530 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7531 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7532 part_str);
7533 else
7534 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7535 hw->mac.type, hw->phy.type, part_str);
7536
7537 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7538 e_dev_warn("PCI-Express bandwidth available for this card is "
7539 "not sufficient for optimal performance.\n");
7540 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7541 "is required.\n");
7542 }
7543
7544 /* reset the hardware with the new settings */
7545 err = hw->mac.ops.start_hw(hw);
7546 if (err == IXGBE_ERR_EEPROM_VERSION) {
7547 /* We are running on a pre-production device, log a warning */
7548 e_dev_warn("This device is a pre-production adapter/LOM. "
7549 "Please be aware there may be issues associated "
7550 "with your hardware. If you are experiencing "
7551 "problems please contact your Intel or hardware "
7552 "representative who provided you with this "
7553 "hardware.\n");
7554 }
7555 strcpy(netdev->name, "eth%d");
7556 err = register_netdev(netdev);
7557 if (err)
7558 goto err_register;
7559
7560 /* power down the optics for 82599 SFP+ fiber */
7561 if (hw->mac.ops.disable_tx_laser)
7562 hw->mac.ops.disable_tx_laser(hw);
7563
7564 /* carrier off reporting is important to ethtool even BEFORE open */
7565 netif_carrier_off(netdev);
7566
7567 #ifdef CONFIG_IXGBE_DCA
7568 if (dca_add_requester(&pdev->dev) == 0) {
7569 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7570 ixgbe_setup_dca(adapter);
7571 }
7572 #endif
7573 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7574 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7575 for (i = 0; i < adapter->num_vfs; i++)
7576 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7577 }
7578
7579 /* firmware requires driver version to be 0xFFFFFFFF
7580 * since os does not support feature
7581 */
7582 if (hw->mac.ops.set_fw_drv_ver)
7583 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7584 0xFF);
7585
7586 /* add san mac addr to netdev */
7587 ixgbe_add_sanmac_netdev(netdev);
7588
7589 e_dev_info("%s\n", ixgbe_default_device_descr);
7590 cards_found++;
7591
7592 #ifdef CONFIG_IXGBE_HWMON
7593 if (ixgbe_sysfs_init(adapter))
7594 e_err(probe, "failed to allocate sysfs resources\n");
7595 #endif /* CONFIG_IXGBE_HWMON */
7596
7597 #ifdef CONFIG_DEBUG_FS
7598 ixgbe_dbg_adapter_init(adapter);
7599 #endif /* CONFIG_DEBUG_FS */
7600
7601 return 0;
7602
7603 err_register:
7604 ixgbe_release_hw_control(adapter);
7605 ixgbe_clear_interrupt_scheme(adapter);
7606 err_sw_init:
7607 ixgbe_disable_sriov(adapter);
7608 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7609 iounmap(hw->hw_addr);
7610 err_ioremap:
7611 free_netdev(netdev);
7612 err_alloc_etherdev:
7613 pci_release_selected_regions(pdev,
7614 pci_select_bars(pdev, IORESOURCE_MEM));
7615 err_pci_reg:
7616 err_dma:
7617 pci_disable_device(pdev);
7618 return err;
7619 }
7620
7621 /**
7622 * ixgbe_remove - Device Removal Routine
7623 * @pdev: PCI device information struct
7624 *
7625 * ixgbe_remove is called by the PCI subsystem to alert the driver
7626 * that it should release a PCI device. The could be caused by a
7627 * Hot-Plug event, or because the driver is going to be removed from
7628 * memory.
7629 **/
7630 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7631 {
7632 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7633 struct net_device *netdev = adapter->netdev;
7634
7635 #ifdef CONFIG_DEBUG_FS
7636 ixgbe_dbg_adapter_exit(adapter);
7637 #endif /*CONFIG_DEBUG_FS */
7638
7639 set_bit(__IXGBE_DOWN, &adapter->state);
7640 cancel_work_sync(&adapter->service_task);
7641
7642
7643 #ifdef CONFIG_IXGBE_DCA
7644 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7645 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7646 dca_remove_requester(&pdev->dev);
7647 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7648 }
7649
7650 #endif
7651 #ifdef CONFIG_IXGBE_HWMON
7652 ixgbe_sysfs_exit(adapter);
7653 #endif /* CONFIG_IXGBE_HWMON */
7654
7655 /* remove the added san mac */
7656 ixgbe_del_sanmac_netdev(netdev);
7657
7658 if (netdev->reg_state == NETREG_REGISTERED)
7659 unregister_netdev(netdev);
7660
7661 ixgbe_disable_sriov(adapter);
7662
7663 ixgbe_clear_interrupt_scheme(adapter);
7664
7665 ixgbe_release_hw_control(adapter);
7666
7667 #ifdef CONFIG_DCB
7668 kfree(adapter->ixgbe_ieee_pfc);
7669 kfree(adapter->ixgbe_ieee_ets);
7670
7671 #endif
7672 iounmap(adapter->hw.hw_addr);
7673 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7674 IORESOURCE_MEM));
7675
7676 e_dev_info("complete\n");
7677
7678 free_netdev(netdev);
7679
7680 pci_disable_pcie_error_reporting(pdev);
7681
7682 pci_disable_device(pdev);
7683 }
7684
7685 /**
7686 * ixgbe_io_error_detected - called when PCI error is detected
7687 * @pdev: Pointer to PCI device
7688 * @state: The current pci connection state
7689 *
7690 * This function is called after a PCI bus error affecting
7691 * this device has been detected.
7692 */
7693 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7694 pci_channel_state_t state)
7695 {
7696 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7697 struct net_device *netdev = adapter->netdev;
7698
7699 #ifdef CONFIG_PCI_IOV
7700 struct pci_dev *bdev, *vfdev;
7701 u32 dw0, dw1, dw2, dw3;
7702 int vf, pos;
7703 u16 req_id, pf_func;
7704
7705 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7706 adapter->num_vfs == 0)
7707 goto skip_bad_vf_detection;
7708
7709 bdev = pdev->bus->self;
7710 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7711 bdev = bdev->bus->self;
7712
7713 if (!bdev)
7714 goto skip_bad_vf_detection;
7715
7716 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7717 if (!pos)
7718 goto skip_bad_vf_detection;
7719
7720 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7721 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7722 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7723 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7724
7725 req_id = dw1 >> 16;
7726 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7727 if (!(req_id & 0x0080))
7728 goto skip_bad_vf_detection;
7729
7730 pf_func = req_id & 0x01;
7731 if ((pf_func & 1) == (pdev->devfn & 1)) {
7732 unsigned int device_id;
7733
7734 vf = (req_id & 0x7F) >> 1;
7735 e_dev_err("VF %d has caused a PCIe error\n", vf);
7736 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7737 "%8.8x\tdw3: %8.8x\n",
7738 dw0, dw1, dw2, dw3);
7739 switch (adapter->hw.mac.type) {
7740 case ixgbe_mac_82599EB:
7741 device_id = IXGBE_82599_VF_DEVICE_ID;
7742 break;
7743 case ixgbe_mac_X540:
7744 device_id = IXGBE_X540_VF_DEVICE_ID;
7745 break;
7746 default:
7747 device_id = 0;
7748 break;
7749 }
7750
7751 /* Find the pci device of the offending VF */
7752 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7753 while (vfdev) {
7754 if (vfdev->devfn == (req_id & 0xFF))
7755 break;
7756 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7757 device_id, vfdev);
7758 }
7759 /*
7760 * There's a slim chance the VF could have been hot plugged,
7761 * so if it is no longer present we don't need to issue the
7762 * VFLR. Just clean up the AER in that case.
7763 */
7764 if (vfdev) {
7765 e_dev_err("Issuing VFLR to VF %d\n", vf);
7766 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7767 }
7768
7769 pci_cleanup_aer_uncorrect_error_status(pdev);
7770 }
7771
7772 /*
7773 * Even though the error may have occurred on the other port
7774 * we still need to increment the vf error reference count for
7775 * both ports because the I/O resume function will be called
7776 * for both of them.
7777 */
7778 adapter->vferr_refcount++;
7779
7780 return PCI_ERS_RESULT_RECOVERED;
7781
7782 skip_bad_vf_detection:
7783 #endif /* CONFIG_PCI_IOV */
7784 netif_device_detach(netdev);
7785
7786 if (state == pci_channel_io_perm_failure)
7787 return PCI_ERS_RESULT_DISCONNECT;
7788
7789 if (netif_running(netdev))
7790 ixgbe_down(adapter);
7791 pci_disable_device(pdev);
7792
7793 /* Request a slot reset. */
7794 return PCI_ERS_RESULT_NEED_RESET;
7795 }
7796
7797 /**
7798 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7799 * @pdev: Pointer to PCI device
7800 *
7801 * Restart the card from scratch, as if from a cold-boot.
7802 */
7803 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7804 {
7805 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7806 pci_ers_result_t result;
7807 int err;
7808
7809 if (pci_enable_device_mem(pdev)) {
7810 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7811 result = PCI_ERS_RESULT_DISCONNECT;
7812 } else {
7813 pci_set_master(pdev);
7814 pci_restore_state(pdev);
7815 pci_save_state(pdev);
7816
7817 pci_wake_from_d3(pdev, false);
7818
7819 ixgbe_reset(adapter);
7820 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7821 result = PCI_ERS_RESULT_RECOVERED;
7822 }
7823
7824 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7825 if (err) {
7826 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7827 "failed 0x%0x\n", err);
7828 /* non-fatal, continue */
7829 }
7830
7831 return result;
7832 }
7833
7834 /**
7835 * ixgbe_io_resume - called when traffic can start flowing again.
7836 * @pdev: Pointer to PCI device
7837 *
7838 * This callback is called when the error recovery driver tells us that
7839 * its OK to resume normal operation.
7840 */
7841 static void ixgbe_io_resume(struct pci_dev *pdev)
7842 {
7843 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7844 struct net_device *netdev = adapter->netdev;
7845
7846 #ifdef CONFIG_PCI_IOV
7847 if (adapter->vferr_refcount) {
7848 e_info(drv, "Resuming after VF err\n");
7849 adapter->vferr_refcount--;
7850 return;
7851 }
7852
7853 #endif
7854 if (netif_running(netdev))
7855 ixgbe_up(adapter);
7856
7857 netif_device_attach(netdev);
7858 }
7859
7860 static const struct pci_error_handlers ixgbe_err_handler = {
7861 .error_detected = ixgbe_io_error_detected,
7862 .slot_reset = ixgbe_io_slot_reset,
7863 .resume = ixgbe_io_resume,
7864 };
7865
7866 static struct pci_driver ixgbe_driver = {
7867 .name = ixgbe_driver_name,
7868 .id_table = ixgbe_pci_tbl,
7869 .probe = ixgbe_probe,
7870 .remove = __devexit_p(ixgbe_remove),
7871 #ifdef CONFIG_PM
7872 .suspend = ixgbe_suspend,
7873 .resume = ixgbe_resume,
7874 #endif
7875 .shutdown = ixgbe_shutdown,
7876 .err_handler = &ixgbe_err_handler
7877 };
7878
7879 /**
7880 * ixgbe_init_module - Driver Registration Routine
7881 *
7882 * ixgbe_init_module is the first routine called when the driver is
7883 * loaded. All it does is register with the PCI subsystem.
7884 **/
7885 static int __init ixgbe_init_module(void)
7886 {
7887 int ret;
7888 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7889 pr_info("%s\n", ixgbe_copyright);
7890
7891 #ifdef CONFIG_DEBUG_FS
7892 ixgbe_dbg_init();
7893 #endif /* CONFIG_DEBUG_FS */
7894
7895 #ifdef CONFIG_IXGBE_DCA
7896 dca_register_notify(&dca_notifier);
7897 #endif
7898
7899 ret = pci_register_driver(&ixgbe_driver);
7900 return ret;
7901 }
7902
7903 module_init(ixgbe_init_module);
7904
7905 /**
7906 * ixgbe_exit_module - Driver Exit Cleanup Routine
7907 *
7908 * ixgbe_exit_module is called just before the driver is removed
7909 * from memory.
7910 **/
7911 static void __exit ixgbe_exit_module(void)
7912 {
7913 #ifdef CONFIG_IXGBE_DCA
7914 dca_unregister_notify(&dca_notifier);
7915 #endif
7916 pci_unregister_driver(&ixgbe_driver);
7917
7918 #ifdef CONFIG_DEBUG_FS
7919 ixgbe_dbg_exit();
7920 #endif /* CONFIG_DEBUG_FS */
7921
7922 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7923 }
7924
7925 #ifdef CONFIG_IXGBE_DCA
7926 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7927 void *p)
7928 {
7929 int ret_val;
7930
7931 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7932 __ixgbe_notify_dca);
7933
7934 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7935 }
7936
7937 #endif /* CONFIG_IXGBE_DCA */
7938
7939 module_exit(ixgbe_exit_module);
7940
7941 /* ixgbe_main.c */
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