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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 9
67 #define BUILD 15
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
118 {0, }
119 };
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 void *p);
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129 };
130 #endif
131
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
137 #endif /* CONFIG_PCI_IOV */
138
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155 {
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159 }
160
161 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162 {
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
165 /* flush memory to make sure state is correct before next watchdog */
166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168 }
169
170 struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173 };
174
175 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205 };
206
207
208 /*
209 * ixgbe_regdump - register printout routine
210 */
211 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212 {
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
275 pr_info("%-15s %08x\n", reginfo->name,
276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
282 pr_err("%-15s", rname);
283 for (j = 0; j < 8; j++)
284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
286 }
287
288 }
289
290 /*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293 static void ixgbe_dump(struct ixgbe_adapter *adapter)
294 {
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
300 struct ixgbe_tx_buffer *tx_buffer;
301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
315 pr_info("Device Name state "
316 "trans_start last_rx\n");
317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
326 pr_info(" Register Name Value\n");
327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
377 tx_buffer = &tx_ring->tx_buffer_info[i];
378 u0 = (struct my_u0 *)tx_desc;
379 pr_info("T [0x%03X] %016llX %016llX %016llX"
380 " %04X %p %016llX %p", i,
381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
390 pr_cont(" NTC/U\n");
391 else if (i == tx_ring->next_to_use)
392 pr_cont(" NTU\n");
393 else if (i == tx_ring->next_to_clean)
394 pr_cont(" NTC\n");
395 else
396 pr_cont("\n");
397
398 if (netif_msg_pktdata(adapter) &&
399 dma_unmap_len(tx_buffer, len) != 0)
400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
406 }
407 }
408
409 /* Print RX Rings Summary */
410 rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
412 pr_info("Queue [NTU] [NTC]\n");
413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
464 pr_info("RWB[0x%03X] %016llX "
465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
470 pr_info("R [0x%03X] %016llX "
471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
481 ixgbe_rx_bufsz(rx_ring), true);
482 }
483 }
484
485 if (i == rx_ring->next_to_use)
486 pr_cont(" NTU\n");
487 else if (i == rx_ring->next_to_clean)
488 pr_cont(" NTC\n");
489 else
490 pr_cont("\n");
491
492 }
493 }
494
495 exit:
496 return;
497 }
498
499 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 {
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
507 }
508
509 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 {
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 }
518
519 /*
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
528 u8 queue, u8 msix_vector)
529 {
530 u32 ivar, index;
531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X540:
545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
570 u64 qmask)
571 {
572 u32 mask;
573
574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
578 break;
579 case ixgbe_mac_82599EB:
580 case ixgbe_mac_X540:
581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
585 break;
586 default:
587 break;
588 }
589 }
590
591 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
593 {
594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
597 dma_unmap_single(ring->dev,
598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
606 }
607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
611 }
612
613 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
614 {
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 int i;
618 u32 data;
619
620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
623
624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
632
633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
635 return;
636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640 }
641
642 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643 {
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
655 return;
656 }
657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
663 break;
664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
666 }
667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
673 u8 tc = tx_ring->dcb_tc;
674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
677 }
678 }
679
680 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
681 {
682 return ring->stats.packets;
683 }
684
685 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686 {
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
688 struct ixgbe_hw *hw = &adapter->hw;
689
690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698 }
699
700 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701 {
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
707 clear_check_for_tx_hang(tx_ring);
708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
730 }
731
732 return ret;
733 }
734
735 /**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740 {
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747 }
748
749 /**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
751 * @q_vector: structure containing interrupt and ring information
752 * @tx_ring: tx ring to clean
753 **/
754 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
755 struct ixgbe_ring *tx_ring)
756 {
757 struct ixgbe_adapter *adapter = q_vector->adapter;
758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
760 unsigned int total_bytes = 0, total_packets = 0;
761 unsigned int budget = q_vector->tx.work_limit;
762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
766
767 tx_buffer = &tx_ring->tx_buffer_info[i];
768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
769 i -= tx_ring->count;
770
771 do {
772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
784
785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
787
788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
792 #ifdef CONFIG_IXGBE_PTP
793 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
794 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
795 #endif
796
797 /* free the skb */
798 dev_kfree_skb_any(tx_buffer->skb);
799
800 /* unmap skb header data */
801 dma_unmap_single(tx_ring->dev,
802 dma_unmap_addr(tx_buffer, dma),
803 dma_unmap_len(tx_buffer, len),
804 DMA_TO_DEVICE);
805
806 /* clear tx_buffer data */
807 tx_buffer->skb = NULL;
808 dma_unmap_len_set(tx_buffer, len, 0);
809
810 /* unmap remaining buffers */
811 while (tx_desc != eop_desc) {
812 tx_buffer++;
813 tx_desc++;
814 i++;
815 if (unlikely(!i)) {
816 i -= tx_ring->count;
817 tx_buffer = tx_ring->tx_buffer_info;
818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
819 }
820
821 /* unmap any remaining paged data */
822 if (dma_unmap_len(tx_buffer, len)) {
823 dma_unmap_page(tx_ring->dev,
824 dma_unmap_addr(tx_buffer, dma),
825 dma_unmap_len(tx_buffer, len),
826 DMA_TO_DEVICE);
827 dma_unmap_len_set(tx_buffer, len, 0);
828 }
829 }
830
831 /* move us one more past the eop_desc for start of next pkt */
832 tx_buffer++;
833 tx_desc++;
834 i++;
835 if (unlikely(!i)) {
836 i -= tx_ring->count;
837 tx_buffer = tx_ring->tx_buffer_info;
838 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
839 }
840
841 /* issue prefetch for next Tx descriptor */
842 prefetch(tx_desc);
843
844 /* update budget accounting */
845 budget--;
846 } while (likely(budget));
847
848 i += tx_ring->count;
849 tx_ring->next_to_clean = i;
850 u64_stats_update_begin(&tx_ring->syncp);
851 tx_ring->stats.bytes += total_bytes;
852 tx_ring->stats.packets += total_packets;
853 u64_stats_update_end(&tx_ring->syncp);
854 q_vector->tx.total_bytes += total_bytes;
855 q_vector->tx.total_packets += total_packets;
856
857 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
858 /* schedule immediate reset if we believe we hung */
859 struct ixgbe_hw *hw = &adapter->hw;
860 e_err(drv, "Detected Tx Unit Hang\n"
861 " Tx Queue <%d>\n"
862 " TDH, TDT <%x>, <%x>\n"
863 " next_to_use <%x>\n"
864 " next_to_clean <%x>\n"
865 "tx_buffer_info[next_to_clean]\n"
866 " time_stamp <%lx>\n"
867 " jiffies <%lx>\n",
868 tx_ring->queue_index,
869 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
870 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
871 tx_ring->next_to_use, i,
872 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
873
874 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
875
876 e_info(probe,
877 "tx hang %d detected on queue %d, resetting adapter\n",
878 adapter->tx_timeout_count + 1, tx_ring->queue_index);
879
880 /* schedule immediate reset if we believe we hung */
881 ixgbe_tx_timeout_reset(adapter);
882
883 /* the adapter is about to reset, no point in enabling stuff */
884 return true;
885 }
886
887 netdev_tx_completed_queue(txring_txq(tx_ring),
888 total_packets, total_bytes);
889
890 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
891 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
892 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
893 /* Make sure that anybody stopping the queue after this
894 * sees the new next_to_clean.
895 */
896 smp_mb();
897 if (__netif_subqueue_stopped(tx_ring->netdev,
898 tx_ring->queue_index)
899 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
900 netif_wake_subqueue(tx_ring->netdev,
901 tx_ring->queue_index);
902 ++tx_ring->tx_stats.restart_queue;
903 }
904 }
905
906 return !!budget;
907 }
908
909 #ifdef CONFIG_IXGBE_DCA
910 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
911 struct ixgbe_ring *tx_ring,
912 int cpu)
913 {
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
916 u16 reg_offset;
917
918 switch (hw->mac.type) {
919 case ixgbe_mac_82598EB:
920 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
921 break;
922 case ixgbe_mac_82599EB:
923 case ixgbe_mac_X540:
924 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
925 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
926 break;
927 default:
928 /* for unknown hardware do not write register */
929 return;
930 }
931
932 /*
933 * We can enable relaxed ordering for reads, but not writes when
934 * DCA is enabled. This is due to a known issue in some chipsets
935 * which will cause the DCA tag to be cleared.
936 */
937 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
938 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
939 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940
941 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
942 }
943
944 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *rx_ring,
946 int cpu)
947 {
948 struct ixgbe_hw *hw = &adapter->hw;
949 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
950 u8 reg_idx = rx_ring->reg_idx;
951
952
953 switch (hw->mac.type) {
954 case ixgbe_mac_82599EB:
955 case ixgbe_mac_X540:
956 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
957 break;
958 default:
959 break;
960 }
961
962 /*
963 * We can enable relaxed ordering for reads, but not writes when
964 * DCA is enabled. This is due to a known issue in some chipsets
965 * which will cause the DCA tag to be cleared.
966 */
967 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
968 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
969 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
970
971 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
972 }
973
974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975 {
976 struct ixgbe_adapter *adapter = q_vector->adapter;
977 struct ixgbe_ring *ring;
978 int cpu = get_cpu();
979
980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
983 ixgbe_for_each_ring(ring, q_vector->tx)
984 ixgbe_update_tx_dca(adapter, ring, cpu);
985
986 ixgbe_for_each_ring(ring, q_vector->rx)
987 ixgbe_update_rx_dca(adapter, ring, cpu);
988
989 q_vector->cpu = cpu;
990 out_no_update:
991 put_cpu();
992 }
993
994 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995 {
996 int num_q_vectors;
997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
1005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1006 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1007 else
1008 num_q_vectors = 1;
1009
1010 for (i = 0; i < num_q_vectors; i++) {
1011 adapter->q_vector[i]->cpu = -1;
1012 ixgbe_update_dca(adapter->q_vector[i]);
1013 }
1014 }
1015
1016 static int __ixgbe_notify_dca(struct device *dev, void *data)
1017 {
1018 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1019 unsigned long event = *(unsigned long *)data;
1020
1021 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1022 return 0;
1023
1024 switch (event) {
1025 case DCA_PROVIDER_ADD:
1026 /* if we're already enabled, don't do it again */
1027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1028 break;
1029 if (dca_add_requester(dev) == 0) {
1030 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1031 ixgbe_setup_dca(adapter);
1032 break;
1033 }
1034 /* Fall Through since DCA is disabled. */
1035 case DCA_PROVIDER_REMOVE:
1036 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1037 dca_remove_requester(dev);
1038 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1040 }
1041 break;
1042 }
1043
1044 return 0;
1045 }
1046
1047 #endif /* CONFIG_IXGBE_DCA */
1048 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1049 union ixgbe_adv_rx_desc *rx_desc,
1050 struct sk_buff *skb)
1051 {
1052 if (ring->netdev->features & NETIF_F_RXHASH)
1053 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1054 }
1055
1056 #ifdef IXGBE_FCOE
1057 /**
1058 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1059 * @adapter: address of board private structure
1060 * @rx_desc: advanced rx descriptor
1061 *
1062 * Returns : true if it is FCoE pkt
1063 */
1064 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1065 union ixgbe_adv_rx_desc *rx_desc)
1066 {
1067 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1068
1069 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1070 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1071 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1072 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1073 }
1074
1075 #endif /* IXGBE_FCOE */
1076 /**
1077 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1078 * @ring: structure containing ring specific data
1079 * @rx_desc: current Rx descriptor being processed
1080 * @skb: skb currently being received and modified
1081 **/
1082 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1083 union ixgbe_adv_rx_desc *rx_desc,
1084 struct sk_buff *skb)
1085 {
1086 skb_checksum_none_assert(skb);
1087
1088 /* Rx csum disabled */
1089 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1090 return;
1091
1092 /* if IP and error */
1093 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1094 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1095 ring->rx_stats.csum_err++;
1096 return;
1097 }
1098
1099 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1100 return;
1101
1102 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1103 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1104
1105 /*
1106 * 82599 errata, UDP frames with a 0 checksum can be marked as
1107 * checksum errors.
1108 */
1109 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1110 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1111 return;
1112
1113 ring->rx_stats.csum_err++;
1114 return;
1115 }
1116
1117 /* It must be a TCP or UDP packet with a valid checksum */
1118 skb->ip_summed = CHECKSUM_UNNECESSARY;
1119 }
1120
1121 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1122 {
1123 rx_ring->next_to_use = val;
1124
1125 /* update next to alloc since we have filled the ring */
1126 rx_ring->next_to_alloc = val;
1127 /*
1128 * Force memory writes to complete before letting h/w
1129 * know there are new descriptors to fetch. (Only
1130 * applicable for weak-ordered memory model archs,
1131 * such as IA-64).
1132 */
1133 wmb();
1134 writel(val, rx_ring->tail);
1135 }
1136
1137 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1138 struct ixgbe_rx_buffer *bi)
1139 {
1140 struct page *page = bi->page;
1141 dma_addr_t dma = bi->dma;
1142
1143 /* since we are recycling buffers we should seldom need to alloc */
1144 if (likely(dma))
1145 return true;
1146
1147 /* alloc new page for storage */
1148 if (likely(!page)) {
1149 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1150 ixgbe_rx_pg_order(rx_ring));
1151 if (unlikely(!page)) {
1152 rx_ring->rx_stats.alloc_rx_page_failed++;
1153 return false;
1154 }
1155 bi->page = page;
1156 }
1157
1158 /* map page for use */
1159 dma = dma_map_page(rx_ring->dev, page, 0,
1160 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1161
1162 /*
1163 * if mapping failed free memory back to system since
1164 * there isn't much point in holding memory we can't use
1165 */
1166 if (dma_mapping_error(rx_ring->dev, dma)) {
1167 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1168 bi->page = NULL;
1169
1170 rx_ring->rx_stats.alloc_rx_page_failed++;
1171 return false;
1172 }
1173
1174 bi->dma = dma;
1175 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1176
1177 return true;
1178 }
1179
1180 /**
1181 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1182 * @rx_ring: ring to place buffers on
1183 * @cleaned_count: number of buffers to replace
1184 **/
1185 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1186 {
1187 union ixgbe_adv_rx_desc *rx_desc;
1188 struct ixgbe_rx_buffer *bi;
1189 u16 i = rx_ring->next_to_use;
1190
1191 /* nothing to do */
1192 if (!cleaned_count)
1193 return;
1194
1195 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1196 bi = &rx_ring->rx_buffer_info[i];
1197 i -= rx_ring->count;
1198
1199 do {
1200 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1201 break;
1202
1203 /*
1204 * Refresh the desc even if buffer_addrs didn't change
1205 * because each write-back erases this info.
1206 */
1207 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1208
1209 rx_desc++;
1210 bi++;
1211 i++;
1212 if (unlikely(!i)) {
1213 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1214 bi = rx_ring->rx_buffer_info;
1215 i -= rx_ring->count;
1216 }
1217
1218 /* clear the hdr_addr for the next_to_use descriptor */
1219 rx_desc->read.hdr_addr = 0;
1220
1221 cleaned_count--;
1222 } while (cleaned_count);
1223
1224 i += rx_ring->count;
1225
1226 if (rx_ring->next_to_use != i)
1227 ixgbe_release_rx_desc(rx_ring, i);
1228 }
1229
1230 /**
1231 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1232 * @data: pointer to the start of the headers
1233 * @max_len: total length of section to find headers in
1234 *
1235 * This function is meant to determine the length of headers that will
1236 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1237 * motivation of doing this is to only perform one pull for IPv4 TCP
1238 * packets so that we can do basic things like calculating the gso_size
1239 * based on the average data per packet.
1240 **/
1241 static unsigned int ixgbe_get_headlen(unsigned char *data,
1242 unsigned int max_len)
1243 {
1244 union {
1245 unsigned char *network;
1246 /* l2 headers */
1247 struct ethhdr *eth;
1248 struct vlan_hdr *vlan;
1249 /* l3 headers */
1250 struct iphdr *ipv4;
1251 } hdr;
1252 __be16 protocol;
1253 u8 nexthdr = 0; /* default to not TCP */
1254 u8 hlen;
1255
1256 /* this should never happen, but better safe than sorry */
1257 if (max_len < ETH_HLEN)
1258 return max_len;
1259
1260 /* initialize network frame pointer */
1261 hdr.network = data;
1262
1263 /* set first protocol and move network header forward */
1264 protocol = hdr.eth->h_proto;
1265 hdr.network += ETH_HLEN;
1266
1267 /* handle any vlan tag if present */
1268 if (protocol == __constant_htons(ETH_P_8021Q)) {
1269 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1270 return max_len;
1271
1272 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1273 hdr.network += VLAN_HLEN;
1274 }
1275
1276 /* handle L3 protocols */
1277 if (protocol == __constant_htons(ETH_P_IP)) {
1278 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1279 return max_len;
1280
1281 /* access ihl as a u8 to avoid unaligned access on ia64 */
1282 hlen = (hdr.network[0] & 0x0F) << 2;
1283
1284 /* verify hlen meets minimum size requirements */
1285 if (hlen < sizeof(struct iphdr))
1286 return hdr.network - data;
1287
1288 /* record next protocol */
1289 nexthdr = hdr.ipv4->protocol;
1290 hdr.network += hlen;
1291 #ifdef IXGBE_FCOE
1292 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1293 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1294 return max_len;
1295 hdr.network += FCOE_HEADER_LEN;
1296 #endif
1297 } else {
1298 return hdr.network - data;
1299 }
1300
1301 /* finally sort out TCP */
1302 if (nexthdr == IPPROTO_TCP) {
1303 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1304 return max_len;
1305
1306 /* access doff as a u8 to avoid unaligned access on ia64 */
1307 hlen = (hdr.network[12] & 0xF0) >> 2;
1308
1309 /* verify hlen meets minimum size requirements */
1310 if (hlen < sizeof(struct tcphdr))
1311 return hdr.network - data;
1312
1313 hdr.network += hlen;
1314 }
1315
1316 /*
1317 * If everything has gone correctly hdr.network should be the
1318 * data section of the packet and will be the end of the header.
1319 * If not then it probably represents the end of the last recognized
1320 * header.
1321 */
1322 if ((hdr.network - data) < max_len)
1323 return hdr.network - data;
1324 else
1325 return max_len;
1326 }
1327
1328 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1329 union ixgbe_adv_rx_desc *rx_desc,
1330 struct sk_buff *skb)
1331 {
1332 __le32 rsc_enabled;
1333 u32 rsc_cnt;
1334
1335 if (!ring_is_rsc_enabled(rx_ring))
1336 return;
1337
1338 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1339 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1340
1341 /* If this is an RSC frame rsc_cnt should be non-zero */
1342 if (!rsc_enabled)
1343 return;
1344
1345 rsc_cnt = le32_to_cpu(rsc_enabled);
1346 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1347
1348 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1349 }
1350
1351 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1352 struct sk_buff *skb)
1353 {
1354 u16 hdr_len = skb_headlen(skb);
1355
1356 /* set gso_size to avoid messing up TCP MSS */
1357 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1358 IXGBE_CB(skb)->append_cnt);
1359 }
1360
1361 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1362 struct sk_buff *skb)
1363 {
1364 /* if append_cnt is 0 then frame is not RSC */
1365 if (!IXGBE_CB(skb)->append_cnt)
1366 return;
1367
1368 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1369 rx_ring->rx_stats.rsc_flush++;
1370
1371 ixgbe_set_rsc_gso_size(rx_ring, skb);
1372
1373 /* gso_size is computed using append_cnt so always clear it last */
1374 IXGBE_CB(skb)->append_cnt = 0;
1375 }
1376
1377 /**
1378 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1379 * @rx_ring: rx descriptor ring packet is being transacted on
1380 * @rx_desc: pointer to the EOP Rx descriptor
1381 * @skb: pointer to current skb being populated
1382 *
1383 * This function checks the ring, descriptor, and packet information in
1384 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1385 * other fields within the skb.
1386 **/
1387 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1388 union ixgbe_adv_rx_desc *rx_desc,
1389 struct sk_buff *skb)
1390 {
1391 struct net_device *dev = rx_ring->netdev;
1392
1393 ixgbe_update_rsc_stats(rx_ring, skb);
1394
1395 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1396
1397 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1398
1399 #ifdef CONFIG_IXGBE_PTP
1400 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1401 #endif
1402
1403 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1404 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1405 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1406 __vlan_hwaccel_put_tag(skb, vid);
1407 }
1408
1409 skb_record_rx_queue(skb, rx_ring->queue_index);
1410
1411 skb->protocol = eth_type_trans(skb, dev);
1412 }
1413
1414 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1415 struct sk_buff *skb)
1416 {
1417 struct ixgbe_adapter *adapter = q_vector->adapter;
1418
1419 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1420 napi_gro_receive(&q_vector->napi, skb);
1421 else
1422 netif_rx(skb);
1423 }
1424
1425 /**
1426 * ixgbe_is_non_eop - process handling of non-EOP buffers
1427 * @rx_ring: Rx ring being processed
1428 * @rx_desc: Rx descriptor for current buffer
1429 * @skb: Current socket buffer containing buffer in progress
1430 *
1431 * This function updates next to clean. If the buffer is an EOP buffer
1432 * this function exits returning false, otherwise it will place the
1433 * sk_buff in the next buffer to be chained and return true indicating
1434 * that this is in fact a non-EOP buffer.
1435 **/
1436 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1437 union ixgbe_adv_rx_desc *rx_desc,
1438 struct sk_buff *skb)
1439 {
1440 u32 ntc = rx_ring->next_to_clean + 1;
1441
1442 /* fetch, update, and store next to clean */
1443 ntc = (ntc < rx_ring->count) ? ntc : 0;
1444 rx_ring->next_to_clean = ntc;
1445
1446 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1447
1448 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1449 return false;
1450
1451 /* append_cnt indicates packet is RSC, if so fetch nextp */
1452 if (IXGBE_CB(skb)->append_cnt) {
1453 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1454 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1455 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1456 }
1457
1458 /* place skb in next buffer to be received */
1459 rx_ring->rx_buffer_info[ntc].skb = skb;
1460 rx_ring->rx_stats.non_eop_descs++;
1461
1462 return true;
1463 }
1464
1465 /**
1466 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1467 * @rx_ring: rx descriptor ring packet is being transacted on
1468 * @rx_desc: pointer to the EOP Rx descriptor
1469 * @skb: pointer to current skb being fixed
1470 *
1471 * Check for corrupted packet headers caused by senders on the local L2
1472 * embedded NIC switch not setting up their Tx Descriptors right. These
1473 * should be very rare.
1474 *
1475 * Also address the case where we are pulling data in on pages only
1476 * and as such no data is present in the skb header.
1477 *
1478 * In addition if skb is not at least 60 bytes we need to pad it so that
1479 * it is large enough to qualify as a valid Ethernet frame.
1480 *
1481 * Returns true if an error was encountered and skb was freed.
1482 **/
1483 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1484 union ixgbe_adv_rx_desc *rx_desc,
1485 struct sk_buff *skb)
1486 {
1487 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1488 struct net_device *netdev = rx_ring->netdev;
1489 unsigned char *va;
1490 unsigned int pull_len;
1491
1492 /* if the page was released unmap it, else just sync our portion */
1493 if (unlikely(IXGBE_CB(skb)->page_released)) {
1494 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1495 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1496 IXGBE_CB(skb)->page_released = false;
1497 } else {
1498 dma_sync_single_range_for_cpu(rx_ring->dev,
1499 IXGBE_CB(skb)->dma,
1500 frag->page_offset,
1501 ixgbe_rx_bufsz(rx_ring),
1502 DMA_FROM_DEVICE);
1503 }
1504 IXGBE_CB(skb)->dma = 0;
1505
1506 /* verify that the packet does not have any known errors */
1507 if (unlikely(ixgbe_test_staterr(rx_desc,
1508 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1509 !(netdev->features & NETIF_F_RXALL))) {
1510 dev_kfree_skb_any(skb);
1511 return true;
1512 }
1513
1514 /*
1515 * it is valid to use page_address instead of kmap since we are
1516 * working with pages allocated out of the lomem pool per
1517 * alloc_page(GFP_ATOMIC)
1518 */
1519 va = skb_frag_address(frag);
1520
1521 /*
1522 * we need the header to contain the greater of either ETH_HLEN or
1523 * 60 bytes if the skb->len is less than 60 for skb_pad.
1524 */
1525 pull_len = skb_frag_size(frag);
1526 if (pull_len > 256)
1527 pull_len = ixgbe_get_headlen(va, pull_len);
1528
1529 /* align pull length to size of long to optimize memcpy performance */
1530 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1531
1532 /* update all of the pointers */
1533 skb_frag_size_sub(frag, pull_len);
1534 frag->page_offset += pull_len;
1535 skb->data_len -= pull_len;
1536 skb->tail += pull_len;
1537
1538 /*
1539 * if we sucked the frag empty then we should free it,
1540 * if there are other frags here something is screwed up in hardware
1541 */
1542 if (skb_frag_size(frag) == 0) {
1543 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1544 skb_shinfo(skb)->nr_frags = 0;
1545 __skb_frag_unref(frag);
1546 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1547 }
1548
1549 /* if skb_pad returns an error the skb was freed */
1550 if (unlikely(skb->len < 60)) {
1551 int pad_len = 60 - skb->len;
1552
1553 if (skb_pad(skb, pad_len))
1554 return true;
1555 __skb_put(skb, pad_len);
1556 }
1557
1558 return false;
1559 }
1560
1561 /**
1562 * ixgbe_can_reuse_page - determine if we can reuse a page
1563 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1564 *
1565 * Returns true if page can be reused in another Rx buffer
1566 **/
1567 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1568 {
1569 struct page *page = rx_buffer->page;
1570
1571 /* if we are only owner of page and it is local we can reuse it */
1572 return likely(page_count(page) == 1) &&
1573 likely(page_to_nid(page) == numa_node_id());
1574 }
1575
1576 /**
1577 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1578 * @rx_ring: rx descriptor ring to store buffers on
1579 * @old_buff: donor buffer to have page reused
1580 *
1581 * Syncronizes page for reuse by the adapter
1582 **/
1583 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1584 struct ixgbe_rx_buffer *old_buff)
1585 {
1586 struct ixgbe_rx_buffer *new_buff;
1587 u16 nta = rx_ring->next_to_alloc;
1588 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1589
1590 new_buff = &rx_ring->rx_buffer_info[nta];
1591
1592 /* update, and store next to alloc */
1593 nta++;
1594 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1595
1596 /* transfer page from old buffer to new buffer */
1597 new_buff->page = old_buff->page;
1598 new_buff->dma = old_buff->dma;
1599
1600 /* flip page offset to other buffer and store to new_buff */
1601 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1602
1603 /* sync the buffer for use by the device */
1604 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1605 new_buff->page_offset, bufsz,
1606 DMA_FROM_DEVICE);
1607
1608 /* bump ref count on page before it is given to the stack */
1609 get_page(new_buff->page);
1610 }
1611
1612 /**
1613 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1614 * @rx_ring: rx descriptor ring to transact packets on
1615 * @rx_buffer: buffer containing page to add
1616 * @rx_desc: descriptor containing length of buffer written by hardware
1617 * @skb: sk_buff to place the data into
1618 *
1619 * This function is based on skb_add_rx_frag. I would have used that
1620 * function however it doesn't handle the truesize case correctly since we
1621 * are allocating more memory than might be used for a single receive.
1622 **/
1623 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1624 struct ixgbe_rx_buffer *rx_buffer,
1625 struct sk_buff *skb, int size)
1626 {
1627 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1628 rx_buffer->page, rx_buffer->page_offset,
1629 size);
1630 skb->len += size;
1631 skb->data_len += size;
1632 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1633 }
1634
1635 /**
1636 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1637 * @q_vector: structure containing interrupt and ring information
1638 * @rx_ring: rx descriptor ring to transact packets on
1639 * @budget: Total limit on number of packets to process
1640 *
1641 * This function provides a "bounce buffer" approach to Rx interrupt
1642 * processing. The advantage to this is that on systems that have
1643 * expensive overhead for IOMMU access this provides a means of avoiding
1644 * it by maintaining the mapping of the page to the syste.
1645 *
1646 * Returns true if all work is completed without reaching budget
1647 **/
1648 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1649 struct ixgbe_ring *rx_ring,
1650 int budget)
1651 {
1652 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1653 #ifdef IXGBE_FCOE
1654 struct ixgbe_adapter *adapter = q_vector->adapter;
1655 int ddp_bytes = 0;
1656 #endif /* IXGBE_FCOE */
1657 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1658
1659 do {
1660 struct ixgbe_rx_buffer *rx_buffer;
1661 union ixgbe_adv_rx_desc *rx_desc;
1662 struct sk_buff *skb;
1663 struct page *page;
1664 u16 ntc;
1665
1666 /* return some buffers to hardware, one at a time is too slow */
1667 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1668 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1669 cleaned_count = 0;
1670 }
1671
1672 ntc = rx_ring->next_to_clean;
1673 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1674 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1675
1676 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1677 break;
1678
1679 /*
1680 * This memory barrier is needed to keep us from reading
1681 * any other fields out of the rx_desc until we know the
1682 * RXD_STAT_DD bit is set
1683 */
1684 rmb();
1685
1686 page = rx_buffer->page;
1687 prefetchw(page);
1688
1689 skb = rx_buffer->skb;
1690
1691 if (likely(!skb)) {
1692 void *page_addr = page_address(page) +
1693 rx_buffer->page_offset;
1694
1695 /* prefetch first cache line of first page */
1696 prefetch(page_addr);
1697 #if L1_CACHE_BYTES < 128
1698 prefetch(page_addr + L1_CACHE_BYTES);
1699 #endif
1700
1701 /* allocate a skb to store the frags */
1702 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1703 IXGBE_RX_HDR_SIZE);
1704 if (unlikely(!skb)) {
1705 rx_ring->rx_stats.alloc_rx_buff_failed++;
1706 break;
1707 }
1708
1709 /*
1710 * we will be copying header into skb->data in
1711 * pskb_may_pull so it is in our interest to prefetch
1712 * it now to avoid a possible cache miss
1713 */
1714 prefetchw(skb->data);
1715
1716 /*
1717 * Delay unmapping of the first packet. It carries the
1718 * header information, HW may still access the header
1719 * after the writeback. Only unmap it when EOP is
1720 * reached
1721 */
1722 IXGBE_CB(skb)->dma = rx_buffer->dma;
1723 } else {
1724 /* we are reusing so sync this buffer for CPU use */
1725 dma_sync_single_range_for_cpu(rx_ring->dev,
1726 rx_buffer->dma,
1727 rx_buffer->page_offset,
1728 ixgbe_rx_bufsz(rx_ring),
1729 DMA_FROM_DEVICE);
1730 }
1731
1732 /* pull page into skb */
1733 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1734 le16_to_cpu(rx_desc->wb.upper.length));
1735
1736 if (ixgbe_can_reuse_page(rx_buffer)) {
1737 /* hand second half of page back to the ring */
1738 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1739 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1740 /* the page has been released from the ring */
1741 IXGBE_CB(skb)->page_released = true;
1742 } else {
1743 /* we are not reusing the buffer so unmap it */
1744 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1745 ixgbe_rx_pg_size(rx_ring),
1746 DMA_FROM_DEVICE);
1747 }
1748
1749 /* clear contents of buffer_info */
1750 rx_buffer->skb = NULL;
1751 rx_buffer->dma = 0;
1752 rx_buffer->page = NULL;
1753
1754 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1755
1756 cleaned_count++;
1757
1758 /* place incomplete frames back on ring for completion */
1759 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1760 continue;
1761
1762 /* verify the packet layout is correct */
1763 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1764 continue;
1765
1766 /* probably a little skewed due to removing CRC */
1767 total_rx_bytes += skb->len;
1768 total_rx_packets++;
1769
1770 /* populate checksum, timestamp, VLAN, and protocol */
1771 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1772
1773 #ifdef IXGBE_FCOE
1774 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1775 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1776 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1777 if (!ddp_bytes) {
1778 dev_kfree_skb_any(skb);
1779 continue;
1780 }
1781 }
1782
1783 #endif /* IXGBE_FCOE */
1784 ixgbe_rx_skb(q_vector, skb);
1785
1786 /* update budget accounting */
1787 budget--;
1788 } while (likely(budget));
1789
1790 #ifdef IXGBE_FCOE
1791 /* include DDPed FCoE data */
1792 if (ddp_bytes > 0) {
1793 unsigned int mss;
1794
1795 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1796 sizeof(struct fc_frame_header) -
1797 sizeof(struct fcoe_crc_eof);
1798 if (mss > 512)
1799 mss &= ~511;
1800 total_rx_bytes += ddp_bytes;
1801 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1802 }
1803
1804 #endif /* IXGBE_FCOE */
1805 u64_stats_update_begin(&rx_ring->syncp);
1806 rx_ring->stats.packets += total_rx_packets;
1807 rx_ring->stats.bytes += total_rx_bytes;
1808 u64_stats_update_end(&rx_ring->syncp);
1809 q_vector->rx.total_packets += total_rx_packets;
1810 q_vector->rx.total_bytes += total_rx_bytes;
1811
1812 if (cleaned_count)
1813 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1814
1815 return !!budget;
1816 }
1817
1818 /**
1819 * ixgbe_configure_msix - Configure MSI-X hardware
1820 * @adapter: board private structure
1821 *
1822 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1823 * interrupts.
1824 **/
1825 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1826 {
1827 struct ixgbe_q_vector *q_vector;
1828 int q_vectors, v_idx;
1829 u32 mask;
1830
1831 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1832
1833 /* Populate MSIX to EITR Select */
1834 if (adapter->num_vfs > 32) {
1835 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1837 }
1838
1839 /*
1840 * Populate the IVAR table and set the ITR values to the
1841 * corresponding register.
1842 */
1843 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1844 struct ixgbe_ring *ring;
1845 q_vector = adapter->q_vector[v_idx];
1846
1847 ixgbe_for_each_ring(ring, q_vector->rx)
1848 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1849
1850 ixgbe_for_each_ring(ring, q_vector->tx)
1851 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1852
1853 if (q_vector->tx.ring && !q_vector->rx.ring) {
1854 /* tx only vector */
1855 if (adapter->tx_itr_setting == 1)
1856 q_vector->itr = IXGBE_10K_ITR;
1857 else
1858 q_vector->itr = adapter->tx_itr_setting;
1859 } else {
1860 /* rx or rx/tx vector */
1861 if (adapter->rx_itr_setting == 1)
1862 q_vector->itr = IXGBE_20K_ITR;
1863 else
1864 q_vector->itr = adapter->rx_itr_setting;
1865 }
1866
1867 ixgbe_write_eitr(q_vector);
1868 }
1869
1870 switch (adapter->hw.mac.type) {
1871 case ixgbe_mac_82598EB:
1872 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1873 v_idx);
1874 break;
1875 case ixgbe_mac_82599EB:
1876 case ixgbe_mac_X540:
1877 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1878 break;
1879 default:
1880 break;
1881 }
1882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1883
1884 /* set up to autoclear timer, and the vectors */
1885 mask = IXGBE_EIMS_ENABLE_MASK;
1886 mask &= ~(IXGBE_EIMS_OTHER |
1887 IXGBE_EIMS_MAILBOX |
1888 IXGBE_EIMS_LSC);
1889
1890 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1891 }
1892
1893 enum latency_range {
1894 lowest_latency = 0,
1895 low_latency = 1,
1896 bulk_latency = 2,
1897 latency_invalid = 255
1898 };
1899
1900 /**
1901 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1902 * @q_vector: structure containing interrupt and ring information
1903 * @ring_container: structure containing ring performance data
1904 *
1905 * Stores a new ITR value based on packets and byte
1906 * counts during the last interrupt. The advantage of per interrupt
1907 * computation is faster updates and more accurate ITR for the current
1908 * traffic pattern. Constants in this function were computed
1909 * based on theoretical maximum wire speed and thresholds were set based
1910 * on testing data as well as attempting to minimize response time
1911 * while increasing bulk throughput.
1912 * this functionality is controlled by the InterruptThrottleRate module
1913 * parameter (see ixgbe_param.c)
1914 **/
1915 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1916 struct ixgbe_ring_container *ring_container)
1917 {
1918 int bytes = ring_container->total_bytes;
1919 int packets = ring_container->total_packets;
1920 u32 timepassed_us;
1921 u64 bytes_perint;
1922 u8 itr_setting = ring_container->itr;
1923
1924 if (packets == 0)
1925 return;
1926
1927 /* simple throttlerate management
1928 * 0-10MB/s lowest (100000 ints/s)
1929 * 10-20MB/s low (20000 ints/s)
1930 * 20-1249MB/s bulk (8000 ints/s)
1931 */
1932 /* what was last interrupt timeslice? */
1933 timepassed_us = q_vector->itr >> 2;
1934 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1935
1936 switch (itr_setting) {
1937 case lowest_latency:
1938 if (bytes_perint > 10)
1939 itr_setting = low_latency;
1940 break;
1941 case low_latency:
1942 if (bytes_perint > 20)
1943 itr_setting = bulk_latency;
1944 else if (bytes_perint <= 10)
1945 itr_setting = lowest_latency;
1946 break;
1947 case bulk_latency:
1948 if (bytes_perint <= 20)
1949 itr_setting = low_latency;
1950 break;
1951 }
1952
1953 /* clear work counters since we have the values we need */
1954 ring_container->total_bytes = 0;
1955 ring_container->total_packets = 0;
1956
1957 /* write updated itr to ring container */
1958 ring_container->itr = itr_setting;
1959 }
1960
1961 /**
1962 * ixgbe_write_eitr - write EITR register in hardware specific way
1963 * @q_vector: structure containing interrupt and ring information
1964 *
1965 * This function is made to be called by ethtool and by the driver
1966 * when it needs to update EITR registers at runtime. Hardware
1967 * specific quirks/differences are taken care of here.
1968 */
1969 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1970 {
1971 struct ixgbe_adapter *adapter = q_vector->adapter;
1972 struct ixgbe_hw *hw = &adapter->hw;
1973 int v_idx = q_vector->v_idx;
1974 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1975
1976 switch (adapter->hw.mac.type) {
1977 case ixgbe_mac_82598EB:
1978 /* must write high and low 16 bits to reset counter */
1979 itr_reg |= (itr_reg << 16);
1980 break;
1981 case ixgbe_mac_82599EB:
1982 case ixgbe_mac_X540:
1983 /*
1984 * set the WDIS bit to not clear the timer bits and cause an
1985 * immediate assertion of the interrupt
1986 */
1987 itr_reg |= IXGBE_EITR_CNT_WDIS;
1988 break;
1989 default:
1990 break;
1991 }
1992 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1993 }
1994
1995 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1996 {
1997 u32 new_itr = q_vector->itr;
1998 u8 current_itr;
1999
2000 ixgbe_update_itr(q_vector, &q_vector->tx);
2001 ixgbe_update_itr(q_vector, &q_vector->rx);
2002
2003 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2004
2005 switch (current_itr) {
2006 /* counts and packets in update_itr are dependent on these numbers */
2007 case lowest_latency:
2008 new_itr = IXGBE_100K_ITR;
2009 break;
2010 case low_latency:
2011 new_itr = IXGBE_20K_ITR;
2012 break;
2013 case bulk_latency:
2014 new_itr = IXGBE_8K_ITR;
2015 break;
2016 default:
2017 break;
2018 }
2019
2020 if (new_itr != q_vector->itr) {
2021 /* do an exponential smoothing */
2022 new_itr = (10 * new_itr * q_vector->itr) /
2023 ((9 * new_itr) + q_vector->itr);
2024
2025 /* save the algorithm value here */
2026 q_vector->itr = new_itr;
2027
2028 ixgbe_write_eitr(q_vector);
2029 }
2030 }
2031
2032 /**
2033 * ixgbe_check_overtemp_subtask - check for over temperature
2034 * @adapter: pointer to adapter
2035 **/
2036 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2037 {
2038 struct ixgbe_hw *hw = &adapter->hw;
2039 u32 eicr = adapter->interrupt_event;
2040
2041 if (test_bit(__IXGBE_DOWN, &adapter->state))
2042 return;
2043
2044 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2045 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2046 return;
2047
2048 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2049
2050 switch (hw->device_id) {
2051 case IXGBE_DEV_ID_82599_T3_LOM:
2052 /*
2053 * Since the warning interrupt is for both ports
2054 * we don't have to check if:
2055 * - This interrupt wasn't for our port.
2056 * - We may have missed the interrupt so always have to
2057 * check if we got a LSC
2058 */
2059 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2060 !(eicr & IXGBE_EICR_LSC))
2061 return;
2062
2063 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2064 u32 autoneg;
2065 bool link_up = false;
2066
2067 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2068
2069 if (link_up)
2070 return;
2071 }
2072
2073 /* Check if this is not due to overtemp */
2074 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2075 return;
2076
2077 break;
2078 default:
2079 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2080 return;
2081 break;
2082 }
2083 e_crit(drv,
2084 "Network adapter has been stopped because it has over heated. "
2085 "Restart the computer. If the problem persists, "
2086 "power off the system and replace the adapter\n");
2087
2088 adapter->interrupt_event = 0;
2089 }
2090
2091 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2092 {
2093 struct ixgbe_hw *hw = &adapter->hw;
2094
2095 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2096 (eicr & IXGBE_EICR_GPI_SDP1)) {
2097 e_crit(probe, "Fan has stopped, replace the adapter\n");
2098 /* write to clear the interrupt */
2099 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2100 }
2101 }
2102
2103 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2104 {
2105 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2106 return;
2107
2108 switch (adapter->hw.mac.type) {
2109 case ixgbe_mac_82599EB:
2110 /*
2111 * Need to check link state so complete overtemp check
2112 * on service task
2113 */
2114 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2115 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2116 adapter->interrupt_event = eicr;
2117 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2118 ixgbe_service_event_schedule(adapter);
2119 return;
2120 }
2121 return;
2122 case ixgbe_mac_X540:
2123 if (!(eicr & IXGBE_EICR_TS))
2124 return;
2125 break;
2126 default:
2127 return;
2128 }
2129
2130 e_crit(drv,
2131 "Network adapter has been stopped because it has over heated. "
2132 "Restart the computer. If the problem persists, "
2133 "power off the system and replace the adapter\n");
2134 }
2135
2136 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2137 {
2138 struct ixgbe_hw *hw = &adapter->hw;
2139
2140 if (eicr & IXGBE_EICR_GPI_SDP2) {
2141 /* Clear the interrupt */
2142 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2143 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2144 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2145 ixgbe_service_event_schedule(adapter);
2146 }
2147 }
2148
2149 if (eicr & IXGBE_EICR_GPI_SDP1) {
2150 /* Clear the interrupt */
2151 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2152 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2153 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2154 ixgbe_service_event_schedule(adapter);
2155 }
2156 }
2157 }
2158
2159 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2160 {
2161 struct ixgbe_hw *hw = &adapter->hw;
2162
2163 adapter->lsc_int++;
2164 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2165 adapter->link_check_timeout = jiffies;
2166 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2167 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2168 IXGBE_WRITE_FLUSH(hw);
2169 ixgbe_service_event_schedule(adapter);
2170 }
2171 }
2172
2173 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2174 u64 qmask)
2175 {
2176 u32 mask;
2177 struct ixgbe_hw *hw = &adapter->hw;
2178
2179 switch (hw->mac.type) {
2180 case ixgbe_mac_82598EB:
2181 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2182 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2183 break;
2184 case ixgbe_mac_82599EB:
2185 case ixgbe_mac_X540:
2186 mask = (qmask & 0xFFFFFFFF);
2187 if (mask)
2188 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2189 mask = (qmask >> 32);
2190 if (mask)
2191 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2192 break;
2193 default:
2194 break;
2195 }
2196 /* skip the flush */
2197 }
2198
2199 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2200 u64 qmask)
2201 {
2202 u32 mask;
2203 struct ixgbe_hw *hw = &adapter->hw;
2204
2205 switch (hw->mac.type) {
2206 case ixgbe_mac_82598EB:
2207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2208 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2209 break;
2210 case ixgbe_mac_82599EB:
2211 case ixgbe_mac_X540:
2212 mask = (qmask & 0xFFFFFFFF);
2213 if (mask)
2214 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2215 mask = (qmask >> 32);
2216 if (mask)
2217 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2218 break;
2219 default:
2220 break;
2221 }
2222 /* skip the flush */
2223 }
2224
2225 /**
2226 * ixgbe_irq_enable - Enable default interrupt generation settings
2227 * @adapter: board private structure
2228 **/
2229 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2230 bool flush)
2231 {
2232 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2233
2234 /* don't reenable LSC while waiting for link */
2235 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2236 mask &= ~IXGBE_EIMS_LSC;
2237
2238 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2239 switch (adapter->hw.mac.type) {
2240 case ixgbe_mac_82599EB:
2241 mask |= IXGBE_EIMS_GPI_SDP0;
2242 break;
2243 case ixgbe_mac_X540:
2244 mask |= IXGBE_EIMS_TS;
2245 break;
2246 default:
2247 break;
2248 }
2249 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2250 mask |= IXGBE_EIMS_GPI_SDP1;
2251 switch (adapter->hw.mac.type) {
2252 case ixgbe_mac_82599EB:
2253 mask |= IXGBE_EIMS_GPI_SDP1;
2254 mask |= IXGBE_EIMS_GPI_SDP2;
2255 case ixgbe_mac_X540:
2256 mask |= IXGBE_EIMS_ECC;
2257 mask |= IXGBE_EIMS_MAILBOX;
2258 break;
2259 default:
2260 break;
2261 }
2262 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2263 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2264 mask |= IXGBE_EIMS_FLOW_DIR;
2265
2266 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2267 if (queues)
2268 ixgbe_irq_enable_queues(adapter, ~0);
2269 if (flush)
2270 IXGBE_WRITE_FLUSH(&adapter->hw);
2271 }
2272
2273 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2274 {
2275 struct ixgbe_adapter *adapter = data;
2276 struct ixgbe_hw *hw = &adapter->hw;
2277 u32 eicr;
2278
2279 /*
2280 * Workaround for Silicon errata. Use clear-by-write instead
2281 * of clear-by-read. Reading with EICS will return the
2282 * interrupt causes without clearing, which later be done
2283 * with the write to EICR.
2284 */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2286 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2287
2288 if (eicr & IXGBE_EICR_LSC)
2289 ixgbe_check_lsc(adapter);
2290
2291 if (eicr & IXGBE_EICR_MAILBOX)
2292 ixgbe_msg_task(adapter);
2293
2294 switch (hw->mac.type) {
2295 case ixgbe_mac_82599EB:
2296 case ixgbe_mac_X540:
2297 if (eicr & IXGBE_EICR_ECC)
2298 e_info(link, "Received unrecoverable ECC Err, please "
2299 "reboot\n");
2300 /* Handle Flow Director Full threshold interrupt */
2301 if (eicr & IXGBE_EICR_FLOW_DIR) {
2302 int reinit_count = 0;
2303 int i;
2304 for (i = 0; i < adapter->num_tx_queues; i++) {
2305 struct ixgbe_ring *ring = adapter->tx_ring[i];
2306 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2307 &ring->state))
2308 reinit_count++;
2309 }
2310 if (reinit_count) {
2311 /* no more flow director interrupts until after init */
2312 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2313 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2314 ixgbe_service_event_schedule(adapter);
2315 }
2316 }
2317 ixgbe_check_sfp_event(adapter, eicr);
2318 ixgbe_check_overtemp_event(adapter, eicr);
2319 break;
2320 default:
2321 break;
2322 }
2323
2324 ixgbe_check_fan_failure(adapter, eicr);
2325 #ifdef CONFIG_IXGBE_PTP
2326 ixgbe_ptp_check_pps_event(adapter, eicr);
2327 #endif
2328
2329 /* re-enable the original interrupt state, no lsc, no queues */
2330 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2331 ixgbe_irq_enable(adapter, false, false);
2332
2333 return IRQ_HANDLED;
2334 }
2335
2336 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2337 {
2338 struct ixgbe_q_vector *q_vector = data;
2339
2340 /* EIAM disabled interrupts (on this vector) for us */
2341
2342 if (q_vector->rx.ring || q_vector->tx.ring)
2343 napi_schedule(&q_vector->napi);
2344
2345 return IRQ_HANDLED;
2346 }
2347
2348 /**
2349 * ixgbe_poll - NAPI Rx polling callback
2350 * @napi: structure for representing this polling device
2351 * @budget: how many packets driver is allowed to clean
2352 *
2353 * This function is used for legacy and MSI, NAPI mode
2354 **/
2355 int ixgbe_poll(struct napi_struct *napi, int budget)
2356 {
2357 struct ixgbe_q_vector *q_vector =
2358 container_of(napi, struct ixgbe_q_vector, napi);
2359 struct ixgbe_adapter *adapter = q_vector->adapter;
2360 struct ixgbe_ring *ring;
2361 int per_ring_budget;
2362 bool clean_complete = true;
2363
2364 #ifdef CONFIG_IXGBE_DCA
2365 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2366 ixgbe_update_dca(q_vector);
2367 #endif
2368
2369 ixgbe_for_each_ring(ring, q_vector->tx)
2370 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2371
2372 /* attempt to distribute budget to each queue fairly, but don't allow
2373 * the budget to go below 1 because we'll exit polling */
2374 if (q_vector->rx.count > 1)
2375 per_ring_budget = max(budget/q_vector->rx.count, 1);
2376 else
2377 per_ring_budget = budget;
2378
2379 ixgbe_for_each_ring(ring, q_vector->rx)
2380 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2381 per_ring_budget);
2382
2383 /* If all work not completed, return budget and keep polling */
2384 if (!clean_complete)
2385 return budget;
2386
2387 /* all work done, exit the polling mode */
2388 napi_complete(napi);
2389 if (adapter->rx_itr_setting & 1)
2390 ixgbe_set_itr(q_vector);
2391 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2392 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2393
2394 return 0;
2395 }
2396
2397 /**
2398 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2399 * @adapter: board private structure
2400 *
2401 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2402 * interrupts from the kernel.
2403 **/
2404 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2405 {
2406 struct net_device *netdev = adapter->netdev;
2407 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2408 int vector, err;
2409 int ri = 0, ti = 0;
2410
2411 for (vector = 0; vector < q_vectors; vector++) {
2412 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2413 struct msix_entry *entry = &adapter->msix_entries[vector];
2414
2415 if (q_vector->tx.ring && q_vector->rx.ring) {
2416 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2417 "%s-%s-%d", netdev->name, "TxRx", ri++);
2418 ti++;
2419 } else if (q_vector->rx.ring) {
2420 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2421 "%s-%s-%d", netdev->name, "rx", ri++);
2422 } else if (q_vector->tx.ring) {
2423 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2424 "%s-%s-%d", netdev->name, "tx", ti++);
2425 } else {
2426 /* skip this unused q_vector */
2427 continue;
2428 }
2429 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2430 q_vector->name, q_vector);
2431 if (err) {
2432 e_err(probe, "request_irq failed for MSIX interrupt "
2433 "Error: %d\n", err);
2434 goto free_queue_irqs;
2435 }
2436 /* If Flow Director is enabled, set interrupt affinity */
2437 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2438 /* assign the mask for this irq */
2439 irq_set_affinity_hint(entry->vector,
2440 &q_vector->affinity_mask);
2441 }
2442 }
2443
2444 err = request_irq(adapter->msix_entries[vector].vector,
2445 ixgbe_msix_other, 0, netdev->name, adapter);
2446 if (err) {
2447 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2448 goto free_queue_irqs;
2449 }
2450
2451 return 0;
2452
2453 free_queue_irqs:
2454 while (vector) {
2455 vector--;
2456 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2457 NULL);
2458 free_irq(adapter->msix_entries[vector].vector,
2459 adapter->q_vector[vector]);
2460 }
2461 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2462 pci_disable_msix(adapter->pdev);
2463 kfree(adapter->msix_entries);
2464 adapter->msix_entries = NULL;
2465 return err;
2466 }
2467
2468 /**
2469 * ixgbe_intr - legacy mode Interrupt Handler
2470 * @irq: interrupt number
2471 * @data: pointer to a network interface device structure
2472 **/
2473 static irqreturn_t ixgbe_intr(int irq, void *data)
2474 {
2475 struct ixgbe_adapter *adapter = data;
2476 struct ixgbe_hw *hw = &adapter->hw;
2477 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2478 u32 eicr;
2479
2480 /*
2481 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2482 * before the read of EICR.
2483 */
2484 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2485
2486 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2487 * therefore no explicit interrupt disable is necessary */
2488 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2489 if (!eicr) {
2490 /*
2491 * shared interrupt alert!
2492 * make sure interrupts are enabled because the read will
2493 * have disabled interrupts due to EIAM
2494 * finish the workaround of silicon errata on 82598. Unmask
2495 * the interrupt that we masked before the EICR read.
2496 */
2497 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2498 ixgbe_irq_enable(adapter, true, true);
2499 return IRQ_NONE; /* Not our interrupt */
2500 }
2501
2502 if (eicr & IXGBE_EICR_LSC)
2503 ixgbe_check_lsc(adapter);
2504
2505 switch (hw->mac.type) {
2506 case ixgbe_mac_82599EB:
2507 ixgbe_check_sfp_event(adapter, eicr);
2508 /* Fall through */
2509 case ixgbe_mac_X540:
2510 if (eicr & IXGBE_EICR_ECC)
2511 e_info(link, "Received unrecoverable ECC err, please "
2512 "reboot\n");
2513 ixgbe_check_overtemp_event(adapter, eicr);
2514 break;
2515 default:
2516 break;
2517 }
2518
2519 ixgbe_check_fan_failure(adapter, eicr);
2520 #ifdef CONFIG_IXGBE_PTP
2521 ixgbe_ptp_check_pps_event(adapter, eicr);
2522 #endif
2523
2524 /* would disable interrupts here but EIAM disabled it */
2525 napi_schedule(&q_vector->napi);
2526
2527 /*
2528 * re-enable link(maybe) and non-queue interrupts, no flush.
2529 * ixgbe_poll will re-enable the queue interrupts
2530 */
2531 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2532 ixgbe_irq_enable(adapter, false, false);
2533
2534 return IRQ_HANDLED;
2535 }
2536
2537 /**
2538 * ixgbe_request_irq - initialize interrupts
2539 * @adapter: board private structure
2540 *
2541 * Attempts to configure interrupts using the best available
2542 * capabilities of the hardware and kernel.
2543 **/
2544 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2545 {
2546 struct net_device *netdev = adapter->netdev;
2547 int err;
2548
2549 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2550 err = ixgbe_request_msix_irqs(adapter);
2551 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2552 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2553 netdev->name, adapter);
2554 else
2555 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2556 netdev->name, adapter);
2557
2558 if (err)
2559 e_err(probe, "request_irq failed, Error %d\n", err);
2560
2561 return err;
2562 }
2563
2564 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2565 {
2566 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2567 int i, q_vectors;
2568
2569 q_vectors = adapter->num_msix_vectors;
2570 i = q_vectors - 1;
2571 free_irq(adapter->msix_entries[i].vector, adapter);
2572 i--;
2573
2574 for (; i >= 0; i--) {
2575 /* free only the irqs that were actually requested */
2576 if (!adapter->q_vector[i]->rx.ring &&
2577 !adapter->q_vector[i]->tx.ring)
2578 continue;
2579
2580 /* clear the affinity_mask in the IRQ descriptor */
2581 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2582 NULL);
2583
2584 free_irq(adapter->msix_entries[i].vector,
2585 adapter->q_vector[i]);
2586 }
2587 } else {
2588 free_irq(adapter->pdev->irq, adapter);
2589 }
2590 }
2591
2592 /**
2593 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2594 * @adapter: board private structure
2595 **/
2596 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2597 {
2598 switch (adapter->hw.mac.type) {
2599 case ixgbe_mac_82598EB:
2600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2601 break;
2602 case ixgbe_mac_82599EB:
2603 case ixgbe_mac_X540:
2604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2607 break;
2608 default:
2609 break;
2610 }
2611 IXGBE_WRITE_FLUSH(&adapter->hw);
2612 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2613 int i;
2614 for (i = 0; i < adapter->num_msix_vectors; i++)
2615 synchronize_irq(adapter->msix_entries[i].vector);
2616 } else {
2617 synchronize_irq(adapter->pdev->irq);
2618 }
2619 }
2620
2621 /**
2622 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2623 *
2624 **/
2625 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2626 {
2627 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2628
2629 /* rx/tx vector */
2630 if (adapter->rx_itr_setting == 1)
2631 q_vector->itr = IXGBE_20K_ITR;
2632 else
2633 q_vector->itr = adapter->rx_itr_setting;
2634
2635 ixgbe_write_eitr(q_vector);
2636
2637 ixgbe_set_ivar(adapter, 0, 0, 0);
2638 ixgbe_set_ivar(adapter, 1, 0, 0);
2639
2640 e_info(hw, "Legacy interrupt IVAR setup done\n");
2641 }
2642
2643 /**
2644 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2645 * @adapter: board private structure
2646 * @ring: structure containing ring specific data
2647 *
2648 * Configure the Tx descriptor ring after a reset.
2649 **/
2650 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2651 struct ixgbe_ring *ring)
2652 {
2653 struct ixgbe_hw *hw = &adapter->hw;
2654 u64 tdba = ring->dma;
2655 int wait_loop = 10;
2656 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2657 u8 reg_idx = ring->reg_idx;
2658
2659 /* disable queue to avoid issues while updating state */
2660 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2661 IXGBE_WRITE_FLUSH(hw);
2662
2663 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2664 (tdba & DMA_BIT_MASK(32)));
2665 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2666 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2667 ring->count * sizeof(union ixgbe_adv_tx_desc));
2668 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2669 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2670 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2671
2672 /*
2673 * set WTHRESH to encourage burst writeback, it should not be set
2674 * higher than 1 when ITR is 0 as it could cause false TX hangs
2675 *
2676 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2677 * to or less than the number of on chip descriptors, which is
2678 * currently 40.
2679 */
2680 if (!ring->q_vector || (ring->q_vector->itr < 8))
2681 txdctl |= (1 << 16); /* WTHRESH = 1 */
2682 else
2683 txdctl |= (8 << 16); /* WTHRESH = 8 */
2684
2685 /*
2686 * Setting PTHRESH to 32 both improves performance
2687 * and avoids a TX hang with DFP enabled
2688 */
2689 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2690 32; /* PTHRESH = 32 */
2691
2692 /* reinitialize flowdirector state */
2693 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2694 adapter->atr_sample_rate) {
2695 ring->atr_sample_rate = adapter->atr_sample_rate;
2696 ring->atr_count = 0;
2697 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2698 } else {
2699 ring->atr_sample_rate = 0;
2700 }
2701
2702 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2703
2704 /* enable queue */
2705 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2706
2707 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2708 if (hw->mac.type == ixgbe_mac_82598EB &&
2709 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2710 return;
2711
2712 /* poll to verify queue is enabled */
2713 do {
2714 usleep_range(1000, 2000);
2715 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2716 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2717 if (!wait_loop)
2718 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2719 }
2720
2721 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2722 {
2723 struct ixgbe_hw *hw = &adapter->hw;
2724 u32 rttdcs;
2725 u32 reg;
2726 u8 tcs = netdev_get_num_tc(adapter->netdev);
2727
2728 if (hw->mac.type == ixgbe_mac_82598EB)
2729 return;
2730
2731 /* disable the arbiter while setting MTQC */
2732 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2733 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2734 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2735
2736 /* set transmit pool layout */
2737 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2738 case (IXGBE_FLAG_SRIOV_ENABLED):
2739 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2740 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2741 break;
2742 default:
2743 if (!tcs)
2744 reg = IXGBE_MTQC_64Q_1PB;
2745 else if (tcs <= 4)
2746 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2747 else
2748 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2749
2750 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2751
2752 /* Enable Security TX Buffer IFG for multiple pb */
2753 if (tcs) {
2754 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2755 reg |= IXGBE_SECTX_DCB;
2756 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2757 }
2758 break;
2759 }
2760
2761 /* re-enable the arbiter */
2762 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2763 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2764 }
2765
2766 /**
2767 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2768 * @adapter: board private structure
2769 *
2770 * Configure the Tx unit of the MAC after a reset.
2771 **/
2772 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2773 {
2774 struct ixgbe_hw *hw = &adapter->hw;
2775 u32 dmatxctl;
2776 u32 i;
2777
2778 ixgbe_setup_mtqc(adapter);
2779
2780 if (hw->mac.type != ixgbe_mac_82598EB) {
2781 /* DMATXCTL.EN must be before Tx queues are enabled */
2782 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2783 dmatxctl |= IXGBE_DMATXCTL_TE;
2784 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2785 }
2786
2787 /* Setup the HW Tx Head and Tail descriptor pointers */
2788 for (i = 0; i < adapter->num_tx_queues; i++)
2789 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2790 }
2791
2792 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2793 struct ixgbe_ring *ring)
2794 {
2795 struct ixgbe_hw *hw = &adapter->hw;
2796 u8 reg_idx = ring->reg_idx;
2797 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2798
2799 srrctl |= IXGBE_SRRCTL_DROP_EN;
2800
2801 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2802 }
2803
2804 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2805 struct ixgbe_ring *ring)
2806 {
2807 struct ixgbe_hw *hw = &adapter->hw;
2808 u8 reg_idx = ring->reg_idx;
2809 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2810
2811 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2812
2813 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2814 }
2815
2816 #ifdef CONFIG_IXGBE_DCB
2817 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2818 #else
2819 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2820 #endif
2821 {
2822 int i;
2823 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2824
2825 if (adapter->ixgbe_ieee_pfc)
2826 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2827
2828 /*
2829 * We should set the drop enable bit if:
2830 * SR-IOV is enabled
2831 * or
2832 * Number of Rx queues > 1 and flow control is disabled
2833 *
2834 * This allows us to avoid head of line blocking for security
2835 * and performance reasons.
2836 */
2837 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2838 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2839 for (i = 0; i < adapter->num_rx_queues; i++)
2840 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2841 } else {
2842 for (i = 0; i < adapter->num_rx_queues; i++)
2843 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2844 }
2845 }
2846
2847 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2848
2849 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2850 struct ixgbe_ring *rx_ring)
2851 {
2852 u32 srrctl;
2853 u8 reg_idx = rx_ring->reg_idx;
2854
2855 switch (adapter->hw.mac.type) {
2856 case ixgbe_mac_82598EB: {
2857 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2858 const int mask = feature[RING_F_RSS].mask;
2859 reg_idx = reg_idx & mask;
2860 }
2861 break;
2862 case ixgbe_mac_82599EB:
2863 case ixgbe_mac_X540:
2864 default:
2865 break;
2866 }
2867
2868 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2869
2870 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2871 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2872 if (adapter->num_vfs)
2873 srrctl |= IXGBE_SRRCTL_DROP_EN;
2874
2875 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2876 IXGBE_SRRCTL_BSIZEHDR_MASK;
2877
2878 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2879 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2880 #else
2881 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2882 #endif
2883 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2884
2885 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2886 }
2887
2888 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2889 {
2890 struct ixgbe_hw *hw = &adapter->hw;
2891 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2892 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2893 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2894 u32 mrqc = 0, reta = 0;
2895 u32 rxcsum;
2896 int i, j;
2897 u8 tcs = netdev_get_num_tc(adapter->netdev);
2898 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2899
2900 if (tcs)
2901 maxq = min(maxq, adapter->num_tx_queues / tcs);
2902
2903 /* Fill out hash function seeds */
2904 for (i = 0; i < 10; i++)
2905 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2906
2907 /* Fill out redirection table */
2908 for (i = 0, j = 0; i < 128; i++, j++) {
2909 if (j == maxq)
2910 j = 0;
2911 /* reta = 4-byte sliding window of
2912 * 0x00..(indices-1)(indices-1)00..etc. */
2913 reta = (reta << 8) | (j * 0x11);
2914 if ((i & 3) == 3)
2915 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2916 }
2917
2918 /* Disable indicating checksum in descriptor, enables RSS hash */
2919 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2920 rxcsum |= IXGBE_RXCSUM_PCSD;
2921 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2922
2923 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2924 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2925 mrqc = IXGBE_MRQC_RSSEN;
2926 } else {
2927 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2928 | IXGBE_FLAG_SRIOV_ENABLED);
2929
2930 switch (mask) {
2931 case (IXGBE_FLAG_RSS_ENABLED):
2932 if (!tcs)
2933 mrqc = IXGBE_MRQC_RSSEN;
2934 else if (tcs <= 4)
2935 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2936 else
2937 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2938 break;
2939 case (IXGBE_FLAG_SRIOV_ENABLED):
2940 mrqc = IXGBE_MRQC_VMDQEN;
2941 break;
2942 default:
2943 break;
2944 }
2945 }
2946
2947 /* Perform hash on these packet types */
2948 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2949 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2950 | IXGBE_MRQC_RSS_FIELD_IPV6
2951 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2952
2953 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2954 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2955 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2956 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2957
2958 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2959 }
2960
2961 /**
2962 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2963 * @adapter: address of board private structure
2964 * @index: index of ring to set
2965 **/
2966 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2967 struct ixgbe_ring *ring)
2968 {
2969 struct ixgbe_hw *hw = &adapter->hw;
2970 u32 rscctrl;
2971 u8 reg_idx = ring->reg_idx;
2972
2973 if (!ring_is_rsc_enabled(ring))
2974 return;
2975
2976 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2977 rscctrl |= IXGBE_RSCCTL_RSCEN;
2978 /*
2979 * we must limit the number of descriptors so that the
2980 * total size of max desc * buf_len is not greater
2981 * than 65536
2982 */
2983 #if (PAGE_SIZE <= 8192)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2985 #elif (PAGE_SIZE <= 16384)
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2987 #else
2988 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2989 #endif
2990 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2991 }
2992
2993 #define IXGBE_MAX_RX_DESC_POLL 10
2994 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2995 struct ixgbe_ring *ring)
2996 {
2997 struct ixgbe_hw *hw = &adapter->hw;
2998 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2999 u32 rxdctl;
3000 u8 reg_idx = ring->reg_idx;
3001
3002 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3003 if (hw->mac.type == ixgbe_mac_82598EB &&
3004 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3005 return;
3006
3007 do {
3008 usleep_range(1000, 2000);
3009 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3010 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3011
3012 if (!wait_loop) {
3013 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3014 "the polling period\n", reg_idx);
3015 }
3016 }
3017
3018 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3019 struct ixgbe_ring *ring)
3020 {
3021 struct ixgbe_hw *hw = &adapter->hw;
3022 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3023 u32 rxdctl;
3024 u8 reg_idx = ring->reg_idx;
3025
3026 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3027 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3028
3029 /* write value back with RXDCTL.ENABLE bit cleared */
3030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3031
3032 if (hw->mac.type == ixgbe_mac_82598EB &&
3033 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3034 return;
3035
3036 /* the hardware may take up to 100us to really disable the rx queue */
3037 do {
3038 udelay(10);
3039 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3040 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3041
3042 if (!wait_loop) {
3043 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3044 "the polling period\n", reg_idx);
3045 }
3046 }
3047
3048 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
3050 {
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 u64 rdba = ring->dma;
3053 u32 rxdctl;
3054 u8 reg_idx = ring->reg_idx;
3055
3056 /* disable queue to avoid issues while updating state */
3057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3058 ixgbe_disable_rx_queue(adapter, ring);
3059
3060 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3061 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3062 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3063 ring->count * sizeof(union ixgbe_adv_rx_desc));
3064 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3065 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3066 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3067
3068 ixgbe_configure_srrctl(adapter, ring);
3069 ixgbe_configure_rscctl(adapter, ring);
3070
3071 /* If operating in IOV mode set RLPML for X540 */
3072 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3073 hw->mac.type == ixgbe_mac_X540) {
3074 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3075 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3076 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3077 }
3078
3079 if (hw->mac.type == ixgbe_mac_82598EB) {
3080 /*
3081 * enable cache line friendly hardware writes:
3082 * PTHRESH=32 descriptors (half the internal cache),
3083 * this also removes ugly rx_no_buffer_count increment
3084 * HTHRESH=4 descriptors (to minimize latency on fetch)
3085 * WTHRESH=8 burst writeback up to two cache lines
3086 */
3087 rxdctl &= ~0x3FFFFF;
3088 rxdctl |= 0x080420;
3089 }
3090
3091 /* enable receive descriptor ring */
3092 rxdctl |= IXGBE_RXDCTL_ENABLE;
3093 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3094
3095 ixgbe_rx_desc_queue_enable(adapter, ring);
3096 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3097 }
3098
3099 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3100 {
3101 struct ixgbe_hw *hw = &adapter->hw;
3102 int p;
3103
3104 /* PSRTYPE must be initialized in non 82598 adapters */
3105 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3106 IXGBE_PSRTYPE_UDPHDR |
3107 IXGBE_PSRTYPE_IPV4HDR |
3108 IXGBE_PSRTYPE_L2HDR |
3109 IXGBE_PSRTYPE_IPV6HDR;
3110
3111 if (hw->mac.type == ixgbe_mac_82598EB)
3112 return;
3113
3114 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3115 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3116
3117 for (p = 0; p < adapter->num_rx_pools; p++)
3118 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3119 psrtype);
3120 }
3121
3122 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3123 {
3124 struct ixgbe_hw *hw = &adapter->hw;
3125 u32 gcr_ext;
3126 u32 vt_reg_bits;
3127 u32 reg_offset, vf_shift;
3128 u32 vmdctl;
3129 int i;
3130
3131 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3132 return;
3133
3134 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3135 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3136 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3137 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3138
3139 vf_shift = adapter->num_vfs % 32;
3140 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3141
3142 /* Enable only the PF's pool for Tx/Rx */
3143 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3144 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3145 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3146 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3147 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3148
3149 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3150 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3151
3152 /*
3153 * Set up VF register offsets for selected VT Mode,
3154 * i.e. 32 or 64 VFs for SR-IOV
3155 */
3156 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3157 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3158 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3159 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3160
3161 /* enable Tx loopback for VF/PF communication */
3162 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3163 /* Enable MAC Anti-Spoofing */
3164 hw->mac.ops.set_mac_anti_spoofing(hw,
3165 (adapter->num_vfs != 0),
3166 adapter->num_vfs);
3167 /* For VFs that have spoof checking turned off */
3168 for (i = 0; i < adapter->num_vfs; i++) {
3169 if (!adapter->vfinfo[i].spoofchk_enabled)
3170 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3171 }
3172 }
3173
3174 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3175 {
3176 struct ixgbe_hw *hw = &adapter->hw;
3177 struct net_device *netdev = adapter->netdev;
3178 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3179 struct ixgbe_ring *rx_ring;
3180 int i;
3181 u32 mhadd, hlreg0;
3182
3183 #ifdef IXGBE_FCOE
3184 /* adjust max frame to be able to do baby jumbo for FCoE */
3185 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3186 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3187 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3188
3189 #endif /* IXGBE_FCOE */
3190 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3191 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3192 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3193 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3194
3195 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3196 }
3197
3198 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3199 max_frame += VLAN_HLEN;
3200
3201 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3202 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3203 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3204 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3205
3206 /*
3207 * Setup the HW Rx Head and Tail Descriptor Pointers and
3208 * the Base and Length of the Rx Descriptor Ring
3209 */
3210 for (i = 0; i < adapter->num_rx_queues; i++) {
3211 rx_ring = adapter->rx_ring[i];
3212 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3213 set_ring_rsc_enabled(rx_ring);
3214 else
3215 clear_ring_rsc_enabled(rx_ring);
3216 }
3217 }
3218
3219 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3220 {
3221 struct ixgbe_hw *hw = &adapter->hw;
3222 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3223
3224 switch (hw->mac.type) {
3225 case ixgbe_mac_82598EB:
3226 /*
3227 * For VMDq support of different descriptor types or
3228 * buffer sizes through the use of multiple SRRCTL
3229 * registers, RDRXCTL.MVMEN must be set to 1
3230 *
3231 * also, the manual doesn't mention it clearly but DCA hints
3232 * will only use queue 0's tags unless this bit is set. Side
3233 * effects of setting this bit are only that SRRCTL must be
3234 * fully programmed [0..15]
3235 */
3236 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3237 break;
3238 case ixgbe_mac_82599EB:
3239 case ixgbe_mac_X540:
3240 /* Disable RSC for ACK packets */
3241 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3242 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3243 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3244 /* hardware requires some bits to be set by default */
3245 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3246 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3247 break;
3248 default:
3249 /* We should do nothing since we don't know this hardware */
3250 return;
3251 }
3252
3253 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3254 }
3255
3256 /**
3257 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3258 * @adapter: board private structure
3259 *
3260 * Configure the Rx unit of the MAC after a reset.
3261 **/
3262 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3263 {
3264 struct ixgbe_hw *hw = &adapter->hw;
3265 int i;
3266 u32 rxctrl;
3267
3268 /* disable receives while setting up the descriptors */
3269 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3270 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3271
3272 ixgbe_setup_psrtype(adapter);
3273 ixgbe_setup_rdrxctl(adapter);
3274
3275 /* Program registers for the distribution of queues */
3276 ixgbe_setup_mrqc(adapter);
3277
3278 /* set_rx_buffer_len must be called before ring initialization */
3279 ixgbe_set_rx_buffer_len(adapter);
3280
3281 /*
3282 * Setup the HW Rx Head and Tail Descriptor Pointers and
3283 * the Base and Length of the Rx Descriptor Ring
3284 */
3285 for (i = 0; i < adapter->num_rx_queues; i++)
3286 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3287
3288 /* disable drop enable for 82598 parts */
3289 if (hw->mac.type == ixgbe_mac_82598EB)
3290 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3291
3292 /* enable all receives */
3293 rxctrl |= IXGBE_RXCTRL_RXEN;
3294 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3295 }
3296
3297 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3298 {
3299 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3300 struct ixgbe_hw *hw = &adapter->hw;
3301 int pool_ndx = adapter->num_vfs;
3302
3303 /* add VID to filter table */
3304 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3305 set_bit(vid, adapter->active_vlans);
3306
3307 return 0;
3308 }
3309
3310 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3311 {
3312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3313 struct ixgbe_hw *hw = &adapter->hw;
3314 int pool_ndx = adapter->num_vfs;
3315
3316 /* remove VID from filter table */
3317 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3318 clear_bit(vid, adapter->active_vlans);
3319
3320 return 0;
3321 }
3322
3323 /**
3324 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3325 * @adapter: driver data
3326 */
3327 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3328 {
3329 struct ixgbe_hw *hw = &adapter->hw;
3330 u32 vlnctrl;
3331
3332 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3333 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3334 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3335 }
3336
3337 /**
3338 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3339 * @adapter: driver data
3340 */
3341 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3342 {
3343 struct ixgbe_hw *hw = &adapter->hw;
3344 u32 vlnctrl;
3345
3346 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3347 vlnctrl |= IXGBE_VLNCTRL_VFE;
3348 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3349 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3350 }
3351
3352 /**
3353 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3354 * @adapter: driver data
3355 */
3356 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3357 {
3358 struct ixgbe_hw *hw = &adapter->hw;
3359 u32 vlnctrl;
3360 int i, j;
3361
3362 switch (hw->mac.type) {
3363 case ixgbe_mac_82598EB:
3364 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3365 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3366 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3367 break;
3368 case ixgbe_mac_82599EB:
3369 case ixgbe_mac_X540:
3370 for (i = 0; i < adapter->num_rx_queues; i++) {
3371 j = adapter->rx_ring[i]->reg_idx;
3372 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3373 vlnctrl &= ~IXGBE_RXDCTL_VME;
3374 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3375 }
3376 break;
3377 default:
3378 break;
3379 }
3380 }
3381
3382 /**
3383 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3384 * @adapter: driver data
3385 */
3386 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3387 {
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u32 vlnctrl;
3390 int i, j;
3391
3392 switch (hw->mac.type) {
3393 case ixgbe_mac_82598EB:
3394 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3395 vlnctrl |= IXGBE_VLNCTRL_VME;
3396 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3397 break;
3398 case ixgbe_mac_82599EB:
3399 case ixgbe_mac_X540:
3400 for (i = 0; i < adapter->num_rx_queues; i++) {
3401 j = adapter->rx_ring[i]->reg_idx;
3402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3403 vlnctrl |= IXGBE_RXDCTL_VME;
3404 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3405 }
3406 break;
3407 default:
3408 break;
3409 }
3410 }
3411
3412 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3413 {
3414 u16 vid;
3415
3416 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3417
3418 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3419 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3420 }
3421
3422 /**
3423 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3424 * @netdev: network interface device structure
3425 *
3426 * Writes unicast address list to the RAR table.
3427 * Returns: -ENOMEM on failure/insufficient address space
3428 * 0 on no addresses written
3429 * X on writing X addresses to the RAR table
3430 **/
3431 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3432 {
3433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3434 struct ixgbe_hw *hw = &adapter->hw;
3435 unsigned int vfn = adapter->num_vfs;
3436 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3437 int count = 0;
3438
3439 /* return ENOMEM indicating insufficient memory for addresses */
3440 if (netdev_uc_count(netdev) > rar_entries)
3441 return -ENOMEM;
3442
3443 if (!netdev_uc_empty(netdev) && rar_entries) {
3444 struct netdev_hw_addr *ha;
3445 /* return error if we do not support writing to RAR table */
3446 if (!hw->mac.ops.set_rar)
3447 return -ENOMEM;
3448
3449 netdev_for_each_uc_addr(ha, netdev) {
3450 if (!rar_entries)
3451 break;
3452 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3453 vfn, IXGBE_RAH_AV);
3454 count++;
3455 }
3456 }
3457 /* write the addresses in reverse order to avoid write combining */
3458 for (; rar_entries > 0 ; rar_entries--)
3459 hw->mac.ops.clear_rar(hw, rar_entries);
3460
3461 return count;
3462 }
3463
3464 /**
3465 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3466 * @netdev: network interface device structure
3467 *
3468 * The set_rx_method entry point is called whenever the unicast/multicast
3469 * address list or the network interface flags are updated. This routine is
3470 * responsible for configuring the hardware for proper unicast, multicast and
3471 * promiscuous mode.
3472 **/
3473 void ixgbe_set_rx_mode(struct net_device *netdev)
3474 {
3475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3476 struct ixgbe_hw *hw = &adapter->hw;
3477 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3478 int count;
3479
3480 /* Check for Promiscuous and All Multicast modes */
3481
3482 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3483
3484 /* set all bits that we expect to always be set */
3485 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3486 fctrl |= IXGBE_FCTRL_BAM;
3487 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3488 fctrl |= IXGBE_FCTRL_PMCF;
3489
3490 /* clear the bits we are changing the status of */
3491 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3492
3493 if (netdev->flags & IFF_PROMISC) {
3494 hw->addr_ctrl.user_set_promisc = true;
3495 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3496 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3497 /* don't hardware filter vlans in promisc mode */
3498 ixgbe_vlan_filter_disable(adapter);
3499 } else {
3500 if (netdev->flags & IFF_ALLMULTI) {
3501 fctrl |= IXGBE_FCTRL_MPE;
3502 vmolr |= IXGBE_VMOLR_MPE;
3503 } else {
3504 /*
3505 * Write addresses to the MTA, if the attempt fails
3506 * then we should just turn on promiscuous mode so
3507 * that we can at least receive multicast traffic
3508 */
3509 hw->mac.ops.update_mc_addr_list(hw, netdev);
3510 vmolr |= IXGBE_VMOLR_ROMPE;
3511 }
3512 ixgbe_vlan_filter_enable(adapter);
3513 hw->addr_ctrl.user_set_promisc = false;
3514 }
3515
3516 /*
3517 * Write addresses to available RAR registers, if there is not
3518 * sufficient space to store all the addresses then enable
3519 * unicast promiscuous mode
3520 */
3521 count = ixgbe_write_uc_addr_list(netdev);
3522 if (count < 0) {
3523 fctrl |= IXGBE_FCTRL_UPE;
3524 vmolr |= IXGBE_VMOLR_ROPE;
3525 }
3526
3527 if (adapter->num_vfs) {
3528 ixgbe_restore_vf_multicasts(adapter);
3529 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3530 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3531 IXGBE_VMOLR_ROPE);
3532 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3533 }
3534
3535 /* This is useful for sniffing bad packets. */
3536 if (adapter->netdev->features & NETIF_F_RXALL) {
3537 /* UPE and MPE will be handled by normal PROMISC logic
3538 * in e1000e_set_rx_mode */
3539 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3540 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3541 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3542
3543 fctrl &= ~(IXGBE_FCTRL_DPF);
3544 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3545 }
3546
3547 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3548
3549 if (netdev->features & NETIF_F_HW_VLAN_RX)
3550 ixgbe_vlan_strip_enable(adapter);
3551 else
3552 ixgbe_vlan_strip_disable(adapter);
3553 }
3554
3555 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3556 {
3557 int q_idx;
3558 struct ixgbe_q_vector *q_vector;
3559 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3560
3561 /* legacy and MSI only use one vector */
3562 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3563 q_vectors = 1;
3564
3565 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3566 q_vector = adapter->q_vector[q_idx];
3567 napi_enable(&q_vector->napi);
3568 }
3569 }
3570
3571 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3572 {
3573 int q_idx;
3574 struct ixgbe_q_vector *q_vector;
3575 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3576
3577 /* legacy and MSI only use one vector */
3578 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3579 q_vectors = 1;
3580
3581 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3582 q_vector = adapter->q_vector[q_idx];
3583 napi_disable(&q_vector->napi);
3584 }
3585 }
3586
3587 #ifdef CONFIG_IXGBE_DCB
3588 /*
3589 * ixgbe_configure_dcb - Configure DCB hardware
3590 * @adapter: ixgbe adapter struct
3591 *
3592 * This is called by the driver on open to configure the DCB hardware.
3593 * This is also called by the gennetlink interface when reconfiguring
3594 * the DCB state.
3595 */
3596 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3597 {
3598 struct ixgbe_hw *hw = &adapter->hw;
3599 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3600
3601 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3602 if (hw->mac.type == ixgbe_mac_82598EB)
3603 netif_set_gso_max_size(adapter->netdev, 65536);
3604 return;
3605 }
3606
3607 if (hw->mac.type == ixgbe_mac_82598EB)
3608 netif_set_gso_max_size(adapter->netdev, 32768);
3609
3610 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3611
3612 #ifdef IXGBE_FCOE
3613 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3614 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3615 #endif
3616
3617 /* reconfigure the hardware */
3618 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3619 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3620 DCB_TX_CONFIG);
3621 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3622 DCB_RX_CONFIG);
3623 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3624 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3625 ixgbe_dcb_hw_ets(&adapter->hw,
3626 adapter->ixgbe_ieee_ets,
3627 max_frame);
3628 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3629 adapter->ixgbe_ieee_pfc->pfc_en,
3630 adapter->ixgbe_ieee_ets->prio_tc);
3631 }
3632
3633 /* Enable RSS Hash per TC */
3634 if (hw->mac.type != ixgbe_mac_82598EB) {
3635 int i;
3636 u32 reg = 0;
3637
3638 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3639 u8 msb = 0;
3640 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3641
3642 while (cnt >>= 1)
3643 msb++;
3644
3645 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3646 }
3647 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3648 }
3649 }
3650 #endif
3651
3652 /* Additional bittime to account for IXGBE framing */
3653 #define IXGBE_ETH_FRAMING 20
3654
3655 /*
3656 * ixgbe_hpbthresh - calculate high water mark for flow control
3657 *
3658 * @adapter: board private structure to calculate for
3659 * @pb - packet buffer to calculate
3660 */
3661 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3662 {
3663 struct ixgbe_hw *hw = &adapter->hw;
3664 struct net_device *dev = adapter->netdev;
3665 int link, tc, kb, marker;
3666 u32 dv_id, rx_pba;
3667
3668 /* Calculate max LAN frame size */
3669 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3670
3671 #ifdef IXGBE_FCOE
3672 /* FCoE traffic class uses FCOE jumbo frames */
3673 if (dev->features & NETIF_F_FCOE_MTU) {
3674 int fcoe_pb = 0;
3675
3676 #ifdef CONFIG_IXGBE_DCB
3677 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3678
3679 #endif
3680 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3681 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3682 }
3683 #endif
3684
3685 /* Calculate delay value for device */
3686 switch (hw->mac.type) {
3687 case ixgbe_mac_X540:
3688 dv_id = IXGBE_DV_X540(link, tc);
3689 break;
3690 default:
3691 dv_id = IXGBE_DV(link, tc);
3692 break;
3693 }
3694
3695 /* Loopback switch introduces additional latency */
3696 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3697 dv_id += IXGBE_B2BT(tc);
3698
3699 /* Delay value is calculated in bit times convert to KB */
3700 kb = IXGBE_BT2KB(dv_id);
3701 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3702
3703 marker = rx_pba - kb;
3704
3705 /* It is possible that the packet buffer is not large enough
3706 * to provide required headroom. In this case throw an error
3707 * to user and a do the best we can.
3708 */
3709 if (marker < 0) {
3710 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3711 "headroom to support flow control."
3712 "Decrease MTU or number of traffic classes\n", pb);
3713 marker = tc + 1;
3714 }
3715
3716 return marker;
3717 }
3718
3719 /*
3720 * ixgbe_lpbthresh - calculate low water mark for for flow control
3721 *
3722 * @adapter: board private structure to calculate for
3723 * @pb - packet buffer to calculate
3724 */
3725 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3726 {
3727 struct ixgbe_hw *hw = &adapter->hw;
3728 struct net_device *dev = adapter->netdev;
3729 int tc;
3730 u32 dv_id;
3731
3732 /* Calculate max LAN frame size */
3733 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3734
3735 /* Calculate delay value for device */
3736 switch (hw->mac.type) {
3737 case ixgbe_mac_X540:
3738 dv_id = IXGBE_LOW_DV_X540(tc);
3739 break;
3740 default:
3741 dv_id = IXGBE_LOW_DV(tc);
3742 break;
3743 }
3744
3745 /* Delay value is calculated in bit times convert to KB */
3746 return IXGBE_BT2KB(dv_id);
3747 }
3748
3749 /*
3750 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3751 */
3752 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3753 {
3754 struct ixgbe_hw *hw = &adapter->hw;
3755 int num_tc = netdev_get_num_tc(adapter->netdev);
3756 int i;
3757
3758 if (!num_tc)
3759 num_tc = 1;
3760
3761 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3762
3763 for (i = 0; i < num_tc; i++) {
3764 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3765
3766 /* Low water marks must not be larger than high water marks */
3767 if (hw->fc.low_water > hw->fc.high_water[i])
3768 hw->fc.low_water = 0;
3769 }
3770 }
3771
3772 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3773 {
3774 struct ixgbe_hw *hw = &adapter->hw;
3775 int hdrm;
3776 u8 tc = netdev_get_num_tc(adapter->netdev);
3777
3778 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3779 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3780 hdrm = 32 << adapter->fdir_pballoc;
3781 else
3782 hdrm = 0;
3783
3784 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3785 ixgbe_pbthresh_setup(adapter);
3786 }
3787
3788 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3789 {
3790 struct ixgbe_hw *hw = &adapter->hw;
3791 struct hlist_node *node, *node2;
3792 struct ixgbe_fdir_filter *filter;
3793
3794 spin_lock(&adapter->fdir_perfect_lock);
3795
3796 if (!hlist_empty(&adapter->fdir_filter_list))
3797 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3798
3799 hlist_for_each_entry_safe(filter, node, node2,
3800 &adapter->fdir_filter_list, fdir_node) {
3801 ixgbe_fdir_write_perfect_filter_82599(hw,
3802 &filter->filter,
3803 filter->sw_idx,
3804 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3805 IXGBE_FDIR_DROP_QUEUE :
3806 adapter->rx_ring[filter->action]->reg_idx);
3807 }
3808
3809 spin_unlock(&adapter->fdir_perfect_lock);
3810 }
3811
3812 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3813 {
3814 struct ixgbe_hw *hw = &adapter->hw;
3815
3816 ixgbe_configure_pb(adapter);
3817 #ifdef CONFIG_IXGBE_DCB
3818 ixgbe_configure_dcb(adapter);
3819 #endif
3820
3821 ixgbe_set_rx_mode(adapter->netdev);
3822 ixgbe_restore_vlan(adapter);
3823
3824 #ifdef IXGBE_FCOE
3825 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3826 ixgbe_configure_fcoe(adapter);
3827
3828 #endif /* IXGBE_FCOE */
3829
3830 switch (hw->mac.type) {
3831 case ixgbe_mac_82599EB:
3832 case ixgbe_mac_X540:
3833 hw->mac.ops.disable_rx_buff(hw);
3834 break;
3835 default:
3836 break;
3837 }
3838
3839 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3840 ixgbe_init_fdir_signature_82599(&adapter->hw,
3841 adapter->fdir_pballoc);
3842 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3843 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3844 adapter->fdir_pballoc);
3845 ixgbe_fdir_filter_restore(adapter);
3846 }
3847
3848 switch (hw->mac.type) {
3849 case ixgbe_mac_82599EB:
3850 case ixgbe_mac_X540:
3851 hw->mac.ops.enable_rx_buff(hw);
3852 break;
3853 default:
3854 break;
3855 }
3856
3857 ixgbe_configure_virtualization(adapter);
3858
3859 ixgbe_configure_tx(adapter);
3860 ixgbe_configure_rx(adapter);
3861 }
3862
3863 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3864 {
3865 switch (hw->phy.type) {
3866 case ixgbe_phy_sfp_avago:
3867 case ixgbe_phy_sfp_ftl:
3868 case ixgbe_phy_sfp_intel:
3869 case ixgbe_phy_sfp_unknown:
3870 case ixgbe_phy_sfp_passive_tyco:
3871 case ixgbe_phy_sfp_passive_unknown:
3872 case ixgbe_phy_sfp_active_unknown:
3873 case ixgbe_phy_sfp_ftl_active:
3874 return true;
3875 case ixgbe_phy_nl:
3876 if (hw->mac.type == ixgbe_mac_82598EB)
3877 return true;
3878 default:
3879 return false;
3880 }
3881 }
3882
3883 /**
3884 * ixgbe_sfp_link_config - set up SFP+ link
3885 * @adapter: pointer to private adapter struct
3886 **/
3887 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3888 {
3889 /*
3890 * We are assuming the worst case scenario here, and that
3891 * is that an SFP was inserted/removed after the reset
3892 * but before SFP detection was enabled. As such the best
3893 * solution is to just start searching as soon as we start
3894 */
3895 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3896 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3897
3898 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3899 }
3900
3901 /**
3902 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3903 * @hw: pointer to private hardware struct
3904 *
3905 * Returns 0 on success, negative on failure
3906 **/
3907 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3908 {
3909 u32 autoneg;
3910 bool negotiation, link_up = false;
3911 u32 ret = IXGBE_ERR_LINK_SETUP;
3912
3913 if (hw->mac.ops.check_link)
3914 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3915
3916 if (ret)
3917 goto link_cfg_out;
3918
3919 autoneg = hw->phy.autoneg_advertised;
3920 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3921 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3922 &negotiation);
3923 if (ret)
3924 goto link_cfg_out;
3925
3926 if (hw->mac.ops.setup_link)
3927 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3928 link_cfg_out:
3929 return ret;
3930 }
3931
3932 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3933 {
3934 struct ixgbe_hw *hw = &adapter->hw;
3935 u32 gpie = 0;
3936
3937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3938 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3939 IXGBE_GPIE_OCD;
3940 gpie |= IXGBE_GPIE_EIAME;
3941 /*
3942 * use EIAM to auto-mask when MSI-X interrupt is asserted
3943 * this saves a register write for every interrupt
3944 */
3945 switch (hw->mac.type) {
3946 case ixgbe_mac_82598EB:
3947 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3948 break;
3949 case ixgbe_mac_82599EB:
3950 case ixgbe_mac_X540:
3951 default:
3952 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3953 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3954 break;
3955 }
3956 } else {
3957 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3958 * specifically only auto mask tx and rx interrupts */
3959 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3960 }
3961
3962 /* XXX: to interrupt immediately for EICS writes, enable this */
3963 /* gpie |= IXGBE_GPIE_EIMEN; */
3964
3965 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3966 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3967 gpie |= IXGBE_GPIE_VTMODE_64;
3968 }
3969
3970 /* Enable Thermal over heat sensor interrupt */
3971 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3972 switch (adapter->hw.mac.type) {
3973 case ixgbe_mac_82599EB:
3974 gpie |= IXGBE_SDP0_GPIEN;
3975 break;
3976 case ixgbe_mac_X540:
3977 gpie |= IXGBE_EIMS_TS;
3978 break;
3979 default:
3980 break;
3981 }
3982 }
3983
3984 /* Enable fan failure interrupt */
3985 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3986 gpie |= IXGBE_SDP1_GPIEN;
3987
3988 if (hw->mac.type == ixgbe_mac_82599EB) {
3989 gpie |= IXGBE_SDP1_GPIEN;
3990 gpie |= IXGBE_SDP2_GPIEN;
3991 }
3992
3993 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3994 }
3995
3996 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3997 {
3998 struct ixgbe_hw *hw = &adapter->hw;
3999 int err;
4000 u32 ctrl_ext;
4001
4002 ixgbe_get_hw_control(adapter);
4003 ixgbe_setup_gpie(adapter);
4004
4005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4006 ixgbe_configure_msix(adapter);
4007 else
4008 ixgbe_configure_msi_and_legacy(adapter);
4009
4010 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4011 if (hw->mac.ops.enable_tx_laser &&
4012 ((hw->phy.multispeed_fiber) ||
4013 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4014 (hw->mac.type == ixgbe_mac_82599EB))))
4015 hw->mac.ops.enable_tx_laser(hw);
4016
4017 clear_bit(__IXGBE_DOWN, &adapter->state);
4018 ixgbe_napi_enable_all(adapter);
4019
4020 if (ixgbe_is_sfp(hw)) {
4021 ixgbe_sfp_link_config(adapter);
4022 } else {
4023 err = ixgbe_non_sfp_link_config(hw);
4024 if (err)
4025 e_err(probe, "link_config FAILED %d\n", err);
4026 }
4027
4028 /* clear any pending interrupts, may auto mask */
4029 IXGBE_READ_REG(hw, IXGBE_EICR);
4030 ixgbe_irq_enable(adapter, true, true);
4031
4032 /*
4033 * If this adapter has a fan, check to see if we had a failure
4034 * before we enabled the interrupt.
4035 */
4036 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4037 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4038 if (esdp & IXGBE_ESDP_SDP1)
4039 e_crit(drv, "Fan has stopped, replace the adapter\n");
4040 }
4041
4042 /* enable transmits */
4043 netif_tx_start_all_queues(adapter->netdev);
4044
4045 /* bring the link up in the watchdog, this could race with our first
4046 * link up interrupt but shouldn't be a problem */
4047 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4048 adapter->link_check_timeout = jiffies;
4049 mod_timer(&adapter->service_timer, jiffies);
4050
4051 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4052 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4053 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4054 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4055 }
4056
4057 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4058 {
4059 WARN_ON(in_interrupt());
4060 /* put off any impending NetWatchDogTimeout */
4061 adapter->netdev->trans_start = jiffies;
4062
4063 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4064 usleep_range(1000, 2000);
4065 ixgbe_down(adapter);
4066 /*
4067 * If SR-IOV enabled then wait a bit before bringing the adapter
4068 * back up to give the VFs time to respond to the reset. The
4069 * two second wait is based upon the watchdog timer cycle in
4070 * the VF driver.
4071 */
4072 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4073 msleep(2000);
4074 ixgbe_up(adapter);
4075 clear_bit(__IXGBE_RESETTING, &adapter->state);
4076 }
4077
4078 void ixgbe_up(struct ixgbe_adapter *adapter)
4079 {
4080 /* hardware has been reset, we need to reload some things */
4081 ixgbe_configure(adapter);
4082
4083 ixgbe_up_complete(adapter);
4084 }
4085
4086 void ixgbe_reset(struct ixgbe_adapter *adapter)
4087 {
4088 struct ixgbe_hw *hw = &adapter->hw;
4089 int err;
4090
4091 /* lock SFP init bit to prevent race conditions with the watchdog */
4092 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4093 usleep_range(1000, 2000);
4094
4095 /* clear all SFP and link config related flags while holding SFP_INIT */
4096 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4097 IXGBE_FLAG2_SFP_NEEDS_RESET);
4098 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4099
4100 err = hw->mac.ops.init_hw(hw);
4101 switch (err) {
4102 case 0:
4103 case IXGBE_ERR_SFP_NOT_PRESENT:
4104 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4105 break;
4106 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4107 e_dev_err("master disable timed out\n");
4108 break;
4109 case IXGBE_ERR_EEPROM_VERSION:
4110 /* We are running on a pre-production device, log a warning */
4111 e_dev_warn("This device is a pre-production adapter/LOM. "
4112 "Please be aware there may be issues associated with "
4113 "your hardware. If you are experiencing problems "
4114 "please contact your Intel or hardware "
4115 "representative who provided you with this "
4116 "hardware.\n");
4117 break;
4118 default:
4119 e_dev_err("Hardware Error: %d\n", err);
4120 }
4121
4122 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4123
4124 /* reprogram the RAR[0] in case user changed it. */
4125 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4126 IXGBE_RAH_AV);
4127 }
4128
4129 /**
4130 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4131 * @rx_ring: ring to setup
4132 *
4133 * On many IA platforms the L1 cache has a critical stride of 4K, this
4134 * results in each receive buffer starting in the same cache set. To help
4135 * reduce the pressure on this cache set we can interleave the offsets so
4136 * that only every other buffer will be in the same cache set.
4137 **/
4138 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4139 {
4140 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4141 u16 i;
4142
4143 for (i = 0; i < rx_ring->count; i += 2) {
4144 rx_buffer[0].page_offset = 0;
4145 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4146 rx_buffer = &rx_buffer[2];
4147 }
4148 }
4149
4150 /**
4151 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4152 * @rx_ring: ring to free buffers from
4153 **/
4154 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4155 {
4156 struct device *dev = rx_ring->dev;
4157 unsigned long size;
4158 u16 i;
4159
4160 /* ring already cleared, nothing to do */
4161 if (!rx_ring->rx_buffer_info)
4162 return;
4163
4164 /* Free all the Rx ring sk_buffs */
4165 for (i = 0; i < rx_ring->count; i++) {
4166 struct ixgbe_rx_buffer *rx_buffer;
4167
4168 rx_buffer = &rx_ring->rx_buffer_info[i];
4169 if (rx_buffer->skb) {
4170 struct sk_buff *skb = rx_buffer->skb;
4171 if (IXGBE_CB(skb)->page_released) {
4172 dma_unmap_page(dev,
4173 IXGBE_CB(skb)->dma,
4174 ixgbe_rx_bufsz(rx_ring),
4175 DMA_FROM_DEVICE);
4176 IXGBE_CB(skb)->page_released = false;
4177 }
4178 dev_kfree_skb(skb);
4179 }
4180 rx_buffer->skb = NULL;
4181 if (rx_buffer->dma)
4182 dma_unmap_page(dev, rx_buffer->dma,
4183 ixgbe_rx_pg_size(rx_ring),
4184 DMA_FROM_DEVICE);
4185 rx_buffer->dma = 0;
4186 if (rx_buffer->page)
4187 __free_pages(rx_buffer->page,
4188 ixgbe_rx_pg_order(rx_ring));
4189 rx_buffer->page = NULL;
4190 }
4191
4192 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4193 memset(rx_ring->rx_buffer_info, 0, size);
4194
4195 ixgbe_init_rx_page_offset(rx_ring);
4196
4197 /* Zero out the descriptor ring */
4198 memset(rx_ring->desc, 0, rx_ring->size);
4199
4200 rx_ring->next_to_alloc = 0;
4201 rx_ring->next_to_clean = 0;
4202 rx_ring->next_to_use = 0;
4203 }
4204
4205 /**
4206 * ixgbe_clean_tx_ring - Free Tx Buffers
4207 * @tx_ring: ring to be cleaned
4208 **/
4209 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4210 {
4211 struct ixgbe_tx_buffer *tx_buffer_info;
4212 unsigned long size;
4213 u16 i;
4214
4215 /* ring already cleared, nothing to do */
4216 if (!tx_ring->tx_buffer_info)
4217 return;
4218
4219 /* Free all the Tx ring sk_buffs */
4220 for (i = 0; i < tx_ring->count; i++) {
4221 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4222 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4223 }
4224
4225 netdev_tx_reset_queue(txring_txq(tx_ring));
4226
4227 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4228 memset(tx_ring->tx_buffer_info, 0, size);
4229
4230 /* Zero out the descriptor ring */
4231 memset(tx_ring->desc, 0, tx_ring->size);
4232
4233 tx_ring->next_to_use = 0;
4234 tx_ring->next_to_clean = 0;
4235 }
4236
4237 /**
4238 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4239 * @adapter: board private structure
4240 **/
4241 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4242 {
4243 int i;
4244
4245 for (i = 0; i < adapter->num_rx_queues; i++)
4246 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4247 }
4248
4249 /**
4250 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4251 * @adapter: board private structure
4252 **/
4253 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4254 {
4255 int i;
4256
4257 for (i = 0; i < adapter->num_tx_queues; i++)
4258 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4259 }
4260
4261 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4262 {
4263 struct hlist_node *node, *node2;
4264 struct ixgbe_fdir_filter *filter;
4265
4266 spin_lock(&adapter->fdir_perfect_lock);
4267
4268 hlist_for_each_entry_safe(filter, node, node2,
4269 &adapter->fdir_filter_list, fdir_node) {
4270 hlist_del(&filter->fdir_node);
4271 kfree(filter);
4272 }
4273 adapter->fdir_filter_count = 0;
4274
4275 spin_unlock(&adapter->fdir_perfect_lock);
4276 }
4277
4278 void ixgbe_down(struct ixgbe_adapter *adapter)
4279 {
4280 struct net_device *netdev = adapter->netdev;
4281 struct ixgbe_hw *hw = &adapter->hw;
4282 u32 rxctrl;
4283 int i;
4284
4285 /* signal that we are down to the interrupt handler */
4286 set_bit(__IXGBE_DOWN, &adapter->state);
4287
4288 /* disable receives */
4289 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4290 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4291
4292 /* disable all enabled rx queues */
4293 for (i = 0; i < adapter->num_rx_queues; i++)
4294 /* this call also flushes the previous write */
4295 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4296
4297 usleep_range(10000, 20000);
4298
4299 netif_tx_stop_all_queues(netdev);
4300
4301 /* call carrier off first to avoid false dev_watchdog timeouts */
4302 netif_carrier_off(netdev);
4303 netif_tx_disable(netdev);
4304
4305 ixgbe_irq_disable(adapter);
4306
4307 ixgbe_napi_disable_all(adapter);
4308
4309 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4310 IXGBE_FLAG2_RESET_REQUESTED);
4311 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4312
4313 del_timer_sync(&adapter->service_timer);
4314
4315 if (adapter->num_vfs) {
4316 /* Clear EITR Select mapping */
4317 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4318
4319 /* Mark all the VFs as inactive */
4320 for (i = 0 ; i < adapter->num_vfs; i++)
4321 adapter->vfinfo[i].clear_to_send = false;
4322
4323 /* ping all the active vfs to let them know we are going down */
4324 ixgbe_ping_all_vfs(adapter);
4325
4326 /* Disable all VFTE/VFRE TX/RX */
4327 ixgbe_disable_tx_rx(adapter);
4328 }
4329
4330 /* disable transmits in the hardware now that interrupts are off */
4331 for (i = 0; i < adapter->num_tx_queues; i++) {
4332 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4333 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4334 }
4335
4336 /* Disable the Tx DMA engine on 82599 and X540 */
4337 switch (hw->mac.type) {
4338 case ixgbe_mac_82599EB:
4339 case ixgbe_mac_X540:
4340 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4341 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4342 ~IXGBE_DMATXCTL_TE));
4343 break;
4344 default:
4345 break;
4346 }
4347
4348 if (!pci_channel_offline(adapter->pdev))
4349 ixgbe_reset(adapter);
4350
4351 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4352 if (hw->mac.ops.disable_tx_laser &&
4353 ((hw->phy.multispeed_fiber) ||
4354 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4355 (hw->mac.type == ixgbe_mac_82599EB))))
4356 hw->mac.ops.disable_tx_laser(hw);
4357
4358 ixgbe_clean_all_tx_rings(adapter);
4359 ixgbe_clean_all_rx_rings(adapter);
4360
4361 #ifdef CONFIG_IXGBE_DCA
4362 /* since we reset the hardware DCA settings were cleared */
4363 ixgbe_setup_dca(adapter);
4364 #endif
4365 }
4366
4367 /**
4368 * ixgbe_tx_timeout - Respond to a Tx Hang
4369 * @netdev: network interface device structure
4370 **/
4371 static void ixgbe_tx_timeout(struct net_device *netdev)
4372 {
4373 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4374
4375 /* Do the reset outside of interrupt context */
4376 ixgbe_tx_timeout_reset(adapter);
4377 }
4378
4379 /**
4380 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4381 * @adapter: board private structure to initialize
4382 *
4383 * ixgbe_sw_init initializes the Adapter private data structure.
4384 * Fields are initialized based on PCI device information and
4385 * OS network device settings (MTU size).
4386 **/
4387 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4388 {
4389 struct ixgbe_hw *hw = &adapter->hw;
4390 struct pci_dev *pdev = adapter->pdev;
4391 unsigned int rss;
4392 #ifdef CONFIG_IXGBE_DCB
4393 int j;
4394 struct tc_configuration *tc;
4395 #endif
4396
4397 /* PCI config space info */
4398
4399 hw->vendor_id = pdev->vendor;
4400 hw->device_id = pdev->device;
4401 hw->revision_id = pdev->revision;
4402 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4403 hw->subsystem_device_id = pdev->subsystem_device;
4404
4405 /* Set capability flags */
4406 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4407 adapter->ring_feature[RING_F_RSS].indices = rss;
4408 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4409 switch (hw->mac.type) {
4410 case ixgbe_mac_82598EB:
4411 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4412 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4413 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4414 break;
4415 case ixgbe_mac_X540:
4416 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4417 case ixgbe_mac_82599EB:
4418 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4419 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4420 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4421 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4422 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4423 /* Flow Director hash filters enabled */
4424 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4425 adapter->atr_sample_rate = 20;
4426 adapter->ring_feature[RING_F_FDIR].indices =
4427 IXGBE_MAX_FDIR_INDICES;
4428 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4429 #ifdef IXGBE_FCOE
4430 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4431 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4432 adapter->ring_feature[RING_F_FCOE].indices = 0;
4433 #ifdef CONFIG_IXGBE_DCB
4434 /* Default traffic class to use for FCoE */
4435 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4436 #endif
4437 #endif /* IXGBE_FCOE */
4438 break;
4439 default:
4440 break;
4441 }
4442
4443 /* n-tuple support exists, always init our spinlock */
4444 spin_lock_init(&adapter->fdir_perfect_lock);
4445
4446 #ifdef CONFIG_IXGBE_DCB
4447 switch (hw->mac.type) {
4448 case ixgbe_mac_X540:
4449 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4450 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4451 break;
4452 default:
4453 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4454 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4455 break;
4456 }
4457
4458 /* Configure DCB traffic classes */
4459 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4460 tc = &adapter->dcb_cfg.tc_config[j];
4461 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4462 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4463 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4464 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4465 tc->dcb_pfc = pfc_disabled;
4466 }
4467
4468 /* Initialize default user to priority mapping, UPx->TC0 */
4469 tc = &adapter->dcb_cfg.tc_config[0];
4470 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4471 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4472
4473 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4474 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4475 adapter->dcb_cfg.pfc_mode_enable = false;
4476 adapter->dcb_set_bitmap = 0x00;
4477 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4478 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4479 sizeof(adapter->temp_dcb_cfg));
4480
4481 #endif
4482
4483 /* default flow control settings */
4484 hw->fc.requested_mode = ixgbe_fc_full;
4485 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4486 ixgbe_pbthresh_setup(adapter);
4487 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4488 hw->fc.send_xon = true;
4489 hw->fc.disable_fc_autoneg = false;
4490
4491 /* enable itr by default in dynamic mode */
4492 adapter->rx_itr_setting = 1;
4493 adapter->tx_itr_setting = 1;
4494
4495 /* set default ring sizes */
4496 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4497 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4498
4499 /* set default work limits */
4500 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4501
4502 /* initialize eeprom parameters */
4503 if (ixgbe_init_eeprom_params_generic(hw)) {
4504 e_dev_err("EEPROM initialization failed\n");
4505 return -EIO;
4506 }
4507
4508 set_bit(__IXGBE_DOWN, &adapter->state);
4509
4510 return 0;
4511 }
4512
4513 /**
4514 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4515 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4516 *
4517 * Return 0 on success, negative on failure
4518 **/
4519 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4520 {
4521 struct device *dev = tx_ring->dev;
4522 int orig_node = dev_to_node(dev);
4523 int numa_node = -1;
4524 int size;
4525
4526 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4527
4528 if (tx_ring->q_vector)
4529 numa_node = tx_ring->q_vector->numa_node;
4530
4531 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4532 if (!tx_ring->tx_buffer_info)
4533 tx_ring->tx_buffer_info = vzalloc(size);
4534 if (!tx_ring->tx_buffer_info)
4535 goto err;
4536
4537 /* round up to nearest 4K */
4538 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4539 tx_ring->size = ALIGN(tx_ring->size, 4096);
4540
4541 set_dev_node(dev, numa_node);
4542 tx_ring->desc = dma_alloc_coherent(dev,
4543 tx_ring->size,
4544 &tx_ring->dma,
4545 GFP_KERNEL);
4546 set_dev_node(dev, orig_node);
4547 if (!tx_ring->desc)
4548 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4549 &tx_ring->dma, GFP_KERNEL);
4550 if (!tx_ring->desc)
4551 goto err;
4552
4553 tx_ring->next_to_use = 0;
4554 tx_ring->next_to_clean = 0;
4555 return 0;
4556
4557 err:
4558 vfree(tx_ring->tx_buffer_info);
4559 tx_ring->tx_buffer_info = NULL;
4560 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4561 return -ENOMEM;
4562 }
4563
4564 /**
4565 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4566 * @adapter: board private structure
4567 *
4568 * If this function returns with an error, then it's possible one or
4569 * more of the rings is populated (while the rest are not). It is the
4570 * callers duty to clean those orphaned rings.
4571 *
4572 * Return 0 on success, negative on failure
4573 **/
4574 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4575 {
4576 int i, err = 0;
4577
4578 for (i = 0; i < adapter->num_tx_queues; i++) {
4579 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4580 if (!err)
4581 continue;
4582 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4583 break;
4584 }
4585
4586 return err;
4587 }
4588
4589 /**
4590 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4591 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4592 *
4593 * Returns 0 on success, negative on failure
4594 **/
4595 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4596 {
4597 struct device *dev = rx_ring->dev;
4598 int orig_node = dev_to_node(dev);
4599 int numa_node = -1;
4600 int size;
4601
4602 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4603
4604 if (rx_ring->q_vector)
4605 numa_node = rx_ring->q_vector->numa_node;
4606
4607 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4608 if (!rx_ring->rx_buffer_info)
4609 rx_ring->rx_buffer_info = vzalloc(size);
4610 if (!rx_ring->rx_buffer_info)
4611 goto err;
4612
4613 /* Round up to nearest 4K */
4614 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4615 rx_ring->size = ALIGN(rx_ring->size, 4096);
4616
4617 set_dev_node(dev, numa_node);
4618 rx_ring->desc = dma_alloc_coherent(dev,
4619 rx_ring->size,
4620 &rx_ring->dma,
4621 GFP_KERNEL);
4622 set_dev_node(dev, orig_node);
4623 if (!rx_ring->desc)
4624 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4625 &rx_ring->dma, GFP_KERNEL);
4626 if (!rx_ring->desc)
4627 goto err;
4628
4629 rx_ring->next_to_clean = 0;
4630 rx_ring->next_to_use = 0;
4631
4632 ixgbe_init_rx_page_offset(rx_ring);
4633
4634 return 0;
4635 err:
4636 vfree(rx_ring->rx_buffer_info);
4637 rx_ring->rx_buffer_info = NULL;
4638 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4639 return -ENOMEM;
4640 }
4641
4642 /**
4643 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4644 * @adapter: board private structure
4645 *
4646 * If this function returns with an error, then it's possible one or
4647 * more of the rings is populated (while the rest are not). It is the
4648 * callers duty to clean those orphaned rings.
4649 *
4650 * Return 0 on success, negative on failure
4651 **/
4652 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4653 {
4654 int i, err = 0;
4655
4656 for (i = 0; i < adapter->num_rx_queues; i++) {
4657 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4658 if (!err)
4659 continue;
4660 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4661 break;
4662 }
4663
4664 return err;
4665 }
4666
4667 /**
4668 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4669 * @tx_ring: Tx descriptor ring for a specific queue
4670 *
4671 * Free all transmit software resources
4672 **/
4673 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4674 {
4675 ixgbe_clean_tx_ring(tx_ring);
4676
4677 vfree(tx_ring->tx_buffer_info);
4678 tx_ring->tx_buffer_info = NULL;
4679
4680 /* if not set, then don't free */
4681 if (!tx_ring->desc)
4682 return;
4683
4684 dma_free_coherent(tx_ring->dev, tx_ring->size,
4685 tx_ring->desc, tx_ring->dma);
4686
4687 tx_ring->desc = NULL;
4688 }
4689
4690 /**
4691 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4692 * @adapter: board private structure
4693 *
4694 * Free all transmit software resources
4695 **/
4696 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4697 {
4698 int i;
4699
4700 for (i = 0; i < adapter->num_tx_queues; i++)
4701 if (adapter->tx_ring[i]->desc)
4702 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4703 }
4704
4705 /**
4706 * ixgbe_free_rx_resources - Free Rx Resources
4707 * @rx_ring: ring to clean the resources from
4708 *
4709 * Free all receive software resources
4710 **/
4711 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4712 {
4713 ixgbe_clean_rx_ring(rx_ring);
4714
4715 vfree(rx_ring->rx_buffer_info);
4716 rx_ring->rx_buffer_info = NULL;
4717
4718 /* if not set, then don't free */
4719 if (!rx_ring->desc)
4720 return;
4721
4722 dma_free_coherent(rx_ring->dev, rx_ring->size,
4723 rx_ring->desc, rx_ring->dma);
4724
4725 rx_ring->desc = NULL;
4726 }
4727
4728 /**
4729 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4730 * @adapter: board private structure
4731 *
4732 * Free all receive software resources
4733 **/
4734 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4735 {
4736 int i;
4737
4738 for (i = 0; i < adapter->num_rx_queues; i++)
4739 if (adapter->rx_ring[i]->desc)
4740 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4741 }
4742
4743 /**
4744 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4745 * @netdev: network interface device structure
4746 * @new_mtu: new value for maximum frame size
4747 *
4748 * Returns 0 on success, negative on failure
4749 **/
4750 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4751 {
4752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4753 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4754
4755 /* MTU < 68 is an error and causes problems on some kernels */
4756 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4757 return -EINVAL;
4758
4759 /*
4760 * For 82599EB we cannot allow PF to change MTU greater than 1500
4761 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4762 * don't allocate and chain buffers correctly.
4763 */
4764 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4765 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4766 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4767 return -EINVAL;
4768
4769 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4770
4771 /* must set new MTU before calling down or up */
4772 netdev->mtu = new_mtu;
4773
4774 if (netif_running(netdev))
4775 ixgbe_reinit_locked(adapter);
4776
4777 return 0;
4778 }
4779
4780 /**
4781 * ixgbe_open - Called when a network interface is made active
4782 * @netdev: network interface device structure
4783 *
4784 * Returns 0 on success, negative value on failure
4785 *
4786 * The open entry point is called when a network interface is made
4787 * active by the system (IFF_UP). At this point all resources needed
4788 * for transmit and receive operations are allocated, the interrupt
4789 * handler is registered with the OS, the watchdog timer is started,
4790 * and the stack is notified that the interface is ready.
4791 **/
4792 static int ixgbe_open(struct net_device *netdev)
4793 {
4794 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4795 int err;
4796
4797 /* disallow open during test */
4798 if (test_bit(__IXGBE_TESTING, &adapter->state))
4799 return -EBUSY;
4800
4801 netif_carrier_off(netdev);
4802
4803 /* allocate transmit descriptors */
4804 err = ixgbe_setup_all_tx_resources(adapter);
4805 if (err)
4806 goto err_setup_tx;
4807
4808 /* allocate receive descriptors */
4809 err = ixgbe_setup_all_rx_resources(adapter);
4810 if (err)
4811 goto err_setup_rx;
4812
4813 ixgbe_configure(adapter);
4814
4815 err = ixgbe_request_irq(adapter);
4816 if (err)
4817 goto err_req_irq;
4818
4819 ixgbe_up_complete(adapter);
4820
4821 return 0;
4822
4823 err_req_irq:
4824 err_setup_rx:
4825 ixgbe_free_all_rx_resources(adapter);
4826 err_setup_tx:
4827 ixgbe_free_all_tx_resources(adapter);
4828 ixgbe_reset(adapter);
4829
4830 return err;
4831 }
4832
4833 /**
4834 * ixgbe_close - Disables a network interface
4835 * @netdev: network interface device structure
4836 *
4837 * Returns 0, this is not allowed to fail
4838 *
4839 * The close entry point is called when an interface is de-activated
4840 * by the OS. The hardware is still under the drivers control, but
4841 * needs to be disabled. A global MAC reset is issued to stop the
4842 * hardware, and all transmit and receive resources are freed.
4843 **/
4844 static int ixgbe_close(struct net_device *netdev)
4845 {
4846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4847
4848 ixgbe_down(adapter);
4849 ixgbe_free_irq(adapter);
4850
4851 ixgbe_fdir_filter_exit(adapter);
4852
4853 ixgbe_free_all_tx_resources(adapter);
4854 ixgbe_free_all_rx_resources(adapter);
4855
4856 ixgbe_release_hw_control(adapter);
4857
4858 return 0;
4859 }
4860
4861 #ifdef CONFIG_PM
4862 static int ixgbe_resume(struct pci_dev *pdev)
4863 {
4864 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4865 struct net_device *netdev = adapter->netdev;
4866 u32 err;
4867
4868 pci_set_power_state(pdev, PCI_D0);
4869 pci_restore_state(pdev);
4870 /*
4871 * pci_restore_state clears dev->state_saved so call
4872 * pci_save_state to restore it.
4873 */
4874 pci_save_state(pdev);
4875
4876 err = pci_enable_device_mem(pdev);
4877 if (err) {
4878 e_dev_err("Cannot enable PCI device from suspend\n");
4879 return err;
4880 }
4881 pci_set_master(pdev);
4882
4883 pci_wake_from_d3(pdev, false);
4884
4885 rtnl_lock();
4886 err = ixgbe_init_interrupt_scheme(adapter);
4887 rtnl_unlock();
4888 if (err) {
4889 e_dev_err("Cannot initialize interrupts for device\n");
4890 return err;
4891 }
4892
4893 ixgbe_reset(adapter);
4894
4895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4896
4897 if (netif_running(netdev)) {
4898 err = ixgbe_open(netdev);
4899 if (err)
4900 return err;
4901 }
4902
4903 netif_device_attach(netdev);
4904
4905 return 0;
4906 }
4907 #endif /* CONFIG_PM */
4908
4909 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4910 {
4911 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4912 struct net_device *netdev = adapter->netdev;
4913 struct ixgbe_hw *hw = &adapter->hw;
4914 u32 ctrl, fctrl;
4915 u32 wufc = adapter->wol;
4916 #ifdef CONFIG_PM
4917 int retval = 0;
4918 #endif
4919
4920 netif_device_detach(netdev);
4921
4922 if (netif_running(netdev)) {
4923 rtnl_lock();
4924 ixgbe_down(adapter);
4925 ixgbe_free_irq(adapter);
4926 ixgbe_free_all_tx_resources(adapter);
4927 ixgbe_free_all_rx_resources(adapter);
4928 rtnl_unlock();
4929 }
4930
4931 ixgbe_clear_interrupt_scheme(adapter);
4932
4933 #ifdef CONFIG_PM
4934 retval = pci_save_state(pdev);
4935 if (retval)
4936 return retval;
4937
4938 #endif
4939 if (wufc) {
4940 ixgbe_set_rx_mode(netdev);
4941
4942 /*
4943 * enable the optics for both mult-speed fiber and
4944 * 82599 SFP+ fiber as we can WoL.
4945 */
4946 if (hw->mac.ops.enable_tx_laser &&
4947 (hw->phy.multispeed_fiber ||
4948 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4949 hw->mac.type == ixgbe_mac_82599EB)))
4950 hw->mac.ops.enable_tx_laser(hw);
4951
4952 /* turn on all-multi mode if wake on multicast is enabled */
4953 if (wufc & IXGBE_WUFC_MC) {
4954 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4955 fctrl |= IXGBE_FCTRL_MPE;
4956 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4957 }
4958
4959 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4960 ctrl |= IXGBE_CTRL_GIO_DIS;
4961 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4962
4963 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4964 } else {
4965 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4966 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4967 }
4968
4969 switch (hw->mac.type) {
4970 case ixgbe_mac_82598EB:
4971 pci_wake_from_d3(pdev, false);
4972 break;
4973 case ixgbe_mac_82599EB:
4974 case ixgbe_mac_X540:
4975 pci_wake_from_d3(pdev, !!wufc);
4976 break;
4977 default:
4978 break;
4979 }
4980
4981 *enable_wake = !!wufc;
4982
4983 ixgbe_release_hw_control(adapter);
4984
4985 pci_disable_device(pdev);
4986
4987 return 0;
4988 }
4989
4990 #ifdef CONFIG_PM
4991 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4992 {
4993 int retval;
4994 bool wake;
4995
4996 retval = __ixgbe_shutdown(pdev, &wake);
4997 if (retval)
4998 return retval;
4999
5000 if (wake) {
5001 pci_prepare_to_sleep(pdev);
5002 } else {
5003 pci_wake_from_d3(pdev, false);
5004 pci_set_power_state(pdev, PCI_D3hot);
5005 }
5006
5007 return 0;
5008 }
5009 #endif /* CONFIG_PM */
5010
5011 static void ixgbe_shutdown(struct pci_dev *pdev)
5012 {
5013 bool wake;
5014
5015 __ixgbe_shutdown(pdev, &wake);
5016
5017 if (system_state == SYSTEM_POWER_OFF) {
5018 pci_wake_from_d3(pdev, wake);
5019 pci_set_power_state(pdev, PCI_D3hot);
5020 }
5021 }
5022
5023 /**
5024 * ixgbe_update_stats - Update the board statistics counters.
5025 * @adapter: board private structure
5026 **/
5027 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5028 {
5029 struct net_device *netdev = adapter->netdev;
5030 struct ixgbe_hw *hw = &adapter->hw;
5031 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5032 u64 total_mpc = 0;
5033 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5034 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5035 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5036 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5037 #ifdef IXGBE_FCOE
5038 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5039 unsigned int cpu;
5040 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5041 #endif /* IXGBE_FCOE */
5042
5043 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5044 test_bit(__IXGBE_RESETTING, &adapter->state))
5045 return;
5046
5047 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5048 u64 rsc_count = 0;
5049 u64 rsc_flush = 0;
5050 for (i = 0; i < adapter->num_rx_queues; i++) {
5051 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5052 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5053 }
5054 adapter->rsc_total_count = rsc_count;
5055 adapter->rsc_total_flush = rsc_flush;
5056 }
5057
5058 for (i = 0; i < adapter->num_rx_queues; i++) {
5059 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5060 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5061 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5062 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5063 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5064 bytes += rx_ring->stats.bytes;
5065 packets += rx_ring->stats.packets;
5066 }
5067 adapter->non_eop_descs = non_eop_descs;
5068 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5069 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5070 adapter->hw_csum_rx_error = hw_csum_rx_error;
5071 netdev->stats.rx_bytes = bytes;
5072 netdev->stats.rx_packets = packets;
5073
5074 bytes = 0;
5075 packets = 0;
5076 /* gather some stats to the adapter struct that are per queue */
5077 for (i = 0; i < adapter->num_tx_queues; i++) {
5078 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5079 restart_queue += tx_ring->tx_stats.restart_queue;
5080 tx_busy += tx_ring->tx_stats.tx_busy;
5081 bytes += tx_ring->stats.bytes;
5082 packets += tx_ring->stats.packets;
5083 }
5084 adapter->restart_queue = restart_queue;
5085 adapter->tx_busy = tx_busy;
5086 netdev->stats.tx_bytes = bytes;
5087 netdev->stats.tx_packets = packets;
5088
5089 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5090
5091 /* 8 register reads */
5092 for (i = 0; i < 8; i++) {
5093 /* for packet buffers not used, the register should read 0 */
5094 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5095 missed_rx += mpc;
5096 hwstats->mpc[i] += mpc;
5097 total_mpc += hwstats->mpc[i];
5098 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5099 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5100 switch (hw->mac.type) {
5101 case ixgbe_mac_82598EB:
5102 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5103 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5104 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5105 hwstats->pxonrxc[i] +=
5106 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5107 break;
5108 case ixgbe_mac_82599EB:
5109 case ixgbe_mac_X540:
5110 hwstats->pxonrxc[i] +=
5111 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5112 break;
5113 default:
5114 break;
5115 }
5116 }
5117
5118 /*16 register reads */
5119 for (i = 0; i < 16; i++) {
5120 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5121 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5122 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5123 (hw->mac.type == ixgbe_mac_X540)) {
5124 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5125 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5126 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5127 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5128 }
5129 }
5130
5131 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5132 /* work around hardware counting issue */
5133 hwstats->gprc -= missed_rx;
5134
5135 ixgbe_update_xoff_received(adapter);
5136
5137 /* 82598 hardware only has a 32 bit counter in the high register */
5138 switch (hw->mac.type) {
5139 case ixgbe_mac_82598EB:
5140 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5141 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5142 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5143 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5144 break;
5145 case ixgbe_mac_X540:
5146 /* OS2BMC stats are X540 only*/
5147 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5148 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5149 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5150 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5151 case ixgbe_mac_82599EB:
5152 for (i = 0; i < 16; i++)
5153 adapter->hw_rx_no_dma_resources +=
5154 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5155 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5156 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5157 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5158 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5159 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5160 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5161 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5162 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5163 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5164 #ifdef IXGBE_FCOE
5165 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5166 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5167 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5168 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5169 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5170 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5171 /* Add up per cpu counters for total ddp aloc fail */
5172 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5173 for_each_possible_cpu(cpu) {
5174 fcoe_noddp_counts_sum +=
5175 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5176 fcoe_noddp_ext_buff_counts_sum +=
5177 *per_cpu_ptr(fcoe->
5178 pcpu_noddp_ext_buff, cpu);
5179 }
5180 }
5181 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5182 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5183 #endif /* IXGBE_FCOE */
5184 break;
5185 default:
5186 break;
5187 }
5188 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5189 hwstats->bprc += bprc;
5190 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5191 if (hw->mac.type == ixgbe_mac_82598EB)
5192 hwstats->mprc -= bprc;
5193 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5194 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5195 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5196 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5197 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5198 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5199 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5200 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5201 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5202 hwstats->lxontxc += lxon;
5203 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5204 hwstats->lxofftxc += lxoff;
5205 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5206 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5207 /*
5208 * 82598 errata - tx of flow control packets is included in tx counters
5209 */
5210 xon_off_tot = lxon + lxoff;
5211 hwstats->gptc -= xon_off_tot;
5212 hwstats->mptc -= xon_off_tot;
5213 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5214 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5215 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5216 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5217 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5218 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5219 hwstats->ptc64 -= xon_off_tot;
5220 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5221 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5222 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5223 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5224 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5225 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5226
5227 /* Fill out the OS statistics structure */
5228 netdev->stats.multicast = hwstats->mprc;
5229
5230 /* Rx Errors */
5231 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5232 netdev->stats.rx_dropped = 0;
5233 netdev->stats.rx_length_errors = hwstats->rlec;
5234 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5235 netdev->stats.rx_missed_errors = total_mpc;
5236 }
5237
5238 /**
5239 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5240 * @adapter - pointer to the device adapter structure
5241 **/
5242 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5243 {
5244 struct ixgbe_hw *hw = &adapter->hw;
5245 int i;
5246
5247 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5248 return;
5249
5250 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5251
5252 /* if interface is down do nothing */
5253 if (test_bit(__IXGBE_DOWN, &adapter->state))
5254 return;
5255
5256 /* do nothing if we are not using signature filters */
5257 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5258 return;
5259
5260 adapter->fdir_overflow++;
5261
5262 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5263 for (i = 0; i < adapter->num_tx_queues; i++)
5264 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5265 &(adapter->tx_ring[i]->state));
5266 /* re-enable flow director interrupts */
5267 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5268 } else {
5269 e_err(probe, "failed to finish FDIR re-initialization, "
5270 "ignored adding FDIR ATR filters\n");
5271 }
5272 }
5273
5274 /**
5275 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5276 * @adapter - pointer to the device adapter structure
5277 *
5278 * This function serves two purposes. First it strobes the interrupt lines
5279 * in order to make certain interrupts are occurring. Secondly it sets the
5280 * bits needed to check for TX hangs. As a result we should immediately
5281 * determine if a hang has occurred.
5282 */
5283 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5284 {
5285 struct ixgbe_hw *hw = &adapter->hw;
5286 u64 eics = 0;
5287 int i;
5288
5289 /* If we're down or resetting, just bail */
5290 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5291 test_bit(__IXGBE_RESETTING, &adapter->state))
5292 return;
5293
5294 /* Force detection of hung controller */
5295 if (netif_carrier_ok(adapter->netdev)) {
5296 for (i = 0; i < adapter->num_tx_queues; i++)
5297 set_check_for_tx_hang(adapter->tx_ring[i]);
5298 }
5299
5300 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5301 /*
5302 * for legacy and MSI interrupts don't set any bits
5303 * that are enabled for EIAM, because this operation
5304 * would set *both* EIMS and EICS for any bit in EIAM
5305 */
5306 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5307 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5308 } else {
5309 /* get one bit for every active tx/rx interrupt vector */
5310 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5311 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5312 if (qv->rx.ring || qv->tx.ring)
5313 eics |= ((u64)1 << i);
5314 }
5315 }
5316
5317 /* Cause software interrupt to ensure rings are cleaned */
5318 ixgbe_irq_rearm_queues(adapter, eics);
5319
5320 }
5321
5322 /**
5323 * ixgbe_watchdog_update_link - update the link status
5324 * @adapter - pointer to the device adapter structure
5325 * @link_speed - pointer to a u32 to store the link_speed
5326 **/
5327 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5328 {
5329 struct ixgbe_hw *hw = &adapter->hw;
5330 u32 link_speed = adapter->link_speed;
5331 bool link_up = adapter->link_up;
5332 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5333
5334 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5335 return;
5336
5337 if (hw->mac.ops.check_link) {
5338 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5339 } else {
5340 /* always assume link is up, if no check link function */
5341 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5342 link_up = true;
5343 }
5344
5345 if (adapter->ixgbe_ieee_pfc)
5346 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5347
5348 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5349 hw->mac.ops.fc_enable(hw);
5350 ixgbe_set_rx_drop_en(adapter);
5351 }
5352
5353 if (link_up ||
5354 time_after(jiffies, (adapter->link_check_timeout +
5355 IXGBE_TRY_LINK_TIMEOUT))) {
5356 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5357 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5358 IXGBE_WRITE_FLUSH(hw);
5359 }
5360
5361 adapter->link_up = link_up;
5362 adapter->link_speed = link_speed;
5363 }
5364
5365 /**
5366 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5367 * print link up message
5368 * @adapter - pointer to the device adapter structure
5369 **/
5370 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5371 {
5372 struct net_device *netdev = adapter->netdev;
5373 struct ixgbe_hw *hw = &adapter->hw;
5374 u32 link_speed = adapter->link_speed;
5375 bool flow_rx, flow_tx;
5376
5377 /* only continue if link was previously down */
5378 if (netif_carrier_ok(netdev))
5379 return;
5380
5381 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5382
5383 switch (hw->mac.type) {
5384 case ixgbe_mac_82598EB: {
5385 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5386 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5387 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5388 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5389 }
5390 break;
5391 case ixgbe_mac_X540:
5392 case ixgbe_mac_82599EB: {
5393 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5394 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5395 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5396 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5397 }
5398 break;
5399 default:
5400 flow_tx = false;
5401 flow_rx = false;
5402 break;
5403 }
5404
5405 #ifdef CONFIG_IXGBE_PTP
5406 ixgbe_ptp_start_cyclecounter(adapter);
5407 #endif
5408
5409 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5410 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5411 "10 Gbps" :
5412 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5413 "1 Gbps" :
5414 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5415 "100 Mbps" :
5416 "unknown speed"))),
5417 ((flow_rx && flow_tx) ? "RX/TX" :
5418 (flow_rx ? "RX" :
5419 (flow_tx ? "TX" : "None"))));
5420
5421 netif_carrier_on(netdev);
5422 ixgbe_check_vf_rate_limit(adapter);
5423 }
5424
5425 /**
5426 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5427 * print link down message
5428 * @adapter - pointer to the adapter structure
5429 **/
5430 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5431 {
5432 struct net_device *netdev = adapter->netdev;
5433 struct ixgbe_hw *hw = &adapter->hw;
5434
5435 adapter->link_up = false;
5436 adapter->link_speed = 0;
5437
5438 /* only continue if link was up previously */
5439 if (!netif_carrier_ok(netdev))
5440 return;
5441
5442 /* poll for SFP+ cable when link is down */
5443 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5444 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5445
5446 #ifdef CONFIG_IXGBE_PTP
5447 ixgbe_ptp_start_cyclecounter(adapter);
5448 #endif
5449
5450 e_info(drv, "NIC Link is Down\n");
5451 netif_carrier_off(netdev);
5452 }
5453
5454 /**
5455 * ixgbe_watchdog_flush_tx - flush queues on link down
5456 * @adapter - pointer to the device adapter structure
5457 **/
5458 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5459 {
5460 int i;
5461 int some_tx_pending = 0;
5462
5463 if (!netif_carrier_ok(adapter->netdev)) {
5464 for (i = 0; i < adapter->num_tx_queues; i++) {
5465 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5466 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5467 some_tx_pending = 1;
5468 break;
5469 }
5470 }
5471
5472 if (some_tx_pending) {
5473 /* We've lost link, so the controller stops DMA,
5474 * but we've got queued Tx work that's never going
5475 * to get done, so reset controller to flush Tx.
5476 * (Do the reset outside of interrupt context).
5477 */
5478 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5479 }
5480 }
5481 }
5482
5483 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5484 {
5485 u32 ssvpc;
5486
5487 /* Do not perform spoof check for 82598 */
5488 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5489 return;
5490
5491 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5492
5493 /*
5494 * ssvpc register is cleared on read, if zero then no
5495 * spoofed packets in the last interval.
5496 */
5497 if (!ssvpc)
5498 return;
5499
5500 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5501 }
5502
5503 /**
5504 * ixgbe_watchdog_subtask - check and bring link up
5505 * @adapter - pointer to the device adapter structure
5506 **/
5507 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5508 {
5509 /* if interface is down do nothing */
5510 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5511 test_bit(__IXGBE_RESETTING, &adapter->state))
5512 return;
5513
5514 ixgbe_watchdog_update_link(adapter);
5515
5516 if (adapter->link_up)
5517 ixgbe_watchdog_link_is_up(adapter);
5518 else
5519 ixgbe_watchdog_link_is_down(adapter);
5520
5521 ixgbe_spoof_check(adapter);
5522 ixgbe_update_stats(adapter);
5523
5524 ixgbe_watchdog_flush_tx(adapter);
5525 }
5526
5527 /**
5528 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5529 * @adapter - the ixgbe adapter structure
5530 **/
5531 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5532 {
5533 struct ixgbe_hw *hw = &adapter->hw;
5534 s32 err;
5535
5536 /* not searching for SFP so there is nothing to do here */
5537 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5538 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5539 return;
5540
5541 /* someone else is in init, wait until next service event */
5542 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5543 return;
5544
5545 err = hw->phy.ops.identify_sfp(hw);
5546 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5547 goto sfp_out;
5548
5549 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5550 /* If no cable is present, then we need to reset
5551 * the next time we find a good cable. */
5552 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5553 }
5554
5555 /* exit on error */
5556 if (err)
5557 goto sfp_out;
5558
5559 /* exit if reset not needed */
5560 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5561 goto sfp_out;
5562
5563 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5564
5565 /*
5566 * A module may be identified correctly, but the EEPROM may not have
5567 * support for that module. setup_sfp() will fail in that case, so
5568 * we should not allow that module to load.
5569 */
5570 if (hw->mac.type == ixgbe_mac_82598EB)
5571 err = hw->phy.ops.reset(hw);
5572 else
5573 err = hw->mac.ops.setup_sfp(hw);
5574
5575 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5576 goto sfp_out;
5577
5578 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5579 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5580
5581 sfp_out:
5582 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5583
5584 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5585 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5586 e_dev_err("failed to initialize because an unsupported "
5587 "SFP+ module type was detected.\n");
5588 e_dev_err("Reload the driver after installing a "
5589 "supported module.\n");
5590 unregister_netdev(adapter->netdev);
5591 }
5592 }
5593
5594 /**
5595 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5596 * @adapter - the ixgbe adapter structure
5597 **/
5598 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5599 {
5600 struct ixgbe_hw *hw = &adapter->hw;
5601 u32 autoneg;
5602 bool negotiation;
5603
5604 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5605 return;
5606
5607 /* someone else is in init, wait until next service event */
5608 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5609 return;
5610
5611 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5612
5613 autoneg = hw->phy.autoneg_advertised;
5614 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5615 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5616 if (hw->mac.ops.setup_link)
5617 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5618
5619 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5620 adapter->link_check_timeout = jiffies;
5621 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5622 }
5623
5624 #ifdef CONFIG_PCI_IOV
5625 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5626 {
5627 int vf;
5628 struct ixgbe_hw *hw = &adapter->hw;
5629 struct net_device *netdev = adapter->netdev;
5630 u32 gpc;
5631 u32 ciaa, ciad;
5632
5633 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5634 if (gpc) /* If incrementing then no need for the check below */
5635 return;
5636 /*
5637 * Check to see if a bad DMA write target from an errant or
5638 * malicious VF has caused a PCIe error. If so then we can
5639 * issue a VFLR to the offending VF(s) and then resume without
5640 * requesting a full slot reset.
5641 */
5642
5643 for (vf = 0; vf < adapter->num_vfs; vf++) {
5644 ciaa = (vf << 16) | 0x80000000;
5645 /* 32 bit read so align, we really want status at offset 6 */
5646 ciaa |= PCI_COMMAND;
5647 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5648 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5649 ciaa &= 0x7FFFFFFF;
5650 /* disable debug mode asap after reading data */
5651 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5652 /* Get the upper 16 bits which will be the PCI status reg */
5653 ciad >>= 16;
5654 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5655 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5656 /* Issue VFLR */
5657 ciaa = (vf << 16) | 0x80000000;
5658 ciaa |= 0xA8;
5659 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5660 ciad = 0x00008000; /* VFLR */
5661 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5662 ciaa &= 0x7FFFFFFF;
5663 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5664 }
5665 }
5666 }
5667
5668 #endif
5669 /**
5670 * ixgbe_service_timer - Timer Call-back
5671 * @data: pointer to adapter cast into an unsigned long
5672 **/
5673 static void ixgbe_service_timer(unsigned long data)
5674 {
5675 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5676 unsigned long next_event_offset;
5677 bool ready = true;
5678
5679 /* poll faster when waiting for link */
5680 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5681 next_event_offset = HZ / 10;
5682 else
5683 next_event_offset = HZ * 2;
5684
5685 #ifdef CONFIG_PCI_IOV
5686 /*
5687 * don't bother with SR-IOV VF DMA hang check if there are
5688 * no VFs or the link is down
5689 */
5690 if (!adapter->num_vfs ||
5691 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5692 goto normal_timer_service;
5693
5694 /* If we have VFs allocated then we must check for DMA hangs */
5695 ixgbe_check_for_bad_vf(adapter);
5696 next_event_offset = HZ / 50;
5697 adapter->timer_event_accumulator++;
5698
5699 if (adapter->timer_event_accumulator >= 100)
5700 adapter->timer_event_accumulator = 0;
5701 else
5702 ready = false;
5703
5704 normal_timer_service:
5705 #endif
5706 /* Reset the timer */
5707 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5708
5709 if (ready)
5710 ixgbe_service_event_schedule(adapter);
5711 }
5712
5713 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5714 {
5715 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5716 return;
5717
5718 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5719
5720 /* If we're already down or resetting, just bail */
5721 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5722 test_bit(__IXGBE_RESETTING, &adapter->state))
5723 return;
5724
5725 ixgbe_dump(adapter);
5726 netdev_err(adapter->netdev, "Reset adapter\n");
5727 adapter->tx_timeout_count++;
5728
5729 ixgbe_reinit_locked(adapter);
5730 }
5731
5732 /**
5733 * ixgbe_service_task - manages and runs subtasks
5734 * @work: pointer to work_struct containing our data
5735 **/
5736 static void ixgbe_service_task(struct work_struct *work)
5737 {
5738 struct ixgbe_adapter *adapter = container_of(work,
5739 struct ixgbe_adapter,
5740 service_task);
5741
5742 ixgbe_reset_subtask(adapter);
5743 ixgbe_sfp_detection_subtask(adapter);
5744 ixgbe_sfp_link_config_subtask(adapter);
5745 ixgbe_check_overtemp_subtask(adapter);
5746 ixgbe_watchdog_subtask(adapter);
5747 ixgbe_fdir_reinit_subtask(adapter);
5748 ixgbe_check_hang_subtask(adapter);
5749 #ifdef CONFIG_IXGBE_PTP
5750 ixgbe_ptp_overflow_check(adapter);
5751 #endif
5752
5753 ixgbe_service_event_complete(adapter);
5754 }
5755
5756 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5757 struct ixgbe_tx_buffer *first,
5758 u8 *hdr_len)
5759 {
5760 struct sk_buff *skb = first->skb;
5761 u32 vlan_macip_lens, type_tucmd;
5762 u32 mss_l4len_idx, l4len;
5763
5764 if (!skb_is_gso(skb))
5765 return 0;
5766
5767 if (skb_header_cloned(skb)) {
5768 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5769 if (err)
5770 return err;
5771 }
5772
5773 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5774 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5775
5776 if (first->protocol == __constant_htons(ETH_P_IP)) {
5777 struct iphdr *iph = ip_hdr(skb);
5778 iph->tot_len = 0;
5779 iph->check = 0;
5780 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5781 iph->daddr, 0,
5782 IPPROTO_TCP,
5783 0);
5784 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5785 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5786 IXGBE_TX_FLAGS_CSUM |
5787 IXGBE_TX_FLAGS_IPV4;
5788 } else if (skb_is_gso_v6(skb)) {
5789 ipv6_hdr(skb)->payload_len = 0;
5790 tcp_hdr(skb)->check =
5791 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5792 &ipv6_hdr(skb)->daddr,
5793 0, IPPROTO_TCP, 0);
5794 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5795 IXGBE_TX_FLAGS_CSUM;
5796 }
5797
5798 /* compute header lengths */
5799 l4len = tcp_hdrlen(skb);
5800 *hdr_len = skb_transport_offset(skb) + l4len;
5801
5802 /* update gso size and bytecount with header size */
5803 first->gso_segs = skb_shinfo(skb)->gso_segs;
5804 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5805
5806 /* mss_l4len_id: use 1 as index for TSO */
5807 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5808 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5809 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5810
5811 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5812 vlan_macip_lens = skb_network_header_len(skb);
5813 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5814 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5815
5816 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5817 mss_l4len_idx);
5818
5819 return 1;
5820 }
5821
5822 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5823 struct ixgbe_tx_buffer *first)
5824 {
5825 struct sk_buff *skb = first->skb;
5826 u32 vlan_macip_lens = 0;
5827 u32 mss_l4len_idx = 0;
5828 u32 type_tucmd = 0;
5829
5830 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5831 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5832 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5833 return;
5834 } else {
5835 u8 l4_hdr = 0;
5836 switch (first->protocol) {
5837 case __constant_htons(ETH_P_IP):
5838 vlan_macip_lens |= skb_network_header_len(skb);
5839 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5840 l4_hdr = ip_hdr(skb)->protocol;
5841 break;
5842 case __constant_htons(ETH_P_IPV6):
5843 vlan_macip_lens |= skb_network_header_len(skb);
5844 l4_hdr = ipv6_hdr(skb)->nexthdr;
5845 break;
5846 default:
5847 if (unlikely(net_ratelimit())) {
5848 dev_warn(tx_ring->dev,
5849 "partial checksum but proto=%x!\n",
5850 first->protocol);
5851 }
5852 break;
5853 }
5854
5855 switch (l4_hdr) {
5856 case IPPROTO_TCP:
5857 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5858 mss_l4len_idx = tcp_hdrlen(skb) <<
5859 IXGBE_ADVTXD_L4LEN_SHIFT;
5860 break;
5861 case IPPROTO_SCTP:
5862 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5863 mss_l4len_idx = sizeof(struct sctphdr) <<
5864 IXGBE_ADVTXD_L4LEN_SHIFT;
5865 break;
5866 case IPPROTO_UDP:
5867 mss_l4len_idx = sizeof(struct udphdr) <<
5868 IXGBE_ADVTXD_L4LEN_SHIFT;
5869 break;
5870 default:
5871 if (unlikely(net_ratelimit())) {
5872 dev_warn(tx_ring->dev,
5873 "partial checksum but l4 proto=%x!\n",
5874 l4_hdr);
5875 }
5876 break;
5877 }
5878
5879 /* update TX checksum flag */
5880 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5881 }
5882
5883 /* vlan_macip_lens: MACLEN, VLAN tag */
5884 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5885 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5886
5887 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5888 type_tucmd, mss_l4len_idx);
5889 }
5890
5891 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5892 {
5893 /* set type for advanced descriptor with frame checksum insertion */
5894 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5895 IXGBE_ADVTXD_DCMD_IFCS |
5896 IXGBE_ADVTXD_DCMD_DEXT);
5897
5898 /* set HW vlan bit if vlan is present */
5899 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5900 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5901
5902 #ifdef CONFIG_IXGBE_PTP
5903 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5904 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5905 #endif
5906
5907 /* set segmentation enable bits for TSO/FSO */
5908 #ifdef IXGBE_FCOE
5909 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5910 #else
5911 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5912 #endif
5913 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5914
5915 return cmd_type;
5916 }
5917
5918 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5919 u32 tx_flags, unsigned int paylen)
5920 {
5921 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5922
5923 /* enable L4 checksum for TSO and TX checksum offload */
5924 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5925 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5926
5927 /* enble IPv4 checksum for TSO */
5928 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5929 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5930
5931 /* use index 1 context for TSO/FSO/FCOE */
5932 #ifdef IXGBE_FCOE
5933 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5934 #else
5935 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5936 #endif
5937 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5938
5939 /*
5940 * Check Context must be set if Tx switch is enabled, which it
5941 * always is for case where virtual functions are running
5942 */
5943 #ifdef IXGBE_FCOE
5944 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5945 #else
5946 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5947 #endif
5948 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5949
5950 tx_desc->read.olinfo_status = olinfo_status;
5951 }
5952
5953 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5954 IXGBE_TXD_CMD_RS)
5955
5956 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5957 struct ixgbe_tx_buffer *first,
5958 const u8 hdr_len)
5959 {
5960 dma_addr_t dma;
5961 struct sk_buff *skb = first->skb;
5962 struct ixgbe_tx_buffer *tx_buffer;
5963 union ixgbe_adv_tx_desc *tx_desc;
5964 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5965 unsigned int data_len = skb->data_len;
5966 unsigned int size = skb_headlen(skb);
5967 unsigned int paylen = skb->len - hdr_len;
5968 u32 tx_flags = first->tx_flags;
5969 __le32 cmd_type;
5970 u16 i = tx_ring->next_to_use;
5971
5972 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5973
5974 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5975 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5976
5977 #ifdef IXGBE_FCOE
5978 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5979 if (data_len < sizeof(struct fcoe_crc_eof)) {
5980 size -= sizeof(struct fcoe_crc_eof) - data_len;
5981 data_len = 0;
5982 } else {
5983 data_len -= sizeof(struct fcoe_crc_eof);
5984 }
5985 }
5986
5987 #endif
5988 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5989 if (dma_mapping_error(tx_ring->dev, dma))
5990 goto dma_error;
5991
5992 /* record length, and DMA address */
5993 dma_unmap_len_set(first, len, size);
5994 dma_unmap_addr_set(first, dma, dma);
5995
5996 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5997
5998 for (;;) {
5999 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6000 tx_desc->read.cmd_type_len =
6001 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6002
6003 i++;
6004 tx_desc++;
6005 if (i == tx_ring->count) {
6006 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6007 i = 0;
6008 }
6009
6010 dma += IXGBE_MAX_DATA_PER_TXD;
6011 size -= IXGBE_MAX_DATA_PER_TXD;
6012
6013 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6014 tx_desc->read.olinfo_status = 0;
6015 }
6016
6017 if (likely(!data_len))
6018 break;
6019
6020 if (unlikely(skb->no_fcs))
6021 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
6022 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6023
6024 i++;
6025 tx_desc++;
6026 if (i == tx_ring->count) {
6027 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6028 i = 0;
6029 }
6030
6031 #ifdef IXGBE_FCOE
6032 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6033 #else
6034 size = skb_frag_size(frag);
6035 #endif
6036 data_len -= size;
6037
6038 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6039 DMA_TO_DEVICE);
6040 if (dma_mapping_error(tx_ring->dev, dma))
6041 goto dma_error;
6042
6043 tx_buffer = &tx_ring->tx_buffer_info[i];
6044 dma_unmap_len_set(tx_buffer, len, size);
6045 dma_unmap_addr_set(tx_buffer, dma, dma);
6046
6047 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6048 tx_desc->read.olinfo_status = 0;
6049
6050 frag++;
6051 }
6052
6053 /* write last descriptor with RS and EOP bits */
6054 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6055 tx_desc->read.cmd_type_len = cmd_type;
6056
6057 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6058
6059 /* set the timestamp */
6060 first->time_stamp = jiffies;
6061
6062 /*
6063 * Force memory writes to complete before letting h/w know there
6064 * are new descriptors to fetch. (Only applicable for weak-ordered
6065 * memory model archs, such as IA-64).
6066 *
6067 * We also need this memory barrier to make certain all of the
6068 * status bits have been updated before next_to_watch is written.
6069 */
6070 wmb();
6071
6072 /* set next_to_watch value indicating a packet is present */
6073 first->next_to_watch = tx_desc;
6074
6075 i++;
6076 if (i == tx_ring->count)
6077 i = 0;
6078
6079 tx_ring->next_to_use = i;
6080
6081 /* notify HW of packet */
6082 writel(i, tx_ring->tail);
6083
6084 return;
6085 dma_error:
6086 dev_err(tx_ring->dev, "TX DMA map failed\n");
6087
6088 /* clear dma mappings for failed tx_buffer_info map */
6089 for (;;) {
6090 tx_buffer = &tx_ring->tx_buffer_info[i];
6091 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6092 if (tx_buffer == first)
6093 break;
6094 if (i == 0)
6095 i = tx_ring->count;
6096 i--;
6097 }
6098
6099 tx_ring->next_to_use = i;
6100 }
6101
6102 static void ixgbe_atr(struct ixgbe_ring *ring,
6103 struct ixgbe_tx_buffer *first)
6104 {
6105 struct ixgbe_q_vector *q_vector = ring->q_vector;
6106 union ixgbe_atr_hash_dword input = { .dword = 0 };
6107 union ixgbe_atr_hash_dword common = { .dword = 0 };
6108 union {
6109 unsigned char *network;
6110 struct iphdr *ipv4;
6111 struct ipv6hdr *ipv6;
6112 } hdr;
6113 struct tcphdr *th;
6114 __be16 vlan_id;
6115
6116 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6117 if (!q_vector)
6118 return;
6119
6120 /* do nothing if sampling is disabled */
6121 if (!ring->atr_sample_rate)
6122 return;
6123
6124 ring->atr_count++;
6125
6126 /* snag network header to get L4 type and address */
6127 hdr.network = skb_network_header(first->skb);
6128
6129 /* Currently only IPv4/IPv6 with TCP is supported */
6130 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6131 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6132 (first->protocol != __constant_htons(ETH_P_IP) ||
6133 hdr.ipv4->protocol != IPPROTO_TCP))
6134 return;
6135
6136 th = tcp_hdr(first->skb);
6137
6138 /* skip this packet since it is invalid or the socket is closing */
6139 if (!th || th->fin)
6140 return;
6141
6142 /* sample on all syn packets or once every atr sample count */
6143 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6144 return;
6145
6146 /* reset sample count */
6147 ring->atr_count = 0;
6148
6149 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6150
6151 /*
6152 * src and dst are inverted, think how the receiver sees them
6153 *
6154 * The input is broken into two sections, a non-compressed section
6155 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6156 * is XORed together and stored in the compressed dword.
6157 */
6158 input.formatted.vlan_id = vlan_id;
6159
6160 /*
6161 * since src port and flex bytes occupy the same word XOR them together
6162 * and write the value to source port portion of compressed dword
6163 */
6164 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6165 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6166 else
6167 common.port.src ^= th->dest ^ first->protocol;
6168 common.port.dst ^= th->source;
6169
6170 if (first->protocol == __constant_htons(ETH_P_IP)) {
6171 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6172 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6173 } else {
6174 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6175 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6176 hdr.ipv6->saddr.s6_addr32[1] ^
6177 hdr.ipv6->saddr.s6_addr32[2] ^
6178 hdr.ipv6->saddr.s6_addr32[3] ^
6179 hdr.ipv6->daddr.s6_addr32[0] ^
6180 hdr.ipv6->daddr.s6_addr32[1] ^
6181 hdr.ipv6->daddr.s6_addr32[2] ^
6182 hdr.ipv6->daddr.s6_addr32[3];
6183 }
6184
6185 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6186 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6187 input, common, ring->queue_index);
6188 }
6189
6190 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6191 {
6192 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6193 /* Herbert's original patch had:
6194 * smp_mb__after_netif_stop_queue();
6195 * but since that doesn't exist yet, just open code it. */
6196 smp_mb();
6197
6198 /* We need to check again in a case another CPU has just
6199 * made room available. */
6200 if (likely(ixgbe_desc_unused(tx_ring) < size))
6201 return -EBUSY;
6202
6203 /* A reprieve! - use start_queue because it doesn't call schedule */
6204 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6205 ++tx_ring->tx_stats.restart_queue;
6206 return 0;
6207 }
6208
6209 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6210 {
6211 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6212 return 0;
6213 return __ixgbe_maybe_stop_tx(tx_ring, size);
6214 }
6215
6216 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6217 {
6218 struct ixgbe_adapter *adapter = netdev_priv(dev);
6219 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6220 smp_processor_id();
6221 #ifdef IXGBE_FCOE
6222 __be16 protocol = vlan_get_protocol(skb);
6223
6224 if (((protocol == htons(ETH_P_FCOE)) ||
6225 (protocol == htons(ETH_P_FIP))) &&
6226 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6227 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6228 txq += adapter->ring_feature[RING_F_FCOE].mask;
6229 return txq;
6230 }
6231 #endif
6232
6233 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6234 while (unlikely(txq >= dev->real_num_tx_queues))
6235 txq -= dev->real_num_tx_queues;
6236 return txq;
6237 }
6238
6239 return skb_tx_hash(dev, skb);
6240 }
6241
6242 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6243 struct ixgbe_adapter *adapter,
6244 struct ixgbe_ring *tx_ring)
6245 {
6246 struct ixgbe_tx_buffer *first;
6247 int tso;
6248 u32 tx_flags = 0;
6249 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6250 unsigned short f;
6251 #endif
6252 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6253 __be16 protocol = skb->protocol;
6254 u8 hdr_len = 0;
6255
6256 /*
6257 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6258 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6259 * + 2 desc gap to keep tail from touching head,
6260 * + 1 desc for context descriptor,
6261 * otherwise try next time
6262 */
6263 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6264 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6265 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6266 #else
6267 count += skb_shinfo(skb)->nr_frags;
6268 #endif
6269 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6270 tx_ring->tx_stats.tx_busy++;
6271 return NETDEV_TX_BUSY;
6272 }
6273
6274 /* record the location of the first descriptor for this packet */
6275 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6276 first->skb = skb;
6277 first->bytecount = skb->len;
6278 first->gso_segs = 1;
6279
6280 /* if we have a HW VLAN tag being added default to the HW one */
6281 if (vlan_tx_tag_present(skb)) {
6282 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6283 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6284 /* else if it is a SW VLAN check the next protocol and store the tag */
6285 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6286 struct vlan_hdr *vhdr, _vhdr;
6287 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6288 if (!vhdr)
6289 goto out_drop;
6290
6291 protocol = vhdr->h_vlan_encapsulated_proto;
6292 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6293 IXGBE_TX_FLAGS_VLAN_SHIFT;
6294 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6295 }
6296
6297 skb_tx_timestamp(skb);
6298
6299 #ifdef CONFIG_IXGBE_PTP
6300 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6301 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6302 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6303 }
6304 #endif
6305
6306 #ifdef CONFIG_PCI_IOV
6307 /*
6308 * Use the l2switch_enable flag - would be false if the DMA
6309 * Tx switch had been disabled.
6310 */
6311 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6312 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6313
6314 #endif
6315 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6316 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6317 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6318 (skb->priority != TC_PRIO_CONTROL))) {
6319 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6320 tx_flags |= (skb->priority & 0x7) <<
6321 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6322 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6323 struct vlan_ethhdr *vhdr;
6324 if (skb_header_cloned(skb) &&
6325 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6326 goto out_drop;
6327 vhdr = (struct vlan_ethhdr *)skb->data;
6328 vhdr->h_vlan_TCI = htons(tx_flags >>
6329 IXGBE_TX_FLAGS_VLAN_SHIFT);
6330 } else {
6331 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6332 }
6333 }
6334
6335 /* record initial flags and protocol */
6336 first->tx_flags = tx_flags;
6337 first->protocol = protocol;
6338
6339 #ifdef IXGBE_FCOE
6340 /* setup tx offload for FCoE */
6341 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6342 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6343 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6344 if (tso < 0)
6345 goto out_drop;
6346
6347 goto xmit_fcoe;
6348 }
6349
6350 #endif /* IXGBE_FCOE */
6351 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6352 if (tso < 0)
6353 goto out_drop;
6354 else if (!tso)
6355 ixgbe_tx_csum(tx_ring, first);
6356
6357 /* add the ATR filter if ATR is on */
6358 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6359 ixgbe_atr(tx_ring, first);
6360
6361 #ifdef IXGBE_FCOE
6362 xmit_fcoe:
6363 #endif /* IXGBE_FCOE */
6364 ixgbe_tx_map(tx_ring, first, hdr_len);
6365
6366 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6367
6368 return NETDEV_TX_OK;
6369
6370 out_drop:
6371 dev_kfree_skb_any(first->skb);
6372 first->skb = NULL;
6373
6374 return NETDEV_TX_OK;
6375 }
6376
6377 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6378 struct net_device *netdev)
6379 {
6380 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6381 struct ixgbe_ring *tx_ring;
6382
6383 /*
6384 * The minimum packet size for olinfo paylen is 17 so pad the skb
6385 * in order to meet this minimum size requirement.
6386 */
6387 if (unlikely(skb->len < 17)) {
6388 if (skb_pad(skb, 17 - skb->len))
6389 return NETDEV_TX_OK;
6390 skb->len = 17;
6391 }
6392
6393 tx_ring = adapter->tx_ring[skb->queue_mapping];
6394 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6395 }
6396
6397 /**
6398 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6399 * @netdev: network interface device structure
6400 * @p: pointer to an address structure
6401 *
6402 * Returns 0 on success, negative on failure
6403 **/
6404 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6405 {
6406 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6407 struct ixgbe_hw *hw = &adapter->hw;
6408 struct sockaddr *addr = p;
6409
6410 if (!is_valid_ether_addr(addr->sa_data))
6411 return -EADDRNOTAVAIL;
6412
6413 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6414 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6415
6416 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6417 IXGBE_RAH_AV);
6418
6419 return 0;
6420 }
6421
6422 static int
6423 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6424 {
6425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6426 struct ixgbe_hw *hw = &adapter->hw;
6427 u16 value;
6428 int rc;
6429
6430 if (prtad != hw->phy.mdio.prtad)
6431 return -EINVAL;
6432 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6433 if (!rc)
6434 rc = value;
6435 return rc;
6436 }
6437
6438 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6439 u16 addr, u16 value)
6440 {
6441 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6442 struct ixgbe_hw *hw = &adapter->hw;
6443
6444 if (prtad != hw->phy.mdio.prtad)
6445 return -EINVAL;
6446 return hw->phy.ops.write_reg(hw, addr, devad, value);
6447 }
6448
6449 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6450 {
6451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6452
6453 switch (cmd) {
6454 #ifdef CONFIG_IXGBE_PTP
6455 case SIOCSHWTSTAMP:
6456 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6457 #endif
6458 default:
6459 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6460 }
6461 }
6462
6463 /**
6464 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6465 * netdev->dev_addrs
6466 * @netdev: network interface device structure
6467 *
6468 * Returns non-zero on failure
6469 **/
6470 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6471 {
6472 int err = 0;
6473 struct ixgbe_adapter *adapter = netdev_priv(dev);
6474 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6475
6476 if (is_valid_ether_addr(mac->san_addr)) {
6477 rtnl_lock();
6478 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6479 rtnl_unlock();
6480 }
6481 return err;
6482 }
6483
6484 /**
6485 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6486 * netdev->dev_addrs
6487 * @netdev: network interface device structure
6488 *
6489 * Returns non-zero on failure
6490 **/
6491 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6492 {
6493 int err = 0;
6494 struct ixgbe_adapter *adapter = netdev_priv(dev);
6495 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6496
6497 if (is_valid_ether_addr(mac->san_addr)) {
6498 rtnl_lock();
6499 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6500 rtnl_unlock();
6501 }
6502 return err;
6503 }
6504
6505 #ifdef CONFIG_NET_POLL_CONTROLLER
6506 /*
6507 * Polling 'interrupt' - used by things like netconsole to send skbs
6508 * without having to re-enable interrupts. It's not called while
6509 * the interrupt routine is executing.
6510 */
6511 static void ixgbe_netpoll(struct net_device *netdev)
6512 {
6513 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6514 int i;
6515
6516 /* if interface is down do nothing */
6517 if (test_bit(__IXGBE_DOWN, &adapter->state))
6518 return;
6519
6520 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6521 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6522 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6523 for (i = 0; i < num_q_vectors; i++) {
6524 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6525 ixgbe_msix_clean_rings(0, q_vector);
6526 }
6527 } else {
6528 ixgbe_intr(adapter->pdev->irq, netdev);
6529 }
6530 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6531 }
6532
6533 #endif
6534 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6535 struct rtnl_link_stats64 *stats)
6536 {
6537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6538 int i;
6539
6540 rcu_read_lock();
6541 for (i = 0; i < adapter->num_rx_queues; i++) {
6542 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6543 u64 bytes, packets;
6544 unsigned int start;
6545
6546 if (ring) {
6547 do {
6548 start = u64_stats_fetch_begin_bh(&ring->syncp);
6549 packets = ring->stats.packets;
6550 bytes = ring->stats.bytes;
6551 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6552 stats->rx_packets += packets;
6553 stats->rx_bytes += bytes;
6554 }
6555 }
6556
6557 for (i = 0; i < adapter->num_tx_queues; i++) {
6558 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6559 u64 bytes, packets;
6560 unsigned int start;
6561
6562 if (ring) {
6563 do {
6564 start = u64_stats_fetch_begin_bh(&ring->syncp);
6565 packets = ring->stats.packets;
6566 bytes = ring->stats.bytes;
6567 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6568 stats->tx_packets += packets;
6569 stats->tx_bytes += bytes;
6570 }
6571 }
6572 rcu_read_unlock();
6573 /* following stats updated by ixgbe_watchdog_task() */
6574 stats->multicast = netdev->stats.multicast;
6575 stats->rx_errors = netdev->stats.rx_errors;
6576 stats->rx_length_errors = netdev->stats.rx_length_errors;
6577 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6578 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6579 return stats;
6580 }
6581
6582 #ifdef CONFIG_IXGBE_DCB
6583 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6584 * #adapter: pointer to ixgbe_adapter
6585 * @tc: number of traffic classes currently enabled
6586 *
6587 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6588 * 802.1Q priority maps to a packet buffer that exists.
6589 */
6590 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6591 {
6592 struct ixgbe_hw *hw = &adapter->hw;
6593 u32 reg, rsave;
6594 int i;
6595
6596 /* 82598 have a static priority to TC mapping that can not
6597 * be changed so no validation is needed.
6598 */
6599 if (hw->mac.type == ixgbe_mac_82598EB)
6600 return;
6601
6602 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6603 rsave = reg;
6604
6605 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6606 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6607
6608 /* If up2tc is out of bounds default to zero */
6609 if (up2tc > tc)
6610 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6611 }
6612
6613 if (reg != rsave)
6614 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6615
6616 return;
6617 }
6618
6619 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6620 * classes.
6621 *
6622 * @netdev: net device to configure
6623 * @tc: number of traffic classes to enable
6624 */
6625 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6626 {
6627 struct ixgbe_adapter *adapter = netdev_priv(dev);
6628 struct ixgbe_hw *hw = &adapter->hw;
6629
6630 /* Multiple traffic classes requires multiple queues */
6631 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6632 e_err(drv, "Enable failed, needs MSI-X\n");
6633 return -EINVAL;
6634 }
6635
6636 /* Hardware supports up to 8 traffic classes */
6637 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6638 (hw->mac.type == ixgbe_mac_82598EB &&
6639 tc < MAX_TRAFFIC_CLASS))
6640 return -EINVAL;
6641
6642 /* Hardware has to reinitialize queues and interrupts to
6643 * match packet buffer alignment. Unfortunately, the
6644 * hardware is not flexible enough to do this dynamically.
6645 */
6646 if (netif_running(dev))
6647 ixgbe_close(dev);
6648 ixgbe_clear_interrupt_scheme(adapter);
6649
6650 if (tc) {
6651 netdev_set_num_tc(dev, tc);
6652 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6653 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6654
6655 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6656 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6657 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6658 }
6659 } else {
6660 netdev_reset_tc(dev);
6661 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6662 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6663
6664 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6665 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6666
6667 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6668 adapter->dcb_cfg.pfc_mode_enable = false;
6669 }
6670
6671 ixgbe_init_interrupt_scheme(adapter);
6672 ixgbe_validate_rtr(adapter, tc);
6673 if (netif_running(dev))
6674 ixgbe_open(dev);
6675
6676 return 0;
6677 }
6678
6679 #endif /* CONFIG_IXGBE_DCB */
6680 void ixgbe_do_reset(struct net_device *netdev)
6681 {
6682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6683
6684 if (netif_running(netdev))
6685 ixgbe_reinit_locked(adapter);
6686 else
6687 ixgbe_reset(adapter);
6688 }
6689
6690 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6691 netdev_features_t features)
6692 {
6693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6694
6695 /* return error if RXHASH is being enabled when RSS is not supported */
6696 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6697 features &= ~NETIF_F_RXHASH;
6698
6699 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6700 if (!(features & NETIF_F_RXCSUM))
6701 features &= ~NETIF_F_LRO;
6702
6703 /* Turn off LRO if not RSC capable */
6704 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6705 features &= ~NETIF_F_LRO;
6706
6707 return features;
6708 }
6709
6710 static int ixgbe_set_features(struct net_device *netdev,
6711 netdev_features_t features)
6712 {
6713 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6714 netdev_features_t changed = netdev->features ^ features;
6715 bool need_reset = false;
6716
6717 /* Make sure RSC matches LRO, reset if change */
6718 if (!(features & NETIF_F_LRO)) {
6719 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6720 need_reset = true;
6721 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6722 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6723 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6724 if (adapter->rx_itr_setting == 1 ||
6725 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6726 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6727 need_reset = true;
6728 } else if ((changed ^ features) & NETIF_F_LRO) {
6729 e_info(probe, "rx-usecs set too low, "
6730 "disabling RSC\n");
6731 }
6732 }
6733
6734 /*
6735 * Check if Flow Director n-tuple support was enabled or disabled. If
6736 * the state changed, we need to reset.
6737 */
6738 if (!(features & NETIF_F_NTUPLE)) {
6739 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6740 /* turn off Flow Director, set ATR and reset */
6741 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6742 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6743 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6744 need_reset = true;
6745 }
6746 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6747 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6748 /* turn off ATR, enable perfect filters and reset */
6749 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6750 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6751 need_reset = true;
6752 }
6753
6754 if (features & NETIF_F_HW_VLAN_RX)
6755 ixgbe_vlan_strip_enable(adapter);
6756 else
6757 ixgbe_vlan_strip_disable(adapter);
6758
6759 if (changed & NETIF_F_RXALL)
6760 need_reset = true;
6761
6762 netdev->features = features;
6763 if (need_reset)
6764 ixgbe_do_reset(netdev);
6765
6766 return 0;
6767 }
6768
6769 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6770 struct net_device *dev,
6771 unsigned char *addr,
6772 u16 flags)
6773 {
6774 struct ixgbe_adapter *adapter = netdev_priv(dev);
6775 int err = -EOPNOTSUPP;
6776
6777 if (ndm->ndm_state & NUD_PERMANENT) {
6778 pr_info("%s: FDB only supports static addresses\n",
6779 ixgbe_driver_name);
6780 return -EINVAL;
6781 }
6782
6783 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6784 if (is_unicast_ether_addr(addr))
6785 err = dev_uc_add_excl(dev, addr);
6786 else if (is_multicast_ether_addr(addr))
6787 err = dev_mc_add_excl(dev, addr);
6788 else
6789 err = -EINVAL;
6790 }
6791
6792 /* Only return duplicate errors if NLM_F_EXCL is set */
6793 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6794 err = 0;
6795
6796 return err;
6797 }
6798
6799 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6800 struct net_device *dev,
6801 unsigned char *addr)
6802 {
6803 struct ixgbe_adapter *adapter = netdev_priv(dev);
6804 int err = -EOPNOTSUPP;
6805
6806 if (ndm->ndm_state & NUD_PERMANENT) {
6807 pr_info("%s: FDB only supports static addresses\n",
6808 ixgbe_driver_name);
6809 return -EINVAL;
6810 }
6811
6812 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6813 if (is_unicast_ether_addr(addr))
6814 err = dev_uc_del(dev, addr);
6815 else if (is_multicast_ether_addr(addr))
6816 err = dev_mc_del(dev, addr);
6817 else
6818 err = -EINVAL;
6819 }
6820
6821 return err;
6822 }
6823
6824 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6825 struct netlink_callback *cb,
6826 struct net_device *dev,
6827 int idx)
6828 {
6829 struct ixgbe_adapter *adapter = netdev_priv(dev);
6830
6831 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6832 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6833
6834 return idx;
6835 }
6836
6837 static const struct net_device_ops ixgbe_netdev_ops = {
6838 .ndo_open = ixgbe_open,
6839 .ndo_stop = ixgbe_close,
6840 .ndo_start_xmit = ixgbe_xmit_frame,
6841 .ndo_select_queue = ixgbe_select_queue,
6842 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6843 .ndo_validate_addr = eth_validate_addr,
6844 .ndo_set_mac_address = ixgbe_set_mac,
6845 .ndo_change_mtu = ixgbe_change_mtu,
6846 .ndo_tx_timeout = ixgbe_tx_timeout,
6847 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6848 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6849 .ndo_do_ioctl = ixgbe_ioctl,
6850 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6851 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6852 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6853 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6854 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6855 .ndo_get_stats64 = ixgbe_get_stats64,
6856 #ifdef CONFIG_IXGBE_DCB
6857 .ndo_setup_tc = ixgbe_setup_tc,
6858 #endif
6859 #ifdef CONFIG_NET_POLL_CONTROLLER
6860 .ndo_poll_controller = ixgbe_netpoll,
6861 #endif
6862 #ifdef IXGBE_FCOE
6863 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6864 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6865 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6866 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6867 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6868 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6869 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6870 #endif /* IXGBE_FCOE */
6871 .ndo_set_features = ixgbe_set_features,
6872 .ndo_fix_features = ixgbe_fix_features,
6873 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6874 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6875 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
6876 };
6877
6878 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6879 const struct ixgbe_info *ii)
6880 {
6881 #ifdef CONFIG_PCI_IOV
6882 struct ixgbe_hw *hw = &adapter->hw;
6883
6884 if (hw->mac.type == ixgbe_mac_82598EB)
6885 return;
6886
6887 /* The 82599 supports up to 64 VFs per physical function
6888 * but this implementation limits allocation to 63 so that
6889 * basic networking resources are still available to the
6890 * physical function. If the user requests greater thn
6891 * 63 VFs then it is an error - reset to default of zero.
6892 */
6893 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
6894 ixgbe_enable_sriov(adapter, ii);
6895 #endif /* CONFIG_PCI_IOV */
6896 }
6897
6898 /**
6899 * ixgbe_wol_supported - Check whether device supports WoL
6900 * @hw: hw specific details
6901 * @device_id: the device ID
6902 * @subdev_id: the subsystem device ID
6903 *
6904 * This function is used by probe and ethtool to determine
6905 * which devices have WoL support
6906 *
6907 **/
6908 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6909 u16 subdevice_id)
6910 {
6911 struct ixgbe_hw *hw = &adapter->hw;
6912 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6913 int is_wol_supported = 0;
6914
6915 switch (device_id) {
6916 case IXGBE_DEV_ID_82599_SFP:
6917 /* Only these subdevices could supports WOL */
6918 switch (subdevice_id) {
6919 case IXGBE_SUBDEV_ID_82599_560FLR:
6920 /* only support first port */
6921 if (hw->bus.func != 0)
6922 break;
6923 case IXGBE_SUBDEV_ID_82599_SFP:
6924 is_wol_supported = 1;
6925 break;
6926 }
6927 break;
6928 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6929 /* All except this subdevice support WOL */
6930 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6931 is_wol_supported = 1;
6932 break;
6933 case IXGBE_DEV_ID_82599_KX4:
6934 is_wol_supported = 1;
6935 break;
6936 case IXGBE_DEV_ID_X540T:
6937 /* check eeprom to see if enabled wol */
6938 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6939 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6940 (hw->bus.func == 0))) {
6941 is_wol_supported = 1;
6942 }
6943 break;
6944 }
6945
6946 return is_wol_supported;
6947 }
6948
6949 /**
6950 * ixgbe_probe - Device Initialization Routine
6951 * @pdev: PCI device information struct
6952 * @ent: entry in ixgbe_pci_tbl
6953 *
6954 * Returns 0 on success, negative on failure
6955 *
6956 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6957 * The OS initialization, configuring of the adapter private structure,
6958 * and a hardware reset occur.
6959 **/
6960 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6961 const struct pci_device_id *ent)
6962 {
6963 struct net_device *netdev;
6964 struct ixgbe_adapter *adapter = NULL;
6965 struct ixgbe_hw *hw;
6966 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6967 static int cards_found;
6968 int i, err, pci_using_dac;
6969 u8 part_str[IXGBE_PBANUM_LENGTH];
6970 unsigned int indices = num_possible_cpus();
6971 #ifdef IXGBE_FCOE
6972 u16 device_caps;
6973 #endif
6974 u32 eec;
6975
6976 /* Catch broken hardware that put the wrong VF device ID in
6977 * the PCIe SR-IOV capability.
6978 */
6979 if (pdev->is_virtfn) {
6980 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6981 pci_name(pdev), pdev->vendor, pdev->device);
6982 return -EINVAL;
6983 }
6984
6985 err = pci_enable_device_mem(pdev);
6986 if (err)
6987 return err;
6988
6989 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6990 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6991 pci_using_dac = 1;
6992 } else {
6993 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6994 if (err) {
6995 err = dma_set_coherent_mask(&pdev->dev,
6996 DMA_BIT_MASK(32));
6997 if (err) {
6998 dev_err(&pdev->dev,
6999 "No usable DMA configuration, aborting\n");
7000 goto err_dma;
7001 }
7002 }
7003 pci_using_dac = 0;
7004 }
7005
7006 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7007 IORESOURCE_MEM), ixgbe_driver_name);
7008 if (err) {
7009 dev_err(&pdev->dev,
7010 "pci_request_selected_regions failed 0x%x\n", err);
7011 goto err_pci_reg;
7012 }
7013
7014 pci_enable_pcie_error_reporting(pdev);
7015
7016 pci_set_master(pdev);
7017 pci_save_state(pdev);
7018
7019 #ifdef CONFIG_IXGBE_DCB
7020 indices *= MAX_TRAFFIC_CLASS;
7021 #endif
7022
7023 if (ii->mac == ixgbe_mac_82598EB)
7024 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7025 else
7026 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7027
7028 #ifdef IXGBE_FCOE
7029 indices += min_t(unsigned int, num_possible_cpus(),
7030 IXGBE_MAX_FCOE_INDICES);
7031 #endif
7032 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7033 if (!netdev) {
7034 err = -ENOMEM;
7035 goto err_alloc_etherdev;
7036 }
7037
7038 SET_NETDEV_DEV(netdev, &pdev->dev);
7039
7040 adapter = netdev_priv(netdev);
7041 pci_set_drvdata(pdev, adapter);
7042
7043 adapter->netdev = netdev;
7044 adapter->pdev = pdev;
7045 hw = &adapter->hw;
7046 hw->back = adapter;
7047 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7048
7049 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7050 pci_resource_len(pdev, 0));
7051 if (!hw->hw_addr) {
7052 err = -EIO;
7053 goto err_ioremap;
7054 }
7055
7056 for (i = 1; i <= 5; i++) {
7057 if (pci_resource_len(pdev, i) == 0)
7058 continue;
7059 }
7060
7061 netdev->netdev_ops = &ixgbe_netdev_ops;
7062 ixgbe_set_ethtool_ops(netdev);
7063 netdev->watchdog_timeo = 5 * HZ;
7064 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7065
7066 adapter->bd_number = cards_found;
7067
7068 /* Setup hw api */
7069 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7070 hw->mac.type = ii->mac;
7071
7072 /* EEPROM */
7073 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7074 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7075 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7076 if (!(eec & (1 << 8)))
7077 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7078
7079 /* PHY */
7080 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7081 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7082 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7083 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7084 hw->phy.mdio.mmds = 0;
7085 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7086 hw->phy.mdio.dev = netdev;
7087 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7088 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7089
7090 ii->get_invariants(hw);
7091
7092 /* setup the private structure */
7093 err = ixgbe_sw_init(adapter);
7094 if (err)
7095 goto err_sw_init;
7096
7097 /* Make it possible the adapter to be woken up via WOL */
7098 switch (adapter->hw.mac.type) {
7099 case ixgbe_mac_82599EB:
7100 case ixgbe_mac_X540:
7101 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7102 break;
7103 default:
7104 break;
7105 }
7106
7107 /*
7108 * If there is a fan on this device and it has failed log the
7109 * failure.
7110 */
7111 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7112 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7113 if (esdp & IXGBE_ESDP_SDP1)
7114 e_crit(probe, "Fan has stopped, replace the adapter\n");
7115 }
7116
7117 if (allow_unsupported_sfp)
7118 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7119
7120 /* reset_hw fills in the perm_addr as well */
7121 hw->phy.reset_if_overtemp = true;
7122 err = hw->mac.ops.reset_hw(hw);
7123 hw->phy.reset_if_overtemp = false;
7124 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7125 hw->mac.type == ixgbe_mac_82598EB) {
7126 err = 0;
7127 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7128 e_dev_err("failed to load because an unsupported SFP+ "
7129 "module type was detected.\n");
7130 e_dev_err("Reload the driver after installing a supported "
7131 "module.\n");
7132 goto err_sw_init;
7133 } else if (err) {
7134 e_dev_err("HW Init failed: %d\n", err);
7135 goto err_sw_init;
7136 }
7137
7138 ixgbe_probe_vf(adapter, ii);
7139
7140 netdev->features = NETIF_F_SG |
7141 NETIF_F_IP_CSUM |
7142 NETIF_F_IPV6_CSUM |
7143 NETIF_F_HW_VLAN_TX |
7144 NETIF_F_HW_VLAN_RX |
7145 NETIF_F_HW_VLAN_FILTER |
7146 NETIF_F_TSO |
7147 NETIF_F_TSO6 |
7148 NETIF_F_RXHASH |
7149 NETIF_F_RXCSUM;
7150
7151 netdev->hw_features = netdev->features;
7152
7153 switch (adapter->hw.mac.type) {
7154 case ixgbe_mac_82599EB:
7155 case ixgbe_mac_X540:
7156 netdev->features |= NETIF_F_SCTP_CSUM;
7157 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7158 NETIF_F_NTUPLE;
7159 break;
7160 default:
7161 break;
7162 }
7163
7164 netdev->hw_features |= NETIF_F_RXALL;
7165
7166 netdev->vlan_features |= NETIF_F_TSO;
7167 netdev->vlan_features |= NETIF_F_TSO6;
7168 netdev->vlan_features |= NETIF_F_IP_CSUM;
7169 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7170 netdev->vlan_features |= NETIF_F_SG;
7171
7172 netdev->priv_flags |= IFF_UNICAST_FLT;
7173 netdev->priv_flags |= IFF_SUPP_NOFCS;
7174
7175 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7176 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7177 IXGBE_FLAG_DCB_ENABLED);
7178
7179 #ifdef CONFIG_IXGBE_DCB
7180 netdev->dcbnl_ops = &dcbnl_ops;
7181 #endif
7182
7183 #ifdef IXGBE_FCOE
7184 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7185 if (hw->mac.ops.get_device_caps) {
7186 hw->mac.ops.get_device_caps(hw, &device_caps);
7187 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7188 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7189 }
7190 }
7191 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7192 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7193 netdev->vlan_features |= NETIF_F_FSO;
7194 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7195 }
7196 #endif /* IXGBE_FCOE */
7197 if (pci_using_dac) {
7198 netdev->features |= NETIF_F_HIGHDMA;
7199 netdev->vlan_features |= NETIF_F_HIGHDMA;
7200 }
7201
7202 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7203 netdev->hw_features |= NETIF_F_LRO;
7204 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7205 netdev->features |= NETIF_F_LRO;
7206
7207 /* make sure the EEPROM is good */
7208 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7209 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7210 err = -EIO;
7211 goto err_sw_init;
7212 }
7213
7214 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7215 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7216
7217 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7218 e_dev_err("invalid MAC address\n");
7219 err = -EIO;
7220 goto err_sw_init;
7221 }
7222
7223 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7224 (unsigned long) adapter);
7225
7226 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7227 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7228
7229 err = ixgbe_init_interrupt_scheme(adapter);
7230 if (err)
7231 goto err_sw_init;
7232
7233 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7234 netdev->hw_features &= ~NETIF_F_RXHASH;
7235 netdev->features &= ~NETIF_F_RXHASH;
7236 }
7237
7238 /* WOL not supported for all devices */
7239 adapter->wol = 0;
7240 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7241 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7242 adapter->wol = IXGBE_WUFC_MAG;
7243
7244 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7245
7246 #ifdef CONFIG_IXGBE_PTP
7247 ixgbe_ptp_init(adapter);
7248 #endif /* CONFIG_IXGBE_PTP*/
7249
7250 /* save off EEPROM version number */
7251 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7252 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7253
7254 /* pick up the PCI bus settings for reporting later */
7255 hw->mac.ops.get_bus_info(hw);
7256
7257 /* print bus type/speed/width info */
7258 e_dev_info("(PCI Express:%s:%s) %pM\n",
7259 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7260 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7261 "Unknown"),
7262 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7263 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7264 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7265 "Unknown"),
7266 netdev->dev_addr);
7267
7268 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7269 if (err)
7270 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7271 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7272 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7273 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7274 part_str);
7275 else
7276 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7277 hw->mac.type, hw->phy.type, part_str);
7278
7279 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7280 e_dev_warn("PCI-Express bandwidth available for this card is "
7281 "not sufficient for optimal performance.\n");
7282 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7283 "is required.\n");
7284 }
7285
7286 /* reset the hardware with the new settings */
7287 err = hw->mac.ops.start_hw(hw);
7288 if (err == IXGBE_ERR_EEPROM_VERSION) {
7289 /* We are running on a pre-production device, log a warning */
7290 e_dev_warn("This device is a pre-production adapter/LOM. "
7291 "Please be aware there may be issues associated "
7292 "with your hardware. If you are experiencing "
7293 "problems please contact your Intel or hardware "
7294 "representative who provided you with this "
7295 "hardware.\n");
7296 }
7297 strcpy(netdev->name, "eth%d");
7298 err = register_netdev(netdev);
7299 if (err)
7300 goto err_register;
7301
7302 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7303 if (hw->mac.ops.disable_tx_laser &&
7304 ((hw->phy.multispeed_fiber) ||
7305 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7306 (hw->mac.type == ixgbe_mac_82599EB))))
7307 hw->mac.ops.disable_tx_laser(hw);
7308
7309 /* carrier off reporting is important to ethtool even BEFORE open */
7310 netif_carrier_off(netdev);
7311
7312 #ifdef CONFIG_IXGBE_DCA
7313 if (dca_add_requester(&pdev->dev) == 0) {
7314 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7315 ixgbe_setup_dca(adapter);
7316 }
7317 #endif
7318 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7319 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7320 for (i = 0; i < adapter->num_vfs; i++)
7321 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7322 }
7323
7324 /* firmware requires driver version to be 0xFFFFFFFF
7325 * since os does not support feature
7326 */
7327 if (hw->mac.ops.set_fw_drv_ver)
7328 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7329 0xFF);
7330
7331 /* add san mac addr to netdev */
7332 ixgbe_add_sanmac_netdev(netdev);
7333
7334 e_dev_info("%s\n", ixgbe_default_device_descr);
7335 cards_found++;
7336
7337 #ifdef CONFIG_IXGBE_HWMON
7338 if (ixgbe_sysfs_init(adapter))
7339 e_err(probe, "failed to allocate sysfs resources\n");
7340 #endif /* CONFIG_IXGBE_HWMON */
7341
7342 return 0;
7343
7344 err_register:
7345 ixgbe_release_hw_control(adapter);
7346 ixgbe_clear_interrupt_scheme(adapter);
7347 err_sw_init:
7348 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7349 ixgbe_disable_sriov(adapter);
7350 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7351 iounmap(hw->hw_addr);
7352 err_ioremap:
7353 free_netdev(netdev);
7354 err_alloc_etherdev:
7355 pci_release_selected_regions(pdev,
7356 pci_select_bars(pdev, IORESOURCE_MEM));
7357 err_pci_reg:
7358 err_dma:
7359 pci_disable_device(pdev);
7360 return err;
7361 }
7362
7363 /**
7364 * ixgbe_remove - Device Removal Routine
7365 * @pdev: PCI device information struct
7366 *
7367 * ixgbe_remove is called by the PCI subsystem to alert the driver
7368 * that it should release a PCI device. The could be caused by a
7369 * Hot-Plug event, or because the driver is going to be removed from
7370 * memory.
7371 **/
7372 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7373 {
7374 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7375 struct net_device *netdev = adapter->netdev;
7376
7377 set_bit(__IXGBE_DOWN, &adapter->state);
7378 cancel_work_sync(&adapter->service_task);
7379
7380 #ifdef CONFIG_IXGBE_PTP
7381 ixgbe_ptp_stop(adapter);
7382 #endif
7383
7384 #ifdef CONFIG_IXGBE_DCA
7385 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7386 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7387 dca_remove_requester(&pdev->dev);
7388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7389 }
7390
7391 #endif
7392 #ifdef CONFIG_IXGBE_HWMON
7393 ixgbe_sysfs_exit(adapter);
7394 #endif /* CONFIG_IXGBE_HWMON */
7395
7396 #ifdef IXGBE_FCOE
7397 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7398 ixgbe_cleanup_fcoe(adapter);
7399
7400 #endif /* IXGBE_FCOE */
7401
7402 /* remove the added san mac */
7403 ixgbe_del_sanmac_netdev(netdev);
7404
7405 if (netdev->reg_state == NETREG_REGISTERED)
7406 unregister_netdev(netdev);
7407
7408 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7409 if (!(ixgbe_check_vf_assignment(adapter)))
7410 ixgbe_disable_sriov(adapter);
7411 else
7412 e_dev_warn("Unloading driver while VFs are assigned "
7413 "- VFs will not be deallocated\n");
7414 }
7415
7416 ixgbe_clear_interrupt_scheme(adapter);
7417
7418 ixgbe_release_hw_control(adapter);
7419
7420 #ifdef CONFIG_DCB
7421 kfree(adapter->ixgbe_ieee_pfc);
7422 kfree(adapter->ixgbe_ieee_ets);
7423
7424 #endif
7425 iounmap(adapter->hw.hw_addr);
7426 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7427 IORESOURCE_MEM));
7428
7429 e_dev_info("complete\n");
7430
7431 free_netdev(netdev);
7432
7433 pci_disable_pcie_error_reporting(pdev);
7434
7435 pci_disable_device(pdev);
7436 }
7437
7438 /**
7439 * ixgbe_io_error_detected - called when PCI error is detected
7440 * @pdev: Pointer to PCI device
7441 * @state: The current pci connection state
7442 *
7443 * This function is called after a PCI bus error affecting
7444 * this device has been detected.
7445 */
7446 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7447 pci_channel_state_t state)
7448 {
7449 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7450 struct net_device *netdev = adapter->netdev;
7451
7452 #ifdef CONFIG_PCI_IOV
7453 struct pci_dev *bdev, *vfdev;
7454 u32 dw0, dw1, dw2, dw3;
7455 int vf, pos;
7456 u16 req_id, pf_func;
7457
7458 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7459 adapter->num_vfs == 0)
7460 goto skip_bad_vf_detection;
7461
7462 bdev = pdev->bus->self;
7463 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7464 bdev = bdev->bus->self;
7465
7466 if (!bdev)
7467 goto skip_bad_vf_detection;
7468
7469 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7470 if (!pos)
7471 goto skip_bad_vf_detection;
7472
7473 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7474 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7475 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7476 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7477
7478 req_id = dw1 >> 16;
7479 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7480 if (!(req_id & 0x0080))
7481 goto skip_bad_vf_detection;
7482
7483 pf_func = req_id & 0x01;
7484 if ((pf_func & 1) == (pdev->devfn & 1)) {
7485 unsigned int device_id;
7486
7487 vf = (req_id & 0x7F) >> 1;
7488 e_dev_err("VF %d has caused a PCIe error\n", vf);
7489 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7490 "%8.8x\tdw3: %8.8x\n",
7491 dw0, dw1, dw2, dw3);
7492 switch (adapter->hw.mac.type) {
7493 case ixgbe_mac_82599EB:
7494 device_id = IXGBE_82599_VF_DEVICE_ID;
7495 break;
7496 case ixgbe_mac_X540:
7497 device_id = IXGBE_X540_VF_DEVICE_ID;
7498 break;
7499 default:
7500 device_id = 0;
7501 break;
7502 }
7503
7504 /* Find the pci device of the offending VF */
7505 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7506 while (vfdev) {
7507 if (vfdev->devfn == (req_id & 0xFF))
7508 break;
7509 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7510 device_id, vfdev);
7511 }
7512 /*
7513 * There's a slim chance the VF could have been hot plugged,
7514 * so if it is no longer present we don't need to issue the
7515 * VFLR. Just clean up the AER in that case.
7516 */
7517 if (vfdev) {
7518 e_dev_err("Issuing VFLR to VF %d\n", vf);
7519 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7520 }
7521
7522 pci_cleanup_aer_uncorrect_error_status(pdev);
7523 }
7524
7525 /*
7526 * Even though the error may have occurred on the other port
7527 * we still need to increment the vf error reference count for
7528 * both ports because the I/O resume function will be called
7529 * for both of them.
7530 */
7531 adapter->vferr_refcount++;
7532
7533 return PCI_ERS_RESULT_RECOVERED;
7534
7535 skip_bad_vf_detection:
7536 #endif /* CONFIG_PCI_IOV */
7537 netif_device_detach(netdev);
7538
7539 if (state == pci_channel_io_perm_failure)
7540 return PCI_ERS_RESULT_DISCONNECT;
7541
7542 if (netif_running(netdev))
7543 ixgbe_down(adapter);
7544 pci_disable_device(pdev);
7545
7546 /* Request a slot reset. */
7547 return PCI_ERS_RESULT_NEED_RESET;
7548 }
7549
7550 /**
7551 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7552 * @pdev: Pointer to PCI device
7553 *
7554 * Restart the card from scratch, as if from a cold-boot.
7555 */
7556 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7557 {
7558 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7559 pci_ers_result_t result;
7560 int err;
7561
7562 if (pci_enable_device_mem(pdev)) {
7563 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7564 result = PCI_ERS_RESULT_DISCONNECT;
7565 } else {
7566 pci_set_master(pdev);
7567 pci_restore_state(pdev);
7568 pci_save_state(pdev);
7569
7570 pci_wake_from_d3(pdev, false);
7571
7572 ixgbe_reset(adapter);
7573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7574 result = PCI_ERS_RESULT_RECOVERED;
7575 }
7576
7577 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7578 if (err) {
7579 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7580 "failed 0x%0x\n", err);
7581 /* non-fatal, continue */
7582 }
7583
7584 return result;
7585 }
7586
7587 /**
7588 * ixgbe_io_resume - called when traffic can start flowing again.
7589 * @pdev: Pointer to PCI device
7590 *
7591 * This callback is called when the error recovery driver tells us that
7592 * its OK to resume normal operation.
7593 */
7594 static void ixgbe_io_resume(struct pci_dev *pdev)
7595 {
7596 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7597 struct net_device *netdev = adapter->netdev;
7598
7599 #ifdef CONFIG_PCI_IOV
7600 if (adapter->vferr_refcount) {
7601 e_info(drv, "Resuming after VF err\n");
7602 adapter->vferr_refcount--;
7603 return;
7604 }
7605
7606 #endif
7607 if (netif_running(netdev))
7608 ixgbe_up(adapter);
7609
7610 netif_device_attach(netdev);
7611 }
7612
7613 static struct pci_error_handlers ixgbe_err_handler = {
7614 .error_detected = ixgbe_io_error_detected,
7615 .slot_reset = ixgbe_io_slot_reset,
7616 .resume = ixgbe_io_resume,
7617 };
7618
7619 static struct pci_driver ixgbe_driver = {
7620 .name = ixgbe_driver_name,
7621 .id_table = ixgbe_pci_tbl,
7622 .probe = ixgbe_probe,
7623 .remove = __devexit_p(ixgbe_remove),
7624 #ifdef CONFIG_PM
7625 .suspend = ixgbe_suspend,
7626 .resume = ixgbe_resume,
7627 #endif
7628 .shutdown = ixgbe_shutdown,
7629 .err_handler = &ixgbe_err_handler
7630 };
7631
7632 /**
7633 * ixgbe_init_module - Driver Registration Routine
7634 *
7635 * ixgbe_init_module is the first routine called when the driver is
7636 * loaded. All it does is register with the PCI subsystem.
7637 **/
7638 static int __init ixgbe_init_module(void)
7639 {
7640 int ret;
7641 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7642 pr_info("%s\n", ixgbe_copyright);
7643
7644 #ifdef CONFIG_IXGBE_DCA
7645 dca_register_notify(&dca_notifier);
7646 #endif
7647
7648 ret = pci_register_driver(&ixgbe_driver);
7649 return ret;
7650 }
7651
7652 module_init(ixgbe_init_module);
7653
7654 /**
7655 * ixgbe_exit_module - Driver Exit Cleanup Routine
7656 *
7657 * ixgbe_exit_module is called just before the driver is removed
7658 * from memory.
7659 **/
7660 static void __exit ixgbe_exit_module(void)
7661 {
7662 #ifdef CONFIG_IXGBE_DCA
7663 dca_unregister_notify(&dca_notifier);
7664 #endif
7665 pci_unregister_driver(&ixgbe_driver);
7666 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7667 }
7668
7669 #ifdef CONFIG_IXGBE_DCA
7670 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7671 void *p)
7672 {
7673 int ret_val;
7674
7675 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7676 __ixgbe_notify_dca);
7677
7678 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7679 }
7680
7681 #endif /* CONFIG_IXGBE_DCA */
7682
7683 module_exit(ixgbe_exit_module);
7684
7685 /* ixgbe_main.c */
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