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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.13.10-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 /* required last entry */
116 {0, }
117 };
118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
120 #ifdef CONFIG_IXGBE_DCA
121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
122 void *p);
123 static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127 };
128 #endif
129
130 #ifdef CONFIG_PCI_IOV
131 static unsigned int max_vfs;
132 module_param(max_vfs, uint, 0);
133 MODULE_PARM_DESC(max_vfs,
134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
135 #endif /* CONFIG_PCI_IOV */
136
137 static unsigned int allow_unsupported_sfp;
138 module_param(allow_unsupported_sfp, uint, 0);
139 MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143 static int debug = -1;
144 module_param(debug, int, 0);
145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149 MODULE_LICENSE("GPL");
150 MODULE_VERSION(DRV_VERSION);
151
152 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
153 u32 reg, u16 *value)
154 {
155 int pos = 0;
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
168 if (!pos)
169 return -1;
170
171 pci_read_config_word(parent_dev, pos + reg, value);
172 return 0;
173 }
174
175 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176 {
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196 }
197
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199 {
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203 }
204
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206 {
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchdog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212 }
213
214 struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217 };
218
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249 };
250
251
252 /*
253 * ixgbe_regdump - register printout routine
254 */
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256 {
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
330 }
331
332 }
333
334 /*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
338 {
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info(" %s %s %s %s\n",
382 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
383 "leng", "ntw", "timestamp");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
387 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
388 n, tx_ring->next_to_use, tx_ring->next_to_clean,
389 (u64)dma_unmap_addr(tx_buffer, dma),
390 dma_unmap_len(tx_buffer, len),
391 tx_buffer->next_to_watch,
392 (u64)tx_buffer->time_stamp);
393 }
394
395 /* Print TX Rings */
396 if (!netif_msg_tx_done(adapter))
397 goto rx_ring_summary;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
400
401 /* Transmit Descriptor Formats
402 *
403 * 82598 Advanced Transmit Descriptor
404 * +--------------------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +--------------------------------------------------------------+
407 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
408 * +--------------------------------------------------------------+
409 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
410 *
411 * 82598 Advanced Transmit Descriptor (Write-Back Format)
412 * +--------------------------------------------------------------+
413 * 0 | RSV [63:0] |
414 * +--------------------------------------------------------------+
415 * 8 | RSV | STA | NXTSEQ |
416 * +--------------------------------------------------------------+
417 * 63 36 35 32 31 0
418 *
419 * 82599+ Advanced Transmit Descriptor
420 * +--------------------------------------------------------------+
421 * 0 | Buffer Address [63:0] |
422 * +--------------------------------------------------------------+
423 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
424 * +--------------------------------------------------------------+
425 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
426 *
427 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
428 * +--------------------------------------------------------------+
429 * 0 | RSV [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | RSV | STA | RSV |
432 * +--------------------------------------------------------------+
433 * 63 36 35 32 31 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("%s%s %s %s %s %s\n",
442 "T [desc] [address 63:0 ] ",
443 "[PlPOIdStDDt Ln] [bi->dma ] ",
444 "leng", "ntw", "timestamp", "bi->skb");
445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
447 tx_desc = IXGBE_TX_DESC(tx_ring, i);
448 tx_buffer = &tx_ring->tx_buffer_info[i];
449 u0 = (struct my_u0 *)tx_desc;
450 if (dma_unmap_len(tx_buffer, len) > 0) {
451 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
452 i,
453 le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(tx_buffer, dma),
456 dma_unmap_len(tx_buffer, len),
457 tx_buffer->next_to_watch,
458 (u64)tx_buffer->time_stamp,
459 tx_buffer->skb);
460 if (i == tx_ring->next_to_use &&
461 i == tx_ring->next_to_clean)
462 pr_cont(" NTC/U\n");
463 else if (i == tx_ring->next_to_use)
464 pr_cont(" NTU\n");
465 else if (i == tx_ring->next_to_clean)
466 pr_cont(" NTC\n");
467 else
468 pr_cont("\n");
469
470 if (netif_msg_pktdata(adapter) &&
471 tx_buffer->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS, 16, 1,
474 tx_buffer->skb->data,
475 dma_unmap_len(tx_buffer, len),
476 true);
477 }
478 }
479 }
480
481 /* Print RX Rings Summary */
482 rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
484 pr_info("Queue [NTU] [NTC]\n");
485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
487 pr_info("%5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Receive Descriptor Formats
498 *
499 * 82598 Advanced Receive Descriptor (Read) Format
500 * 63 1 0
501 * +-----------------------------------------------------+
502 * 0 | Packet Buffer Address [63:1] |A0/NSE|
503 * +----------------------------------------------+------+
504 * 8 | Header Buffer Address [63:1] | DD |
505 * +-----------------------------------------------------+
506 *
507 *
508 * 82598 Advanced Receive Descriptor (Write-Back) Format
509 *
510 * 63 48 47 32 31 30 21 20 16 15 4 3 0
511 * +------------------------------------------------------+
512 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
513 * | Packet | IP | | | | Type | Type |
514 * | Checksum | Ident | | | | | |
515 * +------------------------------------------------------+
516 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
517 * +------------------------------------------------------+
518 * 63 48 47 32 31 20 19 0
519 *
520 * 82599+ Advanced Receive Descriptor (Read) Format
521 * 63 1 0
522 * +-----------------------------------------------------+
523 * 0 | Packet Buffer Address [63:1] |A0/NSE|
524 * +----------------------------------------------+------+
525 * 8 | Header Buffer Address [63:1] | DD |
526 * +-----------------------------------------------------+
527 *
528 *
529 * 82599+ Advanced Receive Descriptor (Write-Back) Format
530 *
531 * 63 48 47 32 31 30 21 20 17 16 4 3 0
532 * +------------------------------------------------------+
533 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
534 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
535 * |/ Flow Dir Flt ID | | | | | |
536 * +------------------------------------------------------+
537 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
538 * +------------------------------------------------------+
539 * 63 48 47 32 31 20 19 0
540 */
541
542 for (n = 0; n < adapter->num_rx_queues; n++) {
543 rx_ring = adapter->rx_ring[n];
544 pr_info("------------------------------------\n");
545 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
546 pr_info("------------------------------------\n");
547 pr_info("%s%s%s",
548 "R [desc] [ PktBuf A0] ",
549 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
550 "<-- Adv Rx Read format\n");
551 pr_info("%s%s%s",
552 "RWB[desc] [PcsmIpSHl PtRs] ",
553 "[vl er S cks ln] ---------------- [bi->skb ] ",
554 "<-- Adv Rx Write-Back format\n");
555
556 for (i = 0; i < rx_ring->count; i++) {
557 rx_buffer_info = &rx_ring->rx_buffer_info[i];
558 rx_desc = IXGBE_RX_DESC(rx_ring, i);
559 u0 = (struct my_u0 *)rx_desc;
560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
561 if (staterr & IXGBE_RXD_STAT_DD) {
562 /* Descriptor Done */
563 pr_info("RWB[0x%03X] %016llX "
564 "%016llX ---------------- %p", i,
565 le64_to_cpu(u0->a),
566 le64_to_cpu(u0->b),
567 rx_buffer_info->skb);
568 } else {
569 pr_info("R [0x%03X] %016llX "
570 "%016llX %016llX %p", i,
571 le64_to_cpu(u0->a),
572 le64_to_cpu(u0->b),
573 (u64)rx_buffer_info->dma,
574 rx_buffer_info->skb);
575
576 if (netif_msg_pktdata(adapter) &&
577 rx_buffer_info->dma) {
578 print_hex_dump(KERN_INFO, "",
579 DUMP_PREFIX_ADDRESS, 16, 1,
580 page_address(rx_buffer_info->page) +
581 rx_buffer_info->page_offset,
582 ixgbe_rx_bufsz(rx_ring), true);
583 }
584 }
585
586 if (i == rx_ring->next_to_use)
587 pr_cont(" NTU\n");
588 else if (i == rx_ring->next_to_clean)
589 pr_cont(" NTC\n");
590 else
591 pr_cont("\n");
592
593 }
594 }
595
596 exit:
597 return;
598 }
599
600 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
601 {
602 u32 ctrl_ext;
603
604 /* Let firmware take over control of h/w */
605 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
607 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
608 }
609
610 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
611 {
612 u32 ctrl_ext;
613
614 /* Let firmware know the driver has taken over */
615 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
617 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
618 }
619
620 /**
621 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
622 * @adapter: pointer to adapter struct
623 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
624 * @queue: queue to map the corresponding interrupt to
625 * @msix_vector: the vector to map to the corresponding queue
626 *
627 */
628 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
629 u8 queue, u8 msix_vector)
630 {
631 u32 ivar, index;
632 struct ixgbe_hw *hw = &adapter->hw;
633 switch (hw->mac.type) {
634 case ixgbe_mac_82598EB:
635 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
636 if (direction == -1)
637 direction = 0;
638 index = (((direction * 64) + queue) >> 2) & 0x1F;
639 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
640 ivar &= ~(0xFF << (8 * (queue & 0x3)));
641 ivar |= (msix_vector << (8 * (queue & 0x3)));
642 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
643 break;
644 case ixgbe_mac_82599EB:
645 case ixgbe_mac_X540:
646 if (direction == -1) {
647 /* other causes */
648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
649 index = ((queue & 1) * 8);
650 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
651 ivar &= ~(0xFF << index);
652 ivar |= (msix_vector << index);
653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
654 break;
655 } else {
656 /* tx or rx causes */
657 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
658 index = ((16 * (queue & 1)) + (8 * direction));
659 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
660 ivar &= ~(0xFF << index);
661 ivar |= (msix_vector << index);
662 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
663 break;
664 }
665 default:
666 break;
667 }
668 }
669
670 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
671 u64 qmask)
672 {
673 u32 mask;
674
675 switch (adapter->hw.mac.type) {
676 case ixgbe_mac_82598EB:
677 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
679 break;
680 case ixgbe_mac_82599EB:
681 case ixgbe_mac_X540:
682 mask = (qmask & 0xFFFFFFFF);
683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
684 mask = (qmask >> 32);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
686 break;
687 default:
688 break;
689 }
690 }
691
692 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
693 struct ixgbe_tx_buffer *tx_buffer)
694 {
695 if (tx_buffer->skb) {
696 dev_kfree_skb_any(tx_buffer->skb);
697 if (dma_unmap_len(tx_buffer, len))
698 dma_unmap_single(ring->dev,
699 dma_unmap_addr(tx_buffer, dma),
700 dma_unmap_len(tx_buffer, len),
701 DMA_TO_DEVICE);
702 } else if (dma_unmap_len(tx_buffer, len)) {
703 dma_unmap_page(ring->dev,
704 dma_unmap_addr(tx_buffer, dma),
705 dma_unmap_len(tx_buffer, len),
706 DMA_TO_DEVICE);
707 }
708 tx_buffer->next_to_watch = NULL;
709 tx_buffer->skb = NULL;
710 dma_unmap_len_set(tx_buffer, len, 0);
711 /* tx_buffer must be completely set up in the transmit path */
712 }
713
714 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
715 {
716 struct ixgbe_hw *hw = &adapter->hw;
717 struct ixgbe_hw_stats *hwstats = &adapter->stats;
718 int i;
719 u32 data;
720
721 if ((hw->fc.current_mode != ixgbe_fc_full) &&
722 (hw->fc.current_mode != ixgbe_fc_rx_pause))
723 return;
724
725 switch (hw->mac.type) {
726 case ixgbe_mac_82598EB:
727 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
728 break;
729 default:
730 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
731 }
732 hwstats->lxoffrxc += data;
733
734 /* refill credits (no tx hang) if we received xoff */
735 if (!data)
736 return;
737
738 for (i = 0; i < adapter->num_tx_queues; i++)
739 clear_bit(__IXGBE_HANG_CHECK_ARMED,
740 &adapter->tx_ring[i]->state);
741 }
742
743 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
744 {
745 struct ixgbe_hw *hw = &adapter->hw;
746 struct ixgbe_hw_stats *hwstats = &adapter->stats;
747 u32 xoff[8] = {0};
748 u8 tc;
749 int i;
750 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
751
752 if (adapter->ixgbe_ieee_pfc)
753 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
754
755 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
756 ixgbe_update_xoff_rx_lfc(adapter);
757 return;
758 }
759
760 /* update stats for each tc, only valid with PFC enabled */
761 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
762 u32 pxoffrxc;
763
764 switch (hw->mac.type) {
765 case ixgbe_mac_82598EB:
766 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
767 break;
768 default:
769 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
770 }
771 hwstats->pxoffrxc[i] += pxoffrxc;
772 /* Get the TC for given UP */
773 tc = netdev_get_prio_tc_map(adapter->netdev, i);
774 xoff[tc] += pxoffrxc;
775 }
776
777 /* disarm tx queues that have received xoff frames */
778 for (i = 0; i < adapter->num_tx_queues; i++) {
779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
780
781 tc = tx_ring->dcb_tc;
782 if (xoff[tc])
783 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
784 }
785 }
786
787 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
788 {
789 return ring->stats.packets;
790 }
791
792 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
793 {
794 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
795 struct ixgbe_hw *hw = &adapter->hw;
796
797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
799
800 if (head != tail)
801 return (head < tail) ?
802 tail - head : (tail + ring->count - head);
803
804 return 0;
805 }
806
807 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
808 {
809 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
810 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
811 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
812 bool ret = false;
813
814 clear_check_for_tx_hang(tx_ring);
815
816 /*
817 * Check for a hung queue, but be thorough. This verifies
818 * that a transmit has been completed since the previous
819 * check AND there is at least one packet pending. The
820 * ARMED bit is set to indicate a potential hang. The
821 * bit is cleared if a pause frame is received to remove
822 * false hang detection due to PFC or 802.3x frames. By
823 * requiring this to fail twice we avoid races with
824 * pfc clearing the ARMED bit and conditions where we
825 * run the check_tx_hang logic with a transmit completion
826 * pending but without time to complete it yet.
827 */
828 if ((tx_done_old == tx_done) && tx_pending) {
829 /* make sure it is true for two checks in a row */
830 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
831 &tx_ring->state);
832 } else {
833 /* update completed stats and continue */
834 tx_ring->tx_stats.tx_done_old = tx_done;
835 /* reset the countdown */
836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
837 }
838
839 return ret;
840 }
841
842 /**
843 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
844 * @adapter: driver private struct
845 **/
846 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
847 {
848
849 /* Do the reset outside of interrupt context */
850 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
851 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
852 e_warn(drv, "initiating reset due to tx timeout\n");
853 ixgbe_service_event_schedule(adapter);
854 }
855 }
856
857 /**
858 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
859 * @q_vector: structure containing interrupt and ring information
860 * @tx_ring: tx ring to clean
861 **/
862 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
863 struct ixgbe_ring *tx_ring)
864 {
865 struct ixgbe_adapter *adapter = q_vector->adapter;
866 struct ixgbe_tx_buffer *tx_buffer;
867 union ixgbe_adv_tx_desc *tx_desc;
868 unsigned int total_bytes = 0, total_packets = 0;
869 unsigned int budget = q_vector->tx.work_limit;
870 unsigned int i = tx_ring->next_to_clean;
871
872 if (test_bit(__IXGBE_DOWN, &adapter->state))
873 return true;
874
875 tx_buffer = &tx_ring->tx_buffer_info[i];
876 tx_desc = IXGBE_TX_DESC(tx_ring, i);
877 i -= tx_ring->count;
878
879 do {
880 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
881
882 /* if next_to_watch is not set then there is no work pending */
883 if (!eop_desc)
884 break;
885
886 /* prevent any other reads prior to eop_desc */
887 read_barrier_depends();
888
889 /* if DD is not set pending work has not been completed */
890 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
891 break;
892
893 /* clear next_to_watch to prevent false hangs */
894 tx_buffer->next_to_watch = NULL;
895
896 /* update the statistics for this packet */
897 total_bytes += tx_buffer->bytecount;
898 total_packets += tx_buffer->gso_segs;
899
900 /* free the skb */
901 dev_kfree_skb_any(tx_buffer->skb);
902
903 /* unmap skb header data */
904 dma_unmap_single(tx_ring->dev,
905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
907 DMA_TO_DEVICE);
908
909 /* clear tx_buffer data */
910 tx_buffer->skb = NULL;
911 dma_unmap_len_set(tx_buffer, len, 0);
912
913 /* unmap remaining buffers */
914 while (tx_desc != eop_desc) {
915 tx_buffer++;
916 tx_desc++;
917 i++;
918 if (unlikely(!i)) {
919 i -= tx_ring->count;
920 tx_buffer = tx_ring->tx_buffer_info;
921 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
922 }
923
924 /* unmap any remaining paged data */
925 if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(tx_ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 dma_unmap_len_set(tx_buffer, len, 0);
931 }
932 }
933
934 /* move us one more past the eop_desc for start of next pkt */
935 tx_buffer++;
936 tx_desc++;
937 i++;
938 if (unlikely(!i)) {
939 i -= tx_ring->count;
940 tx_buffer = tx_ring->tx_buffer_info;
941 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
942 }
943
944 /* issue prefetch for next Tx descriptor */
945 prefetch(tx_desc);
946
947 /* update budget accounting */
948 budget--;
949 } while (likely(budget));
950
951 i += tx_ring->count;
952 tx_ring->next_to_clean = i;
953 u64_stats_update_begin(&tx_ring->syncp);
954 tx_ring->stats.bytes += total_bytes;
955 tx_ring->stats.packets += total_packets;
956 u64_stats_update_end(&tx_ring->syncp);
957 q_vector->tx.total_bytes += total_bytes;
958 q_vector->tx.total_packets += total_packets;
959
960 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
961 /* schedule immediate reset if we believe we hung */
962 struct ixgbe_hw *hw = &adapter->hw;
963 e_err(drv, "Detected Tx Unit Hang\n"
964 " Tx Queue <%d>\n"
965 " TDH, TDT <%x>, <%x>\n"
966 " next_to_use <%x>\n"
967 " next_to_clean <%x>\n"
968 "tx_buffer_info[next_to_clean]\n"
969 " time_stamp <%lx>\n"
970 " jiffies <%lx>\n",
971 tx_ring->queue_index,
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
974 tx_ring->next_to_use, i,
975 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
976
977 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
978
979 e_info(probe,
980 "tx hang %d detected on queue %d, resetting adapter\n",
981 adapter->tx_timeout_count + 1, tx_ring->queue_index);
982
983 /* schedule immediate reset if we believe we hung */
984 ixgbe_tx_timeout_reset(adapter);
985
986 /* the adapter is about to reset, no point in enabling stuff */
987 return true;
988 }
989
990 netdev_tx_completed_queue(txring_txq(tx_ring),
991 total_packets, total_bytes);
992
993 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
994 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
995 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
996 /* Make sure that anybody stopping the queue after this
997 * sees the new next_to_clean.
998 */
999 smp_mb();
1000 if (__netif_subqueue_stopped(tx_ring->netdev,
1001 tx_ring->queue_index)
1002 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1003 netif_wake_subqueue(tx_ring->netdev,
1004 tx_ring->queue_index);
1005 ++tx_ring->tx_stats.restart_queue;
1006 }
1007 }
1008
1009 return !!budget;
1010 }
1011
1012 #ifdef CONFIG_IXGBE_DCA
1013 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1014 struct ixgbe_ring *tx_ring,
1015 int cpu)
1016 {
1017 struct ixgbe_hw *hw = &adapter->hw;
1018 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1019 u16 reg_offset;
1020
1021 switch (hw->mac.type) {
1022 case ixgbe_mac_82598EB:
1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1024 break;
1025 case ixgbe_mac_82599EB:
1026 case ixgbe_mac_X540:
1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1028 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1029 break;
1030 default:
1031 /* for unknown hardware do not write register */
1032 return;
1033 }
1034
1035 /*
1036 * We can enable relaxed ordering for reads, but not writes when
1037 * DCA is enabled. This is due to a known issue in some chipsets
1038 * which will cause the DCA tag to be cleared.
1039 */
1040 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1041 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1042 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1043
1044 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1045 }
1046
1047 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1048 struct ixgbe_ring *rx_ring,
1049 int cpu)
1050 {
1051 struct ixgbe_hw *hw = &adapter->hw;
1052 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1053 u8 reg_idx = rx_ring->reg_idx;
1054
1055
1056 switch (hw->mac.type) {
1057 case ixgbe_mac_82599EB:
1058 case ixgbe_mac_X540:
1059 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1060 break;
1061 default:
1062 break;
1063 }
1064
1065 /*
1066 * We can enable relaxed ordering for reads, but not writes when
1067 * DCA is enabled. This is due to a known issue in some chipsets
1068 * which will cause the DCA tag to be cleared.
1069 */
1070 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1071 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1072
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1074 }
1075
1076 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1077 {
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct ixgbe_ring *ring;
1080 int cpu = get_cpu();
1081
1082 if (q_vector->cpu == cpu)
1083 goto out_no_update;
1084
1085 ixgbe_for_each_ring(ring, q_vector->tx)
1086 ixgbe_update_tx_dca(adapter, ring, cpu);
1087
1088 ixgbe_for_each_ring(ring, q_vector->rx)
1089 ixgbe_update_rx_dca(adapter, ring, cpu);
1090
1091 q_vector->cpu = cpu;
1092 out_no_update:
1093 put_cpu();
1094 }
1095
1096 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1097 {
1098 int i;
1099
1100 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1101 return;
1102
1103 /* always use CB2 mode, difference is masked in the CB driver */
1104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1105
1106 for (i = 0; i < adapter->num_q_vectors; i++) {
1107 adapter->q_vector[i]->cpu = -1;
1108 ixgbe_update_dca(adapter->q_vector[i]);
1109 }
1110 }
1111
1112 static int __ixgbe_notify_dca(struct device *dev, void *data)
1113 {
1114 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1115 unsigned long event = *(unsigned long *)data;
1116
1117 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1118 return 0;
1119
1120 switch (event) {
1121 case DCA_PROVIDER_ADD:
1122 /* if we're already enabled, don't do it again */
1123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1124 break;
1125 if (dca_add_requester(dev) == 0) {
1126 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1127 ixgbe_setup_dca(adapter);
1128 break;
1129 }
1130 /* Fall Through since DCA is disabled. */
1131 case DCA_PROVIDER_REMOVE:
1132 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1133 dca_remove_requester(dev);
1134 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1136 }
1137 break;
1138 }
1139
1140 return 0;
1141 }
1142
1143 #endif /* CONFIG_IXGBE_DCA */
1144 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1145 union ixgbe_adv_rx_desc *rx_desc,
1146 struct sk_buff *skb)
1147 {
1148 if (ring->netdev->features & NETIF_F_RXHASH)
1149 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1150 }
1151
1152 #ifdef IXGBE_FCOE
1153 /**
1154 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1155 * @ring: structure containing ring specific data
1156 * @rx_desc: advanced rx descriptor
1157 *
1158 * Returns : true if it is FCoE pkt
1159 */
1160 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1161 union ixgbe_adv_rx_desc *rx_desc)
1162 {
1163 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1164
1165 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1166 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1167 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1168 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1169 }
1170
1171 #endif /* IXGBE_FCOE */
1172 /**
1173 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1174 * @ring: structure containing ring specific data
1175 * @rx_desc: current Rx descriptor being processed
1176 * @skb: skb currently being received and modified
1177 **/
1178 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1179 union ixgbe_adv_rx_desc *rx_desc,
1180 struct sk_buff *skb)
1181 {
1182 skb_checksum_none_assert(skb);
1183
1184 /* Rx csum disabled */
1185 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1186 return;
1187
1188 /* if IP and error */
1189 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1190 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1191 ring->rx_stats.csum_err++;
1192 return;
1193 }
1194
1195 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1196 return;
1197
1198 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1199 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1200
1201 /*
1202 * 82599 errata, UDP frames with a 0 checksum can be marked as
1203 * checksum errors.
1204 */
1205 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1206 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1207 return;
1208
1209 ring->rx_stats.csum_err++;
1210 return;
1211 }
1212
1213 /* It must be a TCP or UDP packet with a valid checksum */
1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
1215 }
1216
1217 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1218 {
1219 rx_ring->next_to_use = val;
1220
1221 /* update next to alloc since we have filled the ring */
1222 rx_ring->next_to_alloc = val;
1223 /*
1224 * Force memory writes to complete before letting h/w
1225 * know there are new descriptors to fetch. (Only
1226 * applicable for weak-ordered memory model archs,
1227 * such as IA-64).
1228 */
1229 wmb();
1230 writel(val, rx_ring->tail);
1231 }
1232
1233 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1234 struct ixgbe_rx_buffer *bi)
1235 {
1236 struct page *page = bi->page;
1237 dma_addr_t dma = bi->dma;
1238
1239 /* since we are recycling buffers we should seldom need to alloc */
1240 if (likely(dma))
1241 return true;
1242
1243 /* alloc new page for storage */
1244 if (likely(!page)) {
1245 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1246 bi->skb, ixgbe_rx_pg_order(rx_ring));
1247 if (unlikely(!page)) {
1248 rx_ring->rx_stats.alloc_rx_page_failed++;
1249 return false;
1250 }
1251 bi->page = page;
1252 }
1253
1254 /* map page for use */
1255 dma = dma_map_page(rx_ring->dev, page, 0,
1256 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1257
1258 /*
1259 * if mapping failed free memory back to system since
1260 * there isn't much point in holding memory we can't use
1261 */
1262 if (dma_mapping_error(rx_ring->dev, dma)) {
1263 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1264 bi->page = NULL;
1265
1266 rx_ring->rx_stats.alloc_rx_page_failed++;
1267 return false;
1268 }
1269
1270 bi->dma = dma;
1271 bi->page_offset = 0;
1272
1273 return true;
1274 }
1275
1276 /**
1277 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1278 * @rx_ring: ring to place buffers on
1279 * @cleaned_count: number of buffers to replace
1280 **/
1281 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1282 {
1283 union ixgbe_adv_rx_desc *rx_desc;
1284 struct ixgbe_rx_buffer *bi;
1285 u16 i = rx_ring->next_to_use;
1286
1287 /* nothing to do */
1288 if (!cleaned_count)
1289 return;
1290
1291 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1292 bi = &rx_ring->rx_buffer_info[i];
1293 i -= rx_ring->count;
1294
1295 do {
1296 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1297 break;
1298
1299 /*
1300 * Refresh the desc even if buffer_addrs didn't change
1301 * because each write-back erases this info.
1302 */
1303 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1304
1305 rx_desc++;
1306 bi++;
1307 i++;
1308 if (unlikely(!i)) {
1309 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1310 bi = rx_ring->rx_buffer_info;
1311 i -= rx_ring->count;
1312 }
1313
1314 /* clear the hdr_addr for the next_to_use descriptor */
1315 rx_desc->read.hdr_addr = 0;
1316
1317 cleaned_count--;
1318 } while (cleaned_count);
1319
1320 i += rx_ring->count;
1321
1322 if (rx_ring->next_to_use != i)
1323 ixgbe_release_rx_desc(rx_ring, i);
1324 }
1325
1326 /**
1327 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1328 * @data: pointer to the start of the headers
1329 * @max_len: total length of section to find headers in
1330 *
1331 * This function is meant to determine the length of headers that will
1332 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1333 * motivation of doing this is to only perform one pull for IPv4 TCP
1334 * packets so that we can do basic things like calculating the gso_size
1335 * based on the average data per packet.
1336 **/
1337 static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 unsigned int max_len)
1339 {
1340 union {
1341 unsigned char *network;
1342 /* l2 headers */
1343 struct ethhdr *eth;
1344 struct vlan_hdr *vlan;
1345 /* l3 headers */
1346 struct iphdr *ipv4;
1347 struct ipv6hdr *ipv6;
1348 } hdr;
1349 __be16 protocol;
1350 u8 nexthdr = 0; /* default to not TCP */
1351 u8 hlen;
1352
1353 /* this should never happen, but better safe than sorry */
1354 if (max_len < ETH_HLEN)
1355 return max_len;
1356
1357 /* initialize network frame pointer */
1358 hdr.network = data;
1359
1360 /* set first protocol and move network header forward */
1361 protocol = hdr.eth->h_proto;
1362 hdr.network += ETH_HLEN;
1363
1364 /* handle any vlan tag if present */
1365 if (protocol == __constant_htons(ETH_P_8021Q)) {
1366 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1367 return max_len;
1368
1369 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1370 hdr.network += VLAN_HLEN;
1371 }
1372
1373 /* handle L3 protocols */
1374 if (protocol == __constant_htons(ETH_P_IP)) {
1375 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1376 return max_len;
1377
1378 /* access ihl as a u8 to avoid unaligned access on ia64 */
1379 hlen = (hdr.network[0] & 0x0F) << 2;
1380
1381 /* verify hlen meets minimum size requirements */
1382 if (hlen < sizeof(struct iphdr))
1383 return hdr.network - data;
1384
1385 /* record next protocol if header is present */
1386 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1387 nexthdr = hdr.ipv4->protocol;
1388 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1389 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1390 return max_len;
1391
1392 /* record next protocol */
1393 nexthdr = hdr.ipv6->nexthdr;
1394 hlen = sizeof(struct ipv6hdr);
1395 #ifdef IXGBE_FCOE
1396 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1397 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1398 return max_len;
1399 hlen = FCOE_HEADER_LEN;
1400 #endif
1401 } else {
1402 return hdr.network - data;
1403 }
1404
1405 /* relocate pointer to start of L4 header */
1406 hdr.network += hlen;
1407
1408 /* finally sort out TCP/UDP */
1409 if (nexthdr == IPPROTO_TCP) {
1410 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1411 return max_len;
1412
1413 /* access doff as a u8 to avoid unaligned access on ia64 */
1414 hlen = (hdr.network[12] & 0xF0) >> 2;
1415
1416 /* verify hlen meets minimum size requirements */
1417 if (hlen < sizeof(struct tcphdr))
1418 return hdr.network - data;
1419
1420 hdr.network += hlen;
1421 } else if (nexthdr == IPPROTO_UDP) {
1422 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1423 return max_len;
1424
1425 hdr.network += sizeof(struct udphdr);
1426 }
1427
1428 /*
1429 * If everything has gone correctly hdr.network should be the
1430 * data section of the packet and will be the end of the header.
1431 * If not then it probably represents the end of the last recognized
1432 * header.
1433 */
1434 if ((hdr.network - data) < max_len)
1435 return hdr.network - data;
1436 else
1437 return max_len;
1438 }
1439
1440 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1441 struct sk_buff *skb)
1442 {
1443 u16 hdr_len = skb_headlen(skb);
1444
1445 /* set gso_size to avoid messing up TCP MSS */
1446 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1447 IXGBE_CB(skb)->append_cnt);
1448 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1449 }
1450
1451 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1452 struct sk_buff *skb)
1453 {
1454 /* if append_cnt is 0 then frame is not RSC */
1455 if (!IXGBE_CB(skb)->append_cnt)
1456 return;
1457
1458 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1459 rx_ring->rx_stats.rsc_flush++;
1460
1461 ixgbe_set_rsc_gso_size(rx_ring, skb);
1462
1463 /* gso_size is computed using append_cnt so always clear it last */
1464 IXGBE_CB(skb)->append_cnt = 0;
1465 }
1466
1467 /**
1468 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1469 * @rx_ring: rx descriptor ring packet is being transacted on
1470 * @rx_desc: pointer to the EOP Rx descriptor
1471 * @skb: pointer to current skb being populated
1472 *
1473 * This function checks the ring, descriptor, and packet information in
1474 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1475 * other fields within the skb.
1476 **/
1477 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480 {
1481 struct net_device *dev = rx_ring->netdev;
1482
1483 ixgbe_update_rsc_stats(rx_ring, skb);
1484
1485 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1486
1487 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1488
1489 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1490
1491 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1492 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1493 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1494 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1495 }
1496
1497 skb_record_rx_queue(skb, rx_ring->queue_index);
1498
1499 skb->protocol = eth_type_trans(skb, dev);
1500 }
1501
1502 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1503 struct sk_buff *skb)
1504 {
1505 struct ixgbe_adapter *adapter = q_vector->adapter;
1506
1507 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1508 napi_gro_receive(&q_vector->napi, skb);
1509 else
1510 netif_rx(skb);
1511 }
1512
1513 /**
1514 * ixgbe_is_non_eop - process handling of non-EOP buffers
1515 * @rx_ring: Rx ring being processed
1516 * @rx_desc: Rx descriptor for current buffer
1517 * @skb: Current socket buffer containing buffer in progress
1518 *
1519 * This function updates next to clean. If the buffer is an EOP buffer
1520 * this function exits returning false, otherwise it will place the
1521 * sk_buff in the next buffer to be chained and return true indicating
1522 * that this is in fact a non-EOP buffer.
1523 **/
1524 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1525 union ixgbe_adv_rx_desc *rx_desc,
1526 struct sk_buff *skb)
1527 {
1528 u32 ntc = rx_ring->next_to_clean + 1;
1529
1530 /* fetch, update, and store next to clean */
1531 ntc = (ntc < rx_ring->count) ? ntc : 0;
1532 rx_ring->next_to_clean = ntc;
1533
1534 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1535
1536 /* update RSC append count if present */
1537 if (ring_is_rsc_enabled(rx_ring)) {
1538 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1539 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1540
1541 if (unlikely(rsc_enabled)) {
1542 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1543
1544 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1545 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1546
1547 /* update ntc based on RSC value */
1548 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1549 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1550 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1551 }
1552 }
1553
1554 /* if we are the last buffer then there is nothing else to do */
1555 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1556 return false;
1557
1558 /* place skb in next buffer to be received */
1559 rx_ring->rx_buffer_info[ntc].skb = skb;
1560 rx_ring->rx_stats.non_eop_descs++;
1561
1562 return true;
1563 }
1564
1565 /**
1566 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1567 * @rx_ring: rx descriptor ring packet is being transacted on
1568 * @skb: pointer to current skb being adjusted
1569 *
1570 * This function is an ixgbe specific version of __pskb_pull_tail. The
1571 * main difference between this version and the original function is that
1572 * this function can make several assumptions about the state of things
1573 * that allow for significant optimizations versus the standard function.
1574 * As a result we can do things like drop a frag and maintain an accurate
1575 * truesize for the skb.
1576 */
1577 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1578 struct sk_buff *skb)
1579 {
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1581 unsigned char *va;
1582 unsigned int pull_len;
1583
1584 /*
1585 * it is valid to use page_address instead of kmap since we are
1586 * working with pages allocated out of the lomem pool per
1587 * alloc_page(GFP_ATOMIC)
1588 */
1589 va = skb_frag_address(frag);
1590
1591 /*
1592 * we need the header to contain the greater of either ETH_HLEN or
1593 * 60 bytes if the skb->len is less than 60 for skb_pad.
1594 */
1595 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1596
1597 /* align pull length to size of long to optimize memcpy performance */
1598 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1599
1600 /* update all of the pointers */
1601 skb_frag_size_sub(frag, pull_len);
1602 frag->page_offset += pull_len;
1603 skb->data_len -= pull_len;
1604 skb->tail += pull_len;
1605 }
1606
1607 /**
1608 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1609 * @rx_ring: rx descriptor ring packet is being transacted on
1610 * @skb: pointer to current skb being updated
1611 *
1612 * This function provides a basic DMA sync up for the first fragment of an
1613 * skb. The reason for doing this is that the first fragment cannot be
1614 * unmapped until we have reached the end of packet descriptor for a buffer
1615 * chain.
1616 */
1617 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1618 struct sk_buff *skb)
1619 {
1620 /* if the page was released unmap it, else just sync our portion */
1621 if (unlikely(IXGBE_CB(skb)->page_released)) {
1622 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1623 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1624 IXGBE_CB(skb)->page_released = false;
1625 } else {
1626 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1627
1628 dma_sync_single_range_for_cpu(rx_ring->dev,
1629 IXGBE_CB(skb)->dma,
1630 frag->page_offset,
1631 ixgbe_rx_bufsz(rx_ring),
1632 DMA_FROM_DEVICE);
1633 }
1634 IXGBE_CB(skb)->dma = 0;
1635 }
1636
1637 /**
1638 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1639 * @rx_ring: rx descriptor ring packet is being transacted on
1640 * @rx_desc: pointer to the EOP Rx descriptor
1641 * @skb: pointer to current skb being fixed
1642 *
1643 * Check for corrupted packet headers caused by senders on the local L2
1644 * embedded NIC switch not setting up their Tx Descriptors right. These
1645 * should be very rare.
1646 *
1647 * Also address the case where we are pulling data in on pages only
1648 * and as such no data is present in the skb header.
1649 *
1650 * In addition if skb is not at least 60 bytes we need to pad it so that
1651 * it is large enough to qualify as a valid Ethernet frame.
1652 *
1653 * Returns true if an error was encountered and skb was freed.
1654 **/
1655 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1656 union ixgbe_adv_rx_desc *rx_desc,
1657 struct sk_buff *skb)
1658 {
1659 struct net_device *netdev = rx_ring->netdev;
1660
1661 /* verify that the packet does not have any known errors */
1662 if (unlikely(ixgbe_test_staterr(rx_desc,
1663 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1664 !(netdev->features & NETIF_F_RXALL))) {
1665 dev_kfree_skb_any(skb);
1666 return true;
1667 }
1668
1669 /* place header in linear portion of buffer */
1670 if (skb_is_nonlinear(skb))
1671 ixgbe_pull_tail(rx_ring, skb);
1672
1673 #ifdef IXGBE_FCOE
1674 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1675 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1676 return false;
1677
1678 #endif
1679 /* if skb_pad returns an error the skb was freed */
1680 if (unlikely(skb->len < 60)) {
1681 int pad_len = 60 - skb->len;
1682
1683 if (skb_pad(skb, pad_len))
1684 return true;
1685 __skb_put(skb, pad_len);
1686 }
1687
1688 return false;
1689 }
1690
1691 /**
1692 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1693 * @rx_ring: rx descriptor ring to store buffers on
1694 * @old_buff: donor buffer to have page reused
1695 *
1696 * Synchronizes page for reuse by the adapter
1697 **/
1698 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1699 struct ixgbe_rx_buffer *old_buff)
1700 {
1701 struct ixgbe_rx_buffer *new_buff;
1702 u16 nta = rx_ring->next_to_alloc;
1703
1704 new_buff = &rx_ring->rx_buffer_info[nta];
1705
1706 /* update, and store next to alloc */
1707 nta++;
1708 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1709
1710 /* transfer page from old buffer to new buffer */
1711 new_buff->page = old_buff->page;
1712 new_buff->dma = old_buff->dma;
1713 new_buff->page_offset = old_buff->page_offset;
1714
1715 /* sync the buffer for use by the device */
1716 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1717 new_buff->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721
1722 /**
1723 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1724 * @rx_ring: rx descriptor ring to transact packets on
1725 * @rx_buffer: buffer containing page to add
1726 * @rx_desc: descriptor containing length of buffer written by hardware
1727 * @skb: sk_buff to place the data into
1728 *
1729 * This function will add the data contained in rx_buffer->page to the skb.
1730 * This is done either through a direct copy if the data in the buffer is
1731 * less than the skb header size, otherwise it will just attach the page as
1732 * a frag to the skb.
1733 *
1734 * The function will then update the page offset if necessary and return
1735 * true if the buffer can be reused by the adapter.
1736 **/
1737 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1738 struct ixgbe_rx_buffer *rx_buffer,
1739 union ixgbe_adv_rx_desc *rx_desc,
1740 struct sk_buff *skb)
1741 {
1742 struct page *page = rx_buffer->page;
1743 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1744 #if (PAGE_SIZE < 8192)
1745 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1746 #else
1747 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1748 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1749 ixgbe_rx_bufsz(rx_ring);
1750 #endif
1751
1752 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1753 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1754
1755 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1756
1757 /* we can reuse buffer as-is, just make sure it is local */
1758 if (likely(page_to_nid(page) == numa_node_id()))
1759 return true;
1760
1761 /* this page cannot be reused so discard it */
1762 put_page(page);
1763 return false;
1764 }
1765
1766 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1767 rx_buffer->page_offset, size, truesize);
1768
1769 /* avoid re-using remote pages */
1770 if (unlikely(page_to_nid(page) != numa_node_id()))
1771 return false;
1772
1773 #if (PAGE_SIZE < 8192)
1774 /* if we are only owner of page we can reuse it */
1775 if (unlikely(page_count(page) != 1))
1776 return false;
1777
1778 /* flip page offset to other buffer */
1779 rx_buffer->page_offset ^= truesize;
1780
1781 /*
1782 * since we are the only owner of the page and we need to
1783 * increment it, just set the value to 2 in order to avoid
1784 * an unecessary locked operation
1785 */
1786 atomic_set(&page->_count, 2);
1787 #else
1788 /* move offset up to the next cache line */
1789 rx_buffer->page_offset += truesize;
1790
1791 if (rx_buffer->page_offset > last_offset)
1792 return false;
1793
1794 /* bump ref count on page before it is given to the stack */
1795 get_page(page);
1796 #endif
1797
1798 return true;
1799 }
1800
1801 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1802 union ixgbe_adv_rx_desc *rx_desc)
1803 {
1804 struct ixgbe_rx_buffer *rx_buffer;
1805 struct sk_buff *skb;
1806 struct page *page;
1807
1808 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1809 page = rx_buffer->page;
1810 prefetchw(page);
1811
1812 skb = rx_buffer->skb;
1813
1814 if (likely(!skb)) {
1815 void *page_addr = page_address(page) +
1816 rx_buffer->page_offset;
1817
1818 /* prefetch first cache line of first page */
1819 prefetch(page_addr);
1820 #if L1_CACHE_BYTES < 128
1821 prefetch(page_addr + L1_CACHE_BYTES);
1822 #endif
1823
1824 /* allocate a skb to store the frags */
1825 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1826 IXGBE_RX_HDR_SIZE);
1827 if (unlikely(!skb)) {
1828 rx_ring->rx_stats.alloc_rx_buff_failed++;
1829 return NULL;
1830 }
1831
1832 /*
1833 * we will be copying header into skb->data in
1834 * pskb_may_pull so it is in our interest to prefetch
1835 * it now to avoid a possible cache miss
1836 */
1837 prefetchw(skb->data);
1838
1839 /*
1840 * Delay unmapping of the first packet. It carries the
1841 * header information, HW may still access the header
1842 * after the writeback. Only unmap it when EOP is
1843 * reached
1844 */
1845 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1846 goto dma_sync;
1847
1848 IXGBE_CB(skb)->dma = rx_buffer->dma;
1849 } else {
1850 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1851 ixgbe_dma_sync_frag(rx_ring, skb);
1852
1853 dma_sync:
1854 /* we are reusing so sync this buffer for CPU use */
1855 dma_sync_single_range_for_cpu(rx_ring->dev,
1856 rx_buffer->dma,
1857 rx_buffer->page_offset,
1858 ixgbe_rx_bufsz(rx_ring),
1859 DMA_FROM_DEVICE);
1860 }
1861
1862 /* pull page into skb */
1863 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1864 /* hand second half of page back to the ring */
1865 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1866 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1867 /* the page has been released from the ring */
1868 IXGBE_CB(skb)->page_released = true;
1869 } else {
1870 /* we are not reusing the buffer so unmap it */
1871 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1872 ixgbe_rx_pg_size(rx_ring),
1873 DMA_FROM_DEVICE);
1874 }
1875
1876 /* clear contents of buffer_info */
1877 rx_buffer->skb = NULL;
1878 rx_buffer->dma = 0;
1879 rx_buffer->page = NULL;
1880
1881 return skb;
1882 }
1883
1884 /**
1885 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1886 * @q_vector: structure containing interrupt and ring information
1887 * @rx_ring: rx descriptor ring to transact packets on
1888 * @budget: Total limit on number of packets to process
1889 *
1890 * This function provides a "bounce buffer" approach to Rx interrupt
1891 * processing. The advantage to this is that on systems that have
1892 * expensive overhead for IOMMU access this provides a means of avoiding
1893 * it by maintaining the mapping of the page to the syste.
1894 *
1895 * Returns true if all work is completed without reaching budget
1896 **/
1897 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1898 struct ixgbe_ring *rx_ring,
1899 const int budget)
1900 {
1901 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1902 #ifdef IXGBE_FCOE
1903 struct ixgbe_adapter *adapter = q_vector->adapter;
1904 int ddp_bytes;
1905 unsigned int mss = 0;
1906 #endif /* IXGBE_FCOE */
1907 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1908
1909 do {
1910 union ixgbe_adv_rx_desc *rx_desc;
1911 struct sk_buff *skb;
1912
1913 /* return some buffers to hardware, one at a time is too slow */
1914 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1915 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1916 cleaned_count = 0;
1917 }
1918
1919 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1920
1921 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1922 break;
1923
1924 /*
1925 * This memory barrier is needed to keep us from reading
1926 * any other fields out of the rx_desc until we know the
1927 * RXD_STAT_DD bit is set
1928 */
1929 rmb();
1930
1931 /* retrieve a buffer from the ring */
1932 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1933
1934 /* exit if we failed to retrieve a buffer */
1935 if (!skb)
1936 break;
1937
1938 cleaned_count++;
1939
1940 /* place incomplete frames back on ring for completion */
1941 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1942 continue;
1943
1944 /* verify the packet layout is correct */
1945 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1946 continue;
1947
1948 /* probably a little skewed due to removing CRC */
1949 total_rx_bytes += skb->len;
1950
1951 /* populate checksum, timestamp, VLAN, and protocol */
1952 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1953
1954 #ifdef IXGBE_FCOE
1955 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1956 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1957 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1958 /* include DDPed FCoE data */
1959 if (ddp_bytes > 0) {
1960 if (!mss) {
1961 mss = rx_ring->netdev->mtu -
1962 sizeof(struct fcoe_hdr) -
1963 sizeof(struct fc_frame_header) -
1964 sizeof(struct fcoe_crc_eof);
1965 if (mss > 512)
1966 mss &= ~511;
1967 }
1968 total_rx_bytes += ddp_bytes;
1969 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1970 mss);
1971 }
1972 if (!ddp_bytes) {
1973 dev_kfree_skb_any(skb);
1974 continue;
1975 }
1976 }
1977
1978 #endif /* IXGBE_FCOE */
1979 ixgbe_rx_skb(q_vector, skb);
1980
1981 /* update budget accounting */
1982 total_rx_packets++;
1983 } while (likely(total_rx_packets < budget));
1984
1985 u64_stats_update_begin(&rx_ring->syncp);
1986 rx_ring->stats.packets += total_rx_packets;
1987 rx_ring->stats.bytes += total_rx_bytes;
1988 u64_stats_update_end(&rx_ring->syncp);
1989 q_vector->rx.total_packets += total_rx_packets;
1990 q_vector->rx.total_bytes += total_rx_bytes;
1991
1992 if (cleaned_count)
1993 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1994
1995 return (total_rx_packets < budget);
1996 }
1997
1998 /**
1999 * ixgbe_configure_msix - Configure MSI-X hardware
2000 * @adapter: board private structure
2001 *
2002 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2003 * interrupts.
2004 **/
2005 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2006 {
2007 struct ixgbe_q_vector *q_vector;
2008 int v_idx;
2009 u32 mask;
2010
2011 /* Populate MSIX to EITR Select */
2012 if (adapter->num_vfs > 32) {
2013 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2015 }
2016
2017 /*
2018 * Populate the IVAR table and set the ITR values to the
2019 * corresponding register.
2020 */
2021 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2022 struct ixgbe_ring *ring;
2023 q_vector = adapter->q_vector[v_idx];
2024
2025 ixgbe_for_each_ring(ring, q_vector->rx)
2026 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2027
2028 ixgbe_for_each_ring(ring, q_vector->tx)
2029 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2030
2031 ixgbe_write_eitr(q_vector);
2032 }
2033
2034 switch (adapter->hw.mac.type) {
2035 case ixgbe_mac_82598EB:
2036 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2037 v_idx);
2038 break;
2039 case ixgbe_mac_82599EB:
2040 case ixgbe_mac_X540:
2041 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2042 break;
2043 default:
2044 break;
2045 }
2046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2047
2048 /* set up to autoclear timer, and the vectors */
2049 mask = IXGBE_EIMS_ENABLE_MASK;
2050 mask &= ~(IXGBE_EIMS_OTHER |
2051 IXGBE_EIMS_MAILBOX |
2052 IXGBE_EIMS_LSC);
2053
2054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2055 }
2056
2057 enum latency_range {
2058 lowest_latency = 0,
2059 low_latency = 1,
2060 bulk_latency = 2,
2061 latency_invalid = 255
2062 };
2063
2064 /**
2065 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2066 * @q_vector: structure containing interrupt and ring information
2067 * @ring_container: structure containing ring performance data
2068 *
2069 * Stores a new ITR value based on packets and byte
2070 * counts during the last interrupt. The advantage of per interrupt
2071 * computation is faster updates and more accurate ITR for the current
2072 * traffic pattern. Constants in this function were computed
2073 * based on theoretical maximum wire speed and thresholds were set based
2074 * on testing data as well as attempting to minimize response time
2075 * while increasing bulk throughput.
2076 * this functionality is controlled by the InterruptThrottleRate module
2077 * parameter (see ixgbe_param.c)
2078 **/
2079 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2080 struct ixgbe_ring_container *ring_container)
2081 {
2082 int bytes = ring_container->total_bytes;
2083 int packets = ring_container->total_packets;
2084 u32 timepassed_us;
2085 u64 bytes_perint;
2086 u8 itr_setting = ring_container->itr;
2087
2088 if (packets == 0)
2089 return;
2090
2091 /* simple throttlerate management
2092 * 0-10MB/s lowest (100000 ints/s)
2093 * 10-20MB/s low (20000 ints/s)
2094 * 20-1249MB/s bulk (8000 ints/s)
2095 */
2096 /* what was last interrupt timeslice? */
2097 timepassed_us = q_vector->itr >> 2;
2098 if (timepassed_us == 0)
2099 return;
2100
2101 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2102
2103 switch (itr_setting) {
2104 case lowest_latency:
2105 if (bytes_perint > 10)
2106 itr_setting = low_latency;
2107 break;
2108 case low_latency:
2109 if (bytes_perint > 20)
2110 itr_setting = bulk_latency;
2111 else if (bytes_perint <= 10)
2112 itr_setting = lowest_latency;
2113 break;
2114 case bulk_latency:
2115 if (bytes_perint <= 20)
2116 itr_setting = low_latency;
2117 break;
2118 }
2119
2120 /* clear work counters since we have the values we need */
2121 ring_container->total_bytes = 0;
2122 ring_container->total_packets = 0;
2123
2124 /* write updated itr to ring container */
2125 ring_container->itr = itr_setting;
2126 }
2127
2128 /**
2129 * ixgbe_write_eitr - write EITR register in hardware specific way
2130 * @q_vector: structure containing interrupt and ring information
2131 *
2132 * This function is made to be called by ethtool and by the driver
2133 * when it needs to update EITR registers at runtime. Hardware
2134 * specific quirks/differences are taken care of here.
2135 */
2136 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2137 {
2138 struct ixgbe_adapter *adapter = q_vector->adapter;
2139 struct ixgbe_hw *hw = &adapter->hw;
2140 int v_idx = q_vector->v_idx;
2141 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2142
2143 switch (adapter->hw.mac.type) {
2144 case ixgbe_mac_82598EB:
2145 /* must write high and low 16 bits to reset counter */
2146 itr_reg |= (itr_reg << 16);
2147 break;
2148 case ixgbe_mac_82599EB:
2149 case ixgbe_mac_X540:
2150 /*
2151 * set the WDIS bit to not clear the timer bits and cause an
2152 * immediate assertion of the interrupt
2153 */
2154 itr_reg |= IXGBE_EITR_CNT_WDIS;
2155 break;
2156 default:
2157 break;
2158 }
2159 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2160 }
2161
2162 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2163 {
2164 u32 new_itr = q_vector->itr;
2165 u8 current_itr;
2166
2167 ixgbe_update_itr(q_vector, &q_vector->tx);
2168 ixgbe_update_itr(q_vector, &q_vector->rx);
2169
2170 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2171
2172 switch (current_itr) {
2173 /* counts and packets in update_itr are dependent on these numbers */
2174 case lowest_latency:
2175 new_itr = IXGBE_100K_ITR;
2176 break;
2177 case low_latency:
2178 new_itr = IXGBE_20K_ITR;
2179 break;
2180 case bulk_latency:
2181 new_itr = IXGBE_8K_ITR;
2182 break;
2183 default:
2184 break;
2185 }
2186
2187 if (new_itr != q_vector->itr) {
2188 /* do an exponential smoothing */
2189 new_itr = (10 * new_itr * q_vector->itr) /
2190 ((9 * new_itr) + q_vector->itr);
2191
2192 /* save the algorithm value here */
2193 q_vector->itr = new_itr;
2194
2195 ixgbe_write_eitr(q_vector);
2196 }
2197 }
2198
2199 /**
2200 * ixgbe_check_overtemp_subtask - check for over temperature
2201 * @adapter: pointer to adapter
2202 **/
2203 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2204 {
2205 struct ixgbe_hw *hw = &adapter->hw;
2206 u32 eicr = adapter->interrupt_event;
2207
2208 if (test_bit(__IXGBE_DOWN, &adapter->state))
2209 return;
2210
2211 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2212 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2213 return;
2214
2215 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2216
2217 switch (hw->device_id) {
2218 case IXGBE_DEV_ID_82599_T3_LOM:
2219 /*
2220 * Since the warning interrupt is for both ports
2221 * we don't have to check if:
2222 * - This interrupt wasn't for our port.
2223 * - We may have missed the interrupt so always have to
2224 * check if we got a LSC
2225 */
2226 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2227 !(eicr & IXGBE_EICR_LSC))
2228 return;
2229
2230 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2231 u32 speed;
2232 bool link_up = false;
2233
2234 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2235
2236 if (link_up)
2237 return;
2238 }
2239
2240 /* Check if this is not due to overtemp */
2241 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2242 return;
2243
2244 break;
2245 default:
2246 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2247 return;
2248 break;
2249 }
2250 e_crit(drv,
2251 "Network adapter has been stopped because it has over heated. "
2252 "Restart the computer. If the problem persists, "
2253 "power off the system and replace the adapter\n");
2254
2255 adapter->interrupt_event = 0;
2256 }
2257
2258 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2259 {
2260 struct ixgbe_hw *hw = &adapter->hw;
2261
2262 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2263 (eicr & IXGBE_EICR_GPI_SDP1)) {
2264 e_crit(probe, "Fan has stopped, replace the adapter\n");
2265 /* write to clear the interrupt */
2266 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2267 }
2268 }
2269
2270 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2271 {
2272 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2273 return;
2274
2275 switch (adapter->hw.mac.type) {
2276 case ixgbe_mac_82599EB:
2277 /*
2278 * Need to check link state so complete overtemp check
2279 * on service task
2280 */
2281 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2282 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2283 adapter->interrupt_event = eicr;
2284 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2285 ixgbe_service_event_schedule(adapter);
2286 return;
2287 }
2288 return;
2289 case ixgbe_mac_X540:
2290 if (!(eicr & IXGBE_EICR_TS))
2291 return;
2292 break;
2293 default:
2294 return;
2295 }
2296
2297 e_crit(drv,
2298 "Network adapter has been stopped because it has over heated. "
2299 "Restart the computer. If the problem persists, "
2300 "power off the system and replace the adapter\n");
2301 }
2302
2303 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2304 {
2305 struct ixgbe_hw *hw = &adapter->hw;
2306
2307 if (eicr & IXGBE_EICR_GPI_SDP2) {
2308 /* Clear the interrupt */
2309 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2310 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2311 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2312 ixgbe_service_event_schedule(adapter);
2313 }
2314 }
2315
2316 if (eicr & IXGBE_EICR_GPI_SDP1) {
2317 /* Clear the interrupt */
2318 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2319 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2320 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2321 ixgbe_service_event_schedule(adapter);
2322 }
2323 }
2324 }
2325
2326 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2327 {
2328 struct ixgbe_hw *hw = &adapter->hw;
2329
2330 adapter->lsc_int++;
2331 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2332 adapter->link_check_timeout = jiffies;
2333 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2334 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2335 IXGBE_WRITE_FLUSH(hw);
2336 ixgbe_service_event_schedule(adapter);
2337 }
2338 }
2339
2340 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2341 u64 qmask)
2342 {
2343 u32 mask;
2344 struct ixgbe_hw *hw = &adapter->hw;
2345
2346 switch (hw->mac.type) {
2347 case ixgbe_mac_82598EB:
2348 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2349 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2350 break;
2351 case ixgbe_mac_82599EB:
2352 case ixgbe_mac_X540:
2353 mask = (qmask & 0xFFFFFFFF);
2354 if (mask)
2355 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2356 mask = (qmask >> 32);
2357 if (mask)
2358 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2359 break;
2360 default:
2361 break;
2362 }
2363 /* skip the flush */
2364 }
2365
2366 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2367 u64 qmask)
2368 {
2369 u32 mask;
2370 struct ixgbe_hw *hw = &adapter->hw;
2371
2372 switch (hw->mac.type) {
2373 case ixgbe_mac_82598EB:
2374 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2375 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2376 break;
2377 case ixgbe_mac_82599EB:
2378 case ixgbe_mac_X540:
2379 mask = (qmask & 0xFFFFFFFF);
2380 if (mask)
2381 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2382 mask = (qmask >> 32);
2383 if (mask)
2384 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2385 break;
2386 default:
2387 break;
2388 }
2389 /* skip the flush */
2390 }
2391
2392 /**
2393 * ixgbe_irq_enable - Enable default interrupt generation settings
2394 * @adapter: board private structure
2395 **/
2396 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2397 bool flush)
2398 {
2399 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2400
2401 /* don't reenable LSC while waiting for link */
2402 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2403 mask &= ~IXGBE_EIMS_LSC;
2404
2405 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2406 switch (adapter->hw.mac.type) {
2407 case ixgbe_mac_82599EB:
2408 mask |= IXGBE_EIMS_GPI_SDP0;
2409 break;
2410 case ixgbe_mac_X540:
2411 mask |= IXGBE_EIMS_TS;
2412 break;
2413 default:
2414 break;
2415 }
2416 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2417 mask |= IXGBE_EIMS_GPI_SDP1;
2418 switch (adapter->hw.mac.type) {
2419 case ixgbe_mac_82599EB:
2420 mask |= IXGBE_EIMS_GPI_SDP1;
2421 mask |= IXGBE_EIMS_GPI_SDP2;
2422 case ixgbe_mac_X540:
2423 mask |= IXGBE_EIMS_ECC;
2424 mask |= IXGBE_EIMS_MAILBOX;
2425 break;
2426 default:
2427 break;
2428 }
2429
2430 if (adapter->hw.mac.type == ixgbe_mac_X540)
2431 mask |= IXGBE_EIMS_TIMESYNC;
2432
2433 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2434 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2435 mask |= IXGBE_EIMS_FLOW_DIR;
2436
2437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2438 if (queues)
2439 ixgbe_irq_enable_queues(adapter, ~0);
2440 if (flush)
2441 IXGBE_WRITE_FLUSH(&adapter->hw);
2442 }
2443
2444 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2445 {
2446 struct ixgbe_adapter *adapter = data;
2447 struct ixgbe_hw *hw = &adapter->hw;
2448 u32 eicr;
2449
2450 /*
2451 * Workaround for Silicon errata. Use clear-by-write instead
2452 * of clear-by-read. Reading with EICS will return the
2453 * interrupt causes without clearing, which later be done
2454 * with the write to EICR.
2455 */
2456 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2457 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2458
2459 if (eicr & IXGBE_EICR_LSC)
2460 ixgbe_check_lsc(adapter);
2461
2462 if (eicr & IXGBE_EICR_MAILBOX)
2463 ixgbe_msg_task(adapter);
2464
2465 switch (hw->mac.type) {
2466 case ixgbe_mac_82599EB:
2467 case ixgbe_mac_X540:
2468 if (eicr & IXGBE_EICR_ECC)
2469 e_info(link, "Received unrecoverable ECC Err, please "
2470 "reboot\n");
2471 /* Handle Flow Director Full threshold interrupt */
2472 if (eicr & IXGBE_EICR_FLOW_DIR) {
2473 int reinit_count = 0;
2474 int i;
2475 for (i = 0; i < adapter->num_tx_queues; i++) {
2476 struct ixgbe_ring *ring = adapter->tx_ring[i];
2477 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2478 &ring->state))
2479 reinit_count++;
2480 }
2481 if (reinit_count) {
2482 /* no more flow director interrupts until after init */
2483 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2484 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2485 ixgbe_service_event_schedule(adapter);
2486 }
2487 }
2488 ixgbe_check_sfp_event(adapter, eicr);
2489 ixgbe_check_overtemp_event(adapter, eicr);
2490 break;
2491 default:
2492 break;
2493 }
2494
2495 ixgbe_check_fan_failure(adapter, eicr);
2496
2497 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2498 ixgbe_ptp_check_pps_event(adapter, eicr);
2499
2500 /* re-enable the original interrupt state, no lsc, no queues */
2501 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2502 ixgbe_irq_enable(adapter, false, false);
2503
2504 return IRQ_HANDLED;
2505 }
2506
2507 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2508 {
2509 struct ixgbe_q_vector *q_vector = data;
2510
2511 /* EIAM disabled interrupts (on this vector) for us */
2512
2513 if (q_vector->rx.ring || q_vector->tx.ring)
2514 napi_schedule(&q_vector->napi);
2515
2516 return IRQ_HANDLED;
2517 }
2518
2519 /**
2520 * ixgbe_poll - NAPI Rx polling callback
2521 * @napi: structure for representing this polling device
2522 * @budget: how many packets driver is allowed to clean
2523 *
2524 * This function is used for legacy and MSI, NAPI mode
2525 **/
2526 int ixgbe_poll(struct napi_struct *napi, int budget)
2527 {
2528 struct ixgbe_q_vector *q_vector =
2529 container_of(napi, struct ixgbe_q_vector, napi);
2530 struct ixgbe_adapter *adapter = q_vector->adapter;
2531 struct ixgbe_ring *ring;
2532 int per_ring_budget;
2533 bool clean_complete = true;
2534
2535 #ifdef CONFIG_IXGBE_DCA
2536 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2537 ixgbe_update_dca(q_vector);
2538 #endif
2539
2540 ixgbe_for_each_ring(ring, q_vector->tx)
2541 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2542
2543 /* attempt to distribute budget to each queue fairly, but don't allow
2544 * the budget to go below 1 because we'll exit polling */
2545 if (q_vector->rx.count > 1)
2546 per_ring_budget = max(budget/q_vector->rx.count, 1);
2547 else
2548 per_ring_budget = budget;
2549
2550 ixgbe_for_each_ring(ring, q_vector->rx)
2551 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2552 per_ring_budget);
2553
2554 /* If all work not completed, return budget and keep polling */
2555 if (!clean_complete)
2556 return budget;
2557
2558 /* all work done, exit the polling mode */
2559 napi_complete(napi);
2560 if (adapter->rx_itr_setting & 1)
2561 ixgbe_set_itr(q_vector);
2562 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2563 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2564
2565 return 0;
2566 }
2567
2568 /**
2569 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2570 * @adapter: board private structure
2571 *
2572 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2573 * interrupts from the kernel.
2574 **/
2575 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2576 {
2577 struct net_device *netdev = adapter->netdev;
2578 int vector, err;
2579 int ri = 0, ti = 0;
2580
2581 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2582 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2583 struct msix_entry *entry = &adapter->msix_entries[vector];
2584
2585 if (q_vector->tx.ring && q_vector->rx.ring) {
2586 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2587 "%s-%s-%d", netdev->name, "TxRx", ri++);
2588 ti++;
2589 } else if (q_vector->rx.ring) {
2590 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2591 "%s-%s-%d", netdev->name, "rx", ri++);
2592 } else if (q_vector->tx.ring) {
2593 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2594 "%s-%s-%d", netdev->name, "tx", ti++);
2595 } else {
2596 /* skip this unused q_vector */
2597 continue;
2598 }
2599 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2600 q_vector->name, q_vector);
2601 if (err) {
2602 e_err(probe, "request_irq failed for MSIX interrupt "
2603 "Error: %d\n", err);
2604 goto free_queue_irqs;
2605 }
2606 /* If Flow Director is enabled, set interrupt affinity */
2607 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2608 /* assign the mask for this irq */
2609 irq_set_affinity_hint(entry->vector,
2610 &q_vector->affinity_mask);
2611 }
2612 }
2613
2614 err = request_irq(adapter->msix_entries[vector].vector,
2615 ixgbe_msix_other, 0, netdev->name, adapter);
2616 if (err) {
2617 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2618 goto free_queue_irqs;
2619 }
2620
2621 return 0;
2622
2623 free_queue_irqs:
2624 while (vector) {
2625 vector--;
2626 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2627 NULL);
2628 free_irq(adapter->msix_entries[vector].vector,
2629 adapter->q_vector[vector]);
2630 }
2631 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2632 pci_disable_msix(adapter->pdev);
2633 kfree(adapter->msix_entries);
2634 adapter->msix_entries = NULL;
2635 return err;
2636 }
2637
2638 /**
2639 * ixgbe_intr - legacy mode Interrupt Handler
2640 * @irq: interrupt number
2641 * @data: pointer to a network interface device structure
2642 **/
2643 static irqreturn_t ixgbe_intr(int irq, void *data)
2644 {
2645 struct ixgbe_adapter *adapter = data;
2646 struct ixgbe_hw *hw = &adapter->hw;
2647 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2648 u32 eicr;
2649
2650 /*
2651 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2652 * before the read of EICR.
2653 */
2654 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2655
2656 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2657 * therefore no explicit interrupt disable is necessary */
2658 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2659 if (!eicr) {
2660 /*
2661 * shared interrupt alert!
2662 * make sure interrupts are enabled because the read will
2663 * have disabled interrupts due to EIAM
2664 * finish the workaround of silicon errata on 82598. Unmask
2665 * the interrupt that we masked before the EICR read.
2666 */
2667 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2668 ixgbe_irq_enable(adapter, true, true);
2669 return IRQ_NONE; /* Not our interrupt */
2670 }
2671
2672 if (eicr & IXGBE_EICR_LSC)
2673 ixgbe_check_lsc(adapter);
2674
2675 switch (hw->mac.type) {
2676 case ixgbe_mac_82599EB:
2677 ixgbe_check_sfp_event(adapter, eicr);
2678 /* Fall through */
2679 case ixgbe_mac_X540:
2680 if (eicr & IXGBE_EICR_ECC)
2681 e_info(link, "Received unrecoverable ECC err, please "
2682 "reboot\n");
2683 ixgbe_check_overtemp_event(adapter, eicr);
2684 break;
2685 default:
2686 break;
2687 }
2688
2689 ixgbe_check_fan_failure(adapter, eicr);
2690 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2691 ixgbe_ptp_check_pps_event(adapter, eicr);
2692
2693 /* would disable interrupts here but EIAM disabled it */
2694 napi_schedule(&q_vector->napi);
2695
2696 /*
2697 * re-enable link(maybe) and non-queue interrupts, no flush.
2698 * ixgbe_poll will re-enable the queue interrupts
2699 */
2700 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2701 ixgbe_irq_enable(adapter, false, false);
2702
2703 return IRQ_HANDLED;
2704 }
2705
2706 /**
2707 * ixgbe_request_irq - initialize interrupts
2708 * @adapter: board private structure
2709 *
2710 * Attempts to configure interrupts using the best available
2711 * capabilities of the hardware and kernel.
2712 **/
2713 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2714 {
2715 struct net_device *netdev = adapter->netdev;
2716 int err;
2717
2718 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2719 err = ixgbe_request_msix_irqs(adapter);
2720 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2721 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2722 netdev->name, adapter);
2723 else
2724 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2725 netdev->name, adapter);
2726
2727 if (err)
2728 e_err(probe, "request_irq failed, Error %d\n", err);
2729
2730 return err;
2731 }
2732
2733 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2734 {
2735 int vector;
2736
2737 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2738 free_irq(adapter->pdev->irq, adapter);
2739 return;
2740 }
2741
2742 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2743 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2744 struct msix_entry *entry = &adapter->msix_entries[vector];
2745
2746 /* free only the irqs that were actually requested */
2747 if (!q_vector->rx.ring && !q_vector->tx.ring)
2748 continue;
2749
2750 /* clear the affinity_mask in the IRQ descriptor */
2751 irq_set_affinity_hint(entry->vector, NULL);
2752
2753 free_irq(entry->vector, q_vector);
2754 }
2755
2756 free_irq(adapter->msix_entries[vector++].vector, adapter);
2757 }
2758
2759 /**
2760 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2761 * @adapter: board private structure
2762 **/
2763 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2764 {
2765 switch (adapter->hw.mac.type) {
2766 case ixgbe_mac_82598EB:
2767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2768 break;
2769 case ixgbe_mac_82599EB:
2770 case ixgbe_mac_X540:
2771 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2773 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2774 break;
2775 default:
2776 break;
2777 }
2778 IXGBE_WRITE_FLUSH(&adapter->hw);
2779 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2780 int vector;
2781
2782 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2783 synchronize_irq(adapter->msix_entries[vector].vector);
2784
2785 synchronize_irq(adapter->msix_entries[vector++].vector);
2786 } else {
2787 synchronize_irq(adapter->pdev->irq);
2788 }
2789 }
2790
2791 /**
2792 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2793 *
2794 **/
2795 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2796 {
2797 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2798
2799 ixgbe_write_eitr(q_vector);
2800
2801 ixgbe_set_ivar(adapter, 0, 0, 0);
2802 ixgbe_set_ivar(adapter, 1, 0, 0);
2803
2804 e_info(hw, "Legacy interrupt IVAR setup done\n");
2805 }
2806
2807 /**
2808 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2809 * @adapter: board private structure
2810 * @ring: structure containing ring specific data
2811 *
2812 * Configure the Tx descriptor ring after a reset.
2813 **/
2814 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2815 struct ixgbe_ring *ring)
2816 {
2817 struct ixgbe_hw *hw = &adapter->hw;
2818 u64 tdba = ring->dma;
2819 int wait_loop = 10;
2820 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2821 u8 reg_idx = ring->reg_idx;
2822
2823 /* disable queue to avoid issues while updating state */
2824 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2825 IXGBE_WRITE_FLUSH(hw);
2826
2827 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2828 (tdba & DMA_BIT_MASK(32)));
2829 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2830 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2831 ring->count * sizeof(union ixgbe_adv_tx_desc));
2832 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2833 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2834 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2835
2836 /*
2837 * set WTHRESH to encourage burst writeback, it should not be set
2838 * higher than 1 when:
2839 * - ITR is 0 as it could cause false TX hangs
2840 * - ITR is set to > 100k int/sec and BQL is enabled
2841 *
2842 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2843 * to or less than the number of on chip descriptors, which is
2844 * currently 40.
2845 */
2846 #if IS_ENABLED(CONFIG_BQL)
2847 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2848 #else
2849 if (!ring->q_vector || (ring->q_vector->itr < 8))
2850 #endif
2851 txdctl |= (1 << 16); /* WTHRESH = 1 */
2852 else
2853 txdctl |= (8 << 16); /* WTHRESH = 8 */
2854
2855 /*
2856 * Setting PTHRESH to 32 both improves performance
2857 * and avoids a TX hang with DFP enabled
2858 */
2859 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2860 32; /* PTHRESH = 32 */
2861
2862 /* reinitialize flowdirector state */
2863 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2864 ring->atr_sample_rate = adapter->atr_sample_rate;
2865 ring->atr_count = 0;
2866 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2867 } else {
2868 ring->atr_sample_rate = 0;
2869 }
2870
2871 /* initialize XPS */
2872 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2873 struct ixgbe_q_vector *q_vector = ring->q_vector;
2874
2875 if (q_vector)
2876 netif_set_xps_queue(adapter->netdev,
2877 &q_vector->affinity_mask,
2878 ring->queue_index);
2879 }
2880
2881 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2882
2883 /* enable queue */
2884 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2885
2886 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2887 if (hw->mac.type == ixgbe_mac_82598EB &&
2888 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2889 return;
2890
2891 /* poll to verify queue is enabled */
2892 do {
2893 usleep_range(1000, 2000);
2894 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2895 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2896 if (!wait_loop)
2897 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2898 }
2899
2900 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2901 {
2902 struct ixgbe_hw *hw = &adapter->hw;
2903 u32 rttdcs, mtqc;
2904 u8 tcs = netdev_get_num_tc(adapter->netdev);
2905
2906 if (hw->mac.type == ixgbe_mac_82598EB)
2907 return;
2908
2909 /* disable the arbiter while setting MTQC */
2910 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2911 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2912 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2913
2914 /* set transmit pool layout */
2915 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2916 mtqc = IXGBE_MTQC_VT_ENA;
2917 if (tcs > 4)
2918 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2919 else if (tcs > 1)
2920 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2921 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2922 mtqc |= IXGBE_MTQC_32VF;
2923 else
2924 mtqc |= IXGBE_MTQC_64VF;
2925 } else {
2926 if (tcs > 4)
2927 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2928 else if (tcs > 1)
2929 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2930 else
2931 mtqc = IXGBE_MTQC_64Q_1PB;
2932 }
2933
2934 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2935
2936 /* Enable Security TX Buffer IFG for multiple pb */
2937 if (tcs) {
2938 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2939 sectx |= IXGBE_SECTX_DCB;
2940 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2941 }
2942
2943 /* re-enable the arbiter */
2944 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2945 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2946 }
2947
2948 /**
2949 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2950 * @adapter: board private structure
2951 *
2952 * Configure the Tx unit of the MAC after a reset.
2953 **/
2954 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2955 {
2956 struct ixgbe_hw *hw = &adapter->hw;
2957 u32 dmatxctl;
2958 u32 i;
2959
2960 ixgbe_setup_mtqc(adapter);
2961
2962 if (hw->mac.type != ixgbe_mac_82598EB) {
2963 /* DMATXCTL.EN must be before Tx queues are enabled */
2964 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2965 dmatxctl |= IXGBE_DMATXCTL_TE;
2966 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2967 }
2968
2969 /* Setup the HW Tx Head and Tail descriptor pointers */
2970 for (i = 0; i < adapter->num_tx_queues; i++)
2971 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2972 }
2973
2974 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2975 struct ixgbe_ring *ring)
2976 {
2977 struct ixgbe_hw *hw = &adapter->hw;
2978 u8 reg_idx = ring->reg_idx;
2979 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2980
2981 srrctl |= IXGBE_SRRCTL_DROP_EN;
2982
2983 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2984 }
2985
2986 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2987 struct ixgbe_ring *ring)
2988 {
2989 struct ixgbe_hw *hw = &adapter->hw;
2990 u8 reg_idx = ring->reg_idx;
2991 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2992
2993 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2994
2995 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2996 }
2997
2998 #ifdef CONFIG_IXGBE_DCB
2999 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3000 #else
3001 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3002 #endif
3003 {
3004 int i;
3005 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3006
3007 if (adapter->ixgbe_ieee_pfc)
3008 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3009
3010 /*
3011 * We should set the drop enable bit if:
3012 * SR-IOV is enabled
3013 * or
3014 * Number of Rx queues > 1 and flow control is disabled
3015 *
3016 * This allows us to avoid head of line blocking for security
3017 * and performance reasons.
3018 */
3019 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3020 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3021 for (i = 0; i < adapter->num_rx_queues; i++)
3022 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3023 } else {
3024 for (i = 0; i < adapter->num_rx_queues; i++)
3025 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3026 }
3027 }
3028
3029 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3030
3031 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3032 struct ixgbe_ring *rx_ring)
3033 {
3034 struct ixgbe_hw *hw = &adapter->hw;
3035 u32 srrctl;
3036 u8 reg_idx = rx_ring->reg_idx;
3037
3038 if (hw->mac.type == ixgbe_mac_82598EB) {
3039 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3040
3041 /*
3042 * if VMDq is not active we must program one srrctl register
3043 * per RSS queue since we have enabled RDRXCTL.MVMEN
3044 */
3045 reg_idx &= mask;
3046 }
3047
3048 /* configure header buffer length, needed for RSC */
3049 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3050
3051 /* configure the packet buffer length */
3052 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3053
3054 /* configure descriptor type */
3055 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3056
3057 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3058 }
3059
3060 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3061 {
3062 struct ixgbe_hw *hw = &adapter->hw;
3063 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3064 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3065 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3066 u32 mrqc = 0, reta = 0;
3067 u32 rxcsum;
3068 int i, j;
3069 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3070
3071 /*
3072 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3073 * make full use of any rings they may have. We will use the
3074 * PSRTYPE register to control how many rings we use within the PF.
3075 */
3076 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3077 rss_i = 2;
3078
3079 /* Fill out hash function seeds */
3080 for (i = 0; i < 10; i++)
3081 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3082
3083 /* Fill out redirection table */
3084 for (i = 0, j = 0; i < 128; i++, j++) {
3085 if (j == rss_i)
3086 j = 0;
3087 /* reta = 4-byte sliding window of
3088 * 0x00..(indices-1)(indices-1)00..etc. */
3089 reta = (reta << 8) | (j * 0x11);
3090 if ((i & 3) == 3)
3091 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3092 }
3093
3094 /* Disable indicating checksum in descriptor, enables RSS hash */
3095 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3096 rxcsum |= IXGBE_RXCSUM_PCSD;
3097 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3098
3099 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3100 if (adapter->ring_feature[RING_F_RSS].mask)
3101 mrqc = IXGBE_MRQC_RSSEN;
3102 } else {
3103 u8 tcs = netdev_get_num_tc(adapter->netdev);
3104
3105 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3106 if (tcs > 4)
3107 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3108 else if (tcs > 1)
3109 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3110 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3111 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3112 else
3113 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3114 } else {
3115 if (tcs > 4)
3116 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3117 else if (tcs > 1)
3118 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3119 else
3120 mrqc = IXGBE_MRQC_RSSEN;
3121 }
3122 }
3123
3124 /* Perform hash on these packet types */
3125 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3126 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3127 IXGBE_MRQC_RSS_FIELD_IPV6 |
3128 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3129
3130 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3131 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3132 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3133 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3134
3135 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3136 }
3137
3138 /**
3139 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3140 * @adapter: address of board private structure
3141 * @index: index of ring to set
3142 **/
3143 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3144 struct ixgbe_ring *ring)
3145 {
3146 struct ixgbe_hw *hw = &adapter->hw;
3147 u32 rscctrl;
3148 u8 reg_idx = ring->reg_idx;
3149
3150 if (!ring_is_rsc_enabled(ring))
3151 return;
3152
3153 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3154 rscctrl |= IXGBE_RSCCTL_RSCEN;
3155 /*
3156 * we must limit the number of descriptors so that the
3157 * total size of max desc * buf_len is not greater
3158 * than 65536
3159 */
3160 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3161 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3162 }
3163
3164 #define IXGBE_MAX_RX_DESC_POLL 10
3165 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3166 struct ixgbe_ring *ring)
3167 {
3168 struct ixgbe_hw *hw = &adapter->hw;
3169 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3170 u32 rxdctl;
3171 u8 reg_idx = ring->reg_idx;
3172
3173 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3174 if (hw->mac.type == ixgbe_mac_82598EB &&
3175 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3176 return;
3177
3178 do {
3179 usleep_range(1000, 2000);
3180 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3181 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3182
3183 if (!wait_loop) {
3184 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3185 "the polling period\n", reg_idx);
3186 }
3187 }
3188
3189 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3190 struct ixgbe_ring *ring)
3191 {
3192 struct ixgbe_hw *hw = &adapter->hw;
3193 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3194 u32 rxdctl;
3195 u8 reg_idx = ring->reg_idx;
3196
3197 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3198 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3199
3200 /* write value back with RXDCTL.ENABLE bit cleared */
3201 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3202
3203 if (hw->mac.type == ixgbe_mac_82598EB &&
3204 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3205 return;
3206
3207 /* the hardware may take up to 100us to really disable the rx queue */
3208 do {
3209 udelay(10);
3210 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3211 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3212
3213 if (!wait_loop) {
3214 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3215 "the polling period\n", reg_idx);
3216 }
3217 }
3218
3219 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3220 struct ixgbe_ring *ring)
3221 {
3222 struct ixgbe_hw *hw = &adapter->hw;
3223 u64 rdba = ring->dma;
3224 u32 rxdctl;
3225 u8 reg_idx = ring->reg_idx;
3226
3227 /* disable queue to avoid issues while updating state */
3228 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3229 ixgbe_disable_rx_queue(adapter, ring);
3230
3231 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3232 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3233 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3234 ring->count * sizeof(union ixgbe_adv_rx_desc));
3235 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3236 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3237 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3238
3239 ixgbe_configure_srrctl(adapter, ring);
3240 ixgbe_configure_rscctl(adapter, ring);
3241
3242 if (hw->mac.type == ixgbe_mac_82598EB) {
3243 /*
3244 * enable cache line friendly hardware writes:
3245 * PTHRESH=32 descriptors (half the internal cache),
3246 * this also removes ugly rx_no_buffer_count increment
3247 * HTHRESH=4 descriptors (to minimize latency on fetch)
3248 * WTHRESH=8 burst writeback up to two cache lines
3249 */
3250 rxdctl &= ~0x3FFFFF;
3251 rxdctl |= 0x080420;
3252 }
3253
3254 /* enable receive descriptor ring */
3255 rxdctl |= IXGBE_RXDCTL_ENABLE;
3256 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3257
3258 ixgbe_rx_desc_queue_enable(adapter, ring);
3259 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3260 }
3261
3262 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3263 {
3264 struct ixgbe_hw *hw = &adapter->hw;
3265 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3266 int p;
3267
3268 /* PSRTYPE must be initialized in non 82598 adapters */
3269 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3270 IXGBE_PSRTYPE_UDPHDR |
3271 IXGBE_PSRTYPE_IPV4HDR |
3272 IXGBE_PSRTYPE_L2HDR |
3273 IXGBE_PSRTYPE_IPV6HDR;
3274
3275 if (hw->mac.type == ixgbe_mac_82598EB)
3276 return;
3277
3278 if (rss_i > 3)
3279 psrtype |= 2 << 29;
3280 else if (rss_i > 1)
3281 psrtype |= 1 << 29;
3282
3283 for (p = 0; p < adapter->num_rx_pools; p++)
3284 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3285 psrtype);
3286 }
3287
3288 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3289 {
3290 struct ixgbe_hw *hw = &adapter->hw;
3291 u32 reg_offset, vf_shift;
3292 u32 gcr_ext, vmdctl;
3293 int i;
3294
3295 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3296 return;
3297
3298 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3299 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3300 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3301 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3302 vmdctl |= IXGBE_VT_CTL_REPLEN;
3303 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3304
3305 vf_shift = VMDQ_P(0) % 32;
3306 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3307
3308 /* Enable only the PF's pool for Tx/Rx */
3309 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3310 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3311 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3312 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3313 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3314 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3315
3316 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3317 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3318
3319 /*
3320 * Set up VF register offsets for selected VT Mode,
3321 * i.e. 32 or 64 VFs for SR-IOV
3322 */
3323 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3324 case IXGBE_82599_VMDQ_8Q_MASK:
3325 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3326 break;
3327 case IXGBE_82599_VMDQ_4Q_MASK:
3328 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3329 break;
3330 default:
3331 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3332 break;
3333 }
3334
3335 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3336
3337
3338 /* Enable MAC Anti-Spoofing */
3339 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3340 adapter->num_vfs);
3341 /* For VFs that have spoof checking turned off */
3342 for (i = 0; i < adapter->num_vfs; i++) {
3343 if (!adapter->vfinfo[i].spoofchk_enabled)
3344 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3345 }
3346 }
3347
3348 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3349 {
3350 struct ixgbe_hw *hw = &adapter->hw;
3351 struct net_device *netdev = adapter->netdev;
3352 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3353 struct ixgbe_ring *rx_ring;
3354 int i;
3355 u32 mhadd, hlreg0;
3356
3357 #ifdef IXGBE_FCOE
3358 /* adjust max frame to be able to do baby jumbo for FCoE */
3359 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3360 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3361 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3362
3363 #endif /* IXGBE_FCOE */
3364
3365 /* adjust max frame to be at least the size of a standard frame */
3366 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3367 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3368
3369 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3370 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3371 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3372 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3373
3374 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3375 }
3376
3377 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3378 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3379 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3380 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3381
3382 /*
3383 * Setup the HW Rx Head and Tail Descriptor Pointers and
3384 * the Base and Length of the Rx Descriptor Ring
3385 */
3386 for (i = 0; i < adapter->num_rx_queues; i++) {
3387 rx_ring = adapter->rx_ring[i];
3388 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3389 set_ring_rsc_enabled(rx_ring);
3390 else
3391 clear_ring_rsc_enabled(rx_ring);
3392 }
3393 }
3394
3395 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3396 {
3397 struct ixgbe_hw *hw = &adapter->hw;
3398 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3399
3400 switch (hw->mac.type) {
3401 case ixgbe_mac_82598EB:
3402 /*
3403 * For VMDq support of different descriptor types or
3404 * buffer sizes through the use of multiple SRRCTL
3405 * registers, RDRXCTL.MVMEN must be set to 1
3406 *
3407 * also, the manual doesn't mention it clearly but DCA hints
3408 * will only use queue 0's tags unless this bit is set. Side
3409 * effects of setting this bit are only that SRRCTL must be
3410 * fully programmed [0..15]
3411 */
3412 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3413 break;
3414 case ixgbe_mac_82599EB:
3415 case ixgbe_mac_X540:
3416 /* Disable RSC for ACK packets */
3417 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3418 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3419 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3420 /* hardware requires some bits to be set by default */
3421 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3422 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3423 break;
3424 default:
3425 /* We should do nothing since we don't know this hardware */
3426 return;
3427 }
3428
3429 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3430 }
3431
3432 /**
3433 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3434 * @adapter: board private structure
3435 *
3436 * Configure the Rx unit of the MAC after a reset.
3437 **/
3438 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3439 {
3440 struct ixgbe_hw *hw = &adapter->hw;
3441 int i;
3442 u32 rxctrl;
3443
3444 /* disable receives while setting up the descriptors */
3445 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3446 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3447
3448 ixgbe_setup_psrtype(adapter);
3449 ixgbe_setup_rdrxctl(adapter);
3450
3451 /* Program registers for the distribution of queues */
3452 ixgbe_setup_mrqc(adapter);
3453
3454 /* set_rx_buffer_len must be called before ring initialization */
3455 ixgbe_set_rx_buffer_len(adapter);
3456
3457 /*
3458 * Setup the HW Rx Head and Tail Descriptor Pointers and
3459 * the Base and Length of the Rx Descriptor Ring
3460 */
3461 for (i = 0; i < adapter->num_rx_queues; i++)
3462 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3463
3464 /* disable drop enable for 82598 parts */
3465 if (hw->mac.type == ixgbe_mac_82598EB)
3466 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3467
3468 /* enable all receives */
3469 rxctrl |= IXGBE_RXCTRL_RXEN;
3470 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3471 }
3472
3473 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3474 __be16 proto, u16 vid)
3475 {
3476 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3477 struct ixgbe_hw *hw = &adapter->hw;
3478
3479 /* add VID to filter table */
3480 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3481 set_bit(vid, adapter->active_vlans);
3482
3483 return 0;
3484 }
3485
3486 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3487 __be16 proto, u16 vid)
3488 {
3489 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3490 struct ixgbe_hw *hw = &adapter->hw;
3491
3492 /* remove VID from filter table */
3493 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3494 clear_bit(vid, adapter->active_vlans);
3495
3496 return 0;
3497 }
3498
3499 /**
3500 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3501 * @adapter: driver data
3502 */
3503 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3504 {
3505 struct ixgbe_hw *hw = &adapter->hw;
3506 u32 vlnctrl;
3507
3508 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3509 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3510 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3511 }
3512
3513 /**
3514 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3515 * @adapter: driver data
3516 */
3517 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3518 {
3519 struct ixgbe_hw *hw = &adapter->hw;
3520 u32 vlnctrl;
3521
3522 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3523 vlnctrl |= IXGBE_VLNCTRL_VFE;
3524 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3525 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3526 }
3527
3528 /**
3529 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3530 * @adapter: driver data
3531 */
3532 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3533 {
3534 struct ixgbe_hw *hw = &adapter->hw;
3535 u32 vlnctrl;
3536 int i, j;
3537
3538 switch (hw->mac.type) {
3539 case ixgbe_mac_82598EB:
3540 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3541 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3542 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3543 break;
3544 case ixgbe_mac_82599EB:
3545 case ixgbe_mac_X540:
3546 for (i = 0; i < adapter->num_rx_queues; i++) {
3547 j = adapter->rx_ring[i]->reg_idx;
3548 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3549 vlnctrl &= ~IXGBE_RXDCTL_VME;
3550 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3551 }
3552 break;
3553 default:
3554 break;
3555 }
3556 }
3557
3558 /**
3559 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3560 * @adapter: driver data
3561 */
3562 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3563 {
3564 struct ixgbe_hw *hw = &adapter->hw;
3565 u32 vlnctrl;
3566 int i, j;
3567
3568 switch (hw->mac.type) {
3569 case ixgbe_mac_82598EB:
3570 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3571 vlnctrl |= IXGBE_VLNCTRL_VME;
3572 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3573 break;
3574 case ixgbe_mac_82599EB:
3575 case ixgbe_mac_X540:
3576 for (i = 0; i < adapter->num_rx_queues; i++) {
3577 j = adapter->rx_ring[i]->reg_idx;
3578 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3579 vlnctrl |= IXGBE_RXDCTL_VME;
3580 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3581 }
3582 break;
3583 default:
3584 break;
3585 }
3586 }
3587
3588 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3589 {
3590 u16 vid;
3591
3592 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3593
3594 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3595 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3596 }
3597
3598 /**
3599 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3600 * @netdev: network interface device structure
3601 *
3602 * Writes unicast address list to the RAR table.
3603 * Returns: -ENOMEM on failure/insufficient address space
3604 * 0 on no addresses written
3605 * X on writing X addresses to the RAR table
3606 **/
3607 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3608 {
3609 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3610 struct ixgbe_hw *hw = &adapter->hw;
3611 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3612 int count = 0;
3613
3614 /* In SR-IOV mode significantly less RAR entries are available */
3615 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3616 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3617
3618 /* return ENOMEM indicating insufficient memory for addresses */
3619 if (netdev_uc_count(netdev) > rar_entries)
3620 return -ENOMEM;
3621
3622 if (!netdev_uc_empty(netdev)) {
3623 struct netdev_hw_addr *ha;
3624 /* return error if we do not support writing to RAR table */
3625 if (!hw->mac.ops.set_rar)
3626 return -ENOMEM;
3627
3628 netdev_for_each_uc_addr(ha, netdev) {
3629 if (!rar_entries)
3630 break;
3631 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3632 VMDQ_P(0), IXGBE_RAH_AV);
3633 count++;
3634 }
3635 }
3636 /* write the addresses in reverse order to avoid write combining */
3637 for (; rar_entries > 0 ; rar_entries--)
3638 hw->mac.ops.clear_rar(hw, rar_entries);
3639
3640 return count;
3641 }
3642
3643 /**
3644 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3645 * @netdev: network interface device structure
3646 *
3647 * The set_rx_method entry point is called whenever the unicast/multicast
3648 * address list or the network interface flags are updated. This routine is
3649 * responsible for configuring the hardware for proper unicast, multicast and
3650 * promiscuous mode.
3651 **/
3652 void ixgbe_set_rx_mode(struct net_device *netdev)
3653 {
3654 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3655 struct ixgbe_hw *hw = &adapter->hw;
3656 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3657 int count;
3658
3659 /* Check for Promiscuous and All Multicast modes */
3660
3661 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3662
3663 /* set all bits that we expect to always be set */
3664 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3665 fctrl |= IXGBE_FCTRL_BAM;
3666 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3667 fctrl |= IXGBE_FCTRL_PMCF;
3668
3669 /* clear the bits we are changing the status of */
3670 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3671
3672 if (netdev->flags & IFF_PROMISC) {
3673 hw->addr_ctrl.user_set_promisc = true;
3674 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3675 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3676 /* don't hardware filter vlans in promisc mode */
3677 ixgbe_vlan_filter_disable(adapter);
3678 } else {
3679 if (netdev->flags & IFF_ALLMULTI) {
3680 fctrl |= IXGBE_FCTRL_MPE;
3681 vmolr |= IXGBE_VMOLR_MPE;
3682 } else {
3683 /*
3684 * Write addresses to the MTA, if the attempt fails
3685 * then we should just turn on promiscuous mode so
3686 * that we can at least receive multicast traffic
3687 */
3688 hw->mac.ops.update_mc_addr_list(hw, netdev);
3689 vmolr |= IXGBE_VMOLR_ROMPE;
3690 }
3691 ixgbe_vlan_filter_enable(adapter);
3692 hw->addr_ctrl.user_set_promisc = false;
3693 }
3694
3695 /*
3696 * Write addresses to available RAR registers, if there is not
3697 * sufficient space to store all the addresses then enable
3698 * unicast promiscuous mode
3699 */
3700 count = ixgbe_write_uc_addr_list(netdev);
3701 if (count < 0) {
3702 fctrl |= IXGBE_FCTRL_UPE;
3703 vmolr |= IXGBE_VMOLR_ROPE;
3704 }
3705
3706 if (adapter->num_vfs)
3707 ixgbe_restore_vf_multicasts(adapter);
3708
3709 if (hw->mac.type != ixgbe_mac_82598EB) {
3710 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3711 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3712 IXGBE_VMOLR_ROPE);
3713 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3714 }
3715
3716 /* This is useful for sniffing bad packets. */
3717 if (adapter->netdev->features & NETIF_F_RXALL) {
3718 /* UPE and MPE will be handled by normal PROMISC logic
3719 * in e1000e_set_rx_mode */
3720 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3721 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3722 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3723
3724 fctrl &= ~(IXGBE_FCTRL_DPF);
3725 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3726 }
3727
3728 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3729
3730 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3731 ixgbe_vlan_strip_enable(adapter);
3732 else
3733 ixgbe_vlan_strip_disable(adapter);
3734 }
3735
3736 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3737 {
3738 int q_idx;
3739
3740 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3741 napi_enable(&adapter->q_vector[q_idx]->napi);
3742 }
3743
3744 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3745 {
3746 int q_idx;
3747
3748 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3749 napi_disable(&adapter->q_vector[q_idx]->napi);
3750 }
3751
3752 #ifdef CONFIG_IXGBE_DCB
3753 /**
3754 * ixgbe_configure_dcb - Configure DCB hardware
3755 * @adapter: ixgbe adapter struct
3756 *
3757 * This is called by the driver on open to configure the DCB hardware.
3758 * This is also called by the gennetlink interface when reconfiguring
3759 * the DCB state.
3760 */
3761 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3762 {
3763 struct ixgbe_hw *hw = &adapter->hw;
3764 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3765
3766 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3767 if (hw->mac.type == ixgbe_mac_82598EB)
3768 netif_set_gso_max_size(adapter->netdev, 65536);
3769 return;
3770 }
3771
3772 if (hw->mac.type == ixgbe_mac_82598EB)
3773 netif_set_gso_max_size(adapter->netdev, 32768);
3774
3775 #ifdef IXGBE_FCOE
3776 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3777 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3778 #endif
3779
3780 /* reconfigure the hardware */
3781 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3782 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3783 DCB_TX_CONFIG);
3784 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3785 DCB_RX_CONFIG);
3786 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3787 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3788 ixgbe_dcb_hw_ets(&adapter->hw,
3789 adapter->ixgbe_ieee_ets,
3790 max_frame);
3791 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3792 adapter->ixgbe_ieee_pfc->pfc_en,
3793 adapter->ixgbe_ieee_ets->prio_tc);
3794 }
3795
3796 /* Enable RSS Hash per TC */
3797 if (hw->mac.type != ixgbe_mac_82598EB) {
3798 u32 msb = 0;
3799 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3800
3801 while (rss_i) {
3802 msb++;
3803 rss_i >>= 1;
3804 }
3805
3806 /* write msb to all 8 TCs in one write */
3807 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3808 }
3809 }
3810 #endif
3811
3812 /* Additional bittime to account for IXGBE framing */
3813 #define IXGBE_ETH_FRAMING 20
3814
3815 /**
3816 * ixgbe_hpbthresh - calculate high water mark for flow control
3817 *
3818 * @adapter: board private structure to calculate for
3819 * @pb: packet buffer to calculate
3820 */
3821 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3822 {
3823 struct ixgbe_hw *hw = &adapter->hw;
3824 struct net_device *dev = adapter->netdev;
3825 int link, tc, kb, marker;
3826 u32 dv_id, rx_pba;
3827
3828 /* Calculate max LAN frame size */
3829 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3830
3831 #ifdef IXGBE_FCOE
3832 /* FCoE traffic class uses FCOE jumbo frames */
3833 if ((dev->features & NETIF_F_FCOE_MTU) &&
3834 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3835 (pb == ixgbe_fcoe_get_tc(adapter)))
3836 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3837
3838 #endif
3839 /* Calculate delay value for device */
3840 switch (hw->mac.type) {
3841 case ixgbe_mac_X540:
3842 dv_id = IXGBE_DV_X540(link, tc);
3843 break;
3844 default:
3845 dv_id = IXGBE_DV(link, tc);
3846 break;
3847 }
3848
3849 /* Loopback switch introduces additional latency */
3850 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3851 dv_id += IXGBE_B2BT(tc);
3852
3853 /* Delay value is calculated in bit times convert to KB */
3854 kb = IXGBE_BT2KB(dv_id);
3855 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3856
3857 marker = rx_pba - kb;
3858
3859 /* It is possible that the packet buffer is not large enough
3860 * to provide required headroom. In this case throw an error
3861 * to user and a do the best we can.
3862 */
3863 if (marker < 0) {
3864 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3865 "headroom to support flow control."
3866 "Decrease MTU or number of traffic classes\n", pb);
3867 marker = tc + 1;
3868 }
3869
3870 return marker;
3871 }
3872
3873 /**
3874 * ixgbe_lpbthresh - calculate low water mark for for flow control
3875 *
3876 * @adapter: board private structure to calculate for
3877 * @pb: packet buffer to calculate
3878 */
3879 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3880 {
3881 struct ixgbe_hw *hw = &adapter->hw;
3882 struct net_device *dev = adapter->netdev;
3883 int tc;
3884 u32 dv_id;
3885
3886 /* Calculate max LAN frame size */
3887 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3888
3889 /* Calculate delay value for device */
3890 switch (hw->mac.type) {
3891 case ixgbe_mac_X540:
3892 dv_id = IXGBE_LOW_DV_X540(tc);
3893 break;
3894 default:
3895 dv_id = IXGBE_LOW_DV(tc);
3896 break;
3897 }
3898
3899 /* Delay value is calculated in bit times convert to KB */
3900 return IXGBE_BT2KB(dv_id);
3901 }
3902
3903 /*
3904 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3905 */
3906 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3907 {
3908 struct ixgbe_hw *hw = &adapter->hw;
3909 int num_tc = netdev_get_num_tc(adapter->netdev);
3910 int i;
3911
3912 if (!num_tc)
3913 num_tc = 1;
3914
3915 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3916
3917 for (i = 0; i < num_tc; i++) {
3918 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3919
3920 /* Low water marks must not be larger than high water marks */
3921 if (hw->fc.low_water > hw->fc.high_water[i])
3922 hw->fc.low_water = 0;
3923 }
3924 }
3925
3926 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3927 {
3928 struct ixgbe_hw *hw = &adapter->hw;
3929 int hdrm;
3930 u8 tc = netdev_get_num_tc(adapter->netdev);
3931
3932 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3933 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3934 hdrm = 32 << adapter->fdir_pballoc;
3935 else
3936 hdrm = 0;
3937
3938 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3939 ixgbe_pbthresh_setup(adapter);
3940 }
3941
3942 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3943 {
3944 struct ixgbe_hw *hw = &adapter->hw;
3945 struct hlist_node *node2;
3946 struct ixgbe_fdir_filter *filter;
3947
3948 spin_lock(&adapter->fdir_perfect_lock);
3949
3950 if (!hlist_empty(&adapter->fdir_filter_list))
3951 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3952
3953 hlist_for_each_entry_safe(filter, node2,
3954 &adapter->fdir_filter_list, fdir_node) {
3955 ixgbe_fdir_write_perfect_filter_82599(hw,
3956 &filter->filter,
3957 filter->sw_idx,
3958 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3959 IXGBE_FDIR_DROP_QUEUE :
3960 adapter->rx_ring[filter->action]->reg_idx);
3961 }
3962
3963 spin_unlock(&adapter->fdir_perfect_lock);
3964 }
3965
3966 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3967 {
3968 struct ixgbe_hw *hw = &adapter->hw;
3969
3970 ixgbe_configure_pb(adapter);
3971 #ifdef CONFIG_IXGBE_DCB
3972 ixgbe_configure_dcb(adapter);
3973 #endif
3974 /*
3975 * We must restore virtualization before VLANs or else
3976 * the VLVF registers will not be populated
3977 */
3978 ixgbe_configure_virtualization(adapter);
3979
3980 ixgbe_set_rx_mode(adapter->netdev);
3981 ixgbe_restore_vlan(adapter);
3982
3983 switch (hw->mac.type) {
3984 case ixgbe_mac_82599EB:
3985 case ixgbe_mac_X540:
3986 hw->mac.ops.disable_rx_buff(hw);
3987 break;
3988 default:
3989 break;
3990 }
3991
3992 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3993 ixgbe_init_fdir_signature_82599(&adapter->hw,
3994 adapter->fdir_pballoc);
3995 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3996 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3997 adapter->fdir_pballoc);
3998 ixgbe_fdir_filter_restore(adapter);
3999 }
4000
4001 switch (hw->mac.type) {
4002 case ixgbe_mac_82599EB:
4003 case ixgbe_mac_X540:
4004 hw->mac.ops.enable_rx_buff(hw);
4005 break;
4006 default:
4007 break;
4008 }
4009
4010 #ifdef IXGBE_FCOE
4011 /* configure FCoE L2 filters, redirection table, and Rx control */
4012 ixgbe_configure_fcoe(adapter);
4013
4014 #endif /* IXGBE_FCOE */
4015 ixgbe_configure_tx(adapter);
4016 ixgbe_configure_rx(adapter);
4017 }
4018
4019 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4020 {
4021 switch (hw->phy.type) {
4022 case ixgbe_phy_sfp_avago:
4023 case ixgbe_phy_sfp_ftl:
4024 case ixgbe_phy_sfp_intel:
4025 case ixgbe_phy_sfp_unknown:
4026 case ixgbe_phy_sfp_passive_tyco:
4027 case ixgbe_phy_sfp_passive_unknown:
4028 case ixgbe_phy_sfp_active_unknown:
4029 case ixgbe_phy_sfp_ftl_active:
4030 return true;
4031 case ixgbe_phy_nl:
4032 if (hw->mac.type == ixgbe_mac_82598EB)
4033 return true;
4034 default:
4035 return false;
4036 }
4037 }
4038
4039 /**
4040 * ixgbe_sfp_link_config - set up SFP+ link
4041 * @adapter: pointer to private adapter struct
4042 **/
4043 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4044 {
4045 /*
4046 * We are assuming the worst case scenario here, and that
4047 * is that an SFP was inserted/removed after the reset
4048 * but before SFP detection was enabled. As such the best
4049 * solution is to just start searching as soon as we start
4050 */
4051 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4052 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4053
4054 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4055 }
4056
4057 /**
4058 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4059 * @hw: pointer to private hardware struct
4060 *
4061 * Returns 0 on success, negative on failure
4062 **/
4063 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4064 {
4065 u32 speed;
4066 bool autoneg, link_up = false;
4067 u32 ret = IXGBE_ERR_LINK_SETUP;
4068
4069 if (hw->mac.ops.check_link)
4070 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4071
4072 if (ret)
4073 goto link_cfg_out;
4074
4075 speed = hw->phy.autoneg_advertised;
4076 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4077 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4078 &autoneg);
4079 if (ret)
4080 goto link_cfg_out;
4081
4082 if (hw->mac.ops.setup_link)
4083 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4084 link_cfg_out:
4085 return ret;
4086 }
4087
4088 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4089 {
4090 struct ixgbe_hw *hw = &adapter->hw;
4091 u32 gpie = 0;
4092
4093 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4094 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4095 IXGBE_GPIE_OCD;
4096 gpie |= IXGBE_GPIE_EIAME;
4097 /*
4098 * use EIAM to auto-mask when MSI-X interrupt is asserted
4099 * this saves a register write for every interrupt
4100 */
4101 switch (hw->mac.type) {
4102 case ixgbe_mac_82598EB:
4103 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4104 break;
4105 case ixgbe_mac_82599EB:
4106 case ixgbe_mac_X540:
4107 default:
4108 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4109 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4110 break;
4111 }
4112 } else {
4113 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4114 * specifically only auto mask tx and rx interrupts */
4115 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4116 }
4117
4118 /* XXX: to interrupt immediately for EICS writes, enable this */
4119 /* gpie |= IXGBE_GPIE_EIMEN; */
4120
4121 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4122 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4123
4124 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4125 case IXGBE_82599_VMDQ_8Q_MASK:
4126 gpie |= IXGBE_GPIE_VTMODE_16;
4127 break;
4128 case IXGBE_82599_VMDQ_4Q_MASK:
4129 gpie |= IXGBE_GPIE_VTMODE_32;
4130 break;
4131 default:
4132 gpie |= IXGBE_GPIE_VTMODE_64;
4133 break;
4134 }
4135 }
4136
4137 /* Enable Thermal over heat sensor interrupt */
4138 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4139 switch (adapter->hw.mac.type) {
4140 case ixgbe_mac_82599EB:
4141 gpie |= IXGBE_SDP0_GPIEN;
4142 break;
4143 case ixgbe_mac_X540:
4144 gpie |= IXGBE_EIMS_TS;
4145 break;
4146 default:
4147 break;
4148 }
4149 }
4150
4151 /* Enable fan failure interrupt */
4152 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4153 gpie |= IXGBE_SDP1_GPIEN;
4154
4155 if (hw->mac.type == ixgbe_mac_82599EB) {
4156 gpie |= IXGBE_SDP1_GPIEN;
4157 gpie |= IXGBE_SDP2_GPIEN;
4158 }
4159
4160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4161 }
4162
4163 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4164 {
4165 struct ixgbe_hw *hw = &adapter->hw;
4166 int err;
4167 u32 ctrl_ext;
4168
4169 ixgbe_get_hw_control(adapter);
4170 ixgbe_setup_gpie(adapter);
4171
4172 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4173 ixgbe_configure_msix(adapter);
4174 else
4175 ixgbe_configure_msi_and_legacy(adapter);
4176
4177 /* enable the optics for 82599 SFP+ fiber */
4178 if (hw->mac.ops.enable_tx_laser)
4179 hw->mac.ops.enable_tx_laser(hw);
4180
4181 clear_bit(__IXGBE_DOWN, &adapter->state);
4182 ixgbe_napi_enable_all(adapter);
4183
4184 if (ixgbe_is_sfp(hw)) {
4185 ixgbe_sfp_link_config(adapter);
4186 } else {
4187 err = ixgbe_non_sfp_link_config(hw);
4188 if (err)
4189 e_err(probe, "link_config FAILED %d\n", err);
4190 }
4191
4192 /* clear any pending interrupts, may auto mask */
4193 IXGBE_READ_REG(hw, IXGBE_EICR);
4194 ixgbe_irq_enable(adapter, true, true);
4195
4196 /*
4197 * If this adapter has a fan, check to see if we had a failure
4198 * before we enabled the interrupt.
4199 */
4200 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4201 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4202 if (esdp & IXGBE_ESDP_SDP1)
4203 e_crit(drv, "Fan has stopped, replace the adapter\n");
4204 }
4205
4206 /* enable transmits */
4207 netif_tx_start_all_queues(adapter->netdev);
4208
4209 /* bring the link up in the watchdog, this could race with our first
4210 * link up interrupt but shouldn't be a problem */
4211 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4212 adapter->link_check_timeout = jiffies;
4213 mod_timer(&adapter->service_timer, jiffies);
4214
4215 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4216 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4217 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4218 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4219 }
4220
4221 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4222 {
4223 WARN_ON(in_interrupt());
4224 /* put off any impending NetWatchDogTimeout */
4225 adapter->netdev->trans_start = jiffies;
4226
4227 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4228 usleep_range(1000, 2000);
4229 ixgbe_down(adapter);
4230 /*
4231 * If SR-IOV enabled then wait a bit before bringing the adapter
4232 * back up to give the VFs time to respond to the reset. The
4233 * two second wait is based upon the watchdog timer cycle in
4234 * the VF driver.
4235 */
4236 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4237 msleep(2000);
4238 ixgbe_up(adapter);
4239 clear_bit(__IXGBE_RESETTING, &adapter->state);
4240 }
4241
4242 void ixgbe_up(struct ixgbe_adapter *adapter)
4243 {
4244 /* hardware has been reset, we need to reload some things */
4245 ixgbe_configure(adapter);
4246
4247 ixgbe_up_complete(adapter);
4248 }
4249
4250 void ixgbe_reset(struct ixgbe_adapter *adapter)
4251 {
4252 struct ixgbe_hw *hw = &adapter->hw;
4253 int err;
4254
4255 /* lock SFP init bit to prevent race conditions with the watchdog */
4256 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4257 usleep_range(1000, 2000);
4258
4259 /* clear all SFP and link config related flags while holding SFP_INIT */
4260 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4261 IXGBE_FLAG2_SFP_NEEDS_RESET);
4262 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4263
4264 err = hw->mac.ops.init_hw(hw);
4265 switch (err) {
4266 case 0:
4267 case IXGBE_ERR_SFP_NOT_PRESENT:
4268 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4269 break;
4270 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4271 e_dev_err("master disable timed out\n");
4272 break;
4273 case IXGBE_ERR_EEPROM_VERSION:
4274 /* We are running on a pre-production device, log a warning */
4275 e_dev_warn("This device is a pre-production adapter/LOM. "
4276 "Please be aware there may be issues associated with "
4277 "your hardware. If you are experiencing problems "
4278 "please contact your Intel or hardware "
4279 "representative who provided you with this "
4280 "hardware.\n");
4281 break;
4282 default:
4283 e_dev_err("Hardware Error: %d\n", err);
4284 }
4285
4286 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4287
4288 /* reprogram the RAR[0] in case user changed it. */
4289 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4290
4291 /* update SAN MAC vmdq pool selection */
4292 if (hw->mac.san_mac_rar_index)
4293 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4294
4295 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4296 ixgbe_ptp_reset(adapter);
4297 }
4298
4299 /**
4300 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4301 * @rx_ring: ring to free buffers from
4302 **/
4303 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4304 {
4305 struct device *dev = rx_ring->dev;
4306 unsigned long size;
4307 u16 i;
4308
4309 /* ring already cleared, nothing to do */
4310 if (!rx_ring->rx_buffer_info)
4311 return;
4312
4313 /* Free all the Rx ring sk_buffs */
4314 for (i = 0; i < rx_ring->count; i++) {
4315 struct ixgbe_rx_buffer *rx_buffer;
4316
4317 rx_buffer = &rx_ring->rx_buffer_info[i];
4318 if (rx_buffer->skb) {
4319 struct sk_buff *skb = rx_buffer->skb;
4320 if (IXGBE_CB(skb)->page_released) {
4321 dma_unmap_page(dev,
4322 IXGBE_CB(skb)->dma,
4323 ixgbe_rx_bufsz(rx_ring),
4324 DMA_FROM_DEVICE);
4325 IXGBE_CB(skb)->page_released = false;
4326 }
4327 dev_kfree_skb(skb);
4328 }
4329 rx_buffer->skb = NULL;
4330 if (rx_buffer->dma)
4331 dma_unmap_page(dev, rx_buffer->dma,
4332 ixgbe_rx_pg_size(rx_ring),
4333 DMA_FROM_DEVICE);
4334 rx_buffer->dma = 0;
4335 if (rx_buffer->page)
4336 __free_pages(rx_buffer->page,
4337 ixgbe_rx_pg_order(rx_ring));
4338 rx_buffer->page = NULL;
4339 }
4340
4341 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4342 memset(rx_ring->rx_buffer_info, 0, size);
4343
4344 /* Zero out the descriptor ring */
4345 memset(rx_ring->desc, 0, rx_ring->size);
4346
4347 rx_ring->next_to_alloc = 0;
4348 rx_ring->next_to_clean = 0;
4349 rx_ring->next_to_use = 0;
4350 }
4351
4352 /**
4353 * ixgbe_clean_tx_ring - Free Tx Buffers
4354 * @tx_ring: ring to be cleaned
4355 **/
4356 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4357 {
4358 struct ixgbe_tx_buffer *tx_buffer_info;
4359 unsigned long size;
4360 u16 i;
4361
4362 /* ring already cleared, nothing to do */
4363 if (!tx_ring->tx_buffer_info)
4364 return;
4365
4366 /* Free all the Tx ring sk_buffs */
4367 for (i = 0; i < tx_ring->count; i++) {
4368 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4369 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4370 }
4371
4372 netdev_tx_reset_queue(txring_txq(tx_ring));
4373
4374 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4375 memset(tx_ring->tx_buffer_info, 0, size);
4376
4377 /* Zero out the descriptor ring */
4378 memset(tx_ring->desc, 0, tx_ring->size);
4379
4380 tx_ring->next_to_use = 0;
4381 tx_ring->next_to_clean = 0;
4382 }
4383
4384 /**
4385 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4386 * @adapter: board private structure
4387 **/
4388 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4389 {
4390 int i;
4391
4392 for (i = 0; i < adapter->num_rx_queues; i++)
4393 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4394 }
4395
4396 /**
4397 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4398 * @adapter: board private structure
4399 **/
4400 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4401 {
4402 int i;
4403
4404 for (i = 0; i < adapter->num_tx_queues; i++)
4405 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4406 }
4407
4408 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4409 {
4410 struct hlist_node *node2;
4411 struct ixgbe_fdir_filter *filter;
4412
4413 spin_lock(&adapter->fdir_perfect_lock);
4414
4415 hlist_for_each_entry_safe(filter, node2,
4416 &adapter->fdir_filter_list, fdir_node) {
4417 hlist_del(&filter->fdir_node);
4418 kfree(filter);
4419 }
4420 adapter->fdir_filter_count = 0;
4421
4422 spin_unlock(&adapter->fdir_perfect_lock);
4423 }
4424
4425 void ixgbe_down(struct ixgbe_adapter *adapter)
4426 {
4427 struct net_device *netdev = adapter->netdev;
4428 struct ixgbe_hw *hw = &adapter->hw;
4429 u32 rxctrl;
4430 int i;
4431
4432 /* signal that we are down to the interrupt handler */
4433 set_bit(__IXGBE_DOWN, &adapter->state);
4434
4435 /* disable receives */
4436 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4437 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4438
4439 /* disable all enabled rx queues */
4440 for (i = 0; i < adapter->num_rx_queues; i++)
4441 /* this call also flushes the previous write */
4442 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4443
4444 usleep_range(10000, 20000);
4445
4446 netif_tx_stop_all_queues(netdev);
4447
4448 /* call carrier off first to avoid false dev_watchdog timeouts */
4449 netif_carrier_off(netdev);
4450 netif_tx_disable(netdev);
4451
4452 ixgbe_irq_disable(adapter);
4453
4454 ixgbe_napi_disable_all(adapter);
4455
4456 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4457 IXGBE_FLAG2_RESET_REQUESTED);
4458 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4459
4460 del_timer_sync(&adapter->service_timer);
4461
4462 if (adapter->num_vfs) {
4463 /* Clear EITR Select mapping */
4464 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4465
4466 /* Mark all the VFs as inactive */
4467 for (i = 0 ; i < adapter->num_vfs; i++)
4468 adapter->vfinfo[i].clear_to_send = false;
4469
4470 /* ping all the active vfs to let them know we are going down */
4471 ixgbe_ping_all_vfs(adapter);
4472
4473 /* Disable all VFTE/VFRE TX/RX */
4474 ixgbe_disable_tx_rx(adapter);
4475 }
4476
4477 /* disable transmits in the hardware now that interrupts are off */
4478 for (i = 0; i < adapter->num_tx_queues; i++) {
4479 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4480 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4481 }
4482
4483 /* Disable the Tx DMA engine on 82599 and X540 */
4484 switch (hw->mac.type) {
4485 case ixgbe_mac_82599EB:
4486 case ixgbe_mac_X540:
4487 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4488 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4489 ~IXGBE_DMATXCTL_TE));
4490 break;
4491 default:
4492 break;
4493 }
4494
4495 if (!pci_channel_offline(adapter->pdev))
4496 ixgbe_reset(adapter);
4497
4498 /* power down the optics for 82599 SFP+ fiber */
4499 if (hw->mac.ops.disable_tx_laser)
4500 hw->mac.ops.disable_tx_laser(hw);
4501
4502 ixgbe_clean_all_tx_rings(adapter);
4503 ixgbe_clean_all_rx_rings(adapter);
4504
4505 #ifdef CONFIG_IXGBE_DCA
4506 /* since we reset the hardware DCA settings were cleared */
4507 ixgbe_setup_dca(adapter);
4508 #endif
4509 }
4510
4511 /**
4512 * ixgbe_tx_timeout - Respond to a Tx Hang
4513 * @netdev: network interface device structure
4514 **/
4515 static void ixgbe_tx_timeout(struct net_device *netdev)
4516 {
4517 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4518
4519 /* Do the reset outside of interrupt context */
4520 ixgbe_tx_timeout_reset(adapter);
4521 }
4522
4523 /**
4524 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4525 * @adapter: board private structure to initialize
4526 *
4527 * ixgbe_sw_init initializes the Adapter private data structure.
4528 * Fields are initialized based on PCI device information and
4529 * OS network device settings (MTU size).
4530 **/
4531 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4532 {
4533 struct ixgbe_hw *hw = &adapter->hw;
4534 struct pci_dev *pdev = adapter->pdev;
4535 unsigned int rss, fdir;
4536 u32 fwsm;
4537 #ifdef CONFIG_IXGBE_DCB
4538 int j;
4539 struct tc_configuration *tc;
4540 #endif
4541
4542 /* PCI config space info */
4543
4544 hw->vendor_id = pdev->vendor;
4545 hw->device_id = pdev->device;
4546 hw->revision_id = pdev->revision;
4547 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4548 hw->subsystem_device_id = pdev->subsystem_device;
4549
4550 /* Set common capability flags and settings */
4551 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4552 adapter->ring_feature[RING_F_RSS].limit = rss;
4553 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4554 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4555 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4556 adapter->atr_sample_rate = 20;
4557 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4558 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4559 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4560 #ifdef CONFIG_IXGBE_DCA
4561 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4562 #endif
4563 #ifdef IXGBE_FCOE
4564 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4565 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4566 #ifdef CONFIG_IXGBE_DCB
4567 /* Default traffic class to use for FCoE */
4568 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4569 #endif /* CONFIG_IXGBE_DCB */
4570 #endif /* IXGBE_FCOE */
4571
4572 /* Set MAC specific capability flags and exceptions */
4573 switch (hw->mac.type) {
4574 case ixgbe_mac_82598EB:
4575 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4576 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4577
4578 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4579 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4580
4581 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4582 adapter->ring_feature[RING_F_FDIR].limit = 0;
4583 adapter->atr_sample_rate = 0;
4584 adapter->fdir_pballoc = 0;
4585 #ifdef IXGBE_FCOE
4586 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4587 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4588 #ifdef CONFIG_IXGBE_DCB
4589 adapter->fcoe.up = 0;
4590 #endif /* IXGBE_DCB */
4591 #endif /* IXGBE_FCOE */
4592 break;
4593 case ixgbe_mac_82599EB:
4594 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4595 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4596 break;
4597 case ixgbe_mac_X540:
4598 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4599 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4600 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4601 break;
4602 default:
4603 break;
4604 }
4605
4606 #ifdef IXGBE_FCOE
4607 /* FCoE support exists, always init the FCoE lock */
4608 spin_lock_init(&adapter->fcoe.lock);
4609
4610 #endif
4611 /* n-tuple support exists, always init our spinlock */
4612 spin_lock_init(&adapter->fdir_perfect_lock);
4613
4614 #ifdef CONFIG_IXGBE_DCB
4615 switch (hw->mac.type) {
4616 case ixgbe_mac_X540:
4617 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4618 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4619 break;
4620 default:
4621 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4622 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4623 break;
4624 }
4625
4626 /* Configure DCB traffic classes */
4627 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4628 tc = &adapter->dcb_cfg.tc_config[j];
4629 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4630 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4631 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4632 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4633 tc->dcb_pfc = pfc_disabled;
4634 }
4635
4636 /* Initialize default user to priority mapping, UPx->TC0 */
4637 tc = &adapter->dcb_cfg.tc_config[0];
4638 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4639 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4640
4641 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4642 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4643 adapter->dcb_cfg.pfc_mode_enable = false;
4644 adapter->dcb_set_bitmap = 0x00;
4645 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4646 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4647 sizeof(adapter->temp_dcb_cfg));
4648
4649 #endif
4650
4651 /* default flow control settings */
4652 hw->fc.requested_mode = ixgbe_fc_full;
4653 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4654 ixgbe_pbthresh_setup(adapter);
4655 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4656 hw->fc.send_xon = true;
4657 hw->fc.disable_fc_autoneg =
4658 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4659
4660 #ifdef CONFIG_PCI_IOV
4661 /* assign number of SR-IOV VFs */
4662 if (hw->mac.type != ixgbe_mac_82598EB)
4663 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4664
4665 #endif
4666 /* enable itr by default in dynamic mode */
4667 adapter->rx_itr_setting = 1;
4668 adapter->tx_itr_setting = 1;
4669
4670 /* set default ring sizes */
4671 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4672 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4673
4674 /* set default work limits */
4675 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4676
4677 /* initialize eeprom parameters */
4678 if (ixgbe_init_eeprom_params_generic(hw)) {
4679 e_dev_err("EEPROM initialization failed\n");
4680 return -EIO;
4681 }
4682
4683 set_bit(__IXGBE_DOWN, &adapter->state);
4684
4685 return 0;
4686 }
4687
4688 /**
4689 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4690 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4691 *
4692 * Return 0 on success, negative on failure
4693 **/
4694 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4695 {
4696 struct device *dev = tx_ring->dev;
4697 int orig_node = dev_to_node(dev);
4698 int numa_node = -1;
4699 int size;
4700
4701 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4702
4703 if (tx_ring->q_vector)
4704 numa_node = tx_ring->q_vector->numa_node;
4705
4706 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4707 if (!tx_ring->tx_buffer_info)
4708 tx_ring->tx_buffer_info = vzalloc(size);
4709 if (!tx_ring->tx_buffer_info)
4710 goto err;
4711
4712 /* round up to nearest 4K */
4713 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4714 tx_ring->size = ALIGN(tx_ring->size, 4096);
4715
4716 set_dev_node(dev, numa_node);
4717 tx_ring->desc = dma_alloc_coherent(dev,
4718 tx_ring->size,
4719 &tx_ring->dma,
4720 GFP_KERNEL);
4721 set_dev_node(dev, orig_node);
4722 if (!tx_ring->desc)
4723 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4724 &tx_ring->dma, GFP_KERNEL);
4725 if (!tx_ring->desc)
4726 goto err;
4727
4728 tx_ring->next_to_use = 0;
4729 tx_ring->next_to_clean = 0;
4730 return 0;
4731
4732 err:
4733 vfree(tx_ring->tx_buffer_info);
4734 tx_ring->tx_buffer_info = NULL;
4735 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4736 return -ENOMEM;
4737 }
4738
4739 /**
4740 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4741 * @adapter: board private structure
4742 *
4743 * If this function returns with an error, then it's possible one or
4744 * more of the rings is populated (while the rest are not). It is the
4745 * callers duty to clean those orphaned rings.
4746 *
4747 * Return 0 on success, negative on failure
4748 **/
4749 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4750 {
4751 int i, err = 0;
4752
4753 for (i = 0; i < adapter->num_tx_queues; i++) {
4754 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4755 if (!err)
4756 continue;
4757
4758 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4759 goto err_setup_tx;
4760 }
4761
4762 return 0;
4763 err_setup_tx:
4764 /* rewind the index freeing the rings as we go */
4765 while (i--)
4766 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4767 return err;
4768 }
4769
4770 /**
4771 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4772 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4773 *
4774 * Returns 0 on success, negative on failure
4775 **/
4776 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4777 {
4778 struct device *dev = rx_ring->dev;
4779 int orig_node = dev_to_node(dev);
4780 int numa_node = -1;
4781 int size;
4782
4783 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4784
4785 if (rx_ring->q_vector)
4786 numa_node = rx_ring->q_vector->numa_node;
4787
4788 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4789 if (!rx_ring->rx_buffer_info)
4790 rx_ring->rx_buffer_info = vzalloc(size);
4791 if (!rx_ring->rx_buffer_info)
4792 goto err;
4793
4794 /* Round up to nearest 4K */
4795 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4796 rx_ring->size = ALIGN(rx_ring->size, 4096);
4797
4798 set_dev_node(dev, numa_node);
4799 rx_ring->desc = dma_alloc_coherent(dev,
4800 rx_ring->size,
4801 &rx_ring->dma,
4802 GFP_KERNEL);
4803 set_dev_node(dev, orig_node);
4804 if (!rx_ring->desc)
4805 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4806 &rx_ring->dma, GFP_KERNEL);
4807 if (!rx_ring->desc)
4808 goto err;
4809
4810 rx_ring->next_to_clean = 0;
4811 rx_ring->next_to_use = 0;
4812
4813 return 0;
4814 err:
4815 vfree(rx_ring->rx_buffer_info);
4816 rx_ring->rx_buffer_info = NULL;
4817 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4818 return -ENOMEM;
4819 }
4820
4821 /**
4822 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4823 * @adapter: board private structure
4824 *
4825 * If this function returns with an error, then it's possible one or
4826 * more of the rings is populated (while the rest are not). It is the
4827 * callers duty to clean those orphaned rings.
4828 *
4829 * Return 0 on success, negative on failure
4830 **/
4831 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4832 {
4833 int i, err = 0;
4834
4835 for (i = 0; i < adapter->num_rx_queues; i++) {
4836 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4837 if (!err)
4838 continue;
4839
4840 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4841 goto err_setup_rx;
4842 }
4843
4844 #ifdef IXGBE_FCOE
4845 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4846 if (!err)
4847 #endif
4848 return 0;
4849 err_setup_rx:
4850 /* rewind the index freeing the rings as we go */
4851 while (i--)
4852 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4853 return err;
4854 }
4855
4856 /**
4857 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4858 * @tx_ring: Tx descriptor ring for a specific queue
4859 *
4860 * Free all transmit software resources
4861 **/
4862 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4863 {
4864 ixgbe_clean_tx_ring(tx_ring);
4865
4866 vfree(tx_ring->tx_buffer_info);
4867 tx_ring->tx_buffer_info = NULL;
4868
4869 /* if not set, then don't free */
4870 if (!tx_ring->desc)
4871 return;
4872
4873 dma_free_coherent(tx_ring->dev, tx_ring->size,
4874 tx_ring->desc, tx_ring->dma);
4875
4876 tx_ring->desc = NULL;
4877 }
4878
4879 /**
4880 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4881 * @adapter: board private structure
4882 *
4883 * Free all transmit software resources
4884 **/
4885 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4886 {
4887 int i;
4888
4889 for (i = 0; i < adapter->num_tx_queues; i++)
4890 if (adapter->tx_ring[i]->desc)
4891 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4892 }
4893
4894 /**
4895 * ixgbe_free_rx_resources - Free Rx Resources
4896 * @rx_ring: ring to clean the resources from
4897 *
4898 * Free all receive software resources
4899 **/
4900 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4901 {
4902 ixgbe_clean_rx_ring(rx_ring);
4903
4904 vfree(rx_ring->rx_buffer_info);
4905 rx_ring->rx_buffer_info = NULL;
4906
4907 /* if not set, then don't free */
4908 if (!rx_ring->desc)
4909 return;
4910
4911 dma_free_coherent(rx_ring->dev, rx_ring->size,
4912 rx_ring->desc, rx_ring->dma);
4913
4914 rx_ring->desc = NULL;
4915 }
4916
4917 /**
4918 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4919 * @adapter: board private structure
4920 *
4921 * Free all receive software resources
4922 **/
4923 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4924 {
4925 int i;
4926
4927 #ifdef IXGBE_FCOE
4928 ixgbe_free_fcoe_ddp_resources(adapter);
4929
4930 #endif
4931 for (i = 0; i < adapter->num_rx_queues; i++)
4932 if (adapter->rx_ring[i]->desc)
4933 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4934 }
4935
4936 /**
4937 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4938 * @netdev: network interface device structure
4939 * @new_mtu: new value for maximum frame size
4940 *
4941 * Returns 0 on success, negative on failure
4942 **/
4943 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4944 {
4945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4946 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4947
4948 /* MTU < 68 is an error and causes problems on some kernels */
4949 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4950 return -EINVAL;
4951
4952 /*
4953 * For 82599EB we cannot allow legacy VFs to enable their receive
4954 * paths when MTU greater than 1500 is configured. So display a
4955 * warning that legacy VFs will be disabled.
4956 */
4957 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4958 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4959 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4960 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4961
4962 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4963
4964 /* must set new MTU before calling down or up */
4965 netdev->mtu = new_mtu;
4966
4967 if (netif_running(netdev))
4968 ixgbe_reinit_locked(adapter);
4969
4970 return 0;
4971 }
4972
4973 /**
4974 * ixgbe_open - Called when a network interface is made active
4975 * @netdev: network interface device structure
4976 *
4977 * Returns 0 on success, negative value on failure
4978 *
4979 * The open entry point is called when a network interface is made
4980 * active by the system (IFF_UP). At this point all resources needed
4981 * for transmit and receive operations are allocated, the interrupt
4982 * handler is registered with the OS, the watchdog timer is started,
4983 * and the stack is notified that the interface is ready.
4984 **/
4985 static int ixgbe_open(struct net_device *netdev)
4986 {
4987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4988 int err;
4989
4990 /* disallow open during test */
4991 if (test_bit(__IXGBE_TESTING, &adapter->state))
4992 return -EBUSY;
4993
4994 netif_carrier_off(netdev);
4995
4996 /* allocate transmit descriptors */
4997 err = ixgbe_setup_all_tx_resources(adapter);
4998 if (err)
4999 goto err_setup_tx;
5000
5001 /* allocate receive descriptors */
5002 err = ixgbe_setup_all_rx_resources(adapter);
5003 if (err)
5004 goto err_setup_rx;
5005
5006 ixgbe_configure(adapter);
5007
5008 err = ixgbe_request_irq(adapter);
5009 if (err)
5010 goto err_req_irq;
5011
5012 /* Notify the stack of the actual queue counts. */
5013 err = netif_set_real_num_tx_queues(netdev,
5014 adapter->num_rx_pools > 1 ? 1 :
5015 adapter->num_tx_queues);
5016 if (err)
5017 goto err_set_queues;
5018
5019
5020 err = netif_set_real_num_rx_queues(netdev,
5021 adapter->num_rx_pools > 1 ? 1 :
5022 adapter->num_rx_queues);
5023 if (err)
5024 goto err_set_queues;
5025
5026 ixgbe_ptp_init(adapter);
5027
5028 ixgbe_up_complete(adapter);
5029
5030 return 0;
5031
5032 err_set_queues:
5033 ixgbe_free_irq(adapter);
5034 err_req_irq:
5035 ixgbe_free_all_rx_resources(adapter);
5036 err_setup_rx:
5037 ixgbe_free_all_tx_resources(adapter);
5038 err_setup_tx:
5039 ixgbe_reset(adapter);
5040
5041 return err;
5042 }
5043
5044 /**
5045 * ixgbe_close - Disables a network interface
5046 * @netdev: network interface device structure
5047 *
5048 * Returns 0, this is not allowed to fail
5049 *
5050 * The close entry point is called when an interface is de-activated
5051 * by the OS. The hardware is still under the drivers control, but
5052 * needs to be disabled. A global MAC reset is issued to stop the
5053 * hardware, and all transmit and receive resources are freed.
5054 **/
5055 static int ixgbe_close(struct net_device *netdev)
5056 {
5057 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5058
5059 ixgbe_ptp_stop(adapter);
5060
5061 ixgbe_down(adapter);
5062 ixgbe_free_irq(adapter);
5063
5064 ixgbe_fdir_filter_exit(adapter);
5065
5066 ixgbe_free_all_tx_resources(adapter);
5067 ixgbe_free_all_rx_resources(adapter);
5068
5069 ixgbe_release_hw_control(adapter);
5070
5071 return 0;
5072 }
5073
5074 #ifdef CONFIG_PM
5075 static int ixgbe_resume(struct pci_dev *pdev)
5076 {
5077 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5078 struct net_device *netdev = adapter->netdev;
5079 u32 err;
5080
5081 pci_set_power_state(pdev, PCI_D0);
5082 pci_restore_state(pdev);
5083 /*
5084 * pci_restore_state clears dev->state_saved so call
5085 * pci_save_state to restore it.
5086 */
5087 pci_save_state(pdev);
5088
5089 err = pci_enable_device_mem(pdev);
5090 if (err) {
5091 e_dev_err("Cannot enable PCI device from suspend\n");
5092 return err;
5093 }
5094 pci_set_master(pdev);
5095
5096 pci_wake_from_d3(pdev, false);
5097
5098 ixgbe_reset(adapter);
5099
5100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5101
5102 rtnl_lock();
5103 err = ixgbe_init_interrupt_scheme(adapter);
5104 if (!err && netif_running(netdev))
5105 err = ixgbe_open(netdev);
5106
5107 rtnl_unlock();
5108
5109 if (err)
5110 return err;
5111
5112 netif_device_attach(netdev);
5113
5114 return 0;
5115 }
5116 #endif /* CONFIG_PM */
5117
5118 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5119 {
5120 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5121 struct net_device *netdev = adapter->netdev;
5122 struct ixgbe_hw *hw = &adapter->hw;
5123 u32 ctrl, fctrl;
5124 u32 wufc = adapter->wol;
5125 #ifdef CONFIG_PM
5126 int retval = 0;
5127 #endif
5128
5129 netif_device_detach(netdev);
5130
5131 rtnl_lock();
5132 if (netif_running(netdev)) {
5133 ixgbe_down(adapter);
5134 ixgbe_free_irq(adapter);
5135 ixgbe_free_all_tx_resources(adapter);
5136 ixgbe_free_all_rx_resources(adapter);
5137 }
5138 rtnl_unlock();
5139
5140 ixgbe_clear_interrupt_scheme(adapter);
5141
5142 #ifdef CONFIG_PM
5143 retval = pci_save_state(pdev);
5144 if (retval)
5145 return retval;
5146
5147 #endif
5148 if (wufc) {
5149 ixgbe_set_rx_mode(netdev);
5150
5151 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5152 if (hw->mac.ops.enable_tx_laser)
5153 hw->mac.ops.enable_tx_laser(hw);
5154
5155 /* turn on all-multi mode if wake on multicast is enabled */
5156 if (wufc & IXGBE_WUFC_MC) {
5157 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5158 fctrl |= IXGBE_FCTRL_MPE;
5159 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5160 }
5161
5162 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5163 ctrl |= IXGBE_CTRL_GIO_DIS;
5164 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5165
5166 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5167 } else {
5168 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5169 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5170 }
5171
5172 switch (hw->mac.type) {
5173 case ixgbe_mac_82598EB:
5174 pci_wake_from_d3(pdev, false);
5175 break;
5176 case ixgbe_mac_82599EB:
5177 case ixgbe_mac_X540:
5178 pci_wake_from_d3(pdev, !!wufc);
5179 break;
5180 default:
5181 break;
5182 }
5183
5184 *enable_wake = !!wufc;
5185
5186 ixgbe_release_hw_control(adapter);
5187
5188 pci_disable_device(pdev);
5189
5190 return 0;
5191 }
5192
5193 #ifdef CONFIG_PM
5194 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5195 {
5196 int retval;
5197 bool wake;
5198
5199 retval = __ixgbe_shutdown(pdev, &wake);
5200 if (retval)
5201 return retval;
5202
5203 if (wake) {
5204 pci_prepare_to_sleep(pdev);
5205 } else {
5206 pci_wake_from_d3(pdev, false);
5207 pci_set_power_state(pdev, PCI_D3hot);
5208 }
5209
5210 return 0;
5211 }
5212 #endif /* CONFIG_PM */
5213
5214 static void ixgbe_shutdown(struct pci_dev *pdev)
5215 {
5216 bool wake;
5217
5218 __ixgbe_shutdown(pdev, &wake);
5219
5220 if (system_state == SYSTEM_POWER_OFF) {
5221 pci_wake_from_d3(pdev, wake);
5222 pci_set_power_state(pdev, PCI_D3hot);
5223 }
5224 }
5225
5226 /**
5227 * ixgbe_update_stats - Update the board statistics counters.
5228 * @adapter: board private structure
5229 **/
5230 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5231 {
5232 struct net_device *netdev = adapter->netdev;
5233 struct ixgbe_hw *hw = &adapter->hw;
5234 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5235 u64 total_mpc = 0;
5236 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5237 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5238 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5239 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5240
5241 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5242 test_bit(__IXGBE_RESETTING, &adapter->state))
5243 return;
5244
5245 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5246 u64 rsc_count = 0;
5247 u64 rsc_flush = 0;
5248 for (i = 0; i < adapter->num_rx_queues; i++) {
5249 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5250 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5251 }
5252 adapter->rsc_total_count = rsc_count;
5253 adapter->rsc_total_flush = rsc_flush;
5254 }
5255
5256 for (i = 0; i < adapter->num_rx_queues; i++) {
5257 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5258 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5259 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5260 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5261 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5262 bytes += rx_ring->stats.bytes;
5263 packets += rx_ring->stats.packets;
5264 }
5265 adapter->non_eop_descs = non_eop_descs;
5266 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5267 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5268 adapter->hw_csum_rx_error = hw_csum_rx_error;
5269 netdev->stats.rx_bytes = bytes;
5270 netdev->stats.rx_packets = packets;
5271
5272 bytes = 0;
5273 packets = 0;
5274 /* gather some stats to the adapter struct that are per queue */
5275 for (i = 0; i < adapter->num_tx_queues; i++) {
5276 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5277 restart_queue += tx_ring->tx_stats.restart_queue;
5278 tx_busy += tx_ring->tx_stats.tx_busy;
5279 bytes += tx_ring->stats.bytes;
5280 packets += tx_ring->stats.packets;
5281 }
5282 adapter->restart_queue = restart_queue;
5283 adapter->tx_busy = tx_busy;
5284 netdev->stats.tx_bytes = bytes;
5285 netdev->stats.tx_packets = packets;
5286
5287 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5288
5289 /* 8 register reads */
5290 for (i = 0; i < 8; i++) {
5291 /* for packet buffers not used, the register should read 0 */
5292 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5293 missed_rx += mpc;
5294 hwstats->mpc[i] += mpc;
5295 total_mpc += hwstats->mpc[i];
5296 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5297 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5298 switch (hw->mac.type) {
5299 case ixgbe_mac_82598EB:
5300 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5301 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5302 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5303 hwstats->pxonrxc[i] +=
5304 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5305 break;
5306 case ixgbe_mac_82599EB:
5307 case ixgbe_mac_X540:
5308 hwstats->pxonrxc[i] +=
5309 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5310 break;
5311 default:
5312 break;
5313 }
5314 }
5315
5316 /*16 register reads */
5317 for (i = 0; i < 16; i++) {
5318 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5319 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5320 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5321 (hw->mac.type == ixgbe_mac_X540)) {
5322 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5323 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5324 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5325 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5326 }
5327 }
5328
5329 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5330 /* work around hardware counting issue */
5331 hwstats->gprc -= missed_rx;
5332
5333 ixgbe_update_xoff_received(adapter);
5334
5335 /* 82598 hardware only has a 32 bit counter in the high register */
5336 switch (hw->mac.type) {
5337 case ixgbe_mac_82598EB:
5338 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5339 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5340 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5341 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5342 break;
5343 case ixgbe_mac_X540:
5344 /* OS2BMC stats are X540 only*/
5345 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5346 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5347 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5348 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5349 case ixgbe_mac_82599EB:
5350 for (i = 0; i < 16; i++)
5351 adapter->hw_rx_no_dma_resources +=
5352 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5353 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5354 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5355 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5356 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5357 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5358 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5359 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5360 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5361 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5362 #ifdef IXGBE_FCOE
5363 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5364 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5365 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5366 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5367 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5368 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5369 /* Add up per cpu counters for total ddp aloc fail */
5370 if (adapter->fcoe.ddp_pool) {
5371 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5372 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5373 unsigned int cpu;
5374 u64 noddp = 0, noddp_ext_buff = 0;
5375 for_each_possible_cpu(cpu) {
5376 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5377 noddp += ddp_pool->noddp;
5378 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5379 }
5380 hwstats->fcoe_noddp = noddp;
5381 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5382 }
5383 #endif /* IXGBE_FCOE */
5384 break;
5385 default:
5386 break;
5387 }
5388 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5389 hwstats->bprc += bprc;
5390 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5391 if (hw->mac.type == ixgbe_mac_82598EB)
5392 hwstats->mprc -= bprc;
5393 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5394 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5395 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5396 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5397 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5398 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5399 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5400 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5401 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5402 hwstats->lxontxc += lxon;
5403 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5404 hwstats->lxofftxc += lxoff;
5405 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5406 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5407 /*
5408 * 82598 errata - tx of flow control packets is included in tx counters
5409 */
5410 xon_off_tot = lxon + lxoff;
5411 hwstats->gptc -= xon_off_tot;
5412 hwstats->mptc -= xon_off_tot;
5413 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5414 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5415 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5416 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5417 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5418 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5419 hwstats->ptc64 -= xon_off_tot;
5420 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5421 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5422 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5423 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5424 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5425 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5426
5427 /* Fill out the OS statistics structure */
5428 netdev->stats.multicast = hwstats->mprc;
5429
5430 /* Rx Errors */
5431 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5432 netdev->stats.rx_dropped = 0;
5433 netdev->stats.rx_length_errors = hwstats->rlec;
5434 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5435 netdev->stats.rx_missed_errors = total_mpc;
5436 }
5437
5438 /**
5439 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5440 * @adapter: pointer to the device adapter structure
5441 **/
5442 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5443 {
5444 struct ixgbe_hw *hw = &adapter->hw;
5445 int i;
5446
5447 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5448 return;
5449
5450 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5451
5452 /* if interface is down do nothing */
5453 if (test_bit(__IXGBE_DOWN, &adapter->state))
5454 return;
5455
5456 /* do nothing if we are not using signature filters */
5457 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5458 return;
5459
5460 adapter->fdir_overflow++;
5461
5462 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5463 for (i = 0; i < adapter->num_tx_queues; i++)
5464 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5465 &(adapter->tx_ring[i]->state));
5466 /* re-enable flow director interrupts */
5467 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5468 } else {
5469 e_err(probe, "failed to finish FDIR re-initialization, "
5470 "ignored adding FDIR ATR filters\n");
5471 }
5472 }
5473
5474 /**
5475 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5476 * @adapter: pointer to the device adapter structure
5477 *
5478 * This function serves two purposes. First it strobes the interrupt lines
5479 * in order to make certain interrupts are occurring. Secondly it sets the
5480 * bits needed to check for TX hangs. As a result we should immediately
5481 * determine if a hang has occurred.
5482 */
5483 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5484 {
5485 struct ixgbe_hw *hw = &adapter->hw;
5486 u64 eics = 0;
5487 int i;
5488
5489 /* If we're down or resetting, just bail */
5490 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5491 test_bit(__IXGBE_RESETTING, &adapter->state))
5492 return;
5493
5494 /* Force detection of hung controller */
5495 if (netif_carrier_ok(adapter->netdev)) {
5496 for (i = 0; i < adapter->num_tx_queues; i++)
5497 set_check_for_tx_hang(adapter->tx_ring[i]);
5498 }
5499
5500 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5501 /*
5502 * for legacy and MSI interrupts don't set any bits
5503 * that are enabled for EIAM, because this operation
5504 * would set *both* EIMS and EICS for any bit in EIAM
5505 */
5506 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5507 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5508 } else {
5509 /* get one bit for every active tx/rx interrupt vector */
5510 for (i = 0; i < adapter->num_q_vectors; i++) {
5511 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5512 if (qv->rx.ring || qv->tx.ring)
5513 eics |= ((u64)1 << i);
5514 }
5515 }
5516
5517 /* Cause software interrupt to ensure rings are cleaned */
5518 ixgbe_irq_rearm_queues(adapter, eics);
5519
5520 }
5521
5522 /**
5523 * ixgbe_watchdog_update_link - update the link status
5524 * @adapter: pointer to the device adapter structure
5525 * @link_speed: pointer to a u32 to store the link_speed
5526 **/
5527 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5528 {
5529 struct ixgbe_hw *hw = &adapter->hw;
5530 u32 link_speed = adapter->link_speed;
5531 bool link_up = adapter->link_up;
5532 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5533
5534 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5535 return;
5536
5537 if (hw->mac.ops.check_link) {
5538 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5539 } else {
5540 /* always assume link is up, if no check link function */
5541 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5542 link_up = true;
5543 }
5544
5545 if (adapter->ixgbe_ieee_pfc)
5546 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5547
5548 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5549 hw->mac.ops.fc_enable(hw);
5550 ixgbe_set_rx_drop_en(adapter);
5551 }
5552
5553 if (link_up ||
5554 time_after(jiffies, (adapter->link_check_timeout +
5555 IXGBE_TRY_LINK_TIMEOUT))) {
5556 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5557 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5558 IXGBE_WRITE_FLUSH(hw);
5559 }
5560
5561 adapter->link_up = link_up;
5562 adapter->link_speed = link_speed;
5563 }
5564
5565 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5566 {
5567 #ifdef CONFIG_IXGBE_DCB
5568 struct net_device *netdev = adapter->netdev;
5569 struct dcb_app app = {
5570 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5571 .protocol = 0,
5572 };
5573 u8 up = 0;
5574
5575 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5576 up = dcb_ieee_getapp_mask(netdev, &app);
5577
5578 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5579 #endif
5580 }
5581
5582 /**
5583 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5584 * print link up message
5585 * @adapter: pointer to the device adapter structure
5586 **/
5587 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5588 {
5589 struct net_device *netdev = adapter->netdev;
5590 struct ixgbe_hw *hw = &adapter->hw;
5591 u32 link_speed = adapter->link_speed;
5592 bool flow_rx, flow_tx;
5593
5594 /* only continue if link was previously down */
5595 if (netif_carrier_ok(netdev))
5596 return;
5597
5598 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5599
5600 switch (hw->mac.type) {
5601 case ixgbe_mac_82598EB: {
5602 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5603 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5604 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5605 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5606 }
5607 break;
5608 case ixgbe_mac_X540:
5609 case ixgbe_mac_82599EB: {
5610 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5611 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5612 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5613 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5614 }
5615 break;
5616 default:
5617 flow_tx = false;
5618 flow_rx = false;
5619 break;
5620 }
5621
5622 adapter->last_rx_ptp_check = jiffies;
5623
5624 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5625 ixgbe_ptp_start_cyclecounter(adapter);
5626
5627 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5628 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5629 "10 Gbps" :
5630 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5631 "1 Gbps" :
5632 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5633 "100 Mbps" :
5634 "unknown speed"))),
5635 ((flow_rx && flow_tx) ? "RX/TX" :
5636 (flow_rx ? "RX" :
5637 (flow_tx ? "TX" : "None"))));
5638
5639 netif_carrier_on(netdev);
5640 ixgbe_check_vf_rate_limit(adapter);
5641
5642 /* update the default user priority for VFs */
5643 ixgbe_update_default_up(adapter);
5644
5645 /* ping all the active vfs to let them know link has changed */
5646 ixgbe_ping_all_vfs(adapter);
5647 }
5648
5649 /**
5650 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5651 * print link down message
5652 * @adapter: pointer to the adapter structure
5653 **/
5654 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5655 {
5656 struct net_device *netdev = adapter->netdev;
5657 struct ixgbe_hw *hw = &adapter->hw;
5658
5659 adapter->link_up = false;
5660 adapter->link_speed = 0;
5661
5662 /* only continue if link was up previously */
5663 if (!netif_carrier_ok(netdev))
5664 return;
5665
5666 /* poll for SFP+ cable when link is down */
5667 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5668 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5669
5670 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5671 ixgbe_ptp_start_cyclecounter(adapter);
5672
5673 e_info(drv, "NIC Link is Down\n");
5674 netif_carrier_off(netdev);
5675
5676 /* ping all the active vfs to let them know link has changed */
5677 ixgbe_ping_all_vfs(adapter);
5678 }
5679
5680 /**
5681 * ixgbe_watchdog_flush_tx - flush queues on link down
5682 * @adapter: pointer to the device adapter structure
5683 **/
5684 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5685 {
5686 int i;
5687 int some_tx_pending = 0;
5688
5689 if (!netif_carrier_ok(adapter->netdev)) {
5690 for (i = 0; i < adapter->num_tx_queues; i++) {
5691 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5692 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5693 some_tx_pending = 1;
5694 break;
5695 }
5696 }
5697
5698 if (some_tx_pending) {
5699 /* We've lost link, so the controller stops DMA,
5700 * but we've got queued Tx work that's never going
5701 * to get done, so reset controller to flush Tx.
5702 * (Do the reset outside of interrupt context).
5703 */
5704 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5705 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5706 }
5707 }
5708 }
5709
5710 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5711 {
5712 u32 ssvpc;
5713
5714 /* Do not perform spoof check for 82598 or if not in IOV mode */
5715 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5716 adapter->num_vfs == 0)
5717 return;
5718
5719 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5720
5721 /*
5722 * ssvpc register is cleared on read, if zero then no
5723 * spoofed packets in the last interval.
5724 */
5725 if (!ssvpc)
5726 return;
5727
5728 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5729 }
5730
5731 /**
5732 * ixgbe_watchdog_subtask - check and bring link up
5733 * @adapter: pointer to the device adapter structure
5734 **/
5735 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5736 {
5737 /* if interface is down do nothing */
5738 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5739 test_bit(__IXGBE_RESETTING, &adapter->state))
5740 return;
5741
5742 ixgbe_watchdog_update_link(adapter);
5743
5744 if (adapter->link_up)
5745 ixgbe_watchdog_link_is_up(adapter);
5746 else
5747 ixgbe_watchdog_link_is_down(adapter);
5748
5749 ixgbe_spoof_check(adapter);
5750 ixgbe_update_stats(adapter);
5751
5752 ixgbe_watchdog_flush_tx(adapter);
5753 }
5754
5755 /**
5756 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5757 * @adapter: the ixgbe adapter structure
5758 **/
5759 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5760 {
5761 struct ixgbe_hw *hw = &adapter->hw;
5762 s32 err;
5763
5764 /* not searching for SFP so there is nothing to do here */
5765 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5766 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5767 return;
5768
5769 /* concurent i2c reads are not supported */
5770 if (test_bit(__IXGBE_READ_I2C, &adapter->state))
5771 return;
5772
5773 /* someone else is in init, wait until next service event */
5774 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5775 return;
5776
5777 err = hw->phy.ops.identify_sfp(hw);
5778 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5779 goto sfp_out;
5780
5781 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5782 /* If no cable is present, then we need to reset
5783 * the next time we find a good cable. */
5784 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5785 }
5786
5787 /* exit on error */
5788 if (err)
5789 goto sfp_out;
5790
5791 /* exit if reset not needed */
5792 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5793 goto sfp_out;
5794
5795 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5796
5797 /*
5798 * A module may be identified correctly, but the EEPROM may not have
5799 * support for that module. setup_sfp() will fail in that case, so
5800 * we should not allow that module to load.
5801 */
5802 if (hw->mac.type == ixgbe_mac_82598EB)
5803 err = hw->phy.ops.reset(hw);
5804 else
5805 err = hw->mac.ops.setup_sfp(hw);
5806
5807 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5808 goto sfp_out;
5809
5810 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5811 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5812
5813 sfp_out:
5814 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5815
5816 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5817 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5818 e_dev_err("failed to initialize because an unsupported "
5819 "SFP+ module type was detected.\n");
5820 e_dev_err("Reload the driver after installing a "
5821 "supported module.\n");
5822 unregister_netdev(adapter->netdev);
5823 }
5824 }
5825
5826 /**
5827 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5828 * @adapter: the ixgbe adapter structure
5829 **/
5830 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5831 {
5832 struct ixgbe_hw *hw = &adapter->hw;
5833 u32 speed;
5834 bool autoneg = false;
5835
5836 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5837 return;
5838
5839 /* someone else is in init, wait until next service event */
5840 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5841 return;
5842
5843 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5844
5845 speed = hw->phy.autoneg_advertised;
5846 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5847 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
5848 if (hw->mac.ops.setup_link)
5849 hw->mac.ops.setup_link(hw, speed, true);
5850
5851 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5852 adapter->link_check_timeout = jiffies;
5853 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5854 }
5855
5856 #ifdef CONFIG_PCI_IOV
5857 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5858 {
5859 int vf;
5860 struct ixgbe_hw *hw = &adapter->hw;
5861 struct net_device *netdev = adapter->netdev;
5862 u32 gpc;
5863 u32 ciaa, ciad;
5864
5865 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5866 if (gpc) /* If incrementing then no need for the check below */
5867 return;
5868 /*
5869 * Check to see if a bad DMA write target from an errant or
5870 * malicious VF has caused a PCIe error. If so then we can
5871 * issue a VFLR to the offending VF(s) and then resume without
5872 * requesting a full slot reset.
5873 */
5874
5875 for (vf = 0; vf < adapter->num_vfs; vf++) {
5876 ciaa = (vf << 16) | 0x80000000;
5877 /* 32 bit read so align, we really want status at offset 6 */
5878 ciaa |= PCI_COMMAND;
5879 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5880 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5881 ciaa &= 0x7FFFFFFF;
5882 /* disable debug mode asap after reading data */
5883 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5884 /* Get the upper 16 bits which will be the PCI status reg */
5885 ciad >>= 16;
5886 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5887 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5888 /* Issue VFLR */
5889 ciaa = (vf << 16) | 0x80000000;
5890 ciaa |= 0xA8;
5891 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5892 ciad = 0x00008000; /* VFLR */
5893 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5894 ciaa &= 0x7FFFFFFF;
5895 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5896 }
5897 }
5898 }
5899
5900 #endif
5901 /**
5902 * ixgbe_service_timer - Timer Call-back
5903 * @data: pointer to adapter cast into an unsigned long
5904 **/
5905 static void ixgbe_service_timer(unsigned long data)
5906 {
5907 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5908 unsigned long next_event_offset;
5909 bool ready = true;
5910
5911 /* poll faster when waiting for link */
5912 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5913 next_event_offset = HZ / 10;
5914 else
5915 next_event_offset = HZ * 2;
5916
5917 #ifdef CONFIG_PCI_IOV
5918 /*
5919 * don't bother with SR-IOV VF DMA hang check if there are
5920 * no VFs or the link is down
5921 */
5922 if (!adapter->num_vfs ||
5923 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5924 goto normal_timer_service;
5925
5926 /* If we have VFs allocated then we must check for DMA hangs */
5927 ixgbe_check_for_bad_vf(adapter);
5928 next_event_offset = HZ / 50;
5929 adapter->timer_event_accumulator++;
5930
5931 if (adapter->timer_event_accumulator >= 100)
5932 adapter->timer_event_accumulator = 0;
5933 else
5934 ready = false;
5935
5936 normal_timer_service:
5937 #endif
5938 /* Reset the timer */
5939 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5940
5941 if (ready)
5942 ixgbe_service_event_schedule(adapter);
5943 }
5944
5945 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5946 {
5947 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5948 return;
5949
5950 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5951
5952 /* If we're already down or resetting, just bail */
5953 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5954 test_bit(__IXGBE_RESETTING, &adapter->state))
5955 return;
5956
5957 ixgbe_dump(adapter);
5958 netdev_err(adapter->netdev, "Reset adapter\n");
5959 adapter->tx_timeout_count++;
5960
5961 ixgbe_reinit_locked(adapter);
5962 }
5963
5964 /**
5965 * ixgbe_service_task - manages and runs subtasks
5966 * @work: pointer to work_struct containing our data
5967 **/
5968 static void ixgbe_service_task(struct work_struct *work)
5969 {
5970 struct ixgbe_adapter *adapter = container_of(work,
5971 struct ixgbe_adapter,
5972 service_task);
5973 ixgbe_reset_subtask(adapter);
5974 ixgbe_sfp_detection_subtask(adapter);
5975 ixgbe_sfp_link_config_subtask(adapter);
5976 ixgbe_check_overtemp_subtask(adapter);
5977 ixgbe_watchdog_subtask(adapter);
5978 ixgbe_fdir_reinit_subtask(adapter);
5979 ixgbe_check_hang_subtask(adapter);
5980
5981 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5982 ixgbe_ptp_overflow_check(adapter);
5983 ixgbe_ptp_rx_hang(adapter);
5984 }
5985
5986 ixgbe_service_event_complete(adapter);
5987 }
5988
5989 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5990 struct ixgbe_tx_buffer *first,
5991 u8 *hdr_len)
5992 {
5993 struct sk_buff *skb = first->skb;
5994 u32 vlan_macip_lens, type_tucmd;
5995 u32 mss_l4len_idx, l4len;
5996
5997 if (skb->ip_summed != CHECKSUM_PARTIAL)
5998 return 0;
5999
6000 if (!skb_is_gso(skb))
6001 return 0;
6002
6003 if (skb_header_cloned(skb)) {
6004 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6005 if (err)
6006 return err;
6007 }
6008
6009 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6010 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6011
6012 if (first->protocol == __constant_htons(ETH_P_IP)) {
6013 struct iphdr *iph = ip_hdr(skb);
6014 iph->tot_len = 0;
6015 iph->check = 0;
6016 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6017 iph->daddr, 0,
6018 IPPROTO_TCP,
6019 0);
6020 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6021 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6022 IXGBE_TX_FLAGS_CSUM |
6023 IXGBE_TX_FLAGS_IPV4;
6024 } else if (skb_is_gso_v6(skb)) {
6025 ipv6_hdr(skb)->payload_len = 0;
6026 tcp_hdr(skb)->check =
6027 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6028 &ipv6_hdr(skb)->daddr,
6029 0, IPPROTO_TCP, 0);
6030 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6031 IXGBE_TX_FLAGS_CSUM;
6032 }
6033
6034 /* compute header lengths */
6035 l4len = tcp_hdrlen(skb);
6036 *hdr_len = skb_transport_offset(skb) + l4len;
6037
6038 /* update gso size and bytecount with header size */
6039 first->gso_segs = skb_shinfo(skb)->gso_segs;
6040 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6041
6042 /* mss_l4len_id: use 0 as index for TSO */
6043 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6044 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6045
6046 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6047 vlan_macip_lens = skb_network_header_len(skb);
6048 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6049 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6050
6051 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6052 mss_l4len_idx);
6053
6054 return 1;
6055 }
6056
6057 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6058 struct ixgbe_tx_buffer *first)
6059 {
6060 struct sk_buff *skb = first->skb;
6061 u32 vlan_macip_lens = 0;
6062 u32 mss_l4len_idx = 0;
6063 u32 type_tucmd = 0;
6064
6065 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6066 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6067 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6068 return;
6069 } else {
6070 u8 l4_hdr = 0;
6071 switch (first->protocol) {
6072 case __constant_htons(ETH_P_IP):
6073 vlan_macip_lens |= skb_network_header_len(skb);
6074 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6075 l4_hdr = ip_hdr(skb)->protocol;
6076 break;
6077 case __constant_htons(ETH_P_IPV6):
6078 vlan_macip_lens |= skb_network_header_len(skb);
6079 l4_hdr = ipv6_hdr(skb)->nexthdr;
6080 break;
6081 default:
6082 if (unlikely(net_ratelimit())) {
6083 dev_warn(tx_ring->dev,
6084 "partial checksum but proto=%x!\n",
6085 first->protocol);
6086 }
6087 break;
6088 }
6089
6090 switch (l4_hdr) {
6091 case IPPROTO_TCP:
6092 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6093 mss_l4len_idx = tcp_hdrlen(skb) <<
6094 IXGBE_ADVTXD_L4LEN_SHIFT;
6095 break;
6096 case IPPROTO_SCTP:
6097 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6098 mss_l4len_idx = sizeof(struct sctphdr) <<
6099 IXGBE_ADVTXD_L4LEN_SHIFT;
6100 break;
6101 case IPPROTO_UDP:
6102 mss_l4len_idx = sizeof(struct udphdr) <<
6103 IXGBE_ADVTXD_L4LEN_SHIFT;
6104 break;
6105 default:
6106 if (unlikely(net_ratelimit())) {
6107 dev_warn(tx_ring->dev,
6108 "partial checksum but l4 proto=%x!\n",
6109 l4_hdr);
6110 }
6111 break;
6112 }
6113
6114 /* update TX checksum flag */
6115 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6116 }
6117
6118 /* vlan_macip_lens: MACLEN, VLAN tag */
6119 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6120 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6121
6122 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6123 type_tucmd, mss_l4len_idx);
6124 }
6125
6126 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6127 ((_flag <= _result) ? \
6128 ((u32)(_input & _flag) * (_result / _flag)) : \
6129 ((u32)(_input & _flag) / (_flag / _result)))
6130
6131 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6132 {
6133 /* set type for advanced descriptor with frame checksum insertion */
6134 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6135 IXGBE_ADVTXD_DCMD_DEXT |
6136 IXGBE_ADVTXD_DCMD_IFCS;
6137
6138 /* set HW vlan bit if vlan is present */
6139 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6140 IXGBE_ADVTXD_DCMD_VLE);
6141
6142 /* set segmentation enable bits for TSO/FSO */
6143 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6144 IXGBE_ADVTXD_DCMD_TSE);
6145
6146 /* set timestamp bit if present */
6147 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6148 IXGBE_ADVTXD_MAC_TSTAMP);
6149
6150 /* insert frame checksum */
6151 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6152
6153 return cmd_type;
6154 }
6155
6156 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6157 u32 tx_flags, unsigned int paylen)
6158 {
6159 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6160
6161 /* enable L4 checksum for TSO and TX checksum offload */
6162 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6163 IXGBE_TX_FLAGS_CSUM,
6164 IXGBE_ADVTXD_POPTS_TXSM);
6165
6166 /* enble IPv4 checksum for TSO */
6167 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6168 IXGBE_TX_FLAGS_IPV4,
6169 IXGBE_ADVTXD_POPTS_IXSM);
6170
6171 /*
6172 * Check Context must be set if Tx switch is enabled, which it
6173 * always is for case where virtual functions are running
6174 */
6175 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6176 IXGBE_TX_FLAGS_CC,
6177 IXGBE_ADVTXD_CC);
6178
6179 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6180 }
6181
6182 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6183 IXGBE_TXD_CMD_RS)
6184
6185 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6186 struct ixgbe_tx_buffer *first,
6187 const u8 hdr_len)
6188 {
6189 struct sk_buff *skb = first->skb;
6190 struct ixgbe_tx_buffer *tx_buffer;
6191 union ixgbe_adv_tx_desc *tx_desc;
6192 struct skb_frag_struct *frag;
6193 dma_addr_t dma;
6194 unsigned int data_len, size;
6195 u32 tx_flags = first->tx_flags;
6196 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6197 u16 i = tx_ring->next_to_use;
6198
6199 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6200
6201 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6202
6203 size = skb_headlen(skb);
6204 data_len = skb->data_len;
6205
6206 #ifdef IXGBE_FCOE
6207 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6208 if (data_len < sizeof(struct fcoe_crc_eof)) {
6209 size -= sizeof(struct fcoe_crc_eof) - data_len;
6210 data_len = 0;
6211 } else {
6212 data_len -= sizeof(struct fcoe_crc_eof);
6213 }
6214 }
6215
6216 #endif
6217 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6218
6219 tx_buffer = first;
6220
6221 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6222 if (dma_mapping_error(tx_ring->dev, dma))
6223 goto dma_error;
6224
6225 /* record length, and DMA address */
6226 dma_unmap_len_set(tx_buffer, len, size);
6227 dma_unmap_addr_set(tx_buffer, dma, dma);
6228
6229 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6230
6231 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6232 tx_desc->read.cmd_type_len =
6233 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6234
6235 i++;
6236 tx_desc++;
6237 if (i == tx_ring->count) {
6238 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6239 i = 0;
6240 }
6241 tx_desc->read.olinfo_status = 0;
6242
6243 dma += IXGBE_MAX_DATA_PER_TXD;
6244 size -= IXGBE_MAX_DATA_PER_TXD;
6245
6246 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6247 }
6248
6249 if (likely(!data_len))
6250 break;
6251
6252 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6253
6254 i++;
6255 tx_desc++;
6256 if (i == tx_ring->count) {
6257 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6258 i = 0;
6259 }
6260 tx_desc->read.olinfo_status = 0;
6261
6262 #ifdef IXGBE_FCOE
6263 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6264 #else
6265 size = skb_frag_size(frag);
6266 #endif
6267 data_len -= size;
6268
6269 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6270 DMA_TO_DEVICE);
6271
6272 tx_buffer = &tx_ring->tx_buffer_info[i];
6273 }
6274
6275 /* write last descriptor with RS and EOP bits */
6276 cmd_type |= size | IXGBE_TXD_CMD;
6277 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6278
6279 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6280
6281 /* set the timestamp */
6282 first->time_stamp = jiffies;
6283
6284 /*
6285 * Force memory writes to complete before letting h/w know there
6286 * are new descriptors to fetch. (Only applicable for weak-ordered
6287 * memory model archs, such as IA-64).
6288 *
6289 * We also need this memory barrier to make certain all of the
6290 * status bits have been updated before next_to_watch is written.
6291 */
6292 wmb();
6293
6294 /* set next_to_watch value indicating a packet is present */
6295 first->next_to_watch = tx_desc;
6296
6297 i++;
6298 if (i == tx_ring->count)
6299 i = 0;
6300
6301 tx_ring->next_to_use = i;
6302
6303 /* notify HW of packet */
6304 writel(i, tx_ring->tail);
6305
6306 return;
6307 dma_error:
6308 dev_err(tx_ring->dev, "TX DMA map failed\n");
6309
6310 /* clear dma mappings for failed tx_buffer_info map */
6311 for (;;) {
6312 tx_buffer = &tx_ring->tx_buffer_info[i];
6313 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6314 if (tx_buffer == first)
6315 break;
6316 if (i == 0)
6317 i = tx_ring->count;
6318 i--;
6319 }
6320
6321 tx_ring->next_to_use = i;
6322 }
6323
6324 static void ixgbe_atr(struct ixgbe_ring *ring,
6325 struct ixgbe_tx_buffer *first)
6326 {
6327 struct ixgbe_q_vector *q_vector = ring->q_vector;
6328 union ixgbe_atr_hash_dword input = { .dword = 0 };
6329 union ixgbe_atr_hash_dword common = { .dword = 0 };
6330 union {
6331 unsigned char *network;
6332 struct iphdr *ipv4;
6333 struct ipv6hdr *ipv6;
6334 } hdr;
6335 struct tcphdr *th;
6336 __be16 vlan_id;
6337
6338 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6339 if (!q_vector)
6340 return;
6341
6342 /* do nothing if sampling is disabled */
6343 if (!ring->atr_sample_rate)
6344 return;
6345
6346 ring->atr_count++;
6347
6348 /* snag network header to get L4 type and address */
6349 hdr.network = skb_network_header(first->skb);
6350
6351 /* Currently only IPv4/IPv6 with TCP is supported */
6352 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6353 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6354 (first->protocol != __constant_htons(ETH_P_IP) ||
6355 hdr.ipv4->protocol != IPPROTO_TCP))
6356 return;
6357
6358 th = tcp_hdr(first->skb);
6359
6360 /* skip this packet since it is invalid or the socket is closing */
6361 if (!th || th->fin)
6362 return;
6363
6364 /* sample on all syn packets or once every atr sample count */
6365 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6366 return;
6367
6368 /* reset sample count */
6369 ring->atr_count = 0;
6370
6371 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6372
6373 /*
6374 * src and dst are inverted, think how the receiver sees them
6375 *
6376 * The input is broken into two sections, a non-compressed section
6377 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6378 * is XORed together and stored in the compressed dword.
6379 */
6380 input.formatted.vlan_id = vlan_id;
6381
6382 /*
6383 * since src port and flex bytes occupy the same word XOR them together
6384 * and write the value to source port portion of compressed dword
6385 */
6386 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6387 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6388 else
6389 common.port.src ^= th->dest ^ first->protocol;
6390 common.port.dst ^= th->source;
6391
6392 if (first->protocol == __constant_htons(ETH_P_IP)) {
6393 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6394 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6395 } else {
6396 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6397 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6398 hdr.ipv6->saddr.s6_addr32[1] ^
6399 hdr.ipv6->saddr.s6_addr32[2] ^
6400 hdr.ipv6->saddr.s6_addr32[3] ^
6401 hdr.ipv6->daddr.s6_addr32[0] ^
6402 hdr.ipv6->daddr.s6_addr32[1] ^
6403 hdr.ipv6->daddr.s6_addr32[2] ^
6404 hdr.ipv6->daddr.s6_addr32[3];
6405 }
6406
6407 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6408 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6409 input, common, ring->queue_index);
6410 }
6411
6412 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6413 {
6414 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6415 /* Herbert's original patch had:
6416 * smp_mb__after_netif_stop_queue();
6417 * but since that doesn't exist yet, just open code it. */
6418 smp_mb();
6419
6420 /* We need to check again in a case another CPU has just
6421 * made room available. */
6422 if (likely(ixgbe_desc_unused(tx_ring) < size))
6423 return -EBUSY;
6424
6425 /* A reprieve! - use start_queue because it doesn't call schedule */
6426 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6427 ++tx_ring->tx_stats.restart_queue;
6428 return 0;
6429 }
6430
6431 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6432 {
6433 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6434 return 0;
6435 return __ixgbe_maybe_stop_tx(tx_ring, size);
6436 }
6437
6438 #ifdef IXGBE_FCOE
6439 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6440 {
6441 struct ixgbe_adapter *adapter;
6442 struct ixgbe_ring_feature *f;
6443 int txq;
6444
6445 /*
6446 * only execute the code below if protocol is FCoE
6447 * or FIP and we have FCoE enabled on the adapter
6448 */
6449 switch (vlan_get_protocol(skb)) {
6450 case __constant_htons(ETH_P_FCOE):
6451 case __constant_htons(ETH_P_FIP):
6452 adapter = netdev_priv(dev);
6453
6454 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6455 break;
6456 default:
6457 return __netdev_pick_tx(dev, skb);
6458 }
6459
6460 f = &adapter->ring_feature[RING_F_FCOE];
6461
6462 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6463 smp_processor_id();
6464
6465 while (txq >= f->indices)
6466 txq -= f->indices;
6467
6468 return txq + f->offset;
6469 }
6470
6471 #endif
6472 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6473 struct ixgbe_adapter *adapter,
6474 struct ixgbe_ring *tx_ring)
6475 {
6476 struct ixgbe_tx_buffer *first;
6477 int tso;
6478 u32 tx_flags = 0;
6479 unsigned short f;
6480 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6481 __be16 protocol = skb->protocol;
6482 u8 hdr_len = 0;
6483
6484 /*
6485 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6486 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6487 * + 2 desc gap to keep tail from touching head,
6488 * + 1 desc for context descriptor,
6489 * otherwise try next time
6490 */
6491 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6492 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6493
6494 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6495 tx_ring->tx_stats.tx_busy++;
6496 return NETDEV_TX_BUSY;
6497 }
6498
6499 /* record the location of the first descriptor for this packet */
6500 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6501 first->skb = skb;
6502 first->bytecount = skb->len;
6503 first->gso_segs = 1;
6504
6505 /* if we have a HW VLAN tag being added default to the HW one */
6506 if (vlan_tx_tag_present(skb)) {
6507 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6508 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6509 /* else if it is a SW VLAN check the next protocol and store the tag */
6510 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6511 struct vlan_hdr *vhdr, _vhdr;
6512 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6513 if (!vhdr)
6514 goto out_drop;
6515
6516 protocol = vhdr->h_vlan_encapsulated_proto;
6517 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6518 IXGBE_TX_FLAGS_VLAN_SHIFT;
6519 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6520 }
6521
6522 skb_tx_timestamp(skb);
6523
6524 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6525 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6526 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6527
6528 /* schedule check for Tx timestamp */
6529 adapter->ptp_tx_skb = skb_get(skb);
6530 adapter->ptp_tx_start = jiffies;
6531 schedule_work(&adapter->ptp_tx_work);
6532 }
6533
6534 #ifdef CONFIG_PCI_IOV
6535 /*
6536 * Use the l2switch_enable flag - would be false if the DMA
6537 * Tx switch had been disabled.
6538 */
6539 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6540 tx_flags |= IXGBE_TX_FLAGS_CC;
6541
6542 #endif
6543 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6544 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6545 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6546 (skb->priority != TC_PRIO_CONTROL))) {
6547 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6548 tx_flags |= (skb->priority & 0x7) <<
6549 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6550 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6551 struct vlan_ethhdr *vhdr;
6552 if (skb_header_cloned(skb) &&
6553 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6554 goto out_drop;
6555 vhdr = (struct vlan_ethhdr *)skb->data;
6556 vhdr->h_vlan_TCI = htons(tx_flags >>
6557 IXGBE_TX_FLAGS_VLAN_SHIFT);
6558 } else {
6559 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6560 }
6561 }
6562
6563 /* record initial flags and protocol */
6564 first->tx_flags = tx_flags;
6565 first->protocol = protocol;
6566
6567 #ifdef IXGBE_FCOE
6568 /* setup tx offload for FCoE */
6569 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6570 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6571 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6572 if (tso < 0)
6573 goto out_drop;
6574
6575 goto xmit_fcoe;
6576 }
6577
6578 #endif /* IXGBE_FCOE */
6579 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6580 if (tso < 0)
6581 goto out_drop;
6582 else if (!tso)
6583 ixgbe_tx_csum(tx_ring, first);
6584
6585 /* add the ATR filter if ATR is on */
6586 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6587 ixgbe_atr(tx_ring, first);
6588
6589 #ifdef IXGBE_FCOE
6590 xmit_fcoe:
6591 #endif /* IXGBE_FCOE */
6592 ixgbe_tx_map(tx_ring, first, hdr_len);
6593
6594 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6595
6596 return NETDEV_TX_OK;
6597
6598 out_drop:
6599 dev_kfree_skb_any(first->skb);
6600 first->skb = NULL;
6601
6602 return NETDEV_TX_OK;
6603 }
6604
6605 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6606 struct net_device *netdev)
6607 {
6608 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6609 struct ixgbe_ring *tx_ring;
6610
6611 /*
6612 * The minimum packet size for olinfo paylen is 17 so pad the skb
6613 * in order to meet this minimum size requirement.
6614 */
6615 if (unlikely(skb->len < 17)) {
6616 if (skb_pad(skb, 17 - skb->len))
6617 return NETDEV_TX_OK;
6618 skb->len = 17;
6619 skb_set_tail_pointer(skb, 17);
6620 }
6621
6622 tx_ring = adapter->tx_ring[skb->queue_mapping];
6623 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6624 }
6625
6626 /**
6627 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6628 * @netdev: network interface device structure
6629 * @p: pointer to an address structure
6630 *
6631 * Returns 0 on success, negative on failure
6632 **/
6633 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6634 {
6635 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6636 struct ixgbe_hw *hw = &adapter->hw;
6637 struct sockaddr *addr = p;
6638
6639 if (!is_valid_ether_addr(addr->sa_data))
6640 return -EADDRNOTAVAIL;
6641
6642 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6643 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6644
6645 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6646
6647 return 0;
6648 }
6649
6650 static int
6651 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6652 {
6653 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6654 struct ixgbe_hw *hw = &adapter->hw;
6655 u16 value;
6656 int rc;
6657
6658 if (prtad != hw->phy.mdio.prtad)
6659 return -EINVAL;
6660 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6661 if (!rc)
6662 rc = value;
6663 return rc;
6664 }
6665
6666 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6667 u16 addr, u16 value)
6668 {
6669 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6670 struct ixgbe_hw *hw = &adapter->hw;
6671
6672 if (prtad != hw->phy.mdio.prtad)
6673 return -EINVAL;
6674 return hw->phy.ops.write_reg(hw, addr, devad, value);
6675 }
6676
6677 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6678 {
6679 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6680
6681 switch (cmd) {
6682 case SIOCSHWTSTAMP:
6683 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6684 default:
6685 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6686 }
6687 }
6688
6689 /**
6690 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6691 * netdev->dev_addrs
6692 * @netdev: network interface device structure
6693 *
6694 * Returns non-zero on failure
6695 **/
6696 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6697 {
6698 int err = 0;
6699 struct ixgbe_adapter *adapter = netdev_priv(dev);
6700 struct ixgbe_hw *hw = &adapter->hw;
6701
6702 if (is_valid_ether_addr(hw->mac.san_addr)) {
6703 rtnl_lock();
6704 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6705 rtnl_unlock();
6706
6707 /* update SAN MAC vmdq pool selection */
6708 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6709 }
6710 return err;
6711 }
6712
6713 /**
6714 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6715 * netdev->dev_addrs
6716 * @netdev: network interface device structure
6717 *
6718 * Returns non-zero on failure
6719 **/
6720 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6721 {
6722 int err = 0;
6723 struct ixgbe_adapter *adapter = netdev_priv(dev);
6724 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6725
6726 if (is_valid_ether_addr(mac->san_addr)) {
6727 rtnl_lock();
6728 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6729 rtnl_unlock();
6730 }
6731 return err;
6732 }
6733
6734 #ifdef CONFIG_NET_POLL_CONTROLLER
6735 /*
6736 * Polling 'interrupt' - used by things like netconsole to send skbs
6737 * without having to re-enable interrupts. It's not called while
6738 * the interrupt routine is executing.
6739 */
6740 static void ixgbe_netpoll(struct net_device *netdev)
6741 {
6742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6743 int i;
6744
6745 /* if interface is down do nothing */
6746 if (test_bit(__IXGBE_DOWN, &adapter->state))
6747 return;
6748
6749 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6750 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6751 for (i = 0; i < adapter->num_q_vectors; i++)
6752 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6753 } else {
6754 ixgbe_intr(adapter->pdev->irq, netdev);
6755 }
6756 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6757 }
6758
6759 #endif
6760 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6761 struct rtnl_link_stats64 *stats)
6762 {
6763 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6764 int i;
6765
6766 rcu_read_lock();
6767 for (i = 0; i < adapter->num_rx_queues; i++) {
6768 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6769 u64 bytes, packets;
6770 unsigned int start;
6771
6772 if (ring) {
6773 do {
6774 start = u64_stats_fetch_begin_bh(&ring->syncp);
6775 packets = ring->stats.packets;
6776 bytes = ring->stats.bytes;
6777 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6778 stats->rx_packets += packets;
6779 stats->rx_bytes += bytes;
6780 }
6781 }
6782
6783 for (i = 0; i < adapter->num_tx_queues; i++) {
6784 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6785 u64 bytes, packets;
6786 unsigned int start;
6787
6788 if (ring) {
6789 do {
6790 start = u64_stats_fetch_begin_bh(&ring->syncp);
6791 packets = ring->stats.packets;
6792 bytes = ring->stats.bytes;
6793 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6794 stats->tx_packets += packets;
6795 stats->tx_bytes += bytes;
6796 }
6797 }
6798 rcu_read_unlock();
6799 /* following stats updated by ixgbe_watchdog_task() */
6800 stats->multicast = netdev->stats.multicast;
6801 stats->rx_errors = netdev->stats.rx_errors;
6802 stats->rx_length_errors = netdev->stats.rx_length_errors;
6803 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6804 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6805 return stats;
6806 }
6807
6808 #ifdef CONFIG_IXGBE_DCB
6809 /**
6810 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6811 * @adapter: pointer to ixgbe_adapter
6812 * @tc: number of traffic classes currently enabled
6813 *
6814 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6815 * 802.1Q priority maps to a packet buffer that exists.
6816 */
6817 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6818 {
6819 struct ixgbe_hw *hw = &adapter->hw;
6820 u32 reg, rsave;
6821 int i;
6822
6823 /* 82598 have a static priority to TC mapping that can not
6824 * be changed so no validation is needed.
6825 */
6826 if (hw->mac.type == ixgbe_mac_82598EB)
6827 return;
6828
6829 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6830 rsave = reg;
6831
6832 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6833 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6834
6835 /* If up2tc is out of bounds default to zero */
6836 if (up2tc > tc)
6837 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6838 }
6839
6840 if (reg != rsave)
6841 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6842
6843 return;
6844 }
6845
6846 /**
6847 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6848 * @adapter: Pointer to adapter struct
6849 *
6850 * Populate the netdev user priority to tc map
6851 */
6852 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6853 {
6854 struct net_device *dev = adapter->netdev;
6855 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6856 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6857 u8 prio;
6858
6859 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6860 u8 tc = 0;
6861
6862 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6863 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6864 else if (ets)
6865 tc = ets->prio_tc[prio];
6866
6867 netdev_set_prio_tc_map(dev, prio, tc);
6868 }
6869 }
6870
6871 #endif /* CONFIG_IXGBE_DCB */
6872 /**
6873 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6874 *
6875 * @netdev: net device to configure
6876 * @tc: number of traffic classes to enable
6877 */
6878 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6879 {
6880 struct ixgbe_adapter *adapter = netdev_priv(dev);
6881 struct ixgbe_hw *hw = &adapter->hw;
6882
6883 /* Hardware supports up to 8 traffic classes */
6884 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6885 (hw->mac.type == ixgbe_mac_82598EB &&
6886 tc < MAX_TRAFFIC_CLASS))
6887 return -EINVAL;
6888
6889 /* Hardware has to reinitialize queues and interrupts to
6890 * match packet buffer alignment. Unfortunately, the
6891 * hardware is not flexible enough to do this dynamically.
6892 */
6893 if (netif_running(dev))
6894 ixgbe_close(dev);
6895 ixgbe_clear_interrupt_scheme(adapter);
6896
6897 #ifdef CONFIG_IXGBE_DCB
6898 if (tc) {
6899 netdev_set_num_tc(dev, tc);
6900 ixgbe_set_prio_tc_map(adapter);
6901
6902 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6903
6904 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6905 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6906 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6907 }
6908 } else {
6909 netdev_reset_tc(dev);
6910
6911 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6912 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6913
6914 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6915
6916 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6917 adapter->dcb_cfg.pfc_mode_enable = false;
6918 }
6919
6920 ixgbe_validate_rtr(adapter, tc);
6921
6922 #endif /* CONFIG_IXGBE_DCB */
6923 ixgbe_init_interrupt_scheme(adapter);
6924
6925 if (netif_running(dev))
6926 return ixgbe_open(dev);
6927
6928 return 0;
6929 }
6930
6931 #ifdef CONFIG_PCI_IOV
6932 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6933 {
6934 struct net_device *netdev = adapter->netdev;
6935
6936 rtnl_lock();
6937 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6938 rtnl_unlock();
6939 }
6940
6941 #endif
6942 void ixgbe_do_reset(struct net_device *netdev)
6943 {
6944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6945
6946 if (netif_running(netdev))
6947 ixgbe_reinit_locked(adapter);
6948 else
6949 ixgbe_reset(adapter);
6950 }
6951
6952 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6953 netdev_features_t features)
6954 {
6955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6956
6957 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6958 if (!(features & NETIF_F_RXCSUM))
6959 features &= ~NETIF_F_LRO;
6960
6961 /* Turn off LRO if not RSC capable */
6962 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6963 features &= ~NETIF_F_LRO;
6964
6965 return features;
6966 }
6967
6968 static int ixgbe_set_features(struct net_device *netdev,
6969 netdev_features_t features)
6970 {
6971 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6972 netdev_features_t changed = netdev->features ^ features;
6973 bool need_reset = false;
6974
6975 /* Make sure RSC matches LRO, reset if change */
6976 if (!(features & NETIF_F_LRO)) {
6977 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6978 need_reset = true;
6979 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6980 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6981 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6982 if (adapter->rx_itr_setting == 1 ||
6983 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6984 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6985 need_reset = true;
6986 } else if ((changed ^ features) & NETIF_F_LRO) {
6987 e_info(probe, "rx-usecs set too low, "
6988 "disabling RSC\n");
6989 }
6990 }
6991
6992 /*
6993 * Check if Flow Director n-tuple support was enabled or disabled. If
6994 * the state changed, we need to reset.
6995 */
6996 switch (features & NETIF_F_NTUPLE) {
6997 case NETIF_F_NTUPLE:
6998 /* turn off ATR, enable perfect filters and reset */
6999 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7000 need_reset = true;
7001
7002 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7003 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7004 break;
7005 default:
7006 /* turn off perfect filters, enable ATR and reset */
7007 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7008 need_reset = true;
7009
7010 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7011
7012 /* We cannot enable ATR if SR-IOV is enabled */
7013 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7014 break;
7015
7016 /* We cannot enable ATR if we have 2 or more traffic classes */
7017 if (netdev_get_num_tc(netdev) > 1)
7018 break;
7019
7020 /* We cannot enable ATR if RSS is disabled */
7021 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7022 break;
7023
7024 /* A sample rate of 0 indicates ATR disabled */
7025 if (!adapter->atr_sample_rate)
7026 break;
7027
7028 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7029 break;
7030 }
7031
7032 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7033 ixgbe_vlan_strip_enable(adapter);
7034 else
7035 ixgbe_vlan_strip_disable(adapter);
7036
7037 if (changed & NETIF_F_RXALL)
7038 need_reset = true;
7039
7040 netdev->features = features;
7041 if (need_reset)
7042 ixgbe_do_reset(netdev);
7043
7044 return 0;
7045 }
7046
7047 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7048 struct net_device *dev,
7049 const unsigned char *addr,
7050 u16 flags)
7051 {
7052 struct ixgbe_adapter *adapter = netdev_priv(dev);
7053 int err;
7054
7055 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7056 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7057
7058 /* Hardware does not support aging addresses so if a
7059 * ndm_state is given only allow permanent addresses
7060 */
7061 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7062 pr_info("%s: FDB only supports static addresses\n",
7063 ixgbe_driver_name);
7064 return -EINVAL;
7065 }
7066
7067 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7068 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7069
7070 if (netdev_uc_count(dev) < rar_uc_entries)
7071 err = dev_uc_add_excl(dev, addr);
7072 else
7073 err = -ENOMEM;
7074 } else if (is_multicast_ether_addr(addr)) {
7075 err = dev_mc_add_excl(dev, addr);
7076 } else {
7077 err = -EINVAL;
7078 }
7079
7080 /* Only return duplicate errors if NLM_F_EXCL is set */
7081 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7082 err = 0;
7083
7084 return err;
7085 }
7086
7087 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7088 struct nlmsghdr *nlh)
7089 {
7090 struct ixgbe_adapter *adapter = netdev_priv(dev);
7091 struct nlattr *attr, *br_spec;
7092 int rem;
7093
7094 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7095 return -EOPNOTSUPP;
7096
7097 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7098
7099 nla_for_each_nested(attr, br_spec, rem) {
7100 __u16 mode;
7101 u32 reg = 0;
7102
7103 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7104 continue;
7105
7106 mode = nla_get_u16(attr);
7107 if (mode == BRIDGE_MODE_VEPA) {
7108 reg = 0;
7109 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7110 } else if (mode == BRIDGE_MODE_VEB) {
7111 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7112 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7113 } else
7114 return -EINVAL;
7115
7116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7117
7118 e_info(drv, "enabling bridge mode: %s\n",
7119 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7120 }
7121
7122 return 0;
7123 }
7124
7125 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7126 struct net_device *dev,
7127 u32 filter_mask)
7128 {
7129 struct ixgbe_adapter *adapter = netdev_priv(dev);
7130 u16 mode;
7131
7132 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7133 return 0;
7134
7135 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7136 mode = BRIDGE_MODE_VEB;
7137 else
7138 mode = BRIDGE_MODE_VEPA;
7139
7140 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7141 }
7142
7143 static const struct net_device_ops ixgbe_netdev_ops = {
7144 .ndo_open = ixgbe_open,
7145 .ndo_stop = ixgbe_close,
7146 .ndo_start_xmit = ixgbe_xmit_frame,
7147 #ifdef IXGBE_FCOE
7148 .ndo_select_queue = ixgbe_select_queue,
7149 #endif
7150 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7151 .ndo_validate_addr = eth_validate_addr,
7152 .ndo_set_mac_address = ixgbe_set_mac,
7153 .ndo_change_mtu = ixgbe_change_mtu,
7154 .ndo_tx_timeout = ixgbe_tx_timeout,
7155 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7156 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7157 .ndo_do_ioctl = ixgbe_ioctl,
7158 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7159 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7160 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7161 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7162 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7163 .ndo_get_stats64 = ixgbe_get_stats64,
7164 #ifdef CONFIG_IXGBE_DCB
7165 .ndo_setup_tc = ixgbe_setup_tc,
7166 #endif
7167 #ifdef CONFIG_NET_POLL_CONTROLLER
7168 .ndo_poll_controller = ixgbe_netpoll,
7169 #endif
7170 #ifdef IXGBE_FCOE
7171 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7172 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7173 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7174 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7175 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7176 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7177 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7178 #endif /* IXGBE_FCOE */
7179 .ndo_set_features = ixgbe_set_features,
7180 .ndo_fix_features = ixgbe_fix_features,
7181 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7182 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7183 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7184 };
7185
7186 /**
7187 * ixgbe_wol_supported - Check whether device supports WoL
7188 * @hw: hw specific details
7189 * @device_id: the device ID
7190 * @subdev_id: the subsystem device ID
7191 *
7192 * This function is used by probe and ethtool to determine
7193 * which devices have WoL support
7194 *
7195 **/
7196 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7197 u16 subdevice_id)
7198 {
7199 struct ixgbe_hw *hw = &adapter->hw;
7200 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7201 int is_wol_supported = 0;
7202
7203 switch (device_id) {
7204 case IXGBE_DEV_ID_82599_SFP:
7205 /* Only these subdevices could supports WOL */
7206 switch (subdevice_id) {
7207 case IXGBE_SUBDEV_ID_82599_560FLR:
7208 /* only support first port */
7209 if (hw->bus.func != 0)
7210 break;
7211 case IXGBE_SUBDEV_ID_82599_SFP:
7212 case IXGBE_SUBDEV_ID_82599_RNDC:
7213 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7214 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7215 is_wol_supported = 1;
7216 break;
7217 }
7218 break;
7219 case IXGBE_DEV_ID_82599EN_SFP:
7220 /* Only this subdevice supports WOL */
7221 switch (subdevice_id) {
7222 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7223 is_wol_supported = 1;
7224 break;
7225 }
7226 break;
7227 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7228 /* All except this subdevice support WOL */
7229 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7230 is_wol_supported = 1;
7231 break;
7232 case IXGBE_DEV_ID_82599_KX4:
7233 is_wol_supported = 1;
7234 break;
7235 case IXGBE_DEV_ID_X540T:
7236 case IXGBE_DEV_ID_X540T1:
7237 /* check eeprom to see if enabled wol */
7238 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7239 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7240 (hw->bus.func == 0))) {
7241 is_wol_supported = 1;
7242 }
7243 break;
7244 }
7245
7246 return is_wol_supported;
7247 }
7248
7249 /**
7250 * ixgbe_probe - Device Initialization Routine
7251 * @pdev: PCI device information struct
7252 * @ent: entry in ixgbe_pci_tbl
7253 *
7254 * Returns 0 on success, negative on failure
7255 *
7256 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7257 * The OS initialization, configuring of the adapter private structure,
7258 * and a hardware reset occur.
7259 **/
7260 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7261 {
7262 struct net_device *netdev;
7263 struct ixgbe_adapter *adapter = NULL;
7264 struct ixgbe_hw *hw;
7265 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7266 static int cards_found;
7267 int i, err, pci_using_dac;
7268 unsigned int indices = MAX_TX_QUEUES;
7269 u8 part_str[IXGBE_PBANUM_LENGTH];
7270 #ifdef IXGBE_FCOE
7271 u16 device_caps;
7272 #endif
7273 u32 eec;
7274
7275 /* Catch broken hardware that put the wrong VF device ID in
7276 * the PCIe SR-IOV capability.
7277 */
7278 if (pdev->is_virtfn) {
7279 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7280 pci_name(pdev), pdev->vendor, pdev->device);
7281 return -EINVAL;
7282 }
7283
7284 err = pci_enable_device_mem(pdev);
7285 if (err)
7286 return err;
7287
7288 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7289 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7290 pci_using_dac = 1;
7291 } else {
7292 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7293 if (err) {
7294 err = dma_set_coherent_mask(&pdev->dev,
7295 DMA_BIT_MASK(32));
7296 if (err) {
7297 dev_err(&pdev->dev,
7298 "No usable DMA configuration, aborting\n");
7299 goto err_dma;
7300 }
7301 }
7302 pci_using_dac = 0;
7303 }
7304
7305 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7306 IORESOURCE_MEM), ixgbe_driver_name);
7307 if (err) {
7308 dev_err(&pdev->dev,
7309 "pci_request_selected_regions failed 0x%x\n", err);
7310 goto err_pci_reg;
7311 }
7312
7313 pci_enable_pcie_error_reporting(pdev);
7314
7315 pci_set_master(pdev);
7316 pci_save_state(pdev);
7317
7318 if (ii->mac == ixgbe_mac_82598EB) {
7319 #ifdef CONFIG_IXGBE_DCB
7320 /* 8 TC w/ 4 queues per TC */
7321 indices = 4 * MAX_TRAFFIC_CLASS;
7322 #else
7323 indices = IXGBE_MAX_RSS_INDICES;
7324 #endif
7325 }
7326
7327 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7328 if (!netdev) {
7329 err = -ENOMEM;
7330 goto err_alloc_etherdev;
7331 }
7332
7333 SET_NETDEV_DEV(netdev, &pdev->dev);
7334
7335 adapter = netdev_priv(netdev);
7336 pci_set_drvdata(pdev, adapter);
7337
7338 adapter->netdev = netdev;
7339 adapter->pdev = pdev;
7340 hw = &adapter->hw;
7341 hw->back = adapter;
7342 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7343
7344 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7345 pci_resource_len(pdev, 0));
7346 if (!hw->hw_addr) {
7347 err = -EIO;
7348 goto err_ioremap;
7349 }
7350
7351 netdev->netdev_ops = &ixgbe_netdev_ops;
7352 ixgbe_set_ethtool_ops(netdev);
7353 netdev->watchdog_timeo = 5 * HZ;
7354 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7355
7356 adapter->bd_number = cards_found;
7357
7358 /* Setup hw api */
7359 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7360 hw->mac.type = ii->mac;
7361
7362 /* EEPROM */
7363 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7364 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7365 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7366 if (!(eec & (1 << 8)))
7367 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7368
7369 /* PHY */
7370 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7371 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7372 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7373 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7374 hw->phy.mdio.mmds = 0;
7375 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7376 hw->phy.mdio.dev = netdev;
7377 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7378 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7379
7380 ii->get_invariants(hw);
7381
7382 /* setup the private structure */
7383 err = ixgbe_sw_init(adapter);
7384 if (err)
7385 goto err_sw_init;
7386
7387 /* Cache if MNG FW is up so we don't have to read the REG later */
7388 if (hw->mac.ops.mng_fw_enabled)
7389 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7390
7391 /* Make it possible the adapter to be woken up via WOL */
7392 switch (adapter->hw.mac.type) {
7393 case ixgbe_mac_82599EB:
7394 case ixgbe_mac_X540:
7395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7396 break;
7397 default:
7398 break;
7399 }
7400
7401 /*
7402 * If there is a fan on this device and it has failed log the
7403 * failure.
7404 */
7405 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7406 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7407 if (esdp & IXGBE_ESDP_SDP1)
7408 e_crit(probe, "Fan has stopped, replace the adapter\n");
7409 }
7410
7411 if (allow_unsupported_sfp)
7412 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7413
7414 /* reset_hw fills in the perm_addr as well */
7415 hw->phy.reset_if_overtemp = true;
7416 err = hw->mac.ops.reset_hw(hw);
7417 hw->phy.reset_if_overtemp = false;
7418 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7419 hw->mac.type == ixgbe_mac_82598EB) {
7420 err = 0;
7421 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7422 e_dev_err("failed to load because an unsupported SFP+ "
7423 "module type was detected.\n");
7424 e_dev_err("Reload the driver after installing a supported "
7425 "module.\n");
7426 goto err_sw_init;
7427 } else if (err) {
7428 e_dev_err("HW Init failed: %d\n", err);
7429 goto err_sw_init;
7430 }
7431
7432 #ifdef CONFIG_PCI_IOV
7433 /* SR-IOV not supported on the 82598 */
7434 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7435 goto skip_sriov;
7436 /* Mailbox */
7437 ixgbe_init_mbx_params_pf(hw);
7438 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7439 ixgbe_enable_sriov(adapter);
7440 pci_sriov_set_totalvfs(pdev, 63);
7441 skip_sriov:
7442
7443 #endif
7444 netdev->features = NETIF_F_SG |
7445 NETIF_F_IP_CSUM |
7446 NETIF_F_IPV6_CSUM |
7447 NETIF_F_HW_VLAN_CTAG_TX |
7448 NETIF_F_HW_VLAN_CTAG_RX |
7449 NETIF_F_HW_VLAN_CTAG_FILTER |
7450 NETIF_F_TSO |
7451 NETIF_F_TSO6 |
7452 NETIF_F_RXHASH |
7453 NETIF_F_RXCSUM;
7454
7455 netdev->hw_features = netdev->features;
7456
7457 switch (adapter->hw.mac.type) {
7458 case ixgbe_mac_82599EB:
7459 case ixgbe_mac_X540:
7460 netdev->features |= NETIF_F_SCTP_CSUM;
7461 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7462 NETIF_F_NTUPLE;
7463 break;
7464 default:
7465 break;
7466 }
7467
7468 netdev->hw_features |= NETIF_F_RXALL;
7469
7470 netdev->vlan_features |= NETIF_F_TSO;
7471 netdev->vlan_features |= NETIF_F_TSO6;
7472 netdev->vlan_features |= NETIF_F_IP_CSUM;
7473 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7474 netdev->vlan_features |= NETIF_F_SG;
7475
7476 netdev->priv_flags |= IFF_UNICAST_FLT;
7477 netdev->priv_flags |= IFF_SUPP_NOFCS;
7478
7479 #ifdef CONFIG_IXGBE_DCB
7480 netdev->dcbnl_ops = &dcbnl_ops;
7481 #endif
7482
7483 #ifdef IXGBE_FCOE
7484 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7485 unsigned int fcoe_l;
7486
7487 if (hw->mac.ops.get_device_caps) {
7488 hw->mac.ops.get_device_caps(hw, &device_caps);
7489 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7490 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7491 }
7492
7493
7494 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7495 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7496
7497 netdev->features |= NETIF_F_FSO |
7498 NETIF_F_FCOE_CRC;
7499
7500 netdev->vlan_features |= NETIF_F_FSO |
7501 NETIF_F_FCOE_CRC |
7502 NETIF_F_FCOE_MTU;
7503 }
7504 #endif /* IXGBE_FCOE */
7505 if (pci_using_dac) {
7506 netdev->features |= NETIF_F_HIGHDMA;
7507 netdev->vlan_features |= NETIF_F_HIGHDMA;
7508 }
7509
7510 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7511 netdev->hw_features |= NETIF_F_LRO;
7512 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7513 netdev->features |= NETIF_F_LRO;
7514
7515 /* make sure the EEPROM is good */
7516 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7517 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7518 err = -EIO;
7519 goto err_sw_init;
7520 }
7521
7522 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7523
7524 if (!is_valid_ether_addr(netdev->dev_addr)) {
7525 e_dev_err("invalid MAC address\n");
7526 err = -EIO;
7527 goto err_sw_init;
7528 }
7529
7530 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7531 (unsigned long) adapter);
7532
7533 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7534 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7535
7536 err = ixgbe_init_interrupt_scheme(adapter);
7537 if (err)
7538 goto err_sw_init;
7539
7540 /* WOL not supported for all devices */
7541 adapter->wol = 0;
7542 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7543 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
7544 pdev->subsystem_device);
7545 if (hw->wol_enabled)
7546 adapter->wol = IXGBE_WUFC_MAG;
7547
7548 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7549
7550 /* save off EEPROM version number */
7551 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7552 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7553
7554 /* pick up the PCI bus settings for reporting later */
7555 hw->mac.ops.get_bus_info(hw);
7556 if (hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP)
7557 ixgbe_get_parent_bus_info(adapter);
7558
7559 /* print bus type/speed/width info */
7560 e_dev_info("(PCI Express:%s:%s) %pM\n",
7561 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7562 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7563 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7564 "Unknown"),
7565 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7566 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7567 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7568 "Unknown"),
7569 netdev->dev_addr);
7570
7571 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7572 if (err)
7573 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7574 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7575 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7576 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7577 part_str);
7578 else
7579 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7580 hw->mac.type, hw->phy.type, part_str);
7581
7582 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7583 e_dev_warn("PCI-Express bandwidth available for this card is "
7584 "not sufficient for optimal performance.\n");
7585 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7586 "is required.\n");
7587 }
7588
7589 /* reset the hardware with the new settings */
7590 err = hw->mac.ops.start_hw(hw);
7591 if (err == IXGBE_ERR_EEPROM_VERSION) {
7592 /* We are running on a pre-production device, log a warning */
7593 e_dev_warn("This device is a pre-production adapter/LOM. "
7594 "Please be aware there may be issues associated "
7595 "with your hardware. If you are experiencing "
7596 "problems please contact your Intel or hardware "
7597 "representative who provided you with this "
7598 "hardware.\n");
7599 }
7600 strcpy(netdev->name, "eth%d");
7601 err = register_netdev(netdev);
7602 if (err)
7603 goto err_register;
7604
7605 /* power down the optics for 82599 SFP+ fiber */
7606 if (hw->mac.ops.disable_tx_laser)
7607 hw->mac.ops.disable_tx_laser(hw);
7608
7609 /* carrier off reporting is important to ethtool even BEFORE open */
7610 netif_carrier_off(netdev);
7611
7612 #ifdef CONFIG_IXGBE_DCA
7613 if (dca_add_requester(&pdev->dev) == 0) {
7614 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7615 ixgbe_setup_dca(adapter);
7616 }
7617 #endif
7618 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7619 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7620 for (i = 0; i < adapter->num_vfs; i++)
7621 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7622 }
7623
7624 /* firmware requires driver version to be 0xFFFFFFFF
7625 * since os does not support feature
7626 */
7627 if (hw->mac.ops.set_fw_drv_ver)
7628 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7629 0xFF);
7630
7631 /* add san mac addr to netdev */
7632 ixgbe_add_sanmac_netdev(netdev);
7633
7634 e_dev_info("%s\n", ixgbe_default_device_descr);
7635 cards_found++;
7636
7637 #ifdef CONFIG_IXGBE_HWMON
7638 if (ixgbe_sysfs_init(adapter))
7639 e_err(probe, "failed to allocate sysfs resources\n");
7640 #endif /* CONFIG_IXGBE_HWMON */
7641
7642 ixgbe_dbg_adapter_init(adapter);
7643
7644 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7645 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7646 hw->mac.ops.setup_link(hw,
7647 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7648 true);
7649
7650 return 0;
7651
7652 err_register:
7653 ixgbe_release_hw_control(adapter);
7654 ixgbe_clear_interrupt_scheme(adapter);
7655 err_sw_init:
7656 ixgbe_disable_sriov(adapter);
7657 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7658 iounmap(hw->hw_addr);
7659 err_ioremap:
7660 free_netdev(netdev);
7661 err_alloc_etherdev:
7662 pci_release_selected_regions(pdev,
7663 pci_select_bars(pdev, IORESOURCE_MEM));
7664 err_pci_reg:
7665 err_dma:
7666 pci_disable_device(pdev);
7667 return err;
7668 }
7669
7670 /**
7671 * ixgbe_remove - Device Removal Routine
7672 * @pdev: PCI device information struct
7673 *
7674 * ixgbe_remove is called by the PCI subsystem to alert the driver
7675 * that it should release a PCI device. The could be caused by a
7676 * Hot-Plug event, or because the driver is going to be removed from
7677 * memory.
7678 **/
7679 static void ixgbe_remove(struct pci_dev *pdev)
7680 {
7681 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7682 struct net_device *netdev = adapter->netdev;
7683
7684 ixgbe_dbg_adapter_exit(adapter);
7685
7686 set_bit(__IXGBE_DOWN, &adapter->state);
7687 cancel_work_sync(&adapter->service_task);
7688
7689
7690 #ifdef CONFIG_IXGBE_DCA
7691 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7692 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7693 dca_remove_requester(&pdev->dev);
7694 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7695 }
7696
7697 #endif
7698 #ifdef CONFIG_IXGBE_HWMON
7699 ixgbe_sysfs_exit(adapter);
7700 #endif /* CONFIG_IXGBE_HWMON */
7701
7702 /* remove the added san mac */
7703 ixgbe_del_sanmac_netdev(netdev);
7704
7705 if (netdev->reg_state == NETREG_REGISTERED)
7706 unregister_netdev(netdev);
7707
7708 #ifdef CONFIG_PCI_IOV
7709 /*
7710 * Only disable SR-IOV on unload if the user specified the now
7711 * deprecated max_vfs module parameter.
7712 */
7713 if (max_vfs)
7714 ixgbe_disable_sriov(adapter);
7715 #endif
7716 ixgbe_clear_interrupt_scheme(adapter);
7717
7718 ixgbe_release_hw_control(adapter);
7719
7720 #ifdef CONFIG_DCB
7721 kfree(adapter->ixgbe_ieee_pfc);
7722 kfree(adapter->ixgbe_ieee_ets);
7723
7724 #endif
7725 iounmap(adapter->hw.hw_addr);
7726 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7727 IORESOURCE_MEM));
7728
7729 e_dev_info("complete\n");
7730
7731 free_netdev(netdev);
7732
7733 pci_disable_pcie_error_reporting(pdev);
7734
7735 pci_disable_device(pdev);
7736 }
7737
7738 /**
7739 * ixgbe_io_error_detected - called when PCI error is detected
7740 * @pdev: Pointer to PCI device
7741 * @state: The current pci connection state
7742 *
7743 * This function is called after a PCI bus error affecting
7744 * this device has been detected.
7745 */
7746 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7747 pci_channel_state_t state)
7748 {
7749 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7750 struct net_device *netdev = adapter->netdev;
7751
7752 #ifdef CONFIG_PCI_IOV
7753 struct pci_dev *bdev, *vfdev;
7754 u32 dw0, dw1, dw2, dw3;
7755 int vf, pos;
7756 u16 req_id, pf_func;
7757
7758 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7759 adapter->num_vfs == 0)
7760 goto skip_bad_vf_detection;
7761
7762 bdev = pdev->bus->self;
7763 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7764 bdev = bdev->bus->self;
7765
7766 if (!bdev)
7767 goto skip_bad_vf_detection;
7768
7769 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7770 if (!pos)
7771 goto skip_bad_vf_detection;
7772
7773 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7774 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7775 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7776 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7777
7778 req_id = dw1 >> 16;
7779 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7780 if (!(req_id & 0x0080))
7781 goto skip_bad_vf_detection;
7782
7783 pf_func = req_id & 0x01;
7784 if ((pf_func & 1) == (pdev->devfn & 1)) {
7785 unsigned int device_id;
7786
7787 vf = (req_id & 0x7F) >> 1;
7788 e_dev_err("VF %d has caused a PCIe error\n", vf);
7789 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7790 "%8.8x\tdw3: %8.8x\n",
7791 dw0, dw1, dw2, dw3);
7792 switch (adapter->hw.mac.type) {
7793 case ixgbe_mac_82599EB:
7794 device_id = IXGBE_82599_VF_DEVICE_ID;
7795 break;
7796 case ixgbe_mac_X540:
7797 device_id = IXGBE_X540_VF_DEVICE_ID;
7798 break;
7799 default:
7800 device_id = 0;
7801 break;
7802 }
7803
7804 /* Find the pci device of the offending VF */
7805 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7806 while (vfdev) {
7807 if (vfdev->devfn == (req_id & 0xFF))
7808 break;
7809 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7810 device_id, vfdev);
7811 }
7812 /*
7813 * There's a slim chance the VF could have been hot plugged,
7814 * so if it is no longer present we don't need to issue the
7815 * VFLR. Just clean up the AER in that case.
7816 */
7817 if (vfdev) {
7818 e_dev_err("Issuing VFLR to VF %d\n", vf);
7819 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7820 /* Free device reference count */
7821 pci_dev_put(vfdev);
7822 }
7823
7824 pci_cleanup_aer_uncorrect_error_status(pdev);
7825 }
7826
7827 /*
7828 * Even though the error may have occurred on the other port
7829 * we still need to increment the vf error reference count for
7830 * both ports because the I/O resume function will be called
7831 * for both of them.
7832 */
7833 adapter->vferr_refcount++;
7834
7835 return PCI_ERS_RESULT_RECOVERED;
7836
7837 skip_bad_vf_detection:
7838 #endif /* CONFIG_PCI_IOV */
7839 netif_device_detach(netdev);
7840
7841 if (state == pci_channel_io_perm_failure)
7842 return PCI_ERS_RESULT_DISCONNECT;
7843
7844 if (netif_running(netdev))
7845 ixgbe_down(adapter);
7846 pci_disable_device(pdev);
7847
7848 /* Request a slot reset. */
7849 return PCI_ERS_RESULT_NEED_RESET;
7850 }
7851
7852 /**
7853 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7854 * @pdev: Pointer to PCI device
7855 *
7856 * Restart the card from scratch, as if from a cold-boot.
7857 */
7858 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7859 {
7860 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7861 pci_ers_result_t result;
7862 int err;
7863
7864 if (pci_enable_device_mem(pdev)) {
7865 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7866 result = PCI_ERS_RESULT_DISCONNECT;
7867 } else {
7868 pci_set_master(pdev);
7869 pci_restore_state(pdev);
7870 pci_save_state(pdev);
7871
7872 pci_wake_from_d3(pdev, false);
7873
7874 ixgbe_reset(adapter);
7875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7876 result = PCI_ERS_RESULT_RECOVERED;
7877 }
7878
7879 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7880 if (err) {
7881 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7882 "failed 0x%0x\n", err);
7883 /* non-fatal, continue */
7884 }
7885
7886 return result;
7887 }
7888
7889 /**
7890 * ixgbe_io_resume - called when traffic can start flowing again.
7891 * @pdev: Pointer to PCI device
7892 *
7893 * This callback is called when the error recovery driver tells us that
7894 * its OK to resume normal operation.
7895 */
7896 static void ixgbe_io_resume(struct pci_dev *pdev)
7897 {
7898 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7899 struct net_device *netdev = adapter->netdev;
7900
7901 #ifdef CONFIG_PCI_IOV
7902 if (adapter->vferr_refcount) {
7903 e_info(drv, "Resuming after VF err\n");
7904 adapter->vferr_refcount--;
7905 return;
7906 }
7907
7908 #endif
7909 if (netif_running(netdev))
7910 ixgbe_up(adapter);
7911
7912 netif_device_attach(netdev);
7913 }
7914
7915 static const struct pci_error_handlers ixgbe_err_handler = {
7916 .error_detected = ixgbe_io_error_detected,
7917 .slot_reset = ixgbe_io_slot_reset,
7918 .resume = ixgbe_io_resume,
7919 };
7920
7921 static struct pci_driver ixgbe_driver = {
7922 .name = ixgbe_driver_name,
7923 .id_table = ixgbe_pci_tbl,
7924 .probe = ixgbe_probe,
7925 .remove = ixgbe_remove,
7926 #ifdef CONFIG_PM
7927 .suspend = ixgbe_suspend,
7928 .resume = ixgbe_resume,
7929 #endif
7930 .shutdown = ixgbe_shutdown,
7931 .sriov_configure = ixgbe_pci_sriov_configure,
7932 .err_handler = &ixgbe_err_handler
7933 };
7934
7935 /**
7936 * ixgbe_init_module - Driver Registration Routine
7937 *
7938 * ixgbe_init_module is the first routine called when the driver is
7939 * loaded. All it does is register with the PCI subsystem.
7940 **/
7941 static int __init ixgbe_init_module(void)
7942 {
7943 int ret;
7944 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7945 pr_info("%s\n", ixgbe_copyright);
7946
7947 ixgbe_dbg_init();
7948
7949 ret = pci_register_driver(&ixgbe_driver);
7950 if (ret) {
7951 ixgbe_dbg_exit();
7952 return ret;
7953 }
7954
7955 #ifdef CONFIG_IXGBE_DCA
7956 dca_register_notify(&dca_notifier);
7957 #endif
7958
7959 return 0;
7960 }
7961
7962 module_init(ixgbe_init_module);
7963
7964 /**
7965 * ixgbe_exit_module - Driver Exit Cleanup Routine
7966 *
7967 * ixgbe_exit_module is called just before the driver is removed
7968 * from memory.
7969 **/
7970 static void __exit ixgbe_exit_module(void)
7971 {
7972 #ifdef CONFIG_IXGBE_DCA
7973 dca_unregister_notify(&dca_notifier);
7974 #endif
7975 pci_unregister_driver(&ixgbe_driver);
7976
7977 ixgbe_dbg_exit();
7978
7979 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7980 }
7981
7982 #ifdef CONFIG_IXGBE_DCA
7983 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7984 void *p)
7985 {
7986 int ret_val;
7987
7988 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7989 __ixgbe_notify_dca);
7990
7991 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7992 }
7993
7994 #endif /* CONFIG_IXGBE_DCA */
7995
7996 module_exit(ixgbe_exit_module);
7997
7998 /* ixgbe_main.c */
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