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ixgbe: add setlink, getlink support to ixgbe and ixgbevf
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define MAJ 3
67 #define MIN 9
68 #define BUILD 15
69 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
70 __stringify(BUILD) "-k"
71 const char ixgbe_driver_version[] = DRV_VERSION;
72 static const char ixgbe_copyright[] =
73 "Copyright (c) 1999-2012 Intel Corporation.";
74
75 static const struct ixgbe_info *ixgbe_info_tbl[] = {
76 [board_82598] = &ixgbe_82598_info,
77 [board_82599] = &ixgbe_82599_info,
78 [board_X540] = &ixgbe_X540_info,
79 };
80
81 /* ixgbe_pci_tbl - PCI Device ID Table
82 *
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
85 *
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
88 */
89 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
119 /* required last entry */
120 {0, }
121 };
122 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
123
124 #ifdef CONFIG_IXGBE_DCA
125 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
126 void *p);
127 static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
129 .next = NULL,
130 .priority = 0
131 };
132 #endif
133
134 #ifdef CONFIG_PCI_IOV
135 static unsigned int max_vfs;
136 module_param(max_vfs, uint, 0);
137 MODULE_PARM_DESC(max_vfs,
138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
139 #endif /* CONFIG_PCI_IOV */
140
141 static unsigned int allow_unsupported_sfp;
142 module_param(allow_unsupported_sfp, uint, 0);
143 MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
145
146 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147 static int debug = -1;
148 module_param(debug, int, 0);
149 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
150
151 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153 MODULE_LICENSE("GPL");
154 MODULE_VERSION(DRV_VERSION);
155
156 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
157 {
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
161 }
162
163 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
164 {
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
166
167 /* flush memory to make sure state is correct before next watchdog */
168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
170 }
171
172 struct ixgbe_reg_info {
173 u32 ofs;
174 char *name;
175 };
176
177 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
178
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
183
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
186
187 /* RX Registers */
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
196
197 /* TX Registers */
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
204
205 /* List Terminator */
206 {}
207 };
208
209
210 /*
211 * ixgbe_regdump - register printout routine
212 */
213 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
214 {
215 int i = 0, j = 0;
216 char rname[16];
217 u32 regs[64];
218
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
223 break;
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
227 break;
228 case IXGBE_RDLEN(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
231 break;
232 case IXGBE_RDH(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
235 break;
236 case IXGBE_RDT(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
239 break;
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
243 break;
244 case IXGBE_RDBAL(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
247 break;
248 case IXGBE_RDBAH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
251 break;
252 case IXGBE_TDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
255 break;
256 case IXGBE_TDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
259 break;
260 case IXGBE_TDLEN(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
263 break;
264 case IXGBE_TDH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
267 break;
268 case IXGBE_TDT(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
271 break;
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
275 break;
276 default:
277 pr_info("%-15s %08x\n", reginfo->name,
278 IXGBE_READ_REG(hw, reginfo->ofs));
279 return;
280 }
281
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
284 pr_err("%-15s", rname);
285 for (j = 0; j < 8; j++)
286 pr_cont(" %08x", regs[i*8+j]);
287 pr_cont("\n");
288 }
289
290 }
291
292 /*
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
294 */
295 static void ixgbe_dump(struct ixgbe_adapter *adapter)
296 {
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
300 int n = 0;
301 struct ixgbe_ring *tx_ring;
302 struct ixgbe_tx_buffer *tx_buffer;
303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
308 u32 staterr;
309 int i = 0;
310
311 if (!netif_msg_hw(adapter))
312 return;
313
314 /* Print netdevice Info */
315 if (netdev) {
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
317 pr_info("Device Name state "
318 "trans_start last_rx\n");
319 pr_info("%-15s %016lX %016lX %016lX\n",
320 netdev->name,
321 netdev->state,
322 netdev->trans_start,
323 netdev->last_rx);
324 }
325
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
328 pr_info(" Register Name Value\n");
329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
332 }
333
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
336 goto exit;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
339 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
340 for (n = 0; n < adapter->num_tx_queues; n++) {
341 tx_ring = adapter->tx_ring[n];
342 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
343 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
344 n, tx_ring->next_to_use, tx_ring->next_to_clean,
345 (u64)dma_unmap_addr(tx_buffer, dma),
346 dma_unmap_len(tx_buffer, len),
347 tx_buffer->next_to_watch,
348 (u64)tx_buffer->time_stamp);
349 }
350
351 /* Print TX Rings */
352 if (!netif_msg_tx_done(adapter))
353 goto rx_ring_summary;
354
355 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
356
357 /* Transmit Descriptor Formats
358 *
359 * Advanced Transmit Descriptor
360 * +--------------------------------------------------------------+
361 * 0 | Buffer Address [63:0] |
362 * +--------------------------------------------------------------+
363 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
364 * +--------------------------------------------------------------+
365 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
366 */
367
368 for (n = 0; n < adapter->num_tx_queues; n++) {
369 tx_ring = adapter->tx_ring[n];
370 pr_info("------------------------------------\n");
371 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
372 pr_info("------------------------------------\n");
373 pr_info("T [desc] [address 63:0 ] "
374 "[PlPOIdStDDt Ln] [bi->dma ] "
375 "leng ntw timestamp bi->skb\n");
376
377 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
378 tx_desc = IXGBE_TX_DESC(tx_ring, i);
379 tx_buffer = &tx_ring->tx_buffer_info[i];
380 u0 = (struct my_u0 *)tx_desc;
381 pr_info("T [0x%03X] %016llX %016llX %016llX"
382 " %04X %p %016llX %p", i,
383 le64_to_cpu(u0->a),
384 le64_to_cpu(u0->b),
385 (u64)dma_unmap_addr(tx_buffer, dma),
386 dma_unmap_len(tx_buffer, len),
387 tx_buffer->next_to_watch,
388 (u64)tx_buffer->time_stamp,
389 tx_buffer->skb);
390 if (i == tx_ring->next_to_use &&
391 i == tx_ring->next_to_clean)
392 pr_cont(" NTC/U\n");
393 else if (i == tx_ring->next_to_use)
394 pr_cont(" NTU\n");
395 else if (i == tx_ring->next_to_clean)
396 pr_cont(" NTC\n");
397 else
398 pr_cont("\n");
399
400 if (netif_msg_pktdata(adapter) &&
401 tx_buffer->skb)
402 print_hex_dump(KERN_INFO, "",
403 DUMP_PREFIX_ADDRESS, 16, 1,
404 tx_buffer->skb->data,
405 dma_unmap_len(tx_buffer, len),
406 true);
407 }
408 }
409
410 /* Print RX Rings Summary */
411 rx_ring_summary:
412 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
413 pr_info("Queue [NTU] [NTC]\n");
414 for (n = 0; n < adapter->num_rx_queues; n++) {
415 rx_ring = adapter->rx_ring[n];
416 pr_info("%5d %5X %5X\n",
417 n, rx_ring->next_to_use, rx_ring->next_to_clean);
418 }
419
420 /* Print RX Rings */
421 if (!netif_msg_rx_status(adapter))
422 goto exit;
423
424 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
425
426 /* Advanced Receive Descriptor (Read) Format
427 * 63 1 0
428 * +-----------------------------------------------------+
429 * 0 | Packet Buffer Address [63:1] |A0/NSE|
430 * +----------------------------------------------+------+
431 * 8 | Header Buffer Address [63:1] | DD |
432 * +-----------------------------------------------------+
433 *
434 *
435 * Advanced Receive Descriptor (Write-Back) Format
436 *
437 * 63 48 47 32 31 30 21 20 16 15 4 3 0
438 * +------------------------------------------------------+
439 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
440 * | Checksum Ident | | | | Type | Type |
441 * +------------------------------------------------------+
442 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
443 * +------------------------------------------------------+
444 * 63 48 47 32 31 20 19 0
445 */
446 for (n = 0; n < adapter->num_rx_queues; n++) {
447 rx_ring = adapter->rx_ring[n];
448 pr_info("------------------------------------\n");
449 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
450 pr_info("------------------------------------\n");
451 pr_info("R [desc] [ PktBuf A0] "
452 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
453 "<-- Adv Rx Read format\n");
454 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
455 "[vl er S cks ln] ---------------- [bi->skb] "
456 "<-- Adv Rx Write-Back format\n");
457
458 for (i = 0; i < rx_ring->count; i++) {
459 rx_buffer_info = &rx_ring->rx_buffer_info[i];
460 rx_desc = IXGBE_RX_DESC(rx_ring, i);
461 u0 = (struct my_u0 *)rx_desc;
462 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
463 if (staterr & IXGBE_RXD_STAT_DD) {
464 /* Descriptor Done */
465 pr_info("RWB[0x%03X] %016llX "
466 "%016llX ---------------- %p", i,
467 le64_to_cpu(u0->a),
468 le64_to_cpu(u0->b),
469 rx_buffer_info->skb);
470 } else {
471 pr_info("R [0x%03X] %016llX "
472 "%016llX %016llX %p", i,
473 le64_to_cpu(u0->a),
474 le64_to_cpu(u0->b),
475 (u64)rx_buffer_info->dma,
476 rx_buffer_info->skb);
477
478 if (netif_msg_pktdata(adapter) &&
479 rx_buffer_info->dma) {
480 print_hex_dump(KERN_INFO, "",
481 DUMP_PREFIX_ADDRESS, 16, 1,
482 page_address(rx_buffer_info->page) +
483 rx_buffer_info->page_offset,
484 ixgbe_rx_bufsz(rx_ring), true);
485 }
486 }
487
488 if (i == rx_ring->next_to_use)
489 pr_cont(" NTU\n");
490 else if (i == rx_ring->next_to_clean)
491 pr_cont(" NTC\n");
492 else
493 pr_cont("\n");
494
495 }
496 }
497
498 exit:
499 return;
500 }
501
502 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
503 {
504 u32 ctrl_ext;
505
506 /* Let firmware take over control of h/w */
507 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
509 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
510 }
511
512 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
513 {
514 u32 ctrl_ext;
515
516 /* Let firmware know the driver has taken over */
517 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
518 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
519 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
520 }
521
522 /**
523 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
524 * @adapter: pointer to adapter struct
525 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
526 * @queue: queue to map the corresponding interrupt to
527 * @msix_vector: the vector to map to the corresponding queue
528 *
529 */
530 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
531 u8 queue, u8 msix_vector)
532 {
533 u32 ivar, index;
534 struct ixgbe_hw *hw = &adapter->hw;
535 switch (hw->mac.type) {
536 case ixgbe_mac_82598EB:
537 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
538 if (direction == -1)
539 direction = 0;
540 index = (((direction * 64) + queue) >> 2) & 0x1F;
541 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
542 ivar &= ~(0xFF << (8 * (queue & 0x3)));
543 ivar |= (msix_vector << (8 * (queue & 0x3)));
544 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
545 break;
546 case ixgbe_mac_82599EB:
547 case ixgbe_mac_X540:
548 if (direction == -1) {
549 /* other causes */
550 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
551 index = ((queue & 1) * 8);
552 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
553 ivar &= ~(0xFF << index);
554 ivar |= (msix_vector << index);
555 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
556 break;
557 } else {
558 /* tx or rx causes */
559 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
560 index = ((16 * (queue & 1)) + (8 * direction));
561 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
562 ivar &= ~(0xFF << index);
563 ivar |= (msix_vector << index);
564 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
565 break;
566 }
567 default:
568 break;
569 }
570 }
571
572 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
573 u64 qmask)
574 {
575 u32 mask;
576
577 switch (adapter->hw.mac.type) {
578 case ixgbe_mac_82598EB:
579 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
581 break;
582 case ixgbe_mac_82599EB:
583 case ixgbe_mac_X540:
584 mask = (qmask & 0xFFFFFFFF);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
586 mask = (qmask >> 32);
587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
588 break;
589 default:
590 break;
591 }
592 }
593
594 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
595 struct ixgbe_tx_buffer *tx_buffer)
596 {
597 if (tx_buffer->skb) {
598 dev_kfree_skb_any(tx_buffer->skb);
599 if (dma_unmap_len(tx_buffer, len))
600 dma_unmap_single(ring->dev,
601 dma_unmap_addr(tx_buffer, dma),
602 dma_unmap_len(tx_buffer, len),
603 DMA_TO_DEVICE);
604 } else if (dma_unmap_len(tx_buffer, len)) {
605 dma_unmap_page(ring->dev,
606 dma_unmap_addr(tx_buffer, dma),
607 dma_unmap_len(tx_buffer, len),
608 DMA_TO_DEVICE);
609 }
610 tx_buffer->next_to_watch = NULL;
611 tx_buffer->skb = NULL;
612 dma_unmap_len_set(tx_buffer, len, 0);
613 /* tx_buffer must be completely set up in the transmit path */
614 }
615
616 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
617 {
618 struct ixgbe_hw *hw = &adapter->hw;
619 struct ixgbe_hw_stats *hwstats = &adapter->stats;
620 int i;
621 u32 data;
622
623 if ((hw->fc.current_mode != ixgbe_fc_full) &&
624 (hw->fc.current_mode != ixgbe_fc_rx_pause))
625 return;
626
627 switch (hw->mac.type) {
628 case ixgbe_mac_82598EB:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
630 break;
631 default:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
633 }
634 hwstats->lxoffrxc += data;
635
636 /* refill credits (no tx hang) if we received xoff */
637 if (!data)
638 return;
639
640 for (i = 0; i < adapter->num_tx_queues; i++)
641 clear_bit(__IXGBE_HANG_CHECK_ARMED,
642 &adapter->tx_ring[i]->state);
643 }
644
645 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
646 {
647 struct ixgbe_hw *hw = &adapter->hw;
648 struct ixgbe_hw_stats *hwstats = &adapter->stats;
649 u32 xoff[8] = {0};
650 int i;
651 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
652
653 if (adapter->ixgbe_ieee_pfc)
654 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
655
656 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
657 ixgbe_update_xoff_rx_lfc(adapter);
658 return;
659 }
660
661 /* update stats for each tc, only valid with PFC enabled */
662 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
663 switch (hw->mac.type) {
664 case ixgbe_mac_82598EB:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
666 break;
667 default:
668 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
669 }
670 hwstats->pxoffrxc[i] += xoff[i];
671 }
672
673 /* disarm tx queues that have received xoff frames */
674 for (i = 0; i < adapter->num_tx_queues; i++) {
675 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
676 u8 tc = tx_ring->dcb_tc;
677
678 if (xoff[tc])
679 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
680 }
681 }
682
683 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
684 {
685 return ring->stats.packets;
686 }
687
688 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
689 {
690 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
691 struct ixgbe_hw *hw = &adapter->hw;
692
693 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
694 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
695
696 if (head != tail)
697 return (head < tail) ?
698 tail - head : (tail + ring->count - head);
699
700 return 0;
701 }
702
703 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
704 {
705 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
706 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
707 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
708 bool ret = false;
709
710 clear_check_for_tx_hang(tx_ring);
711
712 /*
713 * Check for a hung queue, but be thorough. This verifies
714 * that a transmit has been completed since the previous
715 * check AND there is at least one packet pending. The
716 * ARMED bit is set to indicate a potential hang. The
717 * bit is cleared if a pause frame is received to remove
718 * false hang detection due to PFC or 802.3x frames. By
719 * requiring this to fail twice we avoid races with
720 * pfc clearing the ARMED bit and conditions where we
721 * run the check_tx_hang logic with a transmit completion
722 * pending but without time to complete it yet.
723 */
724 if ((tx_done_old == tx_done) && tx_pending) {
725 /* make sure it is true for two checks in a row */
726 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
727 &tx_ring->state);
728 } else {
729 /* update completed stats and continue */
730 tx_ring->tx_stats.tx_done_old = tx_done;
731 /* reset the countdown */
732 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
733 }
734
735 return ret;
736 }
737
738 /**
739 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
740 * @adapter: driver private struct
741 **/
742 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
743 {
744
745 /* Do the reset outside of interrupt context */
746 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
747 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
748 ixgbe_service_event_schedule(adapter);
749 }
750 }
751
752 /**
753 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
754 * @q_vector: structure containing interrupt and ring information
755 * @tx_ring: tx ring to clean
756 **/
757 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
758 struct ixgbe_ring *tx_ring)
759 {
760 struct ixgbe_adapter *adapter = q_vector->adapter;
761 struct ixgbe_tx_buffer *tx_buffer;
762 union ixgbe_adv_tx_desc *tx_desc;
763 unsigned int total_bytes = 0, total_packets = 0;
764 unsigned int budget = q_vector->tx.work_limit;
765 unsigned int i = tx_ring->next_to_clean;
766
767 if (test_bit(__IXGBE_DOWN, &adapter->state))
768 return true;
769
770 tx_buffer = &tx_ring->tx_buffer_info[i];
771 tx_desc = IXGBE_TX_DESC(tx_ring, i);
772 i -= tx_ring->count;
773
774 do {
775 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
776
777 /* if next_to_watch is not set then there is no work pending */
778 if (!eop_desc)
779 break;
780
781 /* prevent any other reads prior to eop_desc */
782 rmb();
783
784 /* if DD is not set pending work has not been completed */
785 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
786 break;
787
788 /* clear next_to_watch to prevent false hangs */
789 tx_buffer->next_to_watch = NULL;
790
791 /* update the statistics for this packet */
792 total_bytes += tx_buffer->bytecount;
793 total_packets += tx_buffer->gso_segs;
794
795 #ifdef CONFIG_IXGBE_PTP
796 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
797 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
798 #endif
799
800 /* free the skb */
801 dev_kfree_skb_any(tx_buffer->skb);
802
803 /* unmap skb header data */
804 dma_unmap_single(tx_ring->dev,
805 dma_unmap_addr(tx_buffer, dma),
806 dma_unmap_len(tx_buffer, len),
807 DMA_TO_DEVICE);
808
809 /* clear tx_buffer data */
810 tx_buffer->skb = NULL;
811 dma_unmap_len_set(tx_buffer, len, 0);
812
813 /* unmap remaining buffers */
814 while (tx_desc != eop_desc) {
815 tx_buffer++;
816 tx_desc++;
817 i++;
818 if (unlikely(!i)) {
819 i -= tx_ring->count;
820 tx_buffer = tx_ring->tx_buffer_info;
821 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
822 }
823
824 /* unmap any remaining paged data */
825 if (dma_unmap_len(tx_buffer, len)) {
826 dma_unmap_page(tx_ring->dev,
827 dma_unmap_addr(tx_buffer, dma),
828 dma_unmap_len(tx_buffer, len),
829 DMA_TO_DEVICE);
830 dma_unmap_len_set(tx_buffer, len, 0);
831 }
832 }
833
834 /* move us one more past the eop_desc for start of next pkt */
835 tx_buffer++;
836 tx_desc++;
837 i++;
838 if (unlikely(!i)) {
839 i -= tx_ring->count;
840 tx_buffer = tx_ring->tx_buffer_info;
841 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
842 }
843
844 /* issue prefetch for next Tx descriptor */
845 prefetch(tx_desc);
846
847 /* update budget accounting */
848 budget--;
849 } while (likely(budget));
850
851 i += tx_ring->count;
852 tx_ring->next_to_clean = i;
853 u64_stats_update_begin(&tx_ring->syncp);
854 tx_ring->stats.bytes += total_bytes;
855 tx_ring->stats.packets += total_packets;
856 u64_stats_update_end(&tx_ring->syncp);
857 q_vector->tx.total_bytes += total_bytes;
858 q_vector->tx.total_packets += total_packets;
859
860 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
861 /* schedule immediate reset if we believe we hung */
862 struct ixgbe_hw *hw = &adapter->hw;
863 e_err(drv, "Detected Tx Unit Hang\n"
864 " Tx Queue <%d>\n"
865 " TDH, TDT <%x>, <%x>\n"
866 " next_to_use <%x>\n"
867 " next_to_clean <%x>\n"
868 "tx_buffer_info[next_to_clean]\n"
869 " time_stamp <%lx>\n"
870 " jiffies <%lx>\n",
871 tx_ring->queue_index,
872 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
873 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
874 tx_ring->next_to_use, i,
875 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
876
877 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
878
879 e_info(probe,
880 "tx hang %d detected on queue %d, resetting adapter\n",
881 adapter->tx_timeout_count + 1, tx_ring->queue_index);
882
883 /* schedule immediate reset if we believe we hung */
884 ixgbe_tx_timeout_reset(adapter);
885
886 /* the adapter is about to reset, no point in enabling stuff */
887 return true;
888 }
889
890 netdev_tx_completed_queue(txring_txq(tx_ring),
891 total_packets, total_bytes);
892
893 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
894 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
895 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
896 /* Make sure that anybody stopping the queue after this
897 * sees the new next_to_clean.
898 */
899 smp_mb();
900 if (__netif_subqueue_stopped(tx_ring->netdev,
901 tx_ring->queue_index)
902 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
903 netif_wake_subqueue(tx_ring->netdev,
904 tx_ring->queue_index);
905 ++tx_ring->tx_stats.restart_queue;
906 }
907 }
908
909 return !!budget;
910 }
911
912 #ifdef CONFIG_IXGBE_DCA
913 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
914 struct ixgbe_ring *tx_ring,
915 int cpu)
916 {
917 struct ixgbe_hw *hw = &adapter->hw;
918 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
919 u16 reg_offset;
920
921 switch (hw->mac.type) {
922 case ixgbe_mac_82598EB:
923 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
924 break;
925 case ixgbe_mac_82599EB:
926 case ixgbe_mac_X540:
927 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
928 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
929 break;
930 default:
931 /* for unknown hardware do not write register */
932 return;
933 }
934
935 /*
936 * We can enable relaxed ordering for reads, but not writes when
937 * DCA is enabled. This is due to a known issue in some chipsets
938 * which will cause the DCA tag to be cleared.
939 */
940 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
941 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
942 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
943
944 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
945 }
946
947 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
948 struct ixgbe_ring *rx_ring,
949 int cpu)
950 {
951 struct ixgbe_hw *hw = &adapter->hw;
952 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
953 u8 reg_idx = rx_ring->reg_idx;
954
955
956 switch (hw->mac.type) {
957 case ixgbe_mac_82599EB:
958 case ixgbe_mac_X540:
959 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
960 break;
961 default:
962 break;
963 }
964
965 /*
966 * We can enable relaxed ordering for reads, but not writes when
967 * DCA is enabled. This is due to a known issue in some chipsets
968 * which will cause the DCA tag to be cleared.
969 */
970 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
971 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
972 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
973
974 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
975 }
976
977 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
978 {
979 struct ixgbe_adapter *adapter = q_vector->adapter;
980 struct ixgbe_ring *ring;
981 int cpu = get_cpu();
982
983 if (q_vector->cpu == cpu)
984 goto out_no_update;
985
986 ixgbe_for_each_ring(ring, q_vector->tx)
987 ixgbe_update_tx_dca(adapter, ring, cpu);
988
989 ixgbe_for_each_ring(ring, q_vector->rx)
990 ixgbe_update_rx_dca(adapter, ring, cpu);
991
992 q_vector->cpu = cpu;
993 out_no_update:
994 put_cpu();
995 }
996
997 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
998 {
999 int i;
1000
1001 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1002 return;
1003
1004 /* always use CB2 mode, difference is masked in the CB driver */
1005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1006
1007 for (i = 0; i < adapter->num_q_vectors; i++) {
1008 adapter->q_vector[i]->cpu = -1;
1009 ixgbe_update_dca(adapter->q_vector[i]);
1010 }
1011 }
1012
1013 static int __ixgbe_notify_dca(struct device *dev, void *data)
1014 {
1015 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1016 unsigned long event = *(unsigned long *)data;
1017
1018 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1019 return 0;
1020
1021 switch (event) {
1022 case DCA_PROVIDER_ADD:
1023 /* if we're already enabled, don't do it again */
1024 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1025 break;
1026 if (dca_add_requester(dev) == 0) {
1027 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1028 ixgbe_setup_dca(adapter);
1029 break;
1030 }
1031 /* Fall Through since DCA is disabled. */
1032 case DCA_PROVIDER_REMOVE:
1033 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1034 dca_remove_requester(dev);
1035 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1036 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1037 }
1038 break;
1039 }
1040
1041 return 0;
1042 }
1043
1044 #endif /* CONFIG_IXGBE_DCA */
1045 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1046 union ixgbe_adv_rx_desc *rx_desc,
1047 struct sk_buff *skb)
1048 {
1049 if (ring->netdev->features & NETIF_F_RXHASH)
1050 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1051 }
1052
1053 #ifdef IXGBE_FCOE
1054 /**
1055 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1056 * @ring: structure containing ring specific data
1057 * @rx_desc: advanced rx descriptor
1058 *
1059 * Returns : true if it is FCoE pkt
1060 */
1061 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1062 union ixgbe_adv_rx_desc *rx_desc)
1063 {
1064 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1065
1066 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1067 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1068 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1069 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1070 }
1071
1072 #endif /* IXGBE_FCOE */
1073 /**
1074 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1075 * @ring: structure containing ring specific data
1076 * @rx_desc: current Rx descriptor being processed
1077 * @skb: skb currently being received and modified
1078 **/
1079 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1080 union ixgbe_adv_rx_desc *rx_desc,
1081 struct sk_buff *skb)
1082 {
1083 skb_checksum_none_assert(skb);
1084
1085 /* Rx csum disabled */
1086 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1087 return;
1088
1089 /* if IP and error */
1090 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1091 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1092 ring->rx_stats.csum_err++;
1093 return;
1094 }
1095
1096 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1097 return;
1098
1099 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1100 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1101
1102 /*
1103 * 82599 errata, UDP frames with a 0 checksum can be marked as
1104 * checksum errors.
1105 */
1106 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1107 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1108 return;
1109
1110 ring->rx_stats.csum_err++;
1111 return;
1112 }
1113
1114 /* It must be a TCP or UDP packet with a valid checksum */
1115 skb->ip_summed = CHECKSUM_UNNECESSARY;
1116 }
1117
1118 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1119 {
1120 rx_ring->next_to_use = val;
1121
1122 /* update next to alloc since we have filled the ring */
1123 rx_ring->next_to_alloc = val;
1124 /*
1125 * Force memory writes to complete before letting h/w
1126 * know there are new descriptors to fetch. (Only
1127 * applicable for weak-ordered memory model archs,
1128 * such as IA-64).
1129 */
1130 wmb();
1131 writel(val, rx_ring->tail);
1132 }
1133
1134 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1135 struct ixgbe_rx_buffer *bi)
1136 {
1137 struct page *page = bi->page;
1138 dma_addr_t dma = bi->dma;
1139
1140 /* since we are recycling buffers we should seldom need to alloc */
1141 if (likely(dma))
1142 return true;
1143
1144 /* alloc new page for storage */
1145 if (likely(!page)) {
1146 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1147 bi->skb, ixgbe_rx_pg_order(rx_ring));
1148 if (unlikely(!page)) {
1149 rx_ring->rx_stats.alloc_rx_page_failed++;
1150 return false;
1151 }
1152 bi->page = page;
1153 }
1154
1155 /* map page for use */
1156 dma = dma_map_page(rx_ring->dev, page, 0,
1157 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1158
1159 /*
1160 * if mapping failed free memory back to system since
1161 * there isn't much point in holding memory we can't use
1162 */
1163 if (dma_mapping_error(rx_ring->dev, dma)) {
1164 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1165 bi->page = NULL;
1166
1167 rx_ring->rx_stats.alloc_rx_page_failed++;
1168 return false;
1169 }
1170
1171 bi->dma = dma;
1172 bi->page_offset = 0;
1173
1174 return true;
1175 }
1176
1177 /**
1178 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1179 * @rx_ring: ring to place buffers on
1180 * @cleaned_count: number of buffers to replace
1181 **/
1182 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1183 {
1184 union ixgbe_adv_rx_desc *rx_desc;
1185 struct ixgbe_rx_buffer *bi;
1186 u16 i = rx_ring->next_to_use;
1187
1188 /* nothing to do */
1189 if (!cleaned_count)
1190 return;
1191
1192 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1193 bi = &rx_ring->rx_buffer_info[i];
1194 i -= rx_ring->count;
1195
1196 do {
1197 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1198 break;
1199
1200 /*
1201 * Refresh the desc even if buffer_addrs didn't change
1202 * because each write-back erases this info.
1203 */
1204 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1205
1206 rx_desc++;
1207 bi++;
1208 i++;
1209 if (unlikely(!i)) {
1210 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1211 bi = rx_ring->rx_buffer_info;
1212 i -= rx_ring->count;
1213 }
1214
1215 /* clear the hdr_addr for the next_to_use descriptor */
1216 rx_desc->read.hdr_addr = 0;
1217
1218 cleaned_count--;
1219 } while (cleaned_count);
1220
1221 i += rx_ring->count;
1222
1223 if (rx_ring->next_to_use != i)
1224 ixgbe_release_rx_desc(rx_ring, i);
1225 }
1226
1227 /**
1228 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1229 * @data: pointer to the start of the headers
1230 * @max_len: total length of section to find headers in
1231 *
1232 * This function is meant to determine the length of headers that will
1233 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1234 * motivation of doing this is to only perform one pull for IPv4 TCP
1235 * packets so that we can do basic things like calculating the gso_size
1236 * based on the average data per packet.
1237 **/
1238 static unsigned int ixgbe_get_headlen(unsigned char *data,
1239 unsigned int max_len)
1240 {
1241 union {
1242 unsigned char *network;
1243 /* l2 headers */
1244 struct ethhdr *eth;
1245 struct vlan_hdr *vlan;
1246 /* l3 headers */
1247 struct iphdr *ipv4;
1248 struct ipv6hdr *ipv6;
1249 } hdr;
1250 __be16 protocol;
1251 u8 nexthdr = 0; /* default to not TCP */
1252 u8 hlen;
1253
1254 /* this should never happen, but better safe than sorry */
1255 if (max_len < ETH_HLEN)
1256 return max_len;
1257
1258 /* initialize network frame pointer */
1259 hdr.network = data;
1260
1261 /* set first protocol and move network header forward */
1262 protocol = hdr.eth->h_proto;
1263 hdr.network += ETH_HLEN;
1264
1265 /* handle any vlan tag if present */
1266 if (protocol == __constant_htons(ETH_P_8021Q)) {
1267 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1268 return max_len;
1269
1270 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1271 hdr.network += VLAN_HLEN;
1272 }
1273
1274 /* handle L3 protocols */
1275 if (protocol == __constant_htons(ETH_P_IP)) {
1276 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1277 return max_len;
1278
1279 /* access ihl as a u8 to avoid unaligned access on ia64 */
1280 hlen = (hdr.network[0] & 0x0F) << 2;
1281
1282 /* verify hlen meets minimum size requirements */
1283 if (hlen < sizeof(struct iphdr))
1284 return hdr.network - data;
1285
1286 /* record next protocol */
1287 nexthdr = hdr.ipv4->protocol;
1288 hdr.network += hlen;
1289 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1290 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1291 return max_len;
1292
1293 /* record next protocol */
1294 nexthdr = hdr.ipv6->nexthdr;
1295 hdr.network += sizeof(struct ipv6hdr);
1296 #ifdef IXGBE_FCOE
1297 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1298 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1299 return max_len;
1300 hdr.network += FCOE_HEADER_LEN;
1301 #endif
1302 } else {
1303 return hdr.network - data;
1304 }
1305
1306 /* finally sort out TCP/UDP */
1307 if (nexthdr == IPPROTO_TCP) {
1308 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1309 return max_len;
1310
1311 /* access doff as a u8 to avoid unaligned access on ia64 */
1312 hlen = (hdr.network[12] & 0xF0) >> 2;
1313
1314 /* verify hlen meets minimum size requirements */
1315 if (hlen < sizeof(struct tcphdr))
1316 return hdr.network - data;
1317
1318 hdr.network += hlen;
1319 } else if (nexthdr == IPPROTO_UDP) {
1320 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1321 return max_len;
1322
1323 hdr.network += sizeof(struct udphdr);
1324 }
1325
1326 /*
1327 * If everything has gone correctly hdr.network should be the
1328 * data section of the packet and will be the end of the header.
1329 * If not then it probably represents the end of the last recognized
1330 * header.
1331 */
1332 if ((hdr.network - data) < max_len)
1333 return hdr.network - data;
1334 else
1335 return max_len;
1336 }
1337
1338 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1339 struct sk_buff *skb)
1340 {
1341 u16 hdr_len = skb_headlen(skb);
1342
1343 /* set gso_size to avoid messing up TCP MSS */
1344 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1345 IXGBE_CB(skb)->append_cnt);
1346 }
1347
1348 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1349 struct sk_buff *skb)
1350 {
1351 /* if append_cnt is 0 then frame is not RSC */
1352 if (!IXGBE_CB(skb)->append_cnt)
1353 return;
1354
1355 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1356 rx_ring->rx_stats.rsc_flush++;
1357
1358 ixgbe_set_rsc_gso_size(rx_ring, skb);
1359
1360 /* gso_size is computed using append_cnt so always clear it last */
1361 IXGBE_CB(skb)->append_cnt = 0;
1362 }
1363
1364 /**
1365 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1366 * @rx_ring: rx descriptor ring packet is being transacted on
1367 * @rx_desc: pointer to the EOP Rx descriptor
1368 * @skb: pointer to current skb being populated
1369 *
1370 * This function checks the ring, descriptor, and packet information in
1371 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1372 * other fields within the skb.
1373 **/
1374 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1375 union ixgbe_adv_rx_desc *rx_desc,
1376 struct sk_buff *skb)
1377 {
1378 struct net_device *dev = rx_ring->netdev;
1379
1380 ixgbe_update_rsc_stats(rx_ring, skb);
1381
1382 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1383
1384 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1385
1386 #ifdef CONFIG_IXGBE_PTP
1387 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1388 #endif
1389
1390 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1391 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1392 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1393 __vlan_hwaccel_put_tag(skb, vid);
1394 }
1395
1396 skb_record_rx_queue(skb, rx_ring->queue_index);
1397
1398 skb->protocol = eth_type_trans(skb, dev);
1399 }
1400
1401 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1402 struct sk_buff *skb)
1403 {
1404 struct ixgbe_adapter *adapter = q_vector->adapter;
1405
1406 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1407 napi_gro_receive(&q_vector->napi, skb);
1408 else
1409 netif_rx(skb);
1410 }
1411
1412 /**
1413 * ixgbe_is_non_eop - process handling of non-EOP buffers
1414 * @rx_ring: Rx ring being processed
1415 * @rx_desc: Rx descriptor for current buffer
1416 * @skb: Current socket buffer containing buffer in progress
1417 *
1418 * This function updates next to clean. If the buffer is an EOP buffer
1419 * this function exits returning false, otherwise it will place the
1420 * sk_buff in the next buffer to be chained and return true indicating
1421 * that this is in fact a non-EOP buffer.
1422 **/
1423 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1424 union ixgbe_adv_rx_desc *rx_desc,
1425 struct sk_buff *skb)
1426 {
1427 u32 ntc = rx_ring->next_to_clean + 1;
1428
1429 /* fetch, update, and store next to clean */
1430 ntc = (ntc < rx_ring->count) ? ntc : 0;
1431 rx_ring->next_to_clean = ntc;
1432
1433 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1434
1435 /* update RSC append count if present */
1436 if (ring_is_rsc_enabled(rx_ring)) {
1437 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1438 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1439
1440 if (unlikely(rsc_enabled)) {
1441 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1442
1443 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1444 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1445
1446 /* update ntc based on RSC value */
1447 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1448 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1449 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1450 }
1451 }
1452
1453 /* if we are the last buffer then there is nothing else to do */
1454 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1455 return false;
1456
1457 /* place skb in next buffer to be received */
1458 rx_ring->rx_buffer_info[ntc].skb = skb;
1459 rx_ring->rx_stats.non_eop_descs++;
1460
1461 return true;
1462 }
1463
1464 /**
1465 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1466 * @rx_ring: rx descriptor ring packet is being transacted on
1467 * @skb: pointer to current skb being adjusted
1468 *
1469 * This function is an ixgbe specific version of __pskb_pull_tail. The
1470 * main difference between this version and the original function is that
1471 * this function can make several assumptions about the state of things
1472 * that allow for significant optimizations versus the standard function.
1473 * As a result we can do things like drop a frag and maintain an accurate
1474 * truesize for the skb.
1475 */
1476 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1477 struct sk_buff *skb)
1478 {
1479 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1480 unsigned char *va;
1481 unsigned int pull_len;
1482
1483 /*
1484 * it is valid to use page_address instead of kmap since we are
1485 * working with pages allocated out of the lomem pool per
1486 * alloc_page(GFP_ATOMIC)
1487 */
1488 va = skb_frag_address(frag);
1489
1490 /*
1491 * we need the header to contain the greater of either ETH_HLEN or
1492 * 60 bytes if the skb->len is less than 60 for skb_pad.
1493 */
1494 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1495
1496 /* align pull length to size of long to optimize memcpy performance */
1497 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1498
1499 /* update all of the pointers */
1500 skb_frag_size_sub(frag, pull_len);
1501 frag->page_offset += pull_len;
1502 skb->data_len -= pull_len;
1503 skb->tail += pull_len;
1504 }
1505
1506 /**
1507 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1508 * @rx_ring: rx descriptor ring packet is being transacted on
1509 * @skb: pointer to current skb being updated
1510 *
1511 * This function provides a basic DMA sync up for the first fragment of an
1512 * skb. The reason for doing this is that the first fragment cannot be
1513 * unmapped until we have reached the end of packet descriptor for a buffer
1514 * chain.
1515 */
1516 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1517 struct sk_buff *skb)
1518 {
1519 /* if the page was released unmap it, else just sync our portion */
1520 if (unlikely(IXGBE_CB(skb)->page_released)) {
1521 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1522 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1523 IXGBE_CB(skb)->page_released = false;
1524 } else {
1525 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1526
1527 dma_sync_single_range_for_cpu(rx_ring->dev,
1528 IXGBE_CB(skb)->dma,
1529 frag->page_offset,
1530 ixgbe_rx_bufsz(rx_ring),
1531 DMA_FROM_DEVICE);
1532 }
1533 IXGBE_CB(skb)->dma = 0;
1534 }
1535
1536 /**
1537 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1538 * @rx_ring: rx descriptor ring packet is being transacted on
1539 * @rx_desc: pointer to the EOP Rx descriptor
1540 * @skb: pointer to current skb being fixed
1541 *
1542 * Check for corrupted packet headers caused by senders on the local L2
1543 * embedded NIC switch not setting up their Tx Descriptors right. These
1544 * should be very rare.
1545 *
1546 * Also address the case where we are pulling data in on pages only
1547 * and as such no data is present in the skb header.
1548 *
1549 * In addition if skb is not at least 60 bytes we need to pad it so that
1550 * it is large enough to qualify as a valid Ethernet frame.
1551 *
1552 * Returns true if an error was encountered and skb was freed.
1553 **/
1554 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1555 union ixgbe_adv_rx_desc *rx_desc,
1556 struct sk_buff *skb)
1557 {
1558 struct net_device *netdev = rx_ring->netdev;
1559
1560 /* verify that the packet does not have any known errors */
1561 if (unlikely(ixgbe_test_staterr(rx_desc,
1562 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1563 !(netdev->features & NETIF_F_RXALL))) {
1564 dev_kfree_skb_any(skb);
1565 return true;
1566 }
1567
1568 /* place header in linear portion of buffer */
1569 if (skb_is_nonlinear(skb))
1570 ixgbe_pull_tail(rx_ring, skb);
1571
1572 #ifdef IXGBE_FCOE
1573 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1574 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1575 return false;
1576
1577 #endif
1578 /* if skb_pad returns an error the skb was freed */
1579 if (unlikely(skb->len < 60)) {
1580 int pad_len = 60 - skb->len;
1581
1582 if (skb_pad(skb, pad_len))
1583 return true;
1584 __skb_put(skb, pad_len);
1585 }
1586
1587 return false;
1588 }
1589
1590 /**
1591 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1592 * @rx_ring: rx descriptor ring to store buffers on
1593 * @old_buff: donor buffer to have page reused
1594 *
1595 * Synchronizes page for reuse by the adapter
1596 **/
1597 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1598 struct ixgbe_rx_buffer *old_buff)
1599 {
1600 struct ixgbe_rx_buffer *new_buff;
1601 u16 nta = rx_ring->next_to_alloc;
1602
1603 new_buff = &rx_ring->rx_buffer_info[nta];
1604
1605 /* update, and store next to alloc */
1606 nta++;
1607 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1608
1609 /* transfer page from old buffer to new buffer */
1610 new_buff->page = old_buff->page;
1611 new_buff->dma = old_buff->dma;
1612 new_buff->page_offset = old_buff->page_offset;
1613
1614 /* sync the buffer for use by the device */
1615 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1616 new_buff->page_offset,
1617 ixgbe_rx_bufsz(rx_ring),
1618 DMA_FROM_DEVICE);
1619 }
1620
1621 /**
1622 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1623 * @rx_ring: rx descriptor ring to transact packets on
1624 * @rx_buffer: buffer containing page to add
1625 * @rx_desc: descriptor containing length of buffer written by hardware
1626 * @skb: sk_buff to place the data into
1627 *
1628 * This function will add the data contained in rx_buffer->page to the skb.
1629 * This is done either through a direct copy if the data in the buffer is
1630 * less than the skb header size, otherwise it will just attach the page as
1631 * a frag to the skb.
1632 *
1633 * The function will then update the page offset if necessary and return
1634 * true if the buffer can be reused by the adapter.
1635 **/
1636 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1637 struct ixgbe_rx_buffer *rx_buffer,
1638 union ixgbe_adv_rx_desc *rx_desc,
1639 struct sk_buff *skb)
1640 {
1641 struct page *page = rx_buffer->page;
1642 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1643 #if (PAGE_SIZE < 8192)
1644 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1645 #else
1646 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1647 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1648 ixgbe_rx_bufsz(rx_ring);
1649 #endif
1650
1651 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1652 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1653
1654 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1655
1656 /* we can reuse buffer as-is, just make sure it is local */
1657 if (likely(page_to_nid(page) == numa_node_id()))
1658 return true;
1659
1660 /* this page cannot be reused so discard it */
1661 put_page(page);
1662 return false;
1663 }
1664
1665 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1666 rx_buffer->page_offset, size, truesize);
1667
1668 /* avoid re-using remote pages */
1669 if (unlikely(page_to_nid(page) != numa_node_id()))
1670 return false;
1671
1672 #if (PAGE_SIZE < 8192)
1673 /* if we are only owner of page we can reuse it */
1674 if (unlikely(page_count(page) != 1))
1675 return false;
1676
1677 /* flip page offset to other buffer */
1678 rx_buffer->page_offset ^= truesize;
1679
1680 /*
1681 * since we are the only owner of the page and we need to
1682 * increment it, just set the value to 2 in order to avoid
1683 * an unecessary locked operation
1684 */
1685 atomic_set(&page->_count, 2);
1686 #else
1687 /* move offset up to the next cache line */
1688 rx_buffer->page_offset += truesize;
1689
1690 if (rx_buffer->page_offset > last_offset)
1691 return false;
1692
1693 /* bump ref count on page before it is given to the stack */
1694 get_page(page);
1695 #endif
1696
1697 return true;
1698 }
1699
1700 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1701 union ixgbe_adv_rx_desc *rx_desc)
1702 {
1703 struct ixgbe_rx_buffer *rx_buffer;
1704 struct sk_buff *skb;
1705 struct page *page;
1706
1707 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1708 page = rx_buffer->page;
1709 prefetchw(page);
1710
1711 skb = rx_buffer->skb;
1712
1713 if (likely(!skb)) {
1714 void *page_addr = page_address(page) +
1715 rx_buffer->page_offset;
1716
1717 /* prefetch first cache line of first page */
1718 prefetch(page_addr);
1719 #if L1_CACHE_BYTES < 128
1720 prefetch(page_addr + L1_CACHE_BYTES);
1721 #endif
1722
1723 /* allocate a skb to store the frags */
1724 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1725 IXGBE_RX_HDR_SIZE);
1726 if (unlikely(!skb)) {
1727 rx_ring->rx_stats.alloc_rx_buff_failed++;
1728 return NULL;
1729 }
1730
1731 /*
1732 * we will be copying header into skb->data in
1733 * pskb_may_pull so it is in our interest to prefetch
1734 * it now to avoid a possible cache miss
1735 */
1736 prefetchw(skb->data);
1737
1738 /*
1739 * Delay unmapping of the first packet. It carries the
1740 * header information, HW may still access the header
1741 * after the writeback. Only unmap it when EOP is
1742 * reached
1743 */
1744 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1745 goto dma_sync;
1746
1747 IXGBE_CB(skb)->dma = rx_buffer->dma;
1748 } else {
1749 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1750 ixgbe_dma_sync_frag(rx_ring, skb);
1751
1752 dma_sync:
1753 /* we are reusing so sync this buffer for CPU use */
1754 dma_sync_single_range_for_cpu(rx_ring->dev,
1755 rx_buffer->dma,
1756 rx_buffer->page_offset,
1757 ixgbe_rx_bufsz(rx_ring),
1758 DMA_FROM_DEVICE);
1759 }
1760
1761 /* pull page into skb */
1762 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1763 /* hand second half of page back to the ring */
1764 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1765 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1766 /* the page has been released from the ring */
1767 IXGBE_CB(skb)->page_released = true;
1768 } else {
1769 /* we are not reusing the buffer so unmap it */
1770 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1771 ixgbe_rx_pg_size(rx_ring),
1772 DMA_FROM_DEVICE);
1773 }
1774
1775 /* clear contents of buffer_info */
1776 rx_buffer->skb = NULL;
1777 rx_buffer->dma = 0;
1778 rx_buffer->page = NULL;
1779
1780 return skb;
1781 }
1782
1783 /**
1784 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1785 * @q_vector: structure containing interrupt and ring information
1786 * @rx_ring: rx descriptor ring to transact packets on
1787 * @budget: Total limit on number of packets to process
1788 *
1789 * This function provides a "bounce buffer" approach to Rx interrupt
1790 * processing. The advantage to this is that on systems that have
1791 * expensive overhead for IOMMU access this provides a means of avoiding
1792 * it by maintaining the mapping of the page to the syste.
1793 *
1794 * Returns true if all work is completed without reaching budget
1795 **/
1796 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1797 struct ixgbe_ring *rx_ring,
1798 int budget)
1799 {
1800 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1801 #ifdef IXGBE_FCOE
1802 struct ixgbe_adapter *adapter = q_vector->adapter;
1803 int ddp_bytes;
1804 unsigned int mss = 0;
1805 #endif /* IXGBE_FCOE */
1806 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1807
1808 do {
1809 union ixgbe_adv_rx_desc *rx_desc;
1810 struct sk_buff *skb;
1811
1812 /* return some buffers to hardware, one at a time is too slow */
1813 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1814 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1815 cleaned_count = 0;
1816 }
1817
1818 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1819
1820 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1821 break;
1822
1823 /*
1824 * This memory barrier is needed to keep us from reading
1825 * any other fields out of the rx_desc until we know the
1826 * RXD_STAT_DD bit is set
1827 */
1828 rmb();
1829
1830 /* retrieve a buffer from the ring */
1831 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1832
1833 /* exit if we failed to retrieve a buffer */
1834 if (!skb)
1835 break;
1836
1837 cleaned_count++;
1838
1839 /* place incomplete frames back on ring for completion */
1840 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1841 continue;
1842
1843 /* verify the packet layout is correct */
1844 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1845 continue;
1846
1847 /* probably a little skewed due to removing CRC */
1848 total_rx_bytes += skb->len;
1849 total_rx_packets++;
1850
1851 /* populate checksum, timestamp, VLAN, and protocol */
1852 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1853
1854 #ifdef IXGBE_FCOE
1855 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1856 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1857 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1858 /* include DDPed FCoE data */
1859 if (ddp_bytes > 0) {
1860 if (!mss) {
1861 mss = rx_ring->netdev->mtu -
1862 sizeof(struct fcoe_hdr) -
1863 sizeof(struct fc_frame_header) -
1864 sizeof(struct fcoe_crc_eof);
1865 if (mss > 512)
1866 mss &= ~511;
1867 }
1868 total_rx_bytes += ddp_bytes;
1869 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1870 mss);
1871 }
1872 if (!ddp_bytes) {
1873 dev_kfree_skb_any(skb);
1874 continue;
1875 }
1876 }
1877
1878 #endif /* IXGBE_FCOE */
1879 ixgbe_rx_skb(q_vector, skb);
1880
1881 /* update budget accounting */
1882 budget--;
1883 } while (likely(budget));
1884
1885 u64_stats_update_begin(&rx_ring->syncp);
1886 rx_ring->stats.packets += total_rx_packets;
1887 rx_ring->stats.bytes += total_rx_bytes;
1888 u64_stats_update_end(&rx_ring->syncp);
1889 q_vector->rx.total_packets += total_rx_packets;
1890 q_vector->rx.total_bytes += total_rx_bytes;
1891
1892 if (cleaned_count)
1893 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1894
1895 return !!budget;
1896 }
1897
1898 /**
1899 * ixgbe_configure_msix - Configure MSI-X hardware
1900 * @adapter: board private structure
1901 *
1902 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1903 * interrupts.
1904 **/
1905 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1906 {
1907 struct ixgbe_q_vector *q_vector;
1908 int v_idx;
1909 u32 mask;
1910
1911 /* Populate MSIX to EITR Select */
1912 if (adapter->num_vfs > 32) {
1913 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1914 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1915 }
1916
1917 /*
1918 * Populate the IVAR table and set the ITR values to the
1919 * corresponding register.
1920 */
1921 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1922 struct ixgbe_ring *ring;
1923 q_vector = adapter->q_vector[v_idx];
1924
1925 ixgbe_for_each_ring(ring, q_vector->rx)
1926 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1927
1928 ixgbe_for_each_ring(ring, q_vector->tx)
1929 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1930
1931 if (q_vector->tx.ring && !q_vector->rx.ring) {
1932 /* tx only vector */
1933 if (adapter->tx_itr_setting == 1)
1934 q_vector->itr = IXGBE_10K_ITR;
1935 else
1936 q_vector->itr = adapter->tx_itr_setting;
1937 } else {
1938 /* rx or rx/tx vector */
1939 if (adapter->rx_itr_setting == 1)
1940 q_vector->itr = IXGBE_20K_ITR;
1941 else
1942 q_vector->itr = adapter->rx_itr_setting;
1943 }
1944
1945 ixgbe_write_eitr(q_vector);
1946 }
1947
1948 switch (adapter->hw.mac.type) {
1949 case ixgbe_mac_82598EB:
1950 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1951 v_idx);
1952 break;
1953 case ixgbe_mac_82599EB:
1954 case ixgbe_mac_X540:
1955 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1956 break;
1957 default:
1958 break;
1959 }
1960 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1961
1962 /* set up to autoclear timer, and the vectors */
1963 mask = IXGBE_EIMS_ENABLE_MASK;
1964 mask &= ~(IXGBE_EIMS_OTHER |
1965 IXGBE_EIMS_MAILBOX |
1966 IXGBE_EIMS_LSC);
1967
1968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1969 }
1970
1971 enum latency_range {
1972 lowest_latency = 0,
1973 low_latency = 1,
1974 bulk_latency = 2,
1975 latency_invalid = 255
1976 };
1977
1978 /**
1979 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1980 * @q_vector: structure containing interrupt and ring information
1981 * @ring_container: structure containing ring performance data
1982 *
1983 * Stores a new ITR value based on packets and byte
1984 * counts during the last interrupt. The advantage of per interrupt
1985 * computation is faster updates and more accurate ITR for the current
1986 * traffic pattern. Constants in this function were computed
1987 * based on theoretical maximum wire speed and thresholds were set based
1988 * on testing data as well as attempting to minimize response time
1989 * while increasing bulk throughput.
1990 * this functionality is controlled by the InterruptThrottleRate module
1991 * parameter (see ixgbe_param.c)
1992 **/
1993 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1994 struct ixgbe_ring_container *ring_container)
1995 {
1996 int bytes = ring_container->total_bytes;
1997 int packets = ring_container->total_packets;
1998 u32 timepassed_us;
1999 u64 bytes_perint;
2000 u8 itr_setting = ring_container->itr;
2001
2002 if (packets == 0)
2003 return;
2004
2005 /* simple throttlerate management
2006 * 0-10MB/s lowest (100000 ints/s)
2007 * 10-20MB/s low (20000 ints/s)
2008 * 20-1249MB/s bulk (8000 ints/s)
2009 */
2010 /* what was last interrupt timeslice? */
2011 timepassed_us = q_vector->itr >> 2;
2012 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2013
2014 switch (itr_setting) {
2015 case lowest_latency:
2016 if (bytes_perint > 10)
2017 itr_setting = low_latency;
2018 break;
2019 case low_latency:
2020 if (bytes_perint > 20)
2021 itr_setting = bulk_latency;
2022 else if (bytes_perint <= 10)
2023 itr_setting = lowest_latency;
2024 break;
2025 case bulk_latency:
2026 if (bytes_perint <= 20)
2027 itr_setting = low_latency;
2028 break;
2029 }
2030
2031 /* clear work counters since we have the values we need */
2032 ring_container->total_bytes = 0;
2033 ring_container->total_packets = 0;
2034
2035 /* write updated itr to ring container */
2036 ring_container->itr = itr_setting;
2037 }
2038
2039 /**
2040 * ixgbe_write_eitr - write EITR register in hardware specific way
2041 * @q_vector: structure containing interrupt and ring information
2042 *
2043 * This function is made to be called by ethtool and by the driver
2044 * when it needs to update EITR registers at runtime. Hardware
2045 * specific quirks/differences are taken care of here.
2046 */
2047 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2048 {
2049 struct ixgbe_adapter *adapter = q_vector->adapter;
2050 struct ixgbe_hw *hw = &adapter->hw;
2051 int v_idx = q_vector->v_idx;
2052 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2053
2054 switch (adapter->hw.mac.type) {
2055 case ixgbe_mac_82598EB:
2056 /* must write high and low 16 bits to reset counter */
2057 itr_reg |= (itr_reg << 16);
2058 break;
2059 case ixgbe_mac_82599EB:
2060 case ixgbe_mac_X540:
2061 /*
2062 * set the WDIS bit to not clear the timer bits and cause an
2063 * immediate assertion of the interrupt
2064 */
2065 itr_reg |= IXGBE_EITR_CNT_WDIS;
2066 break;
2067 default:
2068 break;
2069 }
2070 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2071 }
2072
2073 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2074 {
2075 u32 new_itr = q_vector->itr;
2076 u8 current_itr;
2077
2078 ixgbe_update_itr(q_vector, &q_vector->tx);
2079 ixgbe_update_itr(q_vector, &q_vector->rx);
2080
2081 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2082
2083 switch (current_itr) {
2084 /* counts and packets in update_itr are dependent on these numbers */
2085 case lowest_latency:
2086 new_itr = IXGBE_100K_ITR;
2087 break;
2088 case low_latency:
2089 new_itr = IXGBE_20K_ITR;
2090 break;
2091 case bulk_latency:
2092 new_itr = IXGBE_8K_ITR;
2093 break;
2094 default:
2095 break;
2096 }
2097
2098 if (new_itr != q_vector->itr) {
2099 /* do an exponential smoothing */
2100 new_itr = (10 * new_itr * q_vector->itr) /
2101 ((9 * new_itr) + q_vector->itr);
2102
2103 /* save the algorithm value here */
2104 q_vector->itr = new_itr;
2105
2106 ixgbe_write_eitr(q_vector);
2107 }
2108 }
2109
2110 /**
2111 * ixgbe_check_overtemp_subtask - check for over temperature
2112 * @adapter: pointer to adapter
2113 **/
2114 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2115 {
2116 struct ixgbe_hw *hw = &adapter->hw;
2117 u32 eicr = adapter->interrupt_event;
2118
2119 if (test_bit(__IXGBE_DOWN, &adapter->state))
2120 return;
2121
2122 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2123 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2124 return;
2125
2126 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2127
2128 switch (hw->device_id) {
2129 case IXGBE_DEV_ID_82599_T3_LOM:
2130 /*
2131 * Since the warning interrupt is for both ports
2132 * we don't have to check if:
2133 * - This interrupt wasn't for our port.
2134 * - We may have missed the interrupt so always have to
2135 * check if we got a LSC
2136 */
2137 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2138 !(eicr & IXGBE_EICR_LSC))
2139 return;
2140
2141 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2142 u32 autoneg;
2143 bool link_up = false;
2144
2145 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2146
2147 if (link_up)
2148 return;
2149 }
2150
2151 /* Check if this is not due to overtemp */
2152 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2153 return;
2154
2155 break;
2156 default:
2157 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2158 return;
2159 break;
2160 }
2161 e_crit(drv,
2162 "Network adapter has been stopped because it has over heated. "
2163 "Restart the computer. If the problem persists, "
2164 "power off the system and replace the adapter\n");
2165
2166 adapter->interrupt_event = 0;
2167 }
2168
2169 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2170 {
2171 struct ixgbe_hw *hw = &adapter->hw;
2172
2173 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2174 (eicr & IXGBE_EICR_GPI_SDP1)) {
2175 e_crit(probe, "Fan has stopped, replace the adapter\n");
2176 /* write to clear the interrupt */
2177 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2178 }
2179 }
2180
2181 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2182 {
2183 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2184 return;
2185
2186 switch (adapter->hw.mac.type) {
2187 case ixgbe_mac_82599EB:
2188 /*
2189 * Need to check link state so complete overtemp check
2190 * on service task
2191 */
2192 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2193 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2194 adapter->interrupt_event = eicr;
2195 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2196 ixgbe_service_event_schedule(adapter);
2197 return;
2198 }
2199 return;
2200 case ixgbe_mac_X540:
2201 if (!(eicr & IXGBE_EICR_TS))
2202 return;
2203 break;
2204 default:
2205 return;
2206 }
2207
2208 e_crit(drv,
2209 "Network adapter has been stopped because it has over heated. "
2210 "Restart the computer. If the problem persists, "
2211 "power off the system and replace the adapter\n");
2212 }
2213
2214 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2215 {
2216 struct ixgbe_hw *hw = &adapter->hw;
2217
2218 if (eicr & IXGBE_EICR_GPI_SDP2) {
2219 /* Clear the interrupt */
2220 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2221 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2222 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2223 ixgbe_service_event_schedule(adapter);
2224 }
2225 }
2226
2227 if (eicr & IXGBE_EICR_GPI_SDP1) {
2228 /* Clear the interrupt */
2229 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2230 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2231 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2232 ixgbe_service_event_schedule(adapter);
2233 }
2234 }
2235 }
2236
2237 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2238 {
2239 struct ixgbe_hw *hw = &adapter->hw;
2240
2241 adapter->lsc_int++;
2242 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2243 adapter->link_check_timeout = jiffies;
2244 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2245 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2246 IXGBE_WRITE_FLUSH(hw);
2247 ixgbe_service_event_schedule(adapter);
2248 }
2249 }
2250
2251 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2252 u64 qmask)
2253 {
2254 u32 mask;
2255 struct ixgbe_hw *hw = &adapter->hw;
2256
2257 switch (hw->mac.type) {
2258 case ixgbe_mac_82598EB:
2259 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2260 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2261 break;
2262 case ixgbe_mac_82599EB:
2263 case ixgbe_mac_X540:
2264 mask = (qmask & 0xFFFFFFFF);
2265 if (mask)
2266 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2267 mask = (qmask >> 32);
2268 if (mask)
2269 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2270 break;
2271 default:
2272 break;
2273 }
2274 /* skip the flush */
2275 }
2276
2277 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2278 u64 qmask)
2279 {
2280 u32 mask;
2281 struct ixgbe_hw *hw = &adapter->hw;
2282
2283 switch (hw->mac.type) {
2284 case ixgbe_mac_82598EB:
2285 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2286 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2287 break;
2288 case ixgbe_mac_82599EB:
2289 case ixgbe_mac_X540:
2290 mask = (qmask & 0xFFFFFFFF);
2291 if (mask)
2292 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2293 mask = (qmask >> 32);
2294 if (mask)
2295 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2296 break;
2297 default:
2298 break;
2299 }
2300 /* skip the flush */
2301 }
2302
2303 /**
2304 * ixgbe_irq_enable - Enable default interrupt generation settings
2305 * @adapter: board private structure
2306 **/
2307 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2308 bool flush)
2309 {
2310 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2311
2312 /* don't reenable LSC while waiting for link */
2313 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2314 mask &= ~IXGBE_EIMS_LSC;
2315
2316 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2317 switch (adapter->hw.mac.type) {
2318 case ixgbe_mac_82599EB:
2319 mask |= IXGBE_EIMS_GPI_SDP0;
2320 break;
2321 case ixgbe_mac_X540:
2322 mask |= IXGBE_EIMS_TS;
2323 break;
2324 default:
2325 break;
2326 }
2327 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2328 mask |= IXGBE_EIMS_GPI_SDP1;
2329 switch (adapter->hw.mac.type) {
2330 case ixgbe_mac_82599EB:
2331 mask |= IXGBE_EIMS_GPI_SDP1;
2332 mask |= IXGBE_EIMS_GPI_SDP2;
2333 case ixgbe_mac_X540:
2334 mask |= IXGBE_EIMS_ECC;
2335 mask |= IXGBE_EIMS_MAILBOX;
2336 break;
2337 default:
2338 break;
2339 }
2340
2341 #ifdef CONFIG_IXGBE_PTP
2342 if (adapter->hw.mac.type == ixgbe_mac_X540)
2343 mask |= IXGBE_EIMS_TIMESYNC;
2344 #endif
2345
2346 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2347 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2348 mask |= IXGBE_EIMS_FLOW_DIR;
2349
2350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2351 if (queues)
2352 ixgbe_irq_enable_queues(adapter, ~0);
2353 if (flush)
2354 IXGBE_WRITE_FLUSH(&adapter->hw);
2355 }
2356
2357 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2358 {
2359 struct ixgbe_adapter *adapter = data;
2360 struct ixgbe_hw *hw = &adapter->hw;
2361 u32 eicr;
2362
2363 /*
2364 * Workaround for Silicon errata. Use clear-by-write instead
2365 * of clear-by-read. Reading with EICS will return the
2366 * interrupt causes without clearing, which later be done
2367 * with the write to EICR.
2368 */
2369 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2370 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2371
2372 if (eicr & IXGBE_EICR_LSC)
2373 ixgbe_check_lsc(adapter);
2374
2375 if (eicr & IXGBE_EICR_MAILBOX)
2376 ixgbe_msg_task(adapter);
2377
2378 switch (hw->mac.type) {
2379 case ixgbe_mac_82599EB:
2380 case ixgbe_mac_X540:
2381 if (eicr & IXGBE_EICR_ECC)
2382 e_info(link, "Received unrecoverable ECC Err, please "
2383 "reboot\n");
2384 /* Handle Flow Director Full threshold interrupt */
2385 if (eicr & IXGBE_EICR_FLOW_DIR) {
2386 int reinit_count = 0;
2387 int i;
2388 for (i = 0; i < adapter->num_tx_queues; i++) {
2389 struct ixgbe_ring *ring = adapter->tx_ring[i];
2390 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2391 &ring->state))
2392 reinit_count++;
2393 }
2394 if (reinit_count) {
2395 /* no more flow director interrupts until after init */
2396 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2397 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2398 ixgbe_service_event_schedule(adapter);
2399 }
2400 }
2401 ixgbe_check_sfp_event(adapter, eicr);
2402 ixgbe_check_overtemp_event(adapter, eicr);
2403 break;
2404 default:
2405 break;
2406 }
2407
2408 ixgbe_check_fan_failure(adapter, eicr);
2409
2410 #ifdef CONFIG_IXGBE_PTP
2411 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2412 ixgbe_ptp_check_pps_event(adapter, eicr);
2413 #endif
2414
2415 /* re-enable the original interrupt state, no lsc, no queues */
2416 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2417 ixgbe_irq_enable(adapter, false, false);
2418
2419 return IRQ_HANDLED;
2420 }
2421
2422 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2423 {
2424 struct ixgbe_q_vector *q_vector = data;
2425
2426 /* EIAM disabled interrupts (on this vector) for us */
2427
2428 if (q_vector->rx.ring || q_vector->tx.ring)
2429 napi_schedule(&q_vector->napi);
2430
2431 return IRQ_HANDLED;
2432 }
2433
2434 /**
2435 * ixgbe_poll - NAPI Rx polling callback
2436 * @napi: structure for representing this polling device
2437 * @budget: how many packets driver is allowed to clean
2438 *
2439 * This function is used for legacy and MSI, NAPI mode
2440 **/
2441 int ixgbe_poll(struct napi_struct *napi, int budget)
2442 {
2443 struct ixgbe_q_vector *q_vector =
2444 container_of(napi, struct ixgbe_q_vector, napi);
2445 struct ixgbe_adapter *adapter = q_vector->adapter;
2446 struct ixgbe_ring *ring;
2447 int per_ring_budget;
2448 bool clean_complete = true;
2449
2450 #ifdef CONFIG_IXGBE_DCA
2451 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2452 ixgbe_update_dca(q_vector);
2453 #endif
2454
2455 ixgbe_for_each_ring(ring, q_vector->tx)
2456 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2457
2458 /* attempt to distribute budget to each queue fairly, but don't allow
2459 * the budget to go below 1 because we'll exit polling */
2460 if (q_vector->rx.count > 1)
2461 per_ring_budget = max(budget/q_vector->rx.count, 1);
2462 else
2463 per_ring_budget = budget;
2464
2465 ixgbe_for_each_ring(ring, q_vector->rx)
2466 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2467 per_ring_budget);
2468
2469 /* If all work not completed, return budget and keep polling */
2470 if (!clean_complete)
2471 return budget;
2472
2473 /* all work done, exit the polling mode */
2474 napi_complete(napi);
2475 if (adapter->rx_itr_setting & 1)
2476 ixgbe_set_itr(q_vector);
2477 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2478 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2479
2480 return 0;
2481 }
2482
2483 /**
2484 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2485 * @adapter: board private structure
2486 *
2487 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2488 * interrupts from the kernel.
2489 **/
2490 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2491 {
2492 struct net_device *netdev = adapter->netdev;
2493 int vector, err;
2494 int ri = 0, ti = 0;
2495
2496 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2497 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2498 struct msix_entry *entry = &adapter->msix_entries[vector];
2499
2500 if (q_vector->tx.ring && q_vector->rx.ring) {
2501 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2502 "%s-%s-%d", netdev->name, "TxRx", ri++);
2503 ti++;
2504 } else if (q_vector->rx.ring) {
2505 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2506 "%s-%s-%d", netdev->name, "rx", ri++);
2507 } else if (q_vector->tx.ring) {
2508 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2509 "%s-%s-%d", netdev->name, "tx", ti++);
2510 } else {
2511 /* skip this unused q_vector */
2512 continue;
2513 }
2514 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2515 q_vector->name, q_vector);
2516 if (err) {
2517 e_err(probe, "request_irq failed for MSIX interrupt "
2518 "Error: %d\n", err);
2519 goto free_queue_irqs;
2520 }
2521 /* If Flow Director is enabled, set interrupt affinity */
2522 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2523 /* assign the mask for this irq */
2524 irq_set_affinity_hint(entry->vector,
2525 &q_vector->affinity_mask);
2526 }
2527 }
2528
2529 err = request_irq(adapter->msix_entries[vector].vector,
2530 ixgbe_msix_other, 0, netdev->name, adapter);
2531 if (err) {
2532 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2533 goto free_queue_irqs;
2534 }
2535
2536 return 0;
2537
2538 free_queue_irqs:
2539 while (vector) {
2540 vector--;
2541 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2542 NULL);
2543 free_irq(adapter->msix_entries[vector].vector,
2544 adapter->q_vector[vector]);
2545 }
2546 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2547 pci_disable_msix(adapter->pdev);
2548 kfree(adapter->msix_entries);
2549 adapter->msix_entries = NULL;
2550 return err;
2551 }
2552
2553 /**
2554 * ixgbe_intr - legacy mode Interrupt Handler
2555 * @irq: interrupt number
2556 * @data: pointer to a network interface device structure
2557 **/
2558 static irqreturn_t ixgbe_intr(int irq, void *data)
2559 {
2560 struct ixgbe_adapter *adapter = data;
2561 struct ixgbe_hw *hw = &adapter->hw;
2562 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2563 u32 eicr;
2564
2565 /*
2566 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2567 * before the read of EICR.
2568 */
2569 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2570
2571 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2572 * therefore no explicit interrupt disable is necessary */
2573 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2574 if (!eicr) {
2575 /*
2576 * shared interrupt alert!
2577 * make sure interrupts are enabled because the read will
2578 * have disabled interrupts due to EIAM
2579 * finish the workaround of silicon errata on 82598. Unmask
2580 * the interrupt that we masked before the EICR read.
2581 */
2582 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2583 ixgbe_irq_enable(adapter, true, true);
2584 return IRQ_NONE; /* Not our interrupt */
2585 }
2586
2587 if (eicr & IXGBE_EICR_LSC)
2588 ixgbe_check_lsc(adapter);
2589
2590 switch (hw->mac.type) {
2591 case ixgbe_mac_82599EB:
2592 ixgbe_check_sfp_event(adapter, eicr);
2593 /* Fall through */
2594 case ixgbe_mac_X540:
2595 if (eicr & IXGBE_EICR_ECC)
2596 e_info(link, "Received unrecoverable ECC err, please "
2597 "reboot\n");
2598 ixgbe_check_overtemp_event(adapter, eicr);
2599 break;
2600 default:
2601 break;
2602 }
2603
2604 ixgbe_check_fan_failure(adapter, eicr);
2605 #ifdef CONFIG_IXGBE_PTP
2606 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2607 ixgbe_ptp_check_pps_event(adapter, eicr);
2608 #endif
2609
2610 /* would disable interrupts here but EIAM disabled it */
2611 napi_schedule(&q_vector->napi);
2612
2613 /*
2614 * re-enable link(maybe) and non-queue interrupts, no flush.
2615 * ixgbe_poll will re-enable the queue interrupts
2616 */
2617 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2618 ixgbe_irq_enable(adapter, false, false);
2619
2620 return IRQ_HANDLED;
2621 }
2622
2623 /**
2624 * ixgbe_request_irq - initialize interrupts
2625 * @adapter: board private structure
2626 *
2627 * Attempts to configure interrupts using the best available
2628 * capabilities of the hardware and kernel.
2629 **/
2630 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2631 {
2632 struct net_device *netdev = adapter->netdev;
2633 int err;
2634
2635 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2636 err = ixgbe_request_msix_irqs(adapter);
2637 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2638 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2639 netdev->name, adapter);
2640 else
2641 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2642 netdev->name, adapter);
2643
2644 if (err)
2645 e_err(probe, "request_irq failed, Error %d\n", err);
2646
2647 return err;
2648 }
2649
2650 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2651 {
2652 int vector;
2653
2654 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2655 free_irq(adapter->pdev->irq, adapter);
2656 return;
2657 }
2658
2659 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2660 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2661 struct msix_entry *entry = &adapter->msix_entries[vector];
2662
2663 /* free only the irqs that were actually requested */
2664 if (!q_vector->rx.ring && !q_vector->tx.ring)
2665 continue;
2666
2667 /* clear the affinity_mask in the IRQ descriptor */
2668 irq_set_affinity_hint(entry->vector, NULL);
2669
2670 free_irq(entry->vector, q_vector);
2671 }
2672
2673 free_irq(adapter->msix_entries[vector++].vector, adapter);
2674 }
2675
2676 /**
2677 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2678 * @adapter: board private structure
2679 **/
2680 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2681 {
2682 switch (adapter->hw.mac.type) {
2683 case ixgbe_mac_82598EB:
2684 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2685 break;
2686 case ixgbe_mac_82599EB:
2687 case ixgbe_mac_X540:
2688 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2689 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2691 break;
2692 default:
2693 break;
2694 }
2695 IXGBE_WRITE_FLUSH(&adapter->hw);
2696 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2697 int vector;
2698
2699 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2700 synchronize_irq(adapter->msix_entries[vector].vector);
2701
2702 synchronize_irq(adapter->msix_entries[vector++].vector);
2703 } else {
2704 synchronize_irq(adapter->pdev->irq);
2705 }
2706 }
2707
2708 /**
2709 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2710 *
2711 **/
2712 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2713 {
2714 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2715
2716 /* rx/tx vector */
2717 if (adapter->rx_itr_setting == 1)
2718 q_vector->itr = IXGBE_20K_ITR;
2719 else
2720 q_vector->itr = adapter->rx_itr_setting;
2721
2722 ixgbe_write_eitr(q_vector);
2723
2724 ixgbe_set_ivar(adapter, 0, 0, 0);
2725 ixgbe_set_ivar(adapter, 1, 0, 0);
2726
2727 e_info(hw, "Legacy interrupt IVAR setup done\n");
2728 }
2729
2730 /**
2731 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2732 * @adapter: board private structure
2733 * @ring: structure containing ring specific data
2734 *
2735 * Configure the Tx descriptor ring after a reset.
2736 **/
2737 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2738 struct ixgbe_ring *ring)
2739 {
2740 struct ixgbe_hw *hw = &adapter->hw;
2741 u64 tdba = ring->dma;
2742 int wait_loop = 10;
2743 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2744 u8 reg_idx = ring->reg_idx;
2745
2746 /* disable queue to avoid issues while updating state */
2747 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2748 IXGBE_WRITE_FLUSH(hw);
2749
2750 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2751 (tdba & DMA_BIT_MASK(32)));
2752 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2753 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2754 ring->count * sizeof(union ixgbe_adv_tx_desc));
2755 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2756 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2757 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2758
2759 /*
2760 * set WTHRESH to encourage burst writeback, it should not be set
2761 * higher than 1 when ITR is 0 as it could cause false TX hangs
2762 *
2763 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2764 * to or less than the number of on chip descriptors, which is
2765 * currently 40.
2766 */
2767 if (!ring->q_vector || (ring->q_vector->itr < 8))
2768 txdctl |= (1 << 16); /* WTHRESH = 1 */
2769 else
2770 txdctl |= (8 << 16); /* WTHRESH = 8 */
2771
2772 /*
2773 * Setting PTHRESH to 32 both improves performance
2774 * and avoids a TX hang with DFP enabled
2775 */
2776 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2777 32; /* PTHRESH = 32 */
2778
2779 /* reinitialize flowdirector state */
2780 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2781 ring->atr_sample_rate = adapter->atr_sample_rate;
2782 ring->atr_count = 0;
2783 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2784 } else {
2785 ring->atr_sample_rate = 0;
2786 }
2787
2788 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2789
2790 /* enable queue */
2791 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2792
2793 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2794 if (hw->mac.type == ixgbe_mac_82598EB &&
2795 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2796 return;
2797
2798 /* poll to verify queue is enabled */
2799 do {
2800 usleep_range(1000, 2000);
2801 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2802 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2803 if (!wait_loop)
2804 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2805 }
2806
2807 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2808 {
2809 struct ixgbe_hw *hw = &adapter->hw;
2810 u32 rttdcs, mtqc;
2811 u8 tcs = netdev_get_num_tc(adapter->netdev);
2812
2813 if (hw->mac.type == ixgbe_mac_82598EB)
2814 return;
2815
2816 /* disable the arbiter while setting MTQC */
2817 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2818 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2819 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2820
2821 /* set transmit pool layout */
2822 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2823 mtqc = IXGBE_MTQC_VT_ENA;
2824 if (tcs > 4)
2825 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2826 else if (tcs > 1)
2827 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2828 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2829 mtqc |= IXGBE_MTQC_32VF;
2830 else
2831 mtqc |= IXGBE_MTQC_64VF;
2832 } else {
2833 if (tcs > 4)
2834 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2835 else if (tcs > 1)
2836 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2837 else
2838 mtqc = IXGBE_MTQC_64Q_1PB;
2839 }
2840
2841 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2842
2843 /* Enable Security TX Buffer IFG for multiple pb */
2844 if (tcs) {
2845 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2846 sectx |= IXGBE_SECTX_DCB;
2847 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2848 }
2849
2850 /* re-enable the arbiter */
2851 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2852 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2853 }
2854
2855 /**
2856 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2857 * @adapter: board private structure
2858 *
2859 * Configure the Tx unit of the MAC after a reset.
2860 **/
2861 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2862 {
2863 struct ixgbe_hw *hw = &adapter->hw;
2864 u32 dmatxctl;
2865 u32 i;
2866
2867 ixgbe_setup_mtqc(adapter);
2868
2869 if (hw->mac.type != ixgbe_mac_82598EB) {
2870 /* DMATXCTL.EN must be before Tx queues are enabled */
2871 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2872 dmatxctl |= IXGBE_DMATXCTL_TE;
2873 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2874 }
2875
2876 /* Setup the HW Tx Head and Tail descriptor pointers */
2877 for (i = 0; i < adapter->num_tx_queues; i++)
2878 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2879 }
2880
2881 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2882 struct ixgbe_ring *ring)
2883 {
2884 struct ixgbe_hw *hw = &adapter->hw;
2885 u8 reg_idx = ring->reg_idx;
2886 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2887
2888 srrctl |= IXGBE_SRRCTL_DROP_EN;
2889
2890 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2891 }
2892
2893 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2894 struct ixgbe_ring *ring)
2895 {
2896 struct ixgbe_hw *hw = &adapter->hw;
2897 u8 reg_idx = ring->reg_idx;
2898 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2899
2900 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2901
2902 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2903 }
2904
2905 #ifdef CONFIG_IXGBE_DCB
2906 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2907 #else
2908 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2909 #endif
2910 {
2911 int i;
2912 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2913
2914 if (adapter->ixgbe_ieee_pfc)
2915 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2916
2917 /*
2918 * We should set the drop enable bit if:
2919 * SR-IOV is enabled
2920 * or
2921 * Number of Rx queues > 1 and flow control is disabled
2922 *
2923 * This allows us to avoid head of line blocking for security
2924 * and performance reasons.
2925 */
2926 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2927 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2928 for (i = 0; i < adapter->num_rx_queues; i++)
2929 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2930 } else {
2931 for (i = 0; i < adapter->num_rx_queues; i++)
2932 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2933 }
2934 }
2935
2936 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2937
2938 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2939 struct ixgbe_ring *rx_ring)
2940 {
2941 struct ixgbe_hw *hw = &adapter->hw;
2942 u32 srrctl;
2943 u8 reg_idx = rx_ring->reg_idx;
2944
2945 if (hw->mac.type == ixgbe_mac_82598EB) {
2946 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2947
2948 /*
2949 * if VMDq is not active we must program one srrctl register
2950 * per RSS queue since we have enabled RDRXCTL.MVMEN
2951 */
2952 reg_idx &= mask;
2953 }
2954
2955 /* configure header buffer length, needed for RSC */
2956 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
2957
2958 /* configure the packet buffer length */
2959 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2960
2961 /* configure descriptor type */
2962 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2963
2964 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2965 }
2966
2967 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2968 {
2969 struct ixgbe_hw *hw = &adapter->hw;
2970 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2971 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2972 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2973 u32 mrqc = 0, reta = 0;
2974 u32 rxcsum;
2975 int i, j;
2976 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2977
2978 /*
2979 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2980 * make full use of any rings they may have. We will use the
2981 * PSRTYPE register to control how many rings we use within the PF.
2982 */
2983 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2984 rss_i = 2;
2985
2986 /* Fill out hash function seeds */
2987 for (i = 0; i < 10; i++)
2988 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2989
2990 /* Fill out redirection table */
2991 for (i = 0, j = 0; i < 128; i++, j++) {
2992 if (j == rss_i)
2993 j = 0;
2994 /* reta = 4-byte sliding window of
2995 * 0x00..(indices-1)(indices-1)00..etc. */
2996 reta = (reta << 8) | (j * 0x11);
2997 if ((i & 3) == 3)
2998 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2999 }
3000
3001 /* Disable indicating checksum in descriptor, enables RSS hash */
3002 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3003 rxcsum |= IXGBE_RXCSUM_PCSD;
3004 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3005
3006 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3007 if (adapter->ring_feature[RING_F_RSS].mask)
3008 mrqc = IXGBE_MRQC_RSSEN;
3009 } else {
3010 u8 tcs = netdev_get_num_tc(adapter->netdev);
3011
3012 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3013 if (tcs > 4)
3014 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3015 else if (tcs > 1)
3016 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3017 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3018 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3019 else
3020 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3021 } else {
3022 if (tcs > 4)
3023 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3024 else if (tcs > 1)
3025 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3026 else
3027 mrqc = IXGBE_MRQC_RSSEN;
3028 }
3029 }
3030
3031 /* Perform hash on these packet types */
3032 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3033 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3034 IXGBE_MRQC_RSS_FIELD_IPV6 |
3035 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3036
3037 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3038 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3039 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3040 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3041
3042 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3043 }
3044
3045 /**
3046 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3047 * @adapter: address of board private structure
3048 * @index: index of ring to set
3049 **/
3050 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3051 struct ixgbe_ring *ring)
3052 {
3053 struct ixgbe_hw *hw = &adapter->hw;
3054 u32 rscctrl;
3055 u8 reg_idx = ring->reg_idx;
3056
3057 if (!ring_is_rsc_enabled(ring))
3058 return;
3059
3060 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3061 rscctrl |= IXGBE_RSCCTL_RSCEN;
3062 /*
3063 * we must limit the number of descriptors so that the
3064 * total size of max desc * buf_len is not greater
3065 * than 65536
3066 */
3067 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3068 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3069 }
3070
3071 #define IXGBE_MAX_RX_DESC_POLL 10
3072 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3073 struct ixgbe_ring *ring)
3074 {
3075 struct ixgbe_hw *hw = &adapter->hw;
3076 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3077 u32 rxdctl;
3078 u8 reg_idx = ring->reg_idx;
3079
3080 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3081 if (hw->mac.type == ixgbe_mac_82598EB &&
3082 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3083 return;
3084
3085 do {
3086 usleep_range(1000, 2000);
3087 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3088 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3089
3090 if (!wait_loop) {
3091 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3092 "the polling period\n", reg_idx);
3093 }
3094 }
3095
3096 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3097 struct ixgbe_ring *ring)
3098 {
3099 struct ixgbe_hw *hw = &adapter->hw;
3100 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3101 u32 rxdctl;
3102 u8 reg_idx = ring->reg_idx;
3103
3104 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3105 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3106
3107 /* write value back with RXDCTL.ENABLE bit cleared */
3108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3109
3110 if (hw->mac.type == ixgbe_mac_82598EB &&
3111 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3112 return;
3113
3114 /* the hardware may take up to 100us to really disable the rx queue */
3115 do {
3116 udelay(10);
3117 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3118 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3119
3120 if (!wait_loop) {
3121 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3122 "the polling period\n", reg_idx);
3123 }
3124 }
3125
3126 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3127 struct ixgbe_ring *ring)
3128 {
3129 struct ixgbe_hw *hw = &adapter->hw;
3130 u64 rdba = ring->dma;
3131 u32 rxdctl;
3132 u8 reg_idx = ring->reg_idx;
3133
3134 /* disable queue to avoid issues while updating state */
3135 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3136 ixgbe_disable_rx_queue(adapter, ring);
3137
3138 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3139 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3140 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3141 ring->count * sizeof(union ixgbe_adv_rx_desc));
3142 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3143 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3144 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3145
3146 ixgbe_configure_srrctl(adapter, ring);
3147 ixgbe_configure_rscctl(adapter, ring);
3148
3149 /* If operating in IOV mode set RLPML for X540 */
3150 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3151 hw->mac.type == ixgbe_mac_X540) {
3152 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3153 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3154 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3155 }
3156
3157 if (hw->mac.type == ixgbe_mac_82598EB) {
3158 /*
3159 * enable cache line friendly hardware writes:
3160 * PTHRESH=32 descriptors (half the internal cache),
3161 * this also removes ugly rx_no_buffer_count increment
3162 * HTHRESH=4 descriptors (to minimize latency on fetch)
3163 * WTHRESH=8 burst writeback up to two cache lines
3164 */
3165 rxdctl &= ~0x3FFFFF;
3166 rxdctl |= 0x080420;
3167 }
3168
3169 /* enable receive descriptor ring */
3170 rxdctl |= IXGBE_RXDCTL_ENABLE;
3171 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3172
3173 ixgbe_rx_desc_queue_enable(adapter, ring);
3174 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3175 }
3176
3177 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3178 {
3179 struct ixgbe_hw *hw = &adapter->hw;
3180 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3181 int p;
3182
3183 /* PSRTYPE must be initialized in non 82598 adapters */
3184 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3185 IXGBE_PSRTYPE_UDPHDR |
3186 IXGBE_PSRTYPE_IPV4HDR |
3187 IXGBE_PSRTYPE_L2HDR |
3188 IXGBE_PSRTYPE_IPV6HDR;
3189
3190 if (hw->mac.type == ixgbe_mac_82598EB)
3191 return;
3192
3193 if (rss_i > 3)
3194 psrtype |= 2 << 29;
3195 else if (rss_i > 1)
3196 psrtype |= 1 << 29;
3197
3198 for (p = 0; p < adapter->num_rx_pools; p++)
3199 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3200 psrtype);
3201 }
3202
3203 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3204 {
3205 struct ixgbe_hw *hw = &adapter->hw;
3206 u32 reg_offset, vf_shift;
3207 u32 gcr_ext, vmdctl;
3208 int i;
3209
3210 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3211 return;
3212
3213 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3214 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3215 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3216 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3217 vmdctl |= IXGBE_VT_CTL_REPLEN;
3218 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3219
3220 vf_shift = VMDQ_P(0) % 32;
3221 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3222
3223 /* Enable only the PF's pool for Tx/Rx */
3224 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3225 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3226 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3227 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3228
3229 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3230 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3231
3232 /*
3233 * Set up VF register offsets for selected VT Mode,
3234 * i.e. 32 or 64 VFs for SR-IOV
3235 */
3236 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3237 case IXGBE_82599_VMDQ_8Q_MASK:
3238 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3239 break;
3240 case IXGBE_82599_VMDQ_4Q_MASK:
3241 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3242 break;
3243 default:
3244 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3245 break;
3246 }
3247
3248 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3249
3250
3251 /* Enable MAC Anti-Spoofing */
3252 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3253 adapter->num_vfs);
3254 /* For VFs that have spoof checking turned off */
3255 for (i = 0; i < adapter->num_vfs; i++) {
3256 if (!adapter->vfinfo[i].spoofchk_enabled)
3257 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3258 }
3259 }
3260
3261 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3262 {
3263 struct ixgbe_hw *hw = &adapter->hw;
3264 struct net_device *netdev = adapter->netdev;
3265 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3266 struct ixgbe_ring *rx_ring;
3267 int i;
3268 u32 mhadd, hlreg0;
3269
3270 #ifdef IXGBE_FCOE
3271 /* adjust max frame to be able to do baby jumbo for FCoE */
3272 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3273 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3274 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3275
3276 #endif /* IXGBE_FCOE */
3277
3278 /* adjust max frame to be at least the size of a standard frame */
3279 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3280 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3281
3282 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3283 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3284 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3285 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3286
3287 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3288 }
3289
3290 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3291 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3292 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3293 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3294
3295 /*
3296 * Setup the HW Rx Head and Tail Descriptor Pointers and
3297 * the Base and Length of the Rx Descriptor Ring
3298 */
3299 for (i = 0; i < adapter->num_rx_queues; i++) {
3300 rx_ring = adapter->rx_ring[i];
3301 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3302 set_ring_rsc_enabled(rx_ring);
3303 else
3304 clear_ring_rsc_enabled(rx_ring);
3305 }
3306 }
3307
3308 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3309 {
3310 struct ixgbe_hw *hw = &adapter->hw;
3311 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3312
3313 switch (hw->mac.type) {
3314 case ixgbe_mac_82598EB:
3315 /*
3316 * For VMDq support of different descriptor types or
3317 * buffer sizes through the use of multiple SRRCTL
3318 * registers, RDRXCTL.MVMEN must be set to 1
3319 *
3320 * also, the manual doesn't mention it clearly but DCA hints
3321 * will only use queue 0's tags unless this bit is set. Side
3322 * effects of setting this bit are only that SRRCTL must be
3323 * fully programmed [0..15]
3324 */
3325 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3326 break;
3327 case ixgbe_mac_82599EB:
3328 case ixgbe_mac_X540:
3329 /* Disable RSC for ACK packets */
3330 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3331 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3332 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3333 /* hardware requires some bits to be set by default */
3334 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3335 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3336 break;
3337 default:
3338 /* We should do nothing since we don't know this hardware */
3339 return;
3340 }
3341
3342 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3343 }
3344
3345 /**
3346 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3347 * @adapter: board private structure
3348 *
3349 * Configure the Rx unit of the MAC after a reset.
3350 **/
3351 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3352 {
3353 struct ixgbe_hw *hw = &adapter->hw;
3354 int i;
3355 u32 rxctrl;
3356
3357 /* disable receives while setting up the descriptors */
3358 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3359 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3360
3361 ixgbe_setup_psrtype(adapter);
3362 ixgbe_setup_rdrxctl(adapter);
3363
3364 /* Program registers for the distribution of queues */
3365 ixgbe_setup_mrqc(adapter);
3366
3367 /* set_rx_buffer_len must be called before ring initialization */
3368 ixgbe_set_rx_buffer_len(adapter);
3369
3370 /*
3371 * Setup the HW Rx Head and Tail Descriptor Pointers and
3372 * the Base and Length of the Rx Descriptor Ring
3373 */
3374 for (i = 0; i < adapter->num_rx_queues; i++)
3375 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3376
3377 /* disable drop enable for 82598 parts */
3378 if (hw->mac.type == ixgbe_mac_82598EB)
3379 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3380
3381 /* enable all receives */
3382 rxctrl |= IXGBE_RXCTRL_RXEN;
3383 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3384 }
3385
3386 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3387 {
3388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3389 struct ixgbe_hw *hw = &adapter->hw;
3390
3391 /* add VID to filter table */
3392 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3393 set_bit(vid, adapter->active_vlans);
3394
3395 return 0;
3396 }
3397
3398 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3399 {
3400 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3401 struct ixgbe_hw *hw = &adapter->hw;
3402
3403 /* remove VID from filter table */
3404 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3405 clear_bit(vid, adapter->active_vlans);
3406
3407 return 0;
3408 }
3409
3410 /**
3411 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3412 * @adapter: driver data
3413 */
3414 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3415 {
3416 struct ixgbe_hw *hw = &adapter->hw;
3417 u32 vlnctrl;
3418
3419 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3420 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3421 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3422 }
3423
3424 /**
3425 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3426 * @adapter: driver data
3427 */
3428 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3429 {
3430 struct ixgbe_hw *hw = &adapter->hw;
3431 u32 vlnctrl;
3432
3433 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3434 vlnctrl |= IXGBE_VLNCTRL_VFE;
3435 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3436 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3437 }
3438
3439 /**
3440 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3441 * @adapter: driver data
3442 */
3443 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3444 {
3445 struct ixgbe_hw *hw = &adapter->hw;
3446 u32 vlnctrl;
3447 int i, j;
3448
3449 switch (hw->mac.type) {
3450 case ixgbe_mac_82598EB:
3451 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3452 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3453 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3454 break;
3455 case ixgbe_mac_82599EB:
3456 case ixgbe_mac_X540:
3457 for (i = 0; i < adapter->num_rx_queues; i++) {
3458 j = adapter->rx_ring[i]->reg_idx;
3459 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3460 vlnctrl &= ~IXGBE_RXDCTL_VME;
3461 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3462 }
3463 break;
3464 default:
3465 break;
3466 }
3467 }
3468
3469 /**
3470 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3471 * @adapter: driver data
3472 */
3473 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3474 {
3475 struct ixgbe_hw *hw = &adapter->hw;
3476 u32 vlnctrl;
3477 int i, j;
3478
3479 switch (hw->mac.type) {
3480 case ixgbe_mac_82598EB:
3481 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3482 vlnctrl |= IXGBE_VLNCTRL_VME;
3483 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3484 break;
3485 case ixgbe_mac_82599EB:
3486 case ixgbe_mac_X540:
3487 for (i = 0; i < adapter->num_rx_queues; i++) {
3488 j = adapter->rx_ring[i]->reg_idx;
3489 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3490 vlnctrl |= IXGBE_RXDCTL_VME;
3491 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3492 }
3493 break;
3494 default:
3495 break;
3496 }
3497 }
3498
3499 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3500 {
3501 u16 vid;
3502
3503 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3504
3505 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3506 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3507 }
3508
3509 /**
3510 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3511 * @netdev: network interface device structure
3512 *
3513 * Writes unicast address list to the RAR table.
3514 * Returns: -ENOMEM on failure/insufficient address space
3515 * 0 on no addresses written
3516 * X on writing X addresses to the RAR table
3517 **/
3518 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3519 {
3520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3521 struct ixgbe_hw *hw = &adapter->hw;
3522 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3523 int count = 0;
3524
3525 /* In SR-IOV mode significantly less RAR entries are available */
3526 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3527 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3528
3529 /* return ENOMEM indicating insufficient memory for addresses */
3530 if (netdev_uc_count(netdev) > rar_entries)
3531 return -ENOMEM;
3532
3533 if (!netdev_uc_empty(netdev)) {
3534 struct netdev_hw_addr *ha;
3535 /* return error if we do not support writing to RAR table */
3536 if (!hw->mac.ops.set_rar)
3537 return -ENOMEM;
3538
3539 netdev_for_each_uc_addr(ha, netdev) {
3540 if (!rar_entries)
3541 break;
3542 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3543 VMDQ_P(0), IXGBE_RAH_AV);
3544 count++;
3545 }
3546 }
3547 /* write the addresses in reverse order to avoid write combining */
3548 for (; rar_entries > 0 ; rar_entries--)
3549 hw->mac.ops.clear_rar(hw, rar_entries);
3550
3551 return count;
3552 }
3553
3554 /**
3555 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3556 * @netdev: network interface device structure
3557 *
3558 * The set_rx_method entry point is called whenever the unicast/multicast
3559 * address list or the network interface flags are updated. This routine is
3560 * responsible for configuring the hardware for proper unicast, multicast and
3561 * promiscuous mode.
3562 **/
3563 void ixgbe_set_rx_mode(struct net_device *netdev)
3564 {
3565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3566 struct ixgbe_hw *hw = &adapter->hw;
3567 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3568 int count;
3569
3570 /* Check for Promiscuous and All Multicast modes */
3571
3572 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3573
3574 /* set all bits that we expect to always be set */
3575 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3576 fctrl |= IXGBE_FCTRL_BAM;
3577 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3578 fctrl |= IXGBE_FCTRL_PMCF;
3579
3580 /* clear the bits we are changing the status of */
3581 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3582
3583 if (netdev->flags & IFF_PROMISC) {
3584 hw->addr_ctrl.user_set_promisc = true;
3585 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3586 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3587 /* don't hardware filter vlans in promisc mode */
3588 ixgbe_vlan_filter_disable(adapter);
3589 } else {
3590 if (netdev->flags & IFF_ALLMULTI) {
3591 fctrl |= IXGBE_FCTRL_MPE;
3592 vmolr |= IXGBE_VMOLR_MPE;
3593 } else {
3594 /*
3595 * Write addresses to the MTA, if the attempt fails
3596 * then we should just turn on promiscuous mode so
3597 * that we can at least receive multicast traffic
3598 */
3599 hw->mac.ops.update_mc_addr_list(hw, netdev);
3600 vmolr |= IXGBE_VMOLR_ROMPE;
3601 }
3602 ixgbe_vlan_filter_enable(adapter);
3603 hw->addr_ctrl.user_set_promisc = false;
3604 }
3605
3606 /*
3607 * Write addresses to available RAR registers, if there is not
3608 * sufficient space to store all the addresses then enable
3609 * unicast promiscuous mode
3610 */
3611 count = ixgbe_write_uc_addr_list(netdev);
3612 if (count < 0) {
3613 fctrl |= IXGBE_FCTRL_UPE;
3614 vmolr |= IXGBE_VMOLR_ROPE;
3615 }
3616
3617 if (adapter->num_vfs)
3618 ixgbe_restore_vf_multicasts(adapter);
3619
3620 if (hw->mac.type != ixgbe_mac_82598EB) {
3621 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3622 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3623 IXGBE_VMOLR_ROPE);
3624 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3625 }
3626
3627 /* This is useful for sniffing bad packets. */
3628 if (adapter->netdev->features & NETIF_F_RXALL) {
3629 /* UPE and MPE will be handled by normal PROMISC logic
3630 * in e1000e_set_rx_mode */
3631 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3632 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3633 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3634
3635 fctrl &= ~(IXGBE_FCTRL_DPF);
3636 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3637 }
3638
3639 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3640
3641 if (netdev->features & NETIF_F_HW_VLAN_RX)
3642 ixgbe_vlan_strip_enable(adapter);
3643 else
3644 ixgbe_vlan_strip_disable(adapter);
3645 }
3646
3647 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3648 {
3649 int q_idx;
3650
3651 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3652 napi_enable(&adapter->q_vector[q_idx]->napi);
3653 }
3654
3655 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3656 {
3657 int q_idx;
3658
3659 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3660 napi_disable(&adapter->q_vector[q_idx]->napi);
3661 }
3662
3663 #ifdef CONFIG_IXGBE_DCB
3664 /**
3665 * ixgbe_configure_dcb - Configure DCB hardware
3666 * @adapter: ixgbe adapter struct
3667 *
3668 * This is called by the driver on open to configure the DCB hardware.
3669 * This is also called by the gennetlink interface when reconfiguring
3670 * the DCB state.
3671 */
3672 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3673 {
3674 struct ixgbe_hw *hw = &adapter->hw;
3675 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3676
3677 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3678 if (hw->mac.type == ixgbe_mac_82598EB)
3679 netif_set_gso_max_size(adapter->netdev, 65536);
3680 return;
3681 }
3682
3683 if (hw->mac.type == ixgbe_mac_82598EB)
3684 netif_set_gso_max_size(adapter->netdev, 32768);
3685
3686 #ifdef IXGBE_FCOE
3687 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3688 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3689 #endif
3690
3691 /* reconfigure the hardware */
3692 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3693 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3694 DCB_TX_CONFIG);
3695 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3696 DCB_RX_CONFIG);
3697 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3698 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3699 ixgbe_dcb_hw_ets(&adapter->hw,
3700 adapter->ixgbe_ieee_ets,
3701 max_frame);
3702 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3703 adapter->ixgbe_ieee_pfc->pfc_en,
3704 adapter->ixgbe_ieee_ets->prio_tc);
3705 }
3706
3707 /* Enable RSS Hash per TC */
3708 if (hw->mac.type != ixgbe_mac_82598EB) {
3709 u32 msb = 0;
3710 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3711
3712 while (rss_i) {
3713 msb++;
3714 rss_i >>= 1;
3715 }
3716
3717 /* write msb to all 8 TCs in one write */
3718 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3719 }
3720 }
3721 #endif
3722
3723 /* Additional bittime to account for IXGBE framing */
3724 #define IXGBE_ETH_FRAMING 20
3725
3726 /**
3727 * ixgbe_hpbthresh - calculate high water mark for flow control
3728 *
3729 * @adapter: board private structure to calculate for
3730 * @pb: packet buffer to calculate
3731 */
3732 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3733 {
3734 struct ixgbe_hw *hw = &adapter->hw;
3735 struct net_device *dev = adapter->netdev;
3736 int link, tc, kb, marker;
3737 u32 dv_id, rx_pba;
3738
3739 /* Calculate max LAN frame size */
3740 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3741
3742 #ifdef IXGBE_FCOE
3743 /* FCoE traffic class uses FCOE jumbo frames */
3744 if ((dev->features & NETIF_F_FCOE_MTU) &&
3745 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3746 (pb == ixgbe_fcoe_get_tc(adapter)))
3747 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3748
3749 #endif
3750 /* Calculate delay value for device */
3751 switch (hw->mac.type) {
3752 case ixgbe_mac_X540:
3753 dv_id = IXGBE_DV_X540(link, tc);
3754 break;
3755 default:
3756 dv_id = IXGBE_DV(link, tc);
3757 break;
3758 }
3759
3760 /* Loopback switch introduces additional latency */
3761 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3762 dv_id += IXGBE_B2BT(tc);
3763
3764 /* Delay value is calculated in bit times convert to KB */
3765 kb = IXGBE_BT2KB(dv_id);
3766 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3767
3768 marker = rx_pba - kb;
3769
3770 /* It is possible that the packet buffer is not large enough
3771 * to provide required headroom. In this case throw an error
3772 * to user and a do the best we can.
3773 */
3774 if (marker < 0) {
3775 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3776 "headroom to support flow control."
3777 "Decrease MTU or number of traffic classes\n", pb);
3778 marker = tc + 1;
3779 }
3780
3781 return marker;
3782 }
3783
3784 /**
3785 * ixgbe_lpbthresh - calculate low water mark for for flow control
3786 *
3787 * @adapter: board private structure to calculate for
3788 * @pb: packet buffer to calculate
3789 */
3790 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3791 {
3792 struct ixgbe_hw *hw = &adapter->hw;
3793 struct net_device *dev = adapter->netdev;
3794 int tc;
3795 u32 dv_id;
3796
3797 /* Calculate max LAN frame size */
3798 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3799
3800 /* Calculate delay value for device */
3801 switch (hw->mac.type) {
3802 case ixgbe_mac_X540:
3803 dv_id = IXGBE_LOW_DV_X540(tc);
3804 break;
3805 default:
3806 dv_id = IXGBE_LOW_DV(tc);
3807 break;
3808 }
3809
3810 /* Delay value is calculated in bit times convert to KB */
3811 return IXGBE_BT2KB(dv_id);
3812 }
3813
3814 /*
3815 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3816 */
3817 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3818 {
3819 struct ixgbe_hw *hw = &adapter->hw;
3820 int num_tc = netdev_get_num_tc(adapter->netdev);
3821 int i;
3822
3823 if (!num_tc)
3824 num_tc = 1;
3825
3826 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3827
3828 for (i = 0; i < num_tc; i++) {
3829 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3830
3831 /* Low water marks must not be larger than high water marks */
3832 if (hw->fc.low_water > hw->fc.high_water[i])
3833 hw->fc.low_water = 0;
3834 }
3835 }
3836
3837 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3838 {
3839 struct ixgbe_hw *hw = &adapter->hw;
3840 int hdrm;
3841 u8 tc = netdev_get_num_tc(adapter->netdev);
3842
3843 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3844 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3845 hdrm = 32 << adapter->fdir_pballoc;
3846 else
3847 hdrm = 0;
3848
3849 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3850 ixgbe_pbthresh_setup(adapter);
3851 }
3852
3853 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3854 {
3855 struct ixgbe_hw *hw = &adapter->hw;
3856 struct hlist_node *node, *node2;
3857 struct ixgbe_fdir_filter *filter;
3858
3859 spin_lock(&adapter->fdir_perfect_lock);
3860
3861 if (!hlist_empty(&adapter->fdir_filter_list))
3862 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3863
3864 hlist_for_each_entry_safe(filter, node, node2,
3865 &adapter->fdir_filter_list, fdir_node) {
3866 ixgbe_fdir_write_perfect_filter_82599(hw,
3867 &filter->filter,
3868 filter->sw_idx,
3869 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3870 IXGBE_FDIR_DROP_QUEUE :
3871 adapter->rx_ring[filter->action]->reg_idx);
3872 }
3873
3874 spin_unlock(&adapter->fdir_perfect_lock);
3875 }
3876
3877 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3878 {
3879 struct ixgbe_hw *hw = &adapter->hw;
3880
3881 ixgbe_configure_pb(adapter);
3882 #ifdef CONFIG_IXGBE_DCB
3883 ixgbe_configure_dcb(adapter);
3884 #endif
3885 /*
3886 * We must restore virtualization before VLANs or else
3887 * the VLVF registers will not be populated
3888 */
3889 ixgbe_configure_virtualization(adapter);
3890
3891 ixgbe_set_rx_mode(adapter->netdev);
3892 ixgbe_restore_vlan(adapter);
3893
3894 switch (hw->mac.type) {
3895 case ixgbe_mac_82599EB:
3896 case ixgbe_mac_X540:
3897 hw->mac.ops.disable_rx_buff(hw);
3898 break;
3899 default:
3900 break;
3901 }
3902
3903 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3904 ixgbe_init_fdir_signature_82599(&adapter->hw,
3905 adapter->fdir_pballoc);
3906 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3907 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3908 adapter->fdir_pballoc);
3909 ixgbe_fdir_filter_restore(adapter);
3910 }
3911
3912 switch (hw->mac.type) {
3913 case ixgbe_mac_82599EB:
3914 case ixgbe_mac_X540:
3915 hw->mac.ops.enable_rx_buff(hw);
3916 break;
3917 default:
3918 break;
3919 }
3920
3921 #ifdef IXGBE_FCOE
3922 /* configure FCoE L2 filters, redirection table, and Rx control */
3923 ixgbe_configure_fcoe(adapter);
3924
3925 #endif /* IXGBE_FCOE */
3926 ixgbe_configure_tx(adapter);
3927 ixgbe_configure_rx(adapter);
3928 }
3929
3930 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3931 {
3932 switch (hw->phy.type) {
3933 case ixgbe_phy_sfp_avago:
3934 case ixgbe_phy_sfp_ftl:
3935 case ixgbe_phy_sfp_intel:
3936 case ixgbe_phy_sfp_unknown:
3937 case ixgbe_phy_sfp_passive_tyco:
3938 case ixgbe_phy_sfp_passive_unknown:
3939 case ixgbe_phy_sfp_active_unknown:
3940 case ixgbe_phy_sfp_ftl_active:
3941 return true;
3942 case ixgbe_phy_nl:
3943 if (hw->mac.type == ixgbe_mac_82598EB)
3944 return true;
3945 default:
3946 return false;
3947 }
3948 }
3949
3950 /**
3951 * ixgbe_sfp_link_config - set up SFP+ link
3952 * @adapter: pointer to private adapter struct
3953 **/
3954 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3955 {
3956 /*
3957 * We are assuming the worst case scenario here, and that
3958 * is that an SFP was inserted/removed after the reset
3959 * but before SFP detection was enabled. As such the best
3960 * solution is to just start searching as soon as we start
3961 */
3962 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3963 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3964
3965 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3966 }
3967
3968 /**
3969 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3970 * @hw: pointer to private hardware struct
3971 *
3972 * Returns 0 on success, negative on failure
3973 **/
3974 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3975 {
3976 u32 autoneg;
3977 bool negotiation, link_up = false;
3978 u32 ret = IXGBE_ERR_LINK_SETUP;
3979
3980 if (hw->mac.ops.check_link)
3981 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3982
3983 if (ret)
3984 goto link_cfg_out;
3985
3986 autoneg = hw->phy.autoneg_advertised;
3987 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3988 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3989 &negotiation);
3990 if (ret)
3991 goto link_cfg_out;
3992
3993 if (hw->mac.ops.setup_link)
3994 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3995 link_cfg_out:
3996 return ret;
3997 }
3998
3999 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4000 {
4001 struct ixgbe_hw *hw = &adapter->hw;
4002 u32 gpie = 0;
4003
4004 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4005 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4006 IXGBE_GPIE_OCD;
4007 gpie |= IXGBE_GPIE_EIAME;
4008 /*
4009 * use EIAM to auto-mask when MSI-X interrupt is asserted
4010 * this saves a register write for every interrupt
4011 */
4012 switch (hw->mac.type) {
4013 case ixgbe_mac_82598EB:
4014 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4015 break;
4016 case ixgbe_mac_82599EB:
4017 case ixgbe_mac_X540:
4018 default:
4019 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4020 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4021 break;
4022 }
4023 } else {
4024 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4025 * specifically only auto mask tx and rx interrupts */
4026 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4027 }
4028
4029 /* XXX: to interrupt immediately for EICS writes, enable this */
4030 /* gpie |= IXGBE_GPIE_EIMEN; */
4031
4032 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4033 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4034
4035 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4036 case IXGBE_82599_VMDQ_8Q_MASK:
4037 gpie |= IXGBE_GPIE_VTMODE_16;
4038 break;
4039 case IXGBE_82599_VMDQ_4Q_MASK:
4040 gpie |= IXGBE_GPIE_VTMODE_32;
4041 break;
4042 default:
4043 gpie |= IXGBE_GPIE_VTMODE_64;
4044 break;
4045 }
4046 }
4047
4048 /* Enable Thermal over heat sensor interrupt */
4049 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4050 switch (adapter->hw.mac.type) {
4051 case ixgbe_mac_82599EB:
4052 gpie |= IXGBE_SDP0_GPIEN;
4053 break;
4054 case ixgbe_mac_X540:
4055 gpie |= IXGBE_EIMS_TS;
4056 break;
4057 default:
4058 break;
4059 }
4060 }
4061
4062 /* Enable fan failure interrupt */
4063 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4064 gpie |= IXGBE_SDP1_GPIEN;
4065
4066 if (hw->mac.type == ixgbe_mac_82599EB) {
4067 gpie |= IXGBE_SDP1_GPIEN;
4068 gpie |= IXGBE_SDP2_GPIEN;
4069 }
4070
4071 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4072 }
4073
4074 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4075 {
4076 struct ixgbe_hw *hw = &adapter->hw;
4077 int err;
4078 u32 ctrl_ext;
4079
4080 ixgbe_get_hw_control(adapter);
4081 ixgbe_setup_gpie(adapter);
4082
4083 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4084 ixgbe_configure_msix(adapter);
4085 else
4086 ixgbe_configure_msi_and_legacy(adapter);
4087
4088 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4089 if (hw->mac.ops.enable_tx_laser &&
4090 ((hw->phy.multispeed_fiber) ||
4091 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4092 (hw->mac.type == ixgbe_mac_82599EB))))
4093 hw->mac.ops.enable_tx_laser(hw);
4094
4095 clear_bit(__IXGBE_DOWN, &adapter->state);
4096 ixgbe_napi_enable_all(adapter);
4097
4098 if (ixgbe_is_sfp(hw)) {
4099 ixgbe_sfp_link_config(adapter);
4100 } else {
4101 err = ixgbe_non_sfp_link_config(hw);
4102 if (err)
4103 e_err(probe, "link_config FAILED %d\n", err);
4104 }
4105
4106 /* clear any pending interrupts, may auto mask */
4107 IXGBE_READ_REG(hw, IXGBE_EICR);
4108 ixgbe_irq_enable(adapter, true, true);
4109
4110 /*
4111 * If this adapter has a fan, check to see if we had a failure
4112 * before we enabled the interrupt.
4113 */
4114 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4115 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4116 if (esdp & IXGBE_ESDP_SDP1)
4117 e_crit(drv, "Fan has stopped, replace the adapter\n");
4118 }
4119
4120 /* enable transmits */
4121 netif_tx_start_all_queues(adapter->netdev);
4122
4123 /* bring the link up in the watchdog, this could race with our first
4124 * link up interrupt but shouldn't be a problem */
4125 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4126 adapter->link_check_timeout = jiffies;
4127 mod_timer(&adapter->service_timer, jiffies);
4128
4129 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4130 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4131 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4132 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4133 }
4134
4135 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4136 {
4137 WARN_ON(in_interrupt());
4138 /* put off any impending NetWatchDogTimeout */
4139 adapter->netdev->trans_start = jiffies;
4140
4141 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4142 usleep_range(1000, 2000);
4143 ixgbe_down(adapter);
4144 /*
4145 * If SR-IOV enabled then wait a bit before bringing the adapter
4146 * back up to give the VFs time to respond to the reset. The
4147 * two second wait is based upon the watchdog timer cycle in
4148 * the VF driver.
4149 */
4150 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4151 msleep(2000);
4152 ixgbe_up(adapter);
4153 clear_bit(__IXGBE_RESETTING, &adapter->state);
4154 }
4155
4156 void ixgbe_up(struct ixgbe_adapter *adapter)
4157 {
4158 /* hardware has been reset, we need to reload some things */
4159 ixgbe_configure(adapter);
4160
4161 ixgbe_up_complete(adapter);
4162 }
4163
4164 void ixgbe_reset(struct ixgbe_adapter *adapter)
4165 {
4166 struct ixgbe_hw *hw = &adapter->hw;
4167 int err;
4168
4169 /* lock SFP init bit to prevent race conditions with the watchdog */
4170 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4171 usleep_range(1000, 2000);
4172
4173 /* clear all SFP and link config related flags while holding SFP_INIT */
4174 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4175 IXGBE_FLAG2_SFP_NEEDS_RESET);
4176 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4177
4178 err = hw->mac.ops.init_hw(hw);
4179 switch (err) {
4180 case 0:
4181 case IXGBE_ERR_SFP_NOT_PRESENT:
4182 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4183 break;
4184 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4185 e_dev_err("master disable timed out\n");
4186 break;
4187 case IXGBE_ERR_EEPROM_VERSION:
4188 /* We are running on a pre-production device, log a warning */
4189 e_dev_warn("This device is a pre-production adapter/LOM. "
4190 "Please be aware there may be issues associated with "
4191 "your hardware. If you are experiencing problems "
4192 "please contact your Intel or hardware "
4193 "representative who provided you with this "
4194 "hardware.\n");
4195 break;
4196 default:
4197 e_dev_err("Hardware Error: %d\n", err);
4198 }
4199
4200 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4201
4202 /* reprogram the RAR[0] in case user changed it. */
4203 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4204
4205 /* update SAN MAC vmdq pool selection */
4206 if (hw->mac.san_mac_rar_index)
4207 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4208
4209 #ifdef CONFIG_IXGBE_PTP
4210 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4211 ixgbe_ptp_reset(adapter);
4212 #endif
4213 }
4214
4215 /**
4216 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4217 * @rx_ring: ring to free buffers from
4218 **/
4219 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4220 {
4221 struct device *dev = rx_ring->dev;
4222 unsigned long size;
4223 u16 i;
4224
4225 /* ring already cleared, nothing to do */
4226 if (!rx_ring->rx_buffer_info)
4227 return;
4228
4229 /* Free all the Rx ring sk_buffs */
4230 for (i = 0; i < rx_ring->count; i++) {
4231 struct ixgbe_rx_buffer *rx_buffer;
4232
4233 rx_buffer = &rx_ring->rx_buffer_info[i];
4234 if (rx_buffer->skb) {
4235 struct sk_buff *skb = rx_buffer->skb;
4236 if (IXGBE_CB(skb)->page_released) {
4237 dma_unmap_page(dev,
4238 IXGBE_CB(skb)->dma,
4239 ixgbe_rx_bufsz(rx_ring),
4240 DMA_FROM_DEVICE);
4241 IXGBE_CB(skb)->page_released = false;
4242 }
4243 dev_kfree_skb(skb);
4244 }
4245 rx_buffer->skb = NULL;
4246 if (rx_buffer->dma)
4247 dma_unmap_page(dev, rx_buffer->dma,
4248 ixgbe_rx_pg_size(rx_ring),
4249 DMA_FROM_DEVICE);
4250 rx_buffer->dma = 0;
4251 if (rx_buffer->page)
4252 __free_pages(rx_buffer->page,
4253 ixgbe_rx_pg_order(rx_ring));
4254 rx_buffer->page = NULL;
4255 }
4256
4257 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4258 memset(rx_ring->rx_buffer_info, 0, size);
4259
4260 /* Zero out the descriptor ring */
4261 memset(rx_ring->desc, 0, rx_ring->size);
4262
4263 rx_ring->next_to_alloc = 0;
4264 rx_ring->next_to_clean = 0;
4265 rx_ring->next_to_use = 0;
4266 }
4267
4268 /**
4269 * ixgbe_clean_tx_ring - Free Tx Buffers
4270 * @tx_ring: ring to be cleaned
4271 **/
4272 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4273 {
4274 struct ixgbe_tx_buffer *tx_buffer_info;
4275 unsigned long size;
4276 u16 i;
4277
4278 /* ring already cleared, nothing to do */
4279 if (!tx_ring->tx_buffer_info)
4280 return;
4281
4282 /* Free all the Tx ring sk_buffs */
4283 for (i = 0; i < tx_ring->count; i++) {
4284 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4285 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4286 }
4287
4288 netdev_tx_reset_queue(txring_txq(tx_ring));
4289
4290 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4291 memset(tx_ring->tx_buffer_info, 0, size);
4292
4293 /* Zero out the descriptor ring */
4294 memset(tx_ring->desc, 0, tx_ring->size);
4295
4296 tx_ring->next_to_use = 0;
4297 tx_ring->next_to_clean = 0;
4298 }
4299
4300 /**
4301 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4302 * @adapter: board private structure
4303 **/
4304 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4305 {
4306 int i;
4307
4308 for (i = 0; i < adapter->num_rx_queues; i++)
4309 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4310 }
4311
4312 /**
4313 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4314 * @adapter: board private structure
4315 **/
4316 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4317 {
4318 int i;
4319
4320 for (i = 0; i < adapter->num_tx_queues; i++)
4321 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4322 }
4323
4324 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4325 {
4326 struct hlist_node *node, *node2;
4327 struct ixgbe_fdir_filter *filter;
4328
4329 spin_lock(&adapter->fdir_perfect_lock);
4330
4331 hlist_for_each_entry_safe(filter, node, node2,
4332 &adapter->fdir_filter_list, fdir_node) {
4333 hlist_del(&filter->fdir_node);
4334 kfree(filter);
4335 }
4336 adapter->fdir_filter_count = 0;
4337
4338 spin_unlock(&adapter->fdir_perfect_lock);
4339 }
4340
4341 void ixgbe_down(struct ixgbe_adapter *adapter)
4342 {
4343 struct net_device *netdev = adapter->netdev;
4344 struct ixgbe_hw *hw = &adapter->hw;
4345 u32 rxctrl;
4346 int i;
4347
4348 /* signal that we are down to the interrupt handler */
4349 set_bit(__IXGBE_DOWN, &adapter->state);
4350
4351 /* disable receives */
4352 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4353 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4354
4355 /* disable all enabled rx queues */
4356 for (i = 0; i < adapter->num_rx_queues; i++)
4357 /* this call also flushes the previous write */
4358 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4359
4360 usleep_range(10000, 20000);
4361
4362 netif_tx_stop_all_queues(netdev);
4363
4364 /* call carrier off first to avoid false dev_watchdog timeouts */
4365 netif_carrier_off(netdev);
4366 netif_tx_disable(netdev);
4367
4368 ixgbe_irq_disable(adapter);
4369
4370 ixgbe_napi_disable_all(adapter);
4371
4372 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4373 IXGBE_FLAG2_RESET_REQUESTED);
4374 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4375
4376 del_timer_sync(&adapter->service_timer);
4377
4378 if (adapter->num_vfs) {
4379 /* Clear EITR Select mapping */
4380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4381
4382 /* Mark all the VFs as inactive */
4383 for (i = 0 ; i < adapter->num_vfs; i++)
4384 adapter->vfinfo[i].clear_to_send = false;
4385
4386 /* ping all the active vfs to let them know we are going down */
4387 ixgbe_ping_all_vfs(adapter);
4388
4389 /* Disable all VFTE/VFRE TX/RX */
4390 ixgbe_disable_tx_rx(adapter);
4391 }
4392
4393 /* disable transmits in the hardware now that interrupts are off */
4394 for (i = 0; i < adapter->num_tx_queues; i++) {
4395 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4396 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4397 }
4398
4399 /* Disable the Tx DMA engine on 82599 and X540 */
4400 switch (hw->mac.type) {
4401 case ixgbe_mac_82599EB:
4402 case ixgbe_mac_X540:
4403 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4404 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4405 ~IXGBE_DMATXCTL_TE));
4406 break;
4407 default:
4408 break;
4409 }
4410
4411 if (!pci_channel_offline(adapter->pdev))
4412 ixgbe_reset(adapter);
4413
4414 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4415 if (hw->mac.ops.disable_tx_laser &&
4416 ((hw->phy.multispeed_fiber) ||
4417 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4418 (hw->mac.type == ixgbe_mac_82599EB))))
4419 hw->mac.ops.disable_tx_laser(hw);
4420
4421 ixgbe_clean_all_tx_rings(adapter);
4422 ixgbe_clean_all_rx_rings(adapter);
4423
4424 #ifdef CONFIG_IXGBE_DCA
4425 /* since we reset the hardware DCA settings were cleared */
4426 ixgbe_setup_dca(adapter);
4427 #endif
4428 }
4429
4430 /**
4431 * ixgbe_tx_timeout - Respond to a Tx Hang
4432 * @netdev: network interface device structure
4433 **/
4434 static void ixgbe_tx_timeout(struct net_device *netdev)
4435 {
4436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4437
4438 /* Do the reset outside of interrupt context */
4439 ixgbe_tx_timeout_reset(adapter);
4440 }
4441
4442 /**
4443 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4444 * @adapter: board private structure to initialize
4445 *
4446 * ixgbe_sw_init initializes the Adapter private data structure.
4447 * Fields are initialized based on PCI device information and
4448 * OS network device settings (MTU size).
4449 **/
4450 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4451 {
4452 struct ixgbe_hw *hw = &adapter->hw;
4453 struct pci_dev *pdev = adapter->pdev;
4454 unsigned int rss;
4455 #ifdef CONFIG_IXGBE_DCB
4456 int j;
4457 struct tc_configuration *tc;
4458 #endif
4459
4460 /* PCI config space info */
4461
4462 hw->vendor_id = pdev->vendor;
4463 hw->device_id = pdev->device;
4464 hw->revision_id = pdev->revision;
4465 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4466 hw->subsystem_device_id = pdev->subsystem_device;
4467
4468 /* Set capability flags */
4469 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4470 adapter->ring_feature[RING_F_RSS].limit = rss;
4471 switch (hw->mac.type) {
4472 case ixgbe_mac_82598EB:
4473 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4474 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4475 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4476 break;
4477 case ixgbe_mac_X540:
4478 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4479 case ixgbe_mac_82599EB:
4480 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4481 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4482 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4483 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4484 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4485 /* Flow Director hash filters enabled */
4486 adapter->atr_sample_rate = 20;
4487 adapter->ring_feature[RING_F_FDIR].limit =
4488 IXGBE_MAX_FDIR_INDICES;
4489 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4490 #ifdef IXGBE_FCOE
4491 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4492 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4493 #ifdef CONFIG_IXGBE_DCB
4494 /* Default traffic class to use for FCoE */
4495 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4496 #endif
4497 #endif /* IXGBE_FCOE */
4498 break;
4499 default:
4500 break;
4501 }
4502
4503 #ifdef IXGBE_FCOE
4504 /* FCoE support exists, always init the FCoE lock */
4505 spin_lock_init(&adapter->fcoe.lock);
4506
4507 #endif
4508 /* n-tuple support exists, always init our spinlock */
4509 spin_lock_init(&adapter->fdir_perfect_lock);
4510
4511 #ifdef CONFIG_IXGBE_DCB
4512 switch (hw->mac.type) {
4513 case ixgbe_mac_X540:
4514 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4515 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4516 break;
4517 default:
4518 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4519 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4520 break;
4521 }
4522
4523 /* Configure DCB traffic classes */
4524 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4525 tc = &adapter->dcb_cfg.tc_config[j];
4526 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4527 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4528 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4529 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4530 tc->dcb_pfc = pfc_disabled;
4531 }
4532
4533 /* Initialize default user to priority mapping, UPx->TC0 */
4534 tc = &adapter->dcb_cfg.tc_config[0];
4535 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4536 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4537
4538 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4539 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4540 adapter->dcb_cfg.pfc_mode_enable = false;
4541 adapter->dcb_set_bitmap = 0x00;
4542 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4543 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4544 sizeof(adapter->temp_dcb_cfg));
4545
4546 #endif
4547
4548 /* default flow control settings */
4549 hw->fc.requested_mode = ixgbe_fc_full;
4550 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4551 ixgbe_pbthresh_setup(adapter);
4552 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4553 hw->fc.send_xon = true;
4554 hw->fc.disable_fc_autoneg = false;
4555
4556 #ifdef CONFIG_PCI_IOV
4557 /* assign number of SR-IOV VFs */
4558 if (hw->mac.type != ixgbe_mac_82598EB)
4559 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4560
4561 #endif
4562 /* enable itr by default in dynamic mode */
4563 adapter->rx_itr_setting = 1;
4564 adapter->tx_itr_setting = 1;
4565
4566 /* set default ring sizes */
4567 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4568 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4569
4570 /* set default work limits */
4571 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4572
4573 /* initialize eeprom parameters */
4574 if (ixgbe_init_eeprom_params_generic(hw)) {
4575 e_dev_err("EEPROM initialization failed\n");
4576 return -EIO;
4577 }
4578
4579 set_bit(__IXGBE_DOWN, &adapter->state);
4580
4581 return 0;
4582 }
4583
4584 /**
4585 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4586 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4587 *
4588 * Return 0 on success, negative on failure
4589 **/
4590 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4591 {
4592 struct device *dev = tx_ring->dev;
4593 int orig_node = dev_to_node(dev);
4594 int numa_node = -1;
4595 int size;
4596
4597 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4598
4599 if (tx_ring->q_vector)
4600 numa_node = tx_ring->q_vector->numa_node;
4601
4602 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4603 if (!tx_ring->tx_buffer_info)
4604 tx_ring->tx_buffer_info = vzalloc(size);
4605 if (!tx_ring->tx_buffer_info)
4606 goto err;
4607
4608 /* round up to nearest 4K */
4609 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4610 tx_ring->size = ALIGN(tx_ring->size, 4096);
4611
4612 set_dev_node(dev, numa_node);
4613 tx_ring->desc = dma_alloc_coherent(dev,
4614 tx_ring->size,
4615 &tx_ring->dma,
4616 GFP_KERNEL);
4617 set_dev_node(dev, orig_node);
4618 if (!tx_ring->desc)
4619 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4620 &tx_ring->dma, GFP_KERNEL);
4621 if (!tx_ring->desc)
4622 goto err;
4623
4624 tx_ring->next_to_use = 0;
4625 tx_ring->next_to_clean = 0;
4626 return 0;
4627
4628 err:
4629 vfree(tx_ring->tx_buffer_info);
4630 tx_ring->tx_buffer_info = NULL;
4631 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4632 return -ENOMEM;
4633 }
4634
4635 /**
4636 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4637 * @adapter: board private structure
4638 *
4639 * If this function returns with an error, then it's possible one or
4640 * more of the rings is populated (while the rest are not). It is the
4641 * callers duty to clean those orphaned rings.
4642 *
4643 * Return 0 on success, negative on failure
4644 **/
4645 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4646 {
4647 int i, err = 0;
4648
4649 for (i = 0; i < adapter->num_tx_queues; i++) {
4650 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4651 if (!err)
4652 continue;
4653
4654 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4655 goto err_setup_tx;
4656 }
4657
4658 return 0;
4659 err_setup_tx:
4660 /* rewind the index freeing the rings as we go */
4661 while (i--)
4662 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4663 return err;
4664 }
4665
4666 /**
4667 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4668 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4669 *
4670 * Returns 0 on success, negative on failure
4671 **/
4672 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4673 {
4674 struct device *dev = rx_ring->dev;
4675 int orig_node = dev_to_node(dev);
4676 int numa_node = -1;
4677 int size;
4678
4679 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4680
4681 if (rx_ring->q_vector)
4682 numa_node = rx_ring->q_vector->numa_node;
4683
4684 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4685 if (!rx_ring->rx_buffer_info)
4686 rx_ring->rx_buffer_info = vzalloc(size);
4687 if (!rx_ring->rx_buffer_info)
4688 goto err;
4689
4690 /* Round up to nearest 4K */
4691 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4692 rx_ring->size = ALIGN(rx_ring->size, 4096);
4693
4694 set_dev_node(dev, numa_node);
4695 rx_ring->desc = dma_alloc_coherent(dev,
4696 rx_ring->size,
4697 &rx_ring->dma,
4698 GFP_KERNEL);
4699 set_dev_node(dev, orig_node);
4700 if (!rx_ring->desc)
4701 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4702 &rx_ring->dma, GFP_KERNEL);
4703 if (!rx_ring->desc)
4704 goto err;
4705
4706 rx_ring->next_to_clean = 0;
4707 rx_ring->next_to_use = 0;
4708
4709 return 0;
4710 err:
4711 vfree(rx_ring->rx_buffer_info);
4712 rx_ring->rx_buffer_info = NULL;
4713 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4714 return -ENOMEM;
4715 }
4716
4717 /**
4718 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4719 * @adapter: board private structure
4720 *
4721 * If this function returns with an error, then it's possible one or
4722 * more of the rings is populated (while the rest are not). It is the
4723 * callers duty to clean those orphaned rings.
4724 *
4725 * Return 0 on success, negative on failure
4726 **/
4727 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4728 {
4729 int i, err = 0;
4730
4731 for (i = 0; i < adapter->num_rx_queues; i++) {
4732 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4733 if (!err)
4734 continue;
4735
4736 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4737 goto err_setup_rx;
4738 }
4739
4740 #ifdef IXGBE_FCOE
4741 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4742 if (!err)
4743 #endif
4744 return 0;
4745 err_setup_rx:
4746 /* rewind the index freeing the rings as we go */
4747 while (i--)
4748 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4749 return err;
4750 }
4751
4752 /**
4753 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4754 * @tx_ring: Tx descriptor ring for a specific queue
4755 *
4756 * Free all transmit software resources
4757 **/
4758 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4759 {
4760 ixgbe_clean_tx_ring(tx_ring);
4761
4762 vfree(tx_ring->tx_buffer_info);
4763 tx_ring->tx_buffer_info = NULL;
4764
4765 /* if not set, then don't free */
4766 if (!tx_ring->desc)
4767 return;
4768
4769 dma_free_coherent(tx_ring->dev, tx_ring->size,
4770 tx_ring->desc, tx_ring->dma);
4771
4772 tx_ring->desc = NULL;
4773 }
4774
4775 /**
4776 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4777 * @adapter: board private structure
4778 *
4779 * Free all transmit software resources
4780 **/
4781 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4782 {
4783 int i;
4784
4785 for (i = 0; i < adapter->num_tx_queues; i++)
4786 if (adapter->tx_ring[i]->desc)
4787 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4788 }
4789
4790 /**
4791 * ixgbe_free_rx_resources - Free Rx Resources
4792 * @rx_ring: ring to clean the resources from
4793 *
4794 * Free all receive software resources
4795 **/
4796 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4797 {
4798 ixgbe_clean_rx_ring(rx_ring);
4799
4800 vfree(rx_ring->rx_buffer_info);
4801 rx_ring->rx_buffer_info = NULL;
4802
4803 /* if not set, then don't free */
4804 if (!rx_ring->desc)
4805 return;
4806
4807 dma_free_coherent(rx_ring->dev, rx_ring->size,
4808 rx_ring->desc, rx_ring->dma);
4809
4810 rx_ring->desc = NULL;
4811 }
4812
4813 /**
4814 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4815 * @adapter: board private structure
4816 *
4817 * Free all receive software resources
4818 **/
4819 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4820 {
4821 int i;
4822
4823 #ifdef IXGBE_FCOE
4824 ixgbe_free_fcoe_ddp_resources(adapter);
4825
4826 #endif
4827 for (i = 0; i < adapter->num_rx_queues; i++)
4828 if (adapter->rx_ring[i]->desc)
4829 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4830 }
4831
4832 /**
4833 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4834 * @netdev: network interface device structure
4835 * @new_mtu: new value for maximum frame size
4836 *
4837 * Returns 0 on success, negative on failure
4838 **/
4839 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4840 {
4841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4842 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4843
4844 /* MTU < 68 is an error and causes problems on some kernels */
4845 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4846 return -EINVAL;
4847
4848 /*
4849 * For 82599EB we cannot allow legacy VFs to enable their receive
4850 * paths when MTU greater than 1500 is configured. So display a
4851 * warning that legacy VFs will be disabled.
4852 */
4853 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4854 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4855 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4856 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4857
4858 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4859
4860 /* must set new MTU before calling down or up */
4861 netdev->mtu = new_mtu;
4862
4863 if (netif_running(netdev))
4864 ixgbe_reinit_locked(adapter);
4865
4866 return 0;
4867 }
4868
4869 /**
4870 * ixgbe_open - Called when a network interface is made active
4871 * @netdev: network interface device structure
4872 *
4873 * Returns 0 on success, negative value on failure
4874 *
4875 * The open entry point is called when a network interface is made
4876 * active by the system (IFF_UP). At this point all resources needed
4877 * for transmit and receive operations are allocated, the interrupt
4878 * handler is registered with the OS, the watchdog timer is started,
4879 * and the stack is notified that the interface is ready.
4880 **/
4881 static int ixgbe_open(struct net_device *netdev)
4882 {
4883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4884 int err;
4885
4886 /* disallow open during test */
4887 if (test_bit(__IXGBE_TESTING, &adapter->state))
4888 return -EBUSY;
4889
4890 netif_carrier_off(netdev);
4891
4892 /* allocate transmit descriptors */
4893 err = ixgbe_setup_all_tx_resources(adapter);
4894 if (err)
4895 goto err_setup_tx;
4896
4897 /* allocate receive descriptors */
4898 err = ixgbe_setup_all_rx_resources(adapter);
4899 if (err)
4900 goto err_setup_rx;
4901
4902 ixgbe_configure(adapter);
4903
4904 err = ixgbe_request_irq(adapter);
4905 if (err)
4906 goto err_req_irq;
4907
4908 /* Notify the stack of the actual queue counts. */
4909 err = netif_set_real_num_tx_queues(netdev,
4910 adapter->num_rx_pools > 1 ? 1 :
4911 adapter->num_tx_queues);
4912 if (err)
4913 goto err_set_queues;
4914
4915
4916 err = netif_set_real_num_rx_queues(netdev,
4917 adapter->num_rx_pools > 1 ? 1 :
4918 adapter->num_rx_queues);
4919 if (err)
4920 goto err_set_queues;
4921
4922 #ifdef CONFIG_IXGBE_PTP
4923 ixgbe_ptp_init(adapter);
4924 #endif /* CONFIG_IXGBE_PTP*/
4925
4926 ixgbe_up_complete(adapter);
4927
4928 return 0;
4929
4930 err_set_queues:
4931 ixgbe_free_irq(adapter);
4932 err_req_irq:
4933 ixgbe_free_all_rx_resources(adapter);
4934 err_setup_rx:
4935 ixgbe_free_all_tx_resources(adapter);
4936 err_setup_tx:
4937 ixgbe_reset(adapter);
4938
4939 return err;
4940 }
4941
4942 /**
4943 * ixgbe_close - Disables a network interface
4944 * @netdev: network interface device structure
4945 *
4946 * Returns 0, this is not allowed to fail
4947 *
4948 * The close entry point is called when an interface is de-activated
4949 * by the OS. The hardware is still under the drivers control, but
4950 * needs to be disabled. A global MAC reset is issued to stop the
4951 * hardware, and all transmit and receive resources are freed.
4952 **/
4953 static int ixgbe_close(struct net_device *netdev)
4954 {
4955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4956
4957 #ifdef CONFIG_IXGBE_PTP
4958 ixgbe_ptp_stop(adapter);
4959 #endif
4960
4961 ixgbe_down(adapter);
4962 ixgbe_free_irq(adapter);
4963
4964 ixgbe_fdir_filter_exit(adapter);
4965
4966 ixgbe_free_all_tx_resources(adapter);
4967 ixgbe_free_all_rx_resources(adapter);
4968
4969 ixgbe_release_hw_control(adapter);
4970
4971 return 0;
4972 }
4973
4974 #ifdef CONFIG_PM
4975 static int ixgbe_resume(struct pci_dev *pdev)
4976 {
4977 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4978 struct net_device *netdev = adapter->netdev;
4979 u32 err;
4980
4981 pci_set_power_state(pdev, PCI_D0);
4982 pci_restore_state(pdev);
4983 /*
4984 * pci_restore_state clears dev->state_saved so call
4985 * pci_save_state to restore it.
4986 */
4987 pci_save_state(pdev);
4988
4989 err = pci_enable_device_mem(pdev);
4990 if (err) {
4991 e_dev_err("Cannot enable PCI device from suspend\n");
4992 return err;
4993 }
4994 pci_set_master(pdev);
4995
4996 pci_wake_from_d3(pdev, false);
4997
4998 ixgbe_reset(adapter);
4999
5000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5001
5002 rtnl_lock();
5003 err = ixgbe_init_interrupt_scheme(adapter);
5004 if (!err && netif_running(netdev))
5005 err = ixgbe_open(netdev);
5006
5007 rtnl_unlock();
5008
5009 if (err)
5010 return err;
5011
5012 netif_device_attach(netdev);
5013
5014 return 0;
5015 }
5016 #endif /* CONFIG_PM */
5017
5018 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5019 {
5020 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5021 struct net_device *netdev = adapter->netdev;
5022 struct ixgbe_hw *hw = &adapter->hw;
5023 u32 ctrl, fctrl;
5024 u32 wufc = adapter->wol;
5025 #ifdef CONFIG_PM
5026 int retval = 0;
5027 #endif
5028
5029 netif_device_detach(netdev);
5030
5031 if (netif_running(netdev)) {
5032 rtnl_lock();
5033 ixgbe_down(adapter);
5034 ixgbe_free_irq(adapter);
5035 ixgbe_free_all_tx_resources(adapter);
5036 ixgbe_free_all_rx_resources(adapter);
5037 rtnl_unlock();
5038 }
5039
5040 ixgbe_clear_interrupt_scheme(adapter);
5041
5042 #ifdef CONFIG_PM
5043 retval = pci_save_state(pdev);
5044 if (retval)
5045 return retval;
5046
5047 #endif
5048 if (wufc) {
5049 ixgbe_set_rx_mode(netdev);
5050
5051 /*
5052 * enable the optics for both mult-speed fiber and
5053 * 82599 SFP+ fiber as we can WoL.
5054 */
5055 if (hw->mac.ops.enable_tx_laser &&
5056 (hw->phy.multispeed_fiber ||
5057 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
5058 hw->mac.type == ixgbe_mac_82599EB)))
5059 hw->mac.ops.enable_tx_laser(hw);
5060
5061 /* turn on all-multi mode if wake on multicast is enabled */
5062 if (wufc & IXGBE_WUFC_MC) {
5063 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5064 fctrl |= IXGBE_FCTRL_MPE;
5065 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5066 }
5067
5068 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5069 ctrl |= IXGBE_CTRL_GIO_DIS;
5070 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5071
5072 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5073 } else {
5074 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5075 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5076 }
5077
5078 switch (hw->mac.type) {
5079 case ixgbe_mac_82598EB:
5080 pci_wake_from_d3(pdev, false);
5081 break;
5082 case ixgbe_mac_82599EB:
5083 case ixgbe_mac_X540:
5084 pci_wake_from_d3(pdev, !!wufc);
5085 break;
5086 default:
5087 break;
5088 }
5089
5090 *enable_wake = !!wufc;
5091
5092 ixgbe_release_hw_control(adapter);
5093
5094 pci_disable_device(pdev);
5095
5096 return 0;
5097 }
5098
5099 #ifdef CONFIG_PM
5100 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5101 {
5102 int retval;
5103 bool wake;
5104
5105 retval = __ixgbe_shutdown(pdev, &wake);
5106 if (retval)
5107 return retval;
5108
5109 if (wake) {
5110 pci_prepare_to_sleep(pdev);
5111 } else {
5112 pci_wake_from_d3(pdev, false);
5113 pci_set_power_state(pdev, PCI_D3hot);
5114 }
5115
5116 return 0;
5117 }
5118 #endif /* CONFIG_PM */
5119
5120 static void ixgbe_shutdown(struct pci_dev *pdev)
5121 {
5122 bool wake;
5123
5124 __ixgbe_shutdown(pdev, &wake);
5125
5126 if (system_state == SYSTEM_POWER_OFF) {
5127 pci_wake_from_d3(pdev, wake);
5128 pci_set_power_state(pdev, PCI_D3hot);
5129 }
5130 }
5131
5132 /**
5133 * ixgbe_update_stats - Update the board statistics counters.
5134 * @adapter: board private structure
5135 **/
5136 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5137 {
5138 struct net_device *netdev = adapter->netdev;
5139 struct ixgbe_hw *hw = &adapter->hw;
5140 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5141 u64 total_mpc = 0;
5142 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5143 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5144 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5145 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5146
5147 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5148 test_bit(__IXGBE_RESETTING, &adapter->state))
5149 return;
5150
5151 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5152 u64 rsc_count = 0;
5153 u64 rsc_flush = 0;
5154 for (i = 0; i < adapter->num_rx_queues; i++) {
5155 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5156 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5157 }
5158 adapter->rsc_total_count = rsc_count;
5159 adapter->rsc_total_flush = rsc_flush;
5160 }
5161
5162 for (i = 0; i < adapter->num_rx_queues; i++) {
5163 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5164 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5165 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5166 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5167 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5168 bytes += rx_ring->stats.bytes;
5169 packets += rx_ring->stats.packets;
5170 }
5171 adapter->non_eop_descs = non_eop_descs;
5172 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5173 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5174 adapter->hw_csum_rx_error = hw_csum_rx_error;
5175 netdev->stats.rx_bytes = bytes;
5176 netdev->stats.rx_packets = packets;
5177
5178 bytes = 0;
5179 packets = 0;
5180 /* gather some stats to the adapter struct that are per queue */
5181 for (i = 0; i < adapter->num_tx_queues; i++) {
5182 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5183 restart_queue += tx_ring->tx_stats.restart_queue;
5184 tx_busy += tx_ring->tx_stats.tx_busy;
5185 bytes += tx_ring->stats.bytes;
5186 packets += tx_ring->stats.packets;
5187 }
5188 adapter->restart_queue = restart_queue;
5189 adapter->tx_busy = tx_busy;
5190 netdev->stats.tx_bytes = bytes;
5191 netdev->stats.tx_packets = packets;
5192
5193 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5194
5195 /* 8 register reads */
5196 for (i = 0; i < 8; i++) {
5197 /* for packet buffers not used, the register should read 0 */
5198 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5199 missed_rx += mpc;
5200 hwstats->mpc[i] += mpc;
5201 total_mpc += hwstats->mpc[i];
5202 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5203 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5204 switch (hw->mac.type) {
5205 case ixgbe_mac_82598EB:
5206 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5207 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5208 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5209 hwstats->pxonrxc[i] +=
5210 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5211 break;
5212 case ixgbe_mac_82599EB:
5213 case ixgbe_mac_X540:
5214 hwstats->pxonrxc[i] +=
5215 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5216 break;
5217 default:
5218 break;
5219 }
5220 }
5221
5222 /*16 register reads */
5223 for (i = 0; i < 16; i++) {
5224 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5225 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5226 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5227 (hw->mac.type == ixgbe_mac_X540)) {
5228 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5229 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5230 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5231 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5232 }
5233 }
5234
5235 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5236 /* work around hardware counting issue */
5237 hwstats->gprc -= missed_rx;
5238
5239 ixgbe_update_xoff_received(adapter);
5240
5241 /* 82598 hardware only has a 32 bit counter in the high register */
5242 switch (hw->mac.type) {
5243 case ixgbe_mac_82598EB:
5244 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5245 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5246 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5247 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5248 break;
5249 case ixgbe_mac_X540:
5250 /* OS2BMC stats are X540 only*/
5251 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5252 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5253 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5254 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5255 case ixgbe_mac_82599EB:
5256 for (i = 0; i < 16; i++)
5257 adapter->hw_rx_no_dma_resources +=
5258 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5259 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5260 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5261 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5262 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5263 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5264 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5265 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5266 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5267 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5268 #ifdef IXGBE_FCOE
5269 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5270 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5271 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5272 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5273 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5274 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5275 /* Add up per cpu counters for total ddp aloc fail */
5276 if (adapter->fcoe.ddp_pool) {
5277 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5278 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5279 unsigned int cpu;
5280 u64 noddp = 0, noddp_ext_buff = 0;
5281 for_each_possible_cpu(cpu) {
5282 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5283 noddp += ddp_pool->noddp;
5284 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5285 }
5286 hwstats->fcoe_noddp = noddp;
5287 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5288 }
5289 #endif /* IXGBE_FCOE */
5290 break;
5291 default:
5292 break;
5293 }
5294 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5295 hwstats->bprc += bprc;
5296 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5297 if (hw->mac.type == ixgbe_mac_82598EB)
5298 hwstats->mprc -= bprc;
5299 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5300 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5301 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5302 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5303 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5304 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5305 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5306 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5307 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5308 hwstats->lxontxc += lxon;
5309 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5310 hwstats->lxofftxc += lxoff;
5311 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5312 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5313 /*
5314 * 82598 errata - tx of flow control packets is included in tx counters
5315 */
5316 xon_off_tot = lxon + lxoff;
5317 hwstats->gptc -= xon_off_tot;
5318 hwstats->mptc -= xon_off_tot;
5319 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5320 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5321 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5322 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5323 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5324 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5325 hwstats->ptc64 -= xon_off_tot;
5326 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5327 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5328 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5329 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5330 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5331 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5332
5333 /* Fill out the OS statistics structure */
5334 netdev->stats.multicast = hwstats->mprc;
5335
5336 /* Rx Errors */
5337 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5338 netdev->stats.rx_dropped = 0;
5339 netdev->stats.rx_length_errors = hwstats->rlec;
5340 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5341 netdev->stats.rx_missed_errors = total_mpc;
5342 }
5343
5344 /**
5345 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5346 * @adapter: pointer to the device adapter structure
5347 **/
5348 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5349 {
5350 struct ixgbe_hw *hw = &adapter->hw;
5351 int i;
5352
5353 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5354 return;
5355
5356 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5357
5358 /* if interface is down do nothing */
5359 if (test_bit(__IXGBE_DOWN, &adapter->state))
5360 return;
5361
5362 /* do nothing if we are not using signature filters */
5363 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5364 return;
5365
5366 adapter->fdir_overflow++;
5367
5368 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5369 for (i = 0; i < adapter->num_tx_queues; i++)
5370 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5371 &(adapter->tx_ring[i]->state));
5372 /* re-enable flow director interrupts */
5373 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5374 } else {
5375 e_err(probe, "failed to finish FDIR re-initialization, "
5376 "ignored adding FDIR ATR filters\n");
5377 }
5378 }
5379
5380 /**
5381 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5382 * @adapter: pointer to the device adapter structure
5383 *
5384 * This function serves two purposes. First it strobes the interrupt lines
5385 * in order to make certain interrupts are occurring. Secondly it sets the
5386 * bits needed to check for TX hangs. As a result we should immediately
5387 * determine if a hang has occurred.
5388 */
5389 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5390 {
5391 struct ixgbe_hw *hw = &adapter->hw;
5392 u64 eics = 0;
5393 int i;
5394
5395 /* If we're down or resetting, just bail */
5396 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5397 test_bit(__IXGBE_RESETTING, &adapter->state))
5398 return;
5399
5400 /* Force detection of hung controller */
5401 if (netif_carrier_ok(adapter->netdev)) {
5402 for (i = 0; i < adapter->num_tx_queues; i++)
5403 set_check_for_tx_hang(adapter->tx_ring[i]);
5404 }
5405
5406 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5407 /*
5408 * for legacy and MSI interrupts don't set any bits
5409 * that are enabled for EIAM, because this operation
5410 * would set *both* EIMS and EICS for any bit in EIAM
5411 */
5412 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5413 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5414 } else {
5415 /* get one bit for every active tx/rx interrupt vector */
5416 for (i = 0; i < adapter->num_q_vectors; i++) {
5417 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5418 if (qv->rx.ring || qv->tx.ring)
5419 eics |= ((u64)1 << i);
5420 }
5421 }
5422
5423 /* Cause software interrupt to ensure rings are cleaned */
5424 ixgbe_irq_rearm_queues(adapter, eics);
5425
5426 }
5427
5428 /**
5429 * ixgbe_watchdog_update_link - update the link status
5430 * @adapter: pointer to the device adapter structure
5431 * @link_speed: pointer to a u32 to store the link_speed
5432 **/
5433 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5434 {
5435 struct ixgbe_hw *hw = &adapter->hw;
5436 u32 link_speed = adapter->link_speed;
5437 bool link_up = adapter->link_up;
5438 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5439
5440 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5441 return;
5442
5443 if (hw->mac.ops.check_link) {
5444 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5445 } else {
5446 /* always assume link is up, if no check link function */
5447 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5448 link_up = true;
5449 }
5450
5451 if (adapter->ixgbe_ieee_pfc)
5452 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5453
5454 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5455 hw->mac.ops.fc_enable(hw);
5456 ixgbe_set_rx_drop_en(adapter);
5457 }
5458
5459 if (link_up ||
5460 time_after(jiffies, (adapter->link_check_timeout +
5461 IXGBE_TRY_LINK_TIMEOUT))) {
5462 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5463 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5464 IXGBE_WRITE_FLUSH(hw);
5465 }
5466
5467 adapter->link_up = link_up;
5468 adapter->link_speed = link_speed;
5469 }
5470
5471 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5472 {
5473 #ifdef CONFIG_IXGBE_DCB
5474 struct net_device *netdev = adapter->netdev;
5475 struct dcb_app app = {
5476 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5477 .protocol = 0,
5478 };
5479 u8 up = 0;
5480
5481 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5482 up = dcb_ieee_getapp_mask(netdev, &app);
5483
5484 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5485 #endif
5486 }
5487
5488 /**
5489 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5490 * print link up message
5491 * @adapter: pointer to the device adapter structure
5492 **/
5493 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5494 {
5495 struct net_device *netdev = adapter->netdev;
5496 struct ixgbe_hw *hw = &adapter->hw;
5497 u32 link_speed = adapter->link_speed;
5498 bool flow_rx, flow_tx;
5499
5500 /* only continue if link was previously down */
5501 if (netif_carrier_ok(netdev))
5502 return;
5503
5504 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5505
5506 switch (hw->mac.type) {
5507 case ixgbe_mac_82598EB: {
5508 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5509 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5510 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5511 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5512 }
5513 break;
5514 case ixgbe_mac_X540:
5515 case ixgbe_mac_82599EB: {
5516 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5517 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5518 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5519 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5520 }
5521 break;
5522 default:
5523 flow_tx = false;
5524 flow_rx = false;
5525 break;
5526 }
5527
5528 #ifdef CONFIG_IXGBE_PTP
5529 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5530 ixgbe_ptp_start_cyclecounter(adapter);
5531 #endif
5532
5533 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5534 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5535 "10 Gbps" :
5536 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5537 "1 Gbps" :
5538 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5539 "100 Mbps" :
5540 "unknown speed"))),
5541 ((flow_rx && flow_tx) ? "RX/TX" :
5542 (flow_rx ? "RX" :
5543 (flow_tx ? "TX" : "None"))));
5544
5545 netif_carrier_on(netdev);
5546 ixgbe_check_vf_rate_limit(adapter);
5547
5548 /* update the default user priority for VFs */
5549 ixgbe_update_default_up(adapter);
5550
5551 /* ping all the active vfs to let them know link has changed */
5552 ixgbe_ping_all_vfs(adapter);
5553 }
5554
5555 /**
5556 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5557 * print link down message
5558 * @adapter: pointer to the adapter structure
5559 **/
5560 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5561 {
5562 struct net_device *netdev = adapter->netdev;
5563 struct ixgbe_hw *hw = &adapter->hw;
5564
5565 adapter->link_up = false;
5566 adapter->link_speed = 0;
5567
5568 /* only continue if link was up previously */
5569 if (!netif_carrier_ok(netdev))
5570 return;
5571
5572 /* poll for SFP+ cable when link is down */
5573 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5574 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5575
5576 #ifdef CONFIG_IXGBE_PTP
5577 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5578 ixgbe_ptp_start_cyclecounter(adapter);
5579 #endif
5580
5581 e_info(drv, "NIC Link is Down\n");
5582 netif_carrier_off(netdev);
5583
5584 /* ping all the active vfs to let them know link has changed */
5585 ixgbe_ping_all_vfs(adapter);
5586 }
5587
5588 /**
5589 * ixgbe_watchdog_flush_tx - flush queues on link down
5590 * @adapter: pointer to the device adapter structure
5591 **/
5592 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5593 {
5594 int i;
5595 int some_tx_pending = 0;
5596
5597 if (!netif_carrier_ok(adapter->netdev)) {
5598 for (i = 0; i < adapter->num_tx_queues; i++) {
5599 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5600 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5601 some_tx_pending = 1;
5602 break;
5603 }
5604 }
5605
5606 if (some_tx_pending) {
5607 /* We've lost link, so the controller stops DMA,
5608 * but we've got queued Tx work that's never going
5609 * to get done, so reset controller to flush Tx.
5610 * (Do the reset outside of interrupt context).
5611 */
5612 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5613 }
5614 }
5615 }
5616
5617 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5618 {
5619 u32 ssvpc;
5620
5621 /* Do not perform spoof check for 82598 or if not in IOV mode */
5622 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5623 adapter->num_vfs == 0)
5624 return;
5625
5626 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5627
5628 /*
5629 * ssvpc register is cleared on read, if zero then no
5630 * spoofed packets in the last interval.
5631 */
5632 if (!ssvpc)
5633 return;
5634
5635 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5636 }
5637
5638 /**
5639 * ixgbe_watchdog_subtask - check and bring link up
5640 * @adapter: pointer to the device adapter structure
5641 **/
5642 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5643 {
5644 /* if interface is down do nothing */
5645 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5646 test_bit(__IXGBE_RESETTING, &adapter->state))
5647 return;
5648
5649 ixgbe_watchdog_update_link(adapter);
5650
5651 if (adapter->link_up)
5652 ixgbe_watchdog_link_is_up(adapter);
5653 else
5654 ixgbe_watchdog_link_is_down(adapter);
5655
5656 ixgbe_spoof_check(adapter);
5657 ixgbe_update_stats(adapter);
5658
5659 ixgbe_watchdog_flush_tx(adapter);
5660 }
5661
5662 /**
5663 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5664 * @adapter: the ixgbe adapter structure
5665 **/
5666 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5667 {
5668 struct ixgbe_hw *hw = &adapter->hw;
5669 s32 err;
5670
5671 /* not searching for SFP so there is nothing to do here */
5672 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5673 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5674 return;
5675
5676 /* someone else is in init, wait until next service event */
5677 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5678 return;
5679
5680 err = hw->phy.ops.identify_sfp(hw);
5681 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5682 goto sfp_out;
5683
5684 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5685 /* If no cable is present, then we need to reset
5686 * the next time we find a good cable. */
5687 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5688 }
5689
5690 /* exit on error */
5691 if (err)
5692 goto sfp_out;
5693
5694 /* exit if reset not needed */
5695 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5696 goto sfp_out;
5697
5698 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5699
5700 /*
5701 * A module may be identified correctly, but the EEPROM may not have
5702 * support for that module. setup_sfp() will fail in that case, so
5703 * we should not allow that module to load.
5704 */
5705 if (hw->mac.type == ixgbe_mac_82598EB)
5706 err = hw->phy.ops.reset(hw);
5707 else
5708 err = hw->mac.ops.setup_sfp(hw);
5709
5710 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5711 goto sfp_out;
5712
5713 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5714 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5715
5716 sfp_out:
5717 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5718
5719 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5720 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5721 e_dev_err("failed to initialize because an unsupported "
5722 "SFP+ module type was detected.\n");
5723 e_dev_err("Reload the driver after installing a "
5724 "supported module.\n");
5725 unregister_netdev(adapter->netdev);
5726 }
5727 }
5728
5729 /**
5730 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5731 * @adapter: the ixgbe adapter structure
5732 **/
5733 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5734 {
5735 struct ixgbe_hw *hw = &adapter->hw;
5736 u32 autoneg;
5737 bool negotiation;
5738
5739 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5740 return;
5741
5742 /* someone else is in init, wait until next service event */
5743 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5744 return;
5745
5746 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5747
5748 autoneg = hw->phy.autoneg_advertised;
5749 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5750 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5751 if (hw->mac.ops.setup_link)
5752 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5753
5754 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5755 adapter->link_check_timeout = jiffies;
5756 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5757 }
5758
5759 #ifdef CONFIG_PCI_IOV
5760 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5761 {
5762 int vf;
5763 struct ixgbe_hw *hw = &adapter->hw;
5764 struct net_device *netdev = adapter->netdev;
5765 u32 gpc;
5766 u32 ciaa, ciad;
5767
5768 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5769 if (gpc) /* If incrementing then no need for the check below */
5770 return;
5771 /*
5772 * Check to see if a bad DMA write target from an errant or
5773 * malicious VF has caused a PCIe error. If so then we can
5774 * issue a VFLR to the offending VF(s) and then resume without
5775 * requesting a full slot reset.
5776 */
5777
5778 for (vf = 0; vf < adapter->num_vfs; vf++) {
5779 ciaa = (vf << 16) | 0x80000000;
5780 /* 32 bit read so align, we really want status at offset 6 */
5781 ciaa |= PCI_COMMAND;
5782 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5783 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5784 ciaa &= 0x7FFFFFFF;
5785 /* disable debug mode asap after reading data */
5786 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5787 /* Get the upper 16 bits which will be the PCI status reg */
5788 ciad >>= 16;
5789 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5790 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5791 /* Issue VFLR */
5792 ciaa = (vf << 16) | 0x80000000;
5793 ciaa |= 0xA8;
5794 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5795 ciad = 0x00008000; /* VFLR */
5796 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5797 ciaa &= 0x7FFFFFFF;
5798 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5799 }
5800 }
5801 }
5802
5803 #endif
5804 /**
5805 * ixgbe_service_timer - Timer Call-back
5806 * @data: pointer to adapter cast into an unsigned long
5807 **/
5808 static void ixgbe_service_timer(unsigned long data)
5809 {
5810 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5811 unsigned long next_event_offset;
5812 bool ready = true;
5813
5814 /* poll faster when waiting for link */
5815 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5816 next_event_offset = HZ / 10;
5817 else
5818 next_event_offset = HZ * 2;
5819
5820 #ifdef CONFIG_PCI_IOV
5821 /*
5822 * don't bother with SR-IOV VF DMA hang check if there are
5823 * no VFs or the link is down
5824 */
5825 if (!adapter->num_vfs ||
5826 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5827 goto normal_timer_service;
5828
5829 /* If we have VFs allocated then we must check for DMA hangs */
5830 ixgbe_check_for_bad_vf(adapter);
5831 next_event_offset = HZ / 50;
5832 adapter->timer_event_accumulator++;
5833
5834 if (adapter->timer_event_accumulator >= 100)
5835 adapter->timer_event_accumulator = 0;
5836 else
5837 ready = false;
5838
5839 normal_timer_service:
5840 #endif
5841 /* Reset the timer */
5842 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5843
5844 if (ready)
5845 ixgbe_service_event_schedule(adapter);
5846 }
5847
5848 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5849 {
5850 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5851 return;
5852
5853 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5854
5855 /* If we're already down or resetting, just bail */
5856 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5857 test_bit(__IXGBE_RESETTING, &adapter->state))
5858 return;
5859
5860 ixgbe_dump(adapter);
5861 netdev_err(adapter->netdev, "Reset adapter\n");
5862 adapter->tx_timeout_count++;
5863
5864 ixgbe_reinit_locked(adapter);
5865 }
5866
5867 /**
5868 * ixgbe_service_task - manages and runs subtasks
5869 * @work: pointer to work_struct containing our data
5870 **/
5871 static void ixgbe_service_task(struct work_struct *work)
5872 {
5873 struct ixgbe_adapter *adapter = container_of(work,
5874 struct ixgbe_adapter,
5875 service_task);
5876
5877 ixgbe_reset_subtask(adapter);
5878 ixgbe_sfp_detection_subtask(adapter);
5879 ixgbe_sfp_link_config_subtask(adapter);
5880 ixgbe_check_overtemp_subtask(adapter);
5881 ixgbe_watchdog_subtask(adapter);
5882 ixgbe_fdir_reinit_subtask(adapter);
5883 ixgbe_check_hang_subtask(adapter);
5884 #ifdef CONFIG_IXGBE_PTP
5885 ixgbe_ptp_overflow_check(adapter);
5886 #endif
5887
5888 ixgbe_service_event_complete(adapter);
5889 }
5890
5891 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5892 struct ixgbe_tx_buffer *first,
5893 u8 *hdr_len)
5894 {
5895 struct sk_buff *skb = first->skb;
5896 u32 vlan_macip_lens, type_tucmd;
5897 u32 mss_l4len_idx, l4len;
5898
5899 if (!skb_is_gso(skb))
5900 return 0;
5901
5902 if (skb_header_cloned(skb)) {
5903 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5904 if (err)
5905 return err;
5906 }
5907
5908 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5909 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5910
5911 if (first->protocol == __constant_htons(ETH_P_IP)) {
5912 struct iphdr *iph = ip_hdr(skb);
5913 iph->tot_len = 0;
5914 iph->check = 0;
5915 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5916 iph->daddr, 0,
5917 IPPROTO_TCP,
5918 0);
5919 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5920 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5921 IXGBE_TX_FLAGS_CSUM |
5922 IXGBE_TX_FLAGS_IPV4;
5923 } else if (skb_is_gso_v6(skb)) {
5924 ipv6_hdr(skb)->payload_len = 0;
5925 tcp_hdr(skb)->check =
5926 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5927 &ipv6_hdr(skb)->daddr,
5928 0, IPPROTO_TCP, 0);
5929 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5930 IXGBE_TX_FLAGS_CSUM;
5931 }
5932
5933 /* compute header lengths */
5934 l4len = tcp_hdrlen(skb);
5935 *hdr_len = skb_transport_offset(skb) + l4len;
5936
5937 /* update gso size and bytecount with header size */
5938 first->gso_segs = skb_shinfo(skb)->gso_segs;
5939 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5940
5941 /* mss_l4len_id: use 1 as index for TSO */
5942 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5943 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5944 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5945
5946 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5947 vlan_macip_lens = skb_network_header_len(skb);
5948 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5949 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5950
5951 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5952 mss_l4len_idx);
5953
5954 return 1;
5955 }
5956
5957 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5958 struct ixgbe_tx_buffer *first)
5959 {
5960 struct sk_buff *skb = first->skb;
5961 u32 vlan_macip_lens = 0;
5962 u32 mss_l4len_idx = 0;
5963 u32 type_tucmd = 0;
5964
5965 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5966 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5967 if (unlikely(skb->no_fcs))
5968 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5969 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5970 return;
5971 }
5972 } else {
5973 u8 l4_hdr = 0;
5974 switch (first->protocol) {
5975 case __constant_htons(ETH_P_IP):
5976 vlan_macip_lens |= skb_network_header_len(skb);
5977 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5978 l4_hdr = ip_hdr(skb)->protocol;
5979 break;
5980 case __constant_htons(ETH_P_IPV6):
5981 vlan_macip_lens |= skb_network_header_len(skb);
5982 l4_hdr = ipv6_hdr(skb)->nexthdr;
5983 break;
5984 default:
5985 if (unlikely(net_ratelimit())) {
5986 dev_warn(tx_ring->dev,
5987 "partial checksum but proto=%x!\n",
5988 first->protocol);
5989 }
5990 break;
5991 }
5992
5993 switch (l4_hdr) {
5994 case IPPROTO_TCP:
5995 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5996 mss_l4len_idx = tcp_hdrlen(skb) <<
5997 IXGBE_ADVTXD_L4LEN_SHIFT;
5998 break;
5999 case IPPROTO_SCTP:
6000 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6001 mss_l4len_idx = sizeof(struct sctphdr) <<
6002 IXGBE_ADVTXD_L4LEN_SHIFT;
6003 break;
6004 case IPPROTO_UDP:
6005 mss_l4len_idx = sizeof(struct udphdr) <<
6006 IXGBE_ADVTXD_L4LEN_SHIFT;
6007 break;
6008 default:
6009 if (unlikely(net_ratelimit())) {
6010 dev_warn(tx_ring->dev,
6011 "partial checksum but l4 proto=%x!\n",
6012 l4_hdr);
6013 }
6014 break;
6015 }
6016
6017 /* update TX checksum flag */
6018 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6019 }
6020
6021 /* vlan_macip_lens: MACLEN, VLAN tag */
6022 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6023 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6024
6025 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6026 type_tucmd, mss_l4len_idx);
6027 }
6028
6029 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6030 {
6031 /* set type for advanced descriptor with frame checksum insertion */
6032 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6033 IXGBE_ADVTXD_DCMD_DEXT);
6034
6035 /* set HW vlan bit if vlan is present */
6036 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6037 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6038
6039 #ifdef CONFIG_IXGBE_PTP
6040 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6041 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
6042 #endif
6043
6044 /* set segmentation enable bits for TSO/FSO */
6045 #ifdef IXGBE_FCOE
6046 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
6047 #else
6048 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6049 #endif
6050 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6051
6052 /* insert frame checksum */
6053 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6054 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6055
6056 return cmd_type;
6057 }
6058
6059 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6060 u32 tx_flags, unsigned int paylen)
6061 {
6062 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6063
6064 /* enable L4 checksum for TSO and TX checksum offload */
6065 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6066 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6067
6068 /* enble IPv4 checksum for TSO */
6069 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6070 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6071
6072 /* use index 1 context for TSO/FSO/FCOE */
6073 #ifdef IXGBE_FCOE
6074 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6075 #else
6076 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6077 #endif
6078 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6079
6080 /*
6081 * Check Context must be set if Tx switch is enabled, which it
6082 * always is for case where virtual functions are running
6083 */
6084 #ifdef IXGBE_FCOE
6085 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6086 #else
6087 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6088 #endif
6089 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6090
6091 tx_desc->read.olinfo_status = olinfo_status;
6092 }
6093
6094 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6095 IXGBE_TXD_CMD_RS)
6096
6097 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6098 struct ixgbe_tx_buffer *first,
6099 const u8 hdr_len)
6100 {
6101 dma_addr_t dma;
6102 struct sk_buff *skb = first->skb;
6103 struct ixgbe_tx_buffer *tx_buffer;
6104 union ixgbe_adv_tx_desc *tx_desc;
6105 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6106 unsigned int data_len = skb->data_len;
6107 unsigned int size = skb_headlen(skb);
6108 unsigned int paylen = skb->len - hdr_len;
6109 u32 tx_flags = first->tx_flags;
6110 __le32 cmd_type;
6111 u16 i = tx_ring->next_to_use;
6112
6113 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6114
6115 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6116 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6117
6118 #ifdef IXGBE_FCOE
6119 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6120 if (data_len < sizeof(struct fcoe_crc_eof)) {
6121 size -= sizeof(struct fcoe_crc_eof) - data_len;
6122 data_len = 0;
6123 } else {
6124 data_len -= sizeof(struct fcoe_crc_eof);
6125 }
6126 }
6127
6128 #endif
6129 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6130 if (dma_mapping_error(tx_ring->dev, dma))
6131 goto dma_error;
6132
6133 /* record length, and DMA address */
6134 dma_unmap_len_set(first, len, size);
6135 dma_unmap_addr_set(first, dma, dma);
6136
6137 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6138
6139 for (;;) {
6140 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6141 tx_desc->read.cmd_type_len =
6142 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6143
6144 i++;
6145 tx_desc++;
6146 if (i == tx_ring->count) {
6147 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6148 i = 0;
6149 }
6150
6151 dma += IXGBE_MAX_DATA_PER_TXD;
6152 size -= IXGBE_MAX_DATA_PER_TXD;
6153
6154 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6155 tx_desc->read.olinfo_status = 0;
6156 }
6157
6158 if (likely(!data_len))
6159 break;
6160
6161 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6162
6163 i++;
6164 tx_desc++;
6165 if (i == tx_ring->count) {
6166 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6167 i = 0;
6168 }
6169
6170 #ifdef IXGBE_FCOE
6171 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6172 #else
6173 size = skb_frag_size(frag);
6174 #endif
6175 data_len -= size;
6176
6177 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6178 DMA_TO_DEVICE);
6179 if (dma_mapping_error(tx_ring->dev, dma))
6180 goto dma_error;
6181
6182 tx_buffer = &tx_ring->tx_buffer_info[i];
6183 dma_unmap_len_set(tx_buffer, len, size);
6184 dma_unmap_addr_set(tx_buffer, dma, dma);
6185
6186 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6187 tx_desc->read.olinfo_status = 0;
6188
6189 frag++;
6190 }
6191
6192 /* write last descriptor with RS and EOP bits */
6193 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6194 tx_desc->read.cmd_type_len = cmd_type;
6195
6196 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6197
6198 /* set the timestamp */
6199 first->time_stamp = jiffies;
6200
6201 /*
6202 * Force memory writes to complete before letting h/w know there
6203 * are new descriptors to fetch. (Only applicable for weak-ordered
6204 * memory model archs, such as IA-64).
6205 *
6206 * We also need this memory barrier to make certain all of the
6207 * status bits have been updated before next_to_watch is written.
6208 */
6209 wmb();
6210
6211 /* set next_to_watch value indicating a packet is present */
6212 first->next_to_watch = tx_desc;
6213
6214 i++;
6215 if (i == tx_ring->count)
6216 i = 0;
6217
6218 tx_ring->next_to_use = i;
6219
6220 /* notify HW of packet */
6221 writel(i, tx_ring->tail);
6222
6223 return;
6224 dma_error:
6225 dev_err(tx_ring->dev, "TX DMA map failed\n");
6226
6227 /* clear dma mappings for failed tx_buffer_info map */
6228 for (;;) {
6229 tx_buffer = &tx_ring->tx_buffer_info[i];
6230 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6231 if (tx_buffer == first)
6232 break;
6233 if (i == 0)
6234 i = tx_ring->count;
6235 i--;
6236 }
6237
6238 tx_ring->next_to_use = i;
6239 }
6240
6241 static void ixgbe_atr(struct ixgbe_ring *ring,
6242 struct ixgbe_tx_buffer *first)
6243 {
6244 struct ixgbe_q_vector *q_vector = ring->q_vector;
6245 union ixgbe_atr_hash_dword input = { .dword = 0 };
6246 union ixgbe_atr_hash_dword common = { .dword = 0 };
6247 union {
6248 unsigned char *network;
6249 struct iphdr *ipv4;
6250 struct ipv6hdr *ipv6;
6251 } hdr;
6252 struct tcphdr *th;
6253 __be16 vlan_id;
6254
6255 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6256 if (!q_vector)
6257 return;
6258
6259 /* do nothing if sampling is disabled */
6260 if (!ring->atr_sample_rate)
6261 return;
6262
6263 ring->atr_count++;
6264
6265 /* snag network header to get L4 type and address */
6266 hdr.network = skb_network_header(first->skb);
6267
6268 /* Currently only IPv4/IPv6 with TCP is supported */
6269 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6270 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6271 (first->protocol != __constant_htons(ETH_P_IP) ||
6272 hdr.ipv4->protocol != IPPROTO_TCP))
6273 return;
6274
6275 th = tcp_hdr(first->skb);
6276
6277 /* skip this packet since it is invalid or the socket is closing */
6278 if (!th || th->fin)
6279 return;
6280
6281 /* sample on all syn packets or once every atr sample count */
6282 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6283 return;
6284
6285 /* reset sample count */
6286 ring->atr_count = 0;
6287
6288 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6289
6290 /*
6291 * src and dst are inverted, think how the receiver sees them
6292 *
6293 * The input is broken into two sections, a non-compressed section
6294 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6295 * is XORed together and stored in the compressed dword.
6296 */
6297 input.formatted.vlan_id = vlan_id;
6298
6299 /*
6300 * since src port and flex bytes occupy the same word XOR them together
6301 * and write the value to source port portion of compressed dword
6302 */
6303 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6304 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6305 else
6306 common.port.src ^= th->dest ^ first->protocol;
6307 common.port.dst ^= th->source;
6308
6309 if (first->protocol == __constant_htons(ETH_P_IP)) {
6310 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6311 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6312 } else {
6313 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6314 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6315 hdr.ipv6->saddr.s6_addr32[1] ^
6316 hdr.ipv6->saddr.s6_addr32[2] ^
6317 hdr.ipv6->saddr.s6_addr32[3] ^
6318 hdr.ipv6->daddr.s6_addr32[0] ^
6319 hdr.ipv6->daddr.s6_addr32[1] ^
6320 hdr.ipv6->daddr.s6_addr32[2] ^
6321 hdr.ipv6->daddr.s6_addr32[3];
6322 }
6323
6324 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6325 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6326 input, common, ring->queue_index);
6327 }
6328
6329 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6330 {
6331 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6332 /* Herbert's original patch had:
6333 * smp_mb__after_netif_stop_queue();
6334 * but since that doesn't exist yet, just open code it. */
6335 smp_mb();
6336
6337 /* We need to check again in a case another CPU has just
6338 * made room available. */
6339 if (likely(ixgbe_desc_unused(tx_ring) < size))
6340 return -EBUSY;
6341
6342 /* A reprieve! - use start_queue because it doesn't call schedule */
6343 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6344 ++tx_ring->tx_stats.restart_queue;
6345 return 0;
6346 }
6347
6348 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6349 {
6350 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6351 return 0;
6352 return __ixgbe_maybe_stop_tx(tx_ring, size);
6353 }
6354
6355 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6356 {
6357 struct ixgbe_adapter *adapter = netdev_priv(dev);
6358 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6359 smp_processor_id();
6360 #ifdef IXGBE_FCOE
6361 __be16 protocol = vlan_get_protocol(skb);
6362
6363 if (((protocol == htons(ETH_P_FCOE)) ||
6364 (protocol == htons(ETH_P_FIP))) &&
6365 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6366 struct ixgbe_ring_feature *f;
6367
6368 f = &adapter->ring_feature[RING_F_FCOE];
6369
6370 while (txq >= f->indices)
6371 txq -= f->indices;
6372 txq += adapter->ring_feature[RING_F_FCOE].offset;
6373
6374 return txq;
6375 }
6376 #endif
6377
6378 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6379 while (unlikely(txq >= dev->real_num_tx_queues))
6380 txq -= dev->real_num_tx_queues;
6381 return txq;
6382 }
6383
6384 return skb_tx_hash(dev, skb);
6385 }
6386
6387 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6388 struct ixgbe_adapter *adapter,
6389 struct ixgbe_ring *tx_ring)
6390 {
6391 struct ixgbe_tx_buffer *first;
6392 int tso;
6393 u32 tx_flags = 0;
6394 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6395 unsigned short f;
6396 #endif
6397 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6398 __be16 protocol = skb->protocol;
6399 u8 hdr_len = 0;
6400
6401 /*
6402 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6403 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6404 * + 2 desc gap to keep tail from touching head,
6405 * + 1 desc for context descriptor,
6406 * otherwise try next time
6407 */
6408 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6409 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6410 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6411 #else
6412 count += skb_shinfo(skb)->nr_frags;
6413 #endif
6414 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6415 tx_ring->tx_stats.tx_busy++;
6416 return NETDEV_TX_BUSY;
6417 }
6418
6419 /* record the location of the first descriptor for this packet */
6420 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6421 first->skb = skb;
6422 first->bytecount = skb->len;
6423 first->gso_segs = 1;
6424
6425 /* if we have a HW VLAN tag being added default to the HW one */
6426 if (vlan_tx_tag_present(skb)) {
6427 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6428 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6429 /* else if it is a SW VLAN check the next protocol and store the tag */
6430 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6431 struct vlan_hdr *vhdr, _vhdr;
6432 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6433 if (!vhdr)
6434 goto out_drop;
6435
6436 protocol = vhdr->h_vlan_encapsulated_proto;
6437 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6438 IXGBE_TX_FLAGS_VLAN_SHIFT;
6439 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6440 }
6441
6442 skb_tx_timestamp(skb);
6443
6444 #ifdef CONFIG_IXGBE_PTP
6445 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6446 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6447 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6448 }
6449 #endif
6450
6451 #ifdef CONFIG_PCI_IOV
6452 /*
6453 * Use the l2switch_enable flag - would be false if the DMA
6454 * Tx switch had been disabled.
6455 */
6456 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6457 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6458
6459 #endif
6460 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6461 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6462 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6463 (skb->priority != TC_PRIO_CONTROL))) {
6464 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6465 tx_flags |= (skb->priority & 0x7) <<
6466 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6467 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6468 struct vlan_ethhdr *vhdr;
6469 if (skb_header_cloned(skb) &&
6470 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6471 goto out_drop;
6472 vhdr = (struct vlan_ethhdr *)skb->data;
6473 vhdr->h_vlan_TCI = htons(tx_flags >>
6474 IXGBE_TX_FLAGS_VLAN_SHIFT);
6475 } else {
6476 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6477 }
6478 }
6479
6480 /* record initial flags and protocol */
6481 first->tx_flags = tx_flags;
6482 first->protocol = protocol;
6483
6484 #ifdef IXGBE_FCOE
6485 /* setup tx offload for FCoE */
6486 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6487 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6488 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6489 if (tso < 0)
6490 goto out_drop;
6491
6492 goto xmit_fcoe;
6493 }
6494
6495 #endif /* IXGBE_FCOE */
6496 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6497 if (tso < 0)
6498 goto out_drop;
6499 else if (!tso)
6500 ixgbe_tx_csum(tx_ring, first);
6501
6502 /* add the ATR filter if ATR is on */
6503 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6504 ixgbe_atr(tx_ring, first);
6505
6506 #ifdef IXGBE_FCOE
6507 xmit_fcoe:
6508 #endif /* IXGBE_FCOE */
6509 ixgbe_tx_map(tx_ring, first, hdr_len);
6510
6511 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6512
6513 return NETDEV_TX_OK;
6514
6515 out_drop:
6516 dev_kfree_skb_any(first->skb);
6517 first->skb = NULL;
6518
6519 return NETDEV_TX_OK;
6520 }
6521
6522 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6523 struct net_device *netdev)
6524 {
6525 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6526 struct ixgbe_ring *tx_ring;
6527
6528 /*
6529 * The minimum packet size for olinfo paylen is 17 so pad the skb
6530 * in order to meet this minimum size requirement.
6531 */
6532 if (unlikely(skb->len < 17)) {
6533 if (skb_pad(skb, 17 - skb->len))
6534 return NETDEV_TX_OK;
6535 skb->len = 17;
6536 skb_set_tail_pointer(skb, 17);
6537 }
6538
6539 tx_ring = adapter->tx_ring[skb->queue_mapping];
6540 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6541 }
6542
6543 /**
6544 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6545 * @netdev: network interface device structure
6546 * @p: pointer to an address structure
6547 *
6548 * Returns 0 on success, negative on failure
6549 **/
6550 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6551 {
6552 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6553 struct ixgbe_hw *hw = &adapter->hw;
6554 struct sockaddr *addr = p;
6555
6556 if (!is_valid_ether_addr(addr->sa_data))
6557 return -EADDRNOTAVAIL;
6558
6559 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6560 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6561
6562 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6563
6564 return 0;
6565 }
6566
6567 static int
6568 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6569 {
6570 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6571 struct ixgbe_hw *hw = &adapter->hw;
6572 u16 value;
6573 int rc;
6574
6575 if (prtad != hw->phy.mdio.prtad)
6576 return -EINVAL;
6577 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6578 if (!rc)
6579 rc = value;
6580 return rc;
6581 }
6582
6583 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6584 u16 addr, u16 value)
6585 {
6586 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6587 struct ixgbe_hw *hw = &adapter->hw;
6588
6589 if (prtad != hw->phy.mdio.prtad)
6590 return -EINVAL;
6591 return hw->phy.ops.write_reg(hw, addr, devad, value);
6592 }
6593
6594 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6595 {
6596 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6597
6598 switch (cmd) {
6599 #ifdef CONFIG_IXGBE_PTP
6600 case SIOCSHWTSTAMP:
6601 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6602 #endif
6603 default:
6604 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6605 }
6606 }
6607
6608 /**
6609 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6610 * netdev->dev_addrs
6611 * @netdev: network interface device structure
6612 *
6613 * Returns non-zero on failure
6614 **/
6615 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6616 {
6617 int err = 0;
6618 struct ixgbe_adapter *adapter = netdev_priv(dev);
6619 struct ixgbe_hw *hw = &adapter->hw;
6620
6621 if (is_valid_ether_addr(hw->mac.san_addr)) {
6622 rtnl_lock();
6623 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6624 rtnl_unlock();
6625
6626 /* update SAN MAC vmdq pool selection */
6627 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6628 }
6629 return err;
6630 }
6631
6632 /**
6633 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6634 * netdev->dev_addrs
6635 * @netdev: network interface device structure
6636 *
6637 * Returns non-zero on failure
6638 **/
6639 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6640 {
6641 int err = 0;
6642 struct ixgbe_adapter *adapter = netdev_priv(dev);
6643 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6644
6645 if (is_valid_ether_addr(mac->san_addr)) {
6646 rtnl_lock();
6647 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6648 rtnl_unlock();
6649 }
6650 return err;
6651 }
6652
6653 #ifdef CONFIG_NET_POLL_CONTROLLER
6654 /*
6655 * Polling 'interrupt' - used by things like netconsole to send skbs
6656 * without having to re-enable interrupts. It's not called while
6657 * the interrupt routine is executing.
6658 */
6659 static void ixgbe_netpoll(struct net_device *netdev)
6660 {
6661 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6662 int i;
6663
6664 /* if interface is down do nothing */
6665 if (test_bit(__IXGBE_DOWN, &adapter->state))
6666 return;
6667
6668 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6670 for (i = 0; i < adapter->num_q_vectors; i++)
6671 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6672 } else {
6673 ixgbe_intr(adapter->pdev->irq, netdev);
6674 }
6675 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6676 }
6677
6678 #endif
6679 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6680 struct rtnl_link_stats64 *stats)
6681 {
6682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6683 int i;
6684
6685 rcu_read_lock();
6686 for (i = 0; i < adapter->num_rx_queues; i++) {
6687 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6688 u64 bytes, packets;
6689 unsigned int start;
6690
6691 if (ring) {
6692 do {
6693 start = u64_stats_fetch_begin_bh(&ring->syncp);
6694 packets = ring->stats.packets;
6695 bytes = ring->stats.bytes;
6696 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6697 stats->rx_packets += packets;
6698 stats->rx_bytes += bytes;
6699 }
6700 }
6701
6702 for (i = 0; i < adapter->num_tx_queues; i++) {
6703 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6704 u64 bytes, packets;
6705 unsigned int start;
6706
6707 if (ring) {
6708 do {
6709 start = u64_stats_fetch_begin_bh(&ring->syncp);
6710 packets = ring->stats.packets;
6711 bytes = ring->stats.bytes;
6712 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6713 stats->tx_packets += packets;
6714 stats->tx_bytes += bytes;
6715 }
6716 }
6717 rcu_read_unlock();
6718 /* following stats updated by ixgbe_watchdog_task() */
6719 stats->multicast = netdev->stats.multicast;
6720 stats->rx_errors = netdev->stats.rx_errors;
6721 stats->rx_length_errors = netdev->stats.rx_length_errors;
6722 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6723 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6724 return stats;
6725 }
6726
6727 #ifdef CONFIG_IXGBE_DCB
6728 /**
6729 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6730 * @adapter: pointer to ixgbe_adapter
6731 * @tc: number of traffic classes currently enabled
6732 *
6733 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6734 * 802.1Q priority maps to a packet buffer that exists.
6735 */
6736 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6737 {
6738 struct ixgbe_hw *hw = &adapter->hw;
6739 u32 reg, rsave;
6740 int i;
6741
6742 /* 82598 have a static priority to TC mapping that can not
6743 * be changed so no validation is needed.
6744 */
6745 if (hw->mac.type == ixgbe_mac_82598EB)
6746 return;
6747
6748 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6749 rsave = reg;
6750
6751 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6752 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6753
6754 /* If up2tc is out of bounds default to zero */
6755 if (up2tc > tc)
6756 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6757 }
6758
6759 if (reg != rsave)
6760 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6761
6762 return;
6763 }
6764
6765 /**
6766 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6767 * @adapter: Pointer to adapter struct
6768 *
6769 * Populate the netdev user priority to tc map
6770 */
6771 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6772 {
6773 struct net_device *dev = adapter->netdev;
6774 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6775 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6776 u8 prio;
6777
6778 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6779 u8 tc = 0;
6780
6781 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6782 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6783 else if (ets)
6784 tc = ets->prio_tc[prio];
6785
6786 netdev_set_prio_tc_map(dev, prio, tc);
6787 }
6788 }
6789
6790 /**
6791 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6792 *
6793 * @netdev: net device to configure
6794 * @tc: number of traffic classes to enable
6795 */
6796 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6797 {
6798 struct ixgbe_adapter *adapter = netdev_priv(dev);
6799 struct ixgbe_hw *hw = &adapter->hw;
6800
6801 /* Hardware supports up to 8 traffic classes */
6802 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6803 (hw->mac.type == ixgbe_mac_82598EB &&
6804 tc < MAX_TRAFFIC_CLASS))
6805 return -EINVAL;
6806
6807 /* Hardware has to reinitialize queues and interrupts to
6808 * match packet buffer alignment. Unfortunately, the
6809 * hardware is not flexible enough to do this dynamically.
6810 */
6811 if (netif_running(dev))
6812 ixgbe_close(dev);
6813 ixgbe_clear_interrupt_scheme(adapter);
6814
6815 if (tc) {
6816 netdev_set_num_tc(dev, tc);
6817 ixgbe_set_prio_tc_map(adapter);
6818
6819 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6820
6821 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6822 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6823 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6824 }
6825 } else {
6826 netdev_reset_tc(dev);
6827
6828 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6829 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6830
6831 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6832
6833 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6834 adapter->dcb_cfg.pfc_mode_enable = false;
6835 }
6836
6837 ixgbe_init_interrupt_scheme(adapter);
6838 ixgbe_validate_rtr(adapter, tc);
6839 if (netif_running(dev))
6840 ixgbe_open(dev);
6841
6842 return 0;
6843 }
6844
6845 #endif /* CONFIG_IXGBE_DCB */
6846 void ixgbe_do_reset(struct net_device *netdev)
6847 {
6848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6849
6850 if (netif_running(netdev))
6851 ixgbe_reinit_locked(adapter);
6852 else
6853 ixgbe_reset(adapter);
6854 }
6855
6856 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6857 netdev_features_t features)
6858 {
6859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6860
6861 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6862 if (!(features & NETIF_F_RXCSUM))
6863 features &= ~NETIF_F_LRO;
6864
6865 /* Turn off LRO if not RSC capable */
6866 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6867 features &= ~NETIF_F_LRO;
6868
6869 return features;
6870 }
6871
6872 static int ixgbe_set_features(struct net_device *netdev,
6873 netdev_features_t features)
6874 {
6875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6876 netdev_features_t changed = netdev->features ^ features;
6877 bool need_reset = false;
6878
6879 /* Make sure RSC matches LRO, reset if change */
6880 if (!(features & NETIF_F_LRO)) {
6881 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6882 need_reset = true;
6883 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6884 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6885 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6886 if (adapter->rx_itr_setting == 1 ||
6887 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6888 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6889 need_reset = true;
6890 } else if ((changed ^ features) & NETIF_F_LRO) {
6891 e_info(probe, "rx-usecs set too low, "
6892 "disabling RSC\n");
6893 }
6894 }
6895
6896 /*
6897 * Check if Flow Director n-tuple support was enabled or disabled. If
6898 * the state changed, we need to reset.
6899 */
6900 switch (features & NETIF_F_NTUPLE) {
6901 case NETIF_F_NTUPLE:
6902 /* turn off ATR, enable perfect filters and reset */
6903 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6904 need_reset = true;
6905
6906 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6907 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6908 break;
6909 default:
6910 /* turn off perfect filters, enable ATR and reset */
6911 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6912 need_reset = true;
6913
6914 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6915
6916 /* We cannot enable ATR if SR-IOV is enabled */
6917 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6918 break;
6919
6920 /* We cannot enable ATR if we have 2 or more traffic classes */
6921 if (netdev_get_num_tc(netdev) > 1)
6922 break;
6923
6924 /* We cannot enable ATR if RSS is disabled */
6925 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6926 break;
6927
6928 /* A sample rate of 0 indicates ATR disabled */
6929 if (!adapter->atr_sample_rate)
6930 break;
6931
6932 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6933 break;
6934 }
6935
6936 if (features & NETIF_F_HW_VLAN_RX)
6937 ixgbe_vlan_strip_enable(adapter);
6938 else
6939 ixgbe_vlan_strip_disable(adapter);
6940
6941 if (changed & NETIF_F_RXALL)
6942 need_reset = true;
6943
6944 netdev->features = features;
6945 if (need_reset)
6946 ixgbe_do_reset(netdev);
6947
6948 return 0;
6949 }
6950
6951 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6952 struct net_device *dev,
6953 const unsigned char *addr,
6954 u16 flags)
6955 {
6956 struct ixgbe_adapter *adapter = netdev_priv(dev);
6957 int err;
6958
6959 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6960 return -EOPNOTSUPP;
6961
6962 if (ndm->ndm_state & NUD_PERMANENT) {
6963 pr_info("%s: FDB only supports static addresses\n",
6964 ixgbe_driver_name);
6965 return -EINVAL;
6966 }
6967
6968 if (is_unicast_ether_addr(addr)) {
6969 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6970
6971 if (netdev_uc_count(dev) < rar_uc_entries)
6972 err = dev_uc_add_excl(dev, addr);
6973 else
6974 err = -ENOMEM;
6975 } else if (is_multicast_ether_addr(addr)) {
6976 err = dev_mc_add_excl(dev, addr);
6977 } else {
6978 err = -EINVAL;
6979 }
6980
6981 /* Only return duplicate errors if NLM_F_EXCL is set */
6982 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6983 err = 0;
6984
6985 return err;
6986 }
6987
6988 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6989 struct net_device *dev,
6990 const unsigned char *addr)
6991 {
6992 struct ixgbe_adapter *adapter = netdev_priv(dev);
6993 int err = -EOPNOTSUPP;
6994
6995 if (ndm->ndm_state & NUD_PERMANENT) {
6996 pr_info("%s: FDB only supports static addresses\n",
6997 ixgbe_driver_name);
6998 return -EINVAL;
6999 }
7000
7001 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7002 if (is_unicast_ether_addr(addr))
7003 err = dev_uc_del(dev, addr);
7004 else if (is_multicast_ether_addr(addr))
7005 err = dev_mc_del(dev, addr);
7006 else
7007 err = -EINVAL;
7008 }
7009
7010 return err;
7011 }
7012
7013 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7014 struct netlink_callback *cb,
7015 struct net_device *dev,
7016 int idx)
7017 {
7018 struct ixgbe_adapter *adapter = netdev_priv(dev);
7019
7020 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7021 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7022
7023 return idx;
7024 }
7025
7026 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7027 struct nlmsghdr *nlh)
7028 {
7029 struct ixgbe_adapter *adapter = netdev_priv(dev);
7030 struct nlattr *attr, *br_spec;
7031 int rem;
7032
7033 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7034 return -EOPNOTSUPP;
7035
7036 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7037
7038 nla_for_each_nested(attr, br_spec, rem) {
7039 __u16 mode;
7040 u32 reg = 0;
7041
7042 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7043 continue;
7044
7045 mode = nla_get_u16(attr);
7046 if (mode == BRIDGE_MODE_VEPA)
7047 reg = 0;
7048 else if (mode == BRIDGE_MODE_VEB)
7049 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7050 else
7051 return -EINVAL;
7052
7053 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7054
7055 e_info(drv, "enabling bridge mode: %s\n",
7056 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7057 }
7058
7059 return 0;
7060 }
7061
7062 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7063 struct net_device *dev)
7064 {
7065 struct ixgbe_adapter *adapter = netdev_priv(dev);
7066 u16 mode;
7067
7068 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7069 return 0;
7070
7071 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7072 mode = BRIDGE_MODE_VEB;
7073 else
7074 mode = BRIDGE_MODE_VEPA;
7075
7076 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7077 }
7078
7079 static const struct net_device_ops ixgbe_netdev_ops = {
7080 .ndo_open = ixgbe_open,
7081 .ndo_stop = ixgbe_close,
7082 .ndo_start_xmit = ixgbe_xmit_frame,
7083 .ndo_select_queue = ixgbe_select_queue,
7084 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7085 .ndo_validate_addr = eth_validate_addr,
7086 .ndo_set_mac_address = ixgbe_set_mac,
7087 .ndo_change_mtu = ixgbe_change_mtu,
7088 .ndo_tx_timeout = ixgbe_tx_timeout,
7089 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7090 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7091 .ndo_do_ioctl = ixgbe_ioctl,
7092 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7093 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7094 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7095 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7096 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7097 .ndo_get_stats64 = ixgbe_get_stats64,
7098 #ifdef CONFIG_IXGBE_DCB
7099 .ndo_setup_tc = ixgbe_setup_tc,
7100 #endif
7101 #ifdef CONFIG_NET_POLL_CONTROLLER
7102 .ndo_poll_controller = ixgbe_netpoll,
7103 #endif
7104 #ifdef IXGBE_FCOE
7105 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7106 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7107 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7108 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7109 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7110 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7111 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7112 #endif /* IXGBE_FCOE */
7113 .ndo_set_features = ixgbe_set_features,
7114 .ndo_fix_features = ixgbe_fix_features,
7115 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7116 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7117 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7118 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7119 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7120 };
7121
7122 /**
7123 * ixgbe_wol_supported - Check whether device supports WoL
7124 * @hw: hw specific details
7125 * @device_id: the device ID
7126 * @subdev_id: the subsystem device ID
7127 *
7128 * This function is used by probe and ethtool to determine
7129 * which devices have WoL support
7130 *
7131 **/
7132 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7133 u16 subdevice_id)
7134 {
7135 struct ixgbe_hw *hw = &adapter->hw;
7136 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7137 int is_wol_supported = 0;
7138
7139 switch (device_id) {
7140 case IXGBE_DEV_ID_82599_SFP:
7141 /* Only these subdevices could supports WOL */
7142 switch (subdevice_id) {
7143 case IXGBE_SUBDEV_ID_82599_560FLR:
7144 /* only support first port */
7145 if (hw->bus.func != 0)
7146 break;
7147 case IXGBE_SUBDEV_ID_82599_SFP:
7148 case IXGBE_SUBDEV_ID_82599_RNDC:
7149 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7150 is_wol_supported = 1;
7151 break;
7152 }
7153 break;
7154 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7155 /* All except this subdevice support WOL */
7156 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7157 is_wol_supported = 1;
7158 break;
7159 case IXGBE_DEV_ID_82599_KX4:
7160 is_wol_supported = 1;
7161 break;
7162 case IXGBE_DEV_ID_X540T:
7163 case IXGBE_DEV_ID_X540T1:
7164 /* check eeprom to see if enabled wol */
7165 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7166 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7167 (hw->bus.func == 0))) {
7168 is_wol_supported = 1;
7169 }
7170 break;
7171 }
7172
7173 return is_wol_supported;
7174 }
7175
7176 /**
7177 * ixgbe_probe - Device Initialization Routine
7178 * @pdev: PCI device information struct
7179 * @ent: entry in ixgbe_pci_tbl
7180 *
7181 * Returns 0 on success, negative on failure
7182 *
7183 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7184 * The OS initialization, configuring of the adapter private structure,
7185 * and a hardware reset occur.
7186 **/
7187 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7188 const struct pci_device_id *ent)
7189 {
7190 struct net_device *netdev;
7191 struct ixgbe_adapter *adapter = NULL;
7192 struct ixgbe_hw *hw;
7193 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7194 static int cards_found;
7195 int i, err, pci_using_dac;
7196 u8 part_str[IXGBE_PBANUM_LENGTH];
7197 unsigned int indices = num_possible_cpus();
7198 unsigned int dcb_max = 0;
7199 #ifdef IXGBE_FCOE
7200 u16 device_caps;
7201 #endif
7202 u32 eec;
7203
7204 /* Catch broken hardware that put the wrong VF device ID in
7205 * the PCIe SR-IOV capability.
7206 */
7207 if (pdev->is_virtfn) {
7208 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7209 pci_name(pdev), pdev->vendor, pdev->device);
7210 return -EINVAL;
7211 }
7212
7213 err = pci_enable_device_mem(pdev);
7214 if (err)
7215 return err;
7216
7217 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7218 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7219 pci_using_dac = 1;
7220 } else {
7221 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7222 if (err) {
7223 err = dma_set_coherent_mask(&pdev->dev,
7224 DMA_BIT_MASK(32));
7225 if (err) {
7226 dev_err(&pdev->dev,
7227 "No usable DMA configuration, aborting\n");
7228 goto err_dma;
7229 }
7230 }
7231 pci_using_dac = 0;
7232 }
7233
7234 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7235 IORESOURCE_MEM), ixgbe_driver_name);
7236 if (err) {
7237 dev_err(&pdev->dev,
7238 "pci_request_selected_regions failed 0x%x\n", err);
7239 goto err_pci_reg;
7240 }
7241
7242 pci_enable_pcie_error_reporting(pdev);
7243
7244 pci_set_master(pdev);
7245 pci_save_state(pdev);
7246
7247 #ifdef CONFIG_IXGBE_DCB
7248 if (ii->mac == ixgbe_mac_82598EB)
7249 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7250 IXGBE_MAX_RSS_INDICES);
7251 else
7252 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7253 IXGBE_MAX_FDIR_INDICES);
7254 #endif
7255
7256 if (ii->mac == ixgbe_mac_82598EB)
7257 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7258 else
7259 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7260
7261 #ifdef IXGBE_FCOE
7262 indices += min_t(unsigned int, num_possible_cpus(),
7263 IXGBE_MAX_FCOE_INDICES);
7264 #endif
7265 indices = max_t(unsigned int, dcb_max, indices);
7266 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7267 if (!netdev) {
7268 err = -ENOMEM;
7269 goto err_alloc_etherdev;
7270 }
7271
7272 SET_NETDEV_DEV(netdev, &pdev->dev);
7273
7274 adapter = netdev_priv(netdev);
7275 pci_set_drvdata(pdev, adapter);
7276
7277 adapter->netdev = netdev;
7278 adapter->pdev = pdev;
7279 hw = &adapter->hw;
7280 hw->back = adapter;
7281 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7282
7283 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7284 pci_resource_len(pdev, 0));
7285 if (!hw->hw_addr) {
7286 err = -EIO;
7287 goto err_ioremap;
7288 }
7289
7290 netdev->netdev_ops = &ixgbe_netdev_ops;
7291 ixgbe_set_ethtool_ops(netdev);
7292 netdev->watchdog_timeo = 5 * HZ;
7293 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7294
7295 adapter->bd_number = cards_found;
7296
7297 /* Setup hw api */
7298 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7299 hw->mac.type = ii->mac;
7300
7301 /* EEPROM */
7302 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7303 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7304 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7305 if (!(eec & (1 << 8)))
7306 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7307
7308 /* PHY */
7309 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7310 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7311 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7312 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7313 hw->phy.mdio.mmds = 0;
7314 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7315 hw->phy.mdio.dev = netdev;
7316 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7317 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7318
7319 ii->get_invariants(hw);
7320
7321 /* setup the private structure */
7322 err = ixgbe_sw_init(adapter);
7323 if (err)
7324 goto err_sw_init;
7325
7326 /* Make it possible the adapter to be woken up via WOL */
7327 switch (adapter->hw.mac.type) {
7328 case ixgbe_mac_82599EB:
7329 case ixgbe_mac_X540:
7330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7331 break;
7332 default:
7333 break;
7334 }
7335
7336 /*
7337 * If there is a fan on this device and it has failed log the
7338 * failure.
7339 */
7340 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7341 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7342 if (esdp & IXGBE_ESDP_SDP1)
7343 e_crit(probe, "Fan has stopped, replace the adapter\n");
7344 }
7345
7346 if (allow_unsupported_sfp)
7347 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7348
7349 /* reset_hw fills in the perm_addr as well */
7350 hw->phy.reset_if_overtemp = true;
7351 err = hw->mac.ops.reset_hw(hw);
7352 hw->phy.reset_if_overtemp = false;
7353 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7354 hw->mac.type == ixgbe_mac_82598EB) {
7355 err = 0;
7356 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7357 e_dev_err("failed to load because an unsupported SFP+ "
7358 "module type was detected.\n");
7359 e_dev_err("Reload the driver after installing a supported "
7360 "module.\n");
7361 goto err_sw_init;
7362 } else if (err) {
7363 e_dev_err("HW Init failed: %d\n", err);
7364 goto err_sw_init;
7365 }
7366
7367 #ifdef CONFIG_PCI_IOV
7368 ixgbe_enable_sriov(adapter, ii);
7369
7370 #endif
7371 netdev->features = NETIF_F_SG |
7372 NETIF_F_IP_CSUM |
7373 NETIF_F_IPV6_CSUM |
7374 NETIF_F_HW_VLAN_TX |
7375 NETIF_F_HW_VLAN_RX |
7376 NETIF_F_HW_VLAN_FILTER |
7377 NETIF_F_TSO |
7378 NETIF_F_TSO6 |
7379 NETIF_F_RXHASH |
7380 NETIF_F_RXCSUM;
7381
7382 netdev->hw_features = netdev->features;
7383
7384 switch (adapter->hw.mac.type) {
7385 case ixgbe_mac_82599EB:
7386 case ixgbe_mac_X540:
7387 netdev->features |= NETIF_F_SCTP_CSUM;
7388 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7389 NETIF_F_NTUPLE;
7390 break;
7391 default:
7392 break;
7393 }
7394
7395 netdev->hw_features |= NETIF_F_RXALL;
7396
7397 netdev->vlan_features |= NETIF_F_TSO;
7398 netdev->vlan_features |= NETIF_F_TSO6;
7399 netdev->vlan_features |= NETIF_F_IP_CSUM;
7400 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7401 netdev->vlan_features |= NETIF_F_SG;
7402
7403 netdev->priv_flags |= IFF_UNICAST_FLT;
7404 netdev->priv_flags |= IFF_SUPP_NOFCS;
7405
7406 #ifdef CONFIG_IXGBE_DCB
7407 netdev->dcbnl_ops = &dcbnl_ops;
7408 #endif
7409
7410 #ifdef IXGBE_FCOE
7411 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7412 if (hw->mac.ops.get_device_caps) {
7413 hw->mac.ops.get_device_caps(hw, &device_caps);
7414 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7415 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7416 }
7417
7418 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7419
7420 netdev->features |= NETIF_F_FSO |
7421 NETIF_F_FCOE_CRC;
7422
7423 netdev->vlan_features |= NETIF_F_FSO |
7424 NETIF_F_FCOE_CRC |
7425 NETIF_F_FCOE_MTU;
7426 }
7427 #endif /* IXGBE_FCOE */
7428 if (pci_using_dac) {
7429 netdev->features |= NETIF_F_HIGHDMA;
7430 netdev->vlan_features |= NETIF_F_HIGHDMA;
7431 }
7432
7433 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7434 netdev->hw_features |= NETIF_F_LRO;
7435 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7436 netdev->features |= NETIF_F_LRO;
7437
7438 /* make sure the EEPROM is good */
7439 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7440 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7441 err = -EIO;
7442 goto err_sw_init;
7443 }
7444
7445 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7446 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7447
7448 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7449 e_dev_err("invalid MAC address\n");
7450 err = -EIO;
7451 goto err_sw_init;
7452 }
7453
7454 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7455 (unsigned long) adapter);
7456
7457 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7458 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7459
7460 err = ixgbe_init_interrupt_scheme(adapter);
7461 if (err)
7462 goto err_sw_init;
7463
7464 /* WOL not supported for all devices */
7465 adapter->wol = 0;
7466 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7467 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7468 adapter->wol = IXGBE_WUFC_MAG;
7469
7470 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7471
7472 /* save off EEPROM version number */
7473 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7474 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7475
7476 /* pick up the PCI bus settings for reporting later */
7477 hw->mac.ops.get_bus_info(hw);
7478
7479 /* print bus type/speed/width info */
7480 e_dev_info("(PCI Express:%s:%s) %pM\n",
7481 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7482 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7483 "Unknown"),
7484 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7485 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7486 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7487 "Unknown"),
7488 netdev->dev_addr);
7489
7490 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7491 if (err)
7492 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7493 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7494 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7495 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7496 part_str);
7497 else
7498 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7499 hw->mac.type, hw->phy.type, part_str);
7500
7501 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7502 e_dev_warn("PCI-Express bandwidth available for this card is "
7503 "not sufficient for optimal performance.\n");
7504 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7505 "is required.\n");
7506 }
7507
7508 /* reset the hardware with the new settings */
7509 err = hw->mac.ops.start_hw(hw);
7510 if (err == IXGBE_ERR_EEPROM_VERSION) {
7511 /* We are running on a pre-production device, log a warning */
7512 e_dev_warn("This device is a pre-production adapter/LOM. "
7513 "Please be aware there may be issues associated "
7514 "with your hardware. If you are experiencing "
7515 "problems please contact your Intel or hardware "
7516 "representative who provided you with this "
7517 "hardware.\n");
7518 }
7519 strcpy(netdev->name, "eth%d");
7520 err = register_netdev(netdev);
7521 if (err)
7522 goto err_register;
7523
7524 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7525 if (hw->mac.ops.disable_tx_laser &&
7526 ((hw->phy.multispeed_fiber) ||
7527 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7528 (hw->mac.type == ixgbe_mac_82599EB))))
7529 hw->mac.ops.disable_tx_laser(hw);
7530
7531 /* carrier off reporting is important to ethtool even BEFORE open */
7532 netif_carrier_off(netdev);
7533
7534 #ifdef CONFIG_IXGBE_DCA
7535 if (dca_add_requester(&pdev->dev) == 0) {
7536 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7537 ixgbe_setup_dca(adapter);
7538 }
7539 #endif
7540 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7541 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7542 for (i = 0; i < adapter->num_vfs; i++)
7543 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7544 }
7545
7546 /* firmware requires driver version to be 0xFFFFFFFF
7547 * since os does not support feature
7548 */
7549 if (hw->mac.ops.set_fw_drv_ver)
7550 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7551 0xFF);
7552
7553 /* add san mac addr to netdev */
7554 ixgbe_add_sanmac_netdev(netdev);
7555
7556 e_dev_info("%s\n", ixgbe_default_device_descr);
7557 cards_found++;
7558
7559 #ifdef CONFIG_IXGBE_HWMON
7560 if (ixgbe_sysfs_init(adapter))
7561 e_err(probe, "failed to allocate sysfs resources\n");
7562 #endif /* CONFIG_IXGBE_HWMON */
7563
7564 #ifdef CONFIG_DEBUG_FS
7565 ixgbe_dbg_adapter_init(adapter);
7566 #endif /* CONFIG_DEBUG_FS */
7567
7568 return 0;
7569
7570 err_register:
7571 ixgbe_release_hw_control(adapter);
7572 ixgbe_clear_interrupt_scheme(adapter);
7573 err_sw_init:
7574 ixgbe_disable_sriov(adapter);
7575 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7576 iounmap(hw->hw_addr);
7577 err_ioremap:
7578 free_netdev(netdev);
7579 err_alloc_etherdev:
7580 pci_release_selected_regions(pdev,
7581 pci_select_bars(pdev, IORESOURCE_MEM));
7582 err_pci_reg:
7583 err_dma:
7584 pci_disable_device(pdev);
7585 return err;
7586 }
7587
7588 /**
7589 * ixgbe_remove - Device Removal Routine
7590 * @pdev: PCI device information struct
7591 *
7592 * ixgbe_remove is called by the PCI subsystem to alert the driver
7593 * that it should release a PCI device. The could be caused by a
7594 * Hot-Plug event, or because the driver is going to be removed from
7595 * memory.
7596 **/
7597 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7598 {
7599 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7600 struct net_device *netdev = adapter->netdev;
7601
7602 #ifdef CONFIG_DEBUG_FS
7603 ixgbe_dbg_adapter_exit(adapter);
7604 #endif /*CONFIG_DEBUG_FS */
7605
7606 set_bit(__IXGBE_DOWN, &adapter->state);
7607 cancel_work_sync(&adapter->service_task);
7608
7609
7610 #ifdef CONFIG_IXGBE_DCA
7611 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7612 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7613 dca_remove_requester(&pdev->dev);
7614 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7615 }
7616
7617 #endif
7618 #ifdef CONFIG_IXGBE_HWMON
7619 ixgbe_sysfs_exit(adapter);
7620 #endif /* CONFIG_IXGBE_HWMON */
7621
7622 /* remove the added san mac */
7623 ixgbe_del_sanmac_netdev(netdev);
7624
7625 if (netdev->reg_state == NETREG_REGISTERED)
7626 unregister_netdev(netdev);
7627
7628 ixgbe_disable_sriov(adapter);
7629
7630 ixgbe_clear_interrupt_scheme(adapter);
7631
7632 ixgbe_release_hw_control(adapter);
7633
7634 #ifdef CONFIG_DCB
7635 kfree(adapter->ixgbe_ieee_pfc);
7636 kfree(adapter->ixgbe_ieee_ets);
7637
7638 #endif
7639 iounmap(adapter->hw.hw_addr);
7640 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7641 IORESOURCE_MEM));
7642
7643 e_dev_info("complete\n");
7644
7645 free_netdev(netdev);
7646
7647 pci_disable_pcie_error_reporting(pdev);
7648
7649 pci_disable_device(pdev);
7650 }
7651
7652 /**
7653 * ixgbe_io_error_detected - called when PCI error is detected
7654 * @pdev: Pointer to PCI device
7655 * @state: The current pci connection state
7656 *
7657 * This function is called after a PCI bus error affecting
7658 * this device has been detected.
7659 */
7660 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7661 pci_channel_state_t state)
7662 {
7663 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7664 struct net_device *netdev = adapter->netdev;
7665
7666 #ifdef CONFIG_PCI_IOV
7667 struct pci_dev *bdev, *vfdev;
7668 u32 dw0, dw1, dw2, dw3;
7669 int vf, pos;
7670 u16 req_id, pf_func;
7671
7672 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7673 adapter->num_vfs == 0)
7674 goto skip_bad_vf_detection;
7675
7676 bdev = pdev->bus->self;
7677 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7678 bdev = bdev->bus->self;
7679
7680 if (!bdev)
7681 goto skip_bad_vf_detection;
7682
7683 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7684 if (!pos)
7685 goto skip_bad_vf_detection;
7686
7687 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7688 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7689 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7690 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7691
7692 req_id = dw1 >> 16;
7693 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7694 if (!(req_id & 0x0080))
7695 goto skip_bad_vf_detection;
7696
7697 pf_func = req_id & 0x01;
7698 if ((pf_func & 1) == (pdev->devfn & 1)) {
7699 unsigned int device_id;
7700
7701 vf = (req_id & 0x7F) >> 1;
7702 e_dev_err("VF %d has caused a PCIe error\n", vf);
7703 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7704 "%8.8x\tdw3: %8.8x\n",
7705 dw0, dw1, dw2, dw3);
7706 switch (adapter->hw.mac.type) {
7707 case ixgbe_mac_82599EB:
7708 device_id = IXGBE_82599_VF_DEVICE_ID;
7709 break;
7710 case ixgbe_mac_X540:
7711 device_id = IXGBE_X540_VF_DEVICE_ID;
7712 break;
7713 default:
7714 device_id = 0;
7715 break;
7716 }
7717
7718 /* Find the pci device of the offending VF */
7719 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7720 while (vfdev) {
7721 if (vfdev->devfn == (req_id & 0xFF))
7722 break;
7723 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7724 device_id, vfdev);
7725 }
7726 /*
7727 * There's a slim chance the VF could have been hot plugged,
7728 * so if it is no longer present we don't need to issue the
7729 * VFLR. Just clean up the AER in that case.
7730 */
7731 if (vfdev) {
7732 e_dev_err("Issuing VFLR to VF %d\n", vf);
7733 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7734 }
7735
7736 pci_cleanup_aer_uncorrect_error_status(pdev);
7737 }
7738
7739 /*
7740 * Even though the error may have occurred on the other port
7741 * we still need to increment the vf error reference count for
7742 * both ports because the I/O resume function will be called
7743 * for both of them.
7744 */
7745 adapter->vferr_refcount++;
7746
7747 return PCI_ERS_RESULT_RECOVERED;
7748
7749 skip_bad_vf_detection:
7750 #endif /* CONFIG_PCI_IOV */
7751 netif_device_detach(netdev);
7752
7753 if (state == pci_channel_io_perm_failure)
7754 return PCI_ERS_RESULT_DISCONNECT;
7755
7756 if (netif_running(netdev))
7757 ixgbe_down(adapter);
7758 pci_disable_device(pdev);
7759
7760 /* Request a slot reset. */
7761 return PCI_ERS_RESULT_NEED_RESET;
7762 }
7763
7764 /**
7765 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7766 * @pdev: Pointer to PCI device
7767 *
7768 * Restart the card from scratch, as if from a cold-boot.
7769 */
7770 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7771 {
7772 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7773 pci_ers_result_t result;
7774 int err;
7775
7776 if (pci_enable_device_mem(pdev)) {
7777 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7778 result = PCI_ERS_RESULT_DISCONNECT;
7779 } else {
7780 pci_set_master(pdev);
7781 pci_restore_state(pdev);
7782 pci_save_state(pdev);
7783
7784 pci_wake_from_d3(pdev, false);
7785
7786 ixgbe_reset(adapter);
7787 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7788 result = PCI_ERS_RESULT_RECOVERED;
7789 }
7790
7791 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7792 if (err) {
7793 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7794 "failed 0x%0x\n", err);
7795 /* non-fatal, continue */
7796 }
7797
7798 return result;
7799 }
7800
7801 /**
7802 * ixgbe_io_resume - called when traffic can start flowing again.
7803 * @pdev: Pointer to PCI device
7804 *
7805 * This callback is called when the error recovery driver tells us that
7806 * its OK to resume normal operation.
7807 */
7808 static void ixgbe_io_resume(struct pci_dev *pdev)
7809 {
7810 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7811 struct net_device *netdev = adapter->netdev;
7812
7813 #ifdef CONFIG_PCI_IOV
7814 if (adapter->vferr_refcount) {
7815 e_info(drv, "Resuming after VF err\n");
7816 adapter->vferr_refcount--;
7817 return;
7818 }
7819
7820 #endif
7821 if (netif_running(netdev))
7822 ixgbe_up(adapter);
7823
7824 netif_device_attach(netdev);
7825 }
7826
7827 static const struct pci_error_handlers ixgbe_err_handler = {
7828 .error_detected = ixgbe_io_error_detected,
7829 .slot_reset = ixgbe_io_slot_reset,
7830 .resume = ixgbe_io_resume,
7831 };
7832
7833 static struct pci_driver ixgbe_driver = {
7834 .name = ixgbe_driver_name,
7835 .id_table = ixgbe_pci_tbl,
7836 .probe = ixgbe_probe,
7837 .remove = __devexit_p(ixgbe_remove),
7838 #ifdef CONFIG_PM
7839 .suspend = ixgbe_suspend,
7840 .resume = ixgbe_resume,
7841 #endif
7842 .shutdown = ixgbe_shutdown,
7843 .err_handler = &ixgbe_err_handler
7844 };
7845
7846 /**
7847 * ixgbe_init_module - Driver Registration Routine
7848 *
7849 * ixgbe_init_module is the first routine called when the driver is
7850 * loaded. All it does is register with the PCI subsystem.
7851 **/
7852 static int __init ixgbe_init_module(void)
7853 {
7854 int ret;
7855 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7856 pr_info("%s\n", ixgbe_copyright);
7857
7858 #ifdef CONFIG_DEBUG_FS
7859 ixgbe_dbg_init();
7860 #endif /* CONFIG_DEBUG_FS */
7861
7862 #ifdef CONFIG_IXGBE_DCA
7863 dca_register_notify(&dca_notifier);
7864 #endif
7865
7866 ret = pci_register_driver(&ixgbe_driver);
7867 return ret;
7868 }
7869
7870 module_init(ixgbe_init_module);
7871
7872 /**
7873 * ixgbe_exit_module - Driver Exit Cleanup Routine
7874 *
7875 * ixgbe_exit_module is called just before the driver is removed
7876 * from memory.
7877 **/
7878 static void __exit ixgbe_exit_module(void)
7879 {
7880 #ifdef CONFIG_IXGBE_DCA
7881 dca_unregister_notify(&dca_notifier);
7882 #endif
7883 pci_unregister_driver(&ixgbe_driver);
7884
7885 #ifdef CONFIG_DEBUG_FS
7886 ixgbe_dbg_exit();
7887 #endif /* CONFIG_DEBUG_FS */
7888
7889 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7890 }
7891
7892 #ifdef CONFIG_IXGBE_DCA
7893 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7894 void *p)
7895 {
7896 int ret_val;
7897
7898 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7899 __ixgbe_notify_dca);
7900
7901 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7902 }
7903
7904 #endif /* CONFIG_IXGBE_DCA */
7905
7906 module_exit(ixgbe_exit_module);
7907
7908 /* ixgbe_main.c */
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