drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27 #include "ixgbe.h"
  28 #include <linux/export.h>
  29 #include <linux/ptp_classify.h>
  30
  31 /*
  32  * The 82599 and the X540 do not have true 64bit nanosecond scale
  33  * counter registers. Instead, SYSTIME is defined by a fixed point
  34  * system which allows the user to define the scale counter increment
  35  * value at every level change of the oscillator driving the SYSTIME
  36  * value. For both devices the TIMINCA:IV field defines this
  37  * increment. On the X540 device, 31 bits are provided. However on the
  38  * 82599 only provides 24 bits. The time unit is determined by the
  39  * clock frequency of the oscillator in combination with the TIMINCA
  40  * register. When these devices link at 10Gb the oscillator has a
  41  * period of 6.4ns. In order to convert the scale counter into
  42  * nanoseconds the cyclecounter and timecounter structures are
  43  * used. The SYSTIME registers need to be converted to ns values by use
  44  * of only a right shift (division by power of 2). The following math
  45  * determines the largest incvalue that will fit into the available
  46  * bits in the TIMINCA register.
  47  *
  48  * PeriodWidth: Number of bits to store the clock period
  49  * MaxWidth: The maximum width value of the TIMINCA register
  50  * Period: The clock period for the oscillator
  51  * round(): discard the fractional portion of the calculation
  52  *
  53  * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
  54  *
  55  * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
  56  * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
  57  *
  58  * The period also changes based on the link speed:
  59  * At 10Gb link or no link, the period remains the same.
  60  * At 1Gb link, the period is multiplied by 10. (64ns)
  61  * At 100Mb link, the period is multiplied by 100. (640ns)
  62  *
  63  * The calculated value allows us to right shift the SYSTIME register
  64  * value in order to quickly convert it into a nanosecond clock,
  65  * while allowing for the maximum possible adjustment value.
  66  *
  67  * These diagrams are only for the 10Gb link period
  68  *
  69  *           SYSTIMEH            SYSTIMEL
  70  *       +--------------+  +--------------+
  71  * X540  |      32      |  | 1 | 3 |  28  |
  72  *       *--------------+  +--------------+
  73  *        \________ 36 bits ______/  fract
  74  *
  75  *       +--------------+  +--------------+
  76  * 82599 |      32      |  | 8 | 3 |  21  |
  77  *       *--------------+  +--------------+
  78  *        \________ 43 bits ______/  fract
  79  *
  80  * The 36 bit X540 SYSTIME overflows every
  81  *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
  82  *
  83  * The 43 bit 82599 SYSTIME overflows every
  84  *   2^43 * 10^-9 / 3600 = 2.4 hours
  85  */
  86 #define IXGBE_INCVAL_10GB 0x66666666
  87 #define IXGBE_INCVAL_1GB  0x40000000
  88 #define IXGBE_INCVAL_100  0x50000000
  89
  90 #define IXGBE_INCVAL_SHIFT_10GB  28
  91 #define IXGBE_INCVAL_SHIFT_1GB   24
  92 #define IXGBE_INCVAL_SHIFT_100   21
  93
  94 #define IXGBE_INCVAL_SHIFT_82599 7
  95 #define IXGBE_INCPER_SHIFT_82599 24
  96 #define IXGBE_MAX_TIMEADJ_VALUE  0x7FFFFFFFFFFFFFFFULL
  97
  98 #define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
  99
 100 #ifndef NSECS_PER_SEC
 101 #define NSECS_PER_SEC 1000000000ULL
 102 #endif
 103
 104 static struct sock_filter ptp_filter[] = {
 105         PTP_FILTER
 106 };
 107
 108 /**
 109  * ixgbe_ptp_setup_sdp
 110  * @hw: the hardware private structure
 111  *
 112  * this function enables or disables the clock out feature on SDP0 for
 113  * the X540 device. It will create a 1second periodic output that can
 114  * be used as the PPS (via an interrupt).
 115  *
 116  * It calculates when the systime will be on an exact second, and then
 117  * aligns the start of the PPS signal to that value. The shift is
 118  * necessary because it can change based on the link speed.
 119  */
 120 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
 121 {
 122         struct ixgbe_hw *hw = &adapter->hw;
 123         int shift = adapter->cc.shift;
 124         u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
 125         u64 ns = 0, clock_edge = 0;
 126
 127         if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
 128             (hw->mac.type == ixgbe_mac_X540)) {
 129
 130                 /* disable the pin first */
 131                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 132                 IXGBE_WRITE_FLUSH(hw);
 133
 134                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 135
 136                 /*
 137                  * enable the SDP0 pin as output, and connected to the
 138                  * native function for Timesync (ClockOut)
 139                  */
 140                 esdp |= (IXGBE_ESDP_SDP0_DIR |
 141                          IXGBE_ESDP_SDP0_NATIVE);
 142
 143                 /*
 144                  * enable the Clock Out feature on SDP0, and allow
 145                  * interrupts to occur when the pin changes
 146                  */
 147                 tsauxc = (IXGBE_TSAUXC_EN_CLK |
 148                           IXGBE_TSAUXC_SYNCLK |
 149                           IXGBE_TSAUXC_SDP0_INT);
 150
 151                 /* clock period (or pulse length) */
 152                 clktiml = (u32)(NSECS_PER_SEC << shift);
 153                 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
 154
 155                 /*
 156                  * Account for the cyclecounter wrap-around value by
 157                  * using the converted ns value of the current time to
 158                  * check for when the next aligned second would occur.
 159                  */
 160                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 161                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 162                 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
 163
 164                 div_u64_rem(ns, NSECS_PER_SEC, &rem);
 165                 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
 166
 167                 /* specify the initial clock start time */
 168                 trgttiml = (u32)clock_edge;
 169                 trgttimh = (u32)(clock_edge >> 32);
 170
 171                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
 172                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
 173                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 174                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 175
 176                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 177                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 178         } else {
 179                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 180         }
 181
 182         IXGBE_WRITE_FLUSH(hw);
 183 }
 184
 185 /**
 186  * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
 187  * @cc: the cyclecounter structure
 188  *
 189  * this function reads the cyclecounter registers and is called by the
 190  * cyclecounter structure used to construct a ns counter from the
 191  * arbitrary fixed point registers
 192  */
 193 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
 194 {
 195         struct ixgbe_adapter *adapter =
 196                 container_of(cc, struct ixgbe_adapter, cc);
 197         struct ixgbe_hw *hw = &adapter->hw;
 198         u64 stamp = 0;
 199
 200         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 201         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 202
 203         return stamp;
 204 }
 205
 206 /**
 207  * ixgbe_ptp_adjfreq
 208  * @ptp: the ptp clock structure
 209  * @ppb: parts per billion adjustment from base
 210  *
 211  * adjust the frequency of the ptp cycle counter by the
 212  * indicated ppb from the base frequency.
 213  */
 214 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 215 {
 216         struct ixgbe_adapter *adapter =
 217                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 218         struct ixgbe_hw *hw = &adapter->hw;
 219         u64 freq;
 220         u32 diff, incval;
 221         int neg_adj = 0;
 222
 223         if (ppb < 0) {
 224                 neg_adj = 1;
 225                 ppb = -ppb;
 226         }
 227
 228         smp_mb();
 229         incval = ACCESS_ONCE(adapter->base_incval);
 230
 231         freq = incval;
 232         freq *= ppb;
 233         diff = div_u64(freq, 1000000000ULL);
 234
 235         incval = neg_adj ? (incval - diff) : (incval + diff);
 236
 237         switch (hw->mac.type) {
 238         case ixgbe_mac_X540:
 239                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 240                 break;
 241         case ixgbe_mac_82599EB:
 242                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 243                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 244                                 incval);
 245                 break;
 246         default:
 247                 break;
 248         }
 249
 250         return 0;
 251 }
 252
 253 /**
 254  * ixgbe_ptp_adjtime
 255  * @ptp: the ptp clock structure
 256  * @delta: offset to adjust the cycle counter by
 257  *
 258  * adjust the timer by resetting the timecounter structure.
 259  */
 260 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 261 {
 262         struct ixgbe_adapter *adapter =
 263                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 264         unsigned long flags;
 265         u64 now;
 266
 267         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 268
 269         now = timecounter_read(&adapter->tc);
 270         now += delta;
 271
 272         /* reset the timecounter */
 273         timecounter_init(&adapter->tc,
 274                          &adapter->cc,
 275                          now);
 276
 277         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 278
 279         ixgbe_ptp_setup_sdp(adapter);
 280
 281         return 0;
 282 }
 283
 284 /**
 285  * ixgbe_ptp_gettime
 286  * @ptp: the ptp clock structure
 287  * @ts: timespec structure to hold the current time value
 288  *
 289  * read the timecounter and return the correct value on ns,
 290  * after converting it into a struct timespec.
 291  */
 292 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 293 {
 294         struct ixgbe_adapter *adapter =
 295                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 296         u64 ns;
 297         u32 remainder;
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 301         ns = timecounter_read(&adapter->tc);
 302         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 303
 304         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
 305         ts->tv_nsec = remainder;
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * ixgbe_ptp_settime
 312  * @ptp: the ptp clock structure
 313  * @ts: the timespec containing the new time for the cycle counter
 314  *
 315  * reset the timecounter to use a new base value instead of the kernel
 316  * wall timer value.
 317  */
 318 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
 319                              const struct timespec *ts)
 320 {
 321         struct ixgbe_adapter *adapter =
 322                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 323         u64 ns;
 324         unsigned long flags;
 325
 326         ns = ts->tv_sec * 1000000000ULL;
 327         ns += ts->tv_nsec;
 328
 329         /* reset the timecounter */
 330         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 331         timecounter_init(&adapter->tc, &adapter->cc, ns);
 332         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 333
 334         ixgbe_ptp_setup_sdp(adapter);
 335         return 0;
 336 }
 337
 338 /**
 339  * ixgbe_ptp_enable
 340  * @ptp: the ptp clock structure
 341  * @rq: the requested feature to change
 342  * @on: whether to enable or disable the feature
 343  *
 344  * enable (or disable) ancillary features of the phc subsystem.
 345  * our driver only supports the PPS feature on the X540
 346  */
 347 static int ixgbe_ptp_enable(struct ptp_clock_info *ptp,
 348                             struct ptp_clock_request *rq, int on)
 349 {
 350         struct ixgbe_adapter *adapter =
 351                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 352
 353         /**
 354          * When PPS is enabled, unmask the interrupt for the ClockOut
 355          * feature, so that the interrupt handler can send the PPS
 356          * event when the clock SDP triggers. Clear mask when PPS is
 357          * disabled
 358          */
 359         if (rq->type == PTP_CLK_REQ_PPS) {
 360                 switch (adapter->hw.mac.type) {
 361                 case ixgbe_mac_X540:
 362                         if (on)
 363                                 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
 364                         else
 365                                 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 366
 367                         ixgbe_ptp_setup_sdp(adapter);
 368                         return 0;
 369                 default:
 370                         break;
 371                 }
 372         }
 373
 374         return -ENOTSUPP;
 375 }
 376
 377 /**
 378  * ixgbe_ptp_check_pps_event
 379  * @adapter: the private adapter structure
 380  * @eicr: the interrupt cause register value
 381  *
 382  * This function is called by the interrupt routine when checking for
 383  * interrupts. It will check and handle a pps event.
 384  */
 385 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
 386 {
 387         struct ixgbe_hw *hw = &adapter->hw;
 388         struct ptp_clock_event event;
 389
 390         switch (hw->mac.type) {
 391         case ixgbe_mac_X540:
 392                 ptp_clock_event(adapter->ptp_clock, &event);
 393                 break;
 394         default:
 395                 break;
 396         }
 397 }
 398
 399
 400 /**
 401  * ixgbe_ptp_overflow_check - delayed work to detect SYSTIME overflow
 402  * @work: structure containing information about this work task
 403  *
 404  * this work function is scheduled to continue reading the timecounter
 405  * in order to prevent missing when the system time registers wrap
 406  * around. This needs to be run approximately twice a minute when no
 407  * PTP activity is occurring.
 408  */
 409 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
 410 {
 411         unsigned long elapsed_jiffies = adapter->last_overflow_check - jiffies;
 412         struct timespec ts;
 413
 414         if ((adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) &&
 415             (elapsed_jiffies >= IXGBE_OVERFLOW_PERIOD)) {
 416                 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
 417                 adapter->last_overflow_check = jiffies;
 418         }
 419 }
 420
 421 /**
 422  * ixgbe_ptp_match - determine if this skb matches a ptp packet
 423  * @skb: pointer to the skb
 424  * @hwtstamp: pointer to the hwtstamp_config to check
 425  *
 426  * Determine whether the skb should have been timestamped, assuming the
 427  * hwtstamp was set via the hwtstamp ioctl. Returns non-zero when the packet
 428  * should have a timestamp waiting in the registers, and 0 otherwise.
 429  *
 430  * V1 packets have to check the version type to determine whether they are
 431  * correct. However, we can't directly access the data because it might be
 432  * fragmented in the SKB, in paged memory. In order to work around this, we
 433  * use skb_copy_bits which will properly copy the data whether it is in the
 434  * paged memory fragments or not. We have to copy the IP header as well as the
 435  * message type.
 436  */
 437 static int ixgbe_ptp_match(struct sk_buff *skb, int rx_filter)
 438 {
 439         struct iphdr iph;
 440         u8 msgtype;
 441         unsigned int type, offset;
 442
 443         if (rx_filter == HWTSTAMP_FILTER_NONE)
 444                 return 0;
 445
 446         type = sk_run_filter(skb, ptp_filter);
 447
 448         if (likely(rx_filter == HWTSTAMP_FILTER_PTP_V2_EVENT))
 449                 return type & PTP_CLASS_V2;
 450
 451         /* For the remaining cases actually check message type */
 452         switch (type) {
 453         case PTP_CLASS_V1_IPV4:
 454                 skb_copy_bits(skb, OFF_IHL, &iph, sizeof(iph));
 455                 offset = ETH_HLEN + (iph.ihl << 2) + UDP_HLEN + OFF_PTP_CONTROL;
 456                 break;
 457         case PTP_CLASS_V1_IPV6:
 458                 offset = OFF_PTP6 + OFF_PTP_CONTROL;
 459                 break;
 460         default:
 461                 /* other cases invalid or handled above */
 462                 return 0;
 463         }
 464
 465         /* Make sure our buffer is long enough */
 466         if (skb->len < offset)
 467                 return 0;
 468
 469         skb_copy_bits(skb, offset, &msgtype, sizeof(msgtype));
 470
 471         switch (rx_filter) {
 472         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 473                 return (msgtype == IXGBE_RXMTRL_V1_SYNC_MSG);
 474                 break;
 475         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 476                 return (msgtype == IXGBE_RXMTRL_V1_DELAY_REQ_MSG);
 477                 break;
 478         default:
 479                 return 0;
 480         }
 481 }
 482
 483 /**
 484  * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 485  * @q_vector: structure containing interrupt and ring information
 486  * @skb: particular skb to send timestamp with
 487  *
 488  * if the timestamp is valid, we convert it into the timecounter ns
 489  * value, then store that result into the shhwtstamps structure which
 490  * is passed up the network stack
 491  */
 492 void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
 493                            struct sk_buff *skb)
 494 {
 495         struct ixgbe_adapter *adapter;
 496         struct ixgbe_hw *hw;
 497         struct skb_shared_hwtstamps shhwtstamps;
 498         u64 regval = 0, ns;
 499         u32 tsynctxctl;
 500         unsigned long flags;
 501
 502         /* we cannot process timestamps on a ring without a q_vector */
 503         if (!q_vector || !q_vector->adapter)
 504                 return;
 505
 506         adapter = q_vector->adapter;
 507         hw = &adapter->hw;
 508
 509         tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 510         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
 511         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
 512
 513         /*
 514          * if TX timestamp is not valid, exit after clearing the
 515          * timestamp registers
 516          */
 517         if (!(tsynctxctl & IXGBE_TSYNCTXCTL_VALID))
 518                 return;
 519
 520         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 521         ns = timecounter_cyc2time(&adapter->tc, regval);
 522         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 523
 524         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 525         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 526         skb_tstamp_tx(skb, &shhwtstamps);
 527 }
 528
 529 /**
 530  * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
 531  * @q_vector: structure containing interrupt and ring information
 532  * @rx_desc: the rx descriptor
 533  * @skb: particular skb to send timestamp with
 534  *
 535  * if the timestamp is valid, we convert it into the timecounter ns
 536  * value, then store that result into the shhwtstamps structure which
 537  * is passed up the network stack
 538  */
 539 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
 540                            union ixgbe_adv_rx_desc *rx_desc,
 541                            struct sk_buff *skb)
 542 {
 543         struct ixgbe_adapter *adapter;
 544         struct ixgbe_hw *hw;
 545         struct skb_shared_hwtstamps *shhwtstamps;
 546         u64 regval = 0, ns;
 547         u32 tsyncrxctl;
 548         unsigned long flags;
 549
 550         /* we cannot process timestamps on a ring without a q_vector */
 551         if (!q_vector || !q_vector->adapter)
 552                 return;
 553
 554         adapter = q_vector->adapter;
 555         hw = &adapter->hw;
 556
 557         tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 558
 559         /* Check if we have a valid timestamp and make sure the skb should
 560          * have been timestamped */
 561         if (likely(!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID) ||
 562                    !ixgbe_ptp_match(skb, adapter->rx_hwtstamp_filter)))
 563                 return;
 564
 565         /*
 566          * Always read the registers, in order to clear a possible fault
 567          * because of stagnant RX timestamp values for a packet that never
 568          * reached the queue.
 569          */
 570         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
 571         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
 572
 573         /*
 574          * If the timestamp bit is set in the packet's descriptor, we know the
 575          * timestamp belongs to this packet. No other packet can be
 576          * timestamped until the registers for timestamping have been read.
 577          * Therefor only one packet with this bit can be in the queue at a
 578          * time, and the rx timestamp values that were in the registers belong
 579          * to this packet.
 580          *
 581          * If nothing went wrong, then it should have a skb_shared_tx that we
 582          * can turn into a skb_shared_hwtstamps.
 583          */
 584         if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
 585                 return;
 586
 587         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 588         ns = timecounter_cyc2time(&adapter->tc, regval);
 589         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 590
 591         shhwtstamps = skb_hwtstamps(skb);
 592         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 593 }
 594
 595 /**
 596  * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping
 597  * @adapter: pointer to adapter struct
 598  * @ifreq: ioctl data
 599  * @cmd: particular ioctl requested
 600  *
 601  * Outgoing time stamping can be enabled and disabled. Play nice and
 602  * disable it when requested, although it shouldn't case any overhead
 603  * when no packet needs it. At most one packet in the queue may be
 604  * marked for time stamping, otherwise it would be impossible to tell
 605  * for sure to which packet the hardware time stamp belongs.
 606  *
 607  * Incoming time stamping has to be configured via the hardware
 608  * filters. Not all combinations are supported, in particular event
 609  * type has to be specified. Matching the kind of event packet is
 610  * not supported, with the exception of "all V2 events regardless of
 611  * level 2 or 4".
 612  *
 613  * Since hardware always timestamps Path delay packets when timestamping V2
 614  * packets, regardless of the type specified in the register, only use V2
 615  * Event mode. This more accurately tells the user what the hardware is going
 616  * to do anyways.
 617  */
 618 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
 619                              struct ifreq *ifr, int cmd)
 620 {
 621         struct ixgbe_hw *hw = &adapter->hw;
 622         struct hwtstamp_config config;
 623         u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
 624         u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
 625         u32 tsync_rx_mtrl = 0;
 626         bool is_l4 = false;
 627         bool is_l2 = false;
 628         u32 regval;
 629
 630         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 631                 return -EFAULT;
 632
 633         /* reserved for future extensions */
 634         if (config.flags)
 635                 return -EINVAL;
 636
 637         switch (config.tx_type) {
 638         case HWTSTAMP_TX_OFF:
 639                 tsync_tx_ctl = 0;
 640         case HWTSTAMP_TX_ON:
 641                 break;
 642         default:
 643                 return -ERANGE;
 644         }
 645
 646         switch (config.rx_filter) {
 647         case HWTSTAMP_FILTER_NONE:
 648                 tsync_rx_ctl = 0;
 649                 break;
 650         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 651                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 652                 tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG;
 653                 is_l4 = true;
 654                 break;
 655         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 656                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 657                 tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
 658                 is_l4 = true;
 659                 break;
 660         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 661         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 662         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 663         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 664         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 665         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 666         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 667         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 668         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 669                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
 670                 is_l2 = true;
 671                 is_l4 = true;
 672                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 673                 break;
 674         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 675         case HWTSTAMP_FILTER_ALL:
 676         default:
 677                 /*
 678                  * register RXMTRL must be set in order to do V1 packets,
 679                  * therefore it is not possible to time stamp both V1 Sync and
 680                  * Delay_Req messages and hardware does not support
 681                  * timestamping all packets => return error
 682                  */
 683                 config.rx_filter = HWTSTAMP_FILTER_NONE;
 684                 return -ERANGE;
 685         }
 686
 687         if (hw->mac.type == ixgbe_mac_82598EB) {
 688                 if (tsync_rx_ctl | tsync_tx_ctl)
 689                         return -ERANGE;
 690                 return 0;
 691         }
 692
 693         /* Store filter value for later use */
 694         adapter->rx_hwtstamp_filter = config.rx_filter;
 695
 696         /* define ethertype filter for timestamped packets */
 697         if (is_l2)
 698                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(3),
 699                                 (IXGBE_ETQF_FILTER_EN | /* enable filter */
 700                                  IXGBE_ETQF_1588 | /* enable timestamping */
 701                                  ETH_P_1588));     /* 1588 eth protocol type */
 702         else
 703                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(3), 0);
 704
 705 #define PTP_PORT 319
 706         /* L4 Queue Filter[3]: filter by destination port and protocol */
 707         if (is_l4) {
 708                 u32 ftqf = (IXGBE_FTQF_PROTOCOL_UDP /* UDP */
 709                             | IXGBE_FTQF_POOL_MASK_EN /* Pool not compared */
 710                             | IXGBE_FTQF_QUEUE_ENABLE);
 711
 712                 ftqf |= ((IXGBE_FTQF_PROTOCOL_COMP_MASK /* protocol check */
 713                           & IXGBE_FTQF_DEST_PORT_MASK /* dest check */
 714                           & IXGBE_FTQF_SOURCE_PORT_MASK) /* source check */
 715                          << IXGBE_FTQF_5TUPLE_MASK_SHIFT);
 716
 717                 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(3),
 718                                 (3 << IXGBE_IMIR_RX_QUEUE_SHIFT_82599 |
 719                                  IXGBE_IMIR_SIZE_BP_82599));
 720
 721                 /* enable port check */
 722                 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(3),
 723                                 (htons(PTP_PORT) |
 724                                  htons(PTP_PORT) << 16));
 725
 726                 IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), ftqf);
 727
 728                 tsync_rx_mtrl |= PTP_PORT << 16;
 729         } else {
 730                 IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), 0);
 731         }
 732
 733         /* enable/disable TX */
 734         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 735         regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
 736         regval |= tsync_tx_ctl;
 737         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
 738
 739         /* enable/disable RX */
 740         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 741         regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
 742         regval |= tsync_rx_ctl;
 743         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
 744
 745         /* define which PTP packets are time stamped */
 746         IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
 747
 748         IXGBE_WRITE_FLUSH(hw);
 749
 750         /* clear TX/RX time stamp registers, just to be sure */
 751         regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
 752         regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 753
 754         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 755                 -EFAULT : 0;
 756 }
 757
 758 /**
 759  * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
 760  * @adapter: pointer to the adapter structure
 761  *
 762  * This function should be called to set the proper values for the TIMINCA
 763  * register and tell the cyclecounter structure what the tick rate of SYSTIME
 764  * is. It does not directly modify SYSTIME registers or the timecounter
 765  * structure. It should be called whenever a new TIMINCA value is necessary,
 766  * such as during initialization or when the link speed changes.
 767  */
 768 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
 769 {
 770         struct ixgbe_hw *hw = &adapter->hw;
 771         u32 incval = 0;
 772         u32 shift = 0;
 773         unsigned long flags;
 774
 775         /**
 776          * Scale the NIC cycle counter by a large factor so that
 777          * relatively small corrections to the frequency can be added
 778          * or subtracted. The drawbacks of a large factor include
 779          * (a) the clock register overflows more quickly, (b) the cycle
 780          * counter structure must be able to convert the systime value
 781          * to nanoseconds using only a multiplier and a right-shift,
 782          * and (c) the value must fit within the timinca register space
 783          * => math based on internal DMA clock rate and available bits
 784          *
 785          * Note that when there is no link, internal DMA clock is same as when
 786          * link speed is 10Gb. Set the registers correctly even when link is
 787          * down to preserve the clock setting
 788          */
 789         switch (adapter->link_speed) {
 790         case IXGBE_LINK_SPEED_100_FULL:
 791                 incval = IXGBE_INCVAL_100;
 792                 shift = IXGBE_INCVAL_SHIFT_100;
 793                 break;
 794         case IXGBE_LINK_SPEED_1GB_FULL:
 795                 incval = IXGBE_INCVAL_1GB;
 796                 shift = IXGBE_INCVAL_SHIFT_1GB;
 797                 break;
 798         case IXGBE_LINK_SPEED_10GB_FULL:
 799         default:
 800                 incval = IXGBE_INCVAL_10GB;
 801                 shift = IXGBE_INCVAL_SHIFT_10GB;
 802                 break;
 803         }
 804
 805         /**
 806          * Modify the calculated values to fit within the correct
 807          * number of bits specified by the hardware. The 82599 doesn't
 808          * have the same space as the X540, so bitshift the calculated
 809          * values to fit.
 810          */
 811         switch (hw->mac.type) {
 812         case ixgbe_mac_X540:
 813                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 814                 break;
 815         case ixgbe_mac_82599EB:
 816                 incval >>= IXGBE_INCVAL_SHIFT_82599;
 817                 shift -= IXGBE_INCVAL_SHIFT_82599;
 818                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 819                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 820                                 incval);
 821                 break;
 822         default:
 823                 /* other devices aren't supported */
 824                 return;
 825         }
 826
 827         /* update the base incval used to calculate frequency adjustment */
 828         ACCESS_ONCE(adapter->base_incval) = incval;
 829         smp_mb();
 830
 831         /* need lock to prevent incorrect read while modifying cyclecounter */
 832         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 833
 834         memset(&adapter->cc, 0, sizeof(adapter->cc));
 835         adapter->cc.read = ixgbe_ptp_read;
 836         adapter->cc.mask = CLOCKSOURCE_MASK(64);
 837         adapter->cc.shift = shift;
 838         adapter->cc.mult = 1;
 839
 840         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 841 }
 842
 843 /**
 844  * ixgbe_ptp_reset
 845  * @adapter: the ixgbe private board structure
 846  *
 847  * When the MAC resets, all timesync features are reset. This function should be
 848  * called to re-enable the PTP clock structure. It will re-init the timecounter
 849  * structure based on the kernel time as well as setup the cycle counter data.
 850  */
 851 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
 852 {
 853         struct ixgbe_hw *hw = &adapter->hw;
 854         unsigned long flags;
 855
 856         /* set SYSTIME registers to 0 just in case */
 857         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
 858         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
 859         IXGBE_WRITE_FLUSH(hw);
 860
 861         ixgbe_ptp_start_cyclecounter(adapter);
 862
 863         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 864
 865         /* reset the ns time counter */
 866         timecounter_init(&adapter->tc, &adapter->cc,
 867                          ktime_to_ns(ktime_get_real()));
 868
 869         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 870
 871         /*
 872          * Now that the shift has been calculated and the systime
 873          * registers reset, (re-)enable the Clock out feature
 874          */
 875         ixgbe_ptp_setup_sdp(adapter);
 876 }
 877
 878 /**
 879  * ixgbe_ptp_init
 880  * @adapter: the ixgbe private adapter structure
 881  *
 882  * This function performs the required steps for enabling ptp
 883  * support. If ptp support has already been loaded it simply calls the
 884  * cyclecounter init routine and exits.
 885  */
 886 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
 887 {
 888         struct net_device *netdev = adapter->netdev;
 889
 890         switch (adapter->hw.mac.type) {
 891         case ixgbe_mac_X540:
 892                 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
 893                 adapter->ptp_caps.owner = THIS_MODULE;
 894                 adapter->ptp_caps.max_adj = 250000000;
 895                 adapter->ptp_caps.n_alarm = 0;
 896                 adapter->ptp_caps.n_ext_ts = 0;
 897                 adapter->ptp_caps.n_per_out = 0;
 898                 adapter->ptp_caps.pps = 1;
 899                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 900                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 901                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 902                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 903                 adapter->ptp_caps.enable = ixgbe_ptp_enable;
 904                 break;
 905         case ixgbe_mac_82599EB:
 906                 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
 907                 adapter->ptp_caps.owner = THIS_MODULE;
 908                 adapter->ptp_caps.max_adj = 250000000;
 909                 adapter->ptp_caps.n_alarm = 0;
 910                 adapter->ptp_caps.n_ext_ts = 0;
 911                 adapter->ptp_caps.n_per_out = 0;
 912                 adapter->ptp_caps.pps = 0;
 913                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 914                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 915                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 916                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 917                 adapter->ptp_caps.enable = ixgbe_ptp_enable;
 918                 break;
 919         default:
 920                 adapter->ptp_clock = NULL;
 921                 return;
 922         }
 923
 924         /* initialize the ptp filter */
 925         if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter)))
 926                 e_dev_warn("ptp_filter_init failed\n");
 927
 928         spin_lock_init(&adapter->tmreg_lock);
 929
 930         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 931                                                 &adapter->pdev->dev);
 932         if (IS_ERR(adapter->ptp_clock)) {
 933                 adapter->ptp_clock = NULL;
 934                 e_dev_err("ptp_clock_register failed\n");
 935         } else
 936                 e_dev_info("registered PHC device on %s\n", netdev->name);
 937
 938         ixgbe_ptp_reset(adapter);
 939
 940         /* set the flag that PTP has been enabled */
 941         adapter->flags2 |= IXGBE_FLAG2_PTP_ENABLED;
 942
 943         return;
 944 }
 945
 946 /**
 947  * ixgbe_ptp_stop - disable ptp device and stop the overflow check
 948  * @adapter: pointer to adapter struct
 949  *
 950  * this function stops the ptp support, and cancels the delayed work.
 951  */
 952 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
 953 {
 954         /* stop the overflow check task */
 955         adapter->flags2 &= ~(IXGBE_FLAG2_PTP_ENABLED |
 956                              IXGBE_FLAG2_PTP_PPS_ENABLED);
 957
 958         ixgbe_ptp_setup_sdp(adapter);
 959
 960         if (adapter->ptp_clock) {
 961                 ptp_clock_unregister(adapter->ptp_clock);
 962                 adapter->ptp_clock = NULL;
 963                 e_dev_info("removed PHC on %s\n",
 964                            adapter->netdev->name);
 965         }
 966 }