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ixgbe: Update NW_MNG_IF_SEL support for X553
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_x550.c
1 /*******************************************************************************
2 *
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 1999 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * Linux NICS <linux.nics@intel.com>
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 *
23 ******************************************************************************/
24 #include "ixgbe_x540.h"
25 #include "ixgbe_type.h"
26 #include "ixgbe_common.h"
27 #include "ixgbe_phy.h"
28
29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
34
35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
36 {
37 struct ixgbe_mac_info *mac = &hw->mac;
38 struct ixgbe_phy_info *phy = &hw->phy;
39 struct ixgbe_link_info *link = &hw->link;
40
41 /* Start with X540 invariants, since so simular */
42 ixgbe_get_invariants_X540(hw);
43
44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
45 phy->ops.set_phy_power = NULL;
46
47 link->addr = IXGBE_CS4227;
48
49 return 0;
50 }
51
52 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
53 {
54 struct ixgbe_phy_info *phy = &hw->phy;
55
56 /* Start with X540 invariants, since so similar */
57 ixgbe_get_invariants_X540(hw);
58
59 phy->ops.set_phy_power = NULL;
60
61 return 0;
62 }
63
64 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
65 {
66 struct ixgbe_mac_info *mac = &hw->mac;
67 struct ixgbe_phy_info *phy = &hw->phy;
68
69 /* Start with X540 invariants, since so simular */
70 ixgbe_get_invariants_X540(hw);
71
72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
73 phy->ops.set_phy_power = NULL;
74
75 return 0;
76 }
77
78 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
79 {
80 struct ixgbe_phy_info *phy = &hw->phy;
81
82 /* Start with X540 invariants, since so similar */
83 ixgbe_get_invariants_X540(hw);
84
85 phy->ops.set_phy_power = NULL;
86
87 return 0;
88 }
89
90 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
91 * @hw: pointer to hardware structure
92 **/
93 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
94 {
95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
96
97 if (hw->bus.lan_id) {
98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
99 esdp |= IXGBE_ESDP_SDP1_DIR;
100 }
101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
103 IXGBE_WRITE_FLUSH(hw);
104 }
105
106 /**
107 * ixgbe_read_cs4227 - Read CS4227 register
108 * @hw: pointer to hardware structure
109 * @reg: register number to write
110 * @value: pointer to receive value read
111 *
112 * Returns status code
113 */
114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
115 {
116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
117 }
118
119 /**
120 * ixgbe_write_cs4227 - Write CS4227 register
121 * @hw: pointer to hardware structure
122 * @reg: register number to write
123 * @value: value to write to register
124 *
125 * Returns status code
126 */
127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
128 {
129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
130 }
131
132 /**
133 * ixgbe_read_pe - Read register from port expander
134 * @hw: pointer to hardware structure
135 * @reg: register number to read
136 * @value: pointer to receive read value
137 *
138 * Returns status code
139 */
140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
141 {
142 s32 status;
143
144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
145 if (status)
146 hw_err(hw, "port expander access failed with %d\n", status);
147 return status;
148 }
149
150 /**
151 * ixgbe_write_pe - Write register to port expander
152 * @hw: pointer to hardware structure
153 * @reg: register number to write
154 * @value: value to write
155 *
156 * Returns status code
157 */
158 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
159 {
160 s32 status;
161
162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
163 value);
164 if (status)
165 hw_err(hw, "port expander access failed with %d\n", status);
166 return status;
167 }
168
169 /**
170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
171 * @hw: pointer to hardware structure
172 *
173 * This function assumes that the caller has acquired the proper semaphore.
174 * Returns error code
175 */
176 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
177 {
178 s32 status;
179 u32 retry;
180 u16 value;
181 u8 reg;
182
183 /* Trigger hard reset. */
184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
185 if (status)
186 return status;
187 reg |= IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
189 if (status)
190 return status;
191
192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
193 if (status)
194 return status;
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
197 if (status)
198 return status;
199
200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
201 if (status)
202 return status;
203 reg &= ~IXGBE_PE_BIT1;
204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
205 if (status)
206 return status;
207
208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
209
210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
211 if (status)
212 return status;
213 reg |= IXGBE_PE_BIT1;
214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
215 if (status)
216 return status;
217
218 /* Wait for the reset to complete. */
219 msleep(IXGBE_CS4227_RESET_DELAY);
220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
222 &value);
223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
224 break;
225 msleep(IXGBE_CS4227_CHECK_DELAY);
226 }
227 if (retry == IXGBE_CS4227_RETRIES) {
228 hw_err(hw, "CS4227 reset did not complete\n");
229 return IXGBE_ERR_PHY;
230 }
231
232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
234 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
235 return IXGBE_ERR_PHY;
236 }
237
238 return 0;
239 }
240
241 /**
242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
243 * @hw: pointer to hardware structure
244 */
245 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
246 {
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 s32 status;
249 u16 value;
250 u8 retry;
251
252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
254 if (status) {
255 hw_err(hw, "semaphore failed with %d\n", status);
256 msleep(IXGBE_CS4227_CHECK_DELAY);
257 continue;
258 }
259
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
263 goto out;
264
265 if (status || value != IXGBE_CS4227_RESET_PENDING)
266 break;
267
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msleep(IXGBE_CS4227_CHECK_DELAY);
271 }
272 /* If still pending, assume other instance failed. */
273 if (retry == IXGBE_CS4227_RETRIES) {
274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
275 if (status) {
276 hw_err(hw, "semaphore failed with %d\n", status);
277 return;
278 }
279 }
280
281 /* Reset the CS4227. */
282 status = ixgbe_reset_cs4227(hw);
283 if (status) {
284 hw_err(hw, "CS4227 reset failed: %d", status);
285 goto out;
286 }
287
288 /* Reset takes so long, temporarily release semaphore in case the
289 * other driver instance is waiting for the reset indication.
290 */
291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
292 IXGBE_CS4227_RESET_PENDING);
293 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
294 usleep_range(10000, 12000);
295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
296 if (status) {
297 hw_err(hw, "semaphore failed with %d", status);
298 return;
299 }
300
301 /* Record completion for next time. */
302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
303 IXGBE_CS4227_RESET_COMPLETE);
304
305 out:
306 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
307 msleep(hw->eeprom.semaphore_delay);
308 }
309
310 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
311 * @hw: pointer to hardware structure
312 *
313 * Returns error code
314 */
315 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
316 {
317 switch (hw->device_id) {
318 case IXGBE_DEV_ID_X550EM_A_SFP:
319 if (hw->bus.lan_id)
320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
321 else
322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
323 return ixgbe_identify_module_generic(hw);
324 case IXGBE_DEV_ID_X550EM_X_SFP:
325 /* set up for CS4227 usage */
326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
327 ixgbe_setup_mux_ctl(hw);
328 ixgbe_check_cs4227(hw);
329 /* Fallthrough */
330 case IXGBE_DEV_ID_X550EM_A_SFP_N:
331 return ixgbe_identify_module_generic(hw);
332 case IXGBE_DEV_ID_X550EM_X_KX4:
333 hw->phy.type = ixgbe_phy_x550em_kx4;
334 break;
335 case IXGBE_DEV_ID_X550EM_X_XFI:
336 hw->phy.type = ixgbe_phy_x550em_xfi;
337 break;
338 case IXGBE_DEV_ID_X550EM_X_KR:
339 case IXGBE_DEV_ID_X550EM_A_KR:
340 case IXGBE_DEV_ID_X550EM_A_KR_L:
341 hw->phy.type = ixgbe_phy_x550em_kr;
342 break;
343 case IXGBE_DEV_ID_X550EM_A_10G_T:
344 if (hw->bus.lan_id)
345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
346 else
347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
348 /* Fallthrough */
349 case IXGBE_DEV_ID_X550EM_X_10G_T:
350 return ixgbe_identify_phy_generic(hw);
351 case IXGBE_DEV_ID_X550EM_X_1G_T:
352 hw->phy.type = ixgbe_phy_ext_1g_t;
353 break;
354 case IXGBE_DEV_ID_X550EM_A_1G_T:
355 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
356 hw->phy.type = ixgbe_phy_fw;
357 hw->phy.ops.read_reg = NULL;
358 hw->phy.ops.write_reg = NULL;
359 if (hw->bus.lan_id)
360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
361 else
362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
363 break;
364 default:
365 break;
366 }
367 return 0;
368 }
369
370 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
371 u32 device_type, u16 *phy_data)
372 {
373 return IXGBE_NOT_IMPLEMENTED;
374 }
375
376 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
377 u32 device_type, u16 phy_data)
378 {
379 return IXGBE_NOT_IMPLEMENTED;
380 }
381
382 /**
383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
384 * @hw: pointer to the hardware structure
385 * @addr: I2C bus address to read from
386 * @reg: I2C device register to read from
387 * @val: pointer to location to receive read value
388 *
389 * Returns an error code on error.
390 **/
391 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
392 u16 reg, u16 *val)
393 {
394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
395 }
396
397 /**
398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
399 * @hw: pointer to the hardware structure
400 * @addr: I2C bus address to read from
401 * @reg: I2C device register to read from
402 * @val: pointer to location to receive read value
403 *
404 * Returns an error code on error.
405 **/
406 static s32
407 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
408 u16 reg, u16 *val)
409 {
410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
411 }
412
413 /**
414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
415 * @hw: pointer to the hardware structure
416 * @addr: I2C bus address to write to
417 * @reg: I2C device register to write to
418 * @val: value to write
419 *
420 * Returns an error code on error.
421 **/
422 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
423 u8 addr, u16 reg, u16 val)
424 {
425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
426 }
427
428 /**
429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
430 * @hw: pointer to the hardware structure
431 * @addr: I2C bus address to write to
432 * @reg: I2C device register to write to
433 * @val: value to write
434 *
435 * Returns an error code on error.
436 **/
437 static s32
438 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
439 u8 addr, u16 reg, u16 val)
440 {
441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
442 }
443
444 /**
445 * ixgbe_fw_phy_activity - Perform an activity on a PHY
446 * @hw: pointer to hardware structure
447 * @activity: activity to perform
448 * @data: Pointer to 4 32-bit words of data
449 */
450 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
451 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
452 {
453 union {
454 struct ixgbe_hic_phy_activity_req cmd;
455 struct ixgbe_hic_phy_activity_resp rsp;
456 } hic;
457 u16 retries = FW_PHY_ACT_RETRIES;
458 s32 rc;
459 u32 i;
460
461 do {
462 memset(&hic, 0, sizeof(hic));
463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
466 hic.cmd.port_number = hw->bus.lan_id;
467 hic.cmd.activity_id = cpu_to_le16(activity);
468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
469 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
470
471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
472 IXGBE_HI_COMMAND_TIMEOUT,
473 true);
474 if (rc)
475 return rc;
476 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
477 FW_CEM_RESP_STATUS_SUCCESS) {
478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
480 return 0;
481 }
482 usleep_range(20, 30);
483 --retries;
484 } while (retries > 0);
485
486 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
487 }
488
489 static const struct {
490 u16 fw_speed;
491 ixgbe_link_speed phy_speed;
492 } ixgbe_fw_map[] = {
493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
499 };
500
501 /**
502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
503 * @hw: pointer to hardware structure
504 *
505 * Returns error code
506 */
507 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
508 {
509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
510 u16 phy_speeds;
511 u16 phy_id_lo;
512 s32 rc;
513 u16 i;
514
515 if (hw->phy.id)
516 return 0;
517
518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
519 if (rc)
520 return rc;
521
522 hw->phy.speeds_supported = 0;
523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
525 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
527 }
528
529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
534 return IXGBE_ERR_PHY_ADDR_INVALID;
535
536 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
538 IXGBE_LINK_SPEED_1GB_FULL;
539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
540 return 0;
541 }
542
543 /**
544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
545 * @hw: pointer to hardware structure
546 *
547 * Returns error code
548 */
549 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
550 {
551 if (hw->bus.lan_id)
552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
553 else
554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
555
556 hw->phy.type = ixgbe_phy_fw;
557 hw->phy.ops.read_reg = NULL;
558 hw->phy.ops.write_reg = NULL;
559 return ixgbe_get_phy_id_fw(hw);
560 }
561
562 /**
563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
564 * @hw: pointer to hardware structure
565 *
566 * Returns error code
567 */
568 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
569 {
570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
571
572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
574 }
575
576 /**
577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
578 * @hw: pointer to hardware structure
579 */
580 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
581 {
582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
583 s32 rc;
584 u16 i;
585
586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
587 return 0;
588
589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
591 return IXGBE_ERR_INVALID_LINK_SETTINGS;
592 }
593
594 switch (hw->fc.requested_mode) {
595 case ixgbe_fc_full:
596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
598 break;
599 case ixgbe_fc_rx_pause:
600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
602 break;
603 case ixgbe_fc_tx_pause:
604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
606 break;
607 default:
608 break;
609 }
610
611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
613 setup[0] |= ixgbe_fw_map[i].fw_speed;
614 }
615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
616
617 if (hw->phy.eee_speeds_advertised)
618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
619
620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
621 if (rc)
622 return rc;
623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
624 return IXGBE_ERR_OVERTEMP;
625 return 0;
626 }
627
628 /**
629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
630 * @hw: pointer to hardware structure
631 *
632 * Called at init time to set up flow control.
633 */
634 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
635 {
636 if (hw->fc.requested_mode == ixgbe_fc_default)
637 hw->fc.requested_mode = ixgbe_fc_full;
638
639 return ixgbe_setup_fw_link(hw);
640 }
641
642 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
643 * @hw: pointer to hardware structure
644 *
645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
646 * ixgbe_hw struct in order to set up EEPROM access.
647 **/
648 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
649 {
650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
651 u32 eec;
652 u16 eeprom_size;
653
654 if (eeprom->type == ixgbe_eeprom_uninitialized) {
655 eeprom->semaphore_delay = 10;
656 eeprom->type = ixgbe_flash;
657
658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
660 IXGBE_EEC_SIZE_SHIFT);
661 eeprom->word_size = BIT(eeprom_size +
662 IXGBE_EEPROM_WORD_SIZE_SHIFT);
663
664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
665 eeprom->type, eeprom->word_size);
666 }
667
668 return 0;
669 }
670
671 /**
672 * ixgbe_iosf_wait - Wait for IOSF command completion
673 * @hw: pointer to hardware structure
674 * @ctrl: pointer to location to receive final IOSF control value
675 *
676 * Return: failing status on timeout
677 *
678 * Note: ctrl can be NULL if the IOSF control register value is not needed
679 */
680 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
681 {
682 u32 i, command;
683
684 /* Check every 10 usec to see if the address cycle completed.
685 * The SB IOSF BUSY bit will clear when the operation is
686 * complete.
687 */
688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
691 break;
692 udelay(10);
693 }
694 if (ctrl)
695 *ctrl = command;
696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
697 hw_dbg(hw, "IOSF wait timed out\n");
698 return IXGBE_ERR_PHY;
699 }
700
701 return 0;
702 }
703
704 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
705 * IOSF device
706 * @hw: pointer to hardware structure
707 * @reg_addr: 32 bit PHY register to write
708 * @device_type: 3 bit device type
709 * @phy_data: Pointer to read data from the register
710 **/
711 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
712 u32 device_type, u32 *data)
713 {
714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
715 u32 command, error;
716 s32 ret;
717
718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
719 if (ret)
720 return ret;
721
722 ret = ixgbe_iosf_wait(hw, NULL);
723 if (ret)
724 goto out;
725
726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
728
729 /* Write IOSF control register */
730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
731
732 ret = ixgbe_iosf_wait(hw, &command);
733
734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
737 hw_dbg(hw, "Failed to read, error %x\n", error);
738 return IXGBE_ERR_PHY;
739 }
740
741 if (!ret)
742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
743
744 out:
745 hw->mac.ops.release_swfw_sync(hw, gssr);
746 return ret;
747 }
748
749 /**
750 * ixgbe_get_phy_token - Get the token for shared PHY access
751 * @hw: Pointer to hardware structure
752 */
753 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
754 {
755 struct ixgbe_hic_phy_token_req token_cmd;
756 s32 status;
757
758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
762 token_cmd.port_number = hw->bus.lan_id;
763 token_cmd.command_type = FW_PHY_TOKEN_REQ;
764 token_cmd.pad = 0;
765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
766 IXGBE_HI_COMMAND_TIMEOUT,
767 true);
768 if (status)
769 return status;
770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
771 return 0;
772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
773 return IXGBE_ERR_FW_RESP_INVALID;
774
775 return IXGBE_ERR_TOKEN_RETRY;
776 }
777
778 /**
779 * ixgbe_put_phy_token - Put the token for shared PHY access
780 * @hw: Pointer to hardware structure
781 */
782 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
783 {
784 struct ixgbe_hic_phy_token_req token_cmd;
785 s32 status;
786
787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
791 token_cmd.port_number = hw->bus.lan_id;
792 token_cmd.command_type = FW_PHY_TOKEN_REL;
793 token_cmd.pad = 0;
794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
795 IXGBE_HI_COMMAND_TIMEOUT,
796 true);
797 if (status)
798 return status;
799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
800 return 0;
801 return IXGBE_ERR_FW_RESP_INVALID;
802 }
803
804 /**
805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
806 * @hw: pointer to hardware structure
807 * @reg_addr: 32 bit PHY register to write
808 * @device_type: 3 bit device type
809 * @data: Data to write to the register
810 **/
811 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
812 __always_unused u32 device_type,
813 u32 data)
814 {
815 struct ixgbe_hic_internal_phy_req write_cmd;
816
817 memset(&write_cmd, 0, sizeof(write_cmd));
818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
821 write_cmd.port_number = hw->bus.lan_id;
822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
823 write_cmd.address = cpu_to_be16(reg_addr);
824 write_cmd.write_data = cpu_to_be32(data);
825
826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
827 IXGBE_HI_COMMAND_TIMEOUT, false);
828 }
829
830 /**
831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
832 * @hw: pointer to hardware structure
833 * @reg_addr: 32 bit PHY register to write
834 * @device_type: 3 bit device type
835 * @data: Pointer to read data from the register
836 **/
837 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
838 __always_unused u32 device_type,
839 u32 *data)
840 {
841 union {
842 struct ixgbe_hic_internal_phy_req cmd;
843 struct ixgbe_hic_internal_phy_resp rsp;
844 } hic;
845 s32 status;
846
847 memset(&hic, 0, sizeof(hic));
848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
851 hic.cmd.port_number = hw->bus.lan_id;
852 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
853 hic.cmd.address = cpu_to_be16(reg_addr);
854
855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
856 IXGBE_HI_COMMAND_TIMEOUT, true);
857
858 /* Extract the register value from the response. */
859 *data = be32_to_cpu(hic.rsp.read_data);
860
861 return status;
862 }
863
864 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
865 * @hw: pointer to hardware structure
866 * @offset: offset of word in the EEPROM to read
867 * @words: number of words
868 * @data: word(s) read from the EEPROM
869 *
870 * Reads a 16 bit word(s) from the EEPROM using the hostif.
871 **/
872 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
873 u16 offset, u16 words, u16 *data)
874 {
875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
876 struct ixgbe_hic_read_shadow_ram buffer;
877 u32 current_word = 0;
878 u16 words_to_read;
879 s32 status;
880 u32 i;
881
882 /* Take semaphore for the entire operation. */
883 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
884 if (status) {
885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
886 return status;
887 }
888
889 while (words) {
890 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
892 else
893 words_to_read = words;
894
895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
896 buffer.hdr.req.buf_lenh = 0;
897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
899
900 /* convert offset from words to bytes */
901 buffer.address = cpu_to_be32((offset + current_word) * 2);
902 buffer.length = cpu_to_be16(words_to_read * 2);
903
904 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
905 IXGBE_HI_COMMAND_TIMEOUT);
906 if (status) {
907 hw_dbg(hw, "Host interface command failed\n");
908 goto out;
909 }
910
911 for (i = 0; i < words_to_read; i++) {
912 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
913 2 * i;
914 u32 value = IXGBE_READ_REG(hw, reg);
915
916 data[current_word] = (u16)(value & 0xffff);
917 current_word++;
918 i++;
919 if (i < words_to_read) {
920 value >>= 16;
921 data[current_word] = (u16)(value & 0xffff);
922 current_word++;
923 }
924 }
925 words -= words_to_read;
926 }
927
928 out:
929 hw->mac.ops.release_swfw_sync(hw, mask);
930 return status;
931 }
932
933 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
934 * @hw: pointer to hardware structure
935 * @ptr: pointer offset in eeprom
936 * @size: size of section pointed by ptr, if 0 first word will be used as size
937 * @csum: address of checksum to update
938 *
939 * Returns error status for any failure
940 **/
941 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
942 u16 size, u16 *csum, u16 *buffer,
943 u32 buffer_size)
944 {
945 u16 buf[256];
946 s32 status;
947 u16 length, bufsz, i, start;
948 u16 *local_buffer;
949
950 bufsz = sizeof(buf) / sizeof(buf[0]);
951
952 /* Read a chunk at the pointer location */
953 if (!buffer) {
954 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
955 if (status) {
956 hw_dbg(hw, "Failed to read EEPROM image\n");
957 return status;
958 }
959 local_buffer = buf;
960 } else {
961 if (buffer_size < ptr)
962 return IXGBE_ERR_PARAM;
963 local_buffer = &buffer[ptr];
964 }
965
966 if (size) {
967 start = 0;
968 length = size;
969 } else {
970 start = 1;
971 length = local_buffer[0];
972
973 /* Skip pointer section if length is invalid. */
974 if (length == 0xFFFF || length == 0 ||
975 (ptr + length) >= hw->eeprom.word_size)
976 return 0;
977 }
978
979 if (buffer && ((u32)start + (u32)length > buffer_size))
980 return IXGBE_ERR_PARAM;
981
982 for (i = start; length; i++, length--) {
983 if (i == bufsz && !buffer) {
984 ptr += bufsz;
985 i = 0;
986 if (length < bufsz)
987 bufsz = length;
988
989 /* Read a chunk at the pointer location */
990 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
991 bufsz, buf);
992 if (status) {
993 hw_dbg(hw, "Failed to read EEPROM image\n");
994 return status;
995 }
996 }
997 *csum += local_buffer[i];
998 }
999 return 0;
1000 }
1001
1002 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1003 * @hw: pointer to hardware structure
1004 * @buffer: pointer to buffer containing calculated checksum
1005 * @buffer_size: size of buffer
1006 *
1007 * Returns a negative error code on error, or the 16-bit checksum
1008 **/
1009 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
1010 u32 buffer_size)
1011 {
1012 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1013 u16 *local_buffer;
1014 s32 status;
1015 u16 checksum = 0;
1016 u16 pointer, i, size;
1017
1018 hw->eeprom.ops.init_params(hw);
1019
1020 if (!buffer) {
1021 /* Read pointer area */
1022 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1023 IXGBE_EEPROM_LAST_WORD + 1,
1024 eeprom_ptrs);
1025 if (status) {
1026 hw_dbg(hw, "Failed to read EEPROM image\n");
1027 return status;
1028 }
1029 local_buffer = eeprom_ptrs;
1030 } else {
1031 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1032 return IXGBE_ERR_PARAM;
1033 local_buffer = buffer;
1034 }
1035
1036 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1037 * checksum word itself
1038 */
1039 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1040 if (i != IXGBE_EEPROM_CHECKSUM)
1041 checksum += local_buffer[i];
1042
1043 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1044 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1045 */
1046 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1047 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1048 continue;
1049
1050 pointer = local_buffer[i];
1051
1052 /* Skip pointer section if the pointer is invalid. */
1053 if (pointer == 0xFFFF || pointer == 0 ||
1054 pointer >= hw->eeprom.word_size)
1055 continue;
1056
1057 switch (i) {
1058 case IXGBE_PCIE_GENERAL_PTR:
1059 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1060 break;
1061 case IXGBE_PCIE_CONFIG0_PTR:
1062 case IXGBE_PCIE_CONFIG1_PTR:
1063 size = IXGBE_PCIE_CONFIG_SIZE;
1064 break;
1065 default:
1066 size = 0;
1067 break;
1068 }
1069
1070 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1071 buffer, buffer_size);
1072 if (status)
1073 return status;
1074 }
1075
1076 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1077
1078 return (s32)checksum;
1079 }
1080
1081 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1082 * @hw: pointer to hardware structure
1083 *
1084 * Returns a negative error code on error, or the 16-bit checksum
1085 **/
1086 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1087 {
1088 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1089 }
1090
1091 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1092 * @hw: pointer to hardware structure
1093 * @offset: offset of word in the EEPROM to read
1094 * @data: word read from the EEPROM
1095 *
1096 * Reads a 16 bit word from the EEPROM using the hostif.
1097 **/
1098 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1099 {
1100 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1101 struct ixgbe_hic_read_shadow_ram buffer;
1102 s32 status;
1103
1104 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1105 buffer.hdr.req.buf_lenh = 0;
1106 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1107 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1108
1109 /* convert offset from words to bytes */
1110 buffer.address = cpu_to_be32(offset * 2);
1111 /* one word */
1112 buffer.length = cpu_to_be16(sizeof(u16));
1113
1114 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1115 if (status)
1116 return status;
1117
1118 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1119 IXGBE_HI_COMMAND_TIMEOUT);
1120 if (!status) {
1121 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1122 FW_NVM_DATA_OFFSET);
1123 }
1124
1125 hw->mac.ops.release_swfw_sync(hw, mask);
1126 return status;
1127 }
1128
1129 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1130 * @hw: pointer to hardware structure
1131 * @checksum_val: calculated checksum
1132 *
1133 * Performs checksum calculation and validates the EEPROM checksum. If the
1134 * caller does not need checksum_val, the value can be NULL.
1135 **/
1136 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1137 u16 *checksum_val)
1138 {
1139 s32 status;
1140 u16 checksum;
1141 u16 read_checksum = 0;
1142
1143 /* Read the first word from the EEPROM. If this times out or fails, do
1144 * not continue or we could be in for a very long wait while every
1145 * EEPROM read fails
1146 */
1147 status = hw->eeprom.ops.read(hw, 0, &checksum);
1148 if (status) {
1149 hw_dbg(hw, "EEPROM read failed\n");
1150 return status;
1151 }
1152
1153 status = hw->eeprom.ops.calc_checksum(hw);
1154 if (status < 0)
1155 return status;
1156
1157 checksum = (u16)(status & 0xffff);
1158
1159 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1160 &read_checksum);
1161 if (status)
1162 return status;
1163
1164 /* Verify read checksum from EEPROM is the same as
1165 * calculated checksum
1166 */
1167 if (read_checksum != checksum) {
1168 status = IXGBE_ERR_EEPROM_CHECKSUM;
1169 hw_dbg(hw, "Invalid EEPROM checksum");
1170 }
1171
1172 /* If the user cares, return the calculated checksum */
1173 if (checksum_val)
1174 *checksum_val = checksum;
1175
1176 return status;
1177 }
1178
1179 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1180 * @hw: pointer to hardware structure
1181 * @offset: offset of word in the EEPROM to write
1182 * @data: word write to the EEPROM
1183 *
1184 * Write a 16 bit word to the EEPROM using the hostif.
1185 **/
1186 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1187 u16 data)
1188 {
1189 s32 status;
1190 struct ixgbe_hic_write_shadow_ram buffer;
1191
1192 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1193 buffer.hdr.req.buf_lenh = 0;
1194 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1195 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1196
1197 /* one word */
1198 buffer.length = cpu_to_be16(sizeof(u16));
1199 buffer.data = data;
1200 buffer.address = cpu_to_be32(offset * 2);
1201
1202 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1203 IXGBE_HI_COMMAND_TIMEOUT, false);
1204 return status;
1205 }
1206
1207 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1208 * @hw: pointer to hardware structure
1209 * @offset: offset of word in the EEPROM to write
1210 * @data: word write to the EEPROM
1211 *
1212 * Write a 16 bit word to the EEPROM using the hostif.
1213 **/
1214 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1215 {
1216 s32 status = 0;
1217
1218 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1219 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1220 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1221 } else {
1222 hw_dbg(hw, "write ee hostif failed to get semaphore");
1223 status = IXGBE_ERR_SWFW_SYNC;
1224 }
1225
1226 return status;
1227 }
1228
1229 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1230 * @hw: pointer to hardware structure
1231 *
1232 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1233 **/
1234 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1235 {
1236 s32 status = 0;
1237 union ixgbe_hic_hdr2 buffer;
1238
1239 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1240 buffer.req.buf_lenh = 0;
1241 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1242 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1243
1244 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1245 IXGBE_HI_COMMAND_TIMEOUT, false);
1246 return status;
1247 }
1248
1249 /**
1250 * ixgbe_get_bus_info_X550em - Set PCI bus info
1251 * @hw: pointer to hardware structure
1252 *
1253 * Sets bus link width and speed to unknown because X550em is
1254 * not a PCI device.
1255 **/
1256 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1257 {
1258 hw->bus.type = ixgbe_bus_type_internal;
1259 hw->bus.width = ixgbe_bus_width_unknown;
1260 hw->bus.speed = ixgbe_bus_speed_unknown;
1261
1262 hw->mac.ops.set_lan_id(hw);
1263
1264 return 0;
1265 }
1266
1267 /** ixgbe_disable_rx_x550 - Disable RX unit
1268 *
1269 * Enables the Rx DMA unit for x550
1270 **/
1271 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1272 {
1273 u32 rxctrl, pfdtxgswc;
1274 s32 status;
1275 struct ixgbe_hic_disable_rxen fw_cmd;
1276
1277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1278 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1280 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1281 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1282 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1283 hw->mac.set_lben = true;
1284 } else {
1285 hw->mac.set_lben = false;
1286 }
1287
1288 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1289 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1290 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291 fw_cmd.port_number = hw->bus.lan_id;
1292
1293 status = ixgbe_host_interface_command(hw, &fw_cmd,
1294 sizeof(struct ixgbe_hic_disable_rxen),
1295 IXGBE_HI_COMMAND_TIMEOUT, true);
1296
1297 /* If we fail - disable RX using register write */
1298 if (status) {
1299 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1300 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1301 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1303 }
1304 }
1305 }
1306 }
1307
1308 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1309 * @hw: pointer to hardware structure
1310 *
1311 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1312 * checksum and updates the EEPROM and instructs the hardware to update
1313 * the flash.
1314 **/
1315 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1316 {
1317 s32 status;
1318 u16 checksum = 0;
1319
1320 /* Read the first word from the EEPROM. If this times out or fails, do
1321 * not continue or we could be in for a very long wait while every
1322 * EEPROM read fails
1323 */
1324 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1325 if (status) {
1326 hw_dbg(hw, "EEPROM read failed\n");
1327 return status;
1328 }
1329
1330 status = ixgbe_calc_eeprom_checksum_X550(hw);
1331 if (status < 0)
1332 return status;
1333
1334 checksum = (u16)(status & 0xffff);
1335
1336 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1337 checksum);
1338 if (status)
1339 return status;
1340
1341 status = ixgbe_update_flash_X550(hw);
1342
1343 return status;
1344 }
1345
1346 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1347 * @hw: pointer to hardware structure
1348 * @offset: offset of word in the EEPROM to write
1349 * @words: number of words
1350 * @data: word(s) write to the EEPROM
1351 *
1352 *
1353 * Write a 16 bit word(s) to the EEPROM using the hostif.
1354 **/
1355 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1356 u16 offset, u16 words,
1357 u16 *data)
1358 {
1359 s32 status = 0;
1360 u32 i = 0;
1361
1362 /* Take semaphore for the entire operation. */
1363 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1364 if (status) {
1365 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1366 return status;
1367 }
1368
1369 for (i = 0; i < words; i++) {
1370 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1371 data[i]);
1372 if (status) {
1373 hw_dbg(hw, "Eeprom buffered write failed\n");
1374 break;
1375 }
1376 }
1377
1378 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1379
1380 return status;
1381 }
1382
1383 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1384 * IOSF device
1385 *
1386 * @hw: pointer to hardware structure
1387 * @reg_addr: 32 bit PHY register to write
1388 * @device_type: 3 bit device type
1389 * @data: Data to write to the register
1390 **/
1391 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1392 u32 device_type, u32 data)
1393 {
1394 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1395 u32 command, error;
1396 s32 ret;
1397
1398 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1399 if (ret)
1400 return ret;
1401
1402 ret = ixgbe_iosf_wait(hw, NULL);
1403 if (ret)
1404 goto out;
1405
1406 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1407 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1408
1409 /* Write IOSF control register */
1410 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1411
1412 /* Write IOSF data register */
1413 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1414
1415 ret = ixgbe_iosf_wait(hw, &command);
1416
1417 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1418 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1419 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1420 hw_dbg(hw, "Failed to write, error %x\n", error);
1421 return IXGBE_ERR_PHY;
1422 }
1423
1424 out:
1425 hw->mac.ops.release_swfw_sync(hw, gssr);
1426 return ret;
1427 }
1428
1429 /**
1430 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1431 * @hw: pointer to hardware structure
1432 *
1433 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1434 **/
1435 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1436 {
1437 s32 status;
1438 u32 reg_val;
1439
1440 /* Disable training protocol FSM. */
1441 status = ixgbe_read_iosf_sb_reg_x550(hw,
1442 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1443 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1444 if (status)
1445 return status;
1446
1447 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1448 status = ixgbe_write_iosf_sb_reg_x550(hw,
1449 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1450 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1451 if (status)
1452 return status;
1453
1454 /* Disable Flex from training TXFFE. */
1455 status = ixgbe_read_iosf_sb_reg_x550(hw,
1456 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1457 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1458 if (status)
1459 return status;
1460
1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1464 status = ixgbe_write_iosf_sb_reg_x550(hw,
1465 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1466 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1467 if (status)
1468 return status;
1469
1470 status = ixgbe_read_iosf_sb_reg_x550(hw,
1471 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1472 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1473 if (status)
1474 return status;
1475
1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1479 status = ixgbe_write_iosf_sb_reg_x550(hw,
1480 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1482 if (status)
1483 return status;
1484
1485 /* Enable override for coefficients. */
1486 status = ixgbe_read_iosf_sb_reg_x550(hw,
1487 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1488 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1489 if (status)
1490 return status;
1491
1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1496 status = ixgbe_write_iosf_sb_reg_x550(hw,
1497 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1498 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1499 return status;
1500 }
1501
1502 /**
1503 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1504 * internal PHY
1505 * @hw: pointer to hardware structure
1506 **/
1507 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1508 {
1509 s32 status;
1510 u32 link_ctrl;
1511
1512 /* Restart auto-negotiation. */
1513 status = hw->mac.ops.read_iosf_sb_reg(hw,
1514 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1515 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1516
1517 if (status) {
1518 hw_dbg(hw, "Auto-negotiation did not complete\n");
1519 return status;
1520 }
1521
1522 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1523 status = hw->mac.ops.write_iosf_sb_reg(hw,
1524 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1525 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1526
1527 if (hw->mac.type == ixgbe_mac_x550em_a) {
1528 u32 flx_mask_st20;
1529
1530 /* Indicate to FW that AN restart has been asserted */
1531 status = hw->mac.ops.read_iosf_sb_reg(hw,
1532 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1533 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1534
1535 if (status) {
1536 hw_dbg(hw, "Auto-negotiation did not complete\n");
1537 return status;
1538 }
1539
1540 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1541 status = hw->mac.ops.write_iosf_sb_reg(hw,
1542 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1543 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1544 }
1545
1546 return status;
1547 }
1548
1549 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1550 * @hw: pointer to hardware structure
1551 * @speed: the link speed to force
1552 *
1553 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1554 * internal and external PHY at a specific speed, without autonegotiation.
1555 **/
1556 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1557 {
1558 struct ixgbe_mac_info *mac = &hw->mac;
1559 s32 status;
1560 u32 reg_val;
1561
1562 /* iXFI is only supported with X552 */
1563 if (mac->type != ixgbe_mac_X550EM_x)
1564 return IXGBE_ERR_LINK_SETUP;
1565
1566 /* Disable AN and force speed to 10G Serial. */
1567 status = ixgbe_read_iosf_sb_reg_x550(hw,
1568 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1569 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1570 if (status)
1571 return status;
1572
1573 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1574 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1575
1576 /* Select forced link speed for internal PHY. */
1577 switch (*speed) {
1578 case IXGBE_LINK_SPEED_10GB_FULL:
1579 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1580 break;
1581 case IXGBE_LINK_SPEED_1GB_FULL:
1582 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1583 break;
1584 default:
1585 /* Other link speeds are not supported by internal KR PHY. */
1586 return IXGBE_ERR_LINK_SETUP;
1587 }
1588
1589 status = ixgbe_write_iosf_sb_reg_x550(hw,
1590 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1591 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1592 if (status)
1593 return status;
1594
1595 /* Additional configuration needed for x550em_x */
1596 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1597 status = ixgbe_setup_ixfi_x550em_x(hw);
1598 if (status)
1599 return status;
1600 }
1601
1602 /* Toggle port SW reset by AN reset. */
1603 status = ixgbe_restart_an_internal_phy_x550em(hw);
1604
1605 return status;
1606 }
1607
1608 /**
1609 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1610 * @hw: pointer to hardware structure
1611 * @linear: true if SFP module is linear
1612 */
1613 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1614 {
1615 switch (hw->phy.sfp_type) {
1616 case ixgbe_sfp_type_not_present:
1617 return IXGBE_ERR_SFP_NOT_PRESENT;
1618 case ixgbe_sfp_type_da_cu_core0:
1619 case ixgbe_sfp_type_da_cu_core1:
1620 *linear = true;
1621 break;
1622 case ixgbe_sfp_type_srlr_core0:
1623 case ixgbe_sfp_type_srlr_core1:
1624 case ixgbe_sfp_type_da_act_lmt_core0:
1625 case ixgbe_sfp_type_da_act_lmt_core1:
1626 case ixgbe_sfp_type_1g_sx_core0:
1627 case ixgbe_sfp_type_1g_sx_core1:
1628 case ixgbe_sfp_type_1g_lx_core0:
1629 case ixgbe_sfp_type_1g_lx_core1:
1630 *linear = false;
1631 break;
1632 case ixgbe_sfp_type_unknown:
1633 case ixgbe_sfp_type_1g_cu_core0:
1634 case ixgbe_sfp_type_1g_cu_core1:
1635 default:
1636 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1637 }
1638
1639 return 0;
1640 }
1641
1642 /**
1643 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1644 * @hw: pointer to hardware structure
1645 *
1646 * Configures the extern PHY and the integrated KR PHY for SFP support.
1647 */
1648 static s32
1649 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1650 ixgbe_link_speed speed,
1651 __always_unused bool autoneg_wait_to_complete)
1652 {
1653 s32 status;
1654 u16 reg_slice, reg_val;
1655 bool setup_linear = false;
1656
1657 /* Check if SFP module is supported and linear */
1658 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1659
1660 /* If no SFP module present, then return success. Return success since
1661 * there is no reason to configure CS4227 and SFP not present error is
1662 * not accepted in the setup MAC link flow.
1663 */
1664 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1665 return 0;
1666
1667 if (status)
1668 return status;
1669
1670 /* Configure internal PHY for KR/KX. */
1671 ixgbe_setup_kr_speed_x550em(hw, speed);
1672
1673 /* Configure CS4227 LINE side to proper mode. */
1674 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1675 if (setup_linear)
1676 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1677 else
1678 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1679
1680 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1681 reg_val);
1682
1683 return status;
1684 }
1685
1686 /**
1687 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1688 * @hw: pointer to hardware structure
1689 * @speed: the link speed to force
1690 *
1691 * Configures the integrated PHY for native SFI mode. Used to connect the
1692 * internal PHY directly to an SFP cage, without autonegotiation.
1693 **/
1694 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1695 {
1696 struct ixgbe_mac_info *mac = &hw->mac;
1697 s32 status;
1698 u32 reg_val;
1699
1700 /* Disable all AN and force speed to 10G Serial. */
1701 status = mac->ops.read_iosf_sb_reg(hw,
1702 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1703 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1704 if (status)
1705 return status;
1706
1707 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1708 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1711
1712 /* Select forced link speed for internal PHY. */
1713 switch (*speed) {
1714 case IXGBE_LINK_SPEED_10GB_FULL:
1715 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1716 break;
1717 case IXGBE_LINK_SPEED_1GB_FULL:
1718 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1719 break;
1720 default:
1721 /* Other link speeds are not supported by internal PHY. */
1722 return IXGBE_ERR_LINK_SETUP;
1723 }
1724
1725 status = mac->ops.write_iosf_sb_reg(hw,
1726 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1727 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1728
1729 /* Toggle port SW reset by AN reset. */
1730 status = ixgbe_restart_an_internal_phy_x550em(hw);
1731
1732 return status;
1733 }
1734
1735 /**
1736 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1737 * @hw: pointer to hardware structure
1738 *
1739 * Configure the the integrated PHY for native SFP support.
1740 */
1741 static s32
1742 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1743 __always_unused bool autoneg_wait_to_complete)
1744 {
1745 bool setup_linear = false;
1746 u32 reg_phy_int;
1747 s32 ret_val;
1748
1749 /* Check if SFP module is supported and linear */
1750 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1751
1752 /* If no SFP module present, then return success. Return success since
1753 * SFP not present error is not excepted in the setup MAC link flow.
1754 */
1755 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1756 return 0;
1757
1758 if (ret_val)
1759 return ret_val;
1760
1761 /* Configure internal PHY for native SFI based on module type */
1762 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1763 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1764 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
1765 if (ret_val)
1766 return ret_val;
1767
1768 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1769 if (!setup_linear)
1770 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1771
1772 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1773 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1774 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1775 if (ret_val)
1776 return ret_val;
1777
1778 /* Setup SFI internal link. */
1779 return ixgbe_setup_sfi_x550a(hw, &speed);
1780 }
1781
1782 /**
1783 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1784 * @hw: pointer to hardware structure
1785 *
1786 * Configure the the integrated PHY for SFP support.
1787 */
1788 static s32
1789 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1790 __always_unused bool autoneg_wait_to_complete)
1791 {
1792 u32 reg_slice, slice_offset;
1793 bool setup_linear = false;
1794 u16 reg_phy_ext;
1795 s32 ret_val;
1796
1797 /* Check if SFP module is supported and linear */
1798 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1799
1800 /* If no SFP module present, then return success. Return success since
1801 * SFP not present error is not excepted in the setup MAC link flow.
1802 */
1803 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1804 return 0;
1805
1806 if (ret_val)
1807 return ret_val;
1808
1809 /* Configure internal PHY for KR/KX. */
1810 ixgbe_setup_kr_speed_x550em(hw, speed);
1811
1812 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1813 return IXGBE_ERR_PHY_ADDR_INVALID;
1814
1815 /* Get external PHY SKU id */
1816 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1817 IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1818 if (ret_val)
1819 return ret_val;
1820
1821 /* When configuring quad port CS4223, the MAC instance is part
1822 * of the slice offset.
1823 */
1824 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1825 slice_offset = (hw->bus.lan_id +
1826 (hw->bus.instance_id << 1)) << 12;
1827 else
1828 slice_offset = hw->bus.lan_id << 12;
1829
1830 /* Configure CS4227/CS4223 LINE side to proper mode. */
1831 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1832
1833 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1834 IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1835 if (ret_val)
1836 return ret_val;
1837
1838 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1839 (IXGBE_CS4227_EDC_MODE_SR << 1));
1840
1841 if (setup_linear)
1842 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1843 else
1844 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1845
1846 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1847 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1848 if (ret_val)
1849 return ret_val;
1850
1851 /* Flush previous write with a read */
1852 return hw->phy.ops.read_reg(hw, reg_slice,
1853 IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1854 }
1855
1856 /**
1857 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1858 * @hw: pointer to hardware structure
1859 * @speed: new link speed
1860 * @autoneg_wait_to_complete: true when waiting for completion is needed
1861 *
1862 * Setup internal/external PHY link speed based on link speed, then set
1863 * external PHY auto advertised link speed.
1864 *
1865 * Returns error status for any failure
1866 **/
1867 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1868 ixgbe_link_speed speed,
1869 bool autoneg_wait)
1870 {
1871 s32 status;
1872 ixgbe_link_speed force_speed;
1873
1874 /* Setup internal/external PHY link speed to iXFI (10G), unless
1875 * only 1G is auto advertised then setup KX link.
1876 */
1877 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1878 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1879 else
1880 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1881
1882 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1883 */
1884 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1885 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1886 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1887
1888 if (status)
1889 return status;
1890 }
1891
1892 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1893 }
1894
1895 /** ixgbe_check_link_t_X550em - Determine link and speed status
1896 * @hw: pointer to hardware structure
1897 * @speed: pointer to link speed
1898 * @link_up: true when link is up
1899 * @link_up_wait_to_complete: bool used to wait for link up or not
1900 *
1901 * Check that both the MAC and X557 external PHY have link.
1902 **/
1903 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1904 ixgbe_link_speed *speed,
1905 bool *link_up,
1906 bool link_up_wait_to_complete)
1907 {
1908 u32 status;
1909 u16 i, autoneg_status;
1910
1911 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1912 return IXGBE_ERR_CONFIG;
1913
1914 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1915 link_up_wait_to_complete);
1916
1917 /* If check link fails or MAC link is not up, then return */
1918 if (status || !(*link_up))
1919 return status;
1920
1921 /* MAC link is up, so check external PHY link.
1922 * Link status is latching low, and can only be used to detect link
1923 * drop, and not the current status of the link without performing
1924 * back-to-back reads.
1925 */
1926 for (i = 0; i < 2; i++) {
1927 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1928 &autoneg_status);
1929
1930 if (status)
1931 return status;
1932 }
1933
1934 /* If external PHY link is not up, then indicate link not up */
1935 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1936 *link_up = false;
1937
1938 return 0;
1939 }
1940
1941 /**
1942 * ixgbe_setup_sgmii - Set up link for sgmii
1943 * @hw: pointer to hardware structure
1944 */
1945 static s32
1946 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1947 __always_unused bool autoneg_wait_to_complete)
1948 {
1949 struct ixgbe_mac_info *mac = &hw->mac;
1950 u32 lval, sval, flx_val;
1951 s32 rc;
1952
1953 rc = mac->ops.read_iosf_sb_reg(hw,
1954 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1955 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1956 if (rc)
1957 return rc;
1958
1959 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1960 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1961 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1962 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1963 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1964 rc = mac->ops.write_iosf_sb_reg(hw,
1965 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1966 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1967 if (rc)
1968 return rc;
1969
1970 rc = mac->ops.read_iosf_sb_reg(hw,
1971 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1972 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1973 if (rc)
1974 return rc;
1975
1976 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1977 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1978 rc = mac->ops.write_iosf_sb_reg(hw,
1979 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1980 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1981 if (rc)
1982 return rc;
1983
1984 rc = mac->ops.read_iosf_sb_reg(hw,
1985 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1986 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1987 if (rc)
1988 return rc;
1989
1990 rc = mac->ops.read_iosf_sb_reg(hw,
1991 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1992 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1993 if (rc)
1994 return rc;
1995
1996 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1997 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1998 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1999 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2000 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2001
2002 rc = mac->ops.write_iosf_sb_reg(hw,
2003 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2004 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2005 if (rc)
2006 return rc;
2007
2008 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2009 return rc;
2010 }
2011
2012 /**
2013 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2014 * @hw: pointer to hardware structure
2015 */
2016 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2017 bool autoneg_wait)
2018 {
2019 struct ixgbe_mac_info *mac = &hw->mac;
2020 u32 lval, sval, flx_val;
2021 s32 rc;
2022
2023 rc = mac->ops.read_iosf_sb_reg(hw,
2024 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2025 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2026 if (rc)
2027 return rc;
2028
2029 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2030 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2031 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2032 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2033 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2034 rc = mac->ops.write_iosf_sb_reg(hw,
2035 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2036 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2037 if (rc)
2038 return rc;
2039
2040 rc = mac->ops.read_iosf_sb_reg(hw,
2041 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2042 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2043 if (rc)
2044 return rc;
2045
2046 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2047 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2048 rc = mac->ops.write_iosf_sb_reg(hw,
2049 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2050 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2051 if (rc)
2052 return rc;
2053
2054 rc = mac->ops.write_iosf_sb_reg(hw,
2055 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2056 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2057 if (rc)
2058 return rc;
2059
2060 rc = mac->ops.read_iosf_sb_reg(hw,
2061 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2062 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2063 if (rc)
2064 return rc;
2065
2066 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2067 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2068 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2069 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2070 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2071
2072 rc = mac->ops.write_iosf_sb_reg(hw,
2073 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2074 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2075 if (rc)
2076 return rc;
2077
2078 ixgbe_restart_an_internal_phy_x550em(hw);
2079
2080 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2081 }
2082
2083 /**
2084 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2085 * @hw: pointer to hardware structure
2086 *
2087 * Enable flow control according to IEEE clause 37.
2088 */
2089 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2090 {
2091 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2092 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2093 ixgbe_link_speed speed;
2094 bool link_up;
2095
2096 /* AN should have completed when the cable was plugged in.
2097 * Look for reasons to bail out. Bail out if:
2098 * - FC autoneg is disabled, or if
2099 * - link is not up.
2100 */
2101 if (hw->fc.disable_fc_autoneg)
2102 goto out;
2103
2104 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2105 if (!link_up)
2106 goto out;
2107
2108 /* Check if auto-negotiation has completed */
2109 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2110 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2111 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2112 goto out;
2113 }
2114
2115 /* Negotiate the flow control */
2116 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2117 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2118 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2119 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2120 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2121
2122 out:
2123 if (!status) {
2124 hw->fc.fc_was_autonegged = true;
2125 } else {
2126 hw->fc.fc_was_autonegged = false;
2127 hw->fc.current_mode = hw->fc.requested_mode;
2128 }
2129 }
2130
2131 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2132 * @hw: pointer to hardware structure
2133 **/
2134 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2135 {
2136 struct ixgbe_mac_info *mac = &hw->mac;
2137
2138 switch (mac->ops.get_media_type(hw)) {
2139 case ixgbe_media_type_fiber:
2140 mac->ops.setup_fc = NULL;
2141 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2142 break;
2143 case ixgbe_media_type_copper:
2144 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2145 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2146 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2147 break;
2148 }
2149 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2150 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2151 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2152 mac->ops.check_link = ixgbe_check_mac_link_generic;
2153 break;
2154 case ixgbe_media_type_backplane:
2155 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2156 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2157 break;
2158 default:
2159 break;
2160 }
2161 }
2162
2163 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2164 * @hw: pointer to hardware structure
2165 **/
2166 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2167 {
2168 struct ixgbe_mac_info *mac = &hw->mac;
2169
2170 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2171
2172 switch (mac->ops.get_media_type(hw)) {
2173 case ixgbe_media_type_fiber:
2174 /* CS4227 does not support autoneg, so disable the laser control
2175 * functions for SFP+ fiber
2176 */
2177 mac->ops.disable_tx_laser = NULL;
2178 mac->ops.enable_tx_laser = NULL;
2179 mac->ops.flap_tx_laser = NULL;
2180 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2181 switch (hw->device_id) {
2182 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2183 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2184 break;
2185 case IXGBE_DEV_ID_X550EM_A_SFP:
2186 mac->ops.setup_mac_link =
2187 ixgbe_setup_mac_link_sfp_x550a;
2188 break;
2189 default:
2190 mac->ops.setup_mac_link =
2191 ixgbe_setup_mac_link_sfp_x550em;
2192 break;
2193 }
2194 mac->ops.set_rate_select_speed =
2195 ixgbe_set_soft_rate_select_speed;
2196 break;
2197 case ixgbe_media_type_copper:
2198 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2199 break;
2200 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2201 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2202 mac->ops.check_link = ixgbe_check_link_t_X550em;
2203 break;
2204 case ixgbe_media_type_backplane:
2205 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2206 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2207 mac->ops.setup_link = ixgbe_setup_sgmii;
2208 break;
2209 default:
2210 break;
2211 }
2212
2213 /* Additional modification for X550em_a devices */
2214 if (hw->mac.type == ixgbe_mac_x550em_a)
2215 ixgbe_init_mac_link_ops_X550em_a(hw);
2216 }
2217
2218 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2219 * @hw: pointer to hardware structure
2220 */
2221 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2222 {
2223 s32 status;
2224 bool linear;
2225
2226 /* Check if SFP module is supported */
2227 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2228 if (status)
2229 return status;
2230
2231 ixgbe_init_mac_link_ops_X550em(hw);
2232 hw->phy.ops.reset = NULL;
2233
2234 return 0;
2235 }
2236
2237 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2238 * @hw: pointer to hardware structure
2239 * @speed: pointer to link speed
2240 * @autoneg: true when autoneg or autotry is enabled
2241 **/
2242 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2243 ixgbe_link_speed *speed,
2244 bool *autoneg)
2245 {
2246 if (hw->phy.type == ixgbe_phy_fw) {
2247 *autoneg = true;
2248 *speed = hw->phy.speeds_supported;
2249 return 0;
2250 }
2251
2252 /* SFP */
2253 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2254 /* CS4227 SFP must not enable auto-negotiation */
2255 *autoneg = false;
2256
2257 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2258 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
2259 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2260 return 0;
2261 }
2262
2263 /* Link capabilities are based on SFP */
2264 if (hw->phy.multispeed_fiber)
2265 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2266 IXGBE_LINK_SPEED_1GB_FULL;
2267 else
2268 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2269 } else {
2270 switch (hw->phy.type) {
2271 case ixgbe_phy_x550em_kx4:
2272 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2273 IXGBE_LINK_SPEED_2_5GB_FULL |
2274 IXGBE_LINK_SPEED_10GB_FULL;
2275 break;
2276 case ixgbe_phy_x550em_xfi:
2277 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2278 IXGBE_LINK_SPEED_10GB_FULL;
2279 break;
2280 case ixgbe_phy_ext_1g_t:
2281 case ixgbe_phy_sgmii:
2282 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2283 break;
2284 case ixgbe_phy_x550em_kr:
2285 if (hw->mac.type == ixgbe_mac_x550em_a) {
2286 /* check different backplane modes */
2287 if (hw->phy.nw_mng_if_sel &
2288 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2289 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2290 break;
2291 } else if (hw->device_id ==
2292 IXGBE_DEV_ID_X550EM_A_KR_L) {
2293 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2294 break;
2295 }
2296 }
2297 /* fall through */
2298 default:
2299 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2300 IXGBE_LINK_SPEED_1GB_FULL;
2301 break;
2302 }
2303 *autoneg = true;
2304 }
2305 return 0;
2306 }
2307
2308 /**
2309 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2310 * @hw: pointer to hardware structure
2311 * @lsc: pointer to boolean flag which indicates whether external Base T
2312 * PHY interrupt is lsc
2313 *
2314 * Determime if external Base T PHY interrupt cause is high temperature
2315 * failure alarm or link status change.
2316 *
2317 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2318 * failure alarm, else return PHY access status.
2319 **/
2320 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2321 {
2322 u32 status;
2323 u16 reg;
2324
2325 *lsc = false;
2326
2327 /* Vendor alarm triggered */
2328 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2329 MDIO_MMD_VEND1,
2330 &reg);
2331
2332 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2333 return status;
2334
2335 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2336 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2337 MDIO_MMD_VEND1,
2338 &reg);
2339
2340 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2341 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2342 return status;
2343
2344 /* Global alarm triggered */
2345 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2346 MDIO_MMD_VEND1,
2347 &reg);
2348
2349 if (status)
2350 return status;
2351
2352 /* If high temperature failure, then return over temp error and exit */
2353 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2354 /* power down the PHY in case the PHY FW didn't already */
2355 ixgbe_set_copper_phy_power(hw, false);
2356 return IXGBE_ERR_OVERTEMP;
2357 }
2358 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2359 /* device fault alarm triggered */
2360 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2361 MDIO_MMD_VEND1,
2362 &reg);
2363 if (status)
2364 return status;
2365
2366 /* if device fault was due to high temp alarm handle and exit */
2367 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2368 /* power down the PHY in case the PHY FW didn't */
2369 ixgbe_set_copper_phy_power(hw, false);
2370 return IXGBE_ERR_OVERTEMP;
2371 }
2372 }
2373
2374 /* Vendor alarm 2 triggered */
2375 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2376 MDIO_MMD_AN, &reg);
2377
2378 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2379 return status;
2380
2381 /* link connect/disconnect event occurred */
2382 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2383 MDIO_MMD_AN, &reg);
2384
2385 if (status)
2386 return status;
2387
2388 /* Indicate LSC */
2389 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2390 *lsc = true;
2391
2392 return 0;
2393 }
2394
2395 /**
2396 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2397 * @hw: pointer to hardware structure
2398 *
2399 * Enable link status change and temperature failure alarm for the external
2400 * Base T PHY
2401 *
2402 * Returns PHY access status
2403 **/
2404 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2405 {
2406 u32 status;
2407 u16 reg;
2408 bool lsc;
2409
2410 /* Clear interrupt flags */
2411 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2412
2413 /* Enable link status change alarm */
2414
2415 /* Enable the LASI interrupts on X552 devices to receive notifications
2416 * of the link configurations of the external PHY and correspondingly
2417 * support the configuration of the internal iXFI link, since iXFI does
2418 * not support auto-negotiation. This is not required for X553 devices
2419 * having KR support, which performs auto-negotiations and which is used
2420 * as the internal link to the external PHY. Hence adding a check here
2421 * to avoid enabling LASI interrupts for X553 devices.
2422 */
2423 if (hw->mac.type != ixgbe_mac_x550em_a) {
2424 status = hw->phy.ops.read_reg(hw,
2425 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2426 MDIO_MMD_AN, &reg);
2427 if (status)
2428 return status;
2429
2430 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2431
2432 status = hw->phy.ops.write_reg(hw,
2433 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2434 MDIO_MMD_AN, reg);
2435 if (status)
2436 return status;
2437 }
2438
2439 /* Enable high temperature failure and global fault alarms */
2440 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2441 MDIO_MMD_VEND1,
2442 &reg);
2443 if (status)
2444 return status;
2445
2446 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2447 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2448
2449 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2450 MDIO_MMD_VEND1,
2451 reg);
2452 if (status)
2453 return status;
2454
2455 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2456 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2457 MDIO_MMD_VEND1,
2458 &reg);
2459 if (status)
2460 return status;
2461
2462 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2463 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2464
2465 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2466 MDIO_MMD_VEND1,
2467 reg);
2468 if (status)
2469 return status;
2470
2471 /* Enable chip-wide vendor alarm */
2472 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2473 MDIO_MMD_VEND1,
2474 &reg);
2475 if (status)
2476 return status;
2477
2478 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2479
2480 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2481 MDIO_MMD_VEND1,
2482 reg);
2483
2484 return status;
2485 }
2486
2487 /**
2488 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2489 * @hw: pointer to hardware structure
2490 *
2491 * Handle external Base T PHY interrupt. If high temperature
2492 * failure alarm then return error, else if link status change
2493 * then setup internal/external PHY link
2494 *
2495 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2496 * failure alarm, else return PHY access status.
2497 **/
2498 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2499 {
2500 struct ixgbe_phy_info *phy = &hw->phy;
2501 bool lsc;
2502 u32 status;
2503
2504 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2505 if (status)
2506 return status;
2507
2508 if (lsc && phy->ops.setup_internal_link)
2509 return phy->ops.setup_internal_link(hw);
2510
2511 return 0;
2512 }
2513
2514 /**
2515 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2516 * @hw: pointer to hardware structure
2517 * @speed: link speed
2518 *
2519 * Configures the integrated KR PHY.
2520 **/
2521 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2522 ixgbe_link_speed speed)
2523 {
2524 s32 status;
2525 u32 reg_val;
2526
2527 status = hw->mac.ops.read_iosf_sb_reg(hw,
2528 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2529 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2530 if (status)
2531 return status;
2532
2533 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2534 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2535 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2536
2537 /* Advertise 10G support. */
2538 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2539 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2540
2541 /* Advertise 1G support. */
2542 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2543 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2544
2545 status = hw->mac.ops.write_iosf_sb_reg(hw,
2546 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2547 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2548
2549 if (hw->mac.type == ixgbe_mac_x550em_a) {
2550 /* Set lane mode to KR auto negotiation */
2551 status = hw->mac.ops.read_iosf_sb_reg(hw,
2552 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2553 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2554
2555 if (status)
2556 return status;
2557
2558 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2559 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2560 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2561 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2562 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2563
2564 status = hw->mac.ops.write_iosf_sb_reg(hw,
2565 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2566 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2567 }
2568
2569 return ixgbe_restart_an_internal_phy_x550em(hw);
2570 }
2571
2572 /**
2573 * ixgbe_setup_kr_x550em - Configure the KR PHY
2574 * @hw: pointer to hardware structure
2575 **/
2576 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2577 {
2578 /* leave link alone for 2.5G */
2579 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2580 return 0;
2581
2582 if (ixgbe_check_reset_blocked(hw))
2583 return 0;
2584
2585 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2586 }
2587
2588 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2589 * @hw: address of hardware structure
2590 * @link_up: address of boolean to indicate link status
2591 *
2592 * Returns error code if unable to get link status.
2593 **/
2594 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2595 {
2596 u32 ret;
2597 u16 autoneg_status;
2598
2599 *link_up = false;
2600
2601 /* read this twice back to back to indicate current status */
2602 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2603 &autoneg_status);
2604 if (ret)
2605 return ret;
2606
2607 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2608 &autoneg_status);
2609 if (ret)
2610 return ret;
2611
2612 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2613
2614 return 0;
2615 }
2616
2617 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2618 * @hw: point to hardware structure
2619 *
2620 * Configures the link between the integrated KR PHY and the external X557 PHY
2621 * The driver will call this function when it gets a link status change
2622 * interrupt from the X557 PHY. This function configures the link speed
2623 * between the PHYs to match the link speed of the BASE-T link.
2624 *
2625 * A return of a non-zero value indicates an error, and the base driver should
2626 * not report link up.
2627 **/
2628 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2629 {
2630 ixgbe_link_speed force_speed;
2631 bool link_up;
2632 u32 status;
2633 u16 speed;
2634
2635 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2636 return IXGBE_ERR_CONFIG;
2637
2638 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2639 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2640 speed = IXGBE_LINK_SPEED_10GB_FULL |
2641 IXGBE_LINK_SPEED_1GB_FULL;
2642 return ixgbe_setup_kr_speed_x550em(hw, speed);
2643 }
2644
2645 /* If link is not up, then there is no setup necessary so return */
2646 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2647 if (status)
2648 return status;
2649
2650 if (!link_up)
2651 return 0;
2652
2653 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2654 MDIO_MMD_AN,
2655 &speed);
2656 if (status)
2657 return status;
2658
2659 /* If link is not still up, then no setup is necessary so return */
2660 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2661 if (status)
2662 return status;
2663
2664 if (!link_up)
2665 return 0;
2666
2667 /* clear everything but the speed and duplex bits */
2668 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2669
2670 switch (speed) {
2671 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2672 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2673 break;
2674 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2675 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2676 break;
2677 default:
2678 /* Internal PHY does not support anything else */
2679 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2680 }
2681
2682 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2683 }
2684
2685 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2686 * @hw: pointer to hardware structure
2687 **/
2688 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2689 {
2690 s32 status;
2691
2692 status = ixgbe_reset_phy_generic(hw);
2693
2694 if (status)
2695 return status;
2696
2697 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2698 return ixgbe_enable_lasi_ext_t_x550em(hw);
2699 }
2700
2701 /**
2702 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2703 * @hw: pointer to hardware structure
2704 * @led_idx: led number to turn on
2705 **/
2706 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2707 {
2708 u16 phy_data;
2709
2710 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2711 return IXGBE_ERR_PARAM;
2712
2713 /* To turn on the LED, set mode to ON. */
2714 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2715 MDIO_MMD_VEND1, &phy_data);
2716 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2717 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2718 MDIO_MMD_VEND1, phy_data);
2719
2720 return 0;
2721 }
2722
2723 /**
2724 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2725 * @hw: pointer to hardware structure
2726 * @led_idx: led number to turn off
2727 **/
2728 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2729 {
2730 u16 phy_data;
2731
2732 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2733 return IXGBE_ERR_PARAM;
2734
2735 /* To turn on the LED, set mode to ON. */
2736 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2737 MDIO_MMD_VEND1, &phy_data);
2738 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2739 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2740 MDIO_MMD_VEND1, phy_data);
2741
2742 return 0;
2743 }
2744
2745 /**
2746 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2747 * @hw: pointer to the HW structure
2748 * @maj: driver version major number
2749 * @min: driver version minor number
2750 * @build: driver version build number
2751 * @sub: driver version sub build number
2752 * @len: length of driver_ver string
2753 * @driver_ver: driver string
2754 *
2755 * Sends driver version number to firmware through the manageability
2756 * block. On success return 0
2757 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
2758 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
2759 **/
2760 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2761 u8 build, u8 sub, u16 len,
2762 const char *driver_ver)
2763 {
2764 struct ixgbe_hic_drv_info2 fw_cmd;
2765 s32 ret_val;
2766 int i;
2767
2768 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2769 return IXGBE_ERR_INVALID_ARGUMENT;
2770
2771 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2772 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2773 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2774 fw_cmd.port_num = (u8)hw->bus.func;
2775 fw_cmd.ver_maj = maj;
2776 fw_cmd.ver_min = min;
2777 fw_cmd.ver_build = build;
2778 fw_cmd.ver_sub = sub;
2779 fw_cmd.hdr.checksum = 0;
2780 memcpy(fw_cmd.driver_string, driver_ver, len);
2781 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2782 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2783
2784 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2785 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2786 sizeof(fw_cmd),
2787 IXGBE_HI_COMMAND_TIMEOUT,
2788 true);
2789 if (ret_val)
2790 continue;
2791
2792 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2793 FW_CEM_RESP_STATUS_SUCCESS)
2794 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
2795 return 0;
2796 }
2797
2798 return ret_val;
2799 }
2800
2801 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2802 * @hw: pointer to hardware structure
2803 * @lcd_speed: pointer to lowest common link speed
2804 *
2805 * Determine lowest common link speed with link partner.
2806 **/
2807 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2808 ixgbe_link_speed *lcd_speed)
2809 {
2810 u16 an_lp_status;
2811 s32 status;
2812 u16 word = hw->eeprom.ctrl_word_3;
2813
2814 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2815
2816 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2817 MDIO_MMD_AN,
2818 &an_lp_status);
2819 if (status)
2820 return status;
2821
2822 /* If link partner advertised 1G, return 1G */
2823 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2824 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2825 return status;
2826 }
2827
2828 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2829 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2830 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2831 return status;
2832
2833 /* Link partner not capable of lower speeds, return 10G */
2834 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2835 return status;
2836 }
2837
2838 /**
2839 * ixgbe_setup_fc_x550em - Set up flow control
2840 * @hw: pointer to hardware structure
2841 */
2842 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2843 {
2844 bool pause, asm_dir;
2845 u32 reg_val;
2846 s32 rc;
2847
2848 /* Validate the requested mode */
2849 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2850 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2851 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2852 }
2853
2854 /* 10gig parts do not have a word in the EEPROM to determine the
2855 * default flow control setting, so we explicitly set it to full.
2856 */
2857 if (hw->fc.requested_mode == ixgbe_fc_default)
2858 hw->fc.requested_mode = ixgbe_fc_full;
2859
2860 /* Determine PAUSE and ASM_DIR bits. */
2861 switch (hw->fc.requested_mode) {
2862 case ixgbe_fc_none:
2863 pause = false;
2864 asm_dir = false;
2865 break;
2866 case ixgbe_fc_tx_pause:
2867 pause = false;
2868 asm_dir = true;
2869 break;
2870 case ixgbe_fc_rx_pause:
2871 /* Rx Flow control is enabled and Tx Flow control is
2872 * disabled by software override. Since there really
2873 * isn't a way to advertise that we are capable of RX
2874 * Pause ONLY, we will advertise that we support both
2875 * symmetric and asymmetric Rx PAUSE, as such we fall
2876 * through to the fc_full statement. Later, we will
2877 * disable the adapter's ability to send PAUSE frames.
2878 */
2879 /* Fallthrough */
2880 case ixgbe_fc_full:
2881 pause = true;
2882 asm_dir = true;
2883 break;
2884 default:
2885 hw_err(hw, "Flow control param set incorrectly\n");
2886 return IXGBE_ERR_CONFIG;
2887 }
2888
2889 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR &&
2890 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR &&
2891 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L)
2892 return 0;
2893
2894 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2895 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2896 IXGBE_SB_IOSF_TARGET_KR_PHY,
2897 &reg_val);
2898 if (rc)
2899 return rc;
2900
2901 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2902 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2903 if (pause)
2904 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2905 if (asm_dir)
2906 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2907 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2908 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2909 IXGBE_SB_IOSF_TARGET_KR_PHY,
2910 reg_val);
2911
2912 /* This device does not fully support AN. */
2913 hw->fc.disable_fc_autoneg = true;
2914
2915 return rc;
2916 }
2917
2918 /**
2919 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2920 * @hw: pointer to hardware structure
2921 **/
2922 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2923 {
2924 u32 link_s1, lp_an_page_low, an_cntl_1;
2925 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2926 ixgbe_link_speed speed;
2927 bool link_up;
2928
2929 /* AN should have completed when the cable was plugged in.
2930 * Look for reasons to bail out. Bail out if:
2931 * - FC autoneg is disabled, or if
2932 * - link is not up.
2933 */
2934 if (hw->fc.disable_fc_autoneg) {
2935 hw_err(hw, "Flow control autoneg is disabled");
2936 goto out;
2937 }
2938
2939 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2940 if (!link_up) {
2941 hw_err(hw, "The link is down");
2942 goto out;
2943 }
2944
2945 /* Check at auto-negotiation has completed */
2946 status = hw->mac.ops.read_iosf_sb_reg(hw,
2947 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2948 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2949
2950 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2951 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2952 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2953 goto out;
2954 }
2955
2956 /* Read the 10g AN autoc and LP ability registers and resolve
2957 * local flow control settings accordingly
2958 */
2959 status = hw->mac.ops.read_iosf_sb_reg(hw,
2960 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2961 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2962
2963 if (status) {
2964 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2965 goto out;
2966 }
2967
2968 status = hw->mac.ops.read_iosf_sb_reg(hw,
2969 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2970 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2971
2972 if (status) {
2973 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2974 goto out;
2975 }
2976
2977 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2978 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2979 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2980 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2981 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
2982
2983 out:
2984 if (!status) {
2985 hw->fc.fc_was_autonegged = true;
2986 } else {
2987 hw->fc.fc_was_autonegged = false;
2988 hw->fc.current_mode = hw->fc.requested_mode;
2989 }
2990 }
2991
2992 /**
2993 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
2994 * @hw: pointer to hardware structure
2995 **/
2996 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
2997 {
2998 hw->fc.fc_was_autonegged = false;
2999 hw->fc.current_mode = hw->fc.requested_mode;
3000 }
3001
3002 /** ixgbe_enter_lplu_x550em - Transition to low power states
3003 * @hw: pointer to hardware structure
3004 *
3005 * Configures Low Power Link Up on transition to low power states
3006 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3007 * the X557 PHY immediately prior to entering LPLU.
3008 **/
3009 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3010 {
3011 u16 an_10g_cntl_reg, autoneg_reg, speed;
3012 s32 status;
3013 ixgbe_link_speed lcd_speed;
3014 u32 save_autoneg;
3015 bool link_up;
3016
3017 /* If blocked by MNG FW, then don't restart AN */
3018 if (ixgbe_check_reset_blocked(hw))
3019 return 0;
3020
3021 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3022 if (status)
3023 return status;
3024
3025 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3026 &hw->eeprom.ctrl_word_3);
3027 if (status)
3028 return status;
3029
3030 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3031 * manageability disabled, then force link down by entering
3032 * low power mode.
3033 */
3034 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3035 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3036 return ixgbe_set_copper_phy_power(hw, false);
3037
3038 /* Determine LCD */
3039 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3040 if (status)
3041 return status;
3042
3043 /* If no valid LCD link speed, then force link down and exit. */
3044 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3045 return ixgbe_set_copper_phy_power(hw, false);
3046
3047 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3048 MDIO_MMD_AN,
3049 &speed);
3050 if (status)
3051 return status;
3052
3053 /* If no link now, speed is invalid so take link down */
3054 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3055 if (status)
3056 return ixgbe_set_copper_phy_power(hw, false);
3057
3058 /* clear everything but the speed bits */
3059 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3060
3061 /* If current speed is already LCD, then exit. */
3062 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3063 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3064 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3065 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3066 return status;
3067
3068 /* Clear AN completed indication */
3069 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3070 MDIO_MMD_AN,
3071 &autoneg_reg);
3072 if (status)
3073 return status;
3074
3075 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3076 MDIO_MMD_AN,
3077 &an_10g_cntl_reg);
3078 if (status)
3079 return status;
3080
3081 status = hw->phy.ops.read_reg(hw,
3082 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3083 MDIO_MMD_AN,
3084 &autoneg_reg);
3085 if (status)
3086 return status;
3087
3088 save_autoneg = hw->phy.autoneg_advertised;
3089
3090 /* Setup link at least common link speed */
3091 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3092
3093 /* restore autoneg from before setting lplu speed */
3094 hw->phy.autoneg_advertised = save_autoneg;
3095
3096 return status;
3097 }
3098
3099 /**
3100 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3101 * @hw: pointer to hardware structure
3102 */
3103 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3104 {
3105 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3106 s32 rc;
3107
3108 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3109 return 0;
3110
3111 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3112 if (rc)
3113 return rc;
3114 memset(store, 0, sizeof(store));
3115
3116 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3117 if (rc)
3118 return rc;
3119
3120 return ixgbe_setup_fw_link(hw);
3121 }
3122
3123 /**
3124 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3125 * @hw: pointer to hardware structure
3126 */
3127 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3128 {
3129 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3130 s32 rc;
3131
3132 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3133 if (rc)
3134 return rc;
3135
3136 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3137 ixgbe_shutdown_fw_phy(hw);
3138 return IXGBE_ERR_OVERTEMP;
3139 }
3140 return 0;
3141 }
3142
3143 /**
3144 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3145 * @hw: pointer to hardware structure
3146 *
3147 * Read NW_MNG_IF_SEL register and save field values.
3148 */
3149 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3150 {
3151 /* Save NW management interface connected on board. This is used
3152 * to determine internal PHY mode.
3153 */
3154 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3155
3156 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3157 * PHY address. This register field was has only been used for X552.
3158 */
3159 if (hw->mac.type == ixgbe_mac_x550em_a &&
3160 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3161 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
3162 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
3163 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
3164 }
3165 }
3166
3167 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3168 * @hw: pointer to hardware structure
3169 *
3170 * Initialize any function pointers that were not able to be
3171 * set during init_shared_code because the PHY/SFP type was
3172 * not known. Perform the SFP init if necessary.
3173 **/
3174 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3175 {
3176 struct ixgbe_phy_info *phy = &hw->phy;
3177 s32 ret_val;
3178
3179 hw->mac.ops.set_lan_id(hw);
3180
3181 ixgbe_read_mng_if_sel_x550em(hw);
3182
3183 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3184 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3185 ixgbe_setup_mux_ctl(hw);
3186 }
3187
3188 /* Identify the PHY or SFP module */
3189 ret_val = phy->ops.identify(hw);
3190
3191 /* Setup function pointers based on detected hardware */
3192 ixgbe_init_mac_link_ops_X550em(hw);
3193 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3194 phy->ops.reset = NULL;
3195
3196 /* Set functions pointers based on phy type */
3197 switch (hw->phy.type) {
3198 case ixgbe_phy_x550em_kx4:
3199 phy->ops.setup_link = NULL;
3200 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3201 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3202 break;
3203 case ixgbe_phy_x550em_kr:
3204 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3205 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3206 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3207 break;
3208 case ixgbe_phy_x550em_xfi:
3209 /* link is managed by HW */
3210 phy->ops.setup_link = NULL;
3211 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3212 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3213 break;
3214 case ixgbe_phy_x550em_ext_t:
3215 /* Save NW management interface connected on board. This is used
3216 * to determine internal PHY mode
3217 */
3218 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3219
3220 /* If internal link mode is XFI, then setup iXFI internal link,
3221 * else setup KR now.
3222 */
3223 phy->ops.setup_internal_link =
3224 ixgbe_setup_internal_phy_t_x550em;
3225
3226 /* setup SW LPLU only for first revision */
3227 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3228 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3229 IXGBE_FUSES0_REV_MASK))
3230 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3231
3232 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3233 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3234 break;
3235 case ixgbe_phy_sgmii:
3236 phy->ops.setup_link = NULL;
3237 break;
3238 case ixgbe_phy_fw:
3239 phy->ops.setup_link = ixgbe_setup_fw_link;
3240 phy->ops.reset = ixgbe_reset_phy_fw;
3241 break;
3242 case ixgbe_phy_ext_1g_t:
3243 phy->ops.setup_link = NULL;
3244 phy->ops.read_reg = NULL;
3245 phy->ops.write_reg = NULL;
3246 phy->ops.reset = NULL;
3247 break;
3248 default:
3249 break;
3250 }
3251
3252 return ret_val;
3253 }
3254
3255 /** ixgbe_get_media_type_X550em - Get media type
3256 * @hw: pointer to hardware structure
3257 *
3258 * Returns the media type (fiber, copper, backplane)
3259 *
3260 */
3261 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3262 {
3263 enum ixgbe_media_type media_type;
3264
3265 /* Detect if there is a copper PHY attached. */
3266 switch (hw->device_id) {
3267 case IXGBE_DEV_ID_X550EM_A_SGMII:
3268 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3269 hw->phy.type = ixgbe_phy_sgmii;
3270 /* Fallthrough */
3271 case IXGBE_DEV_ID_X550EM_X_KR:
3272 case IXGBE_DEV_ID_X550EM_X_KX4:
3273 case IXGBE_DEV_ID_X550EM_X_XFI:
3274 case IXGBE_DEV_ID_X550EM_A_KR:
3275 case IXGBE_DEV_ID_X550EM_A_KR_L:
3276 media_type = ixgbe_media_type_backplane;
3277 break;
3278 case IXGBE_DEV_ID_X550EM_X_SFP:
3279 case IXGBE_DEV_ID_X550EM_A_SFP:
3280 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3281 media_type = ixgbe_media_type_fiber;
3282 break;
3283 case IXGBE_DEV_ID_X550EM_X_1G_T:
3284 case IXGBE_DEV_ID_X550EM_X_10G_T:
3285 case IXGBE_DEV_ID_X550EM_A_10G_T:
3286 case IXGBE_DEV_ID_X550EM_A_1G_T:
3287 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3288 media_type = ixgbe_media_type_copper;
3289 break;
3290 default:
3291 media_type = ixgbe_media_type_unknown;
3292 break;
3293 }
3294 return media_type;
3295 }
3296
3297 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3298 ** @hw: pointer to hardware structure
3299 **/
3300 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3301 {
3302 s32 status;
3303 u16 reg;
3304
3305 status = hw->phy.ops.read_reg(hw,
3306 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3307 MDIO_MMD_PMAPMD,
3308 &reg);
3309 if (status)
3310 return status;
3311
3312 /* If PHY FW reset completed bit is set then this is the first
3313 * SW instance after a power on so the PHY FW must be un-stalled.
3314 */
3315 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3316 status = hw->phy.ops.read_reg(hw,
3317 IXGBE_MDIO_GLOBAL_RES_PR_10,
3318 MDIO_MMD_VEND1,
3319 &reg);
3320 if (status)
3321 return status;
3322
3323 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3324
3325 status = hw->phy.ops.write_reg(hw,
3326 IXGBE_MDIO_GLOBAL_RES_PR_10,
3327 MDIO_MMD_VEND1,
3328 reg);
3329 if (status)
3330 return status;
3331 }
3332
3333 return status;
3334 }
3335
3336 /**
3337 * ixgbe_set_mdio_speed - Set MDIO clock speed
3338 * @hw: pointer to hardware structure
3339 */
3340 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3341 {
3342 u32 hlreg0;
3343
3344 switch (hw->device_id) {
3345 case IXGBE_DEV_ID_X550EM_X_10G_T:
3346 case IXGBE_DEV_ID_X550EM_A_SGMII:
3347 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3348 case IXGBE_DEV_ID_X550EM_A_10G_T:
3349 case IXGBE_DEV_ID_X550EM_A_SFP:
3350 /* Config MDIO clock speed before the first MDIO PHY access */
3351 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3352 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3353 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3354 break;
3355 case IXGBE_DEV_ID_X550EM_A_1G_T:
3356 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3357 /* Select fast MDIO clock speed for these devices */
3358 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3359 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3360 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3361 break;
3362 default:
3363 break;
3364 }
3365 }
3366
3367 /** ixgbe_reset_hw_X550em - Perform hardware reset
3368 ** @hw: pointer to hardware structure
3369 **
3370 ** Resets the hardware by resetting the transmit and receive units, masks
3371 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3372 ** reset.
3373 **/
3374 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3375 {
3376 ixgbe_link_speed link_speed;
3377 s32 status;
3378 u32 ctrl = 0;
3379 u32 i;
3380 bool link_up = false;
3381 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3382
3383 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3384 status = hw->mac.ops.stop_adapter(hw);
3385 if (status)
3386 return status;
3387
3388 /* flush pending Tx transactions */
3389 ixgbe_clear_tx_pending(hw);
3390
3391 /* PHY ops must be identified and initialized prior to reset */
3392
3393 /* Identify PHY and related function pointers */
3394 status = hw->phy.ops.init(hw);
3395
3396 /* start the external PHY */
3397 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3398 status = ixgbe_init_ext_t_x550em(hw);
3399 if (status)
3400 return status;
3401 }
3402
3403 /* Setup SFP module if there is one present. */
3404 if (hw->phy.sfp_setup_needed) {
3405 status = hw->mac.ops.setup_sfp(hw);
3406 hw->phy.sfp_setup_needed = false;
3407 }
3408
3409 /* Reset PHY */
3410 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3411 hw->phy.ops.reset(hw);
3412
3413 mac_reset_top:
3414 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3415 * If link reset is used when link is up, it might reset the PHY when
3416 * mng is using it. If link is down or the flag to force full link
3417 * reset is set, then perform link reset.
3418 */
3419 ctrl = IXGBE_CTRL_LNK_RST;
3420
3421 if (!hw->force_full_reset) {
3422 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3423 if (link_up)
3424 ctrl = IXGBE_CTRL_RST;
3425 }
3426
3427 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3428 if (status) {
3429 hw_dbg(hw, "semaphore failed with %d", status);
3430 return IXGBE_ERR_SWFW_SYNC;
3431 }
3432
3433 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3434 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3435 IXGBE_WRITE_FLUSH(hw);
3436 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3437 usleep_range(1000, 1200);
3438
3439 /* Poll for reset bit to self-clear meaning reset is complete */
3440 for (i = 0; i < 10; i++) {
3441 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3442 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3443 break;
3444 udelay(1);
3445 }
3446
3447 if (ctrl & IXGBE_CTRL_RST_MASK) {
3448 status = IXGBE_ERR_RESET_FAILED;
3449 hw_dbg(hw, "Reset polling failed to complete.\n");
3450 }
3451
3452 msleep(50);
3453
3454 /* Double resets are required for recovery from certain error
3455 * clear the multicast table. Also reset num_rar_entries to 128,
3456 * since we modify this value when programming the SAN MAC address.
3457 */
3458 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3459 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3460 goto mac_reset_top;
3461 }
3462
3463 /* Store the permanent mac address */
3464 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3465
3466 /* Store MAC address from RAR0, clear receive address registers, and
3467 * clear the multicast table. Also reset num_rar_entries to 128,
3468 * since we modify this value when programming the SAN MAC address.
3469 */
3470 hw->mac.num_rar_entries = 128;
3471 hw->mac.ops.init_rx_addrs(hw);
3472
3473 ixgbe_set_mdio_speed(hw);
3474
3475 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3476 ixgbe_setup_mux_ctl(hw);
3477
3478 return status;
3479 }
3480
3481 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3482 * anti-spoofing
3483 * @hw: pointer to hardware structure
3484 * @enable: enable or disable switch for Ethertype anti-spoofing
3485 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3486 **/
3487 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3488 bool enable, int vf)
3489 {
3490 int vf_target_reg = vf >> 3;
3491 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3492 u32 pfvfspoof;
3493
3494 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3495 if (enable)
3496 pfvfspoof |= BIT(vf_target_shift);
3497 else
3498 pfvfspoof &= ~BIT(vf_target_shift);
3499
3500 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3501 }
3502
3503 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3504 * @hw: pointer to hardware structure
3505 * @enable: enable or disable source address pruning
3506 * @pool: Rx pool to set source address pruning for
3507 **/
3508 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3509 bool enable,
3510 unsigned int pool)
3511 {
3512 u64 pfflp;
3513
3514 /* max rx pool is 63 */
3515 if (pool > 63)
3516 return;
3517
3518 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3519 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3520
3521 if (enable)
3522 pfflp |= (1ULL << pool);
3523 else
3524 pfflp &= ~(1ULL << pool);
3525
3526 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3527 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3528 }
3529
3530 /**
3531 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3532 * @hw: pointer to hardware structure
3533 *
3534 * Called at init time to set up flow control.
3535 **/
3536 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3537 {
3538 s32 status = 0;
3539 u32 an_cntl = 0;
3540
3541 /* Validate the requested mode */
3542 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3543 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3544 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3545 }
3546
3547 if (hw->fc.requested_mode == ixgbe_fc_default)
3548 hw->fc.requested_mode = ixgbe_fc_full;
3549
3550 /* Set up the 1G and 10G flow control advertisement registers so the
3551 * HW will be able to do FC autoneg once the cable is plugged in. If
3552 * we link at 10G, the 1G advertisement is harmless and vice versa.
3553 */
3554 status = hw->mac.ops.read_iosf_sb_reg(hw,
3555 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3556 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3557
3558 if (status) {
3559 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3560 return status;
3561 }
3562
3563 /* The possible values of fc.requested_mode are:
3564 * 0: Flow control is completely disabled
3565 * 1: Rx flow control is enabled (we can receive pause frames,
3566 * but not send pause frames).
3567 * 2: Tx flow control is enabled (we can send pause frames but
3568 * we do not support receiving pause frames).
3569 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3570 * other: Invalid.
3571 */
3572 switch (hw->fc.requested_mode) {
3573 case ixgbe_fc_none:
3574 /* Flow control completely disabled by software override. */
3575 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3576 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3577 break;
3578 case ixgbe_fc_tx_pause:
3579 /* Tx Flow control is enabled, and Rx Flow control is
3580 * disabled by software override.
3581 */
3582 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3583 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3584 break;
3585 case ixgbe_fc_rx_pause:
3586 /* Rx Flow control is enabled and Tx Flow control is
3587 * disabled by software override. Since there really
3588 * isn't a way to advertise that we are capable of RX
3589 * Pause ONLY, we will advertise that we support both
3590 * symmetric and asymmetric Rx PAUSE, as such we fall
3591 * through to the fc_full statement. Later, we will
3592 * disable the adapter's ability to send PAUSE frames.
3593 */
3594 case ixgbe_fc_full:
3595 /* Flow control (both Rx and Tx) is enabled by SW override. */
3596 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3597 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3598 break;
3599 default:
3600 hw_err(hw, "Flow control param set incorrectly\n");
3601 return IXGBE_ERR_CONFIG;
3602 }
3603
3604 status = hw->mac.ops.write_iosf_sb_reg(hw,
3605 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3606 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3607
3608 /* Restart auto-negotiation. */
3609 status = ixgbe_restart_an_internal_phy_x550em(hw);
3610
3611 return status;
3612 }
3613
3614 /**
3615 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3616 * @hw: pointer to hardware structure
3617 * @state: set mux if 1, clear if 0
3618 */
3619 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3620 {
3621 u32 esdp;
3622
3623 if (!hw->bus.lan_id)
3624 return;
3625 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3626 if (state)
3627 esdp |= IXGBE_ESDP_SDP1;
3628 else
3629 esdp &= ~IXGBE_ESDP_SDP1;
3630 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3631 IXGBE_WRITE_FLUSH(hw);
3632 }
3633
3634 /**
3635 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3636 * @hw: pointer to hardware structure
3637 * @mask: Mask to specify which semaphore to acquire
3638 *
3639 * Acquires the SWFW semaphore and sets the I2C MUX
3640 */
3641 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3642 {
3643 s32 status;
3644
3645 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3646 if (status)
3647 return status;
3648
3649 if (mask & IXGBE_GSSR_I2C_MASK)
3650 ixgbe_set_mux(hw, 1);
3651
3652 return 0;
3653 }
3654
3655 /**
3656 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3657 * @hw: pointer to hardware structure
3658 * @mask: Mask to specify which semaphore to release
3659 *
3660 * Releases the SWFW semaphore and sets the I2C MUX
3661 */
3662 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3663 {
3664 if (mask & IXGBE_GSSR_I2C_MASK)
3665 ixgbe_set_mux(hw, 0);
3666
3667 ixgbe_release_swfw_sync_X540(hw, mask);
3668 }
3669
3670 /**
3671 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3672 * @hw: pointer to hardware structure
3673 * @mask: Mask to specify which semaphore to acquire
3674 *
3675 * Acquires the SWFW semaphore and get the shared PHY token as needed
3676 */
3677 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3678 {
3679 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3680 int retries = FW_PHY_TOKEN_RETRIES;
3681 s32 status;
3682
3683 while (--retries) {
3684 status = 0;
3685 if (hmask)
3686 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3687 if (status)
3688 return status;
3689 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3690 return 0;
3691
3692 status = ixgbe_get_phy_token(hw);
3693 if (!status)
3694 return 0;
3695 if (hmask)
3696 ixgbe_release_swfw_sync_X540(hw, hmask);
3697 if (status != IXGBE_ERR_TOKEN_RETRY)
3698 return status;
3699 msleep(FW_PHY_TOKEN_DELAY);
3700 }
3701
3702 return status;
3703 }
3704
3705 /**
3706 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3707 * @hw: pointer to hardware structure
3708 * @mask: Mask to specify which semaphore to release
3709 *
3710 * Release the SWFW semaphore and puts the shared PHY token as needed
3711 */
3712 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3713 {
3714 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3715
3716 if (mask & IXGBE_GSSR_TOKEN_SM)
3717 ixgbe_put_phy_token(hw);
3718
3719 if (hmask)
3720 ixgbe_release_swfw_sync_X540(hw, hmask);
3721 }
3722
3723 /**
3724 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3725 * @hw: pointer to hardware structure
3726 * @reg_addr: 32 bit address of PHY register to read
3727 * @phy_data: Pointer to read data from PHY register
3728 *
3729 * Reads a value from a specified PHY register using the SWFW lock and PHY
3730 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3731 * instances.
3732 */
3733 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3734 u32 device_type, u16 *phy_data)
3735 {
3736 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3737 s32 status;
3738
3739 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3740 return IXGBE_ERR_SWFW_SYNC;
3741
3742 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3743
3744 hw->mac.ops.release_swfw_sync(hw, mask);
3745
3746 return status;
3747 }
3748
3749 /**
3750 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3751 * @hw: pointer to hardware structure
3752 * @reg_addr: 32 bit PHY register to write
3753 * @device_type: 5 bit device type
3754 * @phy_data: Data to write to the PHY register
3755 *
3756 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3757 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3758 */
3759 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3760 u32 device_type, u16 phy_data)
3761 {
3762 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3763 s32 status;
3764
3765 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3766 return IXGBE_ERR_SWFW_SYNC;
3767
3768 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3769 hw->mac.ops.release_swfw_sync(hw, mask);
3770
3771 return status;
3772 }
3773
3774 #define X550_COMMON_MAC \
3775 .init_hw = &ixgbe_init_hw_generic, \
3776 .start_hw = &ixgbe_start_hw_X540, \
3777 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3778 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3779 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3780 .get_device_caps = &ixgbe_get_device_caps_generic, \
3781 .stop_adapter = &ixgbe_stop_adapter_generic, \
3782 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3783 .read_analog_reg8 = NULL, \
3784 .write_analog_reg8 = NULL, \
3785 .set_rxpba = &ixgbe_set_rxpba_generic, \
3786 .check_link = &ixgbe_check_mac_link_generic, \
3787 .blink_led_start = &ixgbe_blink_led_start_X540, \
3788 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3789 .set_rar = &ixgbe_set_rar_generic, \
3790 .clear_rar = &ixgbe_clear_rar_generic, \
3791 .set_vmdq = &ixgbe_set_vmdq_generic, \
3792 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3793 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3794 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3795 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3796 .enable_mc = &ixgbe_enable_mc_generic, \
3797 .disable_mc = &ixgbe_disable_mc_generic, \
3798 .clear_vfta = &ixgbe_clear_vfta_generic, \
3799 .set_vfta = &ixgbe_set_vfta_generic, \
3800 .fc_enable = &ixgbe_fc_enable_generic, \
3801 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3802 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3803 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3804 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3805 .set_source_address_pruning = \
3806 &ixgbe_set_source_address_pruning_X550, \
3807 .set_ethertype_anti_spoofing = \
3808 &ixgbe_set_ethertype_anti_spoofing_X550, \
3809 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3810 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3811 .get_thermal_sensor_data = NULL, \
3812 .init_thermal_sensor_thresh = NULL, \
3813 .enable_rx = &ixgbe_enable_rx_generic, \
3814 .disable_rx = &ixgbe_disable_rx_x550, \
3815
3816 static const struct ixgbe_mac_operations mac_ops_X550 = {
3817 X550_COMMON_MAC
3818 .led_on = ixgbe_led_on_generic,
3819 .led_off = ixgbe_led_off_generic,
3820 .init_led_link_act = ixgbe_init_led_link_act_generic,
3821 .reset_hw = &ixgbe_reset_hw_X540,
3822 .get_media_type = &ixgbe_get_media_type_X540,
3823 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3824 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3825 .setup_link = &ixgbe_setup_mac_link_X540,
3826 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3827 .get_bus_info = &ixgbe_get_bus_info_generic,
3828 .setup_sfp = NULL,
3829 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3830 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3831 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3832 .prot_autoc_read = prot_autoc_read_generic,
3833 .prot_autoc_write = prot_autoc_write_generic,
3834 .setup_fc = ixgbe_setup_fc_generic,
3835 .fc_autoneg = ixgbe_fc_autoneg,
3836 };
3837
3838 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3839 X550_COMMON_MAC
3840 .led_on = ixgbe_led_on_t_x550em,
3841 .led_off = ixgbe_led_off_t_x550em,
3842 .init_led_link_act = ixgbe_init_led_link_act_generic,
3843 .reset_hw = &ixgbe_reset_hw_X550em,
3844 .get_media_type = &ixgbe_get_media_type_X550em,
3845 .get_san_mac_addr = NULL,
3846 .get_wwn_prefix = NULL,
3847 .setup_link = &ixgbe_setup_mac_link_X540,
3848 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3849 .get_bus_info = &ixgbe_get_bus_info_X550em,
3850 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3851 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3852 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3853 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3854 .setup_fc = NULL, /* defined later */
3855 .fc_autoneg = ixgbe_fc_autoneg,
3856 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3857 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3858 };
3859
3860 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3861 X550_COMMON_MAC
3862 .led_on = NULL,
3863 .led_off = NULL,
3864 .init_led_link_act = NULL,
3865 .reset_hw = &ixgbe_reset_hw_X550em,
3866 .get_media_type = &ixgbe_get_media_type_X550em,
3867 .get_san_mac_addr = NULL,
3868 .get_wwn_prefix = NULL,
3869 .setup_link = &ixgbe_setup_mac_link_X540,
3870 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3871 .get_bus_info = &ixgbe_get_bus_info_X550em,
3872 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3873 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3874 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3875 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3876 .setup_fc = NULL,
3877 .fc_autoneg = ixgbe_fc_autoneg,
3878 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3879 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3880 };
3881
3882 static struct ixgbe_mac_operations mac_ops_x550em_a = {
3883 X550_COMMON_MAC
3884 .led_on = ixgbe_led_on_t_x550em,
3885 .led_off = ixgbe_led_off_t_x550em,
3886 .init_led_link_act = ixgbe_init_led_link_act_generic,
3887 .reset_hw = ixgbe_reset_hw_X550em,
3888 .get_media_type = ixgbe_get_media_type_X550em,
3889 .get_san_mac_addr = NULL,
3890 .get_wwn_prefix = NULL,
3891 .setup_link = &ixgbe_setup_mac_link_X540,
3892 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3893 .get_bus_info = ixgbe_get_bus_info_X550em,
3894 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3895 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3896 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3897 .setup_fc = ixgbe_setup_fc_x550em,
3898 .fc_autoneg = ixgbe_fc_autoneg,
3899 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3900 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3901 };
3902
3903 static struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3904 X550_COMMON_MAC
3905 .led_on = ixgbe_led_on_generic,
3906 .led_off = ixgbe_led_off_generic,
3907 .init_led_link_act = ixgbe_init_led_link_act_generic,
3908 .reset_hw = ixgbe_reset_hw_X550em,
3909 .get_media_type = ixgbe_get_media_type_X550em,
3910 .get_san_mac_addr = NULL,
3911 .get_wwn_prefix = NULL,
3912 .setup_link = NULL, /* defined later */
3913 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3914 .get_bus_info = ixgbe_get_bus_info_X550em,
3915 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3916 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3917 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3918 .setup_fc = ixgbe_setup_fc_x550em,
3919 .fc_autoneg = ixgbe_fc_autoneg,
3920 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3921 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3922 };
3923
3924 #define X550_COMMON_EEP \
3925 .read = &ixgbe_read_ee_hostif_X550, \
3926 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3927 .write = &ixgbe_write_ee_hostif_X550, \
3928 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3929 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3930 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3931 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3932
3933 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3934 X550_COMMON_EEP
3935 .init_params = &ixgbe_init_eeprom_params_X550,
3936 };
3937
3938 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3939 X550_COMMON_EEP
3940 .init_params = &ixgbe_init_eeprom_params_X540,
3941 };
3942
3943 #define X550_COMMON_PHY \
3944 .identify_sfp = &ixgbe_identify_module_generic, \
3945 .reset = NULL, \
3946 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3947 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3948 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3949 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3950 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3951 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3952 .setup_link = &ixgbe_setup_phy_link_generic, \
3953 .set_phy_power = NULL,
3954
3955 static const struct ixgbe_phy_operations phy_ops_X550 = {
3956 X550_COMMON_PHY
3957 .check_overtemp = &ixgbe_tn_check_overtemp,
3958 .init = NULL,
3959 .identify = &ixgbe_identify_phy_generic,
3960 .read_reg = &ixgbe_read_phy_reg_generic,
3961 .write_reg = &ixgbe_write_phy_reg_generic,
3962 };
3963
3964 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3965 X550_COMMON_PHY
3966 .check_overtemp = &ixgbe_tn_check_overtemp,
3967 .init = &ixgbe_init_phy_ops_X550em,
3968 .identify = &ixgbe_identify_phy_x550em,
3969 .read_reg = &ixgbe_read_phy_reg_generic,
3970 .write_reg = &ixgbe_write_phy_reg_generic,
3971 };
3972
3973 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
3974 X550_COMMON_PHY
3975 .check_overtemp = NULL,
3976 .init = ixgbe_init_phy_ops_X550em,
3977 .identify = ixgbe_identify_phy_x550em,
3978 .read_reg = NULL,
3979 .write_reg = NULL,
3980 .read_reg_mdi = NULL,
3981 .write_reg_mdi = NULL,
3982 };
3983
3984 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
3985 X550_COMMON_PHY
3986 .check_overtemp = &ixgbe_tn_check_overtemp,
3987 .init = &ixgbe_init_phy_ops_X550em,
3988 .identify = &ixgbe_identify_phy_x550em,
3989 .read_reg = &ixgbe_read_phy_reg_x550a,
3990 .write_reg = &ixgbe_write_phy_reg_x550a,
3991 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
3992 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
3993 };
3994
3995 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
3996 X550_COMMON_PHY
3997 .check_overtemp = ixgbe_check_overtemp_fw,
3998 .init = ixgbe_init_phy_ops_X550em,
3999 .identify = ixgbe_identify_phy_fw,
4000 .read_reg = NULL,
4001 .write_reg = NULL,
4002 .read_reg_mdi = NULL,
4003 .write_reg_mdi = NULL,
4004 };
4005
4006 static const struct ixgbe_link_operations link_ops_x550em_x = {
4007 .read_link = &ixgbe_read_i2c_combined_generic,
4008 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4009 .write_link = &ixgbe_write_i2c_combined_generic,
4010 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4011 };
4012
4013 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4014 IXGBE_MVALS_INIT(X550)
4015 };
4016
4017 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4018 IXGBE_MVALS_INIT(X550EM_x)
4019 };
4020
4021 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4022 IXGBE_MVALS_INIT(X550EM_a)
4023 };
4024
4025 const struct ixgbe_info ixgbe_X550_info = {
4026 .mac = ixgbe_mac_X550,
4027 .get_invariants = &ixgbe_get_invariants_X540,
4028 .mac_ops = &mac_ops_X550,
4029 .eeprom_ops = &eeprom_ops_X550,
4030 .phy_ops = &phy_ops_X550,
4031 .mbx_ops = &mbx_ops_generic,
4032 .mvals = ixgbe_mvals_X550,
4033 };
4034
4035 const struct ixgbe_info ixgbe_X550EM_x_info = {
4036 .mac = ixgbe_mac_X550EM_x,
4037 .get_invariants = &ixgbe_get_invariants_X550_x,
4038 .mac_ops = &mac_ops_X550EM_x,
4039 .eeprom_ops = &eeprom_ops_X550EM_x,
4040 .phy_ops = &phy_ops_X550EM_x,
4041 .mbx_ops = &mbx_ops_generic,
4042 .mvals = ixgbe_mvals_X550EM_x,
4043 .link_ops = &link_ops_x550em_x,
4044 };
4045
4046 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4047 .mac = ixgbe_mac_X550EM_x,
4048 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4049 .mac_ops = &mac_ops_X550EM_x_fw,
4050 .eeprom_ops = &eeprom_ops_X550EM_x,
4051 .phy_ops = &phy_ops_x550em_x_fw,
4052 .mbx_ops = &mbx_ops_generic,
4053 .mvals = ixgbe_mvals_X550EM_x,
4054 };
4055
4056 const struct ixgbe_info ixgbe_x550em_a_info = {
4057 .mac = ixgbe_mac_x550em_a,
4058 .get_invariants = &ixgbe_get_invariants_X550_a,
4059 .mac_ops = &mac_ops_x550em_a,
4060 .eeprom_ops = &eeprom_ops_X550EM_x,
4061 .phy_ops = &phy_ops_x550em_a,
4062 .mbx_ops = &mbx_ops_generic,
4063 .mvals = ixgbe_mvals_x550em_a,
4064 };
4065
4066 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4067 .mac = ixgbe_mac_x550em_a,
4068 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4069 .mac_ops = &mac_ops_x550em_a_fw,
4070 .eeprom_ops = &eeprom_ops_X550EM_x,
4071 .phy_ops = &phy_ops_x550em_a_fw,
4072 .mbx_ops = &mbx_ops_generic,
4073 .mvals = ixgbe_mvals_x550em_a,
4074 };
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