1 // SPDX-License-Identifier: GPL-2.0-only
3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
5 * Copyright 2008 JMicron Technology Corporation
6 * http://www.jmicron.com/
7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/mii.h>
21 #include <linux/crc32.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
26 #include <linux/ipv6.h>
27 #include <linux/tcp.h>
28 #include <linux/udp.h>
29 #include <linux/if_vlan.h>
30 #include <linux/slab.h>
31 #include <net/ip6_checksum.h>
34 static int force_pseudohp
= -1;
35 static int no_pseudohp
= -1;
36 static int no_extplug
= -1;
37 module_param(force_pseudohp
, int, 0);
38 MODULE_PARM_DESC(force_pseudohp
,
39 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
40 module_param(no_pseudohp
, int, 0);
41 MODULE_PARM_DESC(no_pseudohp
, "Disable pseudo hot-plug feature.");
42 module_param(no_extplug
, int, 0);
43 MODULE_PARM_DESC(no_extplug
,
44 "Do not use external plug signal for pseudo hot-plug.");
47 jme_mdio_read(struct net_device
*netdev
, int phy
, int reg
)
49 struct jme_adapter
*jme
= netdev_priv(netdev
);
50 int i
, val
, again
= (reg
== MII_BMSR
) ? 1 : 0;
53 jwrite32(jme
, JME_SMI
, SMI_OP_REQ
|
58 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
60 val
= jread32(jme
, JME_SMI
);
61 if ((val
& SMI_OP_REQ
) == 0)
66 pr_err("phy(%d) read timeout : %d\n", phy
, reg
);
73 return (val
& SMI_DATA_MASK
) >> SMI_DATA_SHIFT
;
77 jme_mdio_write(struct net_device
*netdev
,
78 int phy
, int reg
, int val
)
80 struct jme_adapter
*jme
= netdev_priv(netdev
);
83 jwrite32(jme
, JME_SMI
, SMI_OP_WRITE
| SMI_OP_REQ
|
84 ((val
<< SMI_DATA_SHIFT
) & SMI_DATA_MASK
) |
85 smi_phy_addr(phy
) | smi_reg_addr(reg
));
88 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
90 if ((jread32(jme
, JME_SMI
) & SMI_OP_REQ
) == 0)
95 pr_err("phy(%d) write timeout : %d\n", phy
, reg
);
99 jme_reset_phy_processor(struct jme_adapter
*jme
)
103 jme_mdio_write(jme
->dev
,
105 MII_ADVERTISE
, ADVERTISE_ALL
|
106 ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
108 if (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
109 jme_mdio_write(jme
->dev
,
112 ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
114 val
= jme_mdio_read(jme
->dev
,
118 jme_mdio_write(jme
->dev
,
120 MII_BMCR
, val
| BMCR_RESET
);
124 jme_setup_wakeup_frame(struct jme_adapter
*jme
,
125 const u32
*mask
, u32 crc
, int fnr
)
132 jwrite32(jme
, JME_WFOI
, WFOI_CRC_SEL
| (fnr
& WFOI_FRAME_SEL
));
134 jwrite32(jme
, JME_WFODP
, crc
);
140 for (i
= 0 ; i
< WAKEUP_FRAME_MASK_DWNR
; ++i
) {
141 jwrite32(jme
, JME_WFOI
,
142 ((i
<< WFOI_MASK_SHIFT
) & WFOI_MASK_SEL
) |
143 (fnr
& WFOI_FRAME_SEL
));
145 jwrite32(jme
, JME_WFODP
, mask
[i
]);
151 jme_mac_rxclk_off(struct jme_adapter
*jme
)
153 jme
->reg_gpreg1
|= GPREG1_RXCLKOFF
;
154 jwrite32f(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
158 jme_mac_rxclk_on(struct jme_adapter
*jme
)
160 jme
->reg_gpreg1
&= ~GPREG1_RXCLKOFF
;
161 jwrite32f(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
165 jme_mac_txclk_off(struct jme_adapter
*jme
)
167 jme
->reg_ghc
&= ~(GHC_TO_CLK_SRC
| GHC_TXMAC_CLK_SRC
);
168 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
172 jme_mac_txclk_on(struct jme_adapter
*jme
)
174 u32 speed
= jme
->reg_ghc
& GHC_SPEED
;
175 if (speed
== GHC_SPEED_1000M
)
176 jme
->reg_ghc
|= GHC_TO_CLK_GPHY
| GHC_TXMAC_CLK_GPHY
;
178 jme
->reg_ghc
|= GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
;
179 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
183 jme_reset_ghc_speed(struct jme_adapter
*jme
)
185 jme
->reg_ghc
&= ~(GHC_SPEED
| GHC_DPX
);
186 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
190 jme_reset_250A2_workaround(struct jme_adapter
*jme
)
192 jme
->reg_gpreg1
&= ~(GPREG1_HALFMODEPATCH
|
194 jwrite32(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
198 jme_assert_ghc_reset(struct jme_adapter
*jme
)
200 jme
->reg_ghc
|= GHC_SWRST
;
201 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
205 jme_clear_ghc_reset(struct jme_adapter
*jme
)
207 jme
->reg_ghc
&= ~GHC_SWRST
;
208 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
212 jme_reset_mac_processor(struct jme_adapter
*jme
)
214 static const u32 mask
[WAKEUP_FRAME_MASK_DWNR
] = {0, 0, 0, 0};
215 u32 crc
= 0xCDCDCDCD;
219 jme_reset_ghc_speed(jme
);
220 jme_reset_250A2_workaround(jme
);
222 jme_mac_rxclk_on(jme
);
223 jme_mac_txclk_on(jme
);
225 jme_assert_ghc_reset(jme
);
227 jme_mac_rxclk_off(jme
);
228 jme_mac_txclk_off(jme
);
230 jme_clear_ghc_reset(jme
);
232 jme_mac_rxclk_on(jme
);
233 jme_mac_txclk_on(jme
);
235 jme_mac_rxclk_off(jme
);
236 jme_mac_txclk_off(jme
);
238 jwrite32(jme
, JME_RXDBA_LO
, 0x00000000);
239 jwrite32(jme
, JME_RXDBA_HI
, 0x00000000);
240 jwrite32(jme
, JME_RXQDC
, 0x00000000);
241 jwrite32(jme
, JME_RXNDA
, 0x00000000);
242 jwrite32(jme
, JME_TXDBA_LO
, 0x00000000);
243 jwrite32(jme
, JME_TXDBA_HI
, 0x00000000);
244 jwrite32(jme
, JME_TXQDC
, 0x00000000);
245 jwrite32(jme
, JME_TXNDA
, 0x00000000);
247 jwrite32(jme
, JME_RXMCHT_LO
, 0x00000000);
248 jwrite32(jme
, JME_RXMCHT_HI
, 0x00000000);
249 for (i
= 0 ; i
< WAKEUP_FRAME_NR
; ++i
)
250 jme_setup_wakeup_frame(jme
, mask
, crc
, i
);
252 gpreg0
= GPREG0_DEFAULT
| GPREG0_LNKINTPOLL
;
254 gpreg0
= GPREG0_DEFAULT
;
255 jwrite32(jme
, JME_GPREG0
, gpreg0
);
259 jme_clear_pm_enable_wol(struct jme_adapter
*jme
)
261 jwrite32(jme
, JME_PMCS
, PMCS_STMASK
| jme
->reg_pmcs
);
265 jme_clear_pm_disable_wol(struct jme_adapter
*jme
)
267 jwrite32(jme
, JME_PMCS
, PMCS_STMASK
);
271 jme_reload_eeprom(struct jme_adapter
*jme
)
276 val
= jread32(jme
, JME_SMBCSR
);
278 if (val
& SMBCSR_EEPROMD
) {
280 jwrite32(jme
, JME_SMBCSR
, val
);
281 val
|= SMBCSR_RELOAD
;
282 jwrite32(jme
, JME_SMBCSR
, val
);
285 for (i
= JME_EEPROM_RELOAD_TIMEOUT
; i
> 0; --i
) {
287 if ((jread32(jme
, JME_SMBCSR
) & SMBCSR_RELOAD
) == 0)
292 pr_err("eeprom reload timeout\n");
301 jme_load_macaddr(struct net_device
*netdev
)
303 struct jme_adapter
*jme
= netdev_priv(netdev
);
304 unsigned char macaddr
[ETH_ALEN
];
307 spin_lock_bh(&jme
->macaddr_lock
);
308 val
= jread32(jme
, JME_RXUMA_LO
);
309 macaddr
[0] = (val
>> 0) & 0xFF;
310 macaddr
[1] = (val
>> 8) & 0xFF;
311 macaddr
[2] = (val
>> 16) & 0xFF;
312 macaddr
[3] = (val
>> 24) & 0xFF;
313 val
= jread32(jme
, JME_RXUMA_HI
);
314 macaddr
[4] = (val
>> 0) & 0xFF;
315 macaddr
[5] = (val
>> 8) & 0xFF;
316 memcpy(netdev
->dev_addr
, macaddr
, ETH_ALEN
);
317 spin_unlock_bh(&jme
->macaddr_lock
);
321 jme_set_rx_pcc(struct jme_adapter
*jme
, int p
)
325 jwrite32(jme
, JME_PCCRX0
,
326 ((PCC_OFF_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
327 ((PCC_OFF_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
330 jwrite32(jme
, JME_PCCRX0
,
331 ((PCC_P1_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
332 ((PCC_P1_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
335 jwrite32(jme
, JME_PCCRX0
,
336 ((PCC_P2_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
337 ((PCC_P2_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
340 jwrite32(jme
, JME_PCCRX0
,
341 ((PCC_P3_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
342 ((PCC_P3_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
349 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
350 netif_info(jme
, rx_status
, jme
->dev
, "Switched to PCC_P%d\n", p
);
354 jme_start_irq(struct jme_adapter
*jme
)
356 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
358 jme_set_rx_pcc(jme
, PCC_P1
);
360 dpi
->attempt
= PCC_P1
;
363 jwrite32(jme
, JME_PCCTX
,
364 ((PCC_TX_TO
<< PCCTXTO_SHIFT
) & PCCTXTO_MASK
) |
365 ((PCC_TX_CNT
<< PCCTX_SHIFT
) & PCCTX_MASK
) |
372 jwrite32(jme
, JME_IENS
, INTR_ENABLE
);
376 jme_stop_irq(struct jme_adapter
*jme
)
381 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
385 jme_linkstat_from_phy(struct jme_adapter
*jme
)
389 phylink
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 17);
390 bmsr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMSR
);
391 if (bmsr
& BMSR_ANCOMP
)
392 phylink
|= PHY_LINK_AUTONEG_COMPLETE
;
398 jme_set_phyfifo_5level(struct jme_adapter
*jme
)
400 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0004);
404 jme_set_phyfifo_8level(struct jme_adapter
*jme
)
406 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0000);
410 jme_check_link(struct net_device
*netdev
, int testonly
)
412 struct jme_adapter
*jme
= netdev_priv(netdev
);
413 u32 phylink
, cnt
= JME_SPDRSV_TIMEOUT
, bmcr
;
420 phylink
= jme_linkstat_from_phy(jme
);
422 phylink
= jread32(jme
, JME_PHY_LINK
);
424 if (phylink
& PHY_LINK_UP
) {
425 if (!(phylink
& PHY_LINK_AUTONEG_COMPLETE
)) {
427 * If we did not enable AN
428 * Speed/Duplex Info should be obtained from SMI
430 phylink
= PHY_LINK_UP
;
432 bmcr
= jme_mdio_read(jme
->dev
,
436 phylink
|= ((bmcr
& BMCR_SPEED1000
) &&
437 (bmcr
& BMCR_SPEED100
) == 0) ?
438 PHY_LINK_SPEED_1000M
:
439 (bmcr
& BMCR_SPEED100
) ?
440 PHY_LINK_SPEED_100M
:
443 phylink
|= (bmcr
& BMCR_FULLDPLX
) ?
446 strcat(linkmsg
, "Forced: ");
449 * Keep polling for speed/duplex resolve complete
451 while (!(phylink
& PHY_LINK_SPEEDDPU_RESOLVED
) &&
457 phylink
= jme_linkstat_from_phy(jme
);
459 phylink
= jread32(jme
, JME_PHY_LINK
);
462 pr_err("Waiting speed resolve timeout\n");
464 strcat(linkmsg
, "ANed: ");
467 if (jme
->phylink
== phylink
) {
474 jme
->phylink
= phylink
;
477 * The speed/duplex setting of jme->reg_ghc already cleared
478 * by jme_reset_mac_processor()
480 switch (phylink
& PHY_LINK_SPEED_MASK
) {
481 case PHY_LINK_SPEED_10M
:
482 jme
->reg_ghc
|= GHC_SPEED_10M
;
483 strcat(linkmsg
, "10 Mbps, ");
485 case PHY_LINK_SPEED_100M
:
486 jme
->reg_ghc
|= GHC_SPEED_100M
;
487 strcat(linkmsg
, "100 Mbps, ");
489 case PHY_LINK_SPEED_1000M
:
490 jme
->reg_ghc
|= GHC_SPEED_1000M
;
491 strcat(linkmsg
, "1000 Mbps, ");
497 if (phylink
& PHY_LINK_DUPLEX
) {
498 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
);
499 jwrite32(jme
, JME_TXTRHD
, TXTRHD_FULLDUPLEX
);
500 jme
->reg_ghc
|= GHC_DPX
;
502 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
|
506 jwrite32(jme
, JME_TXTRHD
, TXTRHD_HALFDUPLEX
);
509 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
);
511 if (is_buggy250(jme
->pdev
->device
, jme
->chiprev
)) {
512 jme
->reg_gpreg1
&= ~(GPREG1_HALFMODEPATCH
|
514 if (!(phylink
& PHY_LINK_DUPLEX
))
515 jme
->reg_gpreg1
|= GPREG1_HALFMODEPATCH
;
516 switch (phylink
& PHY_LINK_SPEED_MASK
) {
517 case PHY_LINK_SPEED_10M
:
518 jme_set_phyfifo_8level(jme
);
519 jme
->reg_gpreg1
|= GPREG1_RSSPATCH
;
521 case PHY_LINK_SPEED_100M
:
522 jme_set_phyfifo_5level(jme
);
523 jme
->reg_gpreg1
|= GPREG1_RSSPATCH
;
525 case PHY_LINK_SPEED_1000M
:
526 jme_set_phyfifo_8level(jme
);
532 jwrite32(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
534 strcat(linkmsg
, (phylink
& PHY_LINK_DUPLEX
) ?
537 strcat(linkmsg
, (phylink
& PHY_LINK_MDI_STAT
) ?
540 netif_info(jme
, link
, jme
->dev
, "Link is up at %s\n", linkmsg
);
541 netif_carrier_on(netdev
);
546 netif_info(jme
, link
, jme
->dev
, "Link is down\n");
548 netif_carrier_off(netdev
);
556 jme_setup_tx_resources(struct jme_adapter
*jme
)
558 struct jme_ring
*txring
= &(jme
->txring
[0]);
560 txring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
561 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
571 txring
->desc
= (void *)ALIGN((unsigned long)(txring
->alloc
),
573 txring
->dma
= ALIGN(txring
->dmaalloc
, RING_DESC_ALIGN
);
574 txring
->next_to_use
= 0;
575 atomic_set(&txring
->next_to_clean
, 0);
576 atomic_set(&txring
->nr_free
, jme
->tx_ring_size
);
578 txring
->bufinf
= kcalloc(jme
->tx_ring_size
,
579 sizeof(struct jme_buffer_info
),
581 if (unlikely(!(txring
->bufinf
)))
582 goto err_free_txring
;
587 dma_free_coherent(&(jme
->pdev
->dev
),
588 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
594 txring
->dmaalloc
= 0;
596 txring
->bufinf
= NULL
;
602 jme_free_tx_resources(struct jme_adapter
*jme
)
605 struct jme_ring
*txring
= &(jme
->txring
[0]);
606 struct jme_buffer_info
*txbi
;
609 if (txring
->bufinf
) {
610 for (i
= 0 ; i
< jme
->tx_ring_size
; ++i
) {
611 txbi
= txring
->bufinf
+ i
;
613 dev_kfree_skb(txbi
->skb
);
619 txbi
->start_xmit
= 0;
621 kfree(txring
->bufinf
);
624 dma_free_coherent(&(jme
->pdev
->dev
),
625 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
629 txring
->alloc
= NULL
;
631 txring
->dmaalloc
= 0;
633 txring
->bufinf
= NULL
;
635 txring
->next_to_use
= 0;
636 atomic_set(&txring
->next_to_clean
, 0);
637 atomic_set(&txring
->nr_free
, 0);
641 jme_enable_tx_engine(struct jme_adapter
*jme
)
646 jwrite32(jme
, JME_TXCS
, TXCS_DEFAULT
| TXCS_SELECT_QUEUE0
);
650 * Setup TX Queue 0 DMA Bass Address
652 jwrite32(jme
, JME_TXDBA_LO
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
653 jwrite32(jme
, JME_TXDBA_HI
, (__u64
)(jme
->txring
[0].dma
) >> 32);
654 jwrite32(jme
, JME_TXNDA
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
657 * Setup TX Descptor Count
659 jwrite32(jme
, JME_TXQDC
, jme
->tx_ring_size
);
665 jwrite32f(jme
, JME_TXCS
, jme
->reg_txcs
|
670 * Start clock for TX MAC Processor
672 jme_mac_txclk_on(jme
);
676 jme_disable_tx_engine(struct jme_adapter
*jme
)
684 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
| TXCS_SELECT_QUEUE0
);
687 val
= jread32(jme
, JME_TXCS
);
688 for (i
= JME_TX_DISABLE_TIMEOUT
; (val
& TXCS_ENABLE
) && i
> 0 ; --i
) {
690 val
= jread32(jme
, JME_TXCS
);
695 pr_err("Disable TX engine timeout\n");
698 * Stop clock for TX MAC Processor
700 jme_mac_txclk_off(jme
);
704 jme_set_clean_rxdesc(struct jme_adapter
*jme
, int i
)
706 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
707 register struct rxdesc
*rxdesc
= rxring
->desc
;
708 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
714 rxdesc
->desc1
.bufaddrh
= cpu_to_le32((__u64
)rxbi
->mapping
>> 32);
715 rxdesc
->desc1
.bufaddrl
= cpu_to_le32(
716 (__u64
)rxbi
->mapping
& 0xFFFFFFFFUL
);
717 rxdesc
->desc1
.datalen
= cpu_to_le16(rxbi
->len
);
718 if (jme
->dev
->features
& NETIF_F_HIGHDMA
)
719 rxdesc
->desc1
.flags
= RXFLAG_64BIT
;
721 rxdesc
->desc1
.flags
|= RXFLAG_OWN
| RXFLAG_INT
;
725 jme_make_new_rx_buf(struct jme_adapter
*jme
, int i
)
727 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
728 struct jme_buffer_info
*rxbi
= rxring
->bufinf
+ i
;
732 skb
= netdev_alloc_skb(jme
->dev
,
733 jme
->dev
->mtu
+ RX_EXTRA_LEN
);
737 mapping
= pci_map_page(jme
->pdev
, virt_to_page(skb
->data
),
738 offset_in_page(skb
->data
), skb_tailroom(skb
),
740 if (unlikely(pci_dma_mapping_error(jme
->pdev
, mapping
))) {
745 if (likely(rxbi
->mapping
))
746 pci_unmap_page(jme
->pdev
, rxbi
->mapping
,
747 rxbi
->len
, PCI_DMA_FROMDEVICE
);
750 rxbi
->len
= skb_tailroom(skb
);
751 rxbi
->mapping
= mapping
;
756 jme_free_rx_buf(struct jme_adapter
*jme
, int i
)
758 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
759 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
763 pci_unmap_page(jme
->pdev
,
767 dev_kfree_skb(rxbi
->skb
);
775 jme_free_rx_resources(struct jme_adapter
*jme
)
778 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
781 if (rxring
->bufinf
) {
782 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
)
783 jme_free_rx_buf(jme
, i
);
784 kfree(rxring
->bufinf
);
787 dma_free_coherent(&(jme
->pdev
->dev
),
788 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
791 rxring
->alloc
= NULL
;
793 rxring
->dmaalloc
= 0;
795 rxring
->bufinf
= NULL
;
797 rxring
->next_to_use
= 0;
798 atomic_set(&rxring
->next_to_clean
, 0);
802 jme_setup_rx_resources(struct jme_adapter
*jme
)
805 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
807 rxring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
808 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
817 rxring
->desc
= (void *)ALIGN((unsigned long)(rxring
->alloc
),
819 rxring
->dma
= ALIGN(rxring
->dmaalloc
, RING_DESC_ALIGN
);
820 rxring
->next_to_use
= 0;
821 atomic_set(&rxring
->next_to_clean
, 0);
823 rxring
->bufinf
= kcalloc(jme
->rx_ring_size
,
824 sizeof(struct jme_buffer_info
),
826 if (unlikely(!(rxring
->bufinf
)))
827 goto err_free_rxring
;
830 * Initiallize Receive Descriptors
832 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
) {
833 if (unlikely(jme_make_new_rx_buf(jme
, i
))) {
834 jme_free_rx_resources(jme
);
838 jme_set_clean_rxdesc(jme
, i
);
844 dma_free_coherent(&(jme
->pdev
->dev
),
845 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
850 rxring
->dmaalloc
= 0;
852 rxring
->bufinf
= NULL
;
858 jme_enable_rx_engine(struct jme_adapter
*jme
)
863 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
868 * Setup RX DMA Bass Address
870 jwrite32(jme
, JME_RXDBA_LO
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
871 jwrite32(jme
, JME_RXDBA_HI
, (__u64
)(jme
->rxring
[0].dma
) >> 32);
872 jwrite32(jme
, JME_RXNDA
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
875 * Setup RX Descriptor Count
877 jwrite32(jme
, JME_RXQDC
, jme
->rx_ring_size
);
880 * Setup Unicast Filter
882 jme_set_unicastaddr(jme
->dev
);
883 jme_set_multi(jme
->dev
);
889 jwrite32f(jme
, JME_RXCS
, jme
->reg_rxcs
|
895 * Start clock for RX MAC Processor
897 jme_mac_rxclk_on(jme
);
901 jme_restart_rx_engine(struct jme_adapter
*jme
)
906 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
913 jme_disable_rx_engine(struct jme_adapter
*jme
)
921 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
);
924 val
= jread32(jme
, JME_RXCS
);
925 for (i
= JME_RX_DISABLE_TIMEOUT
; (val
& RXCS_ENABLE
) && i
> 0 ; --i
) {
927 val
= jread32(jme
, JME_RXCS
);
932 pr_err("Disable RX engine timeout\n");
935 * Stop clock for RX MAC Processor
937 jme_mac_rxclk_off(jme
);
941 jme_udpsum(struct sk_buff
*skb
)
945 if (skb
->len
< (ETH_HLEN
+ sizeof(struct iphdr
)))
947 if (skb
->protocol
!= htons(ETH_P_IP
))
949 skb_set_network_header(skb
, ETH_HLEN
);
950 if ((ip_hdr(skb
)->protocol
!= IPPROTO_UDP
) ||
951 (skb
->len
< (ETH_HLEN
+
952 (ip_hdr(skb
)->ihl
<< 2) +
953 sizeof(struct udphdr
)))) {
954 skb_reset_network_header(skb
);
957 skb_set_transport_header(skb
,
958 ETH_HLEN
+ (ip_hdr(skb
)->ihl
<< 2));
959 csum
= udp_hdr(skb
)->check
;
960 skb_reset_transport_header(skb
);
961 skb_reset_network_header(skb
);
967 jme_rxsum_ok(struct jme_adapter
*jme
, u16 flags
, struct sk_buff
*skb
)
969 if (!(flags
& (RXWBFLAG_TCPON
| RXWBFLAG_UDPON
| RXWBFLAG_IPV4
)))
972 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_TCPON
| RXWBFLAG_TCPCS
))
973 == RXWBFLAG_TCPON
)) {
974 if (flags
& RXWBFLAG_IPV4
)
975 netif_err(jme
, rx_err
, jme
->dev
, "TCP Checksum error\n");
979 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_UDPON
| RXWBFLAG_UDPCS
))
980 == RXWBFLAG_UDPON
) && jme_udpsum(skb
)) {
981 if (flags
& RXWBFLAG_IPV4
)
982 netif_err(jme
, rx_err
, jme
->dev
, "UDP Checksum error\n");
986 if (unlikely((flags
& (RXWBFLAG_IPV4
| RXWBFLAG_IPCS
))
988 netif_err(jme
, rx_err
, jme
->dev
, "IPv4 Checksum error\n");
996 jme_alloc_and_feed_skb(struct jme_adapter
*jme
, int idx
)
998 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
999 struct rxdesc
*rxdesc
= rxring
->desc
;
1000 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
1001 struct sk_buff
*skb
;
1008 pci_dma_sync_single_for_cpu(jme
->pdev
,
1011 PCI_DMA_FROMDEVICE
);
1013 if (unlikely(jme_make_new_rx_buf(jme
, idx
))) {
1014 pci_dma_sync_single_for_device(jme
->pdev
,
1017 PCI_DMA_FROMDEVICE
);
1019 ++(NET_STAT(jme
).rx_dropped
);
1021 framesize
= le16_to_cpu(rxdesc
->descwb
.framesize
)
1024 skb_reserve(skb
, RX_PREPAD_SIZE
);
1025 skb_put(skb
, framesize
);
1026 skb
->protocol
= eth_type_trans(skb
, jme
->dev
);
1028 if (jme_rxsum_ok(jme
, le16_to_cpu(rxdesc
->descwb
.flags
), skb
))
1029 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1031 skb_checksum_none_assert(skb
);
1033 if (rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_TAGON
)) {
1034 u16 vid
= le16_to_cpu(rxdesc
->descwb
.vlan
);
1036 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vid
);
1037 NET_STAT(jme
).rx_bytes
+= 4;
1041 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_DEST
)) ==
1042 cpu_to_le16(RXWBFLAG_DEST_MUL
))
1043 ++(NET_STAT(jme
).multicast
);
1045 NET_STAT(jme
).rx_bytes
+= framesize
;
1046 ++(NET_STAT(jme
).rx_packets
);
1049 jme_set_clean_rxdesc(jme
, idx
);
1054 jme_process_receive(struct jme_adapter
*jme
, int limit
)
1056 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
1057 struct rxdesc
*rxdesc
;
1058 int i
, j
, ccnt
, desccnt
, mask
= jme
->rx_ring_mask
;
1060 if (unlikely(!atomic_dec_and_test(&jme
->rx_cleaning
)))
1063 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1066 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1069 i
= atomic_read(&rxring
->next_to_clean
);
1071 rxdesc
= rxring
->desc
;
1074 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_OWN
)) ||
1075 !(rxdesc
->descwb
.desccnt
& RXWBDCNT_WBCPL
))
1080 desccnt
= rxdesc
->descwb
.desccnt
& RXWBDCNT_DCNT
;
1082 if (unlikely(desccnt
> 1 ||
1083 rxdesc
->descwb
.errstat
& RXWBERR_ALLERR
)) {
1085 if (rxdesc
->descwb
.errstat
& RXWBERR_CRCERR
)
1086 ++(NET_STAT(jme
).rx_crc_errors
);
1087 else if (rxdesc
->descwb
.errstat
& RXWBERR_OVERUN
)
1088 ++(NET_STAT(jme
).rx_fifo_errors
);
1090 ++(NET_STAT(jme
).rx_errors
);
1093 limit
-= desccnt
- 1;
1095 for (j
= i
, ccnt
= desccnt
; ccnt
-- ; ) {
1096 jme_set_clean_rxdesc(jme
, j
);
1097 j
= (j
+ 1) & (mask
);
1101 jme_alloc_and_feed_skb(jme
, i
);
1104 i
= (i
+ desccnt
) & (mask
);
1108 atomic_set(&rxring
->next_to_clean
, i
);
1111 atomic_inc(&jme
->rx_cleaning
);
1113 return limit
> 0 ? limit
: 0;
1118 jme_attempt_pcc(struct dynpcc_info
*dpi
, int atmp
)
1120 if (likely(atmp
== dpi
->cur
)) {
1125 if (dpi
->attempt
== atmp
) {
1128 dpi
->attempt
= atmp
;
1135 jme_dynamic_pcc(struct jme_adapter
*jme
)
1137 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
1139 if ((NET_STAT(jme
).rx_bytes
- dpi
->last_bytes
) > PCC_P3_THRESHOLD
)
1140 jme_attempt_pcc(dpi
, PCC_P3
);
1141 else if ((NET_STAT(jme
).rx_packets
- dpi
->last_pkts
) > PCC_P2_THRESHOLD
||
1142 dpi
->intr_cnt
> PCC_INTR_THRESHOLD
)
1143 jme_attempt_pcc(dpi
, PCC_P2
);
1145 jme_attempt_pcc(dpi
, PCC_P1
);
1147 if (unlikely(dpi
->attempt
!= dpi
->cur
&& dpi
->cnt
> 5)) {
1148 if (dpi
->attempt
< dpi
->cur
)
1149 tasklet_schedule(&jme
->rxclean_task
);
1150 jme_set_rx_pcc(jme
, dpi
->attempt
);
1151 dpi
->cur
= dpi
->attempt
;
1157 jme_start_pcc_timer(struct jme_adapter
*jme
)
1159 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1160 dpi
->last_bytes
= NET_STAT(jme
).rx_bytes
;
1161 dpi
->last_pkts
= NET_STAT(jme
).rx_packets
;
1163 jwrite32(jme
, JME_TMCSR
,
1164 TMCSR_EN
| ((0xFFFFFF - PCC_INTERVAL_US
) & TMCSR_CNT
));
1168 jme_stop_pcc_timer(struct jme_adapter
*jme
)
1170 jwrite32(jme
, JME_TMCSR
, 0);
1174 jme_shutdown_nic(struct jme_adapter
*jme
)
1178 phylink
= jme_linkstat_from_phy(jme
);
1180 if (!(phylink
& PHY_LINK_UP
)) {
1182 * Disable all interrupt before issue timer
1185 jwrite32(jme
, JME_TIMER2
, TMCSR_EN
| 0xFFFFFE);
1190 jme_pcc_tasklet(unsigned long arg
)
1192 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1193 struct net_device
*netdev
= jme
->dev
;
1195 if (unlikely(test_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
))) {
1196 jme_shutdown_nic(jme
);
1200 if (unlikely(!netif_carrier_ok(netdev
) ||
1201 (atomic_read(&jme
->link_changing
) != 1)
1203 jme_stop_pcc_timer(jme
);
1207 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
1208 jme_dynamic_pcc(jme
);
1210 jme_start_pcc_timer(jme
);
1214 jme_polling_mode(struct jme_adapter
*jme
)
1216 jme_set_rx_pcc(jme
, PCC_OFF
);
1220 jme_interrupt_mode(struct jme_adapter
*jme
)
1222 jme_set_rx_pcc(jme
, PCC_P1
);
1226 jme_pseudo_hotplug_enabled(struct jme_adapter
*jme
)
1229 apmc
= jread32(jme
, JME_APMC
);
1230 return apmc
& JME_APMC_PSEUDO_HP_EN
;
1234 jme_start_shutdown_timer(struct jme_adapter
*jme
)
1238 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PCIE_SD_EN
;
1239 apmc
&= ~JME_APMC_EPIEN_CTRL
;
1241 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_EN
);
1244 jwrite32f(jme
, JME_APMC
, apmc
);
1246 jwrite32f(jme
, JME_TIMER2
, 0);
1247 set_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1248 jwrite32(jme
, JME_TMCSR
,
1249 TMCSR_EN
| ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY
) & TMCSR_CNT
));
1253 jme_stop_shutdown_timer(struct jme_adapter
*jme
)
1257 jwrite32f(jme
, JME_TMCSR
, 0);
1258 jwrite32f(jme
, JME_TIMER2
, 0);
1259 clear_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1261 apmc
= jread32(jme
, JME_APMC
);
1262 apmc
&= ~(JME_APMC_PCIE_SD_EN
| JME_APMC_EPIEN_CTRL
);
1263 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_DIS
);
1265 jwrite32f(jme
, JME_APMC
, apmc
);
1269 jme_link_change_tasklet(unsigned long arg
)
1271 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1272 struct net_device
*netdev
= jme
->dev
;
1275 while (!atomic_dec_and_test(&jme
->link_changing
)) {
1276 atomic_inc(&jme
->link_changing
);
1277 netif_info(jme
, intr
, jme
->dev
, "Get link change lock failed\n");
1278 while (atomic_read(&jme
->link_changing
) != 1)
1279 netif_info(jme
, intr
, jme
->dev
, "Waiting link change lock\n");
1282 if (jme_check_link(netdev
, 1) && jme
->old_mtu
== netdev
->mtu
)
1285 jme
->old_mtu
= netdev
->mtu
;
1286 netif_stop_queue(netdev
);
1287 if (jme_pseudo_hotplug_enabled(jme
))
1288 jme_stop_shutdown_timer(jme
);
1290 jme_stop_pcc_timer(jme
);
1291 tasklet_disable(&jme
->txclean_task
);
1292 tasklet_disable(&jme
->rxclean_task
);
1293 tasklet_disable(&jme
->rxempty_task
);
1295 if (netif_carrier_ok(netdev
)) {
1296 jme_disable_rx_engine(jme
);
1297 jme_disable_tx_engine(jme
);
1298 jme_reset_mac_processor(jme
);
1299 jme_free_rx_resources(jme
);
1300 jme_free_tx_resources(jme
);
1302 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1303 jme_polling_mode(jme
);
1305 netif_carrier_off(netdev
);
1308 jme_check_link(netdev
, 0);
1309 if (netif_carrier_ok(netdev
)) {
1310 rc
= jme_setup_rx_resources(jme
);
1312 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1313 goto out_enable_tasklet
;
1316 rc
= jme_setup_tx_resources(jme
);
1318 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1319 goto err_out_free_rx_resources
;
1322 jme_enable_rx_engine(jme
);
1323 jme_enable_tx_engine(jme
);
1325 netif_start_queue(netdev
);
1327 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1328 jme_interrupt_mode(jme
);
1330 jme_start_pcc_timer(jme
);
1331 } else if (jme_pseudo_hotplug_enabled(jme
)) {
1332 jme_start_shutdown_timer(jme
);
1335 goto out_enable_tasklet
;
1337 err_out_free_rx_resources
:
1338 jme_free_rx_resources(jme
);
1340 tasklet_enable(&jme
->txclean_task
);
1341 tasklet_enable(&jme
->rxclean_task
);
1342 tasklet_enable(&jme
->rxempty_task
);
1344 atomic_inc(&jme
->link_changing
);
1348 jme_rx_clean_tasklet(unsigned long arg
)
1350 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1351 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1353 jme_process_receive(jme
, jme
->rx_ring_size
);
1359 jme_poll(JME_NAPI_HOLDER(holder
), JME_NAPI_WEIGHT(budget
))
1361 struct jme_adapter
*jme
= jme_napi_priv(holder
);
1364 rest
= jme_process_receive(jme
, JME_NAPI_WEIGHT_VAL(budget
));
1366 while (atomic_read(&jme
->rx_empty
) > 0) {
1367 atomic_dec(&jme
->rx_empty
);
1368 ++(NET_STAT(jme
).rx_dropped
);
1369 jme_restart_rx_engine(jme
);
1371 atomic_inc(&jme
->rx_empty
);
1374 JME_RX_COMPLETE(netdev
, holder
);
1375 jme_interrupt_mode(jme
);
1378 JME_NAPI_WEIGHT_SET(budget
, rest
);
1379 return JME_NAPI_WEIGHT_VAL(budget
) - rest
;
1383 jme_rx_empty_tasklet(unsigned long arg
)
1385 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1387 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1390 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1393 netif_info(jme
, rx_status
, jme
->dev
, "RX Queue Full!\n");
1395 jme_rx_clean_tasklet(arg
);
1397 while (atomic_read(&jme
->rx_empty
) > 0) {
1398 atomic_dec(&jme
->rx_empty
);
1399 ++(NET_STAT(jme
).rx_dropped
);
1400 jme_restart_rx_engine(jme
);
1402 atomic_inc(&jme
->rx_empty
);
1406 jme_wake_queue_if_stopped(struct jme_adapter
*jme
)
1408 struct jme_ring
*txring
= &(jme
->txring
[0]);
1411 if (unlikely(netif_queue_stopped(jme
->dev
) &&
1412 atomic_read(&txring
->nr_free
) >= (jme
->tx_wake_threshold
))) {
1413 netif_info(jme
, tx_done
, jme
->dev
, "TX Queue Waked\n");
1414 netif_wake_queue(jme
->dev
);
1420 jme_tx_clean_tasklet(unsigned long arg
)
1422 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1423 struct jme_ring
*txring
= &(jme
->txring
[0]);
1424 struct txdesc
*txdesc
= txring
->desc
;
1425 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
, *ttxbi
;
1426 int i
, j
, cnt
= 0, max
, err
, mask
;
1428 tx_dbg(jme
, "Into txclean\n");
1430 if (unlikely(!atomic_dec_and_test(&jme
->tx_cleaning
)))
1433 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1436 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1439 max
= jme
->tx_ring_size
- atomic_read(&txring
->nr_free
);
1440 mask
= jme
->tx_ring_mask
;
1442 for (i
= atomic_read(&txring
->next_to_clean
) ; cnt
< max
; ) {
1446 if (likely(ctxbi
->skb
&&
1447 !(txdesc
[i
].descwb
.flags
& TXWBFLAG_OWN
))) {
1449 tx_dbg(jme
, "txclean: %d+%d@%lu\n",
1450 i
, ctxbi
->nr_desc
, jiffies
);
1452 err
= txdesc
[i
].descwb
.flags
& TXWBFLAG_ALLERR
;
1454 for (j
= 1 ; j
< ctxbi
->nr_desc
; ++j
) {
1455 ttxbi
= txbi
+ ((i
+ j
) & (mask
));
1456 txdesc
[(i
+ j
) & (mask
)].dw
[0] = 0;
1458 pci_unmap_page(jme
->pdev
,
1467 dev_kfree_skb(ctxbi
->skb
);
1469 cnt
+= ctxbi
->nr_desc
;
1471 if (unlikely(err
)) {
1472 ++(NET_STAT(jme
).tx_carrier_errors
);
1474 ++(NET_STAT(jme
).tx_packets
);
1475 NET_STAT(jme
).tx_bytes
+= ctxbi
->len
;
1480 ctxbi
->start_xmit
= 0;
1486 i
= (i
+ ctxbi
->nr_desc
) & mask
;
1491 tx_dbg(jme
, "txclean: done %d@%lu\n", i
, jiffies
);
1492 atomic_set(&txring
->next_to_clean
, i
);
1493 atomic_add(cnt
, &txring
->nr_free
);
1495 jme_wake_queue_if_stopped(jme
);
1498 atomic_inc(&jme
->tx_cleaning
);
1502 jme_intr_msi(struct jme_adapter
*jme
, u32 intrstat
)
1507 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
1509 if (intrstat
& (INTR_LINKCH
| INTR_SWINTR
)) {
1511 * Link change event is critical
1512 * all other events are ignored
1514 jwrite32(jme
, JME_IEVE
, intrstat
);
1515 tasklet_schedule(&jme
->linkch_task
);
1519 if (intrstat
& INTR_TMINTR
) {
1520 jwrite32(jme
, JME_IEVE
, INTR_TMINTR
);
1521 tasklet_schedule(&jme
->pcc_task
);
1524 if (intrstat
& (INTR_PCCTXTO
| INTR_PCCTX
)) {
1525 jwrite32(jme
, JME_IEVE
, INTR_PCCTXTO
| INTR_PCCTX
| INTR_TX0
);
1526 tasklet_schedule(&jme
->txclean_task
);
1529 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1530 jwrite32(jme
, JME_IEVE
, (intrstat
& (INTR_PCCRX0TO
|
1536 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
1537 if (intrstat
& INTR_RX0EMP
)
1538 atomic_inc(&jme
->rx_empty
);
1540 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1541 if (likely(JME_RX_SCHEDULE_PREP(jme
))) {
1542 jme_polling_mode(jme
);
1543 JME_RX_SCHEDULE(jme
);
1547 if (intrstat
& INTR_RX0EMP
) {
1548 atomic_inc(&jme
->rx_empty
);
1549 tasklet_hi_schedule(&jme
->rxempty_task
);
1550 } else if (intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
)) {
1551 tasklet_hi_schedule(&jme
->rxclean_task
);
1557 * Re-enable interrupt
1559 jwrite32f(jme
, JME_IENS
, INTR_ENABLE
);
1563 jme_intr(int irq
, void *dev_id
)
1565 struct net_device
*netdev
= dev_id
;
1566 struct jme_adapter
*jme
= netdev_priv(netdev
);
1569 intrstat
= jread32(jme
, JME_IEVE
);
1572 * Check if it's really an interrupt for us
1574 if (unlikely((intrstat
& INTR_ENABLE
) == 0))
1578 * Check if the device still exist
1580 if (unlikely(intrstat
== ~((typeof(intrstat
))0)))
1583 jme_intr_msi(jme
, intrstat
);
1589 jme_msi(int irq
, void *dev_id
)
1591 struct net_device
*netdev
= dev_id
;
1592 struct jme_adapter
*jme
= netdev_priv(netdev
);
1595 intrstat
= jread32(jme
, JME_IEVE
);
1597 jme_intr_msi(jme
, intrstat
);
1603 jme_reset_link(struct jme_adapter
*jme
)
1605 jwrite32(jme
, JME_TMCSR
, TMCSR_SWIT
);
1609 jme_restart_an(struct jme_adapter
*jme
)
1613 spin_lock_bh(&jme
->phy_lock
);
1614 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1615 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1616 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1617 spin_unlock_bh(&jme
->phy_lock
);
1621 jme_request_irq(struct jme_adapter
*jme
)
1624 struct net_device
*netdev
= jme
->dev
;
1625 irq_handler_t handler
= jme_intr
;
1626 int irq_flags
= IRQF_SHARED
;
1628 if (!pci_enable_msi(jme
->pdev
)) {
1629 set_bit(JME_FLAG_MSI
, &jme
->flags
);
1634 rc
= request_irq(jme
->pdev
->irq
, handler
, irq_flags
, netdev
->name
,
1638 "Unable to request %s interrupt (return: %d)\n",
1639 test_bit(JME_FLAG_MSI
, &jme
->flags
) ? "MSI" : "INTx",
1642 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1643 pci_disable_msi(jme
->pdev
);
1644 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1647 netdev
->irq
= jme
->pdev
->irq
;
1654 jme_free_irq(struct jme_adapter
*jme
)
1656 free_irq(jme
->pdev
->irq
, jme
->dev
);
1657 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1658 pci_disable_msi(jme
->pdev
);
1659 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1660 jme
->dev
->irq
= jme
->pdev
->irq
;
1665 jme_new_phy_on(struct jme_adapter
*jme
)
1669 reg
= jread32(jme
, JME_PHY_PWR
);
1670 reg
&= ~(PHY_PWR_DWN1SEL
| PHY_PWR_DWN1SW
|
1671 PHY_PWR_DWN2
| PHY_PWR_CLKSEL
);
1672 jwrite32(jme
, JME_PHY_PWR
, reg
);
1674 pci_read_config_dword(jme
->pdev
, PCI_PRIV_PE1
, ®
);
1675 reg
&= ~PE1_GPREG0_PBG
;
1676 reg
|= PE1_GPREG0_ENBG
;
1677 pci_write_config_dword(jme
->pdev
, PCI_PRIV_PE1
, reg
);
1681 jme_new_phy_off(struct jme_adapter
*jme
)
1685 reg
= jread32(jme
, JME_PHY_PWR
);
1686 reg
|= PHY_PWR_DWN1SEL
| PHY_PWR_DWN1SW
|
1687 PHY_PWR_DWN2
| PHY_PWR_CLKSEL
;
1688 jwrite32(jme
, JME_PHY_PWR
, reg
);
1690 pci_read_config_dword(jme
->pdev
, PCI_PRIV_PE1
, ®
);
1691 reg
&= ~PE1_GPREG0_PBG
;
1692 reg
|= PE1_GPREG0_PDD3COLD
;
1693 pci_write_config_dword(jme
->pdev
, PCI_PRIV_PE1
, reg
);
1697 jme_phy_on(struct jme_adapter
*jme
)
1701 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1702 bmcr
&= ~BMCR_PDOWN
;
1703 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1705 if (new_phy_power_ctrl(jme
->chip_main_rev
))
1706 jme_new_phy_on(jme
);
1710 jme_phy_off(struct jme_adapter
*jme
)
1714 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1716 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1718 if (new_phy_power_ctrl(jme
->chip_main_rev
))
1719 jme_new_phy_off(jme
);
1723 jme_phy_specreg_read(struct jme_adapter
*jme
, u32 specreg
)
1727 phy_addr
= JM_PHY_SPEC_REG_READ
| specreg
;
1728 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, JM_PHY_SPEC_ADDR_REG
,
1730 return jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
,
1731 JM_PHY_SPEC_DATA_REG
);
1735 jme_phy_specreg_write(struct jme_adapter
*jme
, u32 ext_reg
, u32 phy_data
)
1739 phy_addr
= JM_PHY_SPEC_REG_WRITE
| ext_reg
;
1740 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, JM_PHY_SPEC_DATA_REG
,
1742 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, JM_PHY_SPEC_ADDR_REG
,
1747 jme_phy_calibration(struct jme_adapter
*jme
)
1749 u32 ctrl1000
, phy_data
;
1753 /* Enabel PHY test mode 1 */
1754 ctrl1000
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
);
1755 ctrl1000
&= ~PHY_GAD_TEST_MODE_MSK
;
1756 ctrl1000
|= PHY_GAD_TEST_MODE_1
;
1757 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
, ctrl1000
);
1759 phy_data
= jme_phy_specreg_read(jme
, JM_PHY_EXT_COMM_2_REG
);
1760 phy_data
&= ~JM_PHY_EXT_COMM_2_CALI_MODE_0
;
1761 phy_data
|= JM_PHY_EXT_COMM_2_CALI_LATCH
|
1762 JM_PHY_EXT_COMM_2_CALI_ENABLE
;
1763 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_2_REG
, phy_data
);
1765 phy_data
= jme_phy_specreg_read(jme
, JM_PHY_EXT_COMM_2_REG
);
1766 phy_data
&= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE
|
1767 JM_PHY_EXT_COMM_2_CALI_MODE_0
|
1768 JM_PHY_EXT_COMM_2_CALI_LATCH
);
1769 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_2_REG
, phy_data
);
1771 /* Disable PHY test mode */
1772 ctrl1000
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
);
1773 ctrl1000
&= ~PHY_GAD_TEST_MODE_MSK
;
1774 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
, ctrl1000
);
1779 jme_phy_setEA(struct jme_adapter
*jme
)
1781 u32 phy_comm0
= 0, phy_comm1
= 0;
1784 pci_read_config_byte(jme
->pdev
, PCI_PRIV_SHARE_NICCTRL
, &nic_ctrl
);
1785 if ((nic_ctrl
& 0x3) == JME_FLAG_PHYEA_ENABLE
)
1788 switch (jme
->pdev
->device
) {
1789 case PCI_DEVICE_ID_JMICRON_JMC250
:
1790 if (((jme
->chip_main_rev
== 5) &&
1791 ((jme
->chip_sub_rev
== 0) || (jme
->chip_sub_rev
== 1) ||
1792 (jme
->chip_sub_rev
== 3))) ||
1793 (jme
->chip_main_rev
>= 6)) {
1797 if ((jme
->chip_main_rev
== 3) &&
1798 ((jme
->chip_sub_rev
== 1) || (jme
->chip_sub_rev
== 2)))
1801 case PCI_DEVICE_ID_JMICRON_JMC260
:
1802 if (((jme
->chip_main_rev
== 5) &&
1803 ((jme
->chip_sub_rev
== 0) || (jme
->chip_sub_rev
== 1) ||
1804 (jme
->chip_sub_rev
== 3))) ||
1805 (jme
->chip_main_rev
>= 6)) {
1809 if ((jme
->chip_main_rev
== 3) &&
1810 ((jme
->chip_sub_rev
== 1) || (jme
->chip_sub_rev
== 2)))
1812 if ((jme
->chip_main_rev
== 2) && (jme
->chip_sub_rev
== 0))
1814 if ((jme
->chip_main_rev
== 2) && (jme
->chip_sub_rev
== 2))
1821 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_0_REG
, phy_comm0
);
1823 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_1_REG
, phy_comm1
);
1829 jme_open(struct net_device
*netdev
)
1831 struct jme_adapter
*jme
= netdev_priv(netdev
);
1834 jme_clear_pm_disable_wol(jme
);
1835 JME_NAPI_ENABLE(jme
);
1837 tasklet_init(&jme
->linkch_task
, jme_link_change_tasklet
,
1838 (unsigned long) jme
);
1839 tasklet_init(&jme
->txclean_task
, jme_tx_clean_tasklet
,
1840 (unsigned long) jme
);
1841 tasklet_init(&jme
->rxclean_task
, jme_rx_clean_tasklet
,
1842 (unsigned long) jme
);
1843 tasklet_init(&jme
->rxempty_task
, jme_rx_empty_tasklet
,
1844 (unsigned long) jme
);
1846 rc
= jme_request_irq(jme
);
1853 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
1854 jme_set_link_ksettings(netdev
, &jme
->old_cmd
);
1856 jme_reset_phy_processor(jme
);
1857 jme_phy_calibration(jme
);
1859 jme_reset_link(jme
);
1864 netif_stop_queue(netdev
);
1865 netif_carrier_off(netdev
);
1870 jme_set_100m_half(struct jme_adapter
*jme
)
1875 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1876 tmp
= bmcr
& ~(BMCR_ANENABLE
| BMCR_SPEED100
|
1877 BMCR_SPEED1000
| BMCR_FULLDPLX
);
1878 tmp
|= BMCR_SPEED100
;
1881 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, tmp
);
1884 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
| GHC_LINK_POLL
);
1886 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
);
1889 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1891 jme_wait_link(struct jme_adapter
*jme
)
1893 u32 phylink
, to
= JME_WAIT_LINK_TIME
;
1896 phylink
= jme_linkstat_from_phy(jme
);
1897 while (!(phylink
& PHY_LINK_UP
) && (to
-= 10) > 0) {
1898 usleep_range(10000, 11000);
1899 phylink
= jme_linkstat_from_phy(jme
);
1904 jme_powersave_phy(struct jme_adapter
*jme
)
1906 if (jme
->reg_pmcs
&& device_may_wakeup(&jme
->pdev
->dev
)) {
1907 jme_set_100m_half(jme
);
1908 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
1910 jme_clear_pm_enable_wol(jme
);
1917 jme_close(struct net_device
*netdev
)
1919 struct jme_adapter
*jme
= netdev_priv(netdev
);
1921 netif_stop_queue(netdev
);
1922 netif_carrier_off(netdev
);
1927 JME_NAPI_DISABLE(jme
);
1929 tasklet_kill(&jme
->linkch_task
);
1930 tasklet_kill(&jme
->txclean_task
);
1931 tasklet_kill(&jme
->rxclean_task
);
1932 tasklet_kill(&jme
->rxempty_task
);
1934 jme_disable_rx_engine(jme
);
1935 jme_disable_tx_engine(jme
);
1936 jme_reset_mac_processor(jme
);
1937 jme_free_rx_resources(jme
);
1938 jme_free_tx_resources(jme
);
1946 jme_alloc_txdesc(struct jme_adapter
*jme
,
1947 struct sk_buff
*skb
)
1949 struct jme_ring
*txring
= &(jme
->txring
[0]);
1950 int idx
, nr_alloc
, mask
= jme
->tx_ring_mask
;
1952 idx
= txring
->next_to_use
;
1953 nr_alloc
= skb_shinfo(skb
)->nr_frags
+ 2;
1955 if (unlikely(atomic_read(&txring
->nr_free
) < nr_alloc
))
1958 atomic_sub(nr_alloc
, &txring
->nr_free
);
1960 txring
->next_to_use
= (txring
->next_to_use
+ nr_alloc
) & mask
;
1966 jme_fill_tx_map(struct pci_dev
*pdev
,
1967 struct txdesc
*txdesc
,
1968 struct jme_buffer_info
*txbi
,
1976 dmaaddr
= pci_map_page(pdev
,
1982 if (unlikely(pci_dma_mapping_error(pdev
, dmaaddr
)))
1985 pci_dma_sync_single_for_device(pdev
,
1992 txdesc
->desc2
.flags
= TXFLAG_OWN
;
1993 txdesc
->desc2
.flags
|= (hidma
) ? TXFLAG_64BIT
: 0;
1994 txdesc
->desc2
.datalen
= cpu_to_le16(len
);
1995 txdesc
->desc2
.bufaddrh
= cpu_to_le32((__u64
)dmaaddr
>> 32);
1996 txdesc
->desc2
.bufaddrl
= cpu_to_le32(
1997 (__u64
)dmaaddr
& 0xFFFFFFFFUL
);
1999 txbi
->mapping
= dmaaddr
;
2004 static void jme_drop_tx_map(struct jme_adapter
*jme
, int startidx
, int count
)
2006 struct jme_ring
*txring
= &(jme
->txring
[0]);
2007 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
;
2008 int mask
= jme
->tx_ring_mask
;
2011 for (j
= 0 ; j
< count
; j
++) {
2012 ctxbi
= txbi
+ ((startidx
+ j
+ 2) & (mask
));
2013 pci_unmap_page(jme
->pdev
,
2024 jme_map_tx_skb(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
2026 struct jme_ring
*txring
= &(jme
->txring
[0]);
2027 struct txdesc
*txdesc
= txring
->desc
, *ctxdesc
;
2028 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
;
2029 bool hidma
= jme
->dev
->features
& NETIF_F_HIGHDMA
;
2030 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
2031 int mask
= jme
->tx_ring_mask
;
2035 for (i
= 0 ; i
< nr_frags
; ++i
) {
2036 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2038 ctxdesc
= txdesc
+ ((idx
+ i
+ 2) & (mask
));
2039 ctxbi
= txbi
+ ((idx
+ i
+ 2) & (mask
));
2041 ret
= jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
,
2042 skb_frag_page(frag
), skb_frag_off(frag
),
2043 skb_frag_size(frag
), hidma
);
2045 jme_drop_tx_map(jme
, idx
, i
);
2050 len
= skb_is_nonlinear(skb
) ? skb_headlen(skb
) : skb
->len
;
2051 ctxdesc
= txdesc
+ ((idx
+ 1) & (mask
));
2052 ctxbi
= txbi
+ ((idx
+ 1) & (mask
));
2053 ret
= jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
, virt_to_page(skb
->data
),
2054 offset_in_page(skb
->data
), len
, hidma
);
2056 jme_drop_tx_map(jme
, idx
, i
);
2065 jme_tx_tso(struct sk_buff
*skb
, __le16
*mss
, u8
*flags
)
2067 *mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
<< TXDESC_MSS_SHIFT
);
2069 *flags
|= TXFLAG_LSEN
;
2071 if (skb
->protocol
== htons(ETH_P_IP
)) {
2072 struct iphdr
*iph
= ip_hdr(skb
);
2075 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
2080 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
2082 tcp_hdr(skb
)->check
= ~csum_ipv6_magic(&ip6h
->saddr
,
2095 jme_tx_csum(struct jme_adapter
*jme
, struct sk_buff
*skb
, u8
*flags
)
2097 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2100 switch (skb
->protocol
) {
2101 case htons(ETH_P_IP
):
2102 ip_proto
= ip_hdr(skb
)->protocol
;
2104 case htons(ETH_P_IPV6
):
2105 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
2114 *flags
|= TXFLAG_TCPCS
;
2117 *flags
|= TXFLAG_UDPCS
;
2120 netif_err(jme
, tx_err
, jme
->dev
, "Error upper layer protocol\n");
2127 jme_tx_vlan(struct sk_buff
*skb
, __le16
*vlan
, u8
*flags
)
2129 if (skb_vlan_tag_present(skb
)) {
2130 *flags
|= TXFLAG_TAGON
;
2131 *vlan
= cpu_to_le16(skb_vlan_tag_get(skb
));
2136 jme_fill_tx_desc(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
2138 struct jme_ring
*txring
= &(jme
->txring
[0]);
2139 struct txdesc
*txdesc
;
2140 struct jme_buffer_info
*txbi
;
2144 txdesc
= (struct txdesc
*)txring
->desc
+ idx
;
2145 txbi
= txring
->bufinf
+ idx
;
2151 txdesc
->desc1
.pktsize
= cpu_to_le16(skb
->len
);
2153 * Set OWN bit at final.
2154 * When kernel transmit faster than NIC.
2155 * And NIC trying to send this descriptor before we tell
2156 * it to start sending this TX queue.
2157 * Other fields are already filled correctly.
2160 flags
= TXFLAG_OWN
| TXFLAG_INT
;
2162 * Set checksum flags while not tso
2164 if (jme_tx_tso(skb
, &txdesc
->desc1
.mss
, &flags
))
2165 jme_tx_csum(jme
, skb
, &flags
);
2166 jme_tx_vlan(skb
, &txdesc
->desc1
.vlan
, &flags
);
2167 ret
= jme_map_tx_skb(jme
, skb
, idx
);
2171 txdesc
->desc1
.flags
= flags
;
2173 * Set tx buffer info after telling NIC to send
2174 * For better tx_clean timing
2177 txbi
->nr_desc
= skb_shinfo(skb
)->nr_frags
+ 2;
2179 txbi
->len
= skb
->len
;
2180 txbi
->start_xmit
= jiffies
;
2181 if (!txbi
->start_xmit
)
2182 txbi
->start_xmit
= (0UL-1);
2188 jme_stop_queue_if_full(struct jme_adapter
*jme
)
2190 struct jme_ring
*txring
= &(jme
->txring
[0]);
2191 struct jme_buffer_info
*txbi
= txring
->bufinf
;
2192 int idx
= atomic_read(&txring
->next_to_clean
);
2197 if (unlikely(atomic_read(&txring
->nr_free
) < (MAX_SKB_FRAGS
+2))) {
2198 netif_stop_queue(jme
->dev
);
2199 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Paused\n");
2201 if (atomic_read(&txring
->nr_free
)
2202 >= (jme
->tx_wake_threshold
)) {
2203 netif_wake_queue(jme
->dev
);
2204 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Fast Waked\n");
2208 if (unlikely(txbi
->start_xmit
&&
2209 (jiffies
- txbi
->start_xmit
) >= TX_TIMEOUT
&&
2211 netif_stop_queue(jme
->dev
);
2212 netif_info(jme
, tx_queued
, jme
->dev
,
2213 "TX Queue Stopped %d@%lu\n", idx
, jiffies
);
2218 * This function is already protected by netif_tx_lock()
2222 jme_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2224 struct jme_adapter
*jme
= netdev_priv(netdev
);
2227 if (unlikely(skb_is_gso(skb
) && skb_cow_head(skb
, 0))) {
2228 dev_kfree_skb_any(skb
);
2229 ++(NET_STAT(jme
).tx_dropped
);
2230 return NETDEV_TX_OK
;
2233 idx
= jme_alloc_txdesc(jme
, skb
);
2235 if (unlikely(idx
< 0)) {
2236 netif_stop_queue(netdev
);
2237 netif_err(jme
, tx_err
, jme
->dev
,
2238 "BUG! Tx ring full when queue awake!\n");
2240 return NETDEV_TX_BUSY
;
2243 if (jme_fill_tx_desc(jme
, skb
, idx
))
2244 return NETDEV_TX_OK
;
2246 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
2247 TXCS_SELECT_QUEUE0
|
2251 tx_dbg(jme
, "xmit: %d+%d@%lu\n",
2252 idx
, skb_shinfo(skb
)->nr_frags
+ 2, jiffies
);
2253 jme_stop_queue_if_full(jme
);
2255 return NETDEV_TX_OK
;
2259 jme_set_unicastaddr(struct net_device
*netdev
)
2261 struct jme_adapter
*jme
= netdev_priv(netdev
);
2264 val
= (netdev
->dev_addr
[3] & 0xff) << 24 |
2265 (netdev
->dev_addr
[2] & 0xff) << 16 |
2266 (netdev
->dev_addr
[1] & 0xff) << 8 |
2267 (netdev
->dev_addr
[0] & 0xff);
2268 jwrite32(jme
, JME_RXUMA_LO
, val
);
2269 val
= (netdev
->dev_addr
[5] & 0xff) << 8 |
2270 (netdev
->dev_addr
[4] & 0xff);
2271 jwrite32(jme
, JME_RXUMA_HI
, val
);
2275 jme_set_macaddr(struct net_device
*netdev
, void *p
)
2277 struct jme_adapter
*jme
= netdev_priv(netdev
);
2278 struct sockaddr
*addr
= p
;
2280 if (netif_running(netdev
))
2283 spin_lock_bh(&jme
->macaddr_lock
);
2284 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
2285 jme_set_unicastaddr(netdev
);
2286 spin_unlock_bh(&jme
->macaddr_lock
);
2292 jme_set_multi(struct net_device
*netdev
)
2294 struct jme_adapter
*jme
= netdev_priv(netdev
);
2295 u32 mc_hash
[2] = {};
2297 spin_lock_bh(&jme
->rxmcs_lock
);
2299 jme
->reg_rxmcs
|= RXMCS_BRDFRAME
| RXMCS_UNIFRAME
;
2301 if (netdev
->flags
& IFF_PROMISC
) {
2302 jme
->reg_rxmcs
|= RXMCS_ALLFRAME
;
2303 } else if (netdev
->flags
& IFF_ALLMULTI
) {
2304 jme
->reg_rxmcs
|= RXMCS_ALLMULFRAME
;
2305 } else if (netdev
->flags
& IFF_MULTICAST
) {
2306 struct netdev_hw_addr
*ha
;
2309 jme
->reg_rxmcs
|= RXMCS_MULFRAME
| RXMCS_MULFILTERED
;
2310 netdev_for_each_mc_addr(ha
, netdev
) {
2311 bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) & 0x3F;
2312 mc_hash
[bit_nr
>> 5] |= 1 << (bit_nr
& 0x1F);
2315 jwrite32(jme
, JME_RXMCHT_LO
, mc_hash
[0]);
2316 jwrite32(jme
, JME_RXMCHT_HI
, mc_hash
[1]);
2320 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2322 spin_unlock_bh(&jme
->rxmcs_lock
);
2326 jme_change_mtu(struct net_device
*netdev
, int new_mtu
)
2328 struct jme_adapter
*jme
= netdev_priv(netdev
);
2330 netdev
->mtu
= new_mtu
;
2331 netdev_update_features(netdev
);
2333 jme_restart_rx_engine(jme
);
2334 jme_reset_link(jme
);
2340 jme_tx_timeout(struct net_device
*netdev
, unsigned int txqueue
)
2342 struct jme_adapter
*jme
= netdev_priv(netdev
);
2345 jme_reset_phy_processor(jme
);
2346 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
2347 jme_set_link_ksettings(netdev
, &jme
->old_cmd
);
2350 * Force to Reset the link again
2352 jme_reset_link(jme
);
2356 jme_get_drvinfo(struct net_device
*netdev
,
2357 struct ethtool_drvinfo
*info
)
2359 struct jme_adapter
*jme
= netdev_priv(netdev
);
2361 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
2362 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
2363 strlcpy(info
->bus_info
, pci_name(jme
->pdev
), sizeof(info
->bus_info
));
2367 jme_get_regs_len(struct net_device
*netdev
)
2373 mmapio_memcpy(struct jme_adapter
*jme
, u32
*p
, u32 reg
, int len
)
2377 for (i
= 0 ; i
< len
; i
+= 4)
2378 p
[i
>> 2] = jread32(jme
, reg
+ i
);
2382 mdio_memcpy(struct jme_adapter
*jme
, u32
*p
, int reg_nr
)
2385 u16
*p16
= (u16
*)p
;
2387 for (i
= 0 ; i
< reg_nr
; ++i
)
2388 p16
[i
] = jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, i
);
2392 jme_get_regs(struct net_device
*netdev
, struct ethtool_regs
*regs
, void *p
)
2394 struct jme_adapter
*jme
= netdev_priv(netdev
);
2395 u32
*p32
= (u32
*)p
;
2397 memset(p
, 0xFF, JME_REG_LEN
);
2400 mmapio_memcpy(jme
, p32
, JME_MAC
, JME_MAC_LEN
);
2403 mmapio_memcpy(jme
, p32
, JME_PHY
, JME_PHY_LEN
);
2406 mmapio_memcpy(jme
, p32
, JME_MISC
, JME_MISC_LEN
);
2409 mmapio_memcpy(jme
, p32
, JME_RSS
, JME_RSS_LEN
);
2412 mdio_memcpy(jme
, p32
, JME_PHY_REG_NR
);
2416 jme_get_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2418 struct jme_adapter
*jme
= netdev_priv(netdev
);
2420 ecmd
->tx_coalesce_usecs
= PCC_TX_TO
;
2421 ecmd
->tx_max_coalesced_frames
= PCC_TX_CNT
;
2423 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2424 ecmd
->use_adaptive_rx_coalesce
= false;
2425 ecmd
->rx_coalesce_usecs
= 0;
2426 ecmd
->rx_max_coalesced_frames
= 0;
2430 ecmd
->use_adaptive_rx_coalesce
= true;
2432 switch (jme
->dpi
.cur
) {
2434 ecmd
->rx_coalesce_usecs
= PCC_P1_TO
;
2435 ecmd
->rx_max_coalesced_frames
= PCC_P1_CNT
;
2438 ecmd
->rx_coalesce_usecs
= PCC_P2_TO
;
2439 ecmd
->rx_max_coalesced_frames
= PCC_P2_CNT
;
2442 ecmd
->rx_coalesce_usecs
= PCC_P3_TO
;
2443 ecmd
->rx_max_coalesced_frames
= PCC_P3_CNT
;
2453 jme_set_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2455 struct jme_adapter
*jme
= netdev_priv(netdev
);
2456 struct dynpcc_info
*dpi
= &(jme
->dpi
);
2458 if (netif_running(netdev
))
2461 if (ecmd
->use_adaptive_rx_coalesce
&&
2462 test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2463 clear_bit(JME_FLAG_POLL
, &jme
->flags
);
2464 jme
->jme_rx
= netif_rx
;
2466 dpi
->attempt
= PCC_P1
;
2468 jme_set_rx_pcc(jme
, PCC_P1
);
2469 jme_interrupt_mode(jme
);
2470 } else if (!(ecmd
->use_adaptive_rx_coalesce
) &&
2471 !(test_bit(JME_FLAG_POLL
, &jme
->flags
))) {
2472 set_bit(JME_FLAG_POLL
, &jme
->flags
);
2473 jme
->jme_rx
= netif_receive_skb
;
2474 jme_interrupt_mode(jme
);
2481 jme_get_pauseparam(struct net_device
*netdev
,
2482 struct ethtool_pauseparam
*ecmd
)
2484 struct jme_adapter
*jme
= netdev_priv(netdev
);
2487 ecmd
->tx_pause
= (jme
->reg_txpfc
& TXPFC_PF_EN
) != 0;
2488 ecmd
->rx_pause
= (jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0;
2490 spin_lock_bh(&jme
->phy_lock
);
2491 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2492 spin_unlock_bh(&jme
->phy_lock
);
2495 (val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0;
2499 jme_set_pauseparam(struct net_device
*netdev
,
2500 struct ethtool_pauseparam
*ecmd
)
2502 struct jme_adapter
*jme
= netdev_priv(netdev
);
2505 if (((jme
->reg_txpfc
& TXPFC_PF_EN
) != 0) ^
2506 (ecmd
->tx_pause
!= 0)) {
2509 jme
->reg_txpfc
|= TXPFC_PF_EN
;
2511 jme
->reg_txpfc
&= ~TXPFC_PF_EN
;
2513 jwrite32(jme
, JME_TXPFC
, jme
->reg_txpfc
);
2516 spin_lock_bh(&jme
->rxmcs_lock
);
2517 if (((jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0) ^
2518 (ecmd
->rx_pause
!= 0)) {
2521 jme
->reg_rxmcs
|= RXMCS_FLOWCTRL
;
2523 jme
->reg_rxmcs
&= ~RXMCS_FLOWCTRL
;
2525 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2527 spin_unlock_bh(&jme
->rxmcs_lock
);
2529 spin_lock_bh(&jme
->phy_lock
);
2530 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2531 if (((val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0) ^
2532 (ecmd
->autoneg
!= 0)) {
2535 val
|= (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2537 val
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2539 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
,
2540 MII_ADVERTISE
, val
);
2542 spin_unlock_bh(&jme
->phy_lock
);
2548 jme_get_wol(struct net_device
*netdev
,
2549 struct ethtool_wolinfo
*wol
)
2551 struct jme_adapter
*jme
= netdev_priv(netdev
);
2553 wol
->supported
= WAKE_MAGIC
| WAKE_PHY
;
2557 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
2558 wol
->wolopts
|= WAKE_PHY
;
2560 if (jme
->reg_pmcs
& PMCS_MFEN
)
2561 wol
->wolopts
|= WAKE_MAGIC
;
2566 jme_set_wol(struct net_device
*netdev
,
2567 struct ethtool_wolinfo
*wol
)
2569 struct jme_adapter
*jme
= netdev_priv(netdev
);
2571 if (wol
->wolopts
& (WAKE_MAGICSECURE
|
2580 if (wol
->wolopts
& WAKE_PHY
)
2581 jme
->reg_pmcs
|= PMCS_LFEN
| PMCS_LREN
;
2583 if (wol
->wolopts
& WAKE_MAGIC
)
2584 jme
->reg_pmcs
|= PMCS_MFEN
;
2590 jme_get_link_ksettings(struct net_device
*netdev
,
2591 struct ethtool_link_ksettings
*cmd
)
2593 struct jme_adapter
*jme
= netdev_priv(netdev
);
2595 spin_lock_bh(&jme
->phy_lock
);
2596 mii_ethtool_get_link_ksettings(&jme
->mii_if
, cmd
);
2597 spin_unlock_bh(&jme
->phy_lock
);
2602 jme_set_link_ksettings(struct net_device
*netdev
,
2603 const struct ethtool_link_ksettings
*cmd
)
2605 struct jme_adapter
*jme
= netdev_priv(netdev
);
2608 if (cmd
->base
.speed
== SPEED_1000
&&
2609 cmd
->base
.autoneg
!= AUTONEG_ENABLE
)
2613 * Check If user changed duplex only while force_media.
2614 * Hardware would not generate link change interrupt.
2616 if (jme
->mii_if
.force_media
&&
2617 cmd
->base
.autoneg
!= AUTONEG_ENABLE
&&
2618 (jme
->mii_if
.full_duplex
!= cmd
->base
.duplex
))
2621 spin_lock_bh(&jme
->phy_lock
);
2622 rc
= mii_ethtool_set_link_ksettings(&jme
->mii_if
, cmd
);
2623 spin_unlock_bh(&jme
->phy_lock
);
2627 jme_reset_link(jme
);
2628 jme
->old_cmd
= *cmd
;
2629 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2636 jme_ioctl(struct net_device
*netdev
, struct ifreq
*rq
, int cmd
)
2639 struct jme_adapter
*jme
= netdev_priv(netdev
);
2640 struct mii_ioctl_data
*mii_data
= if_mii(rq
);
2641 unsigned int duplex_chg
;
2643 if (cmd
== SIOCSMIIREG
) {
2644 u16 val
= mii_data
->val_in
;
2645 if (!(val
& (BMCR_RESET
|BMCR_ANENABLE
)) &&
2646 (val
& BMCR_SPEED1000
))
2650 spin_lock_bh(&jme
->phy_lock
);
2651 rc
= generic_mii_ioctl(&jme
->mii_if
, mii_data
, cmd
, &duplex_chg
);
2652 spin_unlock_bh(&jme
->phy_lock
);
2654 if (!rc
&& (cmd
== SIOCSMIIREG
)) {
2656 jme_reset_link(jme
);
2657 jme_get_link_ksettings(netdev
, &jme
->old_cmd
);
2658 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2665 jme_get_link(struct net_device
*netdev
)
2667 struct jme_adapter
*jme
= netdev_priv(netdev
);
2668 return jread32(jme
, JME_PHY_LINK
) & PHY_LINK_UP
;
2672 jme_get_msglevel(struct net_device
*netdev
)
2674 struct jme_adapter
*jme
= netdev_priv(netdev
);
2675 return jme
->msg_enable
;
2679 jme_set_msglevel(struct net_device
*netdev
, u32 value
)
2681 struct jme_adapter
*jme
= netdev_priv(netdev
);
2682 jme
->msg_enable
= value
;
2685 static netdev_features_t
2686 jme_fix_features(struct net_device
*netdev
, netdev_features_t features
)
2688 if (netdev
->mtu
> 1900)
2689 features
&= ~(NETIF_F_ALL_TSO
| NETIF_F_CSUM_MASK
);
2694 jme_set_features(struct net_device
*netdev
, netdev_features_t features
)
2696 struct jme_adapter
*jme
= netdev_priv(netdev
);
2698 spin_lock_bh(&jme
->rxmcs_lock
);
2699 if (features
& NETIF_F_RXCSUM
)
2700 jme
->reg_rxmcs
|= RXMCS_CHECKSUM
;
2702 jme
->reg_rxmcs
&= ~RXMCS_CHECKSUM
;
2703 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2704 spin_unlock_bh(&jme
->rxmcs_lock
);
2709 #ifdef CONFIG_NET_POLL_CONTROLLER
2710 static void jme_netpoll(struct net_device
*dev
)
2712 unsigned long flags
;
2714 local_irq_save(flags
);
2715 jme_intr(dev
->irq
, dev
);
2716 local_irq_restore(flags
);
2721 jme_nway_reset(struct net_device
*netdev
)
2723 struct jme_adapter
*jme
= netdev_priv(netdev
);
2724 jme_restart_an(jme
);
2729 jme_smb_read(struct jme_adapter
*jme
, unsigned int addr
)
2734 val
= jread32(jme
, JME_SMBCSR
);
2735 to
= JME_SMB_BUSY_TIMEOUT
;
2736 while ((val
& SMBCSR_BUSY
) && --to
) {
2738 val
= jread32(jme
, JME_SMBCSR
);
2741 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2745 jwrite32(jme
, JME_SMBINTF
,
2746 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2747 SMBINTF_HWRWN_READ
|
2750 val
= jread32(jme
, JME_SMBINTF
);
2751 to
= JME_SMB_BUSY_TIMEOUT
;
2752 while ((val
& SMBINTF_HWCMD
) && --to
) {
2754 val
= jread32(jme
, JME_SMBINTF
);
2757 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2761 return (val
& SMBINTF_HWDATR
) >> SMBINTF_HWDATR_SHIFT
;
2765 jme_smb_write(struct jme_adapter
*jme
, unsigned int addr
, u8 data
)
2770 val
= jread32(jme
, JME_SMBCSR
);
2771 to
= JME_SMB_BUSY_TIMEOUT
;
2772 while ((val
& SMBCSR_BUSY
) && --to
) {
2774 val
= jread32(jme
, JME_SMBCSR
);
2777 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2781 jwrite32(jme
, JME_SMBINTF
,
2782 ((data
<< SMBINTF_HWDATW_SHIFT
) & SMBINTF_HWDATW
) |
2783 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2784 SMBINTF_HWRWN_WRITE
|
2787 val
= jread32(jme
, JME_SMBINTF
);
2788 to
= JME_SMB_BUSY_TIMEOUT
;
2789 while ((val
& SMBINTF_HWCMD
) && --to
) {
2791 val
= jread32(jme
, JME_SMBINTF
);
2794 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2802 jme_get_eeprom_len(struct net_device
*netdev
)
2804 struct jme_adapter
*jme
= netdev_priv(netdev
);
2806 val
= jread32(jme
, JME_SMBCSR
);
2807 return (val
& SMBCSR_EEPROMD
) ? JME_SMB_LEN
: 0;
2811 jme_get_eeprom(struct net_device
*netdev
,
2812 struct ethtool_eeprom
*eeprom
, u8
*data
)
2814 struct jme_adapter
*jme
= netdev_priv(netdev
);
2815 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2818 * ethtool will check the boundary for us
2820 eeprom
->magic
= JME_EEPROM_MAGIC
;
2821 for (i
= 0 ; i
< len
; ++i
)
2822 data
[i
] = jme_smb_read(jme
, i
+ offset
);
2828 jme_set_eeprom(struct net_device
*netdev
,
2829 struct ethtool_eeprom
*eeprom
, u8
*data
)
2831 struct jme_adapter
*jme
= netdev_priv(netdev
);
2832 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2834 if (eeprom
->magic
!= JME_EEPROM_MAGIC
)
2838 * ethtool will check the boundary for us
2840 for (i
= 0 ; i
< len
; ++i
)
2841 jme_smb_write(jme
, i
+ offset
, data
[i
]);
2846 static const struct ethtool_ops jme_ethtool_ops
= {
2847 .get_drvinfo
= jme_get_drvinfo
,
2848 .get_regs_len
= jme_get_regs_len
,
2849 .get_regs
= jme_get_regs
,
2850 .get_coalesce
= jme_get_coalesce
,
2851 .set_coalesce
= jme_set_coalesce
,
2852 .get_pauseparam
= jme_get_pauseparam
,
2853 .set_pauseparam
= jme_set_pauseparam
,
2854 .get_wol
= jme_get_wol
,
2855 .set_wol
= jme_set_wol
,
2856 .get_link
= jme_get_link
,
2857 .get_msglevel
= jme_get_msglevel
,
2858 .set_msglevel
= jme_set_msglevel
,
2859 .nway_reset
= jme_nway_reset
,
2860 .get_eeprom_len
= jme_get_eeprom_len
,
2861 .get_eeprom
= jme_get_eeprom
,
2862 .set_eeprom
= jme_set_eeprom
,
2863 .get_link_ksettings
= jme_get_link_ksettings
,
2864 .set_link_ksettings
= jme_set_link_ksettings
,
2868 jme_pci_dma64(struct pci_dev
*pdev
)
2870 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2871 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))
2872 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)))
2875 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2876 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
2877 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40)))
2880 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)))
2881 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))
2888 jme_phy_init(struct jme_adapter
*jme
)
2892 reg26
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 26);
2893 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 26, reg26
| 0x1000);
2897 jme_check_hw_ver(struct jme_adapter
*jme
)
2901 chipmode
= jread32(jme
, JME_CHIPMODE
);
2903 jme
->fpgaver
= (chipmode
& CM_FPGAVER_MASK
) >> CM_FPGAVER_SHIFT
;
2904 jme
->chiprev
= (chipmode
& CM_CHIPREV_MASK
) >> CM_CHIPREV_SHIFT
;
2905 jme
->chip_main_rev
= jme
->chiprev
& 0xF;
2906 jme
->chip_sub_rev
= (jme
->chiprev
>> 4) & 0xF;
2909 static const struct net_device_ops jme_netdev_ops
= {
2910 .ndo_open
= jme_open
,
2911 .ndo_stop
= jme_close
,
2912 .ndo_validate_addr
= eth_validate_addr
,
2913 .ndo_do_ioctl
= jme_ioctl
,
2914 .ndo_start_xmit
= jme_start_xmit
,
2915 .ndo_set_mac_address
= jme_set_macaddr
,
2916 .ndo_set_rx_mode
= jme_set_multi
,
2917 .ndo_change_mtu
= jme_change_mtu
,
2918 .ndo_tx_timeout
= jme_tx_timeout
,
2919 .ndo_fix_features
= jme_fix_features
,
2920 .ndo_set_features
= jme_set_features
,
2921 #ifdef CONFIG_NET_POLL_CONTROLLER
2922 .ndo_poll_controller
= jme_netpoll
,
2927 jme_init_one(struct pci_dev
*pdev
,
2928 const struct pci_device_id
*ent
)
2930 int rc
= 0, using_dac
, i
;
2931 struct net_device
*netdev
;
2932 struct jme_adapter
*jme
;
2937 * set up PCI device basics
2939 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
2940 PCIE_LINK_STATE_CLKPM
);
2942 rc
= pci_enable_device(pdev
);
2944 pr_err("Cannot enable PCI device\n");
2948 using_dac
= jme_pci_dma64(pdev
);
2949 if (using_dac
< 0) {
2950 pr_err("Cannot set PCI DMA Mask\n");
2952 goto err_out_disable_pdev
;
2955 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2956 pr_err("No PCI resource region found\n");
2958 goto err_out_disable_pdev
;
2961 rc
= pci_request_regions(pdev
, DRV_NAME
);
2963 pr_err("Cannot obtain PCI resource region\n");
2964 goto err_out_disable_pdev
;
2967 pci_set_master(pdev
);
2970 * alloc and init net device
2972 netdev
= alloc_etherdev(sizeof(*jme
));
2975 goto err_out_release_regions
;
2977 netdev
->netdev_ops
= &jme_netdev_ops
;
2978 netdev
->ethtool_ops
= &jme_ethtool_ops
;
2979 netdev
->watchdog_timeo
= TX_TIMEOUT
;
2980 netdev
->hw_features
= NETIF_F_IP_CSUM
|
2986 netdev
->features
= NETIF_F_IP_CSUM
|
2991 NETIF_F_HW_VLAN_CTAG_TX
|
2992 NETIF_F_HW_VLAN_CTAG_RX
;
2994 netdev
->features
|= NETIF_F_HIGHDMA
;
2996 /* MTU range: 1280 - 9202*/
2997 netdev
->min_mtu
= IPV6_MIN_MTU
;
2998 netdev
->max_mtu
= MAX_ETHERNET_JUMBO_PACKET_SIZE
- ETH_HLEN
;
3000 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3001 pci_set_drvdata(pdev
, netdev
);
3006 jme
= netdev_priv(netdev
);
3009 jme
->jme_rx
= netif_rx
;
3010 jme
->old_mtu
= netdev
->mtu
= 1500;
3012 jme
->tx_ring_size
= 1 << 10;
3013 jme
->tx_ring_mask
= jme
->tx_ring_size
- 1;
3014 jme
->tx_wake_threshold
= 1 << 9;
3015 jme
->rx_ring_size
= 1 << 9;
3016 jme
->rx_ring_mask
= jme
->rx_ring_size
- 1;
3017 jme
->msg_enable
= JME_DEF_MSG_ENABLE
;
3018 jme
->regs
= ioremap(pci_resource_start(pdev
, 0),
3019 pci_resource_len(pdev
, 0));
3021 pr_err("Mapping PCI resource region error\n");
3023 goto err_out_free_netdev
;
3027 apmc
= jread32(jme
, JME_APMC
) & ~JME_APMC_PSEUDO_HP_EN
;
3028 jwrite32(jme
, JME_APMC
, apmc
);
3029 } else if (force_pseudohp
) {
3030 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PSEUDO_HP_EN
;
3031 jwrite32(jme
, JME_APMC
, apmc
);
3034 NETIF_NAPI_SET(netdev
, &jme
->napi
, jme_poll
, NAPI_POLL_WEIGHT
)
3036 spin_lock_init(&jme
->phy_lock
);
3037 spin_lock_init(&jme
->macaddr_lock
);
3038 spin_lock_init(&jme
->rxmcs_lock
);
3040 atomic_set(&jme
->link_changing
, 1);
3041 atomic_set(&jme
->rx_cleaning
, 1);
3042 atomic_set(&jme
->tx_cleaning
, 1);
3043 atomic_set(&jme
->rx_empty
, 1);
3045 tasklet_init(&jme
->pcc_task
,
3047 (unsigned long) jme
);
3048 jme
->dpi
.cur
= PCC_P1
;
3051 jme
->reg_rxcs
= RXCS_DEFAULT
;
3052 jme
->reg_rxmcs
= RXMCS_DEFAULT
;
3054 jme
->reg_pmcs
= PMCS_MFEN
;
3055 jme
->reg_gpreg1
= GPREG1_DEFAULT
;
3057 if (jme
->reg_rxmcs
& RXMCS_CHECKSUM
)
3058 netdev
->features
|= NETIF_F_RXCSUM
;
3061 * Get Max Read Req Size from PCI Config Space
3063 pci_read_config_byte(pdev
, PCI_DCSR_MRRS
, &jme
->mrrs
);
3064 jme
->mrrs
&= PCI_DCSR_MRRS_MASK
;
3065 switch (jme
->mrrs
) {
3067 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_128B
;
3070 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_256B
;
3073 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_512B
;
3078 * Must check before reset_mac_processor
3080 jme_check_hw_ver(jme
);
3081 jme
->mii_if
.dev
= netdev
;
3083 jme
->mii_if
.phy_id
= 0;
3084 for (i
= 1 ; i
< 32 ; ++i
) {
3085 bmcr
= jme_mdio_read(netdev
, i
, MII_BMCR
);
3086 bmsr
= jme_mdio_read(netdev
, i
, MII_BMSR
);
3087 if (bmcr
!= 0xFFFFU
&& (bmcr
!= 0 || bmsr
!= 0)) {
3088 jme
->mii_if
.phy_id
= i
;
3093 if (!jme
->mii_if
.phy_id
) {
3095 pr_err("Can not find phy_id\n");
3099 jme
->reg_ghc
|= GHC_LINK_POLL
;
3101 jme
->mii_if
.phy_id
= 1;
3103 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
3104 jme
->mii_if
.supports_gmii
= true;
3106 jme
->mii_if
.supports_gmii
= false;
3107 jme
->mii_if
.phy_id_mask
= 0x1F;
3108 jme
->mii_if
.reg_num_mask
= 0x1F;
3109 jme
->mii_if
.mdio_read
= jme_mdio_read
;
3110 jme
->mii_if
.mdio_write
= jme_mdio_write
;
3112 jme_clear_pm_disable_wol(jme
);
3113 device_init_wakeup(&pdev
->dev
, true);
3115 jme_set_phyfifo_5level(jme
);
3116 jme
->pcirev
= pdev
->revision
;
3122 * Reset MAC processor and reload EEPROM for MAC Address
3124 jme_reset_mac_processor(jme
);
3125 rc
= jme_reload_eeprom(jme
);
3127 pr_err("Reload eeprom for reading MAC Address error\n");
3130 jme_load_macaddr(netdev
);
3133 * Tell stack that we are not ready to work until open()
3135 netif_carrier_off(netdev
);
3137 rc
= register_netdev(netdev
);
3139 pr_err("Cannot register net device\n");
3143 netif_info(jme
, probe
, jme
->dev
, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3144 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
) ?
3145 "JMC250 Gigabit Ethernet" :
3146 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC260
) ?
3147 "JMC260 Fast Ethernet" : "Unknown",
3148 (jme
->fpgaver
!= 0) ? " (FPGA)" : "",
3149 (jme
->fpgaver
!= 0) ? jme
->fpgaver
: jme
->chiprev
,
3150 jme
->pcirev
, netdev
->dev_addr
);
3156 err_out_free_netdev
:
3157 free_netdev(netdev
);
3158 err_out_release_regions
:
3159 pci_release_regions(pdev
);
3160 err_out_disable_pdev
:
3161 pci_disable_device(pdev
);
3167 jme_remove_one(struct pci_dev
*pdev
)
3169 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3170 struct jme_adapter
*jme
= netdev_priv(netdev
);
3172 unregister_netdev(netdev
);
3174 free_netdev(netdev
);
3175 pci_release_regions(pdev
);
3176 pci_disable_device(pdev
);
3181 jme_shutdown(struct pci_dev
*pdev
)
3183 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3184 struct jme_adapter
*jme
= netdev_priv(netdev
);
3186 jme_powersave_phy(jme
);
3187 pci_pme_active(pdev
, true);
3190 #ifdef CONFIG_PM_SLEEP
3192 jme_suspend(struct device
*dev
)
3194 struct net_device
*netdev
= dev_get_drvdata(dev
);
3195 struct jme_adapter
*jme
= netdev_priv(netdev
);
3197 if (!netif_running(netdev
))
3200 atomic_dec(&jme
->link_changing
);
3202 netif_device_detach(netdev
);
3203 netif_stop_queue(netdev
);
3206 tasklet_disable(&jme
->txclean_task
);
3207 tasklet_disable(&jme
->rxclean_task
);
3208 tasklet_disable(&jme
->rxempty_task
);
3210 if (netif_carrier_ok(netdev
)) {
3211 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
3212 jme_polling_mode(jme
);
3214 jme_stop_pcc_timer(jme
);
3215 jme_disable_rx_engine(jme
);
3216 jme_disable_tx_engine(jme
);
3217 jme_reset_mac_processor(jme
);
3218 jme_free_rx_resources(jme
);
3219 jme_free_tx_resources(jme
);
3220 netif_carrier_off(netdev
);
3224 tasklet_enable(&jme
->txclean_task
);
3225 tasklet_enable(&jme
->rxclean_task
);
3226 tasklet_enable(&jme
->rxempty_task
);
3228 jme_powersave_phy(jme
);
3234 jme_resume(struct device
*dev
)
3236 struct net_device
*netdev
= dev_get_drvdata(dev
);
3237 struct jme_adapter
*jme
= netdev_priv(netdev
);
3239 if (!netif_running(netdev
))
3242 jme_clear_pm_disable_wol(jme
);
3244 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
3245 jme_set_link_ksettings(netdev
, &jme
->old_cmd
);
3247 jme_reset_phy_processor(jme
);
3248 jme_phy_calibration(jme
);
3250 netif_device_attach(netdev
);
3252 atomic_inc(&jme
->link_changing
);
3254 jme_reset_link(jme
);
3261 static SIMPLE_DEV_PM_OPS(jme_pm_ops
, jme_suspend
, jme_resume
);
3262 #define JME_PM_OPS (&jme_pm_ops)
3266 #define JME_PM_OPS NULL
3269 static const struct pci_device_id jme_pci_tbl
[] = {
3270 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC250
) },
3271 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC260
) },
3275 static struct pci_driver jme_driver
= {
3277 .id_table
= jme_pci_tbl
,
3278 .probe
= jme_init_one
,
3279 .remove
= jme_remove_one
,
3280 .shutdown
= jme_shutdown
,
3281 .driver
.pm
= JME_PM_OPS
,
3285 jme_init_module(void)
3287 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION
);
3288 return pci_register_driver(&jme_driver
);
3292 jme_cleanup_module(void)
3294 pci_unregister_driver(&jme_driver
);
3297 module_init(jme_init_module
);
3298 module_exit(jme_cleanup_module
);
3300 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3301 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3302 MODULE_LICENSE("GPL");
3303 MODULE_VERSION(DRV_VERSION
);
3304 MODULE_DEVICE_TABLE(pci
, jme_pci_tbl
);