1 // SPDX-License-Identifier: GPL-2.0-only
3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
5 * Copyright 2008 JMicron Technology Corporation
6 * http://www.jmicron.com/
7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/pci-aspm.h>
18 #include <linux/netdevice.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/crc32.h>
23 #include <linux/delay.h>
24 #include <linux/spinlock.h>
27 #include <linux/ipv6.h>
28 #include <linux/tcp.h>
29 #include <linux/udp.h>
30 #include <linux/if_vlan.h>
31 #include <linux/slab.h>
32 #include <net/ip6_checksum.h>
35 static int force_pseudohp
= -1;
36 static int no_pseudohp
= -1;
37 static int no_extplug
= -1;
38 module_param(force_pseudohp
, int, 0);
39 MODULE_PARM_DESC(force_pseudohp
,
40 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
41 module_param(no_pseudohp
, int, 0);
42 MODULE_PARM_DESC(no_pseudohp
, "Disable pseudo hot-plug feature.");
43 module_param(no_extplug
, int, 0);
44 MODULE_PARM_DESC(no_extplug
,
45 "Do not use external plug signal for pseudo hot-plug.");
48 jme_mdio_read(struct net_device
*netdev
, int phy
, int reg
)
50 struct jme_adapter
*jme
= netdev_priv(netdev
);
51 int i
, val
, again
= (reg
== MII_BMSR
) ? 1 : 0;
54 jwrite32(jme
, JME_SMI
, SMI_OP_REQ
|
59 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
61 val
= jread32(jme
, JME_SMI
);
62 if ((val
& SMI_OP_REQ
) == 0)
67 pr_err("phy(%d) read timeout : %d\n", phy
, reg
);
74 return (val
& SMI_DATA_MASK
) >> SMI_DATA_SHIFT
;
78 jme_mdio_write(struct net_device
*netdev
,
79 int phy
, int reg
, int val
)
81 struct jme_adapter
*jme
= netdev_priv(netdev
);
84 jwrite32(jme
, JME_SMI
, SMI_OP_WRITE
| SMI_OP_REQ
|
85 ((val
<< SMI_DATA_SHIFT
) & SMI_DATA_MASK
) |
86 smi_phy_addr(phy
) | smi_reg_addr(reg
));
89 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
91 if ((jread32(jme
, JME_SMI
) & SMI_OP_REQ
) == 0)
96 pr_err("phy(%d) write timeout : %d\n", phy
, reg
);
100 jme_reset_phy_processor(struct jme_adapter
*jme
)
104 jme_mdio_write(jme
->dev
,
106 MII_ADVERTISE
, ADVERTISE_ALL
|
107 ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
109 if (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
110 jme_mdio_write(jme
->dev
,
113 ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
115 val
= jme_mdio_read(jme
->dev
,
119 jme_mdio_write(jme
->dev
,
121 MII_BMCR
, val
| BMCR_RESET
);
125 jme_setup_wakeup_frame(struct jme_adapter
*jme
,
126 const u32
*mask
, u32 crc
, int fnr
)
133 jwrite32(jme
, JME_WFOI
, WFOI_CRC_SEL
| (fnr
& WFOI_FRAME_SEL
));
135 jwrite32(jme
, JME_WFODP
, crc
);
141 for (i
= 0 ; i
< WAKEUP_FRAME_MASK_DWNR
; ++i
) {
142 jwrite32(jme
, JME_WFOI
,
143 ((i
<< WFOI_MASK_SHIFT
) & WFOI_MASK_SEL
) |
144 (fnr
& WFOI_FRAME_SEL
));
146 jwrite32(jme
, JME_WFODP
, mask
[i
]);
152 jme_mac_rxclk_off(struct jme_adapter
*jme
)
154 jme
->reg_gpreg1
|= GPREG1_RXCLKOFF
;
155 jwrite32f(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
159 jme_mac_rxclk_on(struct jme_adapter
*jme
)
161 jme
->reg_gpreg1
&= ~GPREG1_RXCLKOFF
;
162 jwrite32f(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
166 jme_mac_txclk_off(struct jme_adapter
*jme
)
168 jme
->reg_ghc
&= ~(GHC_TO_CLK_SRC
| GHC_TXMAC_CLK_SRC
);
169 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
173 jme_mac_txclk_on(struct jme_adapter
*jme
)
175 u32 speed
= jme
->reg_ghc
& GHC_SPEED
;
176 if (speed
== GHC_SPEED_1000M
)
177 jme
->reg_ghc
|= GHC_TO_CLK_GPHY
| GHC_TXMAC_CLK_GPHY
;
179 jme
->reg_ghc
|= GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
;
180 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
184 jme_reset_ghc_speed(struct jme_adapter
*jme
)
186 jme
->reg_ghc
&= ~(GHC_SPEED
| GHC_DPX
);
187 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
191 jme_reset_250A2_workaround(struct jme_adapter
*jme
)
193 jme
->reg_gpreg1
&= ~(GPREG1_HALFMODEPATCH
|
195 jwrite32(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
199 jme_assert_ghc_reset(struct jme_adapter
*jme
)
201 jme
->reg_ghc
|= GHC_SWRST
;
202 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
206 jme_clear_ghc_reset(struct jme_adapter
*jme
)
208 jme
->reg_ghc
&= ~GHC_SWRST
;
209 jwrite32f(jme
, JME_GHC
, jme
->reg_ghc
);
213 jme_reset_mac_processor(struct jme_adapter
*jme
)
215 static const u32 mask
[WAKEUP_FRAME_MASK_DWNR
] = {0, 0, 0, 0};
216 u32 crc
= 0xCDCDCDCD;
220 jme_reset_ghc_speed(jme
);
221 jme_reset_250A2_workaround(jme
);
223 jme_mac_rxclk_on(jme
);
224 jme_mac_txclk_on(jme
);
226 jme_assert_ghc_reset(jme
);
228 jme_mac_rxclk_off(jme
);
229 jme_mac_txclk_off(jme
);
231 jme_clear_ghc_reset(jme
);
233 jme_mac_rxclk_on(jme
);
234 jme_mac_txclk_on(jme
);
236 jme_mac_rxclk_off(jme
);
237 jme_mac_txclk_off(jme
);
239 jwrite32(jme
, JME_RXDBA_LO
, 0x00000000);
240 jwrite32(jme
, JME_RXDBA_HI
, 0x00000000);
241 jwrite32(jme
, JME_RXQDC
, 0x00000000);
242 jwrite32(jme
, JME_RXNDA
, 0x00000000);
243 jwrite32(jme
, JME_TXDBA_LO
, 0x00000000);
244 jwrite32(jme
, JME_TXDBA_HI
, 0x00000000);
245 jwrite32(jme
, JME_TXQDC
, 0x00000000);
246 jwrite32(jme
, JME_TXNDA
, 0x00000000);
248 jwrite32(jme
, JME_RXMCHT_LO
, 0x00000000);
249 jwrite32(jme
, JME_RXMCHT_HI
, 0x00000000);
250 for (i
= 0 ; i
< WAKEUP_FRAME_NR
; ++i
)
251 jme_setup_wakeup_frame(jme
, mask
, crc
, i
);
253 gpreg0
= GPREG0_DEFAULT
| GPREG0_LNKINTPOLL
;
255 gpreg0
= GPREG0_DEFAULT
;
256 jwrite32(jme
, JME_GPREG0
, gpreg0
);
260 jme_clear_pm_enable_wol(struct jme_adapter
*jme
)
262 jwrite32(jme
, JME_PMCS
, PMCS_STMASK
| jme
->reg_pmcs
);
266 jme_clear_pm_disable_wol(struct jme_adapter
*jme
)
268 jwrite32(jme
, JME_PMCS
, PMCS_STMASK
);
272 jme_reload_eeprom(struct jme_adapter
*jme
)
277 val
= jread32(jme
, JME_SMBCSR
);
279 if (val
& SMBCSR_EEPROMD
) {
281 jwrite32(jme
, JME_SMBCSR
, val
);
282 val
|= SMBCSR_RELOAD
;
283 jwrite32(jme
, JME_SMBCSR
, val
);
286 for (i
= JME_EEPROM_RELOAD_TIMEOUT
; i
> 0; --i
) {
288 if ((jread32(jme
, JME_SMBCSR
) & SMBCSR_RELOAD
) == 0)
293 pr_err("eeprom reload timeout\n");
302 jme_load_macaddr(struct net_device
*netdev
)
304 struct jme_adapter
*jme
= netdev_priv(netdev
);
305 unsigned char macaddr
[ETH_ALEN
];
308 spin_lock_bh(&jme
->macaddr_lock
);
309 val
= jread32(jme
, JME_RXUMA_LO
);
310 macaddr
[0] = (val
>> 0) & 0xFF;
311 macaddr
[1] = (val
>> 8) & 0xFF;
312 macaddr
[2] = (val
>> 16) & 0xFF;
313 macaddr
[3] = (val
>> 24) & 0xFF;
314 val
= jread32(jme
, JME_RXUMA_HI
);
315 macaddr
[4] = (val
>> 0) & 0xFF;
316 macaddr
[5] = (val
>> 8) & 0xFF;
317 memcpy(netdev
->dev_addr
, macaddr
, ETH_ALEN
);
318 spin_unlock_bh(&jme
->macaddr_lock
);
322 jme_set_rx_pcc(struct jme_adapter
*jme
, int p
)
326 jwrite32(jme
, JME_PCCRX0
,
327 ((PCC_OFF_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
328 ((PCC_OFF_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
331 jwrite32(jme
, JME_PCCRX0
,
332 ((PCC_P1_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
333 ((PCC_P1_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
336 jwrite32(jme
, JME_PCCRX0
,
337 ((PCC_P2_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
338 ((PCC_P2_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
341 jwrite32(jme
, JME_PCCRX0
,
342 ((PCC_P3_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
343 ((PCC_P3_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
350 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
351 netif_info(jme
, rx_status
, jme
->dev
, "Switched to PCC_P%d\n", p
);
355 jme_start_irq(struct jme_adapter
*jme
)
357 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
359 jme_set_rx_pcc(jme
, PCC_P1
);
361 dpi
->attempt
= PCC_P1
;
364 jwrite32(jme
, JME_PCCTX
,
365 ((PCC_TX_TO
<< PCCTXTO_SHIFT
) & PCCTXTO_MASK
) |
366 ((PCC_TX_CNT
<< PCCTX_SHIFT
) & PCCTX_MASK
) |
373 jwrite32(jme
, JME_IENS
, INTR_ENABLE
);
377 jme_stop_irq(struct jme_adapter
*jme
)
382 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
386 jme_linkstat_from_phy(struct jme_adapter
*jme
)
390 phylink
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 17);
391 bmsr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMSR
);
392 if (bmsr
& BMSR_ANCOMP
)
393 phylink
|= PHY_LINK_AUTONEG_COMPLETE
;
399 jme_set_phyfifo_5level(struct jme_adapter
*jme
)
401 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0004);
405 jme_set_phyfifo_8level(struct jme_adapter
*jme
)
407 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0000);
411 jme_check_link(struct net_device
*netdev
, int testonly
)
413 struct jme_adapter
*jme
= netdev_priv(netdev
);
414 u32 phylink
, cnt
= JME_SPDRSV_TIMEOUT
, bmcr
;
421 phylink
= jme_linkstat_from_phy(jme
);
423 phylink
= jread32(jme
, JME_PHY_LINK
);
425 if (phylink
& PHY_LINK_UP
) {
426 if (!(phylink
& PHY_LINK_AUTONEG_COMPLETE
)) {
428 * If we did not enable AN
429 * Speed/Duplex Info should be obtained from SMI
431 phylink
= PHY_LINK_UP
;
433 bmcr
= jme_mdio_read(jme
->dev
,
437 phylink
|= ((bmcr
& BMCR_SPEED1000
) &&
438 (bmcr
& BMCR_SPEED100
) == 0) ?
439 PHY_LINK_SPEED_1000M
:
440 (bmcr
& BMCR_SPEED100
) ?
441 PHY_LINK_SPEED_100M
:
444 phylink
|= (bmcr
& BMCR_FULLDPLX
) ?
447 strcat(linkmsg
, "Forced: ");
450 * Keep polling for speed/duplex resolve complete
452 while (!(phylink
& PHY_LINK_SPEEDDPU_RESOLVED
) &&
458 phylink
= jme_linkstat_from_phy(jme
);
460 phylink
= jread32(jme
, JME_PHY_LINK
);
463 pr_err("Waiting speed resolve timeout\n");
465 strcat(linkmsg
, "ANed: ");
468 if (jme
->phylink
== phylink
) {
475 jme
->phylink
= phylink
;
478 * The speed/duplex setting of jme->reg_ghc already cleared
479 * by jme_reset_mac_processor()
481 switch (phylink
& PHY_LINK_SPEED_MASK
) {
482 case PHY_LINK_SPEED_10M
:
483 jme
->reg_ghc
|= GHC_SPEED_10M
;
484 strcat(linkmsg
, "10 Mbps, ");
486 case PHY_LINK_SPEED_100M
:
487 jme
->reg_ghc
|= GHC_SPEED_100M
;
488 strcat(linkmsg
, "100 Mbps, ");
490 case PHY_LINK_SPEED_1000M
:
491 jme
->reg_ghc
|= GHC_SPEED_1000M
;
492 strcat(linkmsg
, "1000 Mbps, ");
498 if (phylink
& PHY_LINK_DUPLEX
) {
499 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
);
500 jwrite32(jme
, JME_TXTRHD
, TXTRHD_FULLDUPLEX
);
501 jme
->reg_ghc
|= GHC_DPX
;
503 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
|
507 jwrite32(jme
, JME_TXTRHD
, TXTRHD_HALFDUPLEX
);
510 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
);
512 if (is_buggy250(jme
->pdev
->device
, jme
->chiprev
)) {
513 jme
->reg_gpreg1
&= ~(GPREG1_HALFMODEPATCH
|
515 if (!(phylink
& PHY_LINK_DUPLEX
))
516 jme
->reg_gpreg1
|= GPREG1_HALFMODEPATCH
;
517 switch (phylink
& PHY_LINK_SPEED_MASK
) {
518 case PHY_LINK_SPEED_10M
:
519 jme_set_phyfifo_8level(jme
);
520 jme
->reg_gpreg1
|= GPREG1_RSSPATCH
;
522 case PHY_LINK_SPEED_100M
:
523 jme_set_phyfifo_5level(jme
);
524 jme
->reg_gpreg1
|= GPREG1_RSSPATCH
;
526 case PHY_LINK_SPEED_1000M
:
527 jme_set_phyfifo_8level(jme
);
533 jwrite32(jme
, JME_GPREG1
, jme
->reg_gpreg1
);
535 strcat(linkmsg
, (phylink
& PHY_LINK_DUPLEX
) ?
538 strcat(linkmsg
, (phylink
& PHY_LINK_MDI_STAT
) ?
541 netif_info(jme
, link
, jme
->dev
, "Link is up at %s\n", linkmsg
);
542 netif_carrier_on(netdev
);
547 netif_info(jme
, link
, jme
->dev
, "Link is down\n");
549 netif_carrier_off(netdev
);
557 jme_setup_tx_resources(struct jme_adapter
*jme
)
559 struct jme_ring
*txring
= &(jme
->txring
[0]);
561 txring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
562 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
572 txring
->desc
= (void *)ALIGN((unsigned long)(txring
->alloc
),
574 txring
->dma
= ALIGN(txring
->dmaalloc
, RING_DESC_ALIGN
);
575 txring
->next_to_use
= 0;
576 atomic_set(&txring
->next_to_clean
, 0);
577 atomic_set(&txring
->nr_free
, jme
->tx_ring_size
);
579 txring
->bufinf
= kcalloc(jme
->tx_ring_size
,
580 sizeof(struct jme_buffer_info
),
582 if (unlikely(!(txring
->bufinf
)))
583 goto err_free_txring
;
588 dma_free_coherent(&(jme
->pdev
->dev
),
589 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
595 txring
->dmaalloc
= 0;
597 txring
->bufinf
= NULL
;
603 jme_free_tx_resources(struct jme_adapter
*jme
)
606 struct jme_ring
*txring
= &(jme
->txring
[0]);
607 struct jme_buffer_info
*txbi
;
610 if (txring
->bufinf
) {
611 for (i
= 0 ; i
< jme
->tx_ring_size
; ++i
) {
612 txbi
= txring
->bufinf
+ i
;
614 dev_kfree_skb(txbi
->skb
);
620 txbi
->start_xmit
= 0;
622 kfree(txring
->bufinf
);
625 dma_free_coherent(&(jme
->pdev
->dev
),
626 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
630 txring
->alloc
= NULL
;
632 txring
->dmaalloc
= 0;
634 txring
->bufinf
= NULL
;
636 txring
->next_to_use
= 0;
637 atomic_set(&txring
->next_to_clean
, 0);
638 atomic_set(&txring
->nr_free
, 0);
642 jme_enable_tx_engine(struct jme_adapter
*jme
)
647 jwrite32(jme
, JME_TXCS
, TXCS_DEFAULT
| TXCS_SELECT_QUEUE0
);
651 * Setup TX Queue 0 DMA Bass Address
653 jwrite32(jme
, JME_TXDBA_LO
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
654 jwrite32(jme
, JME_TXDBA_HI
, (__u64
)(jme
->txring
[0].dma
) >> 32);
655 jwrite32(jme
, JME_TXNDA
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
658 * Setup TX Descptor Count
660 jwrite32(jme
, JME_TXQDC
, jme
->tx_ring_size
);
666 jwrite32f(jme
, JME_TXCS
, jme
->reg_txcs
|
671 * Start clock for TX MAC Processor
673 jme_mac_txclk_on(jme
);
677 jme_disable_tx_engine(struct jme_adapter
*jme
)
685 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
| TXCS_SELECT_QUEUE0
);
688 val
= jread32(jme
, JME_TXCS
);
689 for (i
= JME_TX_DISABLE_TIMEOUT
; (val
& TXCS_ENABLE
) && i
> 0 ; --i
) {
691 val
= jread32(jme
, JME_TXCS
);
696 pr_err("Disable TX engine timeout\n");
699 * Stop clock for TX MAC Processor
701 jme_mac_txclk_off(jme
);
705 jme_set_clean_rxdesc(struct jme_adapter
*jme
, int i
)
707 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
708 register struct rxdesc
*rxdesc
= rxring
->desc
;
709 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
715 rxdesc
->desc1
.bufaddrh
= cpu_to_le32((__u64
)rxbi
->mapping
>> 32);
716 rxdesc
->desc1
.bufaddrl
= cpu_to_le32(
717 (__u64
)rxbi
->mapping
& 0xFFFFFFFFUL
);
718 rxdesc
->desc1
.datalen
= cpu_to_le16(rxbi
->len
);
719 if (jme
->dev
->features
& NETIF_F_HIGHDMA
)
720 rxdesc
->desc1
.flags
= RXFLAG_64BIT
;
722 rxdesc
->desc1
.flags
|= RXFLAG_OWN
| RXFLAG_INT
;
726 jme_make_new_rx_buf(struct jme_adapter
*jme
, int i
)
728 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
729 struct jme_buffer_info
*rxbi
= rxring
->bufinf
+ i
;
733 skb
= netdev_alloc_skb(jme
->dev
,
734 jme
->dev
->mtu
+ RX_EXTRA_LEN
);
738 mapping
= pci_map_page(jme
->pdev
, virt_to_page(skb
->data
),
739 offset_in_page(skb
->data
), skb_tailroom(skb
),
741 if (unlikely(pci_dma_mapping_error(jme
->pdev
, mapping
))) {
746 if (likely(rxbi
->mapping
))
747 pci_unmap_page(jme
->pdev
, rxbi
->mapping
,
748 rxbi
->len
, PCI_DMA_FROMDEVICE
);
751 rxbi
->len
= skb_tailroom(skb
);
752 rxbi
->mapping
= mapping
;
757 jme_free_rx_buf(struct jme_adapter
*jme
, int i
)
759 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
760 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
764 pci_unmap_page(jme
->pdev
,
768 dev_kfree_skb(rxbi
->skb
);
776 jme_free_rx_resources(struct jme_adapter
*jme
)
779 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
782 if (rxring
->bufinf
) {
783 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
)
784 jme_free_rx_buf(jme
, i
);
785 kfree(rxring
->bufinf
);
788 dma_free_coherent(&(jme
->pdev
->dev
),
789 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
792 rxring
->alloc
= NULL
;
794 rxring
->dmaalloc
= 0;
796 rxring
->bufinf
= NULL
;
798 rxring
->next_to_use
= 0;
799 atomic_set(&rxring
->next_to_clean
, 0);
803 jme_setup_rx_resources(struct jme_adapter
*jme
)
806 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
808 rxring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
809 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
818 rxring
->desc
= (void *)ALIGN((unsigned long)(rxring
->alloc
),
820 rxring
->dma
= ALIGN(rxring
->dmaalloc
, RING_DESC_ALIGN
);
821 rxring
->next_to_use
= 0;
822 atomic_set(&rxring
->next_to_clean
, 0);
824 rxring
->bufinf
= kcalloc(jme
->rx_ring_size
,
825 sizeof(struct jme_buffer_info
),
827 if (unlikely(!(rxring
->bufinf
)))
828 goto err_free_rxring
;
831 * Initiallize Receive Descriptors
833 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
) {
834 if (unlikely(jme_make_new_rx_buf(jme
, i
))) {
835 jme_free_rx_resources(jme
);
839 jme_set_clean_rxdesc(jme
, i
);
845 dma_free_coherent(&(jme
->pdev
->dev
),
846 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
851 rxring
->dmaalloc
= 0;
853 rxring
->bufinf
= NULL
;
859 jme_enable_rx_engine(struct jme_adapter
*jme
)
864 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
869 * Setup RX DMA Bass Address
871 jwrite32(jme
, JME_RXDBA_LO
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
872 jwrite32(jme
, JME_RXDBA_HI
, (__u64
)(jme
->rxring
[0].dma
) >> 32);
873 jwrite32(jme
, JME_RXNDA
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
876 * Setup RX Descriptor Count
878 jwrite32(jme
, JME_RXQDC
, jme
->rx_ring_size
);
881 * Setup Unicast Filter
883 jme_set_unicastaddr(jme
->dev
);
884 jme_set_multi(jme
->dev
);
890 jwrite32f(jme
, JME_RXCS
, jme
->reg_rxcs
|
896 * Start clock for RX MAC Processor
898 jme_mac_rxclk_on(jme
);
902 jme_restart_rx_engine(struct jme_adapter
*jme
)
907 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
914 jme_disable_rx_engine(struct jme_adapter
*jme
)
922 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
);
925 val
= jread32(jme
, JME_RXCS
);
926 for (i
= JME_RX_DISABLE_TIMEOUT
; (val
& RXCS_ENABLE
) && i
> 0 ; --i
) {
928 val
= jread32(jme
, JME_RXCS
);
933 pr_err("Disable RX engine timeout\n");
936 * Stop clock for RX MAC Processor
938 jme_mac_rxclk_off(jme
);
942 jme_udpsum(struct sk_buff
*skb
)
946 if (skb
->len
< (ETH_HLEN
+ sizeof(struct iphdr
)))
948 if (skb
->protocol
!= htons(ETH_P_IP
))
950 skb_set_network_header(skb
, ETH_HLEN
);
951 if ((ip_hdr(skb
)->protocol
!= IPPROTO_UDP
) ||
952 (skb
->len
< (ETH_HLEN
+
953 (ip_hdr(skb
)->ihl
<< 2) +
954 sizeof(struct udphdr
)))) {
955 skb_reset_network_header(skb
);
958 skb_set_transport_header(skb
,
959 ETH_HLEN
+ (ip_hdr(skb
)->ihl
<< 2));
960 csum
= udp_hdr(skb
)->check
;
961 skb_reset_transport_header(skb
);
962 skb_reset_network_header(skb
);
968 jme_rxsum_ok(struct jme_adapter
*jme
, u16 flags
, struct sk_buff
*skb
)
970 if (!(flags
& (RXWBFLAG_TCPON
| RXWBFLAG_UDPON
| RXWBFLAG_IPV4
)))
973 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_TCPON
| RXWBFLAG_TCPCS
))
974 == RXWBFLAG_TCPON
)) {
975 if (flags
& RXWBFLAG_IPV4
)
976 netif_err(jme
, rx_err
, jme
->dev
, "TCP Checksum error\n");
980 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_UDPON
| RXWBFLAG_UDPCS
))
981 == RXWBFLAG_UDPON
) && jme_udpsum(skb
)) {
982 if (flags
& RXWBFLAG_IPV4
)
983 netif_err(jme
, rx_err
, jme
->dev
, "UDP Checksum error\n");
987 if (unlikely((flags
& (RXWBFLAG_IPV4
| RXWBFLAG_IPCS
))
989 netif_err(jme
, rx_err
, jme
->dev
, "IPv4 Checksum error\n");
997 jme_alloc_and_feed_skb(struct jme_adapter
*jme
, int idx
)
999 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
1000 struct rxdesc
*rxdesc
= rxring
->desc
;
1001 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
1002 struct sk_buff
*skb
;
1009 pci_dma_sync_single_for_cpu(jme
->pdev
,
1012 PCI_DMA_FROMDEVICE
);
1014 if (unlikely(jme_make_new_rx_buf(jme
, idx
))) {
1015 pci_dma_sync_single_for_device(jme
->pdev
,
1018 PCI_DMA_FROMDEVICE
);
1020 ++(NET_STAT(jme
).rx_dropped
);
1022 framesize
= le16_to_cpu(rxdesc
->descwb
.framesize
)
1025 skb_reserve(skb
, RX_PREPAD_SIZE
);
1026 skb_put(skb
, framesize
);
1027 skb
->protocol
= eth_type_trans(skb
, jme
->dev
);
1029 if (jme_rxsum_ok(jme
, le16_to_cpu(rxdesc
->descwb
.flags
), skb
))
1030 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1032 skb_checksum_none_assert(skb
);
1034 if (rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_TAGON
)) {
1035 u16 vid
= le16_to_cpu(rxdesc
->descwb
.vlan
);
1037 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vid
);
1038 NET_STAT(jme
).rx_bytes
+= 4;
1042 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_DEST
)) ==
1043 cpu_to_le16(RXWBFLAG_DEST_MUL
))
1044 ++(NET_STAT(jme
).multicast
);
1046 NET_STAT(jme
).rx_bytes
+= framesize
;
1047 ++(NET_STAT(jme
).rx_packets
);
1050 jme_set_clean_rxdesc(jme
, idx
);
1055 jme_process_receive(struct jme_adapter
*jme
, int limit
)
1057 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
1058 struct rxdesc
*rxdesc
;
1059 int i
, j
, ccnt
, desccnt
, mask
= jme
->rx_ring_mask
;
1061 if (unlikely(!atomic_dec_and_test(&jme
->rx_cleaning
)))
1064 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1067 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1070 i
= atomic_read(&rxring
->next_to_clean
);
1072 rxdesc
= rxring
->desc
;
1075 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_OWN
)) ||
1076 !(rxdesc
->descwb
.desccnt
& RXWBDCNT_WBCPL
))
1081 desccnt
= rxdesc
->descwb
.desccnt
& RXWBDCNT_DCNT
;
1083 if (unlikely(desccnt
> 1 ||
1084 rxdesc
->descwb
.errstat
& RXWBERR_ALLERR
)) {
1086 if (rxdesc
->descwb
.errstat
& RXWBERR_CRCERR
)
1087 ++(NET_STAT(jme
).rx_crc_errors
);
1088 else if (rxdesc
->descwb
.errstat
& RXWBERR_OVERUN
)
1089 ++(NET_STAT(jme
).rx_fifo_errors
);
1091 ++(NET_STAT(jme
).rx_errors
);
1094 limit
-= desccnt
- 1;
1096 for (j
= i
, ccnt
= desccnt
; ccnt
-- ; ) {
1097 jme_set_clean_rxdesc(jme
, j
);
1098 j
= (j
+ 1) & (mask
);
1102 jme_alloc_and_feed_skb(jme
, i
);
1105 i
= (i
+ desccnt
) & (mask
);
1109 atomic_set(&rxring
->next_to_clean
, i
);
1112 atomic_inc(&jme
->rx_cleaning
);
1114 return limit
> 0 ? limit
: 0;
1119 jme_attempt_pcc(struct dynpcc_info
*dpi
, int atmp
)
1121 if (likely(atmp
== dpi
->cur
)) {
1126 if (dpi
->attempt
== atmp
) {
1129 dpi
->attempt
= atmp
;
1136 jme_dynamic_pcc(struct jme_adapter
*jme
)
1138 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
1140 if ((NET_STAT(jme
).rx_bytes
- dpi
->last_bytes
) > PCC_P3_THRESHOLD
)
1141 jme_attempt_pcc(dpi
, PCC_P3
);
1142 else if ((NET_STAT(jme
).rx_packets
- dpi
->last_pkts
) > PCC_P2_THRESHOLD
||
1143 dpi
->intr_cnt
> PCC_INTR_THRESHOLD
)
1144 jme_attempt_pcc(dpi
, PCC_P2
);
1146 jme_attempt_pcc(dpi
, PCC_P1
);
1148 if (unlikely(dpi
->attempt
!= dpi
->cur
&& dpi
->cnt
> 5)) {
1149 if (dpi
->attempt
< dpi
->cur
)
1150 tasklet_schedule(&jme
->rxclean_task
);
1151 jme_set_rx_pcc(jme
, dpi
->attempt
);
1152 dpi
->cur
= dpi
->attempt
;
1158 jme_start_pcc_timer(struct jme_adapter
*jme
)
1160 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1161 dpi
->last_bytes
= NET_STAT(jme
).rx_bytes
;
1162 dpi
->last_pkts
= NET_STAT(jme
).rx_packets
;
1164 jwrite32(jme
, JME_TMCSR
,
1165 TMCSR_EN
| ((0xFFFFFF - PCC_INTERVAL_US
) & TMCSR_CNT
));
1169 jme_stop_pcc_timer(struct jme_adapter
*jme
)
1171 jwrite32(jme
, JME_TMCSR
, 0);
1175 jme_shutdown_nic(struct jme_adapter
*jme
)
1179 phylink
= jme_linkstat_from_phy(jme
);
1181 if (!(phylink
& PHY_LINK_UP
)) {
1183 * Disable all interrupt before issue timer
1186 jwrite32(jme
, JME_TIMER2
, TMCSR_EN
| 0xFFFFFE);
1191 jme_pcc_tasklet(unsigned long arg
)
1193 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1194 struct net_device
*netdev
= jme
->dev
;
1196 if (unlikely(test_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
))) {
1197 jme_shutdown_nic(jme
);
1201 if (unlikely(!netif_carrier_ok(netdev
) ||
1202 (atomic_read(&jme
->link_changing
) != 1)
1204 jme_stop_pcc_timer(jme
);
1208 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
1209 jme_dynamic_pcc(jme
);
1211 jme_start_pcc_timer(jme
);
1215 jme_polling_mode(struct jme_adapter
*jme
)
1217 jme_set_rx_pcc(jme
, PCC_OFF
);
1221 jme_interrupt_mode(struct jme_adapter
*jme
)
1223 jme_set_rx_pcc(jme
, PCC_P1
);
1227 jme_pseudo_hotplug_enabled(struct jme_adapter
*jme
)
1230 apmc
= jread32(jme
, JME_APMC
);
1231 return apmc
& JME_APMC_PSEUDO_HP_EN
;
1235 jme_start_shutdown_timer(struct jme_adapter
*jme
)
1239 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PCIE_SD_EN
;
1240 apmc
&= ~JME_APMC_EPIEN_CTRL
;
1242 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_EN
);
1245 jwrite32f(jme
, JME_APMC
, apmc
);
1247 jwrite32f(jme
, JME_TIMER2
, 0);
1248 set_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1249 jwrite32(jme
, JME_TMCSR
,
1250 TMCSR_EN
| ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY
) & TMCSR_CNT
));
1254 jme_stop_shutdown_timer(struct jme_adapter
*jme
)
1258 jwrite32f(jme
, JME_TMCSR
, 0);
1259 jwrite32f(jme
, JME_TIMER2
, 0);
1260 clear_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1262 apmc
= jread32(jme
, JME_APMC
);
1263 apmc
&= ~(JME_APMC_PCIE_SD_EN
| JME_APMC_EPIEN_CTRL
);
1264 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_DIS
);
1266 jwrite32f(jme
, JME_APMC
, apmc
);
1270 jme_link_change_tasklet(unsigned long arg
)
1272 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1273 struct net_device
*netdev
= jme
->dev
;
1276 while (!atomic_dec_and_test(&jme
->link_changing
)) {
1277 atomic_inc(&jme
->link_changing
);
1278 netif_info(jme
, intr
, jme
->dev
, "Get link change lock failed\n");
1279 while (atomic_read(&jme
->link_changing
) != 1)
1280 netif_info(jme
, intr
, jme
->dev
, "Waiting link change lock\n");
1283 if (jme_check_link(netdev
, 1) && jme
->old_mtu
== netdev
->mtu
)
1286 jme
->old_mtu
= netdev
->mtu
;
1287 netif_stop_queue(netdev
);
1288 if (jme_pseudo_hotplug_enabled(jme
))
1289 jme_stop_shutdown_timer(jme
);
1291 jme_stop_pcc_timer(jme
);
1292 tasklet_disable(&jme
->txclean_task
);
1293 tasklet_disable(&jme
->rxclean_task
);
1294 tasklet_disable(&jme
->rxempty_task
);
1296 if (netif_carrier_ok(netdev
)) {
1297 jme_disable_rx_engine(jme
);
1298 jme_disable_tx_engine(jme
);
1299 jme_reset_mac_processor(jme
);
1300 jme_free_rx_resources(jme
);
1301 jme_free_tx_resources(jme
);
1303 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1304 jme_polling_mode(jme
);
1306 netif_carrier_off(netdev
);
1309 jme_check_link(netdev
, 0);
1310 if (netif_carrier_ok(netdev
)) {
1311 rc
= jme_setup_rx_resources(jme
);
1313 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1314 goto out_enable_tasklet
;
1317 rc
= jme_setup_tx_resources(jme
);
1319 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1320 goto err_out_free_rx_resources
;
1323 jme_enable_rx_engine(jme
);
1324 jme_enable_tx_engine(jme
);
1326 netif_start_queue(netdev
);
1328 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1329 jme_interrupt_mode(jme
);
1331 jme_start_pcc_timer(jme
);
1332 } else if (jme_pseudo_hotplug_enabled(jme
)) {
1333 jme_start_shutdown_timer(jme
);
1336 goto out_enable_tasklet
;
1338 err_out_free_rx_resources
:
1339 jme_free_rx_resources(jme
);
1341 tasklet_enable(&jme
->txclean_task
);
1342 tasklet_enable(&jme
->rxclean_task
);
1343 tasklet_enable(&jme
->rxempty_task
);
1345 atomic_inc(&jme
->link_changing
);
1349 jme_rx_clean_tasklet(unsigned long arg
)
1351 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1352 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1354 jme_process_receive(jme
, jme
->rx_ring_size
);
1360 jme_poll(JME_NAPI_HOLDER(holder
), JME_NAPI_WEIGHT(budget
))
1362 struct jme_adapter
*jme
= jme_napi_priv(holder
);
1365 rest
= jme_process_receive(jme
, JME_NAPI_WEIGHT_VAL(budget
));
1367 while (atomic_read(&jme
->rx_empty
) > 0) {
1368 atomic_dec(&jme
->rx_empty
);
1369 ++(NET_STAT(jme
).rx_dropped
);
1370 jme_restart_rx_engine(jme
);
1372 atomic_inc(&jme
->rx_empty
);
1375 JME_RX_COMPLETE(netdev
, holder
);
1376 jme_interrupt_mode(jme
);
1379 JME_NAPI_WEIGHT_SET(budget
, rest
);
1380 return JME_NAPI_WEIGHT_VAL(budget
) - rest
;
1384 jme_rx_empty_tasklet(unsigned long arg
)
1386 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1388 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1391 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1394 netif_info(jme
, rx_status
, jme
->dev
, "RX Queue Full!\n");
1396 jme_rx_clean_tasklet(arg
);
1398 while (atomic_read(&jme
->rx_empty
) > 0) {
1399 atomic_dec(&jme
->rx_empty
);
1400 ++(NET_STAT(jme
).rx_dropped
);
1401 jme_restart_rx_engine(jme
);
1403 atomic_inc(&jme
->rx_empty
);
1407 jme_wake_queue_if_stopped(struct jme_adapter
*jme
)
1409 struct jme_ring
*txring
= &(jme
->txring
[0]);
1412 if (unlikely(netif_queue_stopped(jme
->dev
) &&
1413 atomic_read(&txring
->nr_free
) >= (jme
->tx_wake_threshold
))) {
1414 netif_info(jme
, tx_done
, jme
->dev
, "TX Queue Waked\n");
1415 netif_wake_queue(jme
->dev
);
1421 jme_tx_clean_tasklet(unsigned long arg
)
1423 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1424 struct jme_ring
*txring
= &(jme
->txring
[0]);
1425 struct txdesc
*txdesc
= txring
->desc
;
1426 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
, *ttxbi
;
1427 int i
, j
, cnt
= 0, max
, err
, mask
;
1429 tx_dbg(jme
, "Into txclean\n");
1431 if (unlikely(!atomic_dec_and_test(&jme
->tx_cleaning
)))
1434 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1437 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1440 max
= jme
->tx_ring_size
- atomic_read(&txring
->nr_free
);
1441 mask
= jme
->tx_ring_mask
;
1443 for (i
= atomic_read(&txring
->next_to_clean
) ; cnt
< max
; ) {
1447 if (likely(ctxbi
->skb
&&
1448 !(txdesc
[i
].descwb
.flags
& TXWBFLAG_OWN
))) {
1450 tx_dbg(jme
, "txclean: %d+%d@%lu\n",
1451 i
, ctxbi
->nr_desc
, jiffies
);
1453 err
= txdesc
[i
].descwb
.flags
& TXWBFLAG_ALLERR
;
1455 for (j
= 1 ; j
< ctxbi
->nr_desc
; ++j
) {
1456 ttxbi
= txbi
+ ((i
+ j
) & (mask
));
1457 txdesc
[(i
+ j
) & (mask
)].dw
[0] = 0;
1459 pci_unmap_page(jme
->pdev
,
1468 dev_kfree_skb(ctxbi
->skb
);
1470 cnt
+= ctxbi
->nr_desc
;
1472 if (unlikely(err
)) {
1473 ++(NET_STAT(jme
).tx_carrier_errors
);
1475 ++(NET_STAT(jme
).tx_packets
);
1476 NET_STAT(jme
).tx_bytes
+= ctxbi
->len
;
1481 ctxbi
->start_xmit
= 0;
1487 i
= (i
+ ctxbi
->nr_desc
) & mask
;
1492 tx_dbg(jme
, "txclean: done %d@%lu\n", i
, jiffies
);
1493 atomic_set(&txring
->next_to_clean
, i
);
1494 atomic_add(cnt
, &txring
->nr_free
);
1496 jme_wake_queue_if_stopped(jme
);
1499 atomic_inc(&jme
->tx_cleaning
);
1503 jme_intr_msi(struct jme_adapter
*jme
, u32 intrstat
)
1508 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
1510 if (intrstat
& (INTR_LINKCH
| INTR_SWINTR
)) {
1512 * Link change event is critical
1513 * all other events are ignored
1515 jwrite32(jme
, JME_IEVE
, intrstat
);
1516 tasklet_schedule(&jme
->linkch_task
);
1520 if (intrstat
& INTR_TMINTR
) {
1521 jwrite32(jme
, JME_IEVE
, INTR_TMINTR
);
1522 tasklet_schedule(&jme
->pcc_task
);
1525 if (intrstat
& (INTR_PCCTXTO
| INTR_PCCTX
)) {
1526 jwrite32(jme
, JME_IEVE
, INTR_PCCTXTO
| INTR_PCCTX
| INTR_TX0
);
1527 tasklet_schedule(&jme
->txclean_task
);
1530 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1531 jwrite32(jme
, JME_IEVE
, (intrstat
& (INTR_PCCRX0TO
|
1537 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
1538 if (intrstat
& INTR_RX0EMP
)
1539 atomic_inc(&jme
->rx_empty
);
1541 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1542 if (likely(JME_RX_SCHEDULE_PREP(jme
))) {
1543 jme_polling_mode(jme
);
1544 JME_RX_SCHEDULE(jme
);
1548 if (intrstat
& INTR_RX0EMP
) {
1549 atomic_inc(&jme
->rx_empty
);
1550 tasklet_hi_schedule(&jme
->rxempty_task
);
1551 } else if (intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
)) {
1552 tasklet_hi_schedule(&jme
->rxclean_task
);
1558 * Re-enable interrupt
1560 jwrite32f(jme
, JME_IENS
, INTR_ENABLE
);
1564 jme_intr(int irq
, void *dev_id
)
1566 struct net_device
*netdev
= dev_id
;
1567 struct jme_adapter
*jme
= netdev_priv(netdev
);
1570 intrstat
= jread32(jme
, JME_IEVE
);
1573 * Check if it's really an interrupt for us
1575 if (unlikely((intrstat
& INTR_ENABLE
) == 0))
1579 * Check if the device still exist
1581 if (unlikely(intrstat
== ~((typeof(intrstat
))0)))
1584 jme_intr_msi(jme
, intrstat
);
1590 jme_msi(int irq
, void *dev_id
)
1592 struct net_device
*netdev
= dev_id
;
1593 struct jme_adapter
*jme
= netdev_priv(netdev
);
1596 intrstat
= jread32(jme
, JME_IEVE
);
1598 jme_intr_msi(jme
, intrstat
);
1604 jme_reset_link(struct jme_adapter
*jme
)
1606 jwrite32(jme
, JME_TMCSR
, TMCSR_SWIT
);
1610 jme_restart_an(struct jme_adapter
*jme
)
1614 spin_lock_bh(&jme
->phy_lock
);
1615 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1616 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1617 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1618 spin_unlock_bh(&jme
->phy_lock
);
1622 jme_request_irq(struct jme_adapter
*jme
)
1625 struct net_device
*netdev
= jme
->dev
;
1626 irq_handler_t handler
= jme_intr
;
1627 int irq_flags
= IRQF_SHARED
;
1629 if (!pci_enable_msi(jme
->pdev
)) {
1630 set_bit(JME_FLAG_MSI
, &jme
->flags
);
1635 rc
= request_irq(jme
->pdev
->irq
, handler
, irq_flags
, netdev
->name
,
1639 "Unable to request %s interrupt (return: %d)\n",
1640 test_bit(JME_FLAG_MSI
, &jme
->flags
) ? "MSI" : "INTx",
1643 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1644 pci_disable_msi(jme
->pdev
);
1645 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1648 netdev
->irq
= jme
->pdev
->irq
;
1655 jme_free_irq(struct jme_adapter
*jme
)
1657 free_irq(jme
->pdev
->irq
, jme
->dev
);
1658 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1659 pci_disable_msi(jme
->pdev
);
1660 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1661 jme
->dev
->irq
= jme
->pdev
->irq
;
1666 jme_new_phy_on(struct jme_adapter
*jme
)
1670 reg
= jread32(jme
, JME_PHY_PWR
);
1671 reg
&= ~(PHY_PWR_DWN1SEL
| PHY_PWR_DWN1SW
|
1672 PHY_PWR_DWN2
| PHY_PWR_CLKSEL
);
1673 jwrite32(jme
, JME_PHY_PWR
, reg
);
1675 pci_read_config_dword(jme
->pdev
, PCI_PRIV_PE1
, ®
);
1676 reg
&= ~PE1_GPREG0_PBG
;
1677 reg
|= PE1_GPREG0_ENBG
;
1678 pci_write_config_dword(jme
->pdev
, PCI_PRIV_PE1
, reg
);
1682 jme_new_phy_off(struct jme_adapter
*jme
)
1686 reg
= jread32(jme
, JME_PHY_PWR
);
1687 reg
|= PHY_PWR_DWN1SEL
| PHY_PWR_DWN1SW
|
1688 PHY_PWR_DWN2
| PHY_PWR_CLKSEL
;
1689 jwrite32(jme
, JME_PHY_PWR
, reg
);
1691 pci_read_config_dword(jme
->pdev
, PCI_PRIV_PE1
, ®
);
1692 reg
&= ~PE1_GPREG0_PBG
;
1693 reg
|= PE1_GPREG0_PDD3COLD
;
1694 pci_write_config_dword(jme
->pdev
, PCI_PRIV_PE1
, reg
);
1698 jme_phy_on(struct jme_adapter
*jme
)
1702 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1703 bmcr
&= ~BMCR_PDOWN
;
1704 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1706 if (new_phy_power_ctrl(jme
->chip_main_rev
))
1707 jme_new_phy_on(jme
);
1711 jme_phy_off(struct jme_adapter
*jme
)
1715 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1717 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1719 if (new_phy_power_ctrl(jme
->chip_main_rev
))
1720 jme_new_phy_off(jme
);
1724 jme_phy_specreg_read(struct jme_adapter
*jme
, u32 specreg
)
1728 phy_addr
= JM_PHY_SPEC_REG_READ
| specreg
;
1729 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, JM_PHY_SPEC_ADDR_REG
,
1731 return jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
,
1732 JM_PHY_SPEC_DATA_REG
);
1736 jme_phy_specreg_write(struct jme_adapter
*jme
, u32 ext_reg
, u32 phy_data
)
1740 phy_addr
= JM_PHY_SPEC_REG_WRITE
| ext_reg
;
1741 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, JM_PHY_SPEC_DATA_REG
,
1743 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, JM_PHY_SPEC_ADDR_REG
,
1748 jme_phy_calibration(struct jme_adapter
*jme
)
1750 u32 ctrl1000
, phy_data
;
1754 /* Enabel PHY test mode 1 */
1755 ctrl1000
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
);
1756 ctrl1000
&= ~PHY_GAD_TEST_MODE_MSK
;
1757 ctrl1000
|= PHY_GAD_TEST_MODE_1
;
1758 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
, ctrl1000
);
1760 phy_data
= jme_phy_specreg_read(jme
, JM_PHY_EXT_COMM_2_REG
);
1761 phy_data
&= ~JM_PHY_EXT_COMM_2_CALI_MODE_0
;
1762 phy_data
|= JM_PHY_EXT_COMM_2_CALI_LATCH
|
1763 JM_PHY_EXT_COMM_2_CALI_ENABLE
;
1764 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_2_REG
, phy_data
);
1766 phy_data
= jme_phy_specreg_read(jme
, JM_PHY_EXT_COMM_2_REG
);
1767 phy_data
&= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE
|
1768 JM_PHY_EXT_COMM_2_CALI_MODE_0
|
1769 JM_PHY_EXT_COMM_2_CALI_LATCH
);
1770 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_2_REG
, phy_data
);
1772 /* Disable PHY test mode */
1773 ctrl1000
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
);
1774 ctrl1000
&= ~PHY_GAD_TEST_MODE_MSK
;
1775 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_CTRL1000
, ctrl1000
);
1780 jme_phy_setEA(struct jme_adapter
*jme
)
1782 u32 phy_comm0
= 0, phy_comm1
= 0;
1785 pci_read_config_byte(jme
->pdev
, PCI_PRIV_SHARE_NICCTRL
, &nic_ctrl
);
1786 if ((nic_ctrl
& 0x3) == JME_FLAG_PHYEA_ENABLE
)
1789 switch (jme
->pdev
->device
) {
1790 case PCI_DEVICE_ID_JMICRON_JMC250
:
1791 if (((jme
->chip_main_rev
== 5) &&
1792 ((jme
->chip_sub_rev
== 0) || (jme
->chip_sub_rev
== 1) ||
1793 (jme
->chip_sub_rev
== 3))) ||
1794 (jme
->chip_main_rev
>= 6)) {
1798 if ((jme
->chip_main_rev
== 3) &&
1799 ((jme
->chip_sub_rev
== 1) || (jme
->chip_sub_rev
== 2)))
1802 case PCI_DEVICE_ID_JMICRON_JMC260
:
1803 if (((jme
->chip_main_rev
== 5) &&
1804 ((jme
->chip_sub_rev
== 0) || (jme
->chip_sub_rev
== 1) ||
1805 (jme
->chip_sub_rev
== 3))) ||
1806 (jme
->chip_main_rev
>= 6)) {
1810 if ((jme
->chip_main_rev
== 3) &&
1811 ((jme
->chip_sub_rev
== 1) || (jme
->chip_sub_rev
== 2)))
1813 if ((jme
->chip_main_rev
== 2) && (jme
->chip_sub_rev
== 0))
1815 if ((jme
->chip_main_rev
== 2) && (jme
->chip_sub_rev
== 2))
1822 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_0_REG
, phy_comm0
);
1824 jme_phy_specreg_write(jme
, JM_PHY_EXT_COMM_1_REG
, phy_comm1
);
1830 jme_open(struct net_device
*netdev
)
1832 struct jme_adapter
*jme
= netdev_priv(netdev
);
1835 jme_clear_pm_disable_wol(jme
);
1836 JME_NAPI_ENABLE(jme
);
1838 tasklet_init(&jme
->linkch_task
, jme_link_change_tasklet
,
1839 (unsigned long) jme
);
1840 tasklet_init(&jme
->txclean_task
, jme_tx_clean_tasklet
,
1841 (unsigned long) jme
);
1842 tasklet_init(&jme
->rxclean_task
, jme_rx_clean_tasklet
,
1843 (unsigned long) jme
);
1844 tasklet_init(&jme
->rxempty_task
, jme_rx_empty_tasklet
,
1845 (unsigned long) jme
);
1847 rc
= jme_request_irq(jme
);
1854 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
1855 jme_set_link_ksettings(netdev
, &jme
->old_cmd
);
1857 jme_reset_phy_processor(jme
);
1858 jme_phy_calibration(jme
);
1860 jme_reset_link(jme
);
1865 netif_stop_queue(netdev
);
1866 netif_carrier_off(netdev
);
1871 jme_set_100m_half(struct jme_adapter
*jme
)
1876 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1877 tmp
= bmcr
& ~(BMCR_ANENABLE
| BMCR_SPEED100
|
1878 BMCR_SPEED1000
| BMCR_FULLDPLX
);
1879 tmp
|= BMCR_SPEED100
;
1882 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, tmp
);
1885 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
| GHC_LINK_POLL
);
1887 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
);
1890 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1892 jme_wait_link(struct jme_adapter
*jme
)
1894 u32 phylink
, to
= JME_WAIT_LINK_TIME
;
1897 phylink
= jme_linkstat_from_phy(jme
);
1898 while (!(phylink
& PHY_LINK_UP
) && (to
-= 10) > 0) {
1899 usleep_range(10000, 11000);
1900 phylink
= jme_linkstat_from_phy(jme
);
1905 jme_powersave_phy(struct jme_adapter
*jme
)
1907 if (jme
->reg_pmcs
&& device_may_wakeup(&jme
->pdev
->dev
)) {
1908 jme_set_100m_half(jme
);
1909 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
1911 jme_clear_pm_enable_wol(jme
);
1918 jme_close(struct net_device
*netdev
)
1920 struct jme_adapter
*jme
= netdev_priv(netdev
);
1922 netif_stop_queue(netdev
);
1923 netif_carrier_off(netdev
);
1928 JME_NAPI_DISABLE(jme
);
1930 tasklet_kill(&jme
->linkch_task
);
1931 tasklet_kill(&jme
->txclean_task
);
1932 tasklet_kill(&jme
->rxclean_task
);
1933 tasklet_kill(&jme
->rxempty_task
);
1935 jme_disable_rx_engine(jme
);
1936 jme_disable_tx_engine(jme
);
1937 jme_reset_mac_processor(jme
);
1938 jme_free_rx_resources(jme
);
1939 jme_free_tx_resources(jme
);
1947 jme_alloc_txdesc(struct jme_adapter
*jme
,
1948 struct sk_buff
*skb
)
1950 struct jme_ring
*txring
= &(jme
->txring
[0]);
1951 int idx
, nr_alloc
, mask
= jme
->tx_ring_mask
;
1953 idx
= txring
->next_to_use
;
1954 nr_alloc
= skb_shinfo(skb
)->nr_frags
+ 2;
1956 if (unlikely(atomic_read(&txring
->nr_free
) < nr_alloc
))
1959 atomic_sub(nr_alloc
, &txring
->nr_free
);
1961 txring
->next_to_use
= (txring
->next_to_use
+ nr_alloc
) & mask
;
1967 jme_fill_tx_map(struct pci_dev
*pdev
,
1968 struct txdesc
*txdesc
,
1969 struct jme_buffer_info
*txbi
,
1977 dmaaddr
= pci_map_page(pdev
,
1983 if (unlikely(pci_dma_mapping_error(pdev
, dmaaddr
)))
1986 pci_dma_sync_single_for_device(pdev
,
1993 txdesc
->desc2
.flags
= TXFLAG_OWN
;
1994 txdesc
->desc2
.flags
|= (hidma
) ? TXFLAG_64BIT
: 0;
1995 txdesc
->desc2
.datalen
= cpu_to_le16(len
);
1996 txdesc
->desc2
.bufaddrh
= cpu_to_le32((__u64
)dmaaddr
>> 32);
1997 txdesc
->desc2
.bufaddrl
= cpu_to_le32(
1998 (__u64
)dmaaddr
& 0xFFFFFFFFUL
);
2000 txbi
->mapping
= dmaaddr
;
2005 static void jme_drop_tx_map(struct jme_adapter
*jme
, int startidx
, int count
)
2007 struct jme_ring
*txring
= &(jme
->txring
[0]);
2008 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
;
2009 int mask
= jme
->tx_ring_mask
;
2012 for (j
= 0 ; j
< count
; j
++) {
2013 ctxbi
= txbi
+ ((startidx
+ j
+ 2) & (mask
));
2014 pci_unmap_page(jme
->pdev
,
2025 jme_map_tx_skb(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
2027 struct jme_ring
*txring
= &(jme
->txring
[0]);
2028 struct txdesc
*txdesc
= txring
->desc
, *ctxdesc
;
2029 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
;
2030 bool hidma
= jme
->dev
->features
& NETIF_F_HIGHDMA
;
2031 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
2032 int mask
= jme
->tx_ring_mask
;
2033 const struct skb_frag_struct
*frag
;
2037 for (i
= 0 ; i
< nr_frags
; ++i
) {
2038 frag
= &skb_shinfo(skb
)->frags
[i
];
2039 ctxdesc
= txdesc
+ ((idx
+ i
+ 2) & (mask
));
2040 ctxbi
= txbi
+ ((idx
+ i
+ 2) & (mask
));
2042 ret
= jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
,
2043 skb_frag_page(frag
),
2044 frag
->page_offset
, skb_frag_size(frag
), hidma
);
2046 jme_drop_tx_map(jme
, idx
, i
);
2052 len
= skb_is_nonlinear(skb
) ? skb_headlen(skb
) : skb
->len
;
2053 ctxdesc
= txdesc
+ ((idx
+ 1) & (mask
));
2054 ctxbi
= txbi
+ ((idx
+ 1) & (mask
));
2055 ret
= jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
, virt_to_page(skb
->data
),
2056 offset_in_page(skb
->data
), len
, hidma
);
2058 jme_drop_tx_map(jme
, idx
, i
);
2067 jme_tx_tso(struct sk_buff
*skb
, __le16
*mss
, u8
*flags
)
2069 *mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
<< TXDESC_MSS_SHIFT
);
2071 *flags
|= TXFLAG_LSEN
;
2073 if (skb
->protocol
== htons(ETH_P_IP
)) {
2074 struct iphdr
*iph
= ip_hdr(skb
);
2077 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
2082 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
2084 tcp_hdr(skb
)->check
= ~csum_ipv6_magic(&ip6h
->saddr
,
2097 jme_tx_csum(struct jme_adapter
*jme
, struct sk_buff
*skb
, u8
*flags
)
2099 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2102 switch (skb
->protocol
) {
2103 case htons(ETH_P_IP
):
2104 ip_proto
= ip_hdr(skb
)->protocol
;
2106 case htons(ETH_P_IPV6
):
2107 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
2116 *flags
|= TXFLAG_TCPCS
;
2119 *flags
|= TXFLAG_UDPCS
;
2122 netif_err(jme
, tx_err
, jme
->dev
, "Error upper layer protocol\n");
2129 jme_tx_vlan(struct sk_buff
*skb
, __le16
*vlan
, u8
*flags
)
2131 if (skb_vlan_tag_present(skb
)) {
2132 *flags
|= TXFLAG_TAGON
;
2133 *vlan
= cpu_to_le16(skb_vlan_tag_get(skb
));
2138 jme_fill_tx_desc(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
2140 struct jme_ring
*txring
= &(jme
->txring
[0]);
2141 struct txdesc
*txdesc
;
2142 struct jme_buffer_info
*txbi
;
2146 txdesc
= (struct txdesc
*)txring
->desc
+ idx
;
2147 txbi
= txring
->bufinf
+ idx
;
2153 txdesc
->desc1
.pktsize
= cpu_to_le16(skb
->len
);
2155 * Set OWN bit at final.
2156 * When kernel transmit faster than NIC.
2157 * And NIC trying to send this descriptor before we tell
2158 * it to start sending this TX queue.
2159 * Other fields are already filled correctly.
2162 flags
= TXFLAG_OWN
| TXFLAG_INT
;
2164 * Set checksum flags while not tso
2166 if (jme_tx_tso(skb
, &txdesc
->desc1
.mss
, &flags
))
2167 jme_tx_csum(jme
, skb
, &flags
);
2168 jme_tx_vlan(skb
, &txdesc
->desc1
.vlan
, &flags
);
2169 ret
= jme_map_tx_skb(jme
, skb
, idx
);
2173 txdesc
->desc1
.flags
= flags
;
2175 * Set tx buffer info after telling NIC to send
2176 * For better tx_clean timing
2179 txbi
->nr_desc
= skb_shinfo(skb
)->nr_frags
+ 2;
2181 txbi
->len
= skb
->len
;
2182 txbi
->start_xmit
= jiffies
;
2183 if (!txbi
->start_xmit
)
2184 txbi
->start_xmit
= (0UL-1);
2190 jme_stop_queue_if_full(struct jme_adapter
*jme
)
2192 struct jme_ring
*txring
= &(jme
->txring
[0]);
2193 struct jme_buffer_info
*txbi
= txring
->bufinf
;
2194 int idx
= atomic_read(&txring
->next_to_clean
);
2199 if (unlikely(atomic_read(&txring
->nr_free
) < (MAX_SKB_FRAGS
+2))) {
2200 netif_stop_queue(jme
->dev
);
2201 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Paused\n");
2203 if (atomic_read(&txring
->nr_free
)
2204 >= (jme
->tx_wake_threshold
)) {
2205 netif_wake_queue(jme
->dev
);
2206 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Fast Waked\n");
2210 if (unlikely(txbi
->start_xmit
&&
2211 (jiffies
- txbi
->start_xmit
) >= TX_TIMEOUT
&&
2213 netif_stop_queue(jme
->dev
);
2214 netif_info(jme
, tx_queued
, jme
->dev
,
2215 "TX Queue Stopped %d@%lu\n", idx
, jiffies
);
2220 * This function is already protected by netif_tx_lock()
2224 jme_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2226 struct jme_adapter
*jme
= netdev_priv(netdev
);
2229 if (unlikely(skb_is_gso(skb
) && skb_cow_head(skb
, 0))) {
2230 dev_kfree_skb_any(skb
);
2231 ++(NET_STAT(jme
).tx_dropped
);
2232 return NETDEV_TX_OK
;
2235 idx
= jme_alloc_txdesc(jme
, skb
);
2237 if (unlikely(idx
< 0)) {
2238 netif_stop_queue(netdev
);
2239 netif_err(jme
, tx_err
, jme
->dev
,
2240 "BUG! Tx ring full when queue awake!\n");
2242 return NETDEV_TX_BUSY
;
2245 if (jme_fill_tx_desc(jme
, skb
, idx
))
2246 return NETDEV_TX_OK
;
2248 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
2249 TXCS_SELECT_QUEUE0
|
2253 tx_dbg(jme
, "xmit: %d+%d@%lu\n",
2254 idx
, skb_shinfo(skb
)->nr_frags
+ 2, jiffies
);
2255 jme_stop_queue_if_full(jme
);
2257 return NETDEV_TX_OK
;
2261 jme_set_unicastaddr(struct net_device
*netdev
)
2263 struct jme_adapter
*jme
= netdev_priv(netdev
);
2266 val
= (netdev
->dev_addr
[3] & 0xff) << 24 |
2267 (netdev
->dev_addr
[2] & 0xff) << 16 |
2268 (netdev
->dev_addr
[1] & 0xff) << 8 |
2269 (netdev
->dev_addr
[0] & 0xff);
2270 jwrite32(jme
, JME_RXUMA_LO
, val
);
2271 val
= (netdev
->dev_addr
[5] & 0xff) << 8 |
2272 (netdev
->dev_addr
[4] & 0xff);
2273 jwrite32(jme
, JME_RXUMA_HI
, val
);
2277 jme_set_macaddr(struct net_device
*netdev
, void *p
)
2279 struct jme_adapter
*jme
= netdev_priv(netdev
);
2280 struct sockaddr
*addr
= p
;
2282 if (netif_running(netdev
))
2285 spin_lock_bh(&jme
->macaddr_lock
);
2286 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
2287 jme_set_unicastaddr(netdev
);
2288 spin_unlock_bh(&jme
->macaddr_lock
);
2294 jme_set_multi(struct net_device
*netdev
)
2296 struct jme_adapter
*jme
= netdev_priv(netdev
);
2297 u32 mc_hash
[2] = {};
2299 spin_lock_bh(&jme
->rxmcs_lock
);
2301 jme
->reg_rxmcs
|= RXMCS_BRDFRAME
| RXMCS_UNIFRAME
;
2303 if (netdev
->flags
& IFF_PROMISC
) {
2304 jme
->reg_rxmcs
|= RXMCS_ALLFRAME
;
2305 } else if (netdev
->flags
& IFF_ALLMULTI
) {
2306 jme
->reg_rxmcs
|= RXMCS_ALLMULFRAME
;
2307 } else if (netdev
->flags
& IFF_MULTICAST
) {
2308 struct netdev_hw_addr
*ha
;
2311 jme
->reg_rxmcs
|= RXMCS_MULFRAME
| RXMCS_MULFILTERED
;
2312 netdev_for_each_mc_addr(ha
, netdev
) {
2313 bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) & 0x3F;
2314 mc_hash
[bit_nr
>> 5] |= 1 << (bit_nr
& 0x1F);
2317 jwrite32(jme
, JME_RXMCHT_LO
, mc_hash
[0]);
2318 jwrite32(jme
, JME_RXMCHT_HI
, mc_hash
[1]);
2322 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2324 spin_unlock_bh(&jme
->rxmcs_lock
);
2328 jme_change_mtu(struct net_device
*netdev
, int new_mtu
)
2330 struct jme_adapter
*jme
= netdev_priv(netdev
);
2332 netdev
->mtu
= new_mtu
;
2333 netdev_update_features(netdev
);
2335 jme_restart_rx_engine(jme
);
2336 jme_reset_link(jme
);
2342 jme_tx_timeout(struct net_device
*netdev
)
2344 struct jme_adapter
*jme
= netdev_priv(netdev
);
2347 jme_reset_phy_processor(jme
);
2348 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
2349 jme_set_link_ksettings(netdev
, &jme
->old_cmd
);
2352 * Force to Reset the link again
2354 jme_reset_link(jme
);
2358 jme_get_drvinfo(struct net_device
*netdev
,
2359 struct ethtool_drvinfo
*info
)
2361 struct jme_adapter
*jme
= netdev_priv(netdev
);
2363 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
2364 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
2365 strlcpy(info
->bus_info
, pci_name(jme
->pdev
), sizeof(info
->bus_info
));
2369 jme_get_regs_len(struct net_device
*netdev
)
2375 mmapio_memcpy(struct jme_adapter
*jme
, u32
*p
, u32 reg
, int len
)
2379 for (i
= 0 ; i
< len
; i
+= 4)
2380 p
[i
>> 2] = jread32(jme
, reg
+ i
);
2384 mdio_memcpy(struct jme_adapter
*jme
, u32
*p
, int reg_nr
)
2387 u16
*p16
= (u16
*)p
;
2389 for (i
= 0 ; i
< reg_nr
; ++i
)
2390 p16
[i
] = jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, i
);
2394 jme_get_regs(struct net_device
*netdev
, struct ethtool_regs
*regs
, void *p
)
2396 struct jme_adapter
*jme
= netdev_priv(netdev
);
2397 u32
*p32
= (u32
*)p
;
2399 memset(p
, 0xFF, JME_REG_LEN
);
2402 mmapio_memcpy(jme
, p32
, JME_MAC
, JME_MAC_LEN
);
2405 mmapio_memcpy(jme
, p32
, JME_PHY
, JME_PHY_LEN
);
2408 mmapio_memcpy(jme
, p32
, JME_MISC
, JME_MISC_LEN
);
2411 mmapio_memcpy(jme
, p32
, JME_RSS
, JME_RSS_LEN
);
2414 mdio_memcpy(jme
, p32
, JME_PHY_REG_NR
);
2418 jme_get_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2420 struct jme_adapter
*jme
= netdev_priv(netdev
);
2422 ecmd
->tx_coalesce_usecs
= PCC_TX_TO
;
2423 ecmd
->tx_max_coalesced_frames
= PCC_TX_CNT
;
2425 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2426 ecmd
->use_adaptive_rx_coalesce
= false;
2427 ecmd
->rx_coalesce_usecs
= 0;
2428 ecmd
->rx_max_coalesced_frames
= 0;
2432 ecmd
->use_adaptive_rx_coalesce
= true;
2434 switch (jme
->dpi
.cur
) {
2436 ecmd
->rx_coalesce_usecs
= PCC_P1_TO
;
2437 ecmd
->rx_max_coalesced_frames
= PCC_P1_CNT
;
2440 ecmd
->rx_coalesce_usecs
= PCC_P2_TO
;
2441 ecmd
->rx_max_coalesced_frames
= PCC_P2_CNT
;
2444 ecmd
->rx_coalesce_usecs
= PCC_P3_TO
;
2445 ecmd
->rx_max_coalesced_frames
= PCC_P3_CNT
;
2455 jme_set_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2457 struct jme_adapter
*jme
= netdev_priv(netdev
);
2458 struct dynpcc_info
*dpi
= &(jme
->dpi
);
2460 if (netif_running(netdev
))
2463 if (ecmd
->use_adaptive_rx_coalesce
&&
2464 test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2465 clear_bit(JME_FLAG_POLL
, &jme
->flags
);
2466 jme
->jme_rx
= netif_rx
;
2468 dpi
->attempt
= PCC_P1
;
2470 jme_set_rx_pcc(jme
, PCC_P1
);
2471 jme_interrupt_mode(jme
);
2472 } else if (!(ecmd
->use_adaptive_rx_coalesce
) &&
2473 !(test_bit(JME_FLAG_POLL
, &jme
->flags
))) {
2474 set_bit(JME_FLAG_POLL
, &jme
->flags
);
2475 jme
->jme_rx
= netif_receive_skb
;
2476 jme_interrupt_mode(jme
);
2483 jme_get_pauseparam(struct net_device
*netdev
,
2484 struct ethtool_pauseparam
*ecmd
)
2486 struct jme_adapter
*jme
= netdev_priv(netdev
);
2489 ecmd
->tx_pause
= (jme
->reg_txpfc
& TXPFC_PF_EN
) != 0;
2490 ecmd
->rx_pause
= (jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0;
2492 spin_lock_bh(&jme
->phy_lock
);
2493 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2494 spin_unlock_bh(&jme
->phy_lock
);
2497 (val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0;
2501 jme_set_pauseparam(struct net_device
*netdev
,
2502 struct ethtool_pauseparam
*ecmd
)
2504 struct jme_adapter
*jme
= netdev_priv(netdev
);
2507 if (((jme
->reg_txpfc
& TXPFC_PF_EN
) != 0) ^
2508 (ecmd
->tx_pause
!= 0)) {
2511 jme
->reg_txpfc
|= TXPFC_PF_EN
;
2513 jme
->reg_txpfc
&= ~TXPFC_PF_EN
;
2515 jwrite32(jme
, JME_TXPFC
, jme
->reg_txpfc
);
2518 spin_lock_bh(&jme
->rxmcs_lock
);
2519 if (((jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0) ^
2520 (ecmd
->rx_pause
!= 0)) {
2523 jme
->reg_rxmcs
|= RXMCS_FLOWCTRL
;
2525 jme
->reg_rxmcs
&= ~RXMCS_FLOWCTRL
;
2527 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2529 spin_unlock_bh(&jme
->rxmcs_lock
);
2531 spin_lock_bh(&jme
->phy_lock
);
2532 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2533 if (((val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0) ^
2534 (ecmd
->autoneg
!= 0)) {
2537 val
|= (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2539 val
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2541 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
,
2542 MII_ADVERTISE
, val
);
2544 spin_unlock_bh(&jme
->phy_lock
);
2550 jme_get_wol(struct net_device
*netdev
,
2551 struct ethtool_wolinfo
*wol
)
2553 struct jme_adapter
*jme
= netdev_priv(netdev
);
2555 wol
->supported
= WAKE_MAGIC
| WAKE_PHY
;
2559 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
2560 wol
->wolopts
|= WAKE_PHY
;
2562 if (jme
->reg_pmcs
& PMCS_MFEN
)
2563 wol
->wolopts
|= WAKE_MAGIC
;
2568 jme_set_wol(struct net_device
*netdev
,
2569 struct ethtool_wolinfo
*wol
)
2571 struct jme_adapter
*jme
= netdev_priv(netdev
);
2573 if (wol
->wolopts
& (WAKE_MAGICSECURE
|
2582 if (wol
->wolopts
& WAKE_PHY
)
2583 jme
->reg_pmcs
|= PMCS_LFEN
| PMCS_LREN
;
2585 if (wol
->wolopts
& WAKE_MAGIC
)
2586 jme
->reg_pmcs
|= PMCS_MFEN
;
2592 jme_get_link_ksettings(struct net_device
*netdev
,
2593 struct ethtool_link_ksettings
*cmd
)
2595 struct jme_adapter
*jme
= netdev_priv(netdev
);
2597 spin_lock_bh(&jme
->phy_lock
);
2598 mii_ethtool_get_link_ksettings(&jme
->mii_if
, cmd
);
2599 spin_unlock_bh(&jme
->phy_lock
);
2604 jme_set_link_ksettings(struct net_device
*netdev
,
2605 const struct ethtool_link_ksettings
*cmd
)
2607 struct jme_adapter
*jme
= netdev_priv(netdev
);
2610 if (cmd
->base
.speed
== SPEED_1000
&&
2611 cmd
->base
.autoneg
!= AUTONEG_ENABLE
)
2615 * Check If user changed duplex only while force_media.
2616 * Hardware would not generate link change interrupt.
2618 if (jme
->mii_if
.force_media
&&
2619 cmd
->base
.autoneg
!= AUTONEG_ENABLE
&&
2620 (jme
->mii_if
.full_duplex
!= cmd
->base
.duplex
))
2623 spin_lock_bh(&jme
->phy_lock
);
2624 rc
= mii_ethtool_set_link_ksettings(&jme
->mii_if
, cmd
);
2625 spin_unlock_bh(&jme
->phy_lock
);
2629 jme_reset_link(jme
);
2630 jme
->old_cmd
= *cmd
;
2631 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2638 jme_ioctl(struct net_device
*netdev
, struct ifreq
*rq
, int cmd
)
2641 struct jme_adapter
*jme
= netdev_priv(netdev
);
2642 struct mii_ioctl_data
*mii_data
= if_mii(rq
);
2643 unsigned int duplex_chg
;
2645 if (cmd
== SIOCSMIIREG
) {
2646 u16 val
= mii_data
->val_in
;
2647 if (!(val
& (BMCR_RESET
|BMCR_ANENABLE
)) &&
2648 (val
& BMCR_SPEED1000
))
2652 spin_lock_bh(&jme
->phy_lock
);
2653 rc
= generic_mii_ioctl(&jme
->mii_if
, mii_data
, cmd
, &duplex_chg
);
2654 spin_unlock_bh(&jme
->phy_lock
);
2656 if (!rc
&& (cmd
== SIOCSMIIREG
)) {
2658 jme_reset_link(jme
);
2659 jme_get_link_ksettings(netdev
, &jme
->old_cmd
);
2660 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2667 jme_get_link(struct net_device
*netdev
)
2669 struct jme_adapter
*jme
= netdev_priv(netdev
);
2670 return jread32(jme
, JME_PHY_LINK
) & PHY_LINK_UP
;
2674 jme_get_msglevel(struct net_device
*netdev
)
2676 struct jme_adapter
*jme
= netdev_priv(netdev
);
2677 return jme
->msg_enable
;
2681 jme_set_msglevel(struct net_device
*netdev
, u32 value
)
2683 struct jme_adapter
*jme
= netdev_priv(netdev
);
2684 jme
->msg_enable
= value
;
2687 static netdev_features_t
2688 jme_fix_features(struct net_device
*netdev
, netdev_features_t features
)
2690 if (netdev
->mtu
> 1900)
2691 features
&= ~(NETIF_F_ALL_TSO
| NETIF_F_CSUM_MASK
);
2696 jme_set_features(struct net_device
*netdev
, netdev_features_t features
)
2698 struct jme_adapter
*jme
= netdev_priv(netdev
);
2700 spin_lock_bh(&jme
->rxmcs_lock
);
2701 if (features
& NETIF_F_RXCSUM
)
2702 jme
->reg_rxmcs
|= RXMCS_CHECKSUM
;
2704 jme
->reg_rxmcs
&= ~RXMCS_CHECKSUM
;
2705 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2706 spin_unlock_bh(&jme
->rxmcs_lock
);
2711 #ifdef CONFIG_NET_POLL_CONTROLLER
2712 static void jme_netpoll(struct net_device
*dev
)
2714 unsigned long flags
;
2716 local_irq_save(flags
);
2717 jme_intr(dev
->irq
, dev
);
2718 local_irq_restore(flags
);
2723 jme_nway_reset(struct net_device
*netdev
)
2725 struct jme_adapter
*jme
= netdev_priv(netdev
);
2726 jme_restart_an(jme
);
2731 jme_smb_read(struct jme_adapter
*jme
, unsigned int addr
)
2736 val
= jread32(jme
, JME_SMBCSR
);
2737 to
= JME_SMB_BUSY_TIMEOUT
;
2738 while ((val
& SMBCSR_BUSY
) && --to
) {
2740 val
= jread32(jme
, JME_SMBCSR
);
2743 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2747 jwrite32(jme
, JME_SMBINTF
,
2748 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2749 SMBINTF_HWRWN_READ
|
2752 val
= jread32(jme
, JME_SMBINTF
);
2753 to
= JME_SMB_BUSY_TIMEOUT
;
2754 while ((val
& SMBINTF_HWCMD
) && --to
) {
2756 val
= jread32(jme
, JME_SMBINTF
);
2759 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2763 return (val
& SMBINTF_HWDATR
) >> SMBINTF_HWDATR_SHIFT
;
2767 jme_smb_write(struct jme_adapter
*jme
, unsigned int addr
, u8 data
)
2772 val
= jread32(jme
, JME_SMBCSR
);
2773 to
= JME_SMB_BUSY_TIMEOUT
;
2774 while ((val
& SMBCSR_BUSY
) && --to
) {
2776 val
= jread32(jme
, JME_SMBCSR
);
2779 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2783 jwrite32(jme
, JME_SMBINTF
,
2784 ((data
<< SMBINTF_HWDATW_SHIFT
) & SMBINTF_HWDATW
) |
2785 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2786 SMBINTF_HWRWN_WRITE
|
2789 val
= jread32(jme
, JME_SMBINTF
);
2790 to
= JME_SMB_BUSY_TIMEOUT
;
2791 while ((val
& SMBINTF_HWCMD
) && --to
) {
2793 val
= jread32(jme
, JME_SMBINTF
);
2796 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2804 jme_get_eeprom_len(struct net_device
*netdev
)
2806 struct jme_adapter
*jme
= netdev_priv(netdev
);
2808 val
= jread32(jme
, JME_SMBCSR
);
2809 return (val
& SMBCSR_EEPROMD
) ? JME_SMB_LEN
: 0;
2813 jme_get_eeprom(struct net_device
*netdev
,
2814 struct ethtool_eeprom
*eeprom
, u8
*data
)
2816 struct jme_adapter
*jme
= netdev_priv(netdev
);
2817 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2820 * ethtool will check the boundary for us
2822 eeprom
->magic
= JME_EEPROM_MAGIC
;
2823 for (i
= 0 ; i
< len
; ++i
)
2824 data
[i
] = jme_smb_read(jme
, i
+ offset
);
2830 jme_set_eeprom(struct net_device
*netdev
,
2831 struct ethtool_eeprom
*eeprom
, u8
*data
)
2833 struct jme_adapter
*jme
= netdev_priv(netdev
);
2834 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2836 if (eeprom
->magic
!= JME_EEPROM_MAGIC
)
2840 * ethtool will check the boundary for us
2842 for (i
= 0 ; i
< len
; ++i
)
2843 jme_smb_write(jme
, i
+ offset
, data
[i
]);
2848 static const struct ethtool_ops jme_ethtool_ops
= {
2849 .get_drvinfo
= jme_get_drvinfo
,
2850 .get_regs_len
= jme_get_regs_len
,
2851 .get_regs
= jme_get_regs
,
2852 .get_coalesce
= jme_get_coalesce
,
2853 .set_coalesce
= jme_set_coalesce
,
2854 .get_pauseparam
= jme_get_pauseparam
,
2855 .set_pauseparam
= jme_set_pauseparam
,
2856 .get_wol
= jme_get_wol
,
2857 .set_wol
= jme_set_wol
,
2858 .get_link
= jme_get_link
,
2859 .get_msglevel
= jme_get_msglevel
,
2860 .set_msglevel
= jme_set_msglevel
,
2861 .nway_reset
= jme_nway_reset
,
2862 .get_eeprom_len
= jme_get_eeprom_len
,
2863 .get_eeprom
= jme_get_eeprom
,
2864 .set_eeprom
= jme_set_eeprom
,
2865 .get_link_ksettings
= jme_get_link_ksettings
,
2866 .set_link_ksettings
= jme_set_link_ksettings
,
2870 jme_pci_dma64(struct pci_dev
*pdev
)
2872 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2873 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))
2874 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)))
2877 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2878 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
2879 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40)))
2882 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)))
2883 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))
2890 jme_phy_init(struct jme_adapter
*jme
)
2894 reg26
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 26);
2895 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 26, reg26
| 0x1000);
2899 jme_check_hw_ver(struct jme_adapter
*jme
)
2903 chipmode
= jread32(jme
, JME_CHIPMODE
);
2905 jme
->fpgaver
= (chipmode
& CM_FPGAVER_MASK
) >> CM_FPGAVER_SHIFT
;
2906 jme
->chiprev
= (chipmode
& CM_CHIPREV_MASK
) >> CM_CHIPREV_SHIFT
;
2907 jme
->chip_main_rev
= jme
->chiprev
& 0xF;
2908 jme
->chip_sub_rev
= (jme
->chiprev
>> 4) & 0xF;
2911 static const struct net_device_ops jme_netdev_ops
= {
2912 .ndo_open
= jme_open
,
2913 .ndo_stop
= jme_close
,
2914 .ndo_validate_addr
= eth_validate_addr
,
2915 .ndo_do_ioctl
= jme_ioctl
,
2916 .ndo_start_xmit
= jme_start_xmit
,
2917 .ndo_set_mac_address
= jme_set_macaddr
,
2918 .ndo_set_rx_mode
= jme_set_multi
,
2919 .ndo_change_mtu
= jme_change_mtu
,
2920 .ndo_tx_timeout
= jme_tx_timeout
,
2921 .ndo_fix_features
= jme_fix_features
,
2922 .ndo_set_features
= jme_set_features
,
2923 #ifdef CONFIG_NET_POLL_CONTROLLER
2924 .ndo_poll_controller
= jme_netpoll
,
2929 jme_init_one(struct pci_dev
*pdev
,
2930 const struct pci_device_id
*ent
)
2932 int rc
= 0, using_dac
, i
;
2933 struct net_device
*netdev
;
2934 struct jme_adapter
*jme
;
2939 * set up PCI device basics
2941 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
2942 PCIE_LINK_STATE_CLKPM
);
2944 rc
= pci_enable_device(pdev
);
2946 pr_err("Cannot enable PCI device\n");
2950 using_dac
= jme_pci_dma64(pdev
);
2951 if (using_dac
< 0) {
2952 pr_err("Cannot set PCI DMA Mask\n");
2954 goto err_out_disable_pdev
;
2957 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2958 pr_err("No PCI resource region found\n");
2960 goto err_out_disable_pdev
;
2963 rc
= pci_request_regions(pdev
, DRV_NAME
);
2965 pr_err("Cannot obtain PCI resource region\n");
2966 goto err_out_disable_pdev
;
2969 pci_set_master(pdev
);
2972 * alloc and init net device
2974 netdev
= alloc_etherdev(sizeof(*jme
));
2977 goto err_out_release_regions
;
2979 netdev
->netdev_ops
= &jme_netdev_ops
;
2980 netdev
->ethtool_ops
= &jme_ethtool_ops
;
2981 netdev
->watchdog_timeo
= TX_TIMEOUT
;
2982 netdev
->hw_features
= NETIF_F_IP_CSUM
|
2988 netdev
->features
= NETIF_F_IP_CSUM
|
2993 NETIF_F_HW_VLAN_CTAG_TX
|
2994 NETIF_F_HW_VLAN_CTAG_RX
;
2996 netdev
->features
|= NETIF_F_HIGHDMA
;
2998 /* MTU range: 1280 - 9202*/
2999 netdev
->min_mtu
= IPV6_MIN_MTU
;
3000 netdev
->max_mtu
= MAX_ETHERNET_JUMBO_PACKET_SIZE
- ETH_HLEN
;
3002 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3003 pci_set_drvdata(pdev
, netdev
);
3008 jme
= netdev_priv(netdev
);
3011 jme
->jme_rx
= netif_rx
;
3012 jme
->old_mtu
= netdev
->mtu
= 1500;
3014 jme
->tx_ring_size
= 1 << 10;
3015 jme
->tx_ring_mask
= jme
->tx_ring_size
- 1;
3016 jme
->tx_wake_threshold
= 1 << 9;
3017 jme
->rx_ring_size
= 1 << 9;
3018 jme
->rx_ring_mask
= jme
->rx_ring_size
- 1;
3019 jme
->msg_enable
= JME_DEF_MSG_ENABLE
;
3020 jme
->regs
= ioremap(pci_resource_start(pdev
, 0),
3021 pci_resource_len(pdev
, 0));
3023 pr_err("Mapping PCI resource region error\n");
3025 goto err_out_free_netdev
;
3029 apmc
= jread32(jme
, JME_APMC
) & ~JME_APMC_PSEUDO_HP_EN
;
3030 jwrite32(jme
, JME_APMC
, apmc
);
3031 } else if (force_pseudohp
) {
3032 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PSEUDO_HP_EN
;
3033 jwrite32(jme
, JME_APMC
, apmc
);
3036 NETIF_NAPI_SET(netdev
, &jme
->napi
, jme_poll
, NAPI_POLL_WEIGHT
)
3038 spin_lock_init(&jme
->phy_lock
);
3039 spin_lock_init(&jme
->macaddr_lock
);
3040 spin_lock_init(&jme
->rxmcs_lock
);
3042 atomic_set(&jme
->link_changing
, 1);
3043 atomic_set(&jme
->rx_cleaning
, 1);
3044 atomic_set(&jme
->tx_cleaning
, 1);
3045 atomic_set(&jme
->rx_empty
, 1);
3047 tasklet_init(&jme
->pcc_task
,
3049 (unsigned long) jme
);
3050 jme
->dpi
.cur
= PCC_P1
;
3053 jme
->reg_rxcs
= RXCS_DEFAULT
;
3054 jme
->reg_rxmcs
= RXMCS_DEFAULT
;
3056 jme
->reg_pmcs
= PMCS_MFEN
;
3057 jme
->reg_gpreg1
= GPREG1_DEFAULT
;
3059 if (jme
->reg_rxmcs
& RXMCS_CHECKSUM
)
3060 netdev
->features
|= NETIF_F_RXCSUM
;
3063 * Get Max Read Req Size from PCI Config Space
3065 pci_read_config_byte(pdev
, PCI_DCSR_MRRS
, &jme
->mrrs
);
3066 jme
->mrrs
&= PCI_DCSR_MRRS_MASK
;
3067 switch (jme
->mrrs
) {
3069 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_128B
;
3072 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_256B
;
3075 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_512B
;
3080 * Must check before reset_mac_processor
3082 jme_check_hw_ver(jme
);
3083 jme
->mii_if
.dev
= netdev
;
3085 jme
->mii_if
.phy_id
= 0;
3086 for (i
= 1 ; i
< 32 ; ++i
) {
3087 bmcr
= jme_mdio_read(netdev
, i
, MII_BMCR
);
3088 bmsr
= jme_mdio_read(netdev
, i
, MII_BMSR
);
3089 if (bmcr
!= 0xFFFFU
&& (bmcr
!= 0 || bmsr
!= 0)) {
3090 jme
->mii_if
.phy_id
= i
;
3095 if (!jme
->mii_if
.phy_id
) {
3097 pr_err("Can not find phy_id\n");
3101 jme
->reg_ghc
|= GHC_LINK_POLL
;
3103 jme
->mii_if
.phy_id
= 1;
3105 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
3106 jme
->mii_if
.supports_gmii
= true;
3108 jme
->mii_if
.supports_gmii
= false;
3109 jme
->mii_if
.phy_id_mask
= 0x1F;
3110 jme
->mii_if
.reg_num_mask
= 0x1F;
3111 jme
->mii_if
.mdio_read
= jme_mdio_read
;
3112 jme
->mii_if
.mdio_write
= jme_mdio_write
;
3114 jme_clear_pm_disable_wol(jme
);
3115 device_init_wakeup(&pdev
->dev
, true);
3117 jme_set_phyfifo_5level(jme
);
3118 jme
->pcirev
= pdev
->revision
;
3124 * Reset MAC processor and reload EEPROM for MAC Address
3126 jme_reset_mac_processor(jme
);
3127 rc
= jme_reload_eeprom(jme
);
3129 pr_err("Reload eeprom for reading MAC Address error\n");
3132 jme_load_macaddr(netdev
);
3135 * Tell stack that we are not ready to work until open()
3137 netif_carrier_off(netdev
);
3139 rc
= register_netdev(netdev
);
3141 pr_err("Cannot register net device\n");
3145 netif_info(jme
, probe
, jme
->dev
, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3146 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
) ?
3147 "JMC250 Gigabit Ethernet" :
3148 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC260
) ?
3149 "JMC260 Fast Ethernet" : "Unknown",
3150 (jme
->fpgaver
!= 0) ? " (FPGA)" : "",
3151 (jme
->fpgaver
!= 0) ? jme
->fpgaver
: jme
->chiprev
,
3152 jme
->pcirev
, netdev
->dev_addr
);
3158 err_out_free_netdev
:
3159 free_netdev(netdev
);
3160 err_out_release_regions
:
3161 pci_release_regions(pdev
);
3162 err_out_disable_pdev
:
3163 pci_disable_device(pdev
);
3169 jme_remove_one(struct pci_dev
*pdev
)
3171 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3172 struct jme_adapter
*jme
= netdev_priv(netdev
);
3174 unregister_netdev(netdev
);
3176 free_netdev(netdev
);
3177 pci_release_regions(pdev
);
3178 pci_disable_device(pdev
);
3183 jme_shutdown(struct pci_dev
*pdev
)
3185 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3186 struct jme_adapter
*jme
= netdev_priv(netdev
);
3188 jme_powersave_phy(jme
);
3189 pci_pme_active(pdev
, true);
3192 #ifdef CONFIG_PM_SLEEP
3194 jme_suspend(struct device
*dev
)
3196 struct pci_dev
*pdev
= to_pci_dev(dev
);
3197 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3198 struct jme_adapter
*jme
= netdev_priv(netdev
);
3200 if (!netif_running(netdev
))
3203 atomic_dec(&jme
->link_changing
);
3205 netif_device_detach(netdev
);
3206 netif_stop_queue(netdev
);
3209 tasklet_disable(&jme
->txclean_task
);
3210 tasklet_disable(&jme
->rxclean_task
);
3211 tasklet_disable(&jme
->rxempty_task
);
3213 if (netif_carrier_ok(netdev
)) {
3214 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
3215 jme_polling_mode(jme
);
3217 jme_stop_pcc_timer(jme
);
3218 jme_disable_rx_engine(jme
);
3219 jme_disable_tx_engine(jme
);
3220 jme_reset_mac_processor(jme
);
3221 jme_free_rx_resources(jme
);
3222 jme_free_tx_resources(jme
);
3223 netif_carrier_off(netdev
);
3227 tasklet_enable(&jme
->txclean_task
);
3228 tasklet_enable(&jme
->rxclean_task
);
3229 tasklet_enable(&jme
->rxempty_task
);
3231 jme_powersave_phy(jme
);
3237 jme_resume(struct device
*dev
)
3239 struct pci_dev
*pdev
= to_pci_dev(dev
);
3240 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3241 struct jme_adapter
*jme
= netdev_priv(netdev
);
3243 if (!netif_running(netdev
))
3246 jme_clear_pm_disable_wol(jme
);
3248 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
3249 jme_set_link_ksettings(netdev
, &jme
->old_cmd
);
3251 jme_reset_phy_processor(jme
);
3252 jme_phy_calibration(jme
);
3254 netif_device_attach(netdev
);
3256 atomic_inc(&jme
->link_changing
);
3258 jme_reset_link(jme
);
3265 static SIMPLE_DEV_PM_OPS(jme_pm_ops
, jme_suspend
, jme_resume
);
3266 #define JME_PM_OPS (&jme_pm_ops)
3270 #define JME_PM_OPS NULL
3273 static const struct pci_device_id jme_pci_tbl
[] = {
3274 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC250
) },
3275 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC260
) },
3279 static struct pci_driver jme_driver
= {
3281 .id_table
= jme_pci_tbl
,
3282 .probe
= jme_init_one
,
3283 .remove
= jme_remove_one
,
3284 .shutdown
= jme_shutdown
,
3285 .driver
.pm
= JME_PM_OPS
,
3289 jme_init_module(void)
3291 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION
);
3292 return pci_register_driver(&jme_driver
);
3296 jme_cleanup_module(void)
3298 pci_unregister_driver(&jme_driver
);
3301 module_init(jme_init_module
);
3302 module_exit(jme_cleanup_module
);
3304 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3305 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3306 MODULE_LICENSE("GPL");
3307 MODULE_VERSION(DRV_VERSION
);
3308 MODULE_DEVICE_TABLE(pci
, jme_pci_tbl
);