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UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / jme.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 *
5 * Copyright 2008 JMicron Technology Corporation
6 * http://www.jmicron.com/
7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/pci-aspm.h>
18 #include <linux/netdevice.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/crc32.h>
23 #include <linux/delay.h>
24 #include <linux/spinlock.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <linux/tcp.h>
29 #include <linux/udp.h>
30 #include <linux/if_vlan.h>
31 #include <linux/slab.h>
32 #include <net/ip6_checksum.h>
33 #include "jme.h"
34
35 static int force_pseudohp = -1;
36 static int no_pseudohp = -1;
37 static int no_extplug = -1;
38 module_param(force_pseudohp, int, 0);
39 MODULE_PARM_DESC(force_pseudohp,
40 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
41 module_param(no_pseudohp, int, 0);
42 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
43 module_param(no_extplug, int, 0);
44 MODULE_PARM_DESC(no_extplug,
45 "Do not use external plug signal for pseudo hot-plug.");
46
47 static int
48 jme_mdio_read(struct net_device *netdev, int phy, int reg)
49 {
50 struct jme_adapter *jme = netdev_priv(netdev);
51 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
52
53 read_again:
54 jwrite32(jme, JME_SMI, SMI_OP_REQ |
55 smi_phy_addr(phy) |
56 smi_reg_addr(reg));
57
58 wmb();
59 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
60 udelay(20);
61 val = jread32(jme, JME_SMI);
62 if ((val & SMI_OP_REQ) == 0)
63 break;
64 }
65
66 if (i == 0) {
67 pr_err("phy(%d) read timeout : %d\n", phy, reg);
68 return 0;
69 }
70
71 if (again--)
72 goto read_again;
73
74 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
75 }
76
77 static void
78 jme_mdio_write(struct net_device *netdev,
79 int phy, int reg, int val)
80 {
81 struct jme_adapter *jme = netdev_priv(netdev);
82 int i;
83
84 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
85 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
86 smi_phy_addr(phy) | smi_reg_addr(reg));
87
88 wmb();
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
90 udelay(20);
91 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
92 break;
93 }
94
95 if (i == 0)
96 pr_err("phy(%d) write timeout : %d\n", phy, reg);
97 }
98
99 static inline void
100 jme_reset_phy_processor(struct jme_adapter *jme)
101 {
102 u32 val;
103
104 jme_mdio_write(jme->dev,
105 jme->mii_if.phy_id,
106 MII_ADVERTISE, ADVERTISE_ALL |
107 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
108
109 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
110 jme_mdio_write(jme->dev,
111 jme->mii_if.phy_id,
112 MII_CTRL1000,
113 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
114
115 val = jme_mdio_read(jme->dev,
116 jme->mii_if.phy_id,
117 MII_BMCR);
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_BMCR, val | BMCR_RESET);
122 }
123
124 static void
125 jme_setup_wakeup_frame(struct jme_adapter *jme,
126 const u32 *mask, u32 crc, int fnr)
127 {
128 int i;
129
130 /*
131 * Setup CRC pattern
132 */
133 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
134 wmb();
135 jwrite32(jme, JME_WFODP, crc);
136 wmb();
137
138 /*
139 * Setup Mask
140 */
141 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
142 jwrite32(jme, JME_WFOI,
143 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
144 (fnr & WFOI_FRAME_SEL));
145 wmb();
146 jwrite32(jme, JME_WFODP, mask[i]);
147 wmb();
148 }
149 }
150
151 static inline void
152 jme_mac_rxclk_off(struct jme_adapter *jme)
153 {
154 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
155 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
156 }
157
158 static inline void
159 jme_mac_rxclk_on(struct jme_adapter *jme)
160 {
161 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
162 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
163 }
164
165 static inline void
166 jme_mac_txclk_off(struct jme_adapter *jme)
167 {
168 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
169 jwrite32f(jme, JME_GHC, jme->reg_ghc);
170 }
171
172 static inline void
173 jme_mac_txclk_on(struct jme_adapter *jme)
174 {
175 u32 speed = jme->reg_ghc & GHC_SPEED;
176 if (speed == GHC_SPEED_1000M)
177 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
178 else
179 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
180 jwrite32f(jme, JME_GHC, jme->reg_ghc);
181 }
182
183 static inline void
184 jme_reset_ghc_speed(struct jme_adapter *jme)
185 {
186 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
187 jwrite32f(jme, JME_GHC, jme->reg_ghc);
188 }
189
190 static inline void
191 jme_reset_250A2_workaround(struct jme_adapter *jme)
192 {
193 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
194 GPREG1_RSSPATCH);
195 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
196 }
197
198 static inline void
199 jme_assert_ghc_reset(struct jme_adapter *jme)
200 {
201 jme->reg_ghc |= GHC_SWRST;
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203 }
204
205 static inline void
206 jme_clear_ghc_reset(struct jme_adapter *jme)
207 {
208 jme->reg_ghc &= ~GHC_SWRST;
209 jwrite32f(jme, JME_GHC, jme->reg_ghc);
210 }
211
212 static void
213 jme_reset_mac_processor(struct jme_adapter *jme)
214 {
215 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
216 u32 crc = 0xCDCDCDCD;
217 u32 gpreg0;
218 int i;
219
220 jme_reset_ghc_speed(jme);
221 jme_reset_250A2_workaround(jme);
222
223 jme_mac_rxclk_on(jme);
224 jme_mac_txclk_on(jme);
225 udelay(1);
226 jme_assert_ghc_reset(jme);
227 udelay(1);
228 jme_mac_rxclk_off(jme);
229 jme_mac_txclk_off(jme);
230 udelay(1);
231 jme_clear_ghc_reset(jme);
232 udelay(1);
233 jme_mac_rxclk_on(jme);
234 jme_mac_txclk_on(jme);
235 udelay(1);
236 jme_mac_rxclk_off(jme);
237 jme_mac_txclk_off(jme);
238
239 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
240 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
241 jwrite32(jme, JME_RXQDC, 0x00000000);
242 jwrite32(jme, JME_RXNDA, 0x00000000);
243 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
244 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
245 jwrite32(jme, JME_TXQDC, 0x00000000);
246 jwrite32(jme, JME_TXNDA, 0x00000000);
247
248 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
249 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
250 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
251 jme_setup_wakeup_frame(jme, mask, crc, i);
252 if (jme->fpgaver)
253 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
254 else
255 gpreg0 = GPREG0_DEFAULT;
256 jwrite32(jme, JME_GPREG0, gpreg0);
257 }
258
259 static inline void
260 jme_clear_pm_enable_wol(struct jme_adapter *jme)
261 {
262 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
263 }
264
265 static inline void
266 jme_clear_pm_disable_wol(struct jme_adapter *jme)
267 {
268 jwrite32(jme, JME_PMCS, PMCS_STMASK);
269 }
270
271 static int
272 jme_reload_eeprom(struct jme_adapter *jme)
273 {
274 u32 val;
275 int i;
276
277 val = jread32(jme, JME_SMBCSR);
278
279 if (val & SMBCSR_EEPROMD) {
280 val |= SMBCSR_CNACK;
281 jwrite32(jme, JME_SMBCSR, val);
282 val |= SMBCSR_RELOAD;
283 jwrite32(jme, JME_SMBCSR, val);
284 mdelay(12);
285
286 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
287 mdelay(1);
288 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
289 break;
290 }
291
292 if (i == 0) {
293 pr_err("eeprom reload timeout\n");
294 return -EIO;
295 }
296 }
297
298 return 0;
299 }
300
301 static void
302 jme_load_macaddr(struct net_device *netdev)
303 {
304 struct jme_adapter *jme = netdev_priv(netdev);
305 unsigned char macaddr[ETH_ALEN];
306 u32 val;
307
308 spin_lock_bh(&jme->macaddr_lock);
309 val = jread32(jme, JME_RXUMA_LO);
310 macaddr[0] = (val >> 0) & 0xFF;
311 macaddr[1] = (val >> 8) & 0xFF;
312 macaddr[2] = (val >> 16) & 0xFF;
313 macaddr[3] = (val >> 24) & 0xFF;
314 val = jread32(jme, JME_RXUMA_HI);
315 macaddr[4] = (val >> 0) & 0xFF;
316 macaddr[5] = (val >> 8) & 0xFF;
317 memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
318 spin_unlock_bh(&jme->macaddr_lock);
319 }
320
321 static inline void
322 jme_set_rx_pcc(struct jme_adapter *jme, int p)
323 {
324 switch (p) {
325 case PCC_OFF:
326 jwrite32(jme, JME_PCCRX0,
327 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
328 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
329 break;
330 case PCC_P1:
331 jwrite32(jme, JME_PCCRX0,
332 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
333 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
334 break;
335 case PCC_P2:
336 jwrite32(jme, JME_PCCRX0,
337 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
338 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
339 break;
340 case PCC_P3:
341 jwrite32(jme, JME_PCCRX0,
342 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
343 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
344 break;
345 default:
346 break;
347 }
348 wmb();
349
350 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
351 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
352 }
353
354 static void
355 jme_start_irq(struct jme_adapter *jme)
356 {
357 register struct dynpcc_info *dpi = &(jme->dpi);
358
359 jme_set_rx_pcc(jme, PCC_P1);
360 dpi->cur = PCC_P1;
361 dpi->attempt = PCC_P1;
362 dpi->cnt = 0;
363
364 jwrite32(jme, JME_PCCTX,
365 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
366 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
367 PCCTXQ0_EN
368 );
369
370 /*
371 * Enable Interrupts
372 */
373 jwrite32(jme, JME_IENS, INTR_ENABLE);
374 }
375
376 static inline void
377 jme_stop_irq(struct jme_adapter *jme)
378 {
379 /*
380 * Disable Interrupts
381 */
382 jwrite32f(jme, JME_IENC, INTR_ENABLE);
383 }
384
385 static u32
386 jme_linkstat_from_phy(struct jme_adapter *jme)
387 {
388 u32 phylink, bmsr;
389
390 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
391 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
392 if (bmsr & BMSR_ANCOMP)
393 phylink |= PHY_LINK_AUTONEG_COMPLETE;
394
395 return phylink;
396 }
397
398 static inline void
399 jme_set_phyfifo_5level(struct jme_adapter *jme)
400 {
401 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
402 }
403
404 static inline void
405 jme_set_phyfifo_8level(struct jme_adapter *jme)
406 {
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
408 }
409
410 static int
411 jme_check_link(struct net_device *netdev, int testonly)
412 {
413 struct jme_adapter *jme = netdev_priv(netdev);
414 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
415 char linkmsg[64];
416 int rc = 0;
417
418 linkmsg[0] = '\0';
419
420 if (jme->fpgaver)
421 phylink = jme_linkstat_from_phy(jme);
422 else
423 phylink = jread32(jme, JME_PHY_LINK);
424
425 if (phylink & PHY_LINK_UP) {
426 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
427 /*
428 * If we did not enable AN
429 * Speed/Duplex Info should be obtained from SMI
430 */
431 phylink = PHY_LINK_UP;
432
433 bmcr = jme_mdio_read(jme->dev,
434 jme->mii_if.phy_id,
435 MII_BMCR);
436
437 phylink |= ((bmcr & BMCR_SPEED1000) &&
438 (bmcr & BMCR_SPEED100) == 0) ?
439 PHY_LINK_SPEED_1000M :
440 (bmcr & BMCR_SPEED100) ?
441 PHY_LINK_SPEED_100M :
442 PHY_LINK_SPEED_10M;
443
444 phylink |= (bmcr & BMCR_FULLDPLX) ?
445 PHY_LINK_DUPLEX : 0;
446
447 strcat(linkmsg, "Forced: ");
448 } else {
449 /*
450 * Keep polling for speed/duplex resolve complete
451 */
452 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
453 --cnt) {
454
455 udelay(1);
456
457 if (jme->fpgaver)
458 phylink = jme_linkstat_from_phy(jme);
459 else
460 phylink = jread32(jme, JME_PHY_LINK);
461 }
462 if (!cnt)
463 pr_err("Waiting speed resolve timeout\n");
464
465 strcat(linkmsg, "ANed: ");
466 }
467
468 if (jme->phylink == phylink) {
469 rc = 1;
470 goto out;
471 }
472 if (testonly)
473 goto out;
474
475 jme->phylink = phylink;
476
477 /*
478 * The speed/duplex setting of jme->reg_ghc already cleared
479 * by jme_reset_mac_processor()
480 */
481 switch (phylink & PHY_LINK_SPEED_MASK) {
482 case PHY_LINK_SPEED_10M:
483 jme->reg_ghc |= GHC_SPEED_10M;
484 strcat(linkmsg, "10 Mbps, ");
485 break;
486 case PHY_LINK_SPEED_100M:
487 jme->reg_ghc |= GHC_SPEED_100M;
488 strcat(linkmsg, "100 Mbps, ");
489 break;
490 case PHY_LINK_SPEED_1000M:
491 jme->reg_ghc |= GHC_SPEED_1000M;
492 strcat(linkmsg, "1000 Mbps, ");
493 break;
494 default:
495 break;
496 }
497
498 if (phylink & PHY_LINK_DUPLEX) {
499 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
500 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
501 jme->reg_ghc |= GHC_DPX;
502 } else {
503 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
504 TXMCS_BACKOFF |
505 TXMCS_CARRIERSENSE |
506 TXMCS_COLLISION);
507 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
508 }
509
510 jwrite32(jme, JME_GHC, jme->reg_ghc);
511
512 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
513 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
514 GPREG1_RSSPATCH);
515 if (!(phylink & PHY_LINK_DUPLEX))
516 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
517 switch (phylink & PHY_LINK_SPEED_MASK) {
518 case PHY_LINK_SPEED_10M:
519 jme_set_phyfifo_8level(jme);
520 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
521 break;
522 case PHY_LINK_SPEED_100M:
523 jme_set_phyfifo_5level(jme);
524 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
525 break;
526 case PHY_LINK_SPEED_1000M:
527 jme_set_phyfifo_8level(jme);
528 break;
529 default:
530 break;
531 }
532 }
533 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
534
535 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
536 "Full-Duplex, " :
537 "Half-Duplex, ");
538 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
539 "MDI-X" :
540 "MDI");
541 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
542 netif_carrier_on(netdev);
543 } else {
544 if (testonly)
545 goto out;
546
547 netif_info(jme, link, jme->dev, "Link is down\n");
548 jme->phylink = 0;
549 netif_carrier_off(netdev);
550 }
551
552 out:
553 return rc;
554 }
555
556 static int
557 jme_setup_tx_resources(struct jme_adapter *jme)
558 {
559 struct jme_ring *txring = &(jme->txring[0]);
560
561 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
562 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
563 &(txring->dmaalloc),
564 GFP_ATOMIC);
565
566 if (!txring->alloc)
567 goto err_set_null;
568
569 /*
570 * 16 Bytes align
571 */
572 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
573 RING_DESC_ALIGN);
574 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
575 txring->next_to_use = 0;
576 atomic_set(&txring->next_to_clean, 0);
577 atomic_set(&txring->nr_free, jme->tx_ring_size);
578
579 txring->bufinf = kcalloc(jme->tx_ring_size,
580 sizeof(struct jme_buffer_info),
581 GFP_ATOMIC);
582 if (unlikely(!(txring->bufinf)))
583 goto err_free_txring;
584
585 return 0;
586
587 err_free_txring:
588 dma_free_coherent(&(jme->pdev->dev),
589 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
590 txring->alloc,
591 txring->dmaalloc);
592
593 err_set_null:
594 txring->desc = NULL;
595 txring->dmaalloc = 0;
596 txring->dma = 0;
597 txring->bufinf = NULL;
598
599 return -ENOMEM;
600 }
601
602 static void
603 jme_free_tx_resources(struct jme_adapter *jme)
604 {
605 int i;
606 struct jme_ring *txring = &(jme->txring[0]);
607 struct jme_buffer_info *txbi;
608
609 if (txring->alloc) {
610 if (txring->bufinf) {
611 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
612 txbi = txring->bufinf + i;
613 if (txbi->skb) {
614 dev_kfree_skb(txbi->skb);
615 txbi->skb = NULL;
616 }
617 txbi->mapping = 0;
618 txbi->len = 0;
619 txbi->nr_desc = 0;
620 txbi->start_xmit = 0;
621 }
622 kfree(txring->bufinf);
623 }
624
625 dma_free_coherent(&(jme->pdev->dev),
626 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
627 txring->alloc,
628 txring->dmaalloc);
629
630 txring->alloc = NULL;
631 txring->desc = NULL;
632 txring->dmaalloc = 0;
633 txring->dma = 0;
634 txring->bufinf = NULL;
635 }
636 txring->next_to_use = 0;
637 atomic_set(&txring->next_to_clean, 0);
638 atomic_set(&txring->nr_free, 0);
639 }
640
641 static inline void
642 jme_enable_tx_engine(struct jme_adapter *jme)
643 {
644 /*
645 * Select Queue 0
646 */
647 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
648 wmb();
649
650 /*
651 * Setup TX Queue 0 DMA Bass Address
652 */
653 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
654 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
655 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
656
657 /*
658 * Setup TX Descptor Count
659 */
660 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
661
662 /*
663 * Enable TX Engine
664 */
665 wmb();
666 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
667 TXCS_SELECT_QUEUE0 |
668 TXCS_ENABLE);
669
670 /*
671 * Start clock for TX MAC Processor
672 */
673 jme_mac_txclk_on(jme);
674 }
675
676 static inline void
677 jme_disable_tx_engine(struct jme_adapter *jme)
678 {
679 int i;
680 u32 val;
681
682 /*
683 * Disable TX Engine
684 */
685 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
686 wmb();
687
688 val = jread32(jme, JME_TXCS);
689 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
690 mdelay(1);
691 val = jread32(jme, JME_TXCS);
692 rmb();
693 }
694
695 if (!i)
696 pr_err("Disable TX engine timeout\n");
697
698 /*
699 * Stop clock for TX MAC Processor
700 */
701 jme_mac_txclk_off(jme);
702 }
703
704 static void
705 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
706 {
707 struct jme_ring *rxring = &(jme->rxring[0]);
708 register struct rxdesc *rxdesc = rxring->desc;
709 struct jme_buffer_info *rxbi = rxring->bufinf;
710 rxdesc += i;
711 rxbi += i;
712
713 rxdesc->dw[0] = 0;
714 rxdesc->dw[1] = 0;
715 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
716 rxdesc->desc1.bufaddrl = cpu_to_le32(
717 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
718 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
719 if (jme->dev->features & NETIF_F_HIGHDMA)
720 rxdesc->desc1.flags = RXFLAG_64BIT;
721 wmb();
722 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
723 }
724
725 static int
726 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
727 {
728 struct jme_ring *rxring = &(jme->rxring[0]);
729 struct jme_buffer_info *rxbi = rxring->bufinf + i;
730 struct sk_buff *skb;
731 dma_addr_t mapping;
732
733 skb = netdev_alloc_skb(jme->dev,
734 jme->dev->mtu + RX_EXTRA_LEN);
735 if (unlikely(!skb))
736 return -ENOMEM;
737
738 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
739 offset_in_page(skb->data), skb_tailroom(skb),
740 PCI_DMA_FROMDEVICE);
741 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
742 dev_kfree_skb(skb);
743 return -ENOMEM;
744 }
745
746 if (likely(rxbi->mapping))
747 pci_unmap_page(jme->pdev, rxbi->mapping,
748 rxbi->len, PCI_DMA_FROMDEVICE);
749
750 rxbi->skb = skb;
751 rxbi->len = skb_tailroom(skb);
752 rxbi->mapping = mapping;
753 return 0;
754 }
755
756 static void
757 jme_free_rx_buf(struct jme_adapter *jme, int i)
758 {
759 struct jme_ring *rxring = &(jme->rxring[0]);
760 struct jme_buffer_info *rxbi = rxring->bufinf;
761 rxbi += i;
762
763 if (rxbi->skb) {
764 pci_unmap_page(jme->pdev,
765 rxbi->mapping,
766 rxbi->len,
767 PCI_DMA_FROMDEVICE);
768 dev_kfree_skb(rxbi->skb);
769 rxbi->skb = NULL;
770 rxbi->mapping = 0;
771 rxbi->len = 0;
772 }
773 }
774
775 static void
776 jme_free_rx_resources(struct jme_adapter *jme)
777 {
778 int i;
779 struct jme_ring *rxring = &(jme->rxring[0]);
780
781 if (rxring->alloc) {
782 if (rxring->bufinf) {
783 for (i = 0 ; i < jme->rx_ring_size ; ++i)
784 jme_free_rx_buf(jme, i);
785 kfree(rxring->bufinf);
786 }
787
788 dma_free_coherent(&(jme->pdev->dev),
789 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
790 rxring->alloc,
791 rxring->dmaalloc);
792 rxring->alloc = NULL;
793 rxring->desc = NULL;
794 rxring->dmaalloc = 0;
795 rxring->dma = 0;
796 rxring->bufinf = NULL;
797 }
798 rxring->next_to_use = 0;
799 atomic_set(&rxring->next_to_clean, 0);
800 }
801
802 static int
803 jme_setup_rx_resources(struct jme_adapter *jme)
804 {
805 int i;
806 struct jme_ring *rxring = &(jme->rxring[0]);
807
808 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
809 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
810 &(rxring->dmaalloc),
811 GFP_ATOMIC);
812 if (!rxring->alloc)
813 goto err_set_null;
814
815 /*
816 * 16 Bytes align
817 */
818 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
819 RING_DESC_ALIGN);
820 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
821 rxring->next_to_use = 0;
822 atomic_set(&rxring->next_to_clean, 0);
823
824 rxring->bufinf = kcalloc(jme->rx_ring_size,
825 sizeof(struct jme_buffer_info),
826 GFP_ATOMIC);
827 if (unlikely(!(rxring->bufinf)))
828 goto err_free_rxring;
829
830 /*
831 * Initiallize Receive Descriptors
832 */
833 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
834 if (unlikely(jme_make_new_rx_buf(jme, i))) {
835 jme_free_rx_resources(jme);
836 return -ENOMEM;
837 }
838
839 jme_set_clean_rxdesc(jme, i);
840 }
841
842 return 0;
843
844 err_free_rxring:
845 dma_free_coherent(&(jme->pdev->dev),
846 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
847 rxring->alloc,
848 rxring->dmaalloc);
849 err_set_null:
850 rxring->desc = NULL;
851 rxring->dmaalloc = 0;
852 rxring->dma = 0;
853 rxring->bufinf = NULL;
854
855 return -ENOMEM;
856 }
857
858 static inline void
859 jme_enable_rx_engine(struct jme_adapter *jme)
860 {
861 /*
862 * Select Queue 0
863 */
864 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
865 RXCS_QUEUESEL_Q0);
866 wmb();
867
868 /*
869 * Setup RX DMA Bass Address
870 */
871 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
872 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
873 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
874
875 /*
876 * Setup RX Descriptor Count
877 */
878 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
879
880 /*
881 * Setup Unicast Filter
882 */
883 jme_set_unicastaddr(jme->dev);
884 jme_set_multi(jme->dev);
885
886 /*
887 * Enable RX Engine
888 */
889 wmb();
890 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
891 RXCS_QUEUESEL_Q0 |
892 RXCS_ENABLE |
893 RXCS_QST);
894
895 /*
896 * Start clock for RX MAC Processor
897 */
898 jme_mac_rxclk_on(jme);
899 }
900
901 static inline void
902 jme_restart_rx_engine(struct jme_adapter *jme)
903 {
904 /*
905 * Start RX Engine
906 */
907 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
908 RXCS_QUEUESEL_Q0 |
909 RXCS_ENABLE |
910 RXCS_QST);
911 }
912
913 static inline void
914 jme_disable_rx_engine(struct jme_adapter *jme)
915 {
916 int i;
917 u32 val;
918
919 /*
920 * Disable RX Engine
921 */
922 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
923 wmb();
924
925 val = jread32(jme, JME_RXCS);
926 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
927 mdelay(1);
928 val = jread32(jme, JME_RXCS);
929 rmb();
930 }
931
932 if (!i)
933 pr_err("Disable RX engine timeout\n");
934
935 /*
936 * Stop clock for RX MAC Processor
937 */
938 jme_mac_rxclk_off(jme);
939 }
940
941 static u16
942 jme_udpsum(struct sk_buff *skb)
943 {
944 u16 csum = 0xFFFFu;
945
946 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
947 return csum;
948 if (skb->protocol != htons(ETH_P_IP))
949 return csum;
950 skb_set_network_header(skb, ETH_HLEN);
951 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
952 (skb->len < (ETH_HLEN +
953 (ip_hdr(skb)->ihl << 2) +
954 sizeof(struct udphdr)))) {
955 skb_reset_network_header(skb);
956 return csum;
957 }
958 skb_set_transport_header(skb,
959 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
960 csum = udp_hdr(skb)->check;
961 skb_reset_transport_header(skb);
962 skb_reset_network_header(skb);
963
964 return csum;
965 }
966
967 static int
968 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
969 {
970 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
971 return false;
972
973 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
974 == RXWBFLAG_TCPON)) {
975 if (flags & RXWBFLAG_IPV4)
976 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
977 return false;
978 }
979
980 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
981 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
982 if (flags & RXWBFLAG_IPV4)
983 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
984 return false;
985 }
986
987 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
988 == RXWBFLAG_IPV4)) {
989 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
990 return false;
991 }
992
993 return true;
994 }
995
996 static void
997 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
998 {
999 struct jme_ring *rxring = &(jme->rxring[0]);
1000 struct rxdesc *rxdesc = rxring->desc;
1001 struct jme_buffer_info *rxbi = rxring->bufinf;
1002 struct sk_buff *skb;
1003 int framesize;
1004
1005 rxdesc += idx;
1006 rxbi += idx;
1007
1008 skb = rxbi->skb;
1009 pci_dma_sync_single_for_cpu(jme->pdev,
1010 rxbi->mapping,
1011 rxbi->len,
1012 PCI_DMA_FROMDEVICE);
1013
1014 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1015 pci_dma_sync_single_for_device(jme->pdev,
1016 rxbi->mapping,
1017 rxbi->len,
1018 PCI_DMA_FROMDEVICE);
1019
1020 ++(NET_STAT(jme).rx_dropped);
1021 } else {
1022 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1023 - RX_PREPAD_SIZE;
1024
1025 skb_reserve(skb, RX_PREPAD_SIZE);
1026 skb_put(skb, framesize);
1027 skb->protocol = eth_type_trans(skb, jme->dev);
1028
1029 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1030 skb->ip_summed = CHECKSUM_UNNECESSARY;
1031 else
1032 skb_checksum_none_assert(skb);
1033
1034 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1035 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1036
1037 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1038 NET_STAT(jme).rx_bytes += 4;
1039 }
1040 jme->jme_rx(skb);
1041
1042 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1043 cpu_to_le16(RXWBFLAG_DEST_MUL))
1044 ++(NET_STAT(jme).multicast);
1045
1046 NET_STAT(jme).rx_bytes += framesize;
1047 ++(NET_STAT(jme).rx_packets);
1048 }
1049
1050 jme_set_clean_rxdesc(jme, idx);
1051
1052 }
1053
1054 static int
1055 jme_process_receive(struct jme_adapter *jme, int limit)
1056 {
1057 struct jme_ring *rxring = &(jme->rxring[0]);
1058 struct rxdesc *rxdesc;
1059 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1060
1061 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1062 goto out_inc;
1063
1064 if (unlikely(atomic_read(&jme->link_changing) != 1))
1065 goto out_inc;
1066
1067 if (unlikely(!netif_carrier_ok(jme->dev)))
1068 goto out_inc;
1069
1070 i = atomic_read(&rxring->next_to_clean);
1071 while (limit > 0) {
1072 rxdesc = rxring->desc;
1073 rxdesc += i;
1074
1075 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1076 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1077 goto out;
1078 --limit;
1079
1080 rmb();
1081 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1082
1083 if (unlikely(desccnt > 1 ||
1084 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1085
1086 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1087 ++(NET_STAT(jme).rx_crc_errors);
1088 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1089 ++(NET_STAT(jme).rx_fifo_errors);
1090 else
1091 ++(NET_STAT(jme).rx_errors);
1092
1093 if (desccnt > 1)
1094 limit -= desccnt - 1;
1095
1096 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1097 jme_set_clean_rxdesc(jme, j);
1098 j = (j + 1) & (mask);
1099 }
1100
1101 } else {
1102 jme_alloc_and_feed_skb(jme, i);
1103 }
1104
1105 i = (i + desccnt) & (mask);
1106 }
1107
1108 out:
1109 atomic_set(&rxring->next_to_clean, i);
1110
1111 out_inc:
1112 atomic_inc(&jme->rx_cleaning);
1113
1114 return limit > 0 ? limit : 0;
1115
1116 }
1117
1118 static void
1119 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1120 {
1121 if (likely(atmp == dpi->cur)) {
1122 dpi->cnt = 0;
1123 return;
1124 }
1125
1126 if (dpi->attempt == atmp) {
1127 ++(dpi->cnt);
1128 } else {
1129 dpi->attempt = atmp;
1130 dpi->cnt = 0;
1131 }
1132
1133 }
1134
1135 static void
1136 jme_dynamic_pcc(struct jme_adapter *jme)
1137 {
1138 register struct dynpcc_info *dpi = &(jme->dpi);
1139
1140 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1141 jme_attempt_pcc(dpi, PCC_P3);
1142 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1143 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1144 jme_attempt_pcc(dpi, PCC_P2);
1145 else
1146 jme_attempt_pcc(dpi, PCC_P1);
1147
1148 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1149 if (dpi->attempt < dpi->cur)
1150 tasklet_schedule(&jme->rxclean_task);
1151 jme_set_rx_pcc(jme, dpi->attempt);
1152 dpi->cur = dpi->attempt;
1153 dpi->cnt = 0;
1154 }
1155 }
1156
1157 static void
1158 jme_start_pcc_timer(struct jme_adapter *jme)
1159 {
1160 struct dynpcc_info *dpi = &(jme->dpi);
1161 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1162 dpi->last_pkts = NET_STAT(jme).rx_packets;
1163 dpi->intr_cnt = 0;
1164 jwrite32(jme, JME_TMCSR,
1165 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1166 }
1167
1168 static inline void
1169 jme_stop_pcc_timer(struct jme_adapter *jme)
1170 {
1171 jwrite32(jme, JME_TMCSR, 0);
1172 }
1173
1174 static void
1175 jme_shutdown_nic(struct jme_adapter *jme)
1176 {
1177 u32 phylink;
1178
1179 phylink = jme_linkstat_from_phy(jme);
1180
1181 if (!(phylink & PHY_LINK_UP)) {
1182 /*
1183 * Disable all interrupt before issue timer
1184 */
1185 jme_stop_irq(jme);
1186 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1187 }
1188 }
1189
1190 static void
1191 jme_pcc_tasklet(unsigned long arg)
1192 {
1193 struct jme_adapter *jme = (struct jme_adapter *)arg;
1194 struct net_device *netdev = jme->dev;
1195
1196 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1197 jme_shutdown_nic(jme);
1198 return;
1199 }
1200
1201 if (unlikely(!netif_carrier_ok(netdev) ||
1202 (atomic_read(&jme->link_changing) != 1)
1203 )) {
1204 jme_stop_pcc_timer(jme);
1205 return;
1206 }
1207
1208 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1209 jme_dynamic_pcc(jme);
1210
1211 jme_start_pcc_timer(jme);
1212 }
1213
1214 static inline void
1215 jme_polling_mode(struct jme_adapter *jme)
1216 {
1217 jme_set_rx_pcc(jme, PCC_OFF);
1218 }
1219
1220 static inline void
1221 jme_interrupt_mode(struct jme_adapter *jme)
1222 {
1223 jme_set_rx_pcc(jme, PCC_P1);
1224 }
1225
1226 static inline int
1227 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1228 {
1229 u32 apmc;
1230 apmc = jread32(jme, JME_APMC);
1231 return apmc & JME_APMC_PSEUDO_HP_EN;
1232 }
1233
1234 static void
1235 jme_start_shutdown_timer(struct jme_adapter *jme)
1236 {
1237 u32 apmc;
1238
1239 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1240 apmc &= ~JME_APMC_EPIEN_CTRL;
1241 if (!no_extplug) {
1242 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1243 wmb();
1244 }
1245 jwrite32f(jme, JME_APMC, apmc);
1246
1247 jwrite32f(jme, JME_TIMER2, 0);
1248 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1249 jwrite32(jme, JME_TMCSR,
1250 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1251 }
1252
1253 static void
1254 jme_stop_shutdown_timer(struct jme_adapter *jme)
1255 {
1256 u32 apmc;
1257
1258 jwrite32f(jme, JME_TMCSR, 0);
1259 jwrite32f(jme, JME_TIMER2, 0);
1260 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1261
1262 apmc = jread32(jme, JME_APMC);
1263 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1264 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1265 wmb();
1266 jwrite32f(jme, JME_APMC, apmc);
1267 }
1268
1269 static void
1270 jme_link_change_tasklet(unsigned long arg)
1271 {
1272 struct jme_adapter *jme = (struct jme_adapter *)arg;
1273 struct net_device *netdev = jme->dev;
1274 int rc;
1275
1276 while (!atomic_dec_and_test(&jme->link_changing)) {
1277 atomic_inc(&jme->link_changing);
1278 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1279 while (atomic_read(&jme->link_changing) != 1)
1280 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1281 }
1282
1283 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1284 goto out;
1285
1286 jme->old_mtu = netdev->mtu;
1287 netif_stop_queue(netdev);
1288 if (jme_pseudo_hotplug_enabled(jme))
1289 jme_stop_shutdown_timer(jme);
1290
1291 jme_stop_pcc_timer(jme);
1292 tasklet_disable(&jme->txclean_task);
1293 tasklet_disable(&jme->rxclean_task);
1294 tasklet_disable(&jme->rxempty_task);
1295
1296 if (netif_carrier_ok(netdev)) {
1297 jme_disable_rx_engine(jme);
1298 jme_disable_tx_engine(jme);
1299 jme_reset_mac_processor(jme);
1300 jme_free_rx_resources(jme);
1301 jme_free_tx_resources(jme);
1302
1303 if (test_bit(JME_FLAG_POLL, &jme->flags))
1304 jme_polling_mode(jme);
1305
1306 netif_carrier_off(netdev);
1307 }
1308
1309 jme_check_link(netdev, 0);
1310 if (netif_carrier_ok(netdev)) {
1311 rc = jme_setup_rx_resources(jme);
1312 if (rc) {
1313 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1314 goto out_enable_tasklet;
1315 }
1316
1317 rc = jme_setup_tx_resources(jme);
1318 if (rc) {
1319 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1320 goto err_out_free_rx_resources;
1321 }
1322
1323 jme_enable_rx_engine(jme);
1324 jme_enable_tx_engine(jme);
1325
1326 netif_start_queue(netdev);
1327
1328 if (test_bit(JME_FLAG_POLL, &jme->flags))
1329 jme_interrupt_mode(jme);
1330
1331 jme_start_pcc_timer(jme);
1332 } else if (jme_pseudo_hotplug_enabled(jme)) {
1333 jme_start_shutdown_timer(jme);
1334 }
1335
1336 goto out_enable_tasklet;
1337
1338 err_out_free_rx_resources:
1339 jme_free_rx_resources(jme);
1340 out_enable_tasklet:
1341 tasklet_enable(&jme->txclean_task);
1342 tasklet_enable(&jme->rxclean_task);
1343 tasklet_enable(&jme->rxempty_task);
1344 out:
1345 atomic_inc(&jme->link_changing);
1346 }
1347
1348 static void
1349 jme_rx_clean_tasklet(unsigned long arg)
1350 {
1351 struct jme_adapter *jme = (struct jme_adapter *)arg;
1352 struct dynpcc_info *dpi = &(jme->dpi);
1353
1354 jme_process_receive(jme, jme->rx_ring_size);
1355 ++(dpi->intr_cnt);
1356
1357 }
1358
1359 static int
1360 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1361 {
1362 struct jme_adapter *jme = jme_napi_priv(holder);
1363 int rest;
1364
1365 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1366
1367 while (atomic_read(&jme->rx_empty) > 0) {
1368 atomic_dec(&jme->rx_empty);
1369 ++(NET_STAT(jme).rx_dropped);
1370 jme_restart_rx_engine(jme);
1371 }
1372 atomic_inc(&jme->rx_empty);
1373
1374 if (rest) {
1375 JME_RX_COMPLETE(netdev, holder);
1376 jme_interrupt_mode(jme);
1377 }
1378
1379 JME_NAPI_WEIGHT_SET(budget, rest);
1380 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1381 }
1382
1383 static void
1384 jme_rx_empty_tasklet(unsigned long arg)
1385 {
1386 struct jme_adapter *jme = (struct jme_adapter *)arg;
1387
1388 if (unlikely(atomic_read(&jme->link_changing) != 1))
1389 return;
1390
1391 if (unlikely(!netif_carrier_ok(jme->dev)))
1392 return;
1393
1394 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1395
1396 jme_rx_clean_tasklet(arg);
1397
1398 while (atomic_read(&jme->rx_empty) > 0) {
1399 atomic_dec(&jme->rx_empty);
1400 ++(NET_STAT(jme).rx_dropped);
1401 jme_restart_rx_engine(jme);
1402 }
1403 atomic_inc(&jme->rx_empty);
1404 }
1405
1406 static void
1407 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1408 {
1409 struct jme_ring *txring = &(jme->txring[0]);
1410
1411 smp_wmb();
1412 if (unlikely(netif_queue_stopped(jme->dev) &&
1413 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1414 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1415 netif_wake_queue(jme->dev);
1416 }
1417
1418 }
1419
1420 static void
1421 jme_tx_clean_tasklet(unsigned long arg)
1422 {
1423 struct jme_adapter *jme = (struct jme_adapter *)arg;
1424 struct jme_ring *txring = &(jme->txring[0]);
1425 struct txdesc *txdesc = txring->desc;
1426 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1427 int i, j, cnt = 0, max, err, mask;
1428
1429 tx_dbg(jme, "Into txclean\n");
1430
1431 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1432 goto out;
1433
1434 if (unlikely(atomic_read(&jme->link_changing) != 1))
1435 goto out;
1436
1437 if (unlikely(!netif_carrier_ok(jme->dev)))
1438 goto out;
1439
1440 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1441 mask = jme->tx_ring_mask;
1442
1443 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1444
1445 ctxbi = txbi + i;
1446
1447 if (likely(ctxbi->skb &&
1448 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1449
1450 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1451 i, ctxbi->nr_desc, jiffies);
1452
1453 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1454
1455 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1456 ttxbi = txbi + ((i + j) & (mask));
1457 txdesc[(i + j) & (mask)].dw[0] = 0;
1458
1459 pci_unmap_page(jme->pdev,
1460 ttxbi->mapping,
1461 ttxbi->len,
1462 PCI_DMA_TODEVICE);
1463
1464 ttxbi->mapping = 0;
1465 ttxbi->len = 0;
1466 }
1467
1468 dev_kfree_skb(ctxbi->skb);
1469
1470 cnt += ctxbi->nr_desc;
1471
1472 if (unlikely(err)) {
1473 ++(NET_STAT(jme).tx_carrier_errors);
1474 } else {
1475 ++(NET_STAT(jme).tx_packets);
1476 NET_STAT(jme).tx_bytes += ctxbi->len;
1477 }
1478
1479 ctxbi->skb = NULL;
1480 ctxbi->len = 0;
1481 ctxbi->start_xmit = 0;
1482
1483 } else {
1484 break;
1485 }
1486
1487 i = (i + ctxbi->nr_desc) & mask;
1488
1489 ctxbi->nr_desc = 0;
1490 }
1491
1492 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1493 atomic_set(&txring->next_to_clean, i);
1494 atomic_add(cnt, &txring->nr_free);
1495
1496 jme_wake_queue_if_stopped(jme);
1497
1498 out:
1499 atomic_inc(&jme->tx_cleaning);
1500 }
1501
1502 static void
1503 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1504 {
1505 /*
1506 * Disable interrupt
1507 */
1508 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1509
1510 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1511 /*
1512 * Link change event is critical
1513 * all other events are ignored
1514 */
1515 jwrite32(jme, JME_IEVE, intrstat);
1516 tasklet_schedule(&jme->linkch_task);
1517 goto out_reenable;
1518 }
1519
1520 if (intrstat & INTR_TMINTR) {
1521 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1522 tasklet_schedule(&jme->pcc_task);
1523 }
1524
1525 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1526 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1527 tasklet_schedule(&jme->txclean_task);
1528 }
1529
1530 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1531 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1532 INTR_PCCRX0 |
1533 INTR_RX0EMP)) |
1534 INTR_RX0);
1535 }
1536
1537 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1538 if (intrstat & INTR_RX0EMP)
1539 atomic_inc(&jme->rx_empty);
1540
1541 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1542 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1543 jme_polling_mode(jme);
1544 JME_RX_SCHEDULE(jme);
1545 }
1546 }
1547 } else {
1548 if (intrstat & INTR_RX0EMP) {
1549 atomic_inc(&jme->rx_empty);
1550 tasklet_hi_schedule(&jme->rxempty_task);
1551 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1552 tasklet_hi_schedule(&jme->rxclean_task);
1553 }
1554 }
1555
1556 out_reenable:
1557 /*
1558 * Re-enable interrupt
1559 */
1560 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1561 }
1562
1563 static irqreturn_t
1564 jme_intr(int irq, void *dev_id)
1565 {
1566 struct net_device *netdev = dev_id;
1567 struct jme_adapter *jme = netdev_priv(netdev);
1568 u32 intrstat;
1569
1570 intrstat = jread32(jme, JME_IEVE);
1571
1572 /*
1573 * Check if it's really an interrupt for us
1574 */
1575 if (unlikely((intrstat & INTR_ENABLE) == 0))
1576 return IRQ_NONE;
1577
1578 /*
1579 * Check if the device still exist
1580 */
1581 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1582 return IRQ_NONE;
1583
1584 jme_intr_msi(jme, intrstat);
1585
1586 return IRQ_HANDLED;
1587 }
1588
1589 static irqreturn_t
1590 jme_msi(int irq, void *dev_id)
1591 {
1592 struct net_device *netdev = dev_id;
1593 struct jme_adapter *jme = netdev_priv(netdev);
1594 u32 intrstat;
1595
1596 intrstat = jread32(jme, JME_IEVE);
1597
1598 jme_intr_msi(jme, intrstat);
1599
1600 return IRQ_HANDLED;
1601 }
1602
1603 static void
1604 jme_reset_link(struct jme_adapter *jme)
1605 {
1606 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1607 }
1608
1609 static void
1610 jme_restart_an(struct jme_adapter *jme)
1611 {
1612 u32 bmcr;
1613
1614 spin_lock_bh(&jme->phy_lock);
1615 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1616 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1617 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1618 spin_unlock_bh(&jme->phy_lock);
1619 }
1620
1621 static int
1622 jme_request_irq(struct jme_adapter *jme)
1623 {
1624 int rc;
1625 struct net_device *netdev = jme->dev;
1626 irq_handler_t handler = jme_intr;
1627 int irq_flags = IRQF_SHARED;
1628
1629 if (!pci_enable_msi(jme->pdev)) {
1630 set_bit(JME_FLAG_MSI, &jme->flags);
1631 handler = jme_msi;
1632 irq_flags = 0;
1633 }
1634
1635 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1636 netdev);
1637 if (rc) {
1638 netdev_err(netdev,
1639 "Unable to request %s interrupt (return: %d)\n",
1640 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1641 rc);
1642
1643 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1644 pci_disable_msi(jme->pdev);
1645 clear_bit(JME_FLAG_MSI, &jme->flags);
1646 }
1647 } else {
1648 netdev->irq = jme->pdev->irq;
1649 }
1650
1651 return rc;
1652 }
1653
1654 static void
1655 jme_free_irq(struct jme_adapter *jme)
1656 {
1657 free_irq(jme->pdev->irq, jme->dev);
1658 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1659 pci_disable_msi(jme->pdev);
1660 clear_bit(JME_FLAG_MSI, &jme->flags);
1661 jme->dev->irq = jme->pdev->irq;
1662 }
1663 }
1664
1665 static inline void
1666 jme_new_phy_on(struct jme_adapter *jme)
1667 {
1668 u32 reg;
1669
1670 reg = jread32(jme, JME_PHY_PWR);
1671 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1672 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1673 jwrite32(jme, JME_PHY_PWR, reg);
1674
1675 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1676 reg &= ~PE1_GPREG0_PBG;
1677 reg |= PE1_GPREG0_ENBG;
1678 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1679 }
1680
1681 static inline void
1682 jme_new_phy_off(struct jme_adapter *jme)
1683 {
1684 u32 reg;
1685
1686 reg = jread32(jme, JME_PHY_PWR);
1687 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1688 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1689 jwrite32(jme, JME_PHY_PWR, reg);
1690
1691 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1692 reg &= ~PE1_GPREG0_PBG;
1693 reg |= PE1_GPREG0_PDD3COLD;
1694 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1695 }
1696
1697 static inline void
1698 jme_phy_on(struct jme_adapter *jme)
1699 {
1700 u32 bmcr;
1701
1702 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1703 bmcr &= ~BMCR_PDOWN;
1704 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1705
1706 if (new_phy_power_ctrl(jme->chip_main_rev))
1707 jme_new_phy_on(jme);
1708 }
1709
1710 static inline void
1711 jme_phy_off(struct jme_adapter *jme)
1712 {
1713 u32 bmcr;
1714
1715 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1716 bmcr |= BMCR_PDOWN;
1717 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1718
1719 if (new_phy_power_ctrl(jme->chip_main_rev))
1720 jme_new_phy_off(jme);
1721 }
1722
1723 static int
1724 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1725 {
1726 u32 phy_addr;
1727
1728 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1729 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1730 phy_addr);
1731 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1732 JM_PHY_SPEC_DATA_REG);
1733 }
1734
1735 static void
1736 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1737 {
1738 u32 phy_addr;
1739
1740 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1741 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1742 phy_data);
1743 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1744 phy_addr);
1745 }
1746
1747 static int
1748 jme_phy_calibration(struct jme_adapter *jme)
1749 {
1750 u32 ctrl1000, phy_data;
1751
1752 jme_phy_off(jme);
1753 jme_phy_on(jme);
1754 /* Enabel PHY test mode 1 */
1755 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1756 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1757 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1758 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1759
1760 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1761 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1762 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1763 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1764 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1765 msleep(20);
1766 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1767 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1768 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1769 JM_PHY_EXT_COMM_2_CALI_LATCH);
1770 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1771
1772 /* Disable PHY test mode */
1773 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1774 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1775 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1776 return 0;
1777 }
1778
1779 static int
1780 jme_phy_setEA(struct jme_adapter *jme)
1781 {
1782 u32 phy_comm0 = 0, phy_comm1 = 0;
1783 u8 nic_ctrl;
1784
1785 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1786 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1787 return 0;
1788
1789 switch (jme->pdev->device) {
1790 case PCI_DEVICE_ID_JMICRON_JMC250:
1791 if (((jme->chip_main_rev == 5) &&
1792 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1793 (jme->chip_sub_rev == 3))) ||
1794 (jme->chip_main_rev >= 6)) {
1795 phy_comm0 = 0x008A;
1796 phy_comm1 = 0x4109;
1797 }
1798 if ((jme->chip_main_rev == 3) &&
1799 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1800 phy_comm0 = 0xE088;
1801 break;
1802 case PCI_DEVICE_ID_JMICRON_JMC260:
1803 if (((jme->chip_main_rev == 5) &&
1804 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1805 (jme->chip_sub_rev == 3))) ||
1806 (jme->chip_main_rev >= 6)) {
1807 phy_comm0 = 0x008A;
1808 phy_comm1 = 0x4109;
1809 }
1810 if ((jme->chip_main_rev == 3) &&
1811 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1812 phy_comm0 = 0xE088;
1813 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1814 phy_comm0 = 0x608A;
1815 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1816 phy_comm0 = 0x408A;
1817 break;
1818 default:
1819 return -ENODEV;
1820 }
1821 if (phy_comm0)
1822 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1823 if (phy_comm1)
1824 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1825
1826 return 0;
1827 }
1828
1829 static int
1830 jme_open(struct net_device *netdev)
1831 {
1832 struct jme_adapter *jme = netdev_priv(netdev);
1833 int rc;
1834
1835 jme_clear_pm_disable_wol(jme);
1836 JME_NAPI_ENABLE(jme);
1837
1838 tasklet_init(&jme->linkch_task, jme_link_change_tasklet,
1839 (unsigned long) jme);
1840 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet,
1841 (unsigned long) jme);
1842 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet,
1843 (unsigned long) jme);
1844 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet,
1845 (unsigned long) jme);
1846
1847 rc = jme_request_irq(jme);
1848 if (rc)
1849 goto err_out;
1850
1851 jme_start_irq(jme);
1852
1853 jme_phy_on(jme);
1854 if (test_bit(JME_FLAG_SSET, &jme->flags))
1855 jme_set_link_ksettings(netdev, &jme->old_cmd);
1856 else
1857 jme_reset_phy_processor(jme);
1858 jme_phy_calibration(jme);
1859 jme_phy_setEA(jme);
1860 jme_reset_link(jme);
1861
1862 return 0;
1863
1864 err_out:
1865 netif_stop_queue(netdev);
1866 netif_carrier_off(netdev);
1867 return rc;
1868 }
1869
1870 static void
1871 jme_set_100m_half(struct jme_adapter *jme)
1872 {
1873 u32 bmcr, tmp;
1874
1875 jme_phy_on(jme);
1876 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1877 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1878 BMCR_SPEED1000 | BMCR_FULLDPLX);
1879 tmp |= BMCR_SPEED100;
1880
1881 if (bmcr != tmp)
1882 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1883
1884 if (jme->fpgaver)
1885 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1886 else
1887 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1888 }
1889
1890 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1891 static void
1892 jme_wait_link(struct jme_adapter *jme)
1893 {
1894 u32 phylink, to = JME_WAIT_LINK_TIME;
1895
1896 msleep(1000);
1897 phylink = jme_linkstat_from_phy(jme);
1898 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1899 usleep_range(10000, 11000);
1900 phylink = jme_linkstat_from_phy(jme);
1901 }
1902 }
1903
1904 static void
1905 jme_powersave_phy(struct jme_adapter *jme)
1906 {
1907 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1908 jme_set_100m_half(jme);
1909 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1910 jme_wait_link(jme);
1911 jme_clear_pm_enable_wol(jme);
1912 } else {
1913 jme_phy_off(jme);
1914 }
1915 }
1916
1917 static int
1918 jme_close(struct net_device *netdev)
1919 {
1920 struct jme_adapter *jme = netdev_priv(netdev);
1921
1922 netif_stop_queue(netdev);
1923 netif_carrier_off(netdev);
1924
1925 jme_stop_irq(jme);
1926 jme_free_irq(jme);
1927
1928 JME_NAPI_DISABLE(jme);
1929
1930 tasklet_kill(&jme->linkch_task);
1931 tasklet_kill(&jme->txclean_task);
1932 tasklet_kill(&jme->rxclean_task);
1933 tasklet_kill(&jme->rxempty_task);
1934
1935 jme_disable_rx_engine(jme);
1936 jme_disable_tx_engine(jme);
1937 jme_reset_mac_processor(jme);
1938 jme_free_rx_resources(jme);
1939 jme_free_tx_resources(jme);
1940 jme->phylink = 0;
1941 jme_phy_off(jme);
1942
1943 return 0;
1944 }
1945
1946 static int
1947 jme_alloc_txdesc(struct jme_adapter *jme,
1948 struct sk_buff *skb)
1949 {
1950 struct jme_ring *txring = &(jme->txring[0]);
1951 int idx, nr_alloc, mask = jme->tx_ring_mask;
1952
1953 idx = txring->next_to_use;
1954 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1955
1956 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1957 return -1;
1958
1959 atomic_sub(nr_alloc, &txring->nr_free);
1960
1961 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1962
1963 return idx;
1964 }
1965
1966 static int
1967 jme_fill_tx_map(struct pci_dev *pdev,
1968 struct txdesc *txdesc,
1969 struct jme_buffer_info *txbi,
1970 struct page *page,
1971 u32 page_offset,
1972 u32 len,
1973 bool hidma)
1974 {
1975 dma_addr_t dmaaddr;
1976
1977 dmaaddr = pci_map_page(pdev,
1978 page,
1979 page_offset,
1980 len,
1981 PCI_DMA_TODEVICE);
1982
1983 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
1984 return -EINVAL;
1985
1986 pci_dma_sync_single_for_device(pdev,
1987 dmaaddr,
1988 len,
1989 PCI_DMA_TODEVICE);
1990
1991 txdesc->dw[0] = 0;
1992 txdesc->dw[1] = 0;
1993 txdesc->desc2.flags = TXFLAG_OWN;
1994 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1995 txdesc->desc2.datalen = cpu_to_le16(len);
1996 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1997 txdesc->desc2.bufaddrl = cpu_to_le32(
1998 (__u64)dmaaddr & 0xFFFFFFFFUL);
1999
2000 txbi->mapping = dmaaddr;
2001 txbi->len = len;
2002 return 0;
2003 }
2004
2005 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
2006 {
2007 struct jme_ring *txring = &(jme->txring[0]);
2008 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2009 int mask = jme->tx_ring_mask;
2010 int j;
2011
2012 for (j = 0 ; j < count ; j++) {
2013 ctxbi = txbi + ((startidx + j + 2) & (mask));
2014 pci_unmap_page(jme->pdev,
2015 ctxbi->mapping,
2016 ctxbi->len,
2017 PCI_DMA_TODEVICE);
2018
2019 ctxbi->mapping = 0;
2020 ctxbi->len = 0;
2021 }
2022 }
2023
2024 static int
2025 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2026 {
2027 struct jme_ring *txring = &(jme->txring[0]);
2028 struct txdesc *txdesc = txring->desc, *ctxdesc;
2029 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2030 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2031 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2032 int mask = jme->tx_ring_mask;
2033 const struct skb_frag_struct *frag;
2034 u32 len;
2035 int ret = 0;
2036
2037 for (i = 0 ; i < nr_frags ; ++i) {
2038 frag = &skb_shinfo(skb)->frags[i];
2039 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2040 ctxbi = txbi + ((idx + i + 2) & (mask));
2041
2042 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2043 skb_frag_page(frag),
2044 frag->page_offset, skb_frag_size(frag), hidma);
2045 if (ret) {
2046 jme_drop_tx_map(jme, idx, i);
2047 goto out;
2048 }
2049
2050 }
2051
2052 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2053 ctxdesc = txdesc + ((idx + 1) & (mask));
2054 ctxbi = txbi + ((idx + 1) & (mask));
2055 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2056 offset_in_page(skb->data), len, hidma);
2057 if (ret)
2058 jme_drop_tx_map(jme, idx, i);
2059
2060 out:
2061 return ret;
2062
2063 }
2064
2065
2066 static int
2067 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2068 {
2069 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2070 if (*mss) {
2071 *flags |= TXFLAG_LSEN;
2072
2073 if (skb->protocol == htons(ETH_P_IP)) {
2074 struct iphdr *iph = ip_hdr(skb);
2075
2076 iph->check = 0;
2077 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2078 iph->daddr, 0,
2079 IPPROTO_TCP,
2080 0);
2081 } else {
2082 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2083
2084 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2085 &ip6h->daddr, 0,
2086 IPPROTO_TCP,
2087 0);
2088 }
2089
2090 return 0;
2091 }
2092
2093 return 1;
2094 }
2095
2096 static void
2097 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2098 {
2099 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2100 u8 ip_proto;
2101
2102 switch (skb->protocol) {
2103 case htons(ETH_P_IP):
2104 ip_proto = ip_hdr(skb)->protocol;
2105 break;
2106 case htons(ETH_P_IPV6):
2107 ip_proto = ipv6_hdr(skb)->nexthdr;
2108 break;
2109 default:
2110 ip_proto = 0;
2111 break;
2112 }
2113
2114 switch (ip_proto) {
2115 case IPPROTO_TCP:
2116 *flags |= TXFLAG_TCPCS;
2117 break;
2118 case IPPROTO_UDP:
2119 *flags |= TXFLAG_UDPCS;
2120 break;
2121 default:
2122 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2123 break;
2124 }
2125 }
2126 }
2127
2128 static inline void
2129 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2130 {
2131 if (skb_vlan_tag_present(skb)) {
2132 *flags |= TXFLAG_TAGON;
2133 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
2134 }
2135 }
2136
2137 static int
2138 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2139 {
2140 struct jme_ring *txring = &(jme->txring[0]);
2141 struct txdesc *txdesc;
2142 struct jme_buffer_info *txbi;
2143 u8 flags;
2144 int ret = 0;
2145
2146 txdesc = (struct txdesc *)txring->desc + idx;
2147 txbi = txring->bufinf + idx;
2148
2149 txdesc->dw[0] = 0;
2150 txdesc->dw[1] = 0;
2151 txdesc->dw[2] = 0;
2152 txdesc->dw[3] = 0;
2153 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2154 /*
2155 * Set OWN bit at final.
2156 * When kernel transmit faster than NIC.
2157 * And NIC trying to send this descriptor before we tell
2158 * it to start sending this TX queue.
2159 * Other fields are already filled correctly.
2160 */
2161 wmb();
2162 flags = TXFLAG_OWN | TXFLAG_INT;
2163 /*
2164 * Set checksum flags while not tso
2165 */
2166 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2167 jme_tx_csum(jme, skb, &flags);
2168 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2169 ret = jme_map_tx_skb(jme, skb, idx);
2170 if (ret)
2171 return ret;
2172
2173 txdesc->desc1.flags = flags;
2174 /*
2175 * Set tx buffer info after telling NIC to send
2176 * For better tx_clean timing
2177 */
2178 wmb();
2179 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2180 txbi->skb = skb;
2181 txbi->len = skb->len;
2182 txbi->start_xmit = jiffies;
2183 if (!txbi->start_xmit)
2184 txbi->start_xmit = (0UL-1);
2185
2186 return 0;
2187 }
2188
2189 static void
2190 jme_stop_queue_if_full(struct jme_adapter *jme)
2191 {
2192 struct jme_ring *txring = &(jme->txring[0]);
2193 struct jme_buffer_info *txbi = txring->bufinf;
2194 int idx = atomic_read(&txring->next_to_clean);
2195
2196 txbi += idx;
2197
2198 smp_wmb();
2199 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2200 netif_stop_queue(jme->dev);
2201 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2202 smp_wmb();
2203 if (atomic_read(&txring->nr_free)
2204 >= (jme->tx_wake_threshold)) {
2205 netif_wake_queue(jme->dev);
2206 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2207 }
2208 }
2209
2210 if (unlikely(txbi->start_xmit &&
2211 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2212 txbi->skb)) {
2213 netif_stop_queue(jme->dev);
2214 netif_info(jme, tx_queued, jme->dev,
2215 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2216 }
2217 }
2218
2219 /*
2220 * This function is already protected by netif_tx_lock()
2221 */
2222
2223 static netdev_tx_t
2224 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2225 {
2226 struct jme_adapter *jme = netdev_priv(netdev);
2227 int idx;
2228
2229 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2230 dev_kfree_skb_any(skb);
2231 ++(NET_STAT(jme).tx_dropped);
2232 return NETDEV_TX_OK;
2233 }
2234
2235 idx = jme_alloc_txdesc(jme, skb);
2236
2237 if (unlikely(idx < 0)) {
2238 netif_stop_queue(netdev);
2239 netif_err(jme, tx_err, jme->dev,
2240 "BUG! Tx ring full when queue awake!\n");
2241
2242 return NETDEV_TX_BUSY;
2243 }
2244
2245 if (jme_fill_tx_desc(jme, skb, idx))
2246 return NETDEV_TX_OK;
2247
2248 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2249 TXCS_SELECT_QUEUE0 |
2250 TXCS_QUEUE0S |
2251 TXCS_ENABLE);
2252
2253 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2254 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2255 jme_stop_queue_if_full(jme);
2256
2257 return NETDEV_TX_OK;
2258 }
2259
2260 static void
2261 jme_set_unicastaddr(struct net_device *netdev)
2262 {
2263 struct jme_adapter *jme = netdev_priv(netdev);
2264 u32 val;
2265
2266 val = (netdev->dev_addr[3] & 0xff) << 24 |
2267 (netdev->dev_addr[2] & 0xff) << 16 |
2268 (netdev->dev_addr[1] & 0xff) << 8 |
2269 (netdev->dev_addr[0] & 0xff);
2270 jwrite32(jme, JME_RXUMA_LO, val);
2271 val = (netdev->dev_addr[5] & 0xff) << 8 |
2272 (netdev->dev_addr[4] & 0xff);
2273 jwrite32(jme, JME_RXUMA_HI, val);
2274 }
2275
2276 static int
2277 jme_set_macaddr(struct net_device *netdev, void *p)
2278 {
2279 struct jme_adapter *jme = netdev_priv(netdev);
2280 struct sockaddr *addr = p;
2281
2282 if (netif_running(netdev))
2283 return -EBUSY;
2284
2285 spin_lock_bh(&jme->macaddr_lock);
2286 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2287 jme_set_unicastaddr(netdev);
2288 spin_unlock_bh(&jme->macaddr_lock);
2289
2290 return 0;
2291 }
2292
2293 static void
2294 jme_set_multi(struct net_device *netdev)
2295 {
2296 struct jme_adapter *jme = netdev_priv(netdev);
2297 u32 mc_hash[2] = {};
2298
2299 spin_lock_bh(&jme->rxmcs_lock);
2300
2301 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2302
2303 if (netdev->flags & IFF_PROMISC) {
2304 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2305 } else if (netdev->flags & IFF_ALLMULTI) {
2306 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2307 } else if (netdev->flags & IFF_MULTICAST) {
2308 struct netdev_hw_addr *ha;
2309 int bit_nr;
2310
2311 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2312 netdev_for_each_mc_addr(ha, netdev) {
2313 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2314 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2315 }
2316
2317 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2318 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2319 }
2320
2321 wmb();
2322 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2323
2324 spin_unlock_bh(&jme->rxmcs_lock);
2325 }
2326
2327 static int
2328 jme_change_mtu(struct net_device *netdev, int new_mtu)
2329 {
2330 struct jme_adapter *jme = netdev_priv(netdev);
2331
2332 netdev->mtu = new_mtu;
2333 netdev_update_features(netdev);
2334
2335 jme_restart_rx_engine(jme);
2336 jme_reset_link(jme);
2337
2338 return 0;
2339 }
2340
2341 static void
2342 jme_tx_timeout(struct net_device *netdev)
2343 {
2344 struct jme_adapter *jme = netdev_priv(netdev);
2345
2346 jme->phylink = 0;
2347 jme_reset_phy_processor(jme);
2348 if (test_bit(JME_FLAG_SSET, &jme->flags))
2349 jme_set_link_ksettings(netdev, &jme->old_cmd);
2350
2351 /*
2352 * Force to Reset the link again
2353 */
2354 jme_reset_link(jme);
2355 }
2356
2357 static void
2358 jme_get_drvinfo(struct net_device *netdev,
2359 struct ethtool_drvinfo *info)
2360 {
2361 struct jme_adapter *jme = netdev_priv(netdev);
2362
2363 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2364 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2365 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2366 }
2367
2368 static int
2369 jme_get_regs_len(struct net_device *netdev)
2370 {
2371 return JME_REG_LEN;
2372 }
2373
2374 static void
2375 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2376 {
2377 int i;
2378
2379 for (i = 0 ; i < len ; i += 4)
2380 p[i >> 2] = jread32(jme, reg + i);
2381 }
2382
2383 static void
2384 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2385 {
2386 int i;
2387 u16 *p16 = (u16 *)p;
2388
2389 for (i = 0 ; i < reg_nr ; ++i)
2390 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2391 }
2392
2393 static void
2394 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2395 {
2396 struct jme_adapter *jme = netdev_priv(netdev);
2397 u32 *p32 = (u32 *)p;
2398
2399 memset(p, 0xFF, JME_REG_LEN);
2400
2401 regs->version = 1;
2402 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2403
2404 p32 += 0x100 >> 2;
2405 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2406
2407 p32 += 0x100 >> 2;
2408 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2409
2410 p32 += 0x100 >> 2;
2411 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2412
2413 p32 += 0x100 >> 2;
2414 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2415 }
2416
2417 static int
2418 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2419 {
2420 struct jme_adapter *jme = netdev_priv(netdev);
2421
2422 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2423 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2424
2425 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2426 ecmd->use_adaptive_rx_coalesce = false;
2427 ecmd->rx_coalesce_usecs = 0;
2428 ecmd->rx_max_coalesced_frames = 0;
2429 return 0;
2430 }
2431
2432 ecmd->use_adaptive_rx_coalesce = true;
2433
2434 switch (jme->dpi.cur) {
2435 case PCC_P1:
2436 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2437 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2438 break;
2439 case PCC_P2:
2440 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2441 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2442 break;
2443 case PCC_P3:
2444 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2445 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2446 break;
2447 default:
2448 break;
2449 }
2450
2451 return 0;
2452 }
2453
2454 static int
2455 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2456 {
2457 struct jme_adapter *jme = netdev_priv(netdev);
2458 struct dynpcc_info *dpi = &(jme->dpi);
2459
2460 if (netif_running(netdev))
2461 return -EBUSY;
2462
2463 if (ecmd->use_adaptive_rx_coalesce &&
2464 test_bit(JME_FLAG_POLL, &jme->flags)) {
2465 clear_bit(JME_FLAG_POLL, &jme->flags);
2466 jme->jme_rx = netif_rx;
2467 dpi->cur = PCC_P1;
2468 dpi->attempt = PCC_P1;
2469 dpi->cnt = 0;
2470 jme_set_rx_pcc(jme, PCC_P1);
2471 jme_interrupt_mode(jme);
2472 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2473 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2474 set_bit(JME_FLAG_POLL, &jme->flags);
2475 jme->jme_rx = netif_receive_skb;
2476 jme_interrupt_mode(jme);
2477 }
2478
2479 return 0;
2480 }
2481
2482 static void
2483 jme_get_pauseparam(struct net_device *netdev,
2484 struct ethtool_pauseparam *ecmd)
2485 {
2486 struct jme_adapter *jme = netdev_priv(netdev);
2487 u32 val;
2488
2489 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2490 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2491
2492 spin_lock_bh(&jme->phy_lock);
2493 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2494 spin_unlock_bh(&jme->phy_lock);
2495
2496 ecmd->autoneg =
2497 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2498 }
2499
2500 static int
2501 jme_set_pauseparam(struct net_device *netdev,
2502 struct ethtool_pauseparam *ecmd)
2503 {
2504 struct jme_adapter *jme = netdev_priv(netdev);
2505 u32 val;
2506
2507 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2508 (ecmd->tx_pause != 0)) {
2509
2510 if (ecmd->tx_pause)
2511 jme->reg_txpfc |= TXPFC_PF_EN;
2512 else
2513 jme->reg_txpfc &= ~TXPFC_PF_EN;
2514
2515 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2516 }
2517
2518 spin_lock_bh(&jme->rxmcs_lock);
2519 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2520 (ecmd->rx_pause != 0)) {
2521
2522 if (ecmd->rx_pause)
2523 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2524 else
2525 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2526
2527 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2528 }
2529 spin_unlock_bh(&jme->rxmcs_lock);
2530
2531 spin_lock_bh(&jme->phy_lock);
2532 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2533 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2534 (ecmd->autoneg != 0)) {
2535
2536 if (ecmd->autoneg)
2537 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2538 else
2539 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2540
2541 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2542 MII_ADVERTISE, val);
2543 }
2544 spin_unlock_bh(&jme->phy_lock);
2545
2546 return 0;
2547 }
2548
2549 static void
2550 jme_get_wol(struct net_device *netdev,
2551 struct ethtool_wolinfo *wol)
2552 {
2553 struct jme_adapter *jme = netdev_priv(netdev);
2554
2555 wol->supported = WAKE_MAGIC | WAKE_PHY;
2556
2557 wol->wolopts = 0;
2558
2559 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2560 wol->wolopts |= WAKE_PHY;
2561
2562 if (jme->reg_pmcs & PMCS_MFEN)
2563 wol->wolopts |= WAKE_MAGIC;
2564
2565 }
2566
2567 static int
2568 jme_set_wol(struct net_device *netdev,
2569 struct ethtool_wolinfo *wol)
2570 {
2571 struct jme_adapter *jme = netdev_priv(netdev);
2572
2573 if (wol->wolopts & (WAKE_MAGICSECURE |
2574 WAKE_UCAST |
2575 WAKE_MCAST |
2576 WAKE_BCAST |
2577 WAKE_ARP))
2578 return -EOPNOTSUPP;
2579
2580 jme->reg_pmcs = 0;
2581
2582 if (wol->wolopts & WAKE_PHY)
2583 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2584
2585 if (wol->wolopts & WAKE_MAGIC)
2586 jme->reg_pmcs |= PMCS_MFEN;
2587
2588 return 0;
2589 }
2590
2591 static int
2592 jme_get_link_ksettings(struct net_device *netdev,
2593 struct ethtool_link_ksettings *cmd)
2594 {
2595 struct jme_adapter *jme = netdev_priv(netdev);
2596
2597 spin_lock_bh(&jme->phy_lock);
2598 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
2599 spin_unlock_bh(&jme->phy_lock);
2600 return 0;
2601 }
2602
2603 static int
2604 jme_set_link_ksettings(struct net_device *netdev,
2605 const struct ethtool_link_ksettings *cmd)
2606 {
2607 struct jme_adapter *jme = netdev_priv(netdev);
2608 int rc, fdc = 0;
2609
2610 if (cmd->base.speed == SPEED_1000 &&
2611 cmd->base.autoneg != AUTONEG_ENABLE)
2612 return -EINVAL;
2613
2614 /*
2615 * Check If user changed duplex only while force_media.
2616 * Hardware would not generate link change interrupt.
2617 */
2618 if (jme->mii_if.force_media &&
2619 cmd->base.autoneg != AUTONEG_ENABLE &&
2620 (jme->mii_if.full_duplex != cmd->base.duplex))
2621 fdc = 1;
2622
2623 spin_lock_bh(&jme->phy_lock);
2624 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
2625 spin_unlock_bh(&jme->phy_lock);
2626
2627 if (!rc) {
2628 if (fdc)
2629 jme_reset_link(jme);
2630 jme->old_cmd = *cmd;
2631 set_bit(JME_FLAG_SSET, &jme->flags);
2632 }
2633
2634 return rc;
2635 }
2636
2637 static int
2638 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2639 {
2640 int rc;
2641 struct jme_adapter *jme = netdev_priv(netdev);
2642 struct mii_ioctl_data *mii_data = if_mii(rq);
2643 unsigned int duplex_chg;
2644
2645 if (cmd == SIOCSMIIREG) {
2646 u16 val = mii_data->val_in;
2647 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2648 (val & BMCR_SPEED1000))
2649 return -EINVAL;
2650 }
2651
2652 spin_lock_bh(&jme->phy_lock);
2653 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2654 spin_unlock_bh(&jme->phy_lock);
2655
2656 if (!rc && (cmd == SIOCSMIIREG)) {
2657 if (duplex_chg)
2658 jme_reset_link(jme);
2659 jme_get_link_ksettings(netdev, &jme->old_cmd);
2660 set_bit(JME_FLAG_SSET, &jme->flags);
2661 }
2662
2663 return rc;
2664 }
2665
2666 static u32
2667 jme_get_link(struct net_device *netdev)
2668 {
2669 struct jme_adapter *jme = netdev_priv(netdev);
2670 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2671 }
2672
2673 static u32
2674 jme_get_msglevel(struct net_device *netdev)
2675 {
2676 struct jme_adapter *jme = netdev_priv(netdev);
2677 return jme->msg_enable;
2678 }
2679
2680 static void
2681 jme_set_msglevel(struct net_device *netdev, u32 value)
2682 {
2683 struct jme_adapter *jme = netdev_priv(netdev);
2684 jme->msg_enable = value;
2685 }
2686
2687 static netdev_features_t
2688 jme_fix_features(struct net_device *netdev, netdev_features_t features)
2689 {
2690 if (netdev->mtu > 1900)
2691 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
2692 return features;
2693 }
2694
2695 static int
2696 jme_set_features(struct net_device *netdev, netdev_features_t features)
2697 {
2698 struct jme_adapter *jme = netdev_priv(netdev);
2699
2700 spin_lock_bh(&jme->rxmcs_lock);
2701 if (features & NETIF_F_RXCSUM)
2702 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2703 else
2704 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2705 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2706 spin_unlock_bh(&jme->rxmcs_lock);
2707
2708 return 0;
2709 }
2710
2711 #ifdef CONFIG_NET_POLL_CONTROLLER
2712 static void jme_netpoll(struct net_device *dev)
2713 {
2714 unsigned long flags;
2715
2716 local_irq_save(flags);
2717 jme_intr(dev->irq, dev);
2718 local_irq_restore(flags);
2719 }
2720 #endif
2721
2722 static int
2723 jme_nway_reset(struct net_device *netdev)
2724 {
2725 struct jme_adapter *jme = netdev_priv(netdev);
2726 jme_restart_an(jme);
2727 return 0;
2728 }
2729
2730 static u8
2731 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2732 {
2733 u32 val;
2734 int to;
2735
2736 val = jread32(jme, JME_SMBCSR);
2737 to = JME_SMB_BUSY_TIMEOUT;
2738 while ((val & SMBCSR_BUSY) && --to) {
2739 msleep(1);
2740 val = jread32(jme, JME_SMBCSR);
2741 }
2742 if (!to) {
2743 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2744 return 0xFF;
2745 }
2746
2747 jwrite32(jme, JME_SMBINTF,
2748 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2749 SMBINTF_HWRWN_READ |
2750 SMBINTF_HWCMD);
2751
2752 val = jread32(jme, JME_SMBINTF);
2753 to = JME_SMB_BUSY_TIMEOUT;
2754 while ((val & SMBINTF_HWCMD) && --to) {
2755 msleep(1);
2756 val = jread32(jme, JME_SMBINTF);
2757 }
2758 if (!to) {
2759 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2760 return 0xFF;
2761 }
2762
2763 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2764 }
2765
2766 static void
2767 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2768 {
2769 u32 val;
2770 int to;
2771
2772 val = jread32(jme, JME_SMBCSR);
2773 to = JME_SMB_BUSY_TIMEOUT;
2774 while ((val & SMBCSR_BUSY) && --to) {
2775 msleep(1);
2776 val = jread32(jme, JME_SMBCSR);
2777 }
2778 if (!to) {
2779 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2780 return;
2781 }
2782
2783 jwrite32(jme, JME_SMBINTF,
2784 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2785 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2786 SMBINTF_HWRWN_WRITE |
2787 SMBINTF_HWCMD);
2788
2789 val = jread32(jme, JME_SMBINTF);
2790 to = JME_SMB_BUSY_TIMEOUT;
2791 while ((val & SMBINTF_HWCMD) && --to) {
2792 msleep(1);
2793 val = jread32(jme, JME_SMBINTF);
2794 }
2795 if (!to) {
2796 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2797 return;
2798 }
2799
2800 mdelay(2);
2801 }
2802
2803 static int
2804 jme_get_eeprom_len(struct net_device *netdev)
2805 {
2806 struct jme_adapter *jme = netdev_priv(netdev);
2807 u32 val;
2808 val = jread32(jme, JME_SMBCSR);
2809 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2810 }
2811
2812 static int
2813 jme_get_eeprom(struct net_device *netdev,
2814 struct ethtool_eeprom *eeprom, u8 *data)
2815 {
2816 struct jme_adapter *jme = netdev_priv(netdev);
2817 int i, offset = eeprom->offset, len = eeprom->len;
2818
2819 /*
2820 * ethtool will check the boundary for us
2821 */
2822 eeprom->magic = JME_EEPROM_MAGIC;
2823 for (i = 0 ; i < len ; ++i)
2824 data[i] = jme_smb_read(jme, i + offset);
2825
2826 return 0;
2827 }
2828
2829 static int
2830 jme_set_eeprom(struct net_device *netdev,
2831 struct ethtool_eeprom *eeprom, u8 *data)
2832 {
2833 struct jme_adapter *jme = netdev_priv(netdev);
2834 int i, offset = eeprom->offset, len = eeprom->len;
2835
2836 if (eeprom->magic != JME_EEPROM_MAGIC)
2837 return -EINVAL;
2838
2839 /*
2840 * ethtool will check the boundary for us
2841 */
2842 for (i = 0 ; i < len ; ++i)
2843 jme_smb_write(jme, i + offset, data[i]);
2844
2845 return 0;
2846 }
2847
2848 static const struct ethtool_ops jme_ethtool_ops = {
2849 .get_drvinfo = jme_get_drvinfo,
2850 .get_regs_len = jme_get_regs_len,
2851 .get_regs = jme_get_regs,
2852 .get_coalesce = jme_get_coalesce,
2853 .set_coalesce = jme_set_coalesce,
2854 .get_pauseparam = jme_get_pauseparam,
2855 .set_pauseparam = jme_set_pauseparam,
2856 .get_wol = jme_get_wol,
2857 .set_wol = jme_set_wol,
2858 .get_link = jme_get_link,
2859 .get_msglevel = jme_get_msglevel,
2860 .set_msglevel = jme_set_msglevel,
2861 .nway_reset = jme_nway_reset,
2862 .get_eeprom_len = jme_get_eeprom_len,
2863 .get_eeprom = jme_get_eeprom,
2864 .set_eeprom = jme_set_eeprom,
2865 .get_link_ksettings = jme_get_link_ksettings,
2866 .set_link_ksettings = jme_set_link_ksettings,
2867 };
2868
2869 static int
2870 jme_pci_dma64(struct pci_dev *pdev)
2871 {
2872 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2873 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2874 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2875 return 1;
2876
2877 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2878 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2879 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2880 return 1;
2881
2882 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2883 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2884 return 0;
2885
2886 return -1;
2887 }
2888
2889 static inline void
2890 jme_phy_init(struct jme_adapter *jme)
2891 {
2892 u16 reg26;
2893
2894 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2895 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2896 }
2897
2898 static inline void
2899 jme_check_hw_ver(struct jme_adapter *jme)
2900 {
2901 u32 chipmode;
2902
2903 chipmode = jread32(jme, JME_CHIPMODE);
2904
2905 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2906 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2907 jme->chip_main_rev = jme->chiprev & 0xF;
2908 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2909 }
2910
2911 static const struct net_device_ops jme_netdev_ops = {
2912 .ndo_open = jme_open,
2913 .ndo_stop = jme_close,
2914 .ndo_validate_addr = eth_validate_addr,
2915 .ndo_do_ioctl = jme_ioctl,
2916 .ndo_start_xmit = jme_start_xmit,
2917 .ndo_set_mac_address = jme_set_macaddr,
2918 .ndo_set_rx_mode = jme_set_multi,
2919 .ndo_change_mtu = jme_change_mtu,
2920 .ndo_tx_timeout = jme_tx_timeout,
2921 .ndo_fix_features = jme_fix_features,
2922 .ndo_set_features = jme_set_features,
2923 #ifdef CONFIG_NET_POLL_CONTROLLER
2924 .ndo_poll_controller = jme_netpoll,
2925 #endif
2926 };
2927
2928 static int
2929 jme_init_one(struct pci_dev *pdev,
2930 const struct pci_device_id *ent)
2931 {
2932 int rc = 0, using_dac, i;
2933 struct net_device *netdev;
2934 struct jme_adapter *jme;
2935 u16 bmcr, bmsr;
2936 u32 apmc;
2937
2938 /*
2939 * set up PCI device basics
2940 */
2941 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2942 PCIE_LINK_STATE_CLKPM);
2943
2944 rc = pci_enable_device(pdev);
2945 if (rc) {
2946 pr_err("Cannot enable PCI device\n");
2947 goto err_out;
2948 }
2949
2950 using_dac = jme_pci_dma64(pdev);
2951 if (using_dac < 0) {
2952 pr_err("Cannot set PCI DMA Mask\n");
2953 rc = -EIO;
2954 goto err_out_disable_pdev;
2955 }
2956
2957 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2958 pr_err("No PCI resource region found\n");
2959 rc = -ENOMEM;
2960 goto err_out_disable_pdev;
2961 }
2962
2963 rc = pci_request_regions(pdev, DRV_NAME);
2964 if (rc) {
2965 pr_err("Cannot obtain PCI resource region\n");
2966 goto err_out_disable_pdev;
2967 }
2968
2969 pci_set_master(pdev);
2970
2971 /*
2972 * alloc and init net device
2973 */
2974 netdev = alloc_etherdev(sizeof(*jme));
2975 if (!netdev) {
2976 rc = -ENOMEM;
2977 goto err_out_release_regions;
2978 }
2979 netdev->netdev_ops = &jme_netdev_ops;
2980 netdev->ethtool_ops = &jme_ethtool_ops;
2981 netdev->watchdog_timeo = TX_TIMEOUT;
2982 netdev->hw_features = NETIF_F_IP_CSUM |
2983 NETIF_F_IPV6_CSUM |
2984 NETIF_F_SG |
2985 NETIF_F_TSO |
2986 NETIF_F_TSO6 |
2987 NETIF_F_RXCSUM;
2988 netdev->features = NETIF_F_IP_CSUM |
2989 NETIF_F_IPV6_CSUM |
2990 NETIF_F_SG |
2991 NETIF_F_TSO |
2992 NETIF_F_TSO6 |
2993 NETIF_F_HW_VLAN_CTAG_TX |
2994 NETIF_F_HW_VLAN_CTAG_RX;
2995 if (using_dac)
2996 netdev->features |= NETIF_F_HIGHDMA;
2997
2998 /* MTU range: 1280 - 9202*/
2999 netdev->min_mtu = IPV6_MIN_MTU;
3000 netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
3001
3002 SET_NETDEV_DEV(netdev, &pdev->dev);
3003 pci_set_drvdata(pdev, netdev);
3004
3005 /*
3006 * init adapter info
3007 */
3008 jme = netdev_priv(netdev);
3009 jme->pdev = pdev;
3010 jme->dev = netdev;
3011 jme->jme_rx = netif_rx;
3012 jme->old_mtu = netdev->mtu = 1500;
3013 jme->phylink = 0;
3014 jme->tx_ring_size = 1 << 10;
3015 jme->tx_ring_mask = jme->tx_ring_size - 1;
3016 jme->tx_wake_threshold = 1 << 9;
3017 jme->rx_ring_size = 1 << 9;
3018 jme->rx_ring_mask = jme->rx_ring_size - 1;
3019 jme->msg_enable = JME_DEF_MSG_ENABLE;
3020 jme->regs = ioremap(pci_resource_start(pdev, 0),
3021 pci_resource_len(pdev, 0));
3022 if (!(jme->regs)) {
3023 pr_err("Mapping PCI resource region error\n");
3024 rc = -ENOMEM;
3025 goto err_out_free_netdev;
3026 }
3027
3028 if (no_pseudohp) {
3029 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3030 jwrite32(jme, JME_APMC, apmc);
3031 } else if (force_pseudohp) {
3032 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3033 jwrite32(jme, JME_APMC, apmc);
3034 }
3035
3036 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
3037
3038 spin_lock_init(&jme->phy_lock);
3039 spin_lock_init(&jme->macaddr_lock);
3040 spin_lock_init(&jme->rxmcs_lock);
3041
3042 atomic_set(&jme->link_changing, 1);
3043 atomic_set(&jme->rx_cleaning, 1);
3044 atomic_set(&jme->tx_cleaning, 1);
3045 atomic_set(&jme->rx_empty, 1);
3046
3047 tasklet_init(&jme->pcc_task,
3048 jme_pcc_tasklet,
3049 (unsigned long) jme);
3050 jme->dpi.cur = PCC_P1;
3051
3052 jme->reg_ghc = 0;
3053 jme->reg_rxcs = RXCS_DEFAULT;
3054 jme->reg_rxmcs = RXMCS_DEFAULT;
3055 jme->reg_txpfc = 0;
3056 jme->reg_pmcs = PMCS_MFEN;
3057 jme->reg_gpreg1 = GPREG1_DEFAULT;
3058
3059 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3060 netdev->features |= NETIF_F_RXCSUM;
3061
3062 /*
3063 * Get Max Read Req Size from PCI Config Space
3064 */
3065 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3066 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3067 switch (jme->mrrs) {
3068 case MRRS_128B:
3069 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3070 break;
3071 case MRRS_256B:
3072 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3073 break;
3074 default:
3075 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3076 break;
3077 }
3078
3079 /*
3080 * Must check before reset_mac_processor
3081 */
3082 jme_check_hw_ver(jme);
3083 jme->mii_if.dev = netdev;
3084 if (jme->fpgaver) {
3085 jme->mii_if.phy_id = 0;
3086 for (i = 1 ; i < 32 ; ++i) {
3087 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3088 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3089 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3090 jme->mii_if.phy_id = i;
3091 break;
3092 }
3093 }
3094
3095 if (!jme->mii_if.phy_id) {
3096 rc = -EIO;
3097 pr_err("Can not find phy_id\n");
3098 goto err_out_unmap;
3099 }
3100
3101 jme->reg_ghc |= GHC_LINK_POLL;
3102 } else {
3103 jme->mii_if.phy_id = 1;
3104 }
3105 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3106 jme->mii_if.supports_gmii = true;
3107 else
3108 jme->mii_if.supports_gmii = false;
3109 jme->mii_if.phy_id_mask = 0x1F;
3110 jme->mii_if.reg_num_mask = 0x1F;
3111 jme->mii_if.mdio_read = jme_mdio_read;
3112 jme->mii_if.mdio_write = jme_mdio_write;
3113
3114 jme_clear_pm_disable_wol(jme);
3115 device_init_wakeup(&pdev->dev, true);
3116
3117 jme_set_phyfifo_5level(jme);
3118 jme->pcirev = pdev->revision;
3119 if (!jme->fpgaver)
3120 jme_phy_init(jme);
3121 jme_phy_off(jme);
3122
3123 /*
3124 * Reset MAC processor and reload EEPROM for MAC Address
3125 */
3126 jme_reset_mac_processor(jme);
3127 rc = jme_reload_eeprom(jme);
3128 if (rc) {
3129 pr_err("Reload eeprom for reading MAC Address error\n");
3130 goto err_out_unmap;
3131 }
3132 jme_load_macaddr(netdev);
3133
3134 /*
3135 * Tell stack that we are not ready to work until open()
3136 */
3137 netif_carrier_off(netdev);
3138
3139 rc = register_netdev(netdev);
3140 if (rc) {
3141 pr_err("Cannot register net device\n");
3142 goto err_out_unmap;
3143 }
3144
3145 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3146 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3147 "JMC250 Gigabit Ethernet" :
3148 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3149 "JMC260 Fast Ethernet" : "Unknown",
3150 (jme->fpgaver != 0) ? " (FPGA)" : "",
3151 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3152 jme->pcirev, netdev->dev_addr);
3153
3154 return 0;
3155
3156 err_out_unmap:
3157 iounmap(jme->regs);
3158 err_out_free_netdev:
3159 free_netdev(netdev);
3160 err_out_release_regions:
3161 pci_release_regions(pdev);
3162 err_out_disable_pdev:
3163 pci_disable_device(pdev);
3164 err_out:
3165 return rc;
3166 }
3167
3168 static void
3169 jme_remove_one(struct pci_dev *pdev)
3170 {
3171 struct net_device *netdev = pci_get_drvdata(pdev);
3172 struct jme_adapter *jme = netdev_priv(netdev);
3173
3174 unregister_netdev(netdev);
3175 iounmap(jme->regs);
3176 free_netdev(netdev);
3177 pci_release_regions(pdev);
3178 pci_disable_device(pdev);
3179
3180 }
3181
3182 static void
3183 jme_shutdown(struct pci_dev *pdev)
3184 {
3185 struct net_device *netdev = pci_get_drvdata(pdev);
3186 struct jme_adapter *jme = netdev_priv(netdev);
3187
3188 jme_powersave_phy(jme);
3189 pci_pme_active(pdev, true);
3190 }
3191
3192 #ifdef CONFIG_PM_SLEEP
3193 static int
3194 jme_suspend(struct device *dev)
3195 {
3196 struct pci_dev *pdev = to_pci_dev(dev);
3197 struct net_device *netdev = pci_get_drvdata(pdev);
3198 struct jme_adapter *jme = netdev_priv(netdev);
3199
3200 if (!netif_running(netdev))
3201 return 0;
3202
3203 atomic_dec(&jme->link_changing);
3204
3205 netif_device_detach(netdev);
3206 netif_stop_queue(netdev);
3207 jme_stop_irq(jme);
3208
3209 tasklet_disable(&jme->txclean_task);
3210 tasklet_disable(&jme->rxclean_task);
3211 tasklet_disable(&jme->rxempty_task);
3212
3213 if (netif_carrier_ok(netdev)) {
3214 if (test_bit(JME_FLAG_POLL, &jme->flags))
3215 jme_polling_mode(jme);
3216
3217 jme_stop_pcc_timer(jme);
3218 jme_disable_rx_engine(jme);
3219 jme_disable_tx_engine(jme);
3220 jme_reset_mac_processor(jme);
3221 jme_free_rx_resources(jme);
3222 jme_free_tx_resources(jme);
3223 netif_carrier_off(netdev);
3224 jme->phylink = 0;
3225 }
3226
3227 tasklet_enable(&jme->txclean_task);
3228 tasklet_enable(&jme->rxclean_task);
3229 tasklet_enable(&jme->rxempty_task);
3230
3231 jme_powersave_phy(jme);
3232
3233 return 0;
3234 }
3235
3236 static int
3237 jme_resume(struct device *dev)
3238 {
3239 struct pci_dev *pdev = to_pci_dev(dev);
3240 struct net_device *netdev = pci_get_drvdata(pdev);
3241 struct jme_adapter *jme = netdev_priv(netdev);
3242
3243 if (!netif_running(netdev))
3244 return 0;
3245
3246 jme_clear_pm_disable_wol(jme);
3247 jme_phy_on(jme);
3248 if (test_bit(JME_FLAG_SSET, &jme->flags))
3249 jme_set_link_ksettings(netdev, &jme->old_cmd);
3250 else
3251 jme_reset_phy_processor(jme);
3252 jme_phy_calibration(jme);
3253 jme_phy_setEA(jme);
3254 netif_device_attach(netdev);
3255
3256 atomic_inc(&jme->link_changing);
3257
3258 jme_reset_link(jme);
3259
3260 jme_start_irq(jme);
3261
3262 return 0;
3263 }
3264
3265 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3266 #define JME_PM_OPS (&jme_pm_ops)
3267
3268 #else
3269
3270 #define JME_PM_OPS NULL
3271 #endif
3272
3273 static const struct pci_device_id jme_pci_tbl[] = {
3274 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3275 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3276 { }
3277 };
3278
3279 static struct pci_driver jme_driver = {
3280 .name = DRV_NAME,
3281 .id_table = jme_pci_tbl,
3282 .probe = jme_init_one,
3283 .remove = jme_remove_one,
3284 .shutdown = jme_shutdown,
3285 .driver.pm = JME_PM_OPS,
3286 };
3287
3288 static int __init
3289 jme_init_module(void)
3290 {
3291 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3292 return pci_register_driver(&jme_driver);
3293 }
3294
3295 static void __exit
3296 jme_cleanup_module(void)
3297 {
3298 pci_unregister_driver(&jme_driver);
3299 }
3300
3301 module_init(jme_init_module);
3302 module_exit(jme_cleanup_module);
3303
3304 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3305 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3306 MODULE_LICENSE("GPL");
3307 MODULE_VERSION(DRV_VERSION);
3308 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
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