2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy.h>
32 #include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
36 #include "mvneta_bm.h"
40 #include <net/page_pool.h>
41 #include <linux/bpf_trace.h>
44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
66 #define MVNETA_PORT_RX_RESET 0x1cc0
67 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
68 #define MVNETA_PHY_ADDR 0x2000
69 #define MVNETA_PHY_ADDR_MASK 0x1f
70 #define MVNETA_MBUS_RETRY 0x2010
71 #define MVNETA_UNIT_INTR_CAUSE 0x2080
72 #define MVNETA_UNIT_CONTROL 0x20B0
73 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
77 #define MVNETA_BASE_ADDR_ENABLE 0x2290
78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
79 #define MVNETA_PORT_CONFIG 0x2400
80 #define MVNETA_UNI_PROMISC_MODE BIT(0)
81 #define MVNETA_DEF_RXQ(q) ((q) << 1)
82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
89 MVNETA_DEF_RXQ_ARP(q) | \
90 MVNETA_DEF_RXQ_TCP(q) | \
91 MVNETA_DEF_RXQ_UDP(q) | \
92 MVNETA_DEF_RXQ_BPDU(q) | \
93 MVNETA_TX_UNSET_ERR_SUM | \
94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
96 #define MVNETA_MAC_ADDR_LOW 0x2414
97 #define MVNETA_MAC_ADDR_HIGH 0x2418
98 #define MVNETA_SDMA_CONFIG 0x241c
99 #define MVNETA_SDMA_BRST_SIZE_16 4
100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
101 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
102 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
103 #define MVNETA_DESC_SWAP BIT(6)
104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
105 #define MVNETA_PORT_STATUS 0x2444
106 #define MVNETA_TX_IN_PRGRS BIT(0)
107 #define MVNETA_TX_FIFO_EMPTY BIT(8)
108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
109 /* Only exists on Armada XP and Armada 370 */
110 #define MVNETA_SERDES_CFG 0x24A0
111 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
112 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
113 #define MVNETA_HSGMII_SERDES_PROTO 0x1107
114 #define MVNETA_TYPE_PRIO 0x24bc
115 #define MVNETA_FORCE_UNI BIT(21)
116 #define MVNETA_TXQ_CMD_1 0x24e4
117 #define MVNETA_TXQ_CMD 0x2448
118 #define MVNETA_TXQ_DISABLE_SHIFT 8
119 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
120 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
121 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
122 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
123 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
124 #define MVNETA_ACC_MODE 0x2500
125 #define MVNETA_BM_ADDRESS 0x2504
126 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
127 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
128 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
129 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
130 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
131 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
133 /* Exception Interrupt Port/Queue Cause register
135 * Their behavior depend of the mapping done using the PCPX2Q
136 * registers. For a given CPU if the bit associated to a queue is not
137 * set, then for the register a read from this CPU will always return
138 * 0 and a write won't do anything
141 #define MVNETA_INTR_NEW_CAUSE 0x25a0
142 #define MVNETA_INTR_NEW_MASK 0x25a4
144 /* bits 0..7 = TXQ SENT, one bit per queue.
145 * bits 8..15 = RXQ OCCUP, one bit per queue.
146 * bits 16..23 = RXQ FREE, one bit per queue.
147 * bit 29 = OLD_REG_SUM, see old reg ?
148 * bit 30 = TX_ERR_SUM, one bit for 4 ports
149 * bit 31 = MISC_SUM, one bit for 4 ports
151 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
152 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
153 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
154 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
155 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
157 #define MVNETA_INTR_OLD_CAUSE 0x25a8
158 #define MVNETA_INTR_OLD_MASK 0x25ac
160 /* Data Path Port/Queue Cause Register */
161 #define MVNETA_INTR_MISC_CAUSE 0x25b0
162 #define MVNETA_INTR_MISC_MASK 0x25b4
164 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
165 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
166 #define MVNETA_CAUSE_PTP BIT(4)
168 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
169 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
170 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
171 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
172 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
173 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
174 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
175 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
178 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
179 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
181 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
182 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
183 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
185 #define MVNETA_INTR_ENABLE 0x25b8
186 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
187 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
189 #define MVNETA_RXQ_CMD 0x2680
190 #define MVNETA_RXQ_DISABLE_SHIFT 8
191 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
192 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
193 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
194 #define MVNETA_GMAC_CTRL_0 0x2c00
195 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
196 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
197 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
198 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
199 #define MVNETA_GMAC_CTRL_2 0x2c08
200 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
201 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
202 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
203 #define MVNETA_GMAC2_PORT_RESET BIT(6)
204 #define MVNETA_GMAC_STATUS 0x2c10
205 #define MVNETA_GMAC_LINK_UP BIT(0)
206 #define MVNETA_GMAC_SPEED_1000 BIT(1)
207 #define MVNETA_GMAC_SPEED_100 BIT(2)
208 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
209 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
210 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
211 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
212 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
213 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
214 #define MVNETA_GMAC_SYNC_OK BIT(14)
215 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
216 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
217 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
218 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
219 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
220 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
221 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
222 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
223 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
224 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
225 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
226 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
227 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
228 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
229 #define MVNETA_GMAC_CTRL_4 0x2c90
230 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
231 #define MVNETA_MIB_COUNTERS_BASE 0x3000
232 #define MVNETA_MIB_LATE_COLLISION 0x7c
233 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
234 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
235 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
236 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
237 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
238 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
239 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
240 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
241 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
242 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
243 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
244 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
245 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
246 #define MVNETA_PORT_TX_RESET 0x3cf0
247 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
248 #define MVNETA_TX_MTU 0x3e0c
249 #define MVNETA_TX_TOKEN_SIZE 0x3e14
250 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
251 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
252 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
254 #define MVNETA_LPI_CTRL_0 0x2cc0
255 #define MVNETA_LPI_CTRL_1 0x2cc4
256 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
257 #define MVNETA_LPI_CTRL_2 0x2cc8
258 #define MVNETA_LPI_STATUS 0x2ccc
260 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
262 /* Descriptor ring Macros */
263 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
264 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
266 /* Various constants */
269 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
270 #define MVNETA_RX_COAL_PKTS 32
271 #define MVNETA_RX_COAL_USEC 100
273 /* The two bytes Marvell header. Either contains a special value used
274 * by Marvell switches when a specific hardware mode is enabled (not
275 * supported by this driver) or is filled automatically by zeroes on
276 * the RX side. Those two bytes being at the front of the Ethernet
277 * header, they allow to have the IP header aligned on a 4 bytes
278 * boundary automatically: the hardware skips those two bytes on its
281 #define MVNETA_MH_SIZE 2
283 #define MVNETA_VLAN_TAG_LEN 4
285 #define MVNETA_TX_CSUM_DEF_SIZE 1600
286 #define MVNETA_TX_CSUM_MAX_SIZE 9800
287 #define MVNETA_ACC_MODE_EXT1 1
288 #define MVNETA_ACC_MODE_EXT2 2
290 #define MVNETA_MAX_DECODE_WIN 6
292 /* Timeout constants */
293 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
294 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
295 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
297 #define MVNETA_TX_MTU_MAX 0x3ffff
299 /* The RSS lookup table actually has 256 entries but we do not use
302 #define MVNETA_RSS_LU_TABLE_SIZE 1
304 /* Max number of Rx descriptors */
305 #define MVNETA_MAX_RXD 512
307 /* Max number of Tx descriptors */
308 #define MVNETA_MAX_TXD 1024
310 /* Max number of allowed TCP segments for software TSO */
311 #define MVNETA_MAX_TSO_SEGS 100
313 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
315 /* descriptor aligned size */
316 #define MVNETA_DESC_ALIGNED_SIZE 32
318 /* Number of bytes to be taken into account by HW when putting incoming data
319 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
320 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
322 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
324 #define MVNETA_RX_PKT_SIZE(mtu) \
325 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
326 ETH_HLEN + ETH_FCS_LEN, \
329 /* Driver assumes that the last 3 bits are 0 */
330 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)
331 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
332 MVNETA_SKB_HEADROOM))
333 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
335 #define IS_TSO_HEADER(txq, addr) \
336 ((addr >= txq->tso_hdrs_phys) && \
337 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
339 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
340 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
343 ETHTOOL_STAT_EEE_WAKEUP
,
344 ETHTOOL_STAT_SKB_ALLOC_ERR
,
345 ETHTOOL_STAT_REFILL_ERR
,
346 ETHTOOL_XDP_REDIRECT
,
352 ETHTOOL_XDP_XMIT_ERR
,
356 struct mvneta_statistic
{
357 unsigned short offset
;
359 const char name
[ETH_GSTRING_LEN
];
366 #define MVNETA_XDP_PASS 0
367 #define MVNETA_XDP_DROPPED BIT(0)
368 #define MVNETA_XDP_TX BIT(1)
369 #define MVNETA_XDP_REDIR BIT(2)
371 static const struct mvneta_statistic mvneta_statistics
[] = {
372 { 0x3000, T_REG_64
, "good_octets_received", },
373 { 0x3010, T_REG_32
, "good_frames_received", },
374 { 0x3008, T_REG_32
, "bad_octets_received", },
375 { 0x3014, T_REG_32
, "bad_frames_received", },
376 { 0x3018, T_REG_32
, "broadcast_frames_received", },
377 { 0x301c, T_REG_32
, "multicast_frames_received", },
378 { 0x3050, T_REG_32
, "unrec_mac_control_received", },
379 { 0x3058, T_REG_32
, "good_fc_received", },
380 { 0x305c, T_REG_32
, "bad_fc_received", },
381 { 0x3060, T_REG_32
, "undersize_received", },
382 { 0x3064, T_REG_32
, "fragments_received", },
383 { 0x3068, T_REG_32
, "oversize_received", },
384 { 0x306c, T_REG_32
, "jabber_received", },
385 { 0x3070, T_REG_32
, "mac_receive_error", },
386 { 0x3074, T_REG_32
, "bad_crc_event", },
387 { 0x3078, T_REG_32
, "collision", },
388 { 0x307c, T_REG_32
, "late_collision", },
389 { 0x2484, T_REG_32
, "rx_discard", },
390 { 0x2488, T_REG_32
, "rx_overrun", },
391 { 0x3020, T_REG_32
, "frames_64_octets", },
392 { 0x3024, T_REG_32
, "frames_65_to_127_octets", },
393 { 0x3028, T_REG_32
, "frames_128_to_255_octets", },
394 { 0x302c, T_REG_32
, "frames_256_to_511_octets", },
395 { 0x3030, T_REG_32
, "frames_512_to_1023_octets", },
396 { 0x3034, T_REG_32
, "frames_1024_to_max_octets", },
397 { 0x3038, T_REG_64
, "good_octets_sent", },
398 { 0x3040, T_REG_32
, "good_frames_sent", },
399 { 0x3044, T_REG_32
, "excessive_collision", },
400 { 0x3048, T_REG_32
, "multicast_frames_sent", },
401 { 0x304c, T_REG_32
, "broadcast_frames_sent", },
402 { 0x3054, T_REG_32
, "fc_sent", },
403 { 0x300c, T_REG_32
, "internal_mac_transmit_err", },
404 { ETHTOOL_STAT_EEE_WAKEUP
, T_SW
, "eee_wakeup_errors", },
405 { ETHTOOL_STAT_SKB_ALLOC_ERR
, T_SW
, "skb_alloc_errors", },
406 { ETHTOOL_STAT_REFILL_ERR
, T_SW
, "refill_errors", },
407 { ETHTOOL_XDP_REDIRECT
, T_SW
, "rx_xdp_redirect", },
408 { ETHTOOL_XDP_PASS
, T_SW
, "rx_xdp_pass", },
409 { ETHTOOL_XDP_DROP
, T_SW
, "rx_xdp_drop", },
410 { ETHTOOL_XDP_TX
, T_SW
, "rx_xdp_tx", },
411 { ETHTOOL_XDP_TX_ERR
, T_SW
, "rx_xdp_tx_errors", },
412 { ETHTOOL_XDP_XMIT
, T_SW
, "tx_xdp_xmit", },
413 { ETHTOOL_XDP_XMIT_ERR
, T_SW
, "tx_xdp_xmit_errors", },
416 struct mvneta_stats
{
431 struct mvneta_ethtool_stats
{
432 struct mvneta_stats ps
;
437 struct mvneta_pcpu_stats
{
438 struct u64_stats_sync syncp
;
440 struct mvneta_ethtool_stats es
;
445 struct mvneta_pcpu_port
{
446 /* Pointer to the shared port */
447 struct mvneta_port
*pp
;
449 /* Pointer to the CPU-local NAPI struct */
450 struct napi_struct napi
;
452 /* Cause of the previous interrupt */
462 struct mvneta_pcpu_port __percpu
*ports
;
463 struct mvneta_pcpu_stats __percpu
*stats
;
469 struct mvneta_rx_queue
*rxqs
;
470 struct mvneta_tx_queue
*txqs
;
471 struct net_device
*dev
;
472 struct hlist_node node_online
;
473 struct hlist_node node_dead
;
475 /* Protect the access to the percpu interrupt registers,
476 * ensuring that the configuration remains coherent.
482 struct napi_struct napi
;
484 struct bpf_prog
*xdp_prog
;
494 phy_interface_t phy_interface
;
495 struct device_node
*dn
;
496 unsigned int tx_csum_limit
;
497 struct phylink
*phylink
;
498 struct phylink_config phylink_config
;
501 struct mvneta_bm
*bm_priv
;
502 struct mvneta_bm_pool
*pool_long
;
503 struct mvneta_bm_pool
*pool_short
;
510 u64 ethtool_stats
[ARRAY_SIZE(mvneta_statistics
)];
512 u32 indir
[MVNETA_RSS_LU_TABLE_SIZE
];
514 /* Flags for special SoC configurations */
515 bool neta_armada3700
;
516 u16 rx_offset_correction
;
517 const struct mbus_dram_target_info
*dram_target_info
;
520 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
521 * layout of the transmit and reception DMA descriptors, and their
522 * layout is therefore defined by the hardware design
525 #define MVNETA_TX_L3_OFF_SHIFT 0
526 #define MVNETA_TX_IP_HLEN_SHIFT 8
527 #define MVNETA_TX_L4_UDP BIT(16)
528 #define MVNETA_TX_L3_IP6 BIT(17)
529 #define MVNETA_TXD_IP_CSUM BIT(18)
530 #define MVNETA_TXD_Z_PAD BIT(19)
531 #define MVNETA_TXD_L_DESC BIT(20)
532 #define MVNETA_TXD_F_DESC BIT(21)
533 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
534 MVNETA_TXD_L_DESC | \
536 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
537 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
539 #define MVNETA_RXD_ERR_CRC 0x0
540 #define MVNETA_RXD_BM_POOL_SHIFT 13
541 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
542 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
543 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
544 #define MVNETA_RXD_ERR_LEN BIT(18)
545 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
546 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
547 #define MVNETA_RXD_L3_IP4 BIT(25)
548 #define MVNETA_RXD_LAST_DESC BIT(26)
549 #define MVNETA_RXD_FIRST_DESC BIT(27)
550 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
551 MVNETA_RXD_LAST_DESC)
552 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
554 #if defined(__LITTLE_ENDIAN)
555 struct mvneta_tx_desc
{
556 u32 command
; /* Options used by HW for packet transmitting.*/
557 u16 reserved1
; /* csum_l4 (for future use) */
558 u16 data_size
; /* Data size of transmitted packet in bytes */
559 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
560 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
561 u32 reserved3
[4]; /* Reserved - (for future use) */
564 struct mvneta_rx_desc
{
565 u32 status
; /* Info about received packet */
566 u16 reserved1
; /* pnc_info - (for future use, PnC) */
567 u16 data_size
; /* Size of received packet in bytes */
569 u32 buf_phys_addr
; /* Physical address of the buffer */
570 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
572 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
573 u16 reserved3
; /* prefetch_cmd, for future use */
574 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
576 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
577 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
580 struct mvneta_tx_desc
{
581 u16 data_size
; /* Data size of transmitted packet in bytes */
582 u16 reserved1
; /* csum_l4 (for future use) */
583 u32 command
; /* Options used by HW for packet transmitting.*/
584 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
585 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
586 u32 reserved3
[4]; /* Reserved - (for future use) */
589 struct mvneta_rx_desc
{
590 u16 data_size
; /* Size of received packet in bytes */
591 u16 reserved1
; /* pnc_info - (for future use, PnC) */
592 u32 status
; /* Info about received packet */
594 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
595 u32 buf_phys_addr
; /* Physical address of the buffer */
597 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
598 u16 reserved3
; /* prefetch_cmd, for future use */
599 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
601 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
602 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
606 enum mvneta_tx_buf_type
{
612 struct mvneta_tx_buf
{
613 enum mvneta_tx_buf_type type
;
615 struct xdp_frame
*xdpf
;
620 struct mvneta_tx_queue
{
621 /* Number of this TX queue, in the range 0-7 */
624 /* Number of TX DMA descriptors in the descriptor ring */
627 /* Number of currently used TX DMA descriptor in the
632 int tx_stop_threshold
;
633 int tx_wake_threshold
;
635 /* Array of transmitted buffers */
636 struct mvneta_tx_buf
*buf
;
638 /* Index of last TX DMA descriptor that was inserted */
641 /* Index of the TX DMA descriptor to be cleaned up */
646 /* Virtual address of the TX DMA descriptors array */
647 struct mvneta_tx_desc
*descs
;
649 /* DMA address of the TX DMA descriptors array */
650 dma_addr_t descs_phys
;
652 /* Index of the last TX DMA descriptor */
655 /* Index of the next TX DMA descriptor to process */
656 int next_desc_to_proc
;
658 /* DMA buffers for TSO headers */
661 /* DMA address of TSO headers */
662 dma_addr_t tso_hdrs_phys
;
664 /* Affinity mask for CPUs*/
665 cpumask_t affinity_mask
;
668 struct mvneta_rx_queue
{
669 /* rx queue number, in the range 0-7 */
672 /* num of rx descriptors in the rx descriptor ring */
679 struct page_pool
*page_pool
;
680 struct xdp_rxq_info xdp_rxq
;
682 /* Virtual address of the RX buffer */
683 void **buf_virt_addr
;
685 /* Virtual address of the RX DMA descriptors array */
686 struct mvneta_rx_desc
*descs
;
688 /* DMA address of the RX DMA descriptors array */
689 dma_addr_t descs_phys
;
691 /* Index of the last RX DMA descriptor */
694 /* Index of the next RX DMA descriptor to process */
695 int next_desc_to_proc
;
697 /* Index of first RX DMA descriptor to refill */
702 static enum cpuhp_state online_hpstate
;
703 /* The hardware supports eight (8) rx queues, but we are only allowing
704 * the first one to be used. Therefore, let's just allocate one queue.
706 static int rxq_number
= 8;
707 static int txq_number
= 8;
711 static int rx_copybreak __read_mostly
= 256;
713 /* HW BM need that each port be identify by a unique ID */
714 static int global_port_id
;
716 #define MVNETA_DRIVER_NAME "mvneta"
717 #define MVNETA_DRIVER_VERSION "1.0"
719 /* Utility/helper methods */
721 /* Write helper method */
722 static void mvreg_write(struct mvneta_port
*pp
, u32 offset
, u32 data
)
724 writel(data
, pp
->base
+ offset
);
727 /* Read helper method */
728 static u32
mvreg_read(struct mvneta_port
*pp
, u32 offset
)
730 return readl(pp
->base
+ offset
);
733 /* Increment txq get counter */
734 static void mvneta_txq_inc_get(struct mvneta_tx_queue
*txq
)
736 txq
->txq_get_index
++;
737 if (txq
->txq_get_index
== txq
->size
)
738 txq
->txq_get_index
= 0;
741 /* Increment txq put counter */
742 static void mvneta_txq_inc_put(struct mvneta_tx_queue
*txq
)
744 txq
->txq_put_index
++;
745 if (txq
->txq_put_index
== txq
->size
)
746 txq
->txq_put_index
= 0;
750 /* Clear all MIB counters */
751 static void mvneta_mib_counters_clear(struct mvneta_port
*pp
)
755 /* Perform dummy reads from MIB counters */
756 for (i
= 0; i
< MVNETA_MIB_LATE_COLLISION
; i
+= 4)
757 mvreg_read(pp
, (MVNETA_MIB_COUNTERS_BASE
+ i
));
758 mvreg_read(pp
, MVNETA_RX_DISCARD_FRAME_COUNT
);
759 mvreg_read(pp
, MVNETA_OVERRUN_FRAME_COUNT
);
762 /* Get System Network Statistics */
764 mvneta_get_stats64(struct net_device
*dev
,
765 struct rtnl_link_stats64
*stats
)
767 struct mvneta_port
*pp
= netdev_priv(dev
);
771 for_each_possible_cpu(cpu
) {
772 struct mvneta_pcpu_stats
*cpu_stats
;
780 cpu_stats
= per_cpu_ptr(pp
->stats
, cpu
);
782 start
= u64_stats_fetch_begin_irq(&cpu_stats
->syncp
);
783 rx_packets
= cpu_stats
->es
.ps
.rx_packets
;
784 rx_bytes
= cpu_stats
->es
.ps
.rx_bytes
;
785 rx_dropped
= cpu_stats
->rx_dropped
;
786 rx_errors
= cpu_stats
->rx_errors
;
787 tx_packets
= cpu_stats
->es
.ps
.tx_packets
;
788 tx_bytes
= cpu_stats
->es
.ps
.tx_bytes
;
789 } while (u64_stats_fetch_retry_irq(&cpu_stats
->syncp
, start
));
791 stats
->rx_packets
+= rx_packets
;
792 stats
->rx_bytes
+= rx_bytes
;
793 stats
->rx_dropped
+= rx_dropped
;
794 stats
->rx_errors
+= rx_errors
;
795 stats
->tx_packets
+= tx_packets
;
796 stats
->tx_bytes
+= tx_bytes
;
799 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
802 /* Rx descriptors helper methods */
804 /* Checks whether the RX descriptor having this status is both the first
805 * and the last descriptor for the RX packet. Each RX packet is currently
806 * received through a single RX descriptor, so not having each RX
807 * descriptor with its first and last bits set is an error
809 static int mvneta_rxq_desc_is_first_last(u32 status
)
811 return (status
& MVNETA_RXD_FIRST_LAST_DESC
) ==
812 MVNETA_RXD_FIRST_LAST_DESC
;
815 /* Add number of descriptors ready to receive new packets */
816 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port
*pp
,
817 struct mvneta_rx_queue
*rxq
,
820 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
823 while (ndescs
> MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
) {
824 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
825 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
<<
826 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
827 ndescs
-= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
;
830 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
831 (ndescs
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
834 /* Get number of RX descriptors occupied by received packets */
835 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port
*pp
,
836 struct mvneta_rx_queue
*rxq
)
840 val
= mvreg_read(pp
, MVNETA_RXQ_STATUS_REG(rxq
->id
));
841 return val
& MVNETA_RXQ_OCCUPIED_ALL_MASK
;
844 /* Update num of rx desc called upon return from rx path or
845 * from mvneta_rxq_drop_pkts().
847 static void mvneta_rxq_desc_num_update(struct mvneta_port
*pp
,
848 struct mvneta_rx_queue
*rxq
,
849 int rx_done
, int rx_filled
)
853 if ((rx_done
<= 0xff) && (rx_filled
<= 0xff)) {
855 (rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
);
856 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
860 /* Only 255 descriptors can be added at once */
861 while ((rx_done
> 0) || (rx_filled
> 0)) {
862 if (rx_done
<= 0xff) {
869 if (rx_filled
<= 0xff) {
870 val
|= rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
873 val
|= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
876 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
880 /* Get pointer to next RX descriptor to be processed by SW */
881 static struct mvneta_rx_desc
*
882 mvneta_rxq_next_desc_get(struct mvneta_rx_queue
*rxq
)
884 int rx_desc
= rxq
->next_desc_to_proc
;
886 rxq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(rxq
, rx_desc
);
887 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
888 return rxq
->descs
+ rx_desc
;
891 /* Change maximum receive size of the port. */
892 static void mvneta_max_rx_size_set(struct mvneta_port
*pp
, int max_rx_size
)
896 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
897 val
&= ~MVNETA_GMAC_MAX_RX_SIZE_MASK
;
898 val
|= ((max_rx_size
- MVNETA_MH_SIZE
) / 2) <<
899 MVNETA_GMAC_MAX_RX_SIZE_SHIFT
;
900 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
904 /* Set rx queue offset */
905 static void mvneta_rxq_offset_set(struct mvneta_port
*pp
,
906 struct mvneta_rx_queue
*rxq
,
911 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
912 val
&= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK
;
915 val
|= MVNETA_RXQ_PKT_OFFSET_MASK(offset
>> 3);
916 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
920 /* Tx descriptors helper methods */
922 /* Update HW with number of TX descriptors to be sent */
923 static void mvneta_txq_pend_desc_add(struct mvneta_port
*pp
,
924 struct mvneta_tx_queue
*txq
,
929 pend_desc
+= txq
->pending
;
931 /* Only 255 Tx descriptors can be added at once */
933 val
= min(pend_desc
, 255);
934 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
936 } while (pend_desc
> 0);
940 /* Get pointer to next TX descriptor to be processed (send) by HW */
941 static struct mvneta_tx_desc
*
942 mvneta_txq_next_desc_get(struct mvneta_tx_queue
*txq
)
944 int tx_desc
= txq
->next_desc_to_proc
;
946 txq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(txq
, tx_desc
);
947 return txq
->descs
+ tx_desc
;
950 /* Release the last allocated TX descriptor. Useful to handle DMA
951 * mapping failures in the TX path.
953 static void mvneta_txq_desc_put(struct mvneta_tx_queue
*txq
)
955 if (txq
->next_desc_to_proc
== 0)
956 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
958 txq
->next_desc_to_proc
--;
961 /* Set rxq buf size */
962 static void mvneta_rxq_buf_size_set(struct mvneta_port
*pp
,
963 struct mvneta_rx_queue
*rxq
,
968 val
= mvreg_read(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
));
970 val
&= ~MVNETA_RXQ_BUF_SIZE_MASK
;
971 val
|= ((buf_size
>> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT
);
973 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), val
);
976 /* Disable buffer management (BM) */
977 static void mvneta_rxq_bm_disable(struct mvneta_port
*pp
,
978 struct mvneta_rx_queue
*rxq
)
982 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
983 val
&= ~MVNETA_RXQ_HW_BUF_ALLOC
;
984 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
987 /* Enable buffer management (BM) */
988 static void mvneta_rxq_bm_enable(struct mvneta_port
*pp
,
989 struct mvneta_rx_queue
*rxq
)
993 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
994 val
|= MVNETA_RXQ_HW_BUF_ALLOC
;
995 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
998 /* Notify HW about port's assignment of pool for bigger packets */
999 static void mvneta_rxq_long_pool_set(struct mvneta_port
*pp
,
1000 struct mvneta_rx_queue
*rxq
)
1004 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
1005 val
&= ~MVNETA_RXQ_LONG_POOL_ID_MASK
;
1006 val
|= (pp
->pool_long
->id
<< MVNETA_RXQ_LONG_POOL_ID_SHIFT
);
1008 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
1011 /* Notify HW about port's assignment of pool for smaller packets */
1012 static void mvneta_rxq_short_pool_set(struct mvneta_port
*pp
,
1013 struct mvneta_rx_queue
*rxq
)
1017 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
1018 val
&= ~MVNETA_RXQ_SHORT_POOL_ID_MASK
;
1019 val
|= (pp
->pool_short
->id
<< MVNETA_RXQ_SHORT_POOL_ID_SHIFT
);
1021 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
1024 /* Set port's receive buffer size for assigned BM pool */
1025 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port
*pp
,
1031 if (!IS_ALIGNED(buf_size
, 8)) {
1032 dev_warn(pp
->dev
->dev
.parent
,
1033 "illegal buf_size value %d, round to %d\n",
1034 buf_size
, ALIGN(buf_size
, 8));
1035 buf_size
= ALIGN(buf_size
, 8);
1038 val
= mvreg_read(pp
, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id
));
1039 val
|= buf_size
& MVNETA_PORT_POOL_BUFFER_SZ_MASK
;
1040 mvreg_write(pp
, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id
), val
);
1043 /* Configure MBUS window in order to enable access BM internal SRAM */
1044 static int mvneta_mbus_io_win_set(struct mvneta_port
*pp
, u32 base
, u32 wsize
,
1047 u32 win_enable
, win_protect
;
1050 win_enable
= mvreg_read(pp
, MVNETA_BASE_ADDR_ENABLE
);
1052 if (pp
->bm_win_id
< 0) {
1053 /* Find first not occupied window */
1054 for (i
= 0; i
< MVNETA_MAX_DECODE_WIN
; i
++) {
1055 if (win_enable
& (1 << i
)) {
1060 if (i
== MVNETA_MAX_DECODE_WIN
)
1066 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
1067 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
1070 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
1072 mvreg_write(pp
, MVNETA_WIN_BASE(i
), (base
& 0xffff0000) |
1073 (attr
<< 8) | target
);
1075 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), (wsize
- 1) & 0xffff0000);
1077 win_protect
= mvreg_read(pp
, MVNETA_ACCESS_PROTECT_ENABLE
);
1078 win_protect
|= 3 << (2 * i
);
1079 mvreg_write(pp
, MVNETA_ACCESS_PROTECT_ENABLE
, win_protect
);
1081 win_enable
&= ~(1 << i
);
1082 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
1087 static int mvneta_bm_port_mbus_init(struct mvneta_port
*pp
)
1093 /* Get BM window information */
1094 err
= mvebu_mbus_get_io_win_info(pp
->bm_priv
->bppi_phys_addr
, &wsize
,
1101 /* Open NETA -> BM window */
1102 err
= mvneta_mbus_io_win_set(pp
, pp
->bm_priv
->bppi_phys_addr
, wsize
,
1105 netdev_info(pp
->dev
, "fail to configure mbus window to BM\n");
1111 /* Assign and initialize pools for port. In case of fail
1112 * buffer manager will remain disabled for current port.
1114 static int mvneta_bm_port_init(struct platform_device
*pdev
,
1115 struct mvneta_port
*pp
)
1117 struct device_node
*dn
= pdev
->dev
.of_node
;
1118 u32 long_pool_id
, short_pool_id
;
1120 if (!pp
->neta_armada3700
) {
1123 ret
= mvneta_bm_port_mbus_init(pp
);
1128 if (of_property_read_u32(dn
, "bm,pool-long", &long_pool_id
)) {
1129 netdev_info(pp
->dev
, "missing long pool id\n");
1133 /* Create port's long pool depending on mtu */
1134 pp
->pool_long
= mvneta_bm_pool_use(pp
->bm_priv
, long_pool_id
,
1135 MVNETA_BM_LONG
, pp
->id
,
1136 MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
));
1137 if (!pp
->pool_long
) {
1138 netdev_info(pp
->dev
, "fail to obtain long pool for port\n");
1142 pp
->pool_long
->port_map
|= 1 << pp
->id
;
1144 mvneta_bm_pool_bufsize_set(pp
, pp
->pool_long
->buf_size
,
1147 /* If short pool id is not defined, assume using single pool */
1148 if (of_property_read_u32(dn
, "bm,pool-short", &short_pool_id
))
1149 short_pool_id
= long_pool_id
;
1151 /* Create port's short pool */
1152 pp
->pool_short
= mvneta_bm_pool_use(pp
->bm_priv
, short_pool_id
,
1153 MVNETA_BM_SHORT
, pp
->id
,
1154 MVNETA_BM_SHORT_PKT_SIZE
);
1155 if (!pp
->pool_short
) {
1156 netdev_info(pp
->dev
, "fail to obtain short pool for port\n");
1157 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
1161 if (short_pool_id
!= long_pool_id
) {
1162 pp
->pool_short
->port_map
|= 1 << pp
->id
;
1163 mvneta_bm_pool_bufsize_set(pp
, pp
->pool_short
->buf_size
,
1164 pp
->pool_short
->id
);
1170 /* Update settings of a pool for bigger packets */
1171 static void mvneta_bm_update_mtu(struct mvneta_port
*pp
, int mtu
)
1173 struct mvneta_bm_pool
*bm_pool
= pp
->pool_long
;
1174 struct hwbm_pool
*hwbm_pool
= &bm_pool
->hwbm_pool
;
1177 /* Release all buffers from long pool */
1178 mvneta_bm_bufs_free(pp
->bm_priv
, bm_pool
, 1 << pp
->id
);
1179 if (hwbm_pool
->buf_num
) {
1180 WARN(1, "cannot free all buffers in pool %d\n",
1185 bm_pool
->pkt_size
= MVNETA_RX_PKT_SIZE(mtu
);
1186 bm_pool
->buf_size
= MVNETA_RX_BUF_SIZE(bm_pool
->pkt_size
);
1187 hwbm_pool
->frag_size
= SKB_DATA_ALIGN(sizeof(struct skb_shared_info
)) +
1188 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool
->pkt_size
));
1190 /* Fill entire long pool */
1191 num
= hwbm_pool_add(hwbm_pool
, hwbm_pool
->size
);
1192 if (num
!= hwbm_pool
->size
) {
1193 WARN(1, "pool %d: %d of %d allocated\n",
1194 bm_pool
->id
, num
, hwbm_pool
->size
);
1197 mvneta_bm_pool_bufsize_set(pp
, bm_pool
->buf_size
, bm_pool
->id
);
1202 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
1203 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
, 1 << pp
->id
);
1206 pp
->rx_offset_correction
= MVNETA_SKB_HEADROOM
;
1207 mvreg_write(pp
, MVNETA_ACC_MODE
, MVNETA_ACC_MODE_EXT1
);
1208 netdev_info(pp
->dev
, "fail to update MTU, fall back to software BM\n");
1211 /* Start the Ethernet port RX and TX activity */
1212 static void mvneta_port_up(struct mvneta_port
*pp
)
1217 /* Enable all initialized TXs. */
1219 for (queue
= 0; queue
< txq_number
; queue
++) {
1220 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
1222 q_map
|= (1 << queue
);
1224 mvreg_write(pp
, MVNETA_TXQ_CMD
, q_map
);
1227 /* Enable all initialized RXQs. */
1228 for (queue
= 0; queue
< rxq_number
; queue
++) {
1229 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
1232 q_map
|= (1 << queue
);
1234 mvreg_write(pp
, MVNETA_RXQ_CMD
, q_map
);
1237 /* Stop the Ethernet port activity */
1238 static void mvneta_port_down(struct mvneta_port
*pp
)
1243 /* Stop Rx port activity. Check port Rx activity. */
1244 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
) & MVNETA_RXQ_ENABLE_MASK
;
1246 /* Issue stop command for active channels only */
1248 mvreg_write(pp
, MVNETA_RXQ_CMD
,
1249 val
<< MVNETA_RXQ_DISABLE_SHIFT
);
1251 /* Wait for all Rx activity to terminate. */
1254 if (count
++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC
) {
1255 netdev_warn(pp
->dev
,
1256 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1262 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
);
1263 } while (val
& MVNETA_RXQ_ENABLE_MASK
);
1265 /* Stop Tx port activity. Check port Tx activity. Issue stop
1266 * command for active channels only
1268 val
= (mvreg_read(pp
, MVNETA_TXQ_CMD
)) & MVNETA_TXQ_ENABLE_MASK
;
1271 mvreg_write(pp
, MVNETA_TXQ_CMD
,
1272 (val
<< MVNETA_TXQ_DISABLE_SHIFT
));
1274 /* Wait for all Tx activity to terminate. */
1277 if (count
++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC
) {
1278 netdev_warn(pp
->dev
,
1279 "TIMEOUT for TX stopped status=0x%08x\n",
1285 /* Check TX Command reg that all Txqs are stopped */
1286 val
= mvreg_read(pp
, MVNETA_TXQ_CMD
);
1288 } while (val
& MVNETA_TXQ_ENABLE_MASK
);
1290 /* Double check to verify that TX FIFO is empty */
1293 if (count
++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT
) {
1294 netdev_warn(pp
->dev
,
1295 "TX FIFO empty timeout status=0x%08x\n",
1301 val
= mvreg_read(pp
, MVNETA_PORT_STATUS
);
1302 } while (!(val
& MVNETA_TX_FIFO_EMPTY
) &&
1303 (val
& MVNETA_TX_IN_PRGRS
));
1308 /* Enable the port by setting the port enable bit of the MAC control register */
1309 static void mvneta_port_enable(struct mvneta_port
*pp
)
1314 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
1315 val
|= MVNETA_GMAC0_PORT_ENABLE
;
1316 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
1319 /* Disable the port and wait for about 200 usec before retuning */
1320 static void mvneta_port_disable(struct mvneta_port
*pp
)
1324 /* Reset the Enable bit in the Serial Control Register */
1325 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
1326 val
&= ~MVNETA_GMAC0_PORT_ENABLE
;
1327 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
1332 /* Multicast tables methods */
1334 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1335 static void mvneta_set_ucast_table(struct mvneta_port
*pp
, int queue
)
1343 val
= 0x1 | (queue
<< 1);
1344 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1347 for (offset
= 0; offset
<= 0xc; offset
+= 4)
1348 mvreg_write(pp
, MVNETA_DA_FILT_UCAST_BASE
+ offset
, val
);
1351 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1352 static void mvneta_set_special_mcast_table(struct mvneta_port
*pp
, int queue
)
1360 val
= 0x1 | (queue
<< 1);
1361 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1364 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
1365 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ offset
, val
);
1369 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1370 static void mvneta_set_other_mcast_table(struct mvneta_port
*pp
, int queue
)
1376 memset(pp
->mcast_count
, 0, sizeof(pp
->mcast_count
));
1379 memset(pp
->mcast_count
, 1, sizeof(pp
->mcast_count
));
1380 val
= 0x1 | (queue
<< 1);
1381 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1384 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
1385 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ offset
, val
);
1388 static void mvneta_percpu_unmask_interrupt(void *arg
)
1390 struct mvneta_port
*pp
= arg
;
1392 /* All the queue are unmasked, but actually only the ones
1393 * mapped to this CPU will be unmasked
1395 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
1396 MVNETA_RX_INTR_MASK_ALL
|
1397 MVNETA_TX_INTR_MASK_ALL
|
1398 MVNETA_MISCINTR_INTR_MASK
);
1401 static void mvneta_percpu_mask_interrupt(void *arg
)
1403 struct mvneta_port
*pp
= arg
;
1405 /* All the queue are masked, but actually only the ones
1406 * mapped to this CPU will be masked
1408 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
1409 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
1410 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
1413 static void mvneta_percpu_clear_intr_cause(void *arg
)
1415 struct mvneta_port
*pp
= arg
;
1417 /* All the queue are cleared, but actually only the ones
1418 * mapped to this CPU will be cleared
1420 mvreg_write(pp
, MVNETA_INTR_NEW_CAUSE
, 0);
1421 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
1422 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
1425 /* This method sets defaults to the NETA port:
1426 * Clears interrupt Cause and Mask registers.
1427 * Clears all MAC tables.
1428 * Sets defaults to all registers.
1429 * Resets RX and TX descriptor rings.
1431 * This method can be called after mvneta_port_down() to return the port
1432 * settings to defaults.
1434 static void mvneta_defaults_set(struct mvneta_port
*pp
)
1439 int max_cpu
= num_present_cpus();
1441 /* Clear all Cause registers */
1442 on_each_cpu(mvneta_percpu_clear_intr_cause
, pp
, true);
1444 /* Mask all interrupts */
1445 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
1446 mvreg_write(pp
, MVNETA_INTR_ENABLE
, 0);
1448 /* Enable MBUS Retry bit16 */
1449 mvreg_write(pp
, MVNETA_MBUS_RETRY
, 0x20);
1451 /* Set CPU queue access map. CPUs are assigned to the RX and
1452 * TX queues modulo their number. If there is only one TX
1453 * queue then it is assigned to the CPU associated to the
1456 for_each_present_cpu(cpu
) {
1457 int rxq_map
= 0, txq_map
= 0;
1459 if (!pp
->neta_armada3700
) {
1460 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
1461 if ((rxq
% max_cpu
) == cpu
)
1462 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(rxq
);
1464 for (txq
= 0; txq
< txq_number
; txq
++)
1465 if ((txq
% max_cpu
) == cpu
)
1466 txq_map
|= MVNETA_CPU_TXQ_ACCESS(txq
);
1468 /* With only one TX queue we configure a special case
1469 * which will allow to get all the irq on a single
1472 if (txq_number
== 1)
1473 txq_map
= (cpu
== pp
->rxq_def
) ?
1474 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1477 txq_map
= MVNETA_CPU_TXQ_ACCESS_ALL_MASK
;
1478 rxq_map
= MVNETA_CPU_RXQ_ACCESS_ALL_MASK
;
1481 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
), rxq_map
| txq_map
);
1484 /* Reset RX and TX DMAs */
1485 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
1486 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
1488 /* Disable Legacy WRR, Disable EJP, Release from reset */
1489 mvreg_write(pp
, MVNETA_TXQ_CMD_1
, 0);
1490 for (queue
= 0; queue
< txq_number
; queue
++) {
1491 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(queue
), 0);
1492 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(queue
), 0);
1495 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
1496 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
1498 /* Set Port Acceleration Mode */
1500 /* HW buffer management + legacy parser */
1501 val
= MVNETA_ACC_MODE_EXT2
;
1503 /* SW buffer management + legacy parser */
1504 val
= MVNETA_ACC_MODE_EXT1
;
1505 mvreg_write(pp
, MVNETA_ACC_MODE
, val
);
1508 mvreg_write(pp
, MVNETA_BM_ADDRESS
, pp
->bm_priv
->bppi_phys_addr
);
1510 /* Update val of portCfg register accordingly with all RxQueue types */
1511 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(pp
->rxq_def
);
1512 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
1515 mvreg_write(pp
, MVNETA_PORT_CONFIG_EXTEND
, val
);
1516 mvreg_write(pp
, MVNETA_RX_MIN_FRAME_SIZE
, 64);
1518 /* Build PORT_SDMA_CONFIG_REG */
1521 /* Default burst size */
1522 val
|= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
1523 val
|= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
1524 val
|= MVNETA_RX_NO_DATA_SWAP
| MVNETA_TX_NO_DATA_SWAP
;
1526 #if defined(__BIG_ENDIAN)
1527 val
|= MVNETA_DESC_SWAP
;
1530 /* Assign port SDMA configuration */
1531 mvreg_write(pp
, MVNETA_SDMA_CONFIG
, val
);
1533 /* Disable PHY polling in hardware, since we're using the
1534 * kernel phylib to do this.
1536 val
= mvreg_read(pp
, MVNETA_UNIT_CONTROL
);
1537 val
&= ~MVNETA_PHY_POLLING_ENABLE
;
1538 mvreg_write(pp
, MVNETA_UNIT_CONTROL
, val
);
1540 mvneta_set_ucast_table(pp
, -1);
1541 mvneta_set_special_mcast_table(pp
, -1);
1542 mvneta_set_other_mcast_table(pp
, -1);
1544 /* Set port interrupt enable register - default enable all */
1545 mvreg_write(pp
, MVNETA_INTR_ENABLE
,
1546 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1547 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK
));
1549 mvneta_mib_counters_clear(pp
);
1552 /* Set max sizes for tx queues */
1553 static void mvneta_txq_max_tx_size_set(struct mvneta_port
*pp
, int max_tx_size
)
1559 mtu
= max_tx_size
* 8;
1560 if (mtu
> MVNETA_TX_MTU_MAX
)
1561 mtu
= MVNETA_TX_MTU_MAX
;
1564 val
= mvreg_read(pp
, MVNETA_TX_MTU
);
1565 val
&= ~MVNETA_TX_MTU_MAX
;
1567 mvreg_write(pp
, MVNETA_TX_MTU
, val
);
1569 /* TX token size and all TXQs token size must be larger that MTU */
1570 val
= mvreg_read(pp
, MVNETA_TX_TOKEN_SIZE
);
1572 size
= val
& MVNETA_TX_TOKEN_SIZE_MAX
;
1575 val
&= ~MVNETA_TX_TOKEN_SIZE_MAX
;
1577 mvreg_write(pp
, MVNETA_TX_TOKEN_SIZE
, val
);
1579 for (queue
= 0; queue
< txq_number
; queue
++) {
1580 val
= mvreg_read(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
));
1582 size
= val
& MVNETA_TXQ_TOKEN_SIZE_MAX
;
1585 val
&= ~MVNETA_TXQ_TOKEN_SIZE_MAX
;
1587 mvreg_write(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
), val
);
1592 /* Set unicast address */
1593 static void mvneta_set_ucast_addr(struct mvneta_port
*pp
, u8 last_nibble
,
1596 unsigned int unicast_reg
;
1597 unsigned int tbl_offset
;
1598 unsigned int reg_offset
;
1600 /* Locate the Unicast table entry */
1601 last_nibble
= (0xf & last_nibble
);
1603 /* offset from unicast tbl base */
1604 tbl_offset
= (last_nibble
/ 4) * 4;
1606 /* offset within the above reg */
1607 reg_offset
= last_nibble
% 4;
1609 unicast_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
));
1612 /* Clear accepts frame bit at specified unicast DA tbl entry */
1613 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1615 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1616 unicast_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1619 mvreg_write(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
), unicast_reg
);
1622 /* Set mac address */
1623 static void mvneta_mac_addr_set(struct mvneta_port
*pp
, unsigned char *addr
,
1630 mac_l
= (addr
[4] << 8) | (addr
[5]);
1631 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) |
1632 (addr
[2] << 8) | (addr
[3] << 0);
1634 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, mac_l
);
1635 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, mac_h
);
1638 /* Accept frames of this address */
1639 mvneta_set_ucast_addr(pp
, addr
[5], queue
);
1642 /* Set the number of packets that will be received before RX interrupt
1643 * will be generated by HW.
1645 static void mvneta_rx_pkts_coal_set(struct mvneta_port
*pp
,
1646 struct mvneta_rx_queue
*rxq
, u32 value
)
1648 mvreg_write(pp
, MVNETA_RXQ_THRESHOLD_REG(rxq
->id
),
1649 value
| MVNETA_RXQ_NON_OCCUPIED(0));
1652 /* Set the time delay in usec before RX interrupt will be generated by
1655 static void mvneta_rx_time_coal_set(struct mvneta_port
*pp
,
1656 struct mvneta_rx_queue
*rxq
, u32 value
)
1659 unsigned long clk_rate
;
1661 clk_rate
= clk_get_rate(pp
->clk
);
1662 val
= (clk_rate
/ 1000000) * value
;
1664 mvreg_write(pp
, MVNETA_RXQ_TIME_COAL_REG(rxq
->id
), val
);
1667 /* Set threshold for TX_DONE pkts coalescing */
1668 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port
*pp
,
1669 struct mvneta_tx_queue
*txq
, u32 value
)
1673 val
= mvreg_read(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
));
1675 val
&= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK
;
1676 val
|= MVNETA_TXQ_SENT_THRESH_MASK(value
);
1678 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), val
);
1681 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1682 static void mvneta_rx_desc_fill(struct mvneta_rx_desc
*rx_desc
,
1683 u32 phys_addr
, void *virt_addr
,
1684 struct mvneta_rx_queue
*rxq
)
1688 rx_desc
->buf_phys_addr
= phys_addr
;
1689 i
= rx_desc
- rxq
->descs
;
1690 rxq
->buf_virt_addr
[i
] = virt_addr
;
1693 /* Decrement sent descriptors counter */
1694 static void mvneta_txq_sent_desc_dec(struct mvneta_port
*pp
,
1695 struct mvneta_tx_queue
*txq
,
1700 /* Only 255 TX descriptors can be updated at once */
1701 while (sent_desc
> 0xff) {
1702 val
= 0xff << MVNETA_TXQ_DEC_SENT_SHIFT
;
1703 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1704 sent_desc
= sent_desc
- 0xff;
1707 val
= sent_desc
<< MVNETA_TXQ_DEC_SENT_SHIFT
;
1708 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1711 /* Get number of TX descriptors already sent by HW */
1712 static int mvneta_txq_sent_desc_num_get(struct mvneta_port
*pp
,
1713 struct mvneta_tx_queue
*txq
)
1718 val
= mvreg_read(pp
, MVNETA_TXQ_STATUS_REG(txq
->id
));
1719 sent_desc
= (val
& MVNETA_TXQ_SENT_DESC_MASK
) >>
1720 MVNETA_TXQ_SENT_DESC_SHIFT
;
1725 /* Get number of sent descriptors and decrement counter.
1726 * The number of sent descriptors is returned.
1728 static int mvneta_txq_sent_desc_proc(struct mvneta_port
*pp
,
1729 struct mvneta_tx_queue
*txq
)
1733 /* Get number of sent descriptors */
1734 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1736 /* Decrement sent descriptors counter */
1738 mvneta_txq_sent_desc_dec(pp
, txq
, sent_desc
);
1743 /* Set TXQ descriptors fields relevant for CSUM calculation */
1744 static u32
mvneta_txq_desc_csum(int l3_offs
, int l3_proto
,
1745 int ip_hdr_len
, int l4_proto
)
1749 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1750 * G_L4_chk, L4_type; required only for checksum
1753 command
= l3_offs
<< MVNETA_TX_L3_OFF_SHIFT
;
1754 command
|= ip_hdr_len
<< MVNETA_TX_IP_HLEN_SHIFT
;
1756 if (l3_proto
== htons(ETH_P_IP
))
1757 command
|= MVNETA_TXD_IP_CSUM
;
1759 command
|= MVNETA_TX_L3_IP6
;
1761 if (l4_proto
== IPPROTO_TCP
)
1762 command
|= MVNETA_TX_L4_CSUM_FULL
;
1763 else if (l4_proto
== IPPROTO_UDP
)
1764 command
|= MVNETA_TX_L4_UDP
| MVNETA_TX_L4_CSUM_FULL
;
1766 command
|= MVNETA_TX_L4_CSUM_NOT
;
1772 /* Display more error info */
1773 static void mvneta_rx_error(struct mvneta_port
*pp
,
1774 struct mvneta_rx_desc
*rx_desc
)
1776 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
1777 u32 status
= rx_desc
->status
;
1779 /* update per-cpu counter */
1780 u64_stats_update_begin(&stats
->syncp
);
1782 u64_stats_update_end(&stats
->syncp
);
1784 switch (status
& MVNETA_RXD_ERR_CODE_MASK
) {
1785 case MVNETA_RXD_ERR_CRC
:
1786 netdev_err(pp
->dev
, "bad rx status %08x (crc error), size=%d\n",
1787 status
, rx_desc
->data_size
);
1789 case MVNETA_RXD_ERR_OVERRUN
:
1790 netdev_err(pp
->dev
, "bad rx status %08x (overrun error), size=%d\n",
1791 status
, rx_desc
->data_size
);
1793 case MVNETA_RXD_ERR_LEN
:
1794 netdev_err(pp
->dev
, "bad rx status %08x (max frame length error), size=%d\n",
1795 status
, rx_desc
->data_size
);
1797 case MVNETA_RXD_ERR_RESOURCE
:
1798 netdev_err(pp
->dev
, "bad rx status %08x (resource error), size=%d\n",
1799 status
, rx_desc
->data_size
);
1804 /* Handle RX checksum offload based on the descriptor's status */
1805 static void mvneta_rx_csum(struct mvneta_port
*pp
, u32 status
,
1806 struct sk_buff
*skb
)
1808 if ((pp
->dev
->features
& NETIF_F_RXCSUM
) &&
1809 (status
& MVNETA_RXD_L3_IP4
) &&
1810 (status
& MVNETA_RXD_L4_CSUM_OK
)) {
1812 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1816 skb
->ip_summed
= CHECKSUM_NONE
;
1819 /* Return tx queue pointer (find last set bit) according to <cause> returned
1820 * form tx_done reg. <cause> must not be null. The return value is always a
1821 * valid queue for matching the first one found in <cause>.
1823 static struct mvneta_tx_queue
*mvneta_tx_done_policy(struct mvneta_port
*pp
,
1826 int queue
= fls(cause
) - 1;
1828 return &pp
->txqs
[queue
];
1831 /* Free tx queue skbuffs */
1832 static void mvneta_txq_bufs_free(struct mvneta_port
*pp
,
1833 struct mvneta_tx_queue
*txq
, int num
,
1834 struct netdev_queue
*nq
, bool napi
)
1836 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1837 struct xdp_frame_bulk bq
;
1840 xdp_frame_bulk_init(&bq
);
1842 rcu_read_lock(); /* need for xdp_return_frame_bulk */
1844 for (i
= 0; i
< num
; i
++) {
1845 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_get_index
];
1846 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+
1849 mvneta_txq_inc_get(txq
);
1851 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
) &&
1852 buf
->type
!= MVNETA_TYPE_XDP_TX
)
1853 dma_unmap_single(pp
->dev
->dev
.parent
,
1854 tx_desc
->buf_phys_addr
,
1855 tx_desc
->data_size
, DMA_TO_DEVICE
);
1856 if (buf
->type
== MVNETA_TYPE_SKB
&& buf
->skb
) {
1857 bytes_compl
+= buf
->skb
->len
;
1859 dev_kfree_skb_any(buf
->skb
);
1860 } else if (buf
->type
== MVNETA_TYPE_XDP_TX
||
1861 buf
->type
== MVNETA_TYPE_XDP_NDO
) {
1862 if (napi
&& buf
->type
== MVNETA_TYPE_XDP_TX
)
1863 xdp_return_frame_rx_napi(buf
->xdpf
);
1865 xdp_return_frame_bulk(buf
->xdpf
, &bq
);
1868 xdp_flush_frame_bulk(&bq
);
1872 netdev_tx_completed_queue(nq
, pkts_compl
, bytes_compl
);
1875 /* Handle end of transmission */
1876 static void mvneta_txq_done(struct mvneta_port
*pp
,
1877 struct mvneta_tx_queue
*txq
)
1879 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1882 tx_done
= mvneta_txq_sent_desc_proc(pp
, txq
);
1886 mvneta_txq_bufs_free(pp
, txq
, tx_done
, nq
, true);
1888 txq
->count
-= tx_done
;
1890 if (netif_tx_queue_stopped(nq
)) {
1891 if (txq
->count
<= txq
->tx_wake_threshold
)
1892 netif_tx_wake_queue(nq
);
1896 /* Refill processing for SW buffer management */
1897 /* Allocate page per descriptor */
1898 static int mvneta_rx_refill(struct mvneta_port
*pp
,
1899 struct mvneta_rx_desc
*rx_desc
,
1900 struct mvneta_rx_queue
*rxq
,
1903 dma_addr_t phys_addr
;
1906 page
= page_pool_alloc_pages(rxq
->page_pool
,
1907 gfp_mask
| __GFP_NOWARN
);
1911 phys_addr
= page_pool_get_dma_addr(page
) + pp
->rx_offset_correction
;
1912 mvneta_rx_desc_fill(rx_desc
, phys_addr
, page
, rxq
);
1917 /* Handle tx checksum */
1918 static u32
mvneta_skb_tx_csum(struct mvneta_port
*pp
, struct sk_buff
*skb
)
1920 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1922 __be16 l3_proto
= vlan_get_protocol(skb
);
1925 if (l3_proto
== htons(ETH_P_IP
)) {
1926 struct iphdr
*ip4h
= ip_hdr(skb
);
1928 /* Calculate IPv4 checksum and L4 checksum */
1929 ip_hdr_len
= ip4h
->ihl
;
1930 l4_proto
= ip4h
->protocol
;
1931 } else if (l3_proto
== htons(ETH_P_IPV6
)) {
1932 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1934 /* Read l4_protocol from one of IPv6 extra headers */
1935 if (skb_network_header_len(skb
) > 0)
1936 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
1937 l4_proto
= ip6h
->nexthdr
;
1939 return MVNETA_TX_L4_CSUM_NOT
;
1941 return mvneta_txq_desc_csum(skb_network_offset(skb
),
1942 l3_proto
, ip_hdr_len
, l4_proto
);
1945 return MVNETA_TX_L4_CSUM_NOT
;
1948 /* Drop packets received by the RXQ and free buffers */
1949 static void mvneta_rxq_drop_pkts(struct mvneta_port
*pp
,
1950 struct mvneta_rx_queue
*rxq
)
1954 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1956 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1959 for (i
= 0; i
< rx_done
; i
++) {
1960 struct mvneta_rx_desc
*rx_desc
=
1961 mvneta_rxq_next_desc_get(rxq
);
1962 u8 pool_id
= MVNETA_RX_GET_BM_POOL_ID(rx_desc
);
1963 struct mvneta_bm_pool
*bm_pool
;
1965 bm_pool
= &pp
->bm_priv
->bm_pools
[pool_id
];
1966 /* Return dropped buffer to the pool */
1967 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
1968 rx_desc
->buf_phys_addr
);
1973 for (i
= 0; i
< rxq
->size
; i
++) {
1974 struct mvneta_rx_desc
*rx_desc
= rxq
->descs
+ i
;
1975 void *data
= rxq
->buf_virt_addr
[i
];
1976 if (!data
|| !(rx_desc
->buf_phys_addr
))
1979 page_pool_put_full_page(rxq
->page_pool
, data
, false);
1981 if (xdp_rxq_info_is_reg(&rxq
->xdp_rxq
))
1982 xdp_rxq_info_unreg(&rxq
->xdp_rxq
);
1983 page_pool_destroy(rxq
->page_pool
);
1984 rxq
->page_pool
= NULL
;
1988 mvneta_update_stats(struct mvneta_port
*pp
,
1989 struct mvneta_stats
*ps
)
1991 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
1993 u64_stats_update_begin(&stats
->syncp
);
1994 stats
->es
.ps
.rx_packets
+= ps
->rx_packets
;
1995 stats
->es
.ps
.rx_bytes
+= ps
->rx_bytes
;
1997 stats
->es
.ps
.xdp_redirect
+= ps
->xdp_redirect
;
1998 stats
->es
.ps
.xdp_pass
+= ps
->xdp_pass
;
1999 stats
->es
.ps
.xdp_drop
+= ps
->xdp_drop
;
2000 u64_stats_update_end(&stats
->syncp
);
2004 int mvneta_rx_refill_queue(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
)
2006 struct mvneta_rx_desc
*rx_desc
;
2007 int curr_desc
= rxq
->first_to_refill
;
2010 for (i
= 0; (i
< rxq
->refill_num
) && (i
< 64); i
++) {
2011 rx_desc
= rxq
->descs
+ curr_desc
;
2012 if (!(rx_desc
->buf_phys_addr
)) {
2013 if (mvneta_rx_refill(pp
, rx_desc
, rxq
, GFP_ATOMIC
)) {
2014 struct mvneta_pcpu_stats
*stats
;
2016 pr_err("Can't refill queue %d. Done %d from %d\n",
2017 rxq
->id
, i
, rxq
->refill_num
);
2019 stats
= this_cpu_ptr(pp
->stats
);
2020 u64_stats_update_begin(&stats
->syncp
);
2021 stats
->es
.refill_error
++;
2022 u64_stats_update_end(&stats
->syncp
);
2026 curr_desc
= MVNETA_QUEUE_NEXT_DESC(rxq
, curr_desc
);
2028 rxq
->refill_num
-= i
;
2029 rxq
->first_to_refill
= curr_desc
;
2035 mvneta_xdp_put_buff(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
2036 struct xdp_buff
*xdp
, struct skb_shared_info
*sinfo
,
2041 for (i
= 0; i
< sinfo
->nr_frags
; i
++)
2042 page_pool_put_full_page(rxq
->page_pool
,
2043 skb_frag_page(&sinfo
->frags
[i
]), true);
2044 page_pool_put_page(rxq
->page_pool
, virt_to_head_page(xdp
->data
),
2049 mvneta_xdp_submit_frame(struct mvneta_port
*pp
, struct mvneta_tx_queue
*txq
,
2050 struct xdp_frame
*xdpf
, bool dma_map
)
2052 struct mvneta_tx_desc
*tx_desc
;
2053 struct mvneta_tx_buf
*buf
;
2054 dma_addr_t dma_addr
;
2056 if (txq
->count
>= txq
->tx_stop_threshold
)
2057 return MVNETA_XDP_DROPPED
;
2059 tx_desc
= mvneta_txq_next_desc_get(txq
);
2061 buf
= &txq
->buf
[txq
->txq_put_index
];
2064 dma_addr
= dma_map_single(pp
->dev
->dev
.parent
, xdpf
->data
,
2065 xdpf
->len
, DMA_TO_DEVICE
);
2066 if (dma_mapping_error(pp
->dev
->dev
.parent
, dma_addr
)) {
2067 mvneta_txq_desc_put(txq
);
2068 return MVNETA_XDP_DROPPED
;
2070 buf
->type
= MVNETA_TYPE_XDP_NDO
;
2072 struct page
*page
= virt_to_page(xdpf
->data
);
2074 dma_addr
= page_pool_get_dma_addr(page
) +
2075 sizeof(*xdpf
) + xdpf
->headroom
;
2076 dma_sync_single_for_device(pp
->dev
->dev
.parent
, dma_addr
,
2077 xdpf
->len
, DMA_BIDIRECTIONAL
);
2078 buf
->type
= MVNETA_TYPE_XDP_TX
;
2082 tx_desc
->command
= MVNETA_TXD_FLZ_DESC
;
2083 tx_desc
->buf_phys_addr
= dma_addr
;
2084 tx_desc
->data_size
= xdpf
->len
;
2086 mvneta_txq_inc_put(txq
);
2090 return MVNETA_XDP_TX
;
2094 mvneta_xdp_xmit_back(struct mvneta_port
*pp
, struct xdp_buff
*xdp
)
2096 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2097 struct mvneta_tx_queue
*txq
;
2098 struct netdev_queue
*nq
;
2099 struct xdp_frame
*xdpf
;
2103 xdpf
= xdp_convert_buff_to_frame(xdp
);
2104 if (unlikely(!xdpf
))
2105 return MVNETA_XDP_DROPPED
;
2107 cpu
= smp_processor_id();
2108 txq
= &pp
->txqs
[cpu
% txq_number
];
2109 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2111 __netif_tx_lock(nq
, cpu
);
2112 ret
= mvneta_xdp_submit_frame(pp
, txq
, xdpf
, false);
2113 if (ret
== MVNETA_XDP_TX
) {
2114 u64_stats_update_begin(&stats
->syncp
);
2115 stats
->es
.ps
.tx_bytes
+= xdpf
->len
;
2116 stats
->es
.ps
.tx_packets
++;
2117 stats
->es
.ps
.xdp_tx
++;
2118 u64_stats_update_end(&stats
->syncp
);
2120 mvneta_txq_pend_desc_add(pp
, txq
, 0);
2122 u64_stats_update_begin(&stats
->syncp
);
2123 stats
->es
.ps
.xdp_tx_err
++;
2124 u64_stats_update_end(&stats
->syncp
);
2126 __netif_tx_unlock(nq
);
2132 mvneta_xdp_xmit(struct net_device
*dev
, int num_frame
,
2133 struct xdp_frame
**frames
, u32 flags
)
2135 struct mvneta_port
*pp
= netdev_priv(dev
);
2136 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2137 int i
, nxmit_byte
= 0, nxmit
= num_frame
;
2138 int cpu
= smp_processor_id();
2139 struct mvneta_tx_queue
*txq
;
2140 struct netdev_queue
*nq
;
2143 if (unlikely(test_bit(__MVNETA_DOWN
, &pp
->state
)))
2146 if (unlikely(flags
& ~XDP_XMIT_FLAGS_MASK
))
2149 txq
= &pp
->txqs
[cpu
% txq_number
];
2150 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2152 __netif_tx_lock(nq
, cpu
);
2153 for (i
= 0; i
< num_frame
; i
++) {
2154 ret
= mvneta_xdp_submit_frame(pp
, txq
, frames
[i
], true);
2155 if (ret
== MVNETA_XDP_TX
) {
2156 nxmit_byte
+= frames
[i
]->len
;
2158 xdp_return_frame_rx_napi(frames
[i
]);
2163 if (unlikely(flags
& XDP_XMIT_FLUSH
))
2164 mvneta_txq_pend_desc_add(pp
, txq
, 0);
2165 __netif_tx_unlock(nq
);
2167 u64_stats_update_begin(&stats
->syncp
);
2168 stats
->es
.ps
.tx_bytes
+= nxmit_byte
;
2169 stats
->es
.ps
.tx_packets
+= nxmit
;
2170 stats
->es
.ps
.xdp_xmit
+= nxmit
;
2171 stats
->es
.ps
.xdp_xmit_err
+= num_frame
- nxmit
;
2172 u64_stats_update_end(&stats
->syncp
);
2178 mvneta_run_xdp(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
2179 struct bpf_prog
*prog
, struct xdp_buff
*xdp
,
2180 u32 frame_sz
, struct mvneta_stats
*stats
)
2182 struct skb_shared_info
*sinfo
= xdp_get_shared_info_from_buff(xdp
);
2183 unsigned int len
, data_len
, sync
;
2186 len
= xdp
->data_end
- xdp
->data_hard_start
- pp
->rx_offset_correction
;
2187 data_len
= xdp
->data_end
- xdp
->data
;
2188 act
= bpf_prog_run_xdp(prog
, xdp
);
2190 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
2191 sync
= xdp
->data_end
- xdp
->data_hard_start
- pp
->rx_offset_correction
;
2192 sync
= max(sync
, len
);
2197 return MVNETA_XDP_PASS
;
2198 case XDP_REDIRECT
: {
2201 err
= xdp_do_redirect(pp
->dev
, xdp
, prog
);
2202 if (unlikely(err
)) {
2203 mvneta_xdp_put_buff(pp
, rxq
, xdp
, sinfo
, sync
);
2204 ret
= MVNETA_XDP_DROPPED
;
2206 ret
= MVNETA_XDP_REDIR
;
2207 stats
->xdp_redirect
++;
2212 ret
= mvneta_xdp_xmit_back(pp
, xdp
);
2213 if (ret
!= MVNETA_XDP_TX
)
2214 mvneta_xdp_put_buff(pp
, rxq
, xdp
, sinfo
, sync
);
2217 bpf_warn_invalid_xdp_action(act
);
2220 trace_xdp_exception(pp
->dev
, prog
, act
);
2223 mvneta_xdp_put_buff(pp
, rxq
, xdp
, sinfo
, sync
);
2224 ret
= MVNETA_XDP_DROPPED
;
2229 stats
->rx_bytes
+= frame_sz
+ xdp
->data_end
- xdp
->data
- data_len
;
2230 stats
->rx_packets
++;
2236 mvneta_swbm_rx_frame(struct mvneta_port
*pp
,
2237 struct mvneta_rx_desc
*rx_desc
,
2238 struct mvneta_rx_queue
*rxq
,
2239 struct xdp_buff
*xdp
, int *size
,
2242 unsigned char *data
= page_address(page
);
2243 int data_len
= -MVNETA_MH_SIZE
, len
;
2244 struct net_device
*dev
= pp
->dev
;
2245 enum dma_data_direction dma_dir
;
2246 struct skb_shared_info
*sinfo
;
2248 if (*size
> MVNETA_MAX_RX_BUF_SIZE
) {
2249 len
= MVNETA_MAX_RX_BUF_SIZE
;
2253 data_len
+= len
- ETH_FCS_LEN
;
2255 *size
= *size
- len
;
2257 dma_dir
= page_pool_get_dma_dir(rxq
->page_pool
);
2258 dma_sync_single_for_cpu(dev
->dev
.parent
,
2259 rx_desc
->buf_phys_addr
,
2262 rx_desc
->buf_phys_addr
= 0;
2264 /* Prefetch header */
2267 xdp
->data_hard_start
= data
;
2268 xdp
->data
= data
+ pp
->rx_offset_correction
+ MVNETA_MH_SIZE
;
2269 xdp
->data_end
= xdp
->data
+ data_len
;
2270 xdp_set_data_meta_invalid(xdp
);
2272 sinfo
= xdp_get_shared_info_from_buff(xdp
);
2273 sinfo
->nr_frags
= 0;
2277 mvneta_swbm_add_rx_fragment(struct mvneta_port
*pp
,
2278 struct mvneta_rx_desc
*rx_desc
,
2279 struct mvneta_rx_queue
*rxq
,
2280 struct xdp_buff
*xdp
, int *size
,
2281 struct skb_shared_info
*xdp_sinfo
,
2284 struct net_device
*dev
= pp
->dev
;
2285 enum dma_data_direction dma_dir
;
2288 if (*size
> MVNETA_MAX_RX_BUF_SIZE
) {
2289 len
= MVNETA_MAX_RX_BUF_SIZE
;
2293 data_len
= len
- ETH_FCS_LEN
;
2295 dma_dir
= page_pool_get_dma_dir(rxq
->page_pool
);
2296 dma_sync_single_for_cpu(dev
->dev
.parent
,
2297 rx_desc
->buf_phys_addr
,
2299 rx_desc
->buf_phys_addr
= 0;
2301 if (data_len
> 0 && xdp_sinfo
->nr_frags
< MAX_SKB_FRAGS
) {
2302 skb_frag_t
*frag
= &xdp_sinfo
->frags
[xdp_sinfo
->nr_frags
++];
2304 skb_frag_off_set(frag
, pp
->rx_offset_correction
);
2305 skb_frag_size_set(frag
, data_len
);
2306 __skb_frag_set_page(frag
, page
);
2308 page_pool_put_full_page(rxq
->page_pool
, page
, true);
2313 struct skb_shared_info
*sinfo
;
2315 sinfo
= xdp_get_shared_info_from_buff(xdp
);
2316 sinfo
->nr_frags
= xdp_sinfo
->nr_frags
;
2317 memcpy(sinfo
->frags
, xdp_sinfo
->frags
,
2318 sinfo
->nr_frags
* sizeof(skb_frag_t
));
2323 static struct sk_buff
*
2324 mvneta_swbm_build_skb(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
2325 struct xdp_buff
*xdp
, u32 desc_status
)
2327 struct skb_shared_info
*sinfo
= xdp_get_shared_info_from_buff(xdp
);
2328 int i
, num_frags
= sinfo
->nr_frags
;
2329 struct sk_buff
*skb
;
2331 skb
= build_skb(xdp
->data_hard_start
, PAGE_SIZE
);
2333 return ERR_PTR(-ENOMEM
);
2335 page_pool_release_page(rxq
->page_pool
, virt_to_page(xdp
->data
));
2337 skb_reserve(skb
, xdp
->data
- xdp
->data_hard_start
);
2338 skb_put(skb
, xdp
->data_end
- xdp
->data
);
2339 mvneta_rx_csum(pp
, desc_status
, skb
);
2341 for (i
= 0; i
< num_frags
; i
++) {
2342 skb_frag_t
*frag
= &sinfo
->frags
[i
];
2344 skb_add_rx_frag(skb
, skb_shinfo(skb
)->nr_frags
,
2345 skb_frag_page(frag
), skb_frag_off(frag
),
2346 skb_frag_size(frag
), PAGE_SIZE
);
2347 page_pool_release_page(rxq
->page_pool
, skb_frag_page(frag
));
2353 /* Main rx processing when using software buffer management */
2354 static int mvneta_rx_swbm(struct napi_struct
*napi
,
2355 struct mvneta_port
*pp
, int budget
,
2356 struct mvneta_rx_queue
*rxq
)
2358 int rx_proc
= 0, rx_todo
, refill
, size
= 0;
2359 struct net_device
*dev
= pp
->dev
;
2360 struct skb_shared_info sinfo
;
2361 struct mvneta_stats ps
= {};
2362 struct bpf_prog
*xdp_prog
;
2363 u32 desc_status
, frame_sz
;
2364 struct xdp_buff xdp_buf
;
2366 xdp_buf
.data_hard_start
= NULL
;
2367 xdp_buf
.frame_sz
= PAGE_SIZE
;
2368 xdp_buf
.rxq
= &rxq
->xdp_rxq
;
2372 /* Get number of received packets */
2373 rx_todo
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
2376 xdp_prog
= READ_ONCE(pp
->xdp_prog
);
2378 /* Fairness NAPI loop */
2379 while (rx_proc
< budget
&& rx_proc
< rx_todo
) {
2380 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
2381 u32 rx_status
, index
;
2382 struct sk_buff
*skb
;
2385 index
= rx_desc
- rxq
->descs
;
2386 page
= (struct page
*)rxq
->buf_virt_addr
[index
];
2388 rx_status
= rx_desc
->status
;
2392 if (rx_status
& MVNETA_RXD_FIRST_DESC
) {
2393 /* Check errors only for FIRST descriptor */
2394 if (rx_status
& MVNETA_RXD_ERR_SUMMARY
) {
2395 mvneta_rx_error(pp
, rx_desc
);
2399 size
= rx_desc
->data_size
;
2400 frame_sz
= size
- ETH_FCS_LEN
;
2401 desc_status
= rx_status
;
2403 mvneta_swbm_rx_frame(pp
, rx_desc
, rxq
, &xdp_buf
,
2406 if (unlikely(!xdp_buf
.data_hard_start
)) {
2407 rx_desc
->buf_phys_addr
= 0;
2408 page_pool_put_full_page(rxq
->page_pool
, page
,
2413 mvneta_swbm_add_rx_fragment(pp
, rx_desc
, rxq
, &xdp_buf
,
2414 &size
, &sinfo
, page
);
2415 } /* Middle or Last descriptor */
2417 if (!(rx_status
& MVNETA_RXD_LAST_DESC
))
2418 /* no last descriptor this time */
2422 mvneta_xdp_put_buff(pp
, rxq
, &xdp_buf
, &sinfo
, -1);
2427 mvneta_run_xdp(pp
, rxq
, xdp_prog
, &xdp_buf
, frame_sz
, &ps
))
2430 skb
= mvneta_swbm_build_skb(pp
, rxq
, &xdp_buf
, desc_status
);
2432 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2434 mvneta_xdp_put_buff(pp
, rxq
, &xdp_buf
, &sinfo
, -1);
2436 u64_stats_update_begin(&stats
->syncp
);
2437 stats
->es
.skb_alloc_error
++;
2438 stats
->rx_dropped
++;
2439 u64_stats_update_end(&stats
->syncp
);
2444 ps
.rx_bytes
+= skb
->len
;
2447 skb
->protocol
= eth_type_trans(skb
, dev
);
2448 napi_gro_receive(napi
, skb
);
2450 xdp_buf
.data_hard_start
= NULL
;
2455 if (xdp_buf
.data_hard_start
)
2456 mvneta_xdp_put_buff(pp
, rxq
, &xdp_buf
, &sinfo
, -1);
2458 if (ps
.xdp_redirect
)
2462 mvneta_update_stats(pp
, &ps
);
2464 /* return some buffers to hardware queue, one at a time is too slow */
2465 refill
= mvneta_rx_refill_queue(pp
, rxq
);
2467 /* Update rxq management counters */
2468 mvneta_rxq_desc_num_update(pp
, rxq
, rx_proc
, refill
);
2470 return ps
.rx_packets
;
2473 /* Main rx processing when using hardware buffer management */
2474 static int mvneta_rx_hwbm(struct napi_struct
*napi
,
2475 struct mvneta_port
*pp
, int rx_todo
,
2476 struct mvneta_rx_queue
*rxq
)
2478 struct net_device
*dev
= pp
->dev
;
2483 /* Get number of received packets */
2484 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
2486 if (rx_todo
> rx_done
)
2491 /* Fairness NAPI loop */
2492 while (rx_done
< rx_todo
) {
2493 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
2494 struct mvneta_bm_pool
*bm_pool
= NULL
;
2495 struct sk_buff
*skb
;
2496 unsigned char *data
;
2497 dma_addr_t phys_addr
;
2498 u32 rx_status
, frag_size
;
2503 rx_status
= rx_desc
->status
;
2504 rx_bytes
= rx_desc
->data_size
- (ETH_FCS_LEN
+ MVNETA_MH_SIZE
);
2505 data
= (u8
*)(uintptr_t)rx_desc
->buf_cookie
;
2506 phys_addr
= rx_desc
->buf_phys_addr
;
2507 pool_id
= MVNETA_RX_GET_BM_POOL_ID(rx_desc
);
2508 bm_pool
= &pp
->bm_priv
->bm_pools
[pool_id
];
2510 if (!mvneta_rxq_desc_is_first_last(rx_status
) ||
2511 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
2512 err_drop_frame_ret_pool
:
2513 /* Return the buffer to the pool */
2514 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
2515 rx_desc
->buf_phys_addr
);
2517 mvneta_rx_error(pp
, rx_desc
);
2518 /* leave the descriptor untouched */
2522 if (rx_bytes
<= rx_copybreak
) {
2523 /* better copy a small frame and not unmap the DMA region */
2524 skb
= netdev_alloc_skb_ip_align(dev
, rx_bytes
);
2526 goto err_drop_frame_ret_pool
;
2528 dma_sync_single_range_for_cpu(&pp
->bm_priv
->pdev
->dev
,
2529 rx_desc
->buf_phys_addr
,
2530 MVNETA_MH_SIZE
+ NET_SKB_PAD
,
2533 skb_put_data(skb
, data
+ MVNETA_MH_SIZE
+ NET_SKB_PAD
,
2536 skb
->protocol
= eth_type_trans(skb
, dev
);
2537 mvneta_rx_csum(pp
, rx_status
, skb
);
2538 napi_gro_receive(napi
, skb
);
2541 rcvd_bytes
+= rx_bytes
;
2543 /* Return the buffer to the pool */
2544 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
2545 rx_desc
->buf_phys_addr
);
2547 /* leave the descriptor and buffer untouched */
2551 /* Refill processing */
2552 err
= hwbm_pool_refill(&bm_pool
->hwbm_pool
, GFP_ATOMIC
);
2554 struct mvneta_pcpu_stats
*stats
;
2556 netdev_err(dev
, "Linux processing - Can't refill\n");
2558 stats
= this_cpu_ptr(pp
->stats
);
2559 u64_stats_update_begin(&stats
->syncp
);
2560 stats
->es
.refill_error
++;
2561 u64_stats_update_end(&stats
->syncp
);
2563 goto err_drop_frame_ret_pool
;
2566 frag_size
= bm_pool
->hwbm_pool
.frag_size
;
2568 skb
= build_skb(data
, frag_size
> PAGE_SIZE
? 0 : frag_size
);
2570 /* After refill old buffer has to be unmapped regardless
2571 * the skb is successfully built or not.
2573 dma_unmap_single(&pp
->bm_priv
->pdev
->dev
, phys_addr
,
2574 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
2576 goto err_drop_frame
;
2579 rcvd_bytes
+= rx_bytes
;
2581 /* Linux processing */
2582 skb_reserve(skb
, MVNETA_MH_SIZE
+ NET_SKB_PAD
);
2583 skb_put(skb
, rx_bytes
);
2585 skb
->protocol
= eth_type_trans(skb
, dev
);
2587 mvneta_rx_csum(pp
, rx_status
, skb
);
2589 napi_gro_receive(napi
, skb
);
2593 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2595 u64_stats_update_begin(&stats
->syncp
);
2596 stats
->es
.ps
.rx_packets
+= rcvd_pkts
;
2597 stats
->es
.ps
.rx_bytes
+= rcvd_bytes
;
2598 u64_stats_update_end(&stats
->syncp
);
2601 /* Update rxq management counters */
2602 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
2608 mvneta_tso_put_hdr(struct sk_buff
*skb
,
2609 struct mvneta_port
*pp
, struct mvneta_tx_queue
*txq
)
2611 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2612 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2613 struct mvneta_tx_desc
*tx_desc
;
2615 tx_desc
= mvneta_txq_next_desc_get(txq
);
2616 tx_desc
->data_size
= hdr_len
;
2617 tx_desc
->command
= mvneta_skb_tx_csum(pp
, skb
);
2618 tx_desc
->command
|= MVNETA_TXD_F_DESC
;
2619 tx_desc
->buf_phys_addr
= txq
->tso_hdrs_phys
+
2620 txq
->txq_put_index
* TSO_HEADER_SIZE
;
2621 buf
->type
= MVNETA_TYPE_SKB
;
2624 mvneta_txq_inc_put(txq
);
2628 mvneta_tso_put_data(struct net_device
*dev
, struct mvneta_tx_queue
*txq
,
2629 struct sk_buff
*skb
, char *data
, int size
,
2630 bool last_tcp
, bool is_last
)
2632 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2633 struct mvneta_tx_desc
*tx_desc
;
2635 tx_desc
= mvneta_txq_next_desc_get(txq
);
2636 tx_desc
->data_size
= size
;
2637 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, data
,
2638 size
, DMA_TO_DEVICE
);
2639 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
2640 tx_desc
->buf_phys_addr
))) {
2641 mvneta_txq_desc_put(txq
);
2645 tx_desc
->command
= 0;
2646 buf
->type
= MVNETA_TYPE_SKB
;
2650 /* last descriptor in the TCP packet */
2651 tx_desc
->command
= MVNETA_TXD_L_DESC
;
2653 /* last descriptor in SKB */
2657 mvneta_txq_inc_put(txq
);
2661 static int mvneta_tx_tso(struct sk_buff
*skb
, struct net_device
*dev
,
2662 struct mvneta_tx_queue
*txq
)
2664 int hdr_len
, total_len
, data_left
;
2666 struct mvneta_port
*pp
= netdev_priv(dev
);
2670 /* Count needed descriptors */
2671 if ((txq
->count
+ tso_count_descs(skb
)) >= txq
->size
)
2674 if (skb_headlen(skb
) < (skb_transport_offset(skb
) + tcp_hdrlen(skb
))) {
2675 pr_info("*** Is this even possible???!?!?\n");
2679 /* Initialize the TSO handler, and prepare the first payload */
2680 hdr_len
= tso_start(skb
, &tso
);
2682 total_len
= skb
->len
- hdr_len
;
2683 while (total_len
> 0) {
2686 data_left
= min_t(int, skb_shinfo(skb
)->gso_size
, total_len
);
2687 total_len
-= data_left
;
2690 /* prepare packet headers: MAC + IP + TCP */
2691 hdr
= txq
->tso_hdrs
+ txq
->txq_put_index
* TSO_HEADER_SIZE
;
2692 tso_build_hdr(skb
, hdr
, &tso
, data_left
, total_len
== 0);
2694 mvneta_tso_put_hdr(skb
, pp
, txq
);
2696 while (data_left
> 0) {
2700 size
= min_t(int, tso
.size
, data_left
);
2702 if (mvneta_tso_put_data(dev
, txq
, skb
,
2709 tso_build_data(skb
, &tso
, size
);
2716 /* Release all used data descriptors; header descriptors must not
2719 for (i
= desc_count
- 1; i
>= 0; i
--) {
2720 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+ i
;
2721 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
))
2722 dma_unmap_single(pp
->dev
->dev
.parent
,
2723 tx_desc
->buf_phys_addr
,
2726 mvneta_txq_desc_put(txq
);
2731 /* Handle tx fragmentation processing */
2732 static int mvneta_tx_frag_process(struct mvneta_port
*pp
, struct sk_buff
*skb
,
2733 struct mvneta_tx_queue
*txq
)
2735 struct mvneta_tx_desc
*tx_desc
;
2736 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
2738 for (i
= 0; i
< nr_frags
; i
++) {
2739 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2740 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2741 void *addr
= skb_frag_address(frag
);
2743 tx_desc
= mvneta_txq_next_desc_get(txq
);
2744 tx_desc
->data_size
= skb_frag_size(frag
);
2746 tx_desc
->buf_phys_addr
=
2747 dma_map_single(pp
->dev
->dev
.parent
, addr
,
2748 tx_desc
->data_size
, DMA_TO_DEVICE
);
2750 if (dma_mapping_error(pp
->dev
->dev
.parent
,
2751 tx_desc
->buf_phys_addr
)) {
2752 mvneta_txq_desc_put(txq
);
2756 if (i
== nr_frags
- 1) {
2757 /* Last descriptor */
2758 tx_desc
->command
= MVNETA_TXD_L_DESC
| MVNETA_TXD_Z_PAD
;
2761 /* Descriptor in the middle: Not First, Not Last */
2762 tx_desc
->command
= 0;
2765 buf
->type
= MVNETA_TYPE_SKB
;
2766 mvneta_txq_inc_put(txq
);
2772 /* Release all descriptors that were used to map fragments of
2773 * this packet, as well as the corresponding DMA mappings
2775 for (i
= i
- 1; i
>= 0; i
--) {
2776 tx_desc
= txq
->descs
+ i
;
2777 dma_unmap_single(pp
->dev
->dev
.parent
,
2778 tx_desc
->buf_phys_addr
,
2781 mvneta_txq_desc_put(txq
);
2787 /* Main tx processing */
2788 static netdev_tx_t
mvneta_tx(struct sk_buff
*skb
, struct net_device
*dev
)
2790 struct mvneta_port
*pp
= netdev_priv(dev
);
2791 u16 txq_id
= skb_get_queue_mapping(skb
);
2792 struct mvneta_tx_queue
*txq
= &pp
->txqs
[txq_id
];
2793 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2794 struct mvneta_tx_desc
*tx_desc
;
2799 if (!netif_running(dev
))
2802 if (skb_is_gso(skb
)) {
2803 frags
= mvneta_tx_tso(skb
, dev
, txq
);
2807 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
2809 /* Get a descriptor for the first part of the packet */
2810 tx_desc
= mvneta_txq_next_desc_get(txq
);
2812 tx_cmd
= mvneta_skb_tx_csum(pp
, skb
);
2814 tx_desc
->data_size
= skb_headlen(skb
);
2816 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
2819 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
2820 tx_desc
->buf_phys_addr
))) {
2821 mvneta_txq_desc_put(txq
);
2826 buf
->type
= MVNETA_TYPE_SKB
;
2828 /* First and Last descriptor */
2829 tx_cmd
|= MVNETA_TXD_FLZ_DESC
;
2830 tx_desc
->command
= tx_cmd
;
2832 mvneta_txq_inc_put(txq
);
2834 /* First but not Last */
2835 tx_cmd
|= MVNETA_TXD_F_DESC
;
2837 mvneta_txq_inc_put(txq
);
2838 tx_desc
->command
= tx_cmd
;
2839 /* Continue with other skb fragments */
2840 if (mvneta_tx_frag_process(pp
, skb
, txq
)) {
2841 dma_unmap_single(dev
->dev
.parent
,
2842 tx_desc
->buf_phys_addr
,
2845 mvneta_txq_desc_put(txq
);
2853 struct netdev_queue
*nq
= netdev_get_tx_queue(dev
, txq_id
);
2854 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2856 netdev_tx_sent_queue(nq
, len
);
2858 txq
->count
+= frags
;
2859 if (txq
->count
>= txq
->tx_stop_threshold
)
2860 netif_tx_stop_queue(nq
);
2862 if (!netdev_xmit_more() || netif_xmit_stopped(nq
) ||
2863 txq
->pending
+ frags
> MVNETA_TXQ_DEC_SENT_MASK
)
2864 mvneta_txq_pend_desc_add(pp
, txq
, frags
);
2866 txq
->pending
+= frags
;
2868 u64_stats_update_begin(&stats
->syncp
);
2869 stats
->es
.ps
.tx_bytes
+= len
;
2870 stats
->es
.ps
.tx_packets
++;
2871 u64_stats_update_end(&stats
->syncp
);
2873 dev
->stats
.tx_dropped
++;
2874 dev_kfree_skb_any(skb
);
2877 return NETDEV_TX_OK
;
2881 /* Free tx resources, when resetting a port */
2882 static void mvneta_txq_done_force(struct mvneta_port
*pp
,
2883 struct mvneta_tx_queue
*txq
)
2886 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2887 int tx_done
= txq
->count
;
2889 mvneta_txq_bufs_free(pp
, txq
, tx_done
, nq
, false);
2893 txq
->txq_put_index
= 0;
2894 txq
->txq_get_index
= 0;
2897 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2898 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2900 static void mvneta_tx_done_gbe(struct mvneta_port
*pp
, u32 cause_tx_done
)
2902 struct mvneta_tx_queue
*txq
;
2903 struct netdev_queue
*nq
;
2904 int cpu
= smp_processor_id();
2906 while (cause_tx_done
) {
2907 txq
= mvneta_tx_done_policy(pp
, cause_tx_done
);
2909 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2910 __netif_tx_lock(nq
, cpu
);
2913 mvneta_txq_done(pp
, txq
);
2915 __netif_tx_unlock(nq
);
2916 cause_tx_done
&= ~((1 << txq
->id
));
2920 /* Compute crc8 of the specified address, using a unique algorithm ,
2921 * according to hw spec, different than generic crc8 algorithm
2923 static int mvneta_addr_crc(unsigned char *addr
)
2928 for (i
= 0; i
< ETH_ALEN
; i
++) {
2931 crc
= (crc
^ addr
[i
]) << 8;
2932 for (j
= 7; j
>= 0; j
--) {
2933 if (crc
& (0x100 << j
))
2941 /* This method controls the net device special MAC multicast support.
2942 * The Special Multicast Table for MAC addresses supports MAC of the form
2943 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2944 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2945 * Table entries in the DA-Filter table. This method set the Special
2946 * Multicast Table appropriate entry.
2948 static void mvneta_set_special_mcast_addr(struct mvneta_port
*pp
,
2949 unsigned char last_byte
,
2952 unsigned int smc_table_reg
;
2953 unsigned int tbl_offset
;
2954 unsigned int reg_offset
;
2956 /* Register offset from SMC table base */
2957 tbl_offset
= (last_byte
/ 4);
2958 /* Entry offset within the above reg */
2959 reg_offset
= last_byte
% 4;
2961 smc_table_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_SPEC_MCAST
2965 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
2967 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
2968 smc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
2971 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ tbl_offset
* 4,
2975 /* This method controls the network device Other MAC multicast support.
2976 * The Other Multicast Table is used for multicast of another type.
2977 * A CRC-8 is used as an index to the Other Multicast Table entries
2978 * in the DA-Filter table.
2979 * The method gets the CRC-8 value from the calling routine and
2980 * sets the Other Multicast Table appropriate entry according to the
2983 static void mvneta_set_other_mcast_addr(struct mvneta_port
*pp
,
2987 unsigned int omc_table_reg
;
2988 unsigned int tbl_offset
;
2989 unsigned int reg_offset
;
2991 tbl_offset
= (crc8
/ 4) * 4; /* Register offset from OMC table base */
2992 reg_offset
= crc8
% 4; /* Entry offset within the above reg */
2994 omc_table_reg
= mvreg_read(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
);
2997 /* Clear accepts frame bit at specified Other DA table entry */
2998 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
3000 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
3001 omc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
3004 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
, omc_table_reg
);
3007 /* The network device supports multicast using two tables:
3008 * 1) Special Multicast Table for MAC addresses of the form
3009 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
3010 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
3011 * Table entries in the DA-Filter table.
3012 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
3013 * is used as an index to the Other Multicast Table entries in the
3016 static int mvneta_mcast_addr_set(struct mvneta_port
*pp
, unsigned char *p_addr
,
3019 unsigned char crc_result
= 0;
3021 if (memcmp(p_addr
, "\x01\x00\x5e\x00\x00", 5) == 0) {
3022 mvneta_set_special_mcast_addr(pp
, p_addr
[5], queue
);
3026 crc_result
= mvneta_addr_crc(p_addr
);
3028 if (pp
->mcast_count
[crc_result
] == 0) {
3029 netdev_info(pp
->dev
, "No valid Mcast for crc8=0x%02x\n",
3034 pp
->mcast_count
[crc_result
]--;
3035 if (pp
->mcast_count
[crc_result
] != 0) {
3036 netdev_info(pp
->dev
,
3037 "After delete there are %d valid Mcast for crc8=0x%02x\n",
3038 pp
->mcast_count
[crc_result
], crc_result
);
3042 pp
->mcast_count
[crc_result
]++;
3044 mvneta_set_other_mcast_addr(pp
, crc_result
, queue
);
3049 /* Configure Fitering mode of Ethernet port */
3050 static void mvneta_rx_unicast_promisc_set(struct mvneta_port
*pp
,
3053 u32 port_cfg_reg
, val
;
3055 port_cfg_reg
= mvreg_read(pp
, MVNETA_PORT_CONFIG
);
3057 val
= mvreg_read(pp
, MVNETA_TYPE_PRIO
);
3059 /* Set / Clear UPM bit in port configuration register */
3061 /* Accept all Unicast addresses */
3062 port_cfg_reg
|= MVNETA_UNI_PROMISC_MODE
;
3063 val
|= MVNETA_FORCE_UNI
;
3064 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, 0xffff);
3065 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, 0xffffffff);
3067 /* Reject all Unicast addresses */
3068 port_cfg_reg
&= ~MVNETA_UNI_PROMISC_MODE
;
3069 val
&= ~MVNETA_FORCE_UNI
;
3072 mvreg_write(pp
, MVNETA_PORT_CONFIG
, port_cfg_reg
);
3073 mvreg_write(pp
, MVNETA_TYPE_PRIO
, val
);
3076 /* register unicast and multicast addresses */
3077 static void mvneta_set_rx_mode(struct net_device
*dev
)
3079 struct mvneta_port
*pp
= netdev_priv(dev
);
3080 struct netdev_hw_addr
*ha
;
3082 if (dev
->flags
& IFF_PROMISC
) {
3083 /* Accept all: Multicast + Unicast */
3084 mvneta_rx_unicast_promisc_set(pp
, 1);
3085 mvneta_set_ucast_table(pp
, pp
->rxq_def
);
3086 mvneta_set_special_mcast_table(pp
, pp
->rxq_def
);
3087 mvneta_set_other_mcast_table(pp
, pp
->rxq_def
);
3089 /* Accept single Unicast */
3090 mvneta_rx_unicast_promisc_set(pp
, 0);
3091 mvneta_set_ucast_table(pp
, -1);
3092 mvneta_mac_addr_set(pp
, dev
->dev_addr
, pp
->rxq_def
);
3094 if (dev
->flags
& IFF_ALLMULTI
) {
3095 /* Accept all multicast */
3096 mvneta_set_special_mcast_table(pp
, pp
->rxq_def
);
3097 mvneta_set_other_mcast_table(pp
, pp
->rxq_def
);
3099 /* Accept only initialized multicast */
3100 mvneta_set_special_mcast_table(pp
, -1);
3101 mvneta_set_other_mcast_table(pp
, -1);
3103 if (!netdev_mc_empty(dev
)) {
3104 netdev_for_each_mc_addr(ha
, dev
) {
3105 mvneta_mcast_addr_set(pp
, ha
->addr
,
3113 /* Interrupt handling - the callback for request_irq() */
3114 static irqreturn_t
mvneta_isr(int irq
, void *dev_id
)
3116 struct mvneta_port
*pp
= (struct mvneta_port
*)dev_id
;
3118 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
3119 napi_schedule(&pp
->napi
);
3124 /* Interrupt handling - the callback for request_percpu_irq() */
3125 static irqreturn_t
mvneta_percpu_isr(int irq
, void *dev_id
)
3127 struct mvneta_pcpu_port
*port
= (struct mvneta_pcpu_port
*)dev_id
;
3129 disable_percpu_irq(port
->pp
->dev
->irq
);
3130 napi_schedule(&port
->napi
);
3135 static void mvneta_link_change(struct mvneta_port
*pp
)
3137 u32 gmac_stat
= mvreg_read(pp
, MVNETA_GMAC_STATUS
);
3139 phylink_mac_change(pp
->phylink
, !!(gmac_stat
& MVNETA_GMAC_LINK_UP
));
3143 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
3144 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
3145 * Bits 8 -15 of the cause Rx Tx register indicate that are received
3146 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
3147 * Each CPU has its own causeRxTx register
3149 static int mvneta_poll(struct napi_struct
*napi
, int budget
)
3154 struct mvneta_port
*pp
= netdev_priv(napi
->dev
);
3155 struct mvneta_pcpu_port
*port
= this_cpu_ptr(pp
->ports
);
3157 if (!netif_running(pp
->dev
)) {
3158 napi_complete(napi
);
3162 /* Read cause register */
3163 cause_rx_tx
= mvreg_read(pp
, MVNETA_INTR_NEW_CAUSE
);
3164 if (cause_rx_tx
& MVNETA_MISCINTR_INTR_MASK
) {
3165 u32 cause_misc
= mvreg_read(pp
, MVNETA_INTR_MISC_CAUSE
);
3167 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
3169 if (cause_misc
& (MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3170 MVNETA_CAUSE_LINK_CHANGE
))
3171 mvneta_link_change(pp
);
3174 /* Release Tx descriptors */
3175 if (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
) {
3176 mvneta_tx_done_gbe(pp
, (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
));
3177 cause_rx_tx
&= ~MVNETA_TX_INTR_MASK_ALL
;
3180 /* For the case where the last mvneta_poll did not process all
3183 cause_rx_tx
|= pp
->neta_armada3700
? pp
->cause_rx_tx
:
3186 rx_queue
= fls(((cause_rx_tx
>> 8) & 0xff));
3188 rx_queue
= rx_queue
- 1;
3190 rx_done
= mvneta_rx_hwbm(napi
, pp
, budget
,
3191 &pp
->rxqs
[rx_queue
]);
3193 rx_done
= mvneta_rx_swbm(napi
, pp
, budget
,
3194 &pp
->rxqs
[rx_queue
]);
3197 if (rx_done
< budget
) {
3199 napi_complete_done(napi
, rx_done
);
3201 if (pp
->neta_armada3700
) {
3202 unsigned long flags
;
3204 local_irq_save(flags
);
3205 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
3206 MVNETA_RX_INTR_MASK(rxq_number
) |
3207 MVNETA_TX_INTR_MASK(txq_number
) |
3208 MVNETA_MISCINTR_INTR_MASK
);
3209 local_irq_restore(flags
);
3211 enable_percpu_irq(pp
->dev
->irq
, 0);
3215 if (pp
->neta_armada3700
)
3216 pp
->cause_rx_tx
= cause_rx_tx
;
3218 port
->cause_rx_tx
= cause_rx_tx
;
3223 static int mvneta_create_page_pool(struct mvneta_port
*pp
,
3224 struct mvneta_rx_queue
*rxq
, int size
)
3226 struct bpf_prog
*xdp_prog
= READ_ONCE(pp
->xdp_prog
);
3227 struct page_pool_params pp_params
= {
3229 .flags
= PP_FLAG_DMA_MAP
| PP_FLAG_DMA_SYNC_DEV
,
3231 .nid
= NUMA_NO_NODE
,
3232 .dev
= pp
->dev
->dev
.parent
,
3233 .dma_dir
= xdp_prog
? DMA_BIDIRECTIONAL
: DMA_FROM_DEVICE
,
3234 .offset
= pp
->rx_offset_correction
,
3235 .max_len
= MVNETA_MAX_RX_BUF_SIZE
,
3239 rxq
->page_pool
= page_pool_create(&pp_params
);
3240 if (IS_ERR(rxq
->page_pool
)) {
3241 err
= PTR_ERR(rxq
->page_pool
);
3242 rxq
->page_pool
= NULL
;
3246 err
= xdp_rxq_info_reg(&rxq
->xdp_rxq
, pp
->dev
, rxq
->id
, 0);
3250 err
= xdp_rxq_info_reg_mem_model(&rxq
->xdp_rxq
, MEM_TYPE_PAGE_POOL
,
3253 goto err_unregister_rxq
;
3258 xdp_rxq_info_unreg(&rxq
->xdp_rxq
);
3260 page_pool_destroy(rxq
->page_pool
);
3261 rxq
->page_pool
= NULL
;
3265 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
3266 static int mvneta_rxq_fill(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
3271 err
= mvneta_create_page_pool(pp
, rxq
, num
);
3275 for (i
= 0; i
< num
; i
++) {
3276 memset(rxq
->descs
+ i
, 0, sizeof(struct mvneta_rx_desc
));
3277 if (mvneta_rx_refill(pp
, rxq
->descs
+ i
, rxq
,
3280 "%s:rxq %d, %d of %d buffs filled\n",
3281 __func__
, rxq
->id
, i
, num
);
3286 /* Add this number of RX descriptors as non occupied (ready to
3289 mvneta_rxq_non_occup_desc_add(pp
, rxq
, i
);
3294 /* Free all packets pending transmit from all TXQs and reset TX port */
3295 static void mvneta_tx_reset(struct mvneta_port
*pp
)
3299 /* free the skb's in the tx ring */
3300 for (queue
= 0; queue
< txq_number
; queue
++)
3301 mvneta_txq_done_force(pp
, &pp
->txqs
[queue
]);
3303 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
3304 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
3307 static void mvneta_rx_reset(struct mvneta_port
*pp
)
3309 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
3310 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
3313 /* Rx/Tx queue initialization/cleanup methods */
3315 static int mvneta_rxq_sw_init(struct mvneta_port
*pp
,
3316 struct mvneta_rx_queue
*rxq
)
3318 rxq
->size
= pp
->rx_ring_size
;
3320 /* Allocate memory for RX descriptors */
3321 rxq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
3322 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3323 &rxq
->descs_phys
, GFP_KERNEL
);
3327 rxq
->last_desc
= rxq
->size
- 1;
3332 static void mvneta_rxq_hw_init(struct mvneta_port
*pp
,
3333 struct mvneta_rx_queue
*rxq
)
3335 /* Set Rx descriptors queue starting address */
3336 mvreg_write(pp
, MVNETA_RXQ_BASE_ADDR_REG(rxq
->id
), rxq
->descs_phys
);
3337 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), rxq
->size
);
3339 /* Set coalescing pkts and time */
3340 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
3341 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
3345 mvneta_rxq_offset_set(pp
, rxq
, 0);
3346 mvneta_rxq_buf_size_set(pp
, rxq
, PAGE_SIZE
< SZ_64K
?
3347 MVNETA_MAX_RX_BUF_SIZE
:
3348 MVNETA_RX_BUF_SIZE(pp
->pkt_size
));
3349 mvneta_rxq_bm_disable(pp
, rxq
);
3350 mvneta_rxq_fill(pp
, rxq
, rxq
->size
);
3353 mvneta_rxq_offset_set(pp
, rxq
,
3354 NET_SKB_PAD
- pp
->rx_offset_correction
);
3356 mvneta_rxq_bm_enable(pp
, rxq
);
3357 /* Fill RXQ with buffers from RX pool */
3358 mvneta_rxq_long_pool_set(pp
, rxq
);
3359 mvneta_rxq_short_pool_set(pp
, rxq
);
3360 mvneta_rxq_non_occup_desc_add(pp
, rxq
, rxq
->size
);
3364 /* Create a specified RX queue */
3365 static int mvneta_rxq_init(struct mvneta_port
*pp
,
3366 struct mvneta_rx_queue
*rxq
)
3371 ret
= mvneta_rxq_sw_init(pp
, rxq
);
3375 mvneta_rxq_hw_init(pp
, rxq
);
3380 /* Cleanup Rx queue */
3381 static void mvneta_rxq_deinit(struct mvneta_port
*pp
,
3382 struct mvneta_rx_queue
*rxq
)
3384 mvneta_rxq_drop_pkts(pp
, rxq
);
3387 dma_free_coherent(pp
->dev
->dev
.parent
,
3388 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3394 rxq
->next_desc_to_proc
= 0;
3395 rxq
->descs_phys
= 0;
3396 rxq
->first_to_refill
= 0;
3397 rxq
->refill_num
= 0;
3400 static int mvneta_txq_sw_init(struct mvneta_port
*pp
,
3401 struct mvneta_tx_queue
*txq
)
3405 txq
->size
= pp
->tx_ring_size
;
3407 /* A queue must always have room for at least one skb.
3408 * Therefore, stop the queue when the free entries reaches
3409 * the maximum number of descriptors per skb.
3411 txq
->tx_stop_threshold
= txq
->size
- MVNETA_MAX_SKB_DESCS
;
3412 txq
->tx_wake_threshold
= txq
->tx_stop_threshold
/ 2;
3414 /* Allocate memory for TX descriptors */
3415 txq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
3416 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3417 &txq
->descs_phys
, GFP_KERNEL
);
3421 txq
->last_desc
= txq
->size
- 1;
3423 txq
->buf
= kmalloc_array(txq
->size
, sizeof(*txq
->buf
), GFP_KERNEL
);
3427 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3428 txq
->tso_hdrs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
3429 txq
->size
* TSO_HEADER_SIZE
,
3430 &txq
->tso_hdrs_phys
, GFP_KERNEL
);
3434 /* Setup XPS mapping */
3435 if (pp
->neta_armada3700
)
3437 else if (txq_number
> 1)
3438 cpu
= txq
->id
% num_present_cpus();
3440 cpu
= pp
->rxq_def
% num_present_cpus();
3441 cpumask_set_cpu(cpu
, &txq
->affinity_mask
);
3442 netif_set_xps_queue(pp
->dev
, &txq
->affinity_mask
, txq
->id
);
3447 static void mvneta_txq_hw_init(struct mvneta_port
*pp
,
3448 struct mvneta_tx_queue
*txq
)
3450 /* Set maximum bandwidth for enabled TXQs */
3451 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0x03ffffff);
3452 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0x3fffffff);
3454 /* Set Tx descriptors queue starting address */
3455 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), txq
->descs_phys
);
3456 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), txq
->size
);
3458 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
3461 /* Create and initialize a tx queue */
3462 static int mvneta_txq_init(struct mvneta_port
*pp
,
3463 struct mvneta_tx_queue
*txq
)
3467 ret
= mvneta_txq_sw_init(pp
, txq
);
3471 mvneta_txq_hw_init(pp
, txq
);
3476 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3477 static void mvneta_txq_sw_deinit(struct mvneta_port
*pp
,
3478 struct mvneta_tx_queue
*txq
)
3480 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
3485 dma_free_coherent(pp
->dev
->dev
.parent
,
3486 txq
->size
* TSO_HEADER_SIZE
,
3487 txq
->tso_hdrs
, txq
->tso_hdrs_phys
);
3489 dma_free_coherent(pp
->dev
->dev
.parent
,
3490 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3491 txq
->descs
, txq
->descs_phys
);
3493 netdev_tx_reset_queue(nq
);
3497 txq
->next_desc_to_proc
= 0;
3498 txq
->descs_phys
= 0;
3501 static void mvneta_txq_hw_deinit(struct mvneta_port
*pp
,
3502 struct mvneta_tx_queue
*txq
)
3504 /* Set minimum bandwidth for disabled TXQs */
3505 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0);
3506 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0);
3508 /* Set Tx descriptors queue starting address and size */
3509 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), 0);
3510 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), 0);
3513 static void mvneta_txq_deinit(struct mvneta_port
*pp
,
3514 struct mvneta_tx_queue
*txq
)
3516 mvneta_txq_sw_deinit(pp
, txq
);
3517 mvneta_txq_hw_deinit(pp
, txq
);
3520 /* Cleanup all Tx queues */
3521 static void mvneta_cleanup_txqs(struct mvneta_port
*pp
)
3525 for (queue
= 0; queue
< txq_number
; queue
++)
3526 mvneta_txq_deinit(pp
, &pp
->txqs
[queue
]);
3529 /* Cleanup all Rx queues */
3530 static void mvneta_cleanup_rxqs(struct mvneta_port
*pp
)
3534 for (queue
= 0; queue
< rxq_number
; queue
++)
3535 mvneta_rxq_deinit(pp
, &pp
->rxqs
[queue
]);
3539 /* Init all Rx queues */
3540 static int mvneta_setup_rxqs(struct mvneta_port
*pp
)
3544 for (queue
= 0; queue
< rxq_number
; queue
++) {
3545 int err
= mvneta_rxq_init(pp
, &pp
->rxqs
[queue
]);
3548 netdev_err(pp
->dev
, "%s: can't create rxq=%d\n",
3550 mvneta_cleanup_rxqs(pp
);
3558 /* Init all tx queues */
3559 static int mvneta_setup_txqs(struct mvneta_port
*pp
)
3563 for (queue
= 0; queue
< txq_number
; queue
++) {
3564 int err
= mvneta_txq_init(pp
, &pp
->txqs
[queue
]);
3566 netdev_err(pp
->dev
, "%s: can't create txq=%d\n",
3568 mvneta_cleanup_txqs(pp
);
3576 static int mvneta_comphy_init(struct mvneta_port
*pp
, phy_interface_t interface
)
3580 ret
= phy_set_mode_ext(pp
->comphy
, PHY_MODE_ETHERNET
, interface
);
3584 return phy_power_on(pp
->comphy
);
3587 static int mvneta_config_interface(struct mvneta_port
*pp
,
3588 phy_interface_t interface
)
3593 if (interface
== PHY_INTERFACE_MODE_SGMII
||
3594 interface
== PHY_INTERFACE_MODE_1000BASEX
||
3595 interface
== PHY_INTERFACE_MODE_2500BASEX
) {
3596 ret
= mvneta_comphy_init(pp
, interface
);
3599 switch (interface
) {
3600 case PHY_INTERFACE_MODE_QSGMII
:
3601 mvreg_write(pp
, MVNETA_SERDES_CFG
,
3602 MVNETA_QSGMII_SERDES_PROTO
);
3605 case PHY_INTERFACE_MODE_SGMII
:
3606 case PHY_INTERFACE_MODE_1000BASEX
:
3607 mvreg_write(pp
, MVNETA_SERDES_CFG
,
3608 MVNETA_SGMII_SERDES_PROTO
);
3611 case PHY_INTERFACE_MODE_2500BASEX
:
3612 mvreg_write(pp
, MVNETA_SERDES_CFG
,
3613 MVNETA_HSGMII_SERDES_PROTO
);
3620 pp
->phy_interface
= interface
;
3625 static void mvneta_start_dev(struct mvneta_port
*pp
)
3629 WARN_ON(mvneta_config_interface(pp
, pp
->phy_interface
));
3631 mvneta_max_rx_size_set(pp
, pp
->pkt_size
);
3632 mvneta_txq_max_tx_size_set(pp
, pp
->pkt_size
);
3634 /* start the Rx/Tx activity */
3635 mvneta_port_enable(pp
);
3637 if (!pp
->neta_armada3700
) {
3638 /* Enable polling on the port */
3639 for_each_online_cpu(cpu
) {
3640 struct mvneta_pcpu_port
*port
=
3641 per_cpu_ptr(pp
->ports
, cpu
);
3643 napi_enable(&port
->napi
);
3646 napi_enable(&pp
->napi
);
3649 /* Unmask interrupts. It has to be done from each CPU */
3650 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
3652 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
3653 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3654 MVNETA_CAUSE_LINK_CHANGE
);
3656 phylink_start(pp
->phylink
);
3658 /* We may have called phylink_speed_down before */
3659 phylink_speed_up(pp
->phylink
);
3661 netif_tx_start_all_queues(pp
->dev
);
3663 clear_bit(__MVNETA_DOWN
, &pp
->state
);
3666 static void mvneta_stop_dev(struct mvneta_port
*pp
)
3670 set_bit(__MVNETA_DOWN
, &pp
->state
);
3672 if (device_may_wakeup(&pp
->dev
->dev
))
3673 phylink_speed_down(pp
->phylink
, false);
3675 phylink_stop(pp
->phylink
);
3677 if (!pp
->neta_armada3700
) {
3678 for_each_online_cpu(cpu
) {
3679 struct mvneta_pcpu_port
*port
=
3680 per_cpu_ptr(pp
->ports
, cpu
);
3682 napi_disable(&port
->napi
);
3685 napi_disable(&pp
->napi
);
3688 netif_carrier_off(pp
->dev
);
3690 mvneta_port_down(pp
);
3691 netif_tx_stop_all_queues(pp
->dev
);
3693 /* Stop the port activity */
3694 mvneta_port_disable(pp
);
3696 /* Clear all ethernet port interrupts */
3697 on_each_cpu(mvneta_percpu_clear_intr_cause
, pp
, true);
3699 /* Mask all ethernet port interrupts */
3700 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
3702 mvneta_tx_reset(pp
);
3703 mvneta_rx_reset(pp
);
3705 WARN_ON(phy_power_off(pp
->comphy
));
3708 static void mvneta_percpu_enable(void *arg
)
3710 struct mvneta_port
*pp
= arg
;
3712 enable_percpu_irq(pp
->dev
->irq
, IRQ_TYPE_NONE
);
3715 static void mvneta_percpu_disable(void *arg
)
3717 struct mvneta_port
*pp
= arg
;
3719 disable_percpu_irq(pp
->dev
->irq
);
3722 /* Change the device mtu */
3723 static int mvneta_change_mtu(struct net_device
*dev
, int mtu
)
3725 struct mvneta_port
*pp
= netdev_priv(dev
);
3728 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu
), 8)) {
3729 netdev_info(dev
, "Illegal MTU value %d, rounding to %d\n",
3730 mtu
, ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8));
3731 mtu
= ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8);
3734 if (pp
->xdp_prog
&& mtu
> MVNETA_MAX_RX_BUF_SIZE
) {
3735 netdev_info(dev
, "Illegal MTU value %d for XDP mode\n", mtu
);
3741 if (!netif_running(dev
)) {
3743 mvneta_bm_update_mtu(pp
, mtu
);
3745 netdev_update_features(dev
);
3749 /* The interface is running, so we have to force a
3750 * reallocation of the queues
3752 mvneta_stop_dev(pp
);
3753 on_each_cpu(mvneta_percpu_disable
, pp
, true);
3755 mvneta_cleanup_txqs(pp
);
3756 mvneta_cleanup_rxqs(pp
);
3759 mvneta_bm_update_mtu(pp
, mtu
);
3761 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(dev
->mtu
);
3763 ret
= mvneta_setup_rxqs(pp
);
3765 netdev_err(dev
, "unable to setup rxqs after MTU change\n");
3769 ret
= mvneta_setup_txqs(pp
);
3771 netdev_err(dev
, "unable to setup txqs after MTU change\n");
3775 on_each_cpu(mvneta_percpu_enable
, pp
, true);
3776 mvneta_start_dev(pp
);
3778 netdev_update_features(dev
);
3783 static netdev_features_t
mvneta_fix_features(struct net_device
*dev
,
3784 netdev_features_t features
)
3786 struct mvneta_port
*pp
= netdev_priv(dev
);
3788 if (pp
->tx_csum_limit
&& dev
->mtu
> pp
->tx_csum_limit
) {
3789 features
&= ~(NETIF_F_IP_CSUM
| NETIF_F_TSO
);
3791 "Disable IP checksum for MTU greater than %dB\n",
3798 /* Get mac address */
3799 static void mvneta_get_mac_addr(struct mvneta_port
*pp
, unsigned char *addr
)
3801 u32 mac_addr_l
, mac_addr_h
;
3803 mac_addr_l
= mvreg_read(pp
, MVNETA_MAC_ADDR_LOW
);
3804 mac_addr_h
= mvreg_read(pp
, MVNETA_MAC_ADDR_HIGH
);
3805 addr
[0] = (mac_addr_h
>> 24) & 0xFF;
3806 addr
[1] = (mac_addr_h
>> 16) & 0xFF;
3807 addr
[2] = (mac_addr_h
>> 8) & 0xFF;
3808 addr
[3] = mac_addr_h
& 0xFF;
3809 addr
[4] = (mac_addr_l
>> 8) & 0xFF;
3810 addr
[5] = mac_addr_l
& 0xFF;
3813 /* Handle setting mac address */
3814 static int mvneta_set_mac_addr(struct net_device
*dev
, void *addr
)
3816 struct mvneta_port
*pp
= netdev_priv(dev
);
3817 struct sockaddr
*sockaddr
= addr
;
3820 ret
= eth_prepare_mac_addr_change(dev
, addr
);
3823 /* Remove previous address table entry */
3824 mvneta_mac_addr_set(pp
, dev
->dev_addr
, -1);
3826 /* Set new addr in hw */
3827 mvneta_mac_addr_set(pp
, sockaddr
->sa_data
, pp
->rxq_def
);
3829 eth_commit_mac_addr_change(dev
, addr
);
3833 static void mvneta_validate(struct phylink_config
*config
,
3834 unsigned long *supported
,
3835 struct phylink_link_state
*state
)
3837 struct net_device
*ndev
= to_net_dev(config
->dev
);
3838 struct mvneta_port
*pp
= netdev_priv(ndev
);
3839 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
3841 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3842 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
3843 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
3844 state
->interface
!= PHY_INTERFACE_MODE_SGMII
&&
3845 !phy_interface_mode_is_8023z(state
->interface
) &&
3846 !phy_interface_mode_is_rgmii(state
->interface
)) {
3847 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
3851 /* Allow all the expected bits */
3852 phylink_set(mask
, Autoneg
);
3853 phylink_set_port_modes(mask
);
3855 /* Asymmetric pause is unsupported */
3856 phylink_set(mask
, Pause
);
3858 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3859 if (pp
->comphy
|| state
->interface
!= PHY_INTERFACE_MODE_2500BASEX
) {
3860 phylink_set(mask
, 1000baseT_Full
);
3861 phylink_set(mask
, 1000baseX_Full
);
3863 if (pp
->comphy
|| state
->interface
== PHY_INTERFACE_MODE_2500BASEX
) {
3864 phylink_set(mask
, 2500baseT_Full
);
3865 phylink_set(mask
, 2500baseX_Full
);
3868 if (!phy_interface_mode_is_8023z(state
->interface
)) {
3869 /* 10M and 100M are only supported in non-802.3z mode */
3870 phylink_set(mask
, 10baseT_Half
);
3871 phylink_set(mask
, 10baseT_Full
);
3872 phylink_set(mask
, 100baseT_Half
);
3873 phylink_set(mask
, 100baseT_Full
);
3876 bitmap_and(supported
, supported
, mask
,
3877 __ETHTOOL_LINK_MODE_MASK_NBITS
);
3878 bitmap_and(state
->advertising
, state
->advertising
, mask
,
3879 __ETHTOOL_LINK_MODE_MASK_NBITS
);
3881 /* We can only operate at 2500BaseX or 1000BaseX. If requested
3882 * to advertise both, only report advertising at 2500BaseX.
3884 phylink_helper_basex_speed(state
);
3887 static void mvneta_mac_pcs_get_state(struct phylink_config
*config
,
3888 struct phylink_link_state
*state
)
3890 struct net_device
*ndev
= to_net_dev(config
->dev
);
3891 struct mvneta_port
*pp
= netdev_priv(ndev
);
3894 gmac_stat
= mvreg_read(pp
, MVNETA_GMAC_STATUS
);
3896 if (gmac_stat
& MVNETA_GMAC_SPEED_1000
)
3898 state
->interface
== PHY_INTERFACE_MODE_2500BASEX
?
3899 SPEED_2500
: SPEED_1000
;
3900 else if (gmac_stat
& MVNETA_GMAC_SPEED_100
)
3901 state
->speed
= SPEED_100
;
3903 state
->speed
= SPEED_10
;
3905 state
->an_complete
= !!(gmac_stat
& MVNETA_GMAC_AN_COMPLETE
);
3906 state
->link
= !!(gmac_stat
& MVNETA_GMAC_LINK_UP
);
3907 state
->duplex
= !!(gmac_stat
& MVNETA_GMAC_FULL_DUPLEX
);
3910 if (gmac_stat
& MVNETA_GMAC_RX_FLOW_CTRL_ENABLE
)
3911 state
->pause
|= MLO_PAUSE_RX
;
3912 if (gmac_stat
& MVNETA_GMAC_TX_FLOW_CTRL_ENABLE
)
3913 state
->pause
|= MLO_PAUSE_TX
;
3916 static void mvneta_mac_an_restart(struct phylink_config
*config
)
3918 struct net_device
*ndev
= to_net_dev(config
->dev
);
3919 struct mvneta_port
*pp
= netdev_priv(ndev
);
3920 u32 gmac_an
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3922 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3923 gmac_an
| MVNETA_GMAC_INBAND_RESTART_AN
);
3924 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3925 gmac_an
& ~MVNETA_GMAC_INBAND_RESTART_AN
);
3928 static void mvneta_mac_config(struct phylink_config
*config
, unsigned int mode
,
3929 const struct phylink_link_state
*state
)
3931 struct net_device
*ndev
= to_net_dev(config
->dev
);
3932 struct mvneta_port
*pp
= netdev_priv(ndev
);
3933 u32 new_ctrl0
, gmac_ctrl0
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
3934 u32 new_ctrl2
, gmac_ctrl2
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
3935 u32 new_ctrl4
, gmac_ctrl4
= mvreg_read(pp
, MVNETA_GMAC_CTRL_4
);
3936 u32 new_clk
, gmac_clk
= mvreg_read(pp
, MVNETA_GMAC_CLOCK_DIVIDER
);
3937 u32 new_an
, gmac_an
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3939 new_ctrl0
= gmac_ctrl0
& ~MVNETA_GMAC0_PORT_1000BASE_X
;
3940 new_ctrl2
= gmac_ctrl2
& ~(MVNETA_GMAC2_INBAND_AN_ENABLE
|
3941 MVNETA_GMAC2_PORT_RESET
);
3942 new_ctrl4
= gmac_ctrl4
& ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE
);
3943 new_clk
= gmac_clk
& ~MVNETA_GMAC_1MS_CLOCK_ENABLE
;
3944 new_an
= gmac_an
& ~(MVNETA_GMAC_INBAND_AN_ENABLE
|
3945 MVNETA_GMAC_INBAND_RESTART_AN
|
3946 MVNETA_GMAC_AN_SPEED_EN
|
3947 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL
|
3948 MVNETA_GMAC_AN_FLOW_CTRL_EN
|
3949 MVNETA_GMAC_AN_DUPLEX_EN
);
3951 /* Even though it might look weird, when we're configured in
3952 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3954 new_ctrl2
|= MVNETA_GMAC2_PORT_RGMII
;
3956 if (state
->interface
== PHY_INTERFACE_MODE_QSGMII
||
3957 state
->interface
== PHY_INTERFACE_MODE_SGMII
||
3958 phy_interface_mode_is_8023z(state
->interface
))
3959 new_ctrl2
|= MVNETA_GMAC2_PCS_ENABLE
;
3961 if (phylink_test(state
->advertising
, Pause
))
3962 new_an
|= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL
;
3964 if (!phylink_autoneg_inband(mode
)) {
3965 /* Phy or fixed speed - nothing to do, leave the
3966 * configured speed, duplex and flow control as-is.
3968 } else if (state
->interface
== PHY_INTERFACE_MODE_SGMII
) {
3969 /* SGMII mode receives the state from the PHY */
3970 new_ctrl2
|= MVNETA_GMAC2_INBAND_AN_ENABLE
;
3971 new_clk
|= MVNETA_GMAC_1MS_CLOCK_ENABLE
;
3972 new_an
= (new_an
& ~(MVNETA_GMAC_FORCE_LINK_DOWN
|
3973 MVNETA_GMAC_FORCE_LINK_PASS
|
3974 MVNETA_GMAC_CONFIG_MII_SPEED
|
3975 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3976 MVNETA_GMAC_CONFIG_FULL_DUPLEX
)) |
3977 MVNETA_GMAC_INBAND_AN_ENABLE
|
3978 MVNETA_GMAC_AN_SPEED_EN
|
3979 MVNETA_GMAC_AN_DUPLEX_EN
;
3981 /* 802.3z negotiation - only 1000base-X */
3982 new_ctrl0
|= MVNETA_GMAC0_PORT_1000BASE_X
;
3983 new_clk
|= MVNETA_GMAC_1MS_CLOCK_ENABLE
;
3984 new_an
= (new_an
& ~(MVNETA_GMAC_FORCE_LINK_DOWN
|
3985 MVNETA_GMAC_FORCE_LINK_PASS
|
3986 MVNETA_GMAC_CONFIG_MII_SPEED
)) |
3987 MVNETA_GMAC_INBAND_AN_ENABLE
|
3988 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3989 /* The MAC only supports FD mode */
3990 MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
3992 if (state
->pause
& MLO_PAUSE_AN
&& state
->an_enabled
)
3993 new_an
|= MVNETA_GMAC_AN_FLOW_CTRL_EN
;
3996 /* Armada 370 documentation says we can only change the port mode
3997 * and in-band enable when the link is down, so force it down
3998 * while making these changes. We also do this for GMAC_CTRL2 */
3999 if ((new_ctrl0
^ gmac_ctrl0
) & MVNETA_GMAC0_PORT_1000BASE_X
||
4000 (new_ctrl2
^ gmac_ctrl2
) & MVNETA_GMAC2_INBAND_AN_ENABLE
||
4001 (new_an
^ gmac_an
) & MVNETA_GMAC_INBAND_AN_ENABLE
) {
4002 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
4003 (gmac_an
& ~MVNETA_GMAC_FORCE_LINK_PASS
) |
4004 MVNETA_GMAC_FORCE_LINK_DOWN
);
4008 /* When at 2.5G, the link partner can send frames with shortened
4011 if (state
->interface
== PHY_INTERFACE_MODE_2500BASEX
)
4012 new_ctrl4
|= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE
;
4014 if (pp
->phy_interface
!= state
->interface
) {
4016 WARN_ON(phy_power_off(pp
->comphy
));
4017 WARN_ON(mvneta_config_interface(pp
, state
->interface
));
4020 if (new_ctrl0
!= gmac_ctrl0
)
4021 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, new_ctrl0
);
4022 if (new_ctrl2
!= gmac_ctrl2
)
4023 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, new_ctrl2
);
4024 if (new_ctrl4
!= gmac_ctrl4
)
4025 mvreg_write(pp
, MVNETA_GMAC_CTRL_4
, new_ctrl4
);
4026 if (new_clk
!= gmac_clk
)
4027 mvreg_write(pp
, MVNETA_GMAC_CLOCK_DIVIDER
, new_clk
);
4028 if (new_an
!= gmac_an
)
4029 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, new_an
);
4031 if (gmac_ctrl2
& MVNETA_GMAC2_PORT_RESET
) {
4032 while ((mvreg_read(pp
, MVNETA_GMAC_CTRL_2
) &
4033 MVNETA_GMAC2_PORT_RESET
) != 0)
4038 static void mvneta_set_eee(struct mvneta_port
*pp
, bool enable
)
4042 lpi_ctl1
= mvreg_read(pp
, MVNETA_LPI_CTRL_1
);
4044 lpi_ctl1
|= MVNETA_LPI_REQUEST_ENABLE
;
4046 lpi_ctl1
&= ~MVNETA_LPI_REQUEST_ENABLE
;
4047 mvreg_write(pp
, MVNETA_LPI_CTRL_1
, lpi_ctl1
);
4050 static void mvneta_mac_link_down(struct phylink_config
*config
,
4051 unsigned int mode
, phy_interface_t interface
)
4053 struct net_device
*ndev
= to_net_dev(config
->dev
);
4054 struct mvneta_port
*pp
= netdev_priv(ndev
);
4057 mvneta_port_down(pp
);
4059 if (!phylink_autoneg_inband(mode
)) {
4060 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
4061 val
&= ~MVNETA_GMAC_FORCE_LINK_PASS
;
4062 val
|= MVNETA_GMAC_FORCE_LINK_DOWN
;
4063 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
4066 pp
->eee_active
= false;
4067 mvneta_set_eee(pp
, false);
4070 static void mvneta_mac_link_up(struct phylink_config
*config
,
4071 struct phy_device
*phy
,
4072 unsigned int mode
, phy_interface_t interface
,
4073 int speed
, int duplex
,
4074 bool tx_pause
, bool rx_pause
)
4076 struct net_device
*ndev
= to_net_dev(config
->dev
);
4077 struct mvneta_port
*pp
= netdev_priv(ndev
);
4080 if (!phylink_autoneg_inband(mode
)) {
4081 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
4082 val
&= ~(MVNETA_GMAC_FORCE_LINK_DOWN
|
4083 MVNETA_GMAC_CONFIG_MII_SPEED
|
4084 MVNETA_GMAC_CONFIG_GMII_SPEED
|
4085 MVNETA_GMAC_CONFIG_FLOW_CTRL
|
4086 MVNETA_GMAC_CONFIG_FULL_DUPLEX
);
4087 val
|= MVNETA_GMAC_FORCE_LINK_PASS
;
4089 if (speed
== SPEED_1000
|| speed
== SPEED_2500
)
4090 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
4091 else if (speed
== SPEED_100
)
4092 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
4094 if (duplex
== DUPLEX_FULL
)
4095 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
4097 if (tx_pause
|| rx_pause
)
4098 val
|= MVNETA_GMAC_CONFIG_FLOW_CTRL
;
4100 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
4102 /* When inband doesn't cover flow control or flow control is
4103 * disabled, we need to manually configure it. This bit will
4104 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
4106 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
4107 val
&= ~MVNETA_GMAC_CONFIG_FLOW_CTRL
;
4109 if (tx_pause
|| rx_pause
)
4110 val
|= MVNETA_GMAC_CONFIG_FLOW_CTRL
;
4112 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
4117 if (phy
&& pp
->eee_enabled
) {
4118 pp
->eee_active
= phy_init_eee(phy
, 0) >= 0;
4119 mvneta_set_eee(pp
, pp
->eee_active
&& pp
->tx_lpi_enabled
);
4123 static const struct phylink_mac_ops mvneta_phylink_ops
= {
4124 .validate
= mvneta_validate
,
4125 .mac_pcs_get_state
= mvneta_mac_pcs_get_state
,
4126 .mac_an_restart
= mvneta_mac_an_restart
,
4127 .mac_config
= mvneta_mac_config
,
4128 .mac_link_down
= mvneta_mac_link_down
,
4129 .mac_link_up
= mvneta_mac_link_up
,
4132 static int mvneta_mdio_probe(struct mvneta_port
*pp
)
4134 struct ethtool_wolinfo wol
= { .cmd
= ETHTOOL_GWOL
};
4135 int err
= phylink_of_phy_connect(pp
->phylink
, pp
->dn
, 0);
4138 netdev_err(pp
->dev
, "could not attach PHY: %d\n", err
);
4140 phylink_ethtool_get_wol(pp
->phylink
, &wol
);
4141 device_set_wakeup_capable(&pp
->dev
->dev
, !!wol
.supported
);
4143 /* PHY WoL may be enabled but device wakeup disabled */
4145 device_set_wakeup_enable(&pp
->dev
->dev
, !!wol
.wolopts
);
4150 static void mvneta_mdio_remove(struct mvneta_port
*pp
)
4152 phylink_disconnect_phy(pp
->phylink
);
4155 /* Electing a CPU must be done in an atomic way: it should be done
4156 * after or before the removal/insertion of a CPU and this function is
4159 static void mvneta_percpu_elect(struct mvneta_port
*pp
)
4161 int elected_cpu
= 0, max_cpu
, cpu
, i
= 0;
4163 /* Use the cpu associated to the rxq when it is online, in all
4164 * the other cases, use the cpu 0 which can't be offline.
4166 if (cpu_online(pp
->rxq_def
))
4167 elected_cpu
= pp
->rxq_def
;
4169 max_cpu
= num_present_cpus();
4171 for_each_online_cpu(cpu
) {
4172 int rxq_map
= 0, txq_map
= 0;
4175 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
4176 if ((rxq
% max_cpu
) == cpu
)
4177 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(rxq
);
4179 if (cpu
== elected_cpu
)
4180 /* Map the default receive queue queue to the
4183 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(pp
->rxq_def
);
4185 /* We update the TX queue map only if we have one
4186 * queue. In this case we associate the TX queue to
4187 * the CPU bound to the default RX queue
4189 if (txq_number
== 1)
4190 txq_map
= (cpu
== elected_cpu
) ?
4191 MVNETA_CPU_TXQ_ACCESS(1) : 0;
4193 txq_map
= mvreg_read(pp
, MVNETA_CPU_MAP(cpu
)) &
4194 MVNETA_CPU_TXQ_ACCESS_ALL_MASK
;
4196 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
), rxq_map
| txq_map
);
4198 /* Update the interrupt mask on each CPU according the
4201 smp_call_function_single(cpu
, mvneta_percpu_unmask_interrupt
,
4208 static int mvneta_cpu_online(unsigned int cpu
, struct hlist_node
*node
)
4211 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
4213 struct mvneta_pcpu_port
*port
= per_cpu_ptr(pp
->ports
, cpu
);
4215 /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts
4216 * are routed to CPU 0, so we don't need all the cpu-hotplug support
4218 if (pp
->neta_armada3700
)
4221 spin_lock(&pp
->lock
);
4223 * Configuring the driver for a new CPU while the driver is
4224 * stopping is racy, so just avoid it.
4226 if (pp
->is_stopped
) {
4227 spin_unlock(&pp
->lock
);
4230 netif_tx_stop_all_queues(pp
->dev
);
4233 * We have to synchronise on tha napi of each CPU except the one
4234 * just being woken up
4236 for_each_online_cpu(other_cpu
) {
4237 if (other_cpu
!= cpu
) {
4238 struct mvneta_pcpu_port
*other_port
=
4239 per_cpu_ptr(pp
->ports
, other_cpu
);
4241 napi_synchronize(&other_port
->napi
);
4245 /* Mask all ethernet port interrupts */
4246 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
4247 napi_enable(&port
->napi
);
4250 * Enable per-CPU interrupts on the CPU that is
4253 mvneta_percpu_enable(pp
);
4256 * Enable per-CPU interrupt on the one CPU we care
4259 mvneta_percpu_elect(pp
);
4261 /* Unmask all ethernet port interrupts */
4262 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
4263 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
4264 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
4265 MVNETA_CAUSE_LINK_CHANGE
);
4266 netif_tx_start_all_queues(pp
->dev
);
4267 spin_unlock(&pp
->lock
);
4271 static int mvneta_cpu_down_prepare(unsigned int cpu
, struct hlist_node
*node
)
4273 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
4275 struct mvneta_pcpu_port
*port
= per_cpu_ptr(pp
->ports
, cpu
);
4278 * Thanks to this lock we are sure that any pending cpu election is
4281 spin_lock(&pp
->lock
);
4282 /* Mask all ethernet port interrupts */
4283 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
4284 spin_unlock(&pp
->lock
);
4286 napi_synchronize(&port
->napi
);
4287 napi_disable(&port
->napi
);
4288 /* Disable per-CPU interrupts on the CPU that is brought down. */
4289 mvneta_percpu_disable(pp
);
4293 static int mvneta_cpu_dead(unsigned int cpu
, struct hlist_node
*node
)
4295 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
4298 /* Check if a new CPU must be elected now this on is down */
4299 spin_lock(&pp
->lock
);
4300 mvneta_percpu_elect(pp
);
4301 spin_unlock(&pp
->lock
);
4302 /* Unmask all ethernet port interrupts */
4303 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
4304 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
4305 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
4306 MVNETA_CAUSE_LINK_CHANGE
);
4307 netif_tx_start_all_queues(pp
->dev
);
4311 static int mvneta_open(struct net_device
*dev
)
4313 struct mvneta_port
*pp
= netdev_priv(dev
);
4316 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
);
4318 ret
= mvneta_setup_rxqs(pp
);
4322 ret
= mvneta_setup_txqs(pp
);
4324 goto err_cleanup_rxqs
;
4326 /* Connect to port interrupt line */
4327 if (pp
->neta_armada3700
)
4328 ret
= request_irq(pp
->dev
->irq
, mvneta_isr
, 0,
4331 ret
= request_percpu_irq(pp
->dev
->irq
, mvneta_percpu_isr
,
4332 dev
->name
, pp
->ports
);
4334 netdev_err(pp
->dev
, "cannot request irq %d\n", pp
->dev
->irq
);
4335 goto err_cleanup_txqs
;
4338 if (!pp
->neta_armada3700
) {
4339 /* Enable per-CPU interrupt on all the CPU to handle our RX
4342 on_each_cpu(mvneta_percpu_enable
, pp
, true);
4344 pp
->is_stopped
= false;
4345 /* Register a CPU notifier to handle the case where our CPU
4346 * might be taken offline.
4348 ret
= cpuhp_state_add_instance_nocalls(online_hpstate
,
4353 ret
= cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
4356 goto err_free_online_hp
;
4359 ret
= mvneta_mdio_probe(pp
);
4361 netdev_err(dev
, "cannot probe MDIO bus\n");
4362 goto err_free_dead_hp
;
4365 mvneta_start_dev(pp
);
4370 if (!pp
->neta_armada3700
)
4371 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
4374 if (!pp
->neta_armada3700
)
4375 cpuhp_state_remove_instance_nocalls(online_hpstate
,
4378 if (pp
->neta_armada3700
) {
4379 free_irq(pp
->dev
->irq
, pp
);
4381 on_each_cpu(mvneta_percpu_disable
, pp
, true);
4382 free_percpu_irq(pp
->dev
->irq
, pp
->ports
);
4385 mvneta_cleanup_txqs(pp
);
4387 mvneta_cleanup_rxqs(pp
);
4391 /* Stop the port, free port interrupt line */
4392 static int mvneta_stop(struct net_device
*dev
)
4394 struct mvneta_port
*pp
= netdev_priv(dev
);
4396 if (!pp
->neta_armada3700
) {
4397 /* Inform that we are stopping so we don't want to setup the
4398 * driver for new CPUs in the notifiers. The code of the
4399 * notifier for CPU online is protected by the same spinlock,
4400 * so when we get the lock, the notifer work is done.
4402 spin_lock(&pp
->lock
);
4403 pp
->is_stopped
= true;
4404 spin_unlock(&pp
->lock
);
4406 mvneta_stop_dev(pp
);
4407 mvneta_mdio_remove(pp
);
4409 cpuhp_state_remove_instance_nocalls(online_hpstate
,
4411 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
4413 on_each_cpu(mvneta_percpu_disable
, pp
, true);
4414 free_percpu_irq(dev
->irq
, pp
->ports
);
4416 mvneta_stop_dev(pp
);
4417 mvneta_mdio_remove(pp
);
4418 free_irq(dev
->irq
, pp
);
4421 mvneta_cleanup_rxqs(pp
);
4422 mvneta_cleanup_txqs(pp
);
4427 static int mvneta_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4429 struct mvneta_port
*pp
= netdev_priv(dev
);
4431 return phylink_mii_ioctl(pp
->phylink
, ifr
, cmd
);
4434 static int mvneta_xdp_setup(struct net_device
*dev
, struct bpf_prog
*prog
,
4435 struct netlink_ext_ack
*extack
)
4437 bool need_update
, running
= netif_running(dev
);
4438 struct mvneta_port
*pp
= netdev_priv(dev
);
4439 struct bpf_prog
*old_prog
;
4441 if (prog
&& dev
->mtu
> MVNETA_MAX_RX_BUF_SIZE
) {
4442 NL_SET_ERR_MSG_MOD(extack
, "MTU too large for XDP");
4447 NL_SET_ERR_MSG_MOD(extack
,
4448 "Hardware Buffer Management not supported on XDP");
4452 need_update
= !!pp
->xdp_prog
!= !!prog
;
4453 if (running
&& need_update
)
4456 old_prog
= xchg(&pp
->xdp_prog
, prog
);
4458 bpf_prog_put(old_prog
);
4460 if (running
&& need_update
)
4461 return mvneta_open(dev
);
4466 static int mvneta_xdp(struct net_device
*dev
, struct netdev_bpf
*xdp
)
4468 switch (xdp
->command
) {
4469 case XDP_SETUP_PROG
:
4470 return mvneta_xdp_setup(dev
, xdp
->prog
, xdp
->extack
);
4476 /* Ethtool methods */
4478 /* Set link ksettings (phy address, speed) for ethtools */
4480 mvneta_ethtool_set_link_ksettings(struct net_device
*ndev
,
4481 const struct ethtool_link_ksettings
*cmd
)
4483 struct mvneta_port
*pp
= netdev_priv(ndev
);
4485 return phylink_ethtool_ksettings_set(pp
->phylink
, cmd
);
4488 /* Get link ksettings for ethtools */
4490 mvneta_ethtool_get_link_ksettings(struct net_device
*ndev
,
4491 struct ethtool_link_ksettings
*cmd
)
4493 struct mvneta_port
*pp
= netdev_priv(ndev
);
4495 return phylink_ethtool_ksettings_get(pp
->phylink
, cmd
);
4498 static int mvneta_ethtool_nway_reset(struct net_device
*dev
)
4500 struct mvneta_port
*pp
= netdev_priv(dev
);
4502 return phylink_ethtool_nway_reset(pp
->phylink
);
4505 /* Set interrupt coalescing for ethtools */
4506 static int mvneta_ethtool_set_coalesce(struct net_device
*dev
,
4507 struct ethtool_coalesce
*c
)
4509 struct mvneta_port
*pp
= netdev_priv(dev
);
4512 for (queue
= 0; queue
< rxq_number
; queue
++) {
4513 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
4514 rxq
->time_coal
= c
->rx_coalesce_usecs
;
4515 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
4516 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
4517 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
4520 for (queue
= 0; queue
< txq_number
; queue
++) {
4521 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
4522 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
4523 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
4529 /* get coalescing for ethtools */
4530 static int mvneta_ethtool_get_coalesce(struct net_device
*dev
,
4531 struct ethtool_coalesce
*c
)
4533 struct mvneta_port
*pp
= netdev_priv(dev
);
4535 c
->rx_coalesce_usecs
= pp
->rxqs
[0].time_coal
;
4536 c
->rx_max_coalesced_frames
= pp
->rxqs
[0].pkts_coal
;
4538 c
->tx_max_coalesced_frames
= pp
->txqs
[0].done_pkts_coal
;
4543 static void mvneta_ethtool_get_drvinfo(struct net_device
*dev
,
4544 struct ethtool_drvinfo
*drvinfo
)
4546 strlcpy(drvinfo
->driver
, MVNETA_DRIVER_NAME
,
4547 sizeof(drvinfo
->driver
));
4548 strlcpy(drvinfo
->version
, MVNETA_DRIVER_VERSION
,
4549 sizeof(drvinfo
->version
));
4550 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
4551 sizeof(drvinfo
->bus_info
));
4555 static void mvneta_ethtool_get_ringparam(struct net_device
*netdev
,
4556 struct ethtool_ringparam
*ring
)
4558 struct mvneta_port
*pp
= netdev_priv(netdev
);
4560 ring
->rx_max_pending
= MVNETA_MAX_RXD
;
4561 ring
->tx_max_pending
= MVNETA_MAX_TXD
;
4562 ring
->rx_pending
= pp
->rx_ring_size
;
4563 ring
->tx_pending
= pp
->tx_ring_size
;
4566 static int mvneta_ethtool_set_ringparam(struct net_device
*dev
,
4567 struct ethtool_ringparam
*ring
)
4569 struct mvneta_port
*pp
= netdev_priv(dev
);
4571 if ((ring
->rx_pending
== 0) || (ring
->tx_pending
== 0))
4573 pp
->rx_ring_size
= ring
->rx_pending
< MVNETA_MAX_RXD
?
4574 ring
->rx_pending
: MVNETA_MAX_RXD
;
4576 pp
->tx_ring_size
= clamp_t(u16
, ring
->tx_pending
,
4577 MVNETA_MAX_SKB_DESCS
* 2, MVNETA_MAX_TXD
);
4578 if (pp
->tx_ring_size
!= ring
->tx_pending
)
4579 netdev_warn(dev
, "TX queue size set to %u (requested %u)\n",
4580 pp
->tx_ring_size
, ring
->tx_pending
);
4582 if (netif_running(dev
)) {
4584 if (mvneta_open(dev
)) {
4586 "error on opening device after ring param change\n");
4594 static void mvneta_ethtool_get_pauseparam(struct net_device
*dev
,
4595 struct ethtool_pauseparam
*pause
)
4597 struct mvneta_port
*pp
= netdev_priv(dev
);
4599 phylink_ethtool_get_pauseparam(pp
->phylink
, pause
);
4602 static int mvneta_ethtool_set_pauseparam(struct net_device
*dev
,
4603 struct ethtool_pauseparam
*pause
)
4605 struct mvneta_port
*pp
= netdev_priv(dev
);
4607 return phylink_ethtool_set_pauseparam(pp
->phylink
, pause
);
4610 static void mvneta_ethtool_get_strings(struct net_device
*netdev
, u32 sset
,
4613 if (sset
== ETH_SS_STATS
) {
4616 for (i
= 0; i
< ARRAY_SIZE(mvneta_statistics
); i
++)
4617 memcpy(data
+ i
* ETH_GSTRING_LEN
,
4618 mvneta_statistics
[i
].name
, ETH_GSTRING_LEN
);
4623 mvneta_ethtool_update_pcpu_stats(struct mvneta_port
*pp
,
4624 struct mvneta_ethtool_stats
*es
)
4629 for_each_possible_cpu(cpu
) {
4630 struct mvneta_pcpu_stats
*stats
;
4631 u64 skb_alloc_error
;
4641 stats
= per_cpu_ptr(pp
->stats
, cpu
);
4643 start
= u64_stats_fetch_begin_irq(&stats
->syncp
);
4644 skb_alloc_error
= stats
->es
.skb_alloc_error
;
4645 refill_error
= stats
->es
.refill_error
;
4646 xdp_redirect
= stats
->es
.ps
.xdp_redirect
;
4647 xdp_pass
= stats
->es
.ps
.xdp_pass
;
4648 xdp_drop
= stats
->es
.ps
.xdp_drop
;
4649 xdp_xmit
= stats
->es
.ps
.xdp_xmit
;
4650 xdp_xmit_err
= stats
->es
.ps
.xdp_xmit_err
;
4651 xdp_tx
= stats
->es
.ps
.xdp_tx
;
4652 xdp_tx_err
= stats
->es
.ps
.xdp_tx_err
;
4653 } while (u64_stats_fetch_retry_irq(&stats
->syncp
, start
));
4655 es
->skb_alloc_error
+= skb_alloc_error
;
4656 es
->refill_error
+= refill_error
;
4657 es
->ps
.xdp_redirect
+= xdp_redirect
;
4658 es
->ps
.xdp_pass
+= xdp_pass
;
4659 es
->ps
.xdp_drop
+= xdp_drop
;
4660 es
->ps
.xdp_xmit
+= xdp_xmit
;
4661 es
->ps
.xdp_xmit_err
+= xdp_xmit_err
;
4662 es
->ps
.xdp_tx
+= xdp_tx
;
4663 es
->ps
.xdp_tx_err
+= xdp_tx_err
;
4667 static void mvneta_ethtool_update_stats(struct mvneta_port
*pp
)
4669 struct mvneta_ethtool_stats stats
= {};
4670 const struct mvneta_statistic
*s
;
4671 void __iomem
*base
= pp
->base
;
4676 mvneta_ethtool_update_pcpu_stats(pp
, &stats
);
4677 for (i
= 0, s
= mvneta_statistics
;
4678 s
< mvneta_statistics
+ ARRAY_SIZE(mvneta_statistics
);
4682 val
= readl_relaxed(base
+ s
->offset
);
4683 pp
->ethtool_stats
[i
] += val
;
4686 /* Docs say to read low 32-bit then high */
4687 low
= readl_relaxed(base
+ s
->offset
);
4688 high
= readl_relaxed(base
+ s
->offset
+ 4);
4689 val
= (u64
)high
<< 32 | low
;
4690 pp
->ethtool_stats
[i
] += val
;
4693 switch (s
->offset
) {
4694 case ETHTOOL_STAT_EEE_WAKEUP
:
4695 val
= phylink_get_eee_err(pp
->phylink
);
4696 pp
->ethtool_stats
[i
] += val
;
4698 case ETHTOOL_STAT_SKB_ALLOC_ERR
:
4699 pp
->ethtool_stats
[i
] = stats
.skb_alloc_error
;
4701 case ETHTOOL_STAT_REFILL_ERR
:
4702 pp
->ethtool_stats
[i
] = stats
.refill_error
;
4704 case ETHTOOL_XDP_REDIRECT
:
4705 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_redirect
;
4707 case ETHTOOL_XDP_PASS
:
4708 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_pass
;
4710 case ETHTOOL_XDP_DROP
:
4711 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_drop
;
4713 case ETHTOOL_XDP_TX
:
4714 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_tx
;
4716 case ETHTOOL_XDP_TX_ERR
:
4717 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_tx_err
;
4719 case ETHTOOL_XDP_XMIT
:
4720 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_xmit
;
4722 case ETHTOOL_XDP_XMIT_ERR
:
4723 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_xmit_err
;
4731 static void mvneta_ethtool_get_stats(struct net_device
*dev
,
4732 struct ethtool_stats
*stats
, u64
*data
)
4734 struct mvneta_port
*pp
= netdev_priv(dev
);
4737 mvneta_ethtool_update_stats(pp
);
4739 for (i
= 0; i
< ARRAY_SIZE(mvneta_statistics
); i
++)
4740 *data
++ = pp
->ethtool_stats
[i
];
4743 static int mvneta_ethtool_get_sset_count(struct net_device
*dev
, int sset
)
4745 if (sset
== ETH_SS_STATS
)
4746 return ARRAY_SIZE(mvneta_statistics
);
4750 static u32
mvneta_ethtool_get_rxfh_indir_size(struct net_device
*dev
)
4752 return MVNETA_RSS_LU_TABLE_SIZE
;
4755 static int mvneta_ethtool_get_rxnfc(struct net_device
*dev
,
4756 struct ethtool_rxnfc
*info
,
4757 u32
*rules __always_unused
)
4759 switch (info
->cmd
) {
4760 case ETHTOOL_GRXRINGS
:
4761 info
->data
= rxq_number
;
4770 static int mvneta_config_rss(struct mvneta_port
*pp
)
4775 netif_tx_stop_all_queues(pp
->dev
);
4777 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
4779 if (!pp
->neta_armada3700
) {
4780 /* We have to synchronise on the napi of each CPU */
4781 for_each_online_cpu(cpu
) {
4782 struct mvneta_pcpu_port
*pcpu_port
=
4783 per_cpu_ptr(pp
->ports
, cpu
);
4785 napi_synchronize(&pcpu_port
->napi
);
4786 napi_disable(&pcpu_port
->napi
);
4789 napi_synchronize(&pp
->napi
);
4790 napi_disable(&pp
->napi
);
4793 pp
->rxq_def
= pp
->indir
[0];
4795 /* Update unicast mapping */
4796 mvneta_set_rx_mode(pp
->dev
);
4798 /* Update val of portCfg register accordingly with all RxQueue types */
4799 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(pp
->rxq_def
);
4800 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
4802 /* Update the elected CPU matching the new rxq_def */
4803 spin_lock(&pp
->lock
);
4804 mvneta_percpu_elect(pp
);
4805 spin_unlock(&pp
->lock
);
4807 if (!pp
->neta_armada3700
) {
4808 /* We have to synchronise on the napi of each CPU */
4809 for_each_online_cpu(cpu
) {
4810 struct mvneta_pcpu_port
*pcpu_port
=
4811 per_cpu_ptr(pp
->ports
, cpu
);
4813 napi_enable(&pcpu_port
->napi
);
4816 napi_enable(&pp
->napi
);
4819 netif_tx_start_all_queues(pp
->dev
);
4824 static int mvneta_ethtool_set_rxfh(struct net_device
*dev
, const u32
*indir
,
4825 const u8
*key
, const u8 hfunc
)
4827 struct mvneta_port
*pp
= netdev_priv(dev
);
4829 /* Current code for Armada 3700 doesn't support RSS features yet */
4830 if (pp
->neta_armada3700
)
4833 /* We require at least one supported parameter to be changed
4834 * and no change in any of the unsupported parameters
4837 (hfunc
!= ETH_RSS_HASH_NO_CHANGE
&& hfunc
!= ETH_RSS_HASH_TOP
))
4843 memcpy(pp
->indir
, indir
, MVNETA_RSS_LU_TABLE_SIZE
);
4845 return mvneta_config_rss(pp
);
4848 static int mvneta_ethtool_get_rxfh(struct net_device
*dev
, u32
*indir
, u8
*key
,
4851 struct mvneta_port
*pp
= netdev_priv(dev
);
4853 /* Current code for Armada 3700 doesn't support RSS features yet */
4854 if (pp
->neta_armada3700
)
4858 *hfunc
= ETH_RSS_HASH_TOP
;
4863 memcpy(indir
, pp
->indir
, MVNETA_RSS_LU_TABLE_SIZE
);
4868 static void mvneta_ethtool_get_wol(struct net_device
*dev
,
4869 struct ethtool_wolinfo
*wol
)
4871 struct mvneta_port
*pp
= netdev_priv(dev
);
4873 phylink_ethtool_get_wol(pp
->phylink
, wol
);
4876 static int mvneta_ethtool_set_wol(struct net_device
*dev
,
4877 struct ethtool_wolinfo
*wol
)
4879 struct mvneta_port
*pp
= netdev_priv(dev
);
4882 ret
= phylink_ethtool_set_wol(pp
->phylink
, wol
);
4884 device_set_wakeup_enable(&dev
->dev
, !!wol
->wolopts
);
4889 static int mvneta_ethtool_get_eee(struct net_device
*dev
,
4890 struct ethtool_eee
*eee
)
4892 struct mvneta_port
*pp
= netdev_priv(dev
);
4895 lpi_ctl0
= mvreg_read(pp
, MVNETA_LPI_CTRL_0
);
4897 eee
->eee_enabled
= pp
->eee_enabled
;
4898 eee
->eee_active
= pp
->eee_active
;
4899 eee
->tx_lpi_enabled
= pp
->tx_lpi_enabled
;
4900 eee
->tx_lpi_timer
= (lpi_ctl0
) >> 8; // * scale;
4902 return phylink_ethtool_get_eee(pp
->phylink
, eee
);
4905 static int mvneta_ethtool_set_eee(struct net_device
*dev
,
4906 struct ethtool_eee
*eee
)
4908 struct mvneta_port
*pp
= netdev_priv(dev
);
4911 /* The Armada 37x documents do not give limits for this other than
4912 * it being an 8-bit register. */
4913 if (eee
->tx_lpi_enabled
&& eee
->tx_lpi_timer
> 255)
4916 lpi_ctl0
= mvreg_read(pp
, MVNETA_LPI_CTRL_0
);
4917 lpi_ctl0
&= ~(0xff << 8);
4918 lpi_ctl0
|= eee
->tx_lpi_timer
<< 8;
4919 mvreg_write(pp
, MVNETA_LPI_CTRL_0
, lpi_ctl0
);
4921 pp
->eee_enabled
= eee
->eee_enabled
;
4922 pp
->tx_lpi_enabled
= eee
->tx_lpi_enabled
;
4924 mvneta_set_eee(pp
, eee
->tx_lpi_enabled
&& eee
->eee_enabled
);
4926 return phylink_ethtool_set_eee(pp
->phylink
, eee
);
4929 static const struct net_device_ops mvneta_netdev_ops
= {
4930 .ndo_open
= mvneta_open
,
4931 .ndo_stop
= mvneta_stop
,
4932 .ndo_start_xmit
= mvneta_tx
,
4933 .ndo_set_rx_mode
= mvneta_set_rx_mode
,
4934 .ndo_set_mac_address
= mvneta_set_mac_addr
,
4935 .ndo_change_mtu
= mvneta_change_mtu
,
4936 .ndo_fix_features
= mvneta_fix_features
,
4937 .ndo_get_stats64
= mvneta_get_stats64
,
4938 .ndo_do_ioctl
= mvneta_ioctl
,
4939 .ndo_bpf
= mvneta_xdp
,
4940 .ndo_xdp_xmit
= mvneta_xdp_xmit
,
4943 static const struct ethtool_ops mvneta_eth_tool_ops
= {
4944 .supported_coalesce_params
= ETHTOOL_COALESCE_RX_USECS
|
4945 ETHTOOL_COALESCE_MAX_FRAMES
,
4946 .nway_reset
= mvneta_ethtool_nway_reset
,
4947 .get_link
= ethtool_op_get_link
,
4948 .set_coalesce
= mvneta_ethtool_set_coalesce
,
4949 .get_coalesce
= mvneta_ethtool_get_coalesce
,
4950 .get_drvinfo
= mvneta_ethtool_get_drvinfo
,
4951 .get_ringparam
= mvneta_ethtool_get_ringparam
,
4952 .set_ringparam
= mvneta_ethtool_set_ringparam
,
4953 .get_pauseparam
= mvneta_ethtool_get_pauseparam
,
4954 .set_pauseparam
= mvneta_ethtool_set_pauseparam
,
4955 .get_strings
= mvneta_ethtool_get_strings
,
4956 .get_ethtool_stats
= mvneta_ethtool_get_stats
,
4957 .get_sset_count
= mvneta_ethtool_get_sset_count
,
4958 .get_rxfh_indir_size
= mvneta_ethtool_get_rxfh_indir_size
,
4959 .get_rxnfc
= mvneta_ethtool_get_rxnfc
,
4960 .get_rxfh
= mvneta_ethtool_get_rxfh
,
4961 .set_rxfh
= mvneta_ethtool_set_rxfh
,
4962 .get_link_ksettings
= mvneta_ethtool_get_link_ksettings
,
4963 .set_link_ksettings
= mvneta_ethtool_set_link_ksettings
,
4964 .get_wol
= mvneta_ethtool_get_wol
,
4965 .set_wol
= mvneta_ethtool_set_wol
,
4966 .get_eee
= mvneta_ethtool_get_eee
,
4967 .set_eee
= mvneta_ethtool_set_eee
,
4971 static int mvneta_init(struct device
*dev
, struct mvneta_port
*pp
)
4976 mvneta_port_disable(pp
);
4978 /* Set port default values */
4979 mvneta_defaults_set(pp
);
4981 pp
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(*pp
->txqs
), GFP_KERNEL
);
4985 /* Initialize TX descriptor rings */
4986 for (queue
= 0; queue
< txq_number
; queue
++) {
4987 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
4989 txq
->size
= pp
->tx_ring_size
;
4990 txq
->done_pkts_coal
= MVNETA_TXDONE_COAL_PKTS
;
4993 pp
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(*pp
->rxqs
), GFP_KERNEL
);
4997 /* Create Rx descriptor rings */
4998 for (queue
= 0; queue
< rxq_number
; queue
++) {
4999 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
5001 rxq
->size
= pp
->rx_ring_size
;
5002 rxq
->pkts_coal
= MVNETA_RX_COAL_PKTS
;
5003 rxq
->time_coal
= MVNETA_RX_COAL_USEC
;
5005 = devm_kmalloc_array(pp
->dev
->dev
.parent
,
5007 sizeof(*rxq
->buf_virt_addr
),
5009 if (!rxq
->buf_virt_addr
)
5016 /* platform glue : initialize decoding windows */
5017 static void mvneta_conf_mbus_windows(struct mvneta_port
*pp
,
5018 const struct mbus_dram_target_info
*dram
)
5024 for (i
= 0; i
< 6; i
++) {
5025 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
5026 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
5029 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
5036 for (i
= 0; i
< dram
->num_cs
; i
++) {
5037 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
5039 mvreg_write(pp
, MVNETA_WIN_BASE(i
),
5040 (cs
->base
& 0xffff0000) |
5041 (cs
->mbus_attr
<< 8) |
5042 dram
->mbus_dram_target_id
);
5044 mvreg_write(pp
, MVNETA_WIN_SIZE(i
),
5045 (cs
->size
- 1) & 0xffff0000);
5047 win_enable
&= ~(1 << i
);
5048 win_protect
|= 3 << (2 * i
);
5051 /* For Armada3700 open default 4GB Mbus window, leaving
5052 * arbitration of target/attribute to a different layer
5055 mvreg_write(pp
, MVNETA_WIN_SIZE(0), 0xffff0000);
5056 win_enable
&= ~BIT(0);
5060 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
5061 mvreg_write(pp
, MVNETA_ACCESS_PROTECT_ENABLE
, win_protect
);
5064 /* Power up the port */
5065 static int mvneta_port_power_up(struct mvneta_port
*pp
, int phy_mode
)
5067 /* MAC Cause register should be cleared */
5068 mvreg_write(pp
, MVNETA_UNIT_INTR_CAUSE
, 0);
5070 if (phy_mode
!= PHY_INTERFACE_MODE_QSGMII
&&
5071 phy_mode
!= PHY_INTERFACE_MODE_SGMII
&&
5072 !phy_interface_mode_is_8023z(phy_mode
) &&
5073 !phy_interface_mode_is_rgmii(phy_mode
))
5079 /* Device initialization routine */
5080 static int mvneta_probe(struct platform_device
*pdev
)
5082 struct device_node
*dn
= pdev
->dev
.of_node
;
5083 struct device_node
*bm_node
;
5084 struct mvneta_port
*pp
;
5085 struct net_device
*dev
;
5086 struct phylink
*phylink
;
5088 const char *dt_mac_addr
;
5089 char hw_mac_addr
[ETH_ALEN
];
5090 phy_interface_t phy_mode
;
5091 const char *mac_from
;
5096 dev
= devm_alloc_etherdev_mqs(&pdev
->dev
, sizeof(struct mvneta_port
),
5097 txq_number
, rxq_number
);
5101 dev
->irq
= irq_of_parse_and_map(dn
, 0);
5105 err
= of_get_phy_mode(dn
, &phy_mode
);
5107 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
5111 comphy
= devm_of_phy_get(&pdev
->dev
, dn
, NULL
);
5112 if (comphy
== ERR_PTR(-EPROBE_DEFER
)) {
5113 err
= -EPROBE_DEFER
;
5115 } else if (IS_ERR(comphy
)) {
5119 pp
= netdev_priv(dev
);
5120 spin_lock_init(&pp
->lock
);
5122 pp
->phylink_config
.dev
= &dev
->dev
;
5123 pp
->phylink_config
.type
= PHYLINK_NETDEV
;
5125 phylink
= phylink_create(&pp
->phylink_config
, pdev
->dev
.fwnode
,
5126 phy_mode
, &mvneta_phylink_ops
);
5127 if (IS_ERR(phylink
)) {
5128 err
= PTR_ERR(phylink
);
5132 dev
->tx_queue_len
= MVNETA_MAX_TXD
;
5133 dev
->watchdog_timeo
= 5 * HZ
;
5134 dev
->netdev_ops
= &mvneta_netdev_ops
;
5136 dev
->ethtool_ops
= &mvneta_eth_tool_ops
;
5138 pp
->phylink
= phylink
;
5139 pp
->comphy
= comphy
;
5140 pp
->phy_interface
= phy_mode
;
5143 pp
->rxq_def
= rxq_def
;
5144 pp
->indir
[0] = rxq_def
;
5146 /* Get special SoC configurations */
5147 if (of_device_is_compatible(dn
, "marvell,armada-3700-neta"))
5148 pp
->neta_armada3700
= true;
5150 pp
->clk
= devm_clk_get(&pdev
->dev
, "core");
5151 if (IS_ERR(pp
->clk
))
5152 pp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
5153 if (IS_ERR(pp
->clk
)) {
5154 err
= PTR_ERR(pp
->clk
);
5155 goto err_free_phylink
;
5158 clk_prepare_enable(pp
->clk
);
5160 pp
->clk_bus
= devm_clk_get(&pdev
->dev
, "bus");
5161 if (!IS_ERR(pp
->clk_bus
))
5162 clk_prepare_enable(pp
->clk_bus
);
5164 pp
->base
= devm_platform_ioremap_resource(pdev
, 0);
5165 if (IS_ERR(pp
->base
)) {
5166 err
= PTR_ERR(pp
->base
);
5170 /* Alloc per-cpu port structure */
5171 pp
->ports
= alloc_percpu(struct mvneta_pcpu_port
);
5177 /* Alloc per-cpu stats */
5178 pp
->stats
= netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats
);
5181 goto err_free_ports
;
5184 dt_mac_addr
= of_get_mac_address(dn
);
5185 if (!IS_ERR(dt_mac_addr
)) {
5186 mac_from
= "device tree";
5187 ether_addr_copy(dev
->dev_addr
, dt_mac_addr
);
5189 mvneta_get_mac_addr(pp
, hw_mac_addr
);
5190 if (is_valid_ether_addr(hw_mac_addr
)) {
5191 mac_from
= "hardware";
5192 memcpy(dev
->dev_addr
, hw_mac_addr
, ETH_ALEN
);
5194 mac_from
= "random";
5195 eth_hw_addr_random(dev
);
5199 if (!of_property_read_u32(dn
, "tx-csum-limit", &tx_csum_limit
)) {
5200 if (tx_csum_limit
< 0 ||
5201 tx_csum_limit
> MVNETA_TX_CSUM_MAX_SIZE
) {
5202 tx_csum_limit
= MVNETA_TX_CSUM_DEF_SIZE
;
5203 dev_info(&pdev
->dev
,
5204 "Wrong TX csum limit in DT, set to %dB\n",
5205 MVNETA_TX_CSUM_DEF_SIZE
);
5207 } else if (of_device_is_compatible(dn
, "marvell,armada-370-neta")) {
5208 tx_csum_limit
= MVNETA_TX_CSUM_DEF_SIZE
;
5210 tx_csum_limit
= MVNETA_TX_CSUM_MAX_SIZE
;
5213 pp
->tx_csum_limit
= tx_csum_limit
;
5215 pp
->dram_target_info
= mv_mbus_dram_info();
5216 /* Armada3700 requires setting default configuration of Mbus
5217 * windows, however without using filled mbus_dram_target_info
5220 if (pp
->dram_target_info
|| pp
->neta_armada3700
)
5221 mvneta_conf_mbus_windows(pp
, pp
->dram_target_info
);
5223 pp
->tx_ring_size
= MVNETA_MAX_TXD
;
5224 pp
->rx_ring_size
= MVNETA_MAX_RXD
;
5227 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5229 pp
->id
= global_port_id
++;
5231 /* Obtain access to BM resources if enabled and already initialized */
5232 bm_node
= of_parse_phandle(dn
, "buffer-manager", 0);
5234 pp
->bm_priv
= mvneta_bm_get(bm_node
);
5236 err
= mvneta_bm_port_init(pdev
, pp
);
5238 dev_info(&pdev
->dev
,
5239 "use SW buffer management\n");
5240 mvneta_bm_put(pp
->bm_priv
);
5244 /* Set RX packet offset correction for platforms, whose
5245 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
5246 * platforms and 0B for 32-bit ones.
5248 pp
->rx_offset_correction
= max(0,
5250 MVNETA_RX_PKT_OFFSET_CORRECTION
);
5252 of_node_put(bm_node
);
5254 /* sw buffer management */
5256 pp
->rx_offset_correction
= MVNETA_SKB_HEADROOM
;
5258 err
= mvneta_init(&pdev
->dev
, pp
);
5262 err
= mvneta_port_power_up(pp
, pp
->phy_interface
);
5264 dev_err(&pdev
->dev
, "can't power up port\n");
5268 /* Armada3700 network controller does not support per-cpu
5269 * operation, so only single NAPI should be initialized.
5271 if (pp
->neta_armada3700
) {
5272 netif_napi_add(dev
, &pp
->napi
, mvneta_poll
, NAPI_POLL_WEIGHT
);
5274 for_each_present_cpu(cpu
) {
5275 struct mvneta_pcpu_port
*port
=
5276 per_cpu_ptr(pp
->ports
, cpu
);
5278 netif_napi_add(dev
, &port
->napi
, mvneta_poll
,
5284 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
5285 NETIF_F_TSO
| NETIF_F_RXCSUM
;
5286 dev
->hw_features
|= dev
->features
;
5287 dev
->vlan_features
|= dev
->features
;
5288 dev
->priv_flags
|= IFF_LIVE_ADDR_CHANGE
;
5289 dev
->gso_max_segs
= MVNETA_MAX_TSO_SEGS
;
5291 /* MTU range: 68 - 9676 */
5292 dev
->min_mtu
= ETH_MIN_MTU
;
5293 /* 9676 == 9700 - 20 and rounding to 8 */
5294 dev
->max_mtu
= 9676;
5296 err
= register_netdev(dev
);
5298 dev_err(&pdev
->dev
, "failed to register\n");
5302 netdev_info(dev
, "Using %s mac address %pM\n", mac_from
,
5305 platform_set_drvdata(pdev
, pp
->dev
);
5311 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
5312 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
,
5314 mvneta_bm_put(pp
->bm_priv
);
5316 free_percpu(pp
->stats
);
5318 free_percpu(pp
->ports
);
5320 clk_disable_unprepare(pp
->clk_bus
);
5321 clk_disable_unprepare(pp
->clk
);
5324 phylink_destroy(pp
->phylink
);
5326 irq_dispose_mapping(dev
->irq
);
5330 /* Device removal routine */
5331 static int mvneta_remove(struct platform_device
*pdev
)
5333 struct net_device
*dev
= platform_get_drvdata(pdev
);
5334 struct mvneta_port
*pp
= netdev_priv(dev
);
5336 unregister_netdev(dev
);
5337 clk_disable_unprepare(pp
->clk_bus
);
5338 clk_disable_unprepare(pp
->clk
);
5339 free_percpu(pp
->ports
);
5340 free_percpu(pp
->stats
);
5341 irq_dispose_mapping(dev
->irq
);
5342 phylink_destroy(pp
->phylink
);
5345 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
5346 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
,
5348 mvneta_bm_put(pp
->bm_priv
);
5354 #ifdef CONFIG_PM_SLEEP
5355 static int mvneta_suspend(struct device
*device
)
5358 struct net_device
*dev
= dev_get_drvdata(device
);
5359 struct mvneta_port
*pp
= netdev_priv(dev
);
5361 if (!netif_running(dev
))
5364 if (!pp
->neta_armada3700
) {
5365 spin_lock(&pp
->lock
);
5366 pp
->is_stopped
= true;
5367 spin_unlock(&pp
->lock
);
5369 cpuhp_state_remove_instance_nocalls(online_hpstate
,
5371 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
5376 mvneta_stop_dev(pp
);
5379 for (queue
= 0; queue
< rxq_number
; queue
++) {
5380 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
5382 mvneta_rxq_drop_pkts(pp
, rxq
);
5385 for (queue
= 0; queue
< txq_number
; queue
++) {
5386 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
5388 mvneta_txq_hw_deinit(pp
, txq
);
5392 netif_device_detach(dev
);
5393 clk_disable_unprepare(pp
->clk_bus
);
5394 clk_disable_unprepare(pp
->clk
);
5399 static int mvneta_resume(struct device
*device
)
5401 struct platform_device
*pdev
= to_platform_device(device
);
5402 struct net_device
*dev
= dev_get_drvdata(device
);
5403 struct mvneta_port
*pp
= netdev_priv(dev
);
5406 clk_prepare_enable(pp
->clk
);
5407 if (!IS_ERR(pp
->clk_bus
))
5408 clk_prepare_enable(pp
->clk_bus
);
5409 if (pp
->dram_target_info
|| pp
->neta_armada3700
)
5410 mvneta_conf_mbus_windows(pp
, pp
->dram_target_info
);
5412 err
= mvneta_bm_port_init(pdev
, pp
);
5414 dev_info(&pdev
->dev
, "use SW buffer management\n");
5415 pp
->rx_offset_correction
= MVNETA_SKB_HEADROOM
;
5419 mvneta_defaults_set(pp
);
5420 err
= mvneta_port_power_up(pp
, pp
->phy_interface
);
5422 dev_err(device
, "can't power up port\n");
5426 netif_device_attach(dev
);
5428 if (!netif_running(dev
))
5431 for (queue
= 0; queue
< rxq_number
; queue
++) {
5432 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
5434 rxq
->next_desc_to_proc
= 0;
5435 mvneta_rxq_hw_init(pp
, rxq
);
5438 for (queue
= 0; queue
< txq_number
; queue
++) {
5439 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
5441 txq
->next_desc_to_proc
= 0;
5442 mvneta_txq_hw_init(pp
, txq
);
5445 if (!pp
->neta_armada3700
) {
5446 spin_lock(&pp
->lock
);
5447 pp
->is_stopped
= false;
5448 spin_unlock(&pp
->lock
);
5449 cpuhp_state_add_instance_nocalls(online_hpstate
,
5451 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
5456 mvneta_start_dev(pp
);
5458 mvneta_set_rx_mode(dev
);
5464 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops
, mvneta_suspend
, mvneta_resume
);
5466 static const struct of_device_id mvneta_match
[] = {
5467 { .compatible
= "marvell,armada-370-neta" },
5468 { .compatible
= "marvell,armada-xp-neta" },
5469 { .compatible
= "marvell,armada-3700-neta" },
5472 MODULE_DEVICE_TABLE(of
, mvneta_match
);
5474 static struct platform_driver mvneta_driver
= {
5475 .probe
= mvneta_probe
,
5476 .remove
= mvneta_remove
,
5478 .name
= MVNETA_DRIVER_NAME
,
5479 .of_match_table
= mvneta_match
,
5480 .pm
= &mvneta_pm_ops
,
5484 static int __init
mvneta_driver_init(void)
5488 ret
= cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN
, "net/mvneta:online",
5490 mvneta_cpu_down_prepare
);
5493 online_hpstate
= ret
;
5494 ret
= cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD
, "net/mvneta:dead",
5495 NULL
, mvneta_cpu_dead
);
5499 ret
= platform_driver_register(&mvneta_driver
);
5505 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD
);
5507 cpuhp_remove_multi_state(online_hpstate
);
5511 module_init(mvneta_driver_init
);
5513 static void __exit
mvneta_driver_exit(void)
5515 platform_driver_unregister(&mvneta_driver
);
5516 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD
);
5517 cpuhp_remove_multi_state(online_hpstate
);
5519 module_exit(mvneta_driver_exit
);
5521 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
5522 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
5523 MODULE_LICENSE("GPL");
5525 module_param(rxq_number
, int, 0444);
5526 module_param(txq_number
, int, 0444);
5528 module_param(rxq_def
, int, 0444);
5529 module_param(rx_copybreak
, int, 0644);