2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/phy_fixed.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
35 #include "mvneta_bm.h"
41 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
42 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
43 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
44 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
45 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
46 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
47 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
48 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
49 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
50 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
51 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
52 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
53 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
54 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
55 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
56 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
57 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
59 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
60 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
61 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
62 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
63 #define MVNETA_PORT_RX_RESET 0x1cc0
64 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
65 #define MVNETA_PHY_ADDR 0x2000
66 #define MVNETA_PHY_ADDR_MASK 0x1f
67 #define MVNETA_MBUS_RETRY 0x2010
68 #define MVNETA_UNIT_INTR_CAUSE 0x2080
69 #define MVNETA_UNIT_CONTROL 0x20B0
70 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
71 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
72 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
73 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
74 #define MVNETA_BASE_ADDR_ENABLE 0x2290
75 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
76 #define MVNETA_PORT_CONFIG 0x2400
77 #define MVNETA_UNI_PROMISC_MODE BIT(0)
78 #define MVNETA_DEF_RXQ(q) ((q) << 1)
79 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
80 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
81 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
82 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
83 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
84 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
85 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
86 MVNETA_DEF_RXQ_ARP(q) | \
87 MVNETA_DEF_RXQ_TCP(q) | \
88 MVNETA_DEF_RXQ_UDP(q) | \
89 MVNETA_DEF_RXQ_BPDU(q) | \
90 MVNETA_TX_UNSET_ERR_SUM | \
91 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
92 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
93 #define MVNETA_MAC_ADDR_LOW 0x2414
94 #define MVNETA_MAC_ADDR_HIGH 0x2418
95 #define MVNETA_SDMA_CONFIG 0x241c
96 #define MVNETA_SDMA_BRST_SIZE_16 4
97 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
98 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
99 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
100 #define MVNETA_DESC_SWAP BIT(6)
101 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
102 #define MVNETA_PORT_STATUS 0x2444
103 #define MVNETA_TX_IN_PRGRS BIT(1)
104 #define MVNETA_TX_FIFO_EMPTY BIT(8)
105 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
106 #define MVNETA_SERDES_CFG 0x24A0
107 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
108 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
109 #define MVNETA_TYPE_PRIO 0x24bc
110 #define MVNETA_FORCE_UNI BIT(21)
111 #define MVNETA_TXQ_CMD_1 0x24e4
112 #define MVNETA_TXQ_CMD 0x2448
113 #define MVNETA_TXQ_DISABLE_SHIFT 8
114 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
115 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
116 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
117 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
118 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
119 #define MVNETA_ACC_MODE 0x2500
120 #define MVNETA_BM_ADDRESS 0x2504
121 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
122 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
123 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
124 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
125 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
126 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
128 /* Exception Interrupt Port/Queue Cause register
130 * Their behavior depend of the mapping done using the PCPX2Q
131 * registers. For a given CPU if the bit associated to a queue is not
132 * set, then for the register a read from this CPU will always return
133 * 0 and a write won't do anything
136 #define MVNETA_INTR_NEW_CAUSE 0x25a0
137 #define MVNETA_INTR_NEW_MASK 0x25a4
139 /* bits 0..7 = TXQ SENT, one bit per queue.
140 * bits 8..15 = RXQ OCCUP, one bit per queue.
141 * bits 16..23 = RXQ FREE, one bit per queue.
142 * bit 29 = OLD_REG_SUM, see old reg ?
143 * bit 30 = TX_ERR_SUM, one bit for 4 ports
144 * bit 31 = MISC_SUM, one bit for 4 ports
146 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
147 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
148 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
149 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
150 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
152 #define MVNETA_INTR_OLD_CAUSE 0x25a8
153 #define MVNETA_INTR_OLD_MASK 0x25ac
155 /* Data Path Port/Queue Cause Register */
156 #define MVNETA_INTR_MISC_CAUSE 0x25b0
157 #define MVNETA_INTR_MISC_MASK 0x25b4
159 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
160 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
161 #define MVNETA_CAUSE_PTP BIT(4)
163 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
164 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
165 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
166 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
167 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
168 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
169 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
170 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
174 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
176 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
177 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
178 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
180 #define MVNETA_INTR_ENABLE 0x25b8
181 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
182 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
184 #define MVNETA_RXQ_CMD 0x2680
185 #define MVNETA_RXQ_DISABLE_SHIFT 8
186 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
187 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
188 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
189 #define MVNETA_GMAC_CTRL_0 0x2c00
190 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
191 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
192 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
193 #define MVNETA_GMAC_CTRL_2 0x2c08
194 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
195 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
196 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
197 #define MVNETA_GMAC2_PORT_RESET BIT(6)
198 #define MVNETA_GMAC_STATUS 0x2c10
199 #define MVNETA_GMAC_LINK_UP BIT(0)
200 #define MVNETA_GMAC_SPEED_1000 BIT(1)
201 #define MVNETA_GMAC_SPEED_100 BIT(2)
202 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
203 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
204 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
205 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
206 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
207 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
208 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
209 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
210 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
211 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
212 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
213 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
214 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
215 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
216 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
217 #define MVNETA_MIB_COUNTERS_BASE 0x3000
218 #define MVNETA_MIB_LATE_COLLISION 0x7c
219 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
220 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
221 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
222 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
223 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
224 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
225 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
226 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
227 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
228 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
229 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
230 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
231 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
232 #define MVNETA_PORT_TX_RESET 0x3cf0
233 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
234 #define MVNETA_TX_MTU 0x3e0c
235 #define MVNETA_TX_TOKEN_SIZE 0x3e14
236 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
237 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
238 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
240 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
242 /* Descriptor ring Macros */
243 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
244 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
246 /* Various constants */
249 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
250 #define MVNETA_RX_COAL_PKTS 32
251 #define MVNETA_RX_COAL_USEC 100
253 /* The two bytes Marvell header. Either contains a special value used
254 * by Marvell switches when a specific hardware mode is enabled (not
255 * supported by this driver) or is filled automatically by zeroes on
256 * the RX side. Those two bytes being at the front of the Ethernet
257 * header, they allow to have the IP header aligned on a 4 bytes
258 * boundary automatically: the hardware skips those two bytes on its
261 #define MVNETA_MH_SIZE 2
263 #define MVNETA_VLAN_TAG_LEN 4
265 #define MVNETA_TX_CSUM_DEF_SIZE 1600
266 #define MVNETA_TX_CSUM_MAX_SIZE 9800
267 #define MVNETA_ACC_MODE_EXT1 1
268 #define MVNETA_ACC_MODE_EXT2 2
270 #define MVNETA_MAX_DECODE_WIN 6
272 /* Timeout constants */
273 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
274 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
275 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
277 #define MVNETA_TX_MTU_MAX 0x3ffff
279 /* The RSS lookup table actually has 256 entries but we do not use
282 #define MVNETA_RSS_LU_TABLE_SIZE 1
284 /* Max number of Rx descriptors */
285 #define MVNETA_MAX_RXD 128
287 /* Max number of Tx descriptors */
288 #define MVNETA_MAX_TXD 532
290 /* Max number of allowed TCP segments for software TSO */
291 #define MVNETA_MAX_TSO_SEGS 100
293 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
295 /* descriptor aligned size */
296 #define MVNETA_DESC_ALIGNED_SIZE 32
298 /* Number of bytes to be taken into account by HW when putting incoming data
299 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
300 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
302 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
304 #define MVNETA_RX_PKT_SIZE(mtu) \
305 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
306 ETH_HLEN + ETH_FCS_LEN, \
309 #define IS_TSO_HEADER(txq, addr) \
310 ((addr >= txq->tso_hdrs_phys) && \
311 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
313 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
314 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
316 struct mvneta_statistic
{
317 unsigned short offset
;
319 const char name
[ETH_GSTRING_LEN
];
325 static const struct mvneta_statistic mvneta_statistics
[] = {
326 { 0x3000, T_REG_64
, "good_octets_received", },
327 { 0x3010, T_REG_32
, "good_frames_received", },
328 { 0x3008, T_REG_32
, "bad_octets_received", },
329 { 0x3014, T_REG_32
, "bad_frames_received", },
330 { 0x3018, T_REG_32
, "broadcast_frames_received", },
331 { 0x301c, T_REG_32
, "multicast_frames_received", },
332 { 0x3050, T_REG_32
, "unrec_mac_control_received", },
333 { 0x3058, T_REG_32
, "good_fc_received", },
334 { 0x305c, T_REG_32
, "bad_fc_received", },
335 { 0x3060, T_REG_32
, "undersize_received", },
336 { 0x3064, T_REG_32
, "fragments_received", },
337 { 0x3068, T_REG_32
, "oversize_received", },
338 { 0x306c, T_REG_32
, "jabber_received", },
339 { 0x3070, T_REG_32
, "mac_receive_error", },
340 { 0x3074, T_REG_32
, "bad_crc_event", },
341 { 0x3078, T_REG_32
, "collision", },
342 { 0x307c, T_REG_32
, "late_collision", },
343 { 0x2484, T_REG_32
, "rx_discard", },
344 { 0x2488, T_REG_32
, "rx_overrun", },
345 { 0x3020, T_REG_32
, "frames_64_octets", },
346 { 0x3024, T_REG_32
, "frames_65_to_127_octets", },
347 { 0x3028, T_REG_32
, "frames_128_to_255_octets", },
348 { 0x302c, T_REG_32
, "frames_256_to_511_octets", },
349 { 0x3030, T_REG_32
, "frames_512_to_1023_octets", },
350 { 0x3034, T_REG_32
, "frames_1024_to_max_octets", },
351 { 0x3038, T_REG_64
, "good_octets_sent", },
352 { 0x3040, T_REG_32
, "good_frames_sent", },
353 { 0x3044, T_REG_32
, "excessive_collision", },
354 { 0x3048, T_REG_32
, "multicast_frames_sent", },
355 { 0x304c, T_REG_32
, "broadcast_frames_sent", },
356 { 0x3054, T_REG_32
, "fc_sent", },
357 { 0x300c, T_REG_32
, "internal_mac_transmit_err", },
360 struct mvneta_pcpu_stats
{
361 struct u64_stats_sync syncp
;
368 struct mvneta_pcpu_port
{
369 /* Pointer to the shared port */
370 struct mvneta_port
*pp
;
372 /* Pointer to the CPU-local NAPI struct */
373 struct napi_struct napi
;
375 /* Cause of the previous interrupt */
381 struct mvneta_pcpu_port __percpu
*ports
;
382 struct mvneta_pcpu_stats __percpu
*stats
;
385 unsigned int frag_size
;
387 struct mvneta_rx_queue
*rxqs
;
388 struct mvneta_tx_queue
*txqs
;
389 struct net_device
*dev
;
390 struct hlist_node node_online
;
391 struct hlist_node node_dead
;
393 /* Protect the access to the percpu interrupt registers,
394 * ensuring that the configuration remains coherent.
400 struct napi_struct napi
;
410 struct mii_bus
*mii_bus
;
411 phy_interface_t phy_interface
;
412 struct device_node
*phy_node
;
416 unsigned int tx_csum_limit
;
417 unsigned int use_inband_status
:1;
419 struct mvneta_bm
*bm_priv
;
420 struct mvneta_bm_pool
*pool_long
;
421 struct mvneta_bm_pool
*pool_short
;
424 u64 ethtool_stats
[ARRAY_SIZE(mvneta_statistics
)];
426 u32 indir
[MVNETA_RSS_LU_TABLE_SIZE
];
428 /* Flags for special SoC configurations */
429 bool neta_armada3700
;
430 u16 rx_offset_correction
;
431 const struct mbus_dram_target_info
*dram_target_info
;
434 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
435 * layout of the transmit and reception DMA descriptors, and their
436 * layout is therefore defined by the hardware design
439 #define MVNETA_TX_L3_OFF_SHIFT 0
440 #define MVNETA_TX_IP_HLEN_SHIFT 8
441 #define MVNETA_TX_L4_UDP BIT(16)
442 #define MVNETA_TX_L3_IP6 BIT(17)
443 #define MVNETA_TXD_IP_CSUM BIT(18)
444 #define MVNETA_TXD_Z_PAD BIT(19)
445 #define MVNETA_TXD_L_DESC BIT(20)
446 #define MVNETA_TXD_F_DESC BIT(21)
447 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
448 MVNETA_TXD_L_DESC | \
450 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
451 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
453 #define MVNETA_RXD_ERR_CRC 0x0
454 #define MVNETA_RXD_BM_POOL_SHIFT 13
455 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
456 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
457 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
458 #define MVNETA_RXD_ERR_LEN BIT(18)
459 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
460 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
461 #define MVNETA_RXD_L3_IP4 BIT(25)
462 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
463 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
465 #if defined(__LITTLE_ENDIAN)
466 struct mvneta_tx_desc
{
467 u32 command
; /* Options used by HW for packet transmitting.*/
468 u16 reserverd1
; /* csum_l4 (for future use) */
469 u16 data_size
; /* Data size of transmitted packet in bytes */
470 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
471 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
472 u32 reserved3
[4]; /* Reserved - (for future use) */
475 struct mvneta_rx_desc
{
476 u32 status
; /* Info about received packet */
477 u16 reserved1
; /* pnc_info - (for future use, PnC) */
478 u16 data_size
; /* Size of received packet in bytes */
480 u32 buf_phys_addr
; /* Physical address of the buffer */
481 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
483 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
484 u16 reserved3
; /* prefetch_cmd, for future use */
485 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
487 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
488 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
491 struct mvneta_tx_desc
{
492 u16 data_size
; /* Data size of transmitted packet in bytes */
493 u16 reserverd1
; /* csum_l4 (for future use) */
494 u32 command
; /* Options used by HW for packet transmitting.*/
495 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
496 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
497 u32 reserved3
[4]; /* Reserved - (for future use) */
500 struct mvneta_rx_desc
{
501 u16 data_size
; /* Size of received packet in bytes */
502 u16 reserved1
; /* pnc_info - (for future use, PnC) */
503 u32 status
; /* Info about received packet */
505 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
506 u32 buf_phys_addr
; /* Physical address of the buffer */
508 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
509 u16 reserved3
; /* prefetch_cmd, for future use */
510 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
512 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
513 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
517 struct mvneta_tx_queue
{
518 /* Number of this TX queue, in the range 0-7 */
521 /* Number of TX DMA descriptors in the descriptor ring */
524 /* Number of currently used TX DMA descriptor in the
529 int tx_stop_threshold
;
530 int tx_wake_threshold
;
532 /* Array of transmitted skb */
533 struct sk_buff
**tx_skb
;
535 /* Index of last TX DMA descriptor that was inserted */
538 /* Index of the TX DMA descriptor to be cleaned up */
543 /* Virtual address of the TX DMA descriptors array */
544 struct mvneta_tx_desc
*descs
;
546 /* DMA address of the TX DMA descriptors array */
547 dma_addr_t descs_phys
;
549 /* Index of the last TX DMA descriptor */
552 /* Index of the next TX DMA descriptor to process */
553 int next_desc_to_proc
;
555 /* DMA buffers for TSO headers */
558 /* DMA address of TSO headers */
559 dma_addr_t tso_hdrs_phys
;
561 /* Affinity mask for CPUs*/
562 cpumask_t affinity_mask
;
565 struct mvneta_rx_queue
{
566 /* rx queue number, in the range 0-7 */
569 /* num of rx descriptors in the rx descriptor ring */
572 /* counter of times when mvneta_refill() failed */
578 /* Virtual address of the RX buffer */
579 void **buf_virt_addr
;
581 /* Virtual address of the RX DMA descriptors array */
582 struct mvneta_rx_desc
*descs
;
584 /* DMA address of the RX DMA descriptors array */
585 dma_addr_t descs_phys
;
587 /* Index of the last RX DMA descriptor */
590 /* Index of the next RX DMA descriptor to process */
591 int next_desc_to_proc
;
594 static enum cpuhp_state online_hpstate
;
595 /* The hardware supports eight (8) rx queues, but we are only allowing
596 * the first one to be used. Therefore, let's just allocate one queue.
598 static int rxq_number
= 8;
599 static int txq_number
= 8;
603 static int rx_copybreak __read_mostly
= 256;
605 /* HW BM need that each port be identify by a unique ID */
606 static int global_port_id
;
608 #define MVNETA_DRIVER_NAME "mvneta"
609 #define MVNETA_DRIVER_VERSION "1.0"
611 /* Utility/helper methods */
613 /* Write helper method */
614 static void mvreg_write(struct mvneta_port
*pp
, u32 offset
, u32 data
)
616 writel(data
, pp
->base
+ offset
);
619 /* Read helper method */
620 static u32
mvreg_read(struct mvneta_port
*pp
, u32 offset
)
622 return readl(pp
->base
+ offset
);
625 /* Increment txq get counter */
626 static void mvneta_txq_inc_get(struct mvneta_tx_queue
*txq
)
628 txq
->txq_get_index
++;
629 if (txq
->txq_get_index
== txq
->size
)
630 txq
->txq_get_index
= 0;
633 /* Increment txq put counter */
634 static void mvneta_txq_inc_put(struct mvneta_tx_queue
*txq
)
636 txq
->txq_put_index
++;
637 if (txq
->txq_put_index
== txq
->size
)
638 txq
->txq_put_index
= 0;
642 /* Clear all MIB counters */
643 static void mvneta_mib_counters_clear(struct mvneta_port
*pp
)
648 /* Perform dummy reads from MIB counters */
649 for (i
= 0; i
< MVNETA_MIB_LATE_COLLISION
; i
+= 4)
650 dummy
= mvreg_read(pp
, (MVNETA_MIB_COUNTERS_BASE
+ i
));
651 dummy
= mvreg_read(pp
, MVNETA_RX_DISCARD_FRAME_COUNT
);
652 dummy
= mvreg_read(pp
, MVNETA_OVERRUN_FRAME_COUNT
);
655 /* Get System Network Statistics */
657 mvneta_get_stats64(struct net_device
*dev
,
658 struct rtnl_link_stats64
*stats
)
660 struct mvneta_port
*pp
= netdev_priv(dev
);
664 for_each_possible_cpu(cpu
) {
665 struct mvneta_pcpu_stats
*cpu_stats
;
671 cpu_stats
= per_cpu_ptr(pp
->stats
, cpu
);
673 start
= u64_stats_fetch_begin_irq(&cpu_stats
->syncp
);
674 rx_packets
= cpu_stats
->rx_packets
;
675 rx_bytes
= cpu_stats
->rx_bytes
;
676 tx_packets
= cpu_stats
->tx_packets
;
677 tx_bytes
= cpu_stats
->tx_bytes
;
678 } while (u64_stats_fetch_retry_irq(&cpu_stats
->syncp
, start
));
680 stats
->rx_packets
+= rx_packets
;
681 stats
->rx_bytes
+= rx_bytes
;
682 stats
->tx_packets
+= tx_packets
;
683 stats
->tx_bytes
+= tx_bytes
;
686 stats
->rx_errors
= dev
->stats
.rx_errors
;
687 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
689 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
692 /* Rx descriptors helper methods */
694 /* Checks whether the RX descriptor having this status is both the first
695 * and the last descriptor for the RX packet. Each RX packet is currently
696 * received through a single RX descriptor, so not having each RX
697 * descriptor with its first and last bits set is an error
699 static int mvneta_rxq_desc_is_first_last(u32 status
)
701 return (status
& MVNETA_RXD_FIRST_LAST_DESC
) ==
702 MVNETA_RXD_FIRST_LAST_DESC
;
705 /* Add number of descriptors ready to receive new packets */
706 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port
*pp
,
707 struct mvneta_rx_queue
*rxq
,
710 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
713 while (ndescs
> MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
) {
714 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
715 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
<<
716 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
717 ndescs
-= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
;
720 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
721 (ndescs
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
724 /* Get number of RX descriptors occupied by received packets */
725 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port
*pp
,
726 struct mvneta_rx_queue
*rxq
)
730 val
= mvreg_read(pp
, MVNETA_RXQ_STATUS_REG(rxq
->id
));
731 return val
& MVNETA_RXQ_OCCUPIED_ALL_MASK
;
734 /* Update num of rx desc called upon return from rx path or
735 * from mvneta_rxq_drop_pkts().
737 static void mvneta_rxq_desc_num_update(struct mvneta_port
*pp
,
738 struct mvneta_rx_queue
*rxq
,
739 int rx_done
, int rx_filled
)
743 if ((rx_done
<= 0xff) && (rx_filled
<= 0xff)) {
745 (rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
);
746 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
750 /* Only 255 descriptors can be added at once */
751 while ((rx_done
> 0) || (rx_filled
> 0)) {
752 if (rx_done
<= 0xff) {
759 if (rx_filled
<= 0xff) {
760 val
|= rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
763 val
|= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
766 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
770 /* Get pointer to next RX descriptor to be processed by SW */
771 static struct mvneta_rx_desc
*
772 mvneta_rxq_next_desc_get(struct mvneta_rx_queue
*rxq
)
774 int rx_desc
= rxq
->next_desc_to_proc
;
776 rxq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(rxq
, rx_desc
);
777 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
778 return rxq
->descs
+ rx_desc
;
781 /* Change maximum receive size of the port. */
782 static void mvneta_max_rx_size_set(struct mvneta_port
*pp
, int max_rx_size
)
786 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
787 val
&= ~MVNETA_GMAC_MAX_RX_SIZE_MASK
;
788 val
|= ((max_rx_size
- MVNETA_MH_SIZE
) / 2) <<
789 MVNETA_GMAC_MAX_RX_SIZE_SHIFT
;
790 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
794 /* Set rx queue offset */
795 static void mvneta_rxq_offset_set(struct mvneta_port
*pp
,
796 struct mvneta_rx_queue
*rxq
,
801 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
802 val
&= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK
;
805 val
|= MVNETA_RXQ_PKT_OFFSET_MASK(offset
>> 3);
806 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
810 /* Tx descriptors helper methods */
812 /* Update HW with number of TX descriptors to be sent */
813 static void mvneta_txq_pend_desc_add(struct mvneta_port
*pp
,
814 struct mvneta_tx_queue
*txq
,
819 pend_desc
+= txq
->pending
;
821 /* Only 255 Tx descriptors can be added at once */
823 val
= min(pend_desc
, 255);
824 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
826 } while (pend_desc
> 0);
830 /* Get pointer to next TX descriptor to be processed (send) by HW */
831 static struct mvneta_tx_desc
*
832 mvneta_txq_next_desc_get(struct mvneta_tx_queue
*txq
)
834 int tx_desc
= txq
->next_desc_to_proc
;
836 txq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(txq
, tx_desc
);
837 return txq
->descs
+ tx_desc
;
840 /* Release the last allocated TX descriptor. Useful to handle DMA
841 * mapping failures in the TX path.
843 static void mvneta_txq_desc_put(struct mvneta_tx_queue
*txq
)
845 if (txq
->next_desc_to_proc
== 0)
846 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
848 txq
->next_desc_to_proc
--;
851 /* Set rxq buf size */
852 static void mvneta_rxq_buf_size_set(struct mvneta_port
*pp
,
853 struct mvneta_rx_queue
*rxq
,
858 val
= mvreg_read(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
));
860 val
&= ~MVNETA_RXQ_BUF_SIZE_MASK
;
861 val
|= ((buf_size
>> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT
);
863 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), val
);
866 /* Disable buffer management (BM) */
867 static void mvneta_rxq_bm_disable(struct mvneta_port
*pp
,
868 struct mvneta_rx_queue
*rxq
)
872 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
873 val
&= ~MVNETA_RXQ_HW_BUF_ALLOC
;
874 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
877 /* Enable buffer management (BM) */
878 static void mvneta_rxq_bm_enable(struct mvneta_port
*pp
,
879 struct mvneta_rx_queue
*rxq
)
883 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
884 val
|= MVNETA_RXQ_HW_BUF_ALLOC
;
885 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
888 /* Notify HW about port's assignment of pool for bigger packets */
889 static void mvneta_rxq_long_pool_set(struct mvneta_port
*pp
,
890 struct mvneta_rx_queue
*rxq
)
894 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
895 val
&= ~MVNETA_RXQ_LONG_POOL_ID_MASK
;
896 val
|= (pp
->pool_long
->id
<< MVNETA_RXQ_LONG_POOL_ID_SHIFT
);
898 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
901 /* Notify HW about port's assignment of pool for smaller packets */
902 static void mvneta_rxq_short_pool_set(struct mvneta_port
*pp
,
903 struct mvneta_rx_queue
*rxq
)
907 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
908 val
&= ~MVNETA_RXQ_SHORT_POOL_ID_MASK
;
909 val
|= (pp
->pool_short
->id
<< MVNETA_RXQ_SHORT_POOL_ID_SHIFT
);
911 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
914 /* Set port's receive buffer size for assigned BM pool */
915 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port
*pp
,
921 if (!IS_ALIGNED(buf_size
, 8)) {
922 dev_warn(pp
->dev
->dev
.parent
,
923 "illegal buf_size value %d, round to %d\n",
924 buf_size
, ALIGN(buf_size
, 8));
925 buf_size
= ALIGN(buf_size
, 8);
928 val
= mvreg_read(pp
, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id
));
929 val
|= buf_size
& MVNETA_PORT_POOL_BUFFER_SZ_MASK
;
930 mvreg_write(pp
, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id
), val
);
933 /* Configure MBUS window in order to enable access BM internal SRAM */
934 static int mvneta_mbus_io_win_set(struct mvneta_port
*pp
, u32 base
, u32 wsize
,
937 u32 win_enable
, win_protect
;
940 win_enable
= mvreg_read(pp
, MVNETA_BASE_ADDR_ENABLE
);
942 if (pp
->bm_win_id
< 0) {
943 /* Find first not occupied window */
944 for (i
= 0; i
< MVNETA_MAX_DECODE_WIN
; i
++) {
945 if (win_enable
& (1 << i
)) {
950 if (i
== MVNETA_MAX_DECODE_WIN
)
956 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
957 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
960 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
962 mvreg_write(pp
, MVNETA_WIN_BASE(i
), (base
& 0xffff0000) |
963 (attr
<< 8) | target
);
965 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), (wsize
- 1) & 0xffff0000);
967 win_protect
= mvreg_read(pp
, MVNETA_ACCESS_PROTECT_ENABLE
);
968 win_protect
|= 3 << (2 * i
);
969 mvreg_write(pp
, MVNETA_ACCESS_PROTECT_ENABLE
, win_protect
);
971 win_enable
&= ~(1 << i
);
972 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
977 static int mvneta_bm_port_mbus_init(struct mvneta_port
*pp
)
983 /* Get BM window information */
984 err
= mvebu_mbus_get_io_win_info(pp
->bm_priv
->bppi_phys_addr
, &wsize
,
991 /* Open NETA -> BM window */
992 err
= mvneta_mbus_io_win_set(pp
, pp
->bm_priv
->bppi_phys_addr
, wsize
,
995 netdev_info(pp
->dev
, "fail to configure mbus window to BM\n");
1001 /* Assign and initialize pools for port. In case of fail
1002 * buffer manager will remain disabled for current port.
1004 static int mvneta_bm_port_init(struct platform_device
*pdev
,
1005 struct mvneta_port
*pp
)
1007 struct device_node
*dn
= pdev
->dev
.of_node
;
1008 u32 long_pool_id
, short_pool_id
;
1010 if (!pp
->neta_armada3700
) {
1013 ret
= mvneta_bm_port_mbus_init(pp
);
1018 if (of_property_read_u32(dn
, "bm,pool-long", &long_pool_id
)) {
1019 netdev_info(pp
->dev
, "missing long pool id\n");
1023 /* Create port's long pool depending on mtu */
1024 pp
->pool_long
= mvneta_bm_pool_use(pp
->bm_priv
, long_pool_id
,
1025 MVNETA_BM_LONG
, pp
->id
,
1026 MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
));
1027 if (!pp
->pool_long
) {
1028 netdev_info(pp
->dev
, "fail to obtain long pool for port\n");
1032 pp
->pool_long
->port_map
|= 1 << pp
->id
;
1034 mvneta_bm_pool_bufsize_set(pp
, pp
->pool_long
->buf_size
,
1037 /* If short pool id is not defined, assume using single pool */
1038 if (of_property_read_u32(dn
, "bm,pool-short", &short_pool_id
))
1039 short_pool_id
= long_pool_id
;
1041 /* Create port's short pool */
1042 pp
->pool_short
= mvneta_bm_pool_use(pp
->bm_priv
, short_pool_id
,
1043 MVNETA_BM_SHORT
, pp
->id
,
1044 MVNETA_BM_SHORT_PKT_SIZE
);
1045 if (!pp
->pool_short
) {
1046 netdev_info(pp
->dev
, "fail to obtain short pool for port\n");
1047 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
1051 if (short_pool_id
!= long_pool_id
) {
1052 pp
->pool_short
->port_map
|= 1 << pp
->id
;
1053 mvneta_bm_pool_bufsize_set(pp
, pp
->pool_short
->buf_size
,
1054 pp
->pool_short
->id
);
1060 /* Update settings of a pool for bigger packets */
1061 static void mvneta_bm_update_mtu(struct mvneta_port
*pp
, int mtu
)
1063 struct mvneta_bm_pool
*bm_pool
= pp
->pool_long
;
1064 struct hwbm_pool
*hwbm_pool
= &bm_pool
->hwbm_pool
;
1067 /* Release all buffers from long pool */
1068 mvneta_bm_bufs_free(pp
->bm_priv
, bm_pool
, 1 << pp
->id
);
1069 if (hwbm_pool
->buf_num
) {
1070 WARN(1, "cannot free all buffers in pool %d\n",
1075 bm_pool
->pkt_size
= MVNETA_RX_PKT_SIZE(mtu
);
1076 bm_pool
->buf_size
= MVNETA_RX_BUF_SIZE(bm_pool
->pkt_size
);
1077 hwbm_pool
->frag_size
= SKB_DATA_ALIGN(sizeof(struct skb_shared_info
)) +
1078 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool
->pkt_size
));
1080 /* Fill entire long pool */
1081 num
= hwbm_pool_add(hwbm_pool
, hwbm_pool
->size
, GFP_ATOMIC
);
1082 if (num
!= hwbm_pool
->size
) {
1083 WARN(1, "pool %d: %d of %d allocated\n",
1084 bm_pool
->id
, num
, hwbm_pool
->size
);
1087 mvneta_bm_pool_bufsize_set(pp
, bm_pool
->buf_size
, bm_pool
->id
);
1092 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
1093 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
, 1 << pp
->id
);
1096 mvreg_write(pp
, MVNETA_ACC_MODE
, MVNETA_ACC_MODE_EXT1
);
1097 netdev_info(pp
->dev
, "fail to update MTU, fall back to software BM\n");
1100 /* Start the Ethernet port RX and TX activity */
1101 static void mvneta_port_up(struct mvneta_port
*pp
)
1106 /* Enable all initialized TXs. */
1108 for (queue
= 0; queue
< txq_number
; queue
++) {
1109 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
1111 q_map
|= (1 << queue
);
1113 mvreg_write(pp
, MVNETA_TXQ_CMD
, q_map
);
1115 /* Enable all initialized RXQs. */
1116 for (queue
= 0; queue
< rxq_number
; queue
++) {
1117 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
1120 q_map
|= (1 << queue
);
1122 mvreg_write(pp
, MVNETA_RXQ_CMD
, q_map
);
1125 /* Stop the Ethernet port activity */
1126 static void mvneta_port_down(struct mvneta_port
*pp
)
1131 /* Stop Rx port activity. Check port Rx activity. */
1132 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
) & MVNETA_RXQ_ENABLE_MASK
;
1134 /* Issue stop command for active channels only */
1136 mvreg_write(pp
, MVNETA_RXQ_CMD
,
1137 val
<< MVNETA_RXQ_DISABLE_SHIFT
);
1139 /* Wait for all Rx activity to terminate. */
1142 if (count
++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC
) {
1143 netdev_warn(pp
->dev
,
1144 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1150 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
);
1151 } while (val
& MVNETA_RXQ_ENABLE_MASK
);
1153 /* Stop Tx port activity. Check port Tx activity. Issue stop
1154 * command for active channels only
1156 val
= (mvreg_read(pp
, MVNETA_TXQ_CMD
)) & MVNETA_TXQ_ENABLE_MASK
;
1159 mvreg_write(pp
, MVNETA_TXQ_CMD
,
1160 (val
<< MVNETA_TXQ_DISABLE_SHIFT
));
1162 /* Wait for all Tx activity to terminate. */
1165 if (count
++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC
) {
1166 netdev_warn(pp
->dev
,
1167 "TIMEOUT for TX stopped status=0x%08x\n",
1173 /* Check TX Command reg that all Txqs are stopped */
1174 val
= mvreg_read(pp
, MVNETA_TXQ_CMD
);
1176 } while (val
& MVNETA_TXQ_ENABLE_MASK
);
1178 /* Double check to verify that TX FIFO is empty */
1181 if (count
++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT
) {
1182 netdev_warn(pp
->dev
,
1183 "TX FIFO empty timeout status=0x%08x\n",
1189 val
= mvreg_read(pp
, MVNETA_PORT_STATUS
);
1190 } while (!(val
& MVNETA_TX_FIFO_EMPTY
) &&
1191 (val
& MVNETA_TX_IN_PRGRS
));
1196 /* Enable the port by setting the port enable bit of the MAC control register */
1197 static void mvneta_port_enable(struct mvneta_port
*pp
)
1202 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
1203 val
|= MVNETA_GMAC0_PORT_ENABLE
;
1204 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
1207 /* Disable the port and wait for about 200 usec before retuning */
1208 static void mvneta_port_disable(struct mvneta_port
*pp
)
1212 /* Reset the Enable bit in the Serial Control Register */
1213 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
1214 val
&= ~MVNETA_GMAC0_PORT_ENABLE
;
1215 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
1220 /* Multicast tables methods */
1222 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1223 static void mvneta_set_ucast_table(struct mvneta_port
*pp
, int queue
)
1231 val
= 0x1 | (queue
<< 1);
1232 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1235 for (offset
= 0; offset
<= 0xc; offset
+= 4)
1236 mvreg_write(pp
, MVNETA_DA_FILT_UCAST_BASE
+ offset
, val
);
1239 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1240 static void mvneta_set_special_mcast_table(struct mvneta_port
*pp
, int queue
)
1248 val
= 0x1 | (queue
<< 1);
1249 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1252 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
1253 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ offset
, val
);
1257 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1258 static void mvneta_set_other_mcast_table(struct mvneta_port
*pp
, int queue
)
1264 memset(pp
->mcast_count
, 0, sizeof(pp
->mcast_count
));
1267 memset(pp
->mcast_count
, 1, sizeof(pp
->mcast_count
));
1268 val
= 0x1 | (queue
<< 1);
1269 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1272 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
1273 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ offset
, val
);
1276 static void mvneta_set_autoneg(struct mvneta_port
*pp
, int enable
)
1281 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
1282 val
&= ~(MVNETA_GMAC_FORCE_LINK_PASS
|
1283 MVNETA_GMAC_FORCE_LINK_DOWN
|
1284 MVNETA_GMAC_AN_FLOW_CTRL_EN
);
1285 val
|= MVNETA_GMAC_INBAND_AN_ENABLE
|
1286 MVNETA_GMAC_AN_SPEED_EN
|
1287 MVNETA_GMAC_AN_DUPLEX_EN
;
1288 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1290 val
= mvreg_read(pp
, MVNETA_GMAC_CLOCK_DIVIDER
);
1291 val
|= MVNETA_GMAC_1MS_CLOCK_ENABLE
;
1292 mvreg_write(pp
, MVNETA_GMAC_CLOCK_DIVIDER
, val
);
1294 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
1295 val
|= MVNETA_GMAC2_INBAND_AN_ENABLE
;
1296 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, val
);
1298 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
1299 val
&= ~(MVNETA_GMAC_INBAND_AN_ENABLE
|
1300 MVNETA_GMAC_AN_SPEED_EN
|
1301 MVNETA_GMAC_AN_DUPLEX_EN
);
1302 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1304 val
= mvreg_read(pp
, MVNETA_GMAC_CLOCK_DIVIDER
);
1305 val
&= ~MVNETA_GMAC_1MS_CLOCK_ENABLE
;
1306 mvreg_write(pp
, MVNETA_GMAC_CLOCK_DIVIDER
, val
);
1308 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
1309 val
&= ~MVNETA_GMAC2_INBAND_AN_ENABLE
;
1310 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, val
);
1314 static void mvneta_percpu_unmask_interrupt(void *arg
)
1316 struct mvneta_port
*pp
= arg
;
1318 /* All the queue are unmasked, but actually only the ones
1319 * mapped to this CPU will be unmasked
1321 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
1322 MVNETA_RX_INTR_MASK_ALL
|
1323 MVNETA_TX_INTR_MASK_ALL
|
1324 MVNETA_MISCINTR_INTR_MASK
);
1327 static void mvneta_percpu_mask_interrupt(void *arg
)
1329 struct mvneta_port
*pp
= arg
;
1331 /* All the queue are masked, but actually only the ones
1332 * mapped to this CPU will be masked
1334 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
1335 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
1336 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
1339 static void mvneta_percpu_clear_intr_cause(void *arg
)
1341 struct mvneta_port
*pp
= arg
;
1343 /* All the queue are cleared, but actually only the ones
1344 * mapped to this CPU will be cleared
1346 mvreg_write(pp
, MVNETA_INTR_NEW_CAUSE
, 0);
1347 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
1348 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
1351 /* This method sets defaults to the NETA port:
1352 * Clears interrupt Cause and Mask registers.
1353 * Clears all MAC tables.
1354 * Sets defaults to all registers.
1355 * Resets RX and TX descriptor rings.
1357 * This method can be called after mvneta_port_down() to return the port
1358 * settings to defaults.
1360 static void mvneta_defaults_set(struct mvneta_port
*pp
)
1365 int max_cpu
= num_present_cpus();
1367 /* Clear all Cause registers */
1368 on_each_cpu(mvneta_percpu_clear_intr_cause
, pp
, true);
1370 /* Mask all interrupts */
1371 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
1372 mvreg_write(pp
, MVNETA_INTR_ENABLE
, 0);
1374 /* Enable MBUS Retry bit16 */
1375 mvreg_write(pp
, MVNETA_MBUS_RETRY
, 0x20);
1377 /* Set CPU queue access map. CPUs are assigned to the RX and
1378 * TX queues modulo their number. If there is only one TX
1379 * queue then it is assigned to the CPU associated to the
1382 for_each_present_cpu(cpu
) {
1383 int rxq_map
= 0, txq_map
= 0;
1385 if (!pp
->neta_armada3700
) {
1386 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
1387 if ((rxq
% max_cpu
) == cpu
)
1388 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(rxq
);
1390 for (txq
= 0; txq
< txq_number
; txq
++)
1391 if ((txq
% max_cpu
) == cpu
)
1392 txq_map
|= MVNETA_CPU_TXQ_ACCESS(txq
);
1394 /* With only one TX queue we configure a special case
1395 * which will allow to get all the irq on a single
1398 if (txq_number
== 1)
1399 txq_map
= (cpu
== pp
->rxq_def
) ?
1400 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1403 txq_map
= MVNETA_CPU_TXQ_ACCESS_ALL_MASK
;
1404 rxq_map
= MVNETA_CPU_RXQ_ACCESS_ALL_MASK
;
1407 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
), rxq_map
| txq_map
);
1410 /* Reset RX and TX DMAs */
1411 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
1412 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
1414 /* Disable Legacy WRR, Disable EJP, Release from reset */
1415 mvreg_write(pp
, MVNETA_TXQ_CMD_1
, 0);
1416 for (queue
= 0; queue
< txq_number
; queue
++) {
1417 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(queue
), 0);
1418 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(queue
), 0);
1421 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
1422 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
1424 /* Set Port Acceleration Mode */
1426 /* HW buffer management + legacy parser */
1427 val
= MVNETA_ACC_MODE_EXT2
;
1429 /* SW buffer management + legacy parser */
1430 val
= MVNETA_ACC_MODE_EXT1
;
1431 mvreg_write(pp
, MVNETA_ACC_MODE
, val
);
1434 mvreg_write(pp
, MVNETA_BM_ADDRESS
, pp
->bm_priv
->bppi_phys_addr
);
1436 /* Update val of portCfg register accordingly with all RxQueue types */
1437 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(pp
->rxq_def
);
1438 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
1441 mvreg_write(pp
, MVNETA_PORT_CONFIG_EXTEND
, val
);
1442 mvreg_write(pp
, MVNETA_RX_MIN_FRAME_SIZE
, 64);
1444 /* Build PORT_SDMA_CONFIG_REG */
1447 /* Default burst size */
1448 val
|= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
1449 val
|= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
1450 val
|= MVNETA_RX_NO_DATA_SWAP
| MVNETA_TX_NO_DATA_SWAP
;
1452 #if defined(__BIG_ENDIAN)
1453 val
|= MVNETA_DESC_SWAP
;
1456 /* Assign port SDMA configuration */
1457 mvreg_write(pp
, MVNETA_SDMA_CONFIG
, val
);
1459 /* Disable PHY polling in hardware, since we're using the
1460 * kernel phylib to do this.
1462 val
= mvreg_read(pp
, MVNETA_UNIT_CONTROL
);
1463 val
&= ~MVNETA_PHY_POLLING_ENABLE
;
1464 mvreg_write(pp
, MVNETA_UNIT_CONTROL
, val
);
1466 mvneta_set_autoneg(pp
, pp
->use_inband_status
);
1467 mvneta_set_ucast_table(pp
, -1);
1468 mvneta_set_special_mcast_table(pp
, -1);
1469 mvneta_set_other_mcast_table(pp
, -1);
1471 /* Set port interrupt enable register - default enable all */
1472 mvreg_write(pp
, MVNETA_INTR_ENABLE
,
1473 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1474 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK
));
1476 mvneta_mib_counters_clear(pp
);
1479 /* Set max sizes for tx queues */
1480 static void mvneta_txq_max_tx_size_set(struct mvneta_port
*pp
, int max_tx_size
)
1486 mtu
= max_tx_size
* 8;
1487 if (mtu
> MVNETA_TX_MTU_MAX
)
1488 mtu
= MVNETA_TX_MTU_MAX
;
1491 val
= mvreg_read(pp
, MVNETA_TX_MTU
);
1492 val
&= ~MVNETA_TX_MTU_MAX
;
1494 mvreg_write(pp
, MVNETA_TX_MTU
, val
);
1496 /* TX token size and all TXQs token size must be larger that MTU */
1497 val
= mvreg_read(pp
, MVNETA_TX_TOKEN_SIZE
);
1499 size
= val
& MVNETA_TX_TOKEN_SIZE_MAX
;
1502 val
&= ~MVNETA_TX_TOKEN_SIZE_MAX
;
1504 mvreg_write(pp
, MVNETA_TX_TOKEN_SIZE
, val
);
1506 for (queue
= 0; queue
< txq_number
; queue
++) {
1507 val
= mvreg_read(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
));
1509 size
= val
& MVNETA_TXQ_TOKEN_SIZE_MAX
;
1512 val
&= ~MVNETA_TXQ_TOKEN_SIZE_MAX
;
1514 mvreg_write(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
), val
);
1519 /* Set unicast address */
1520 static void mvneta_set_ucast_addr(struct mvneta_port
*pp
, u8 last_nibble
,
1523 unsigned int unicast_reg
;
1524 unsigned int tbl_offset
;
1525 unsigned int reg_offset
;
1527 /* Locate the Unicast table entry */
1528 last_nibble
= (0xf & last_nibble
);
1530 /* offset from unicast tbl base */
1531 tbl_offset
= (last_nibble
/ 4) * 4;
1533 /* offset within the above reg */
1534 reg_offset
= last_nibble
% 4;
1536 unicast_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
));
1539 /* Clear accepts frame bit at specified unicast DA tbl entry */
1540 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1542 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1543 unicast_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1546 mvreg_write(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
), unicast_reg
);
1549 /* Set mac address */
1550 static void mvneta_mac_addr_set(struct mvneta_port
*pp
, unsigned char *addr
,
1557 mac_l
= (addr
[4] << 8) | (addr
[5]);
1558 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) |
1559 (addr
[2] << 8) | (addr
[3] << 0);
1561 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, mac_l
);
1562 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, mac_h
);
1565 /* Accept frames of this address */
1566 mvneta_set_ucast_addr(pp
, addr
[5], queue
);
1569 /* Set the number of packets that will be received before RX interrupt
1570 * will be generated by HW.
1572 static void mvneta_rx_pkts_coal_set(struct mvneta_port
*pp
,
1573 struct mvneta_rx_queue
*rxq
, u32 value
)
1575 mvreg_write(pp
, MVNETA_RXQ_THRESHOLD_REG(rxq
->id
),
1576 value
| MVNETA_RXQ_NON_OCCUPIED(0));
1577 rxq
->pkts_coal
= value
;
1580 /* Set the time delay in usec before RX interrupt will be generated by
1583 static void mvneta_rx_time_coal_set(struct mvneta_port
*pp
,
1584 struct mvneta_rx_queue
*rxq
, u32 value
)
1587 unsigned long clk_rate
;
1589 clk_rate
= clk_get_rate(pp
->clk
);
1590 val
= (clk_rate
/ 1000000) * value
;
1592 mvreg_write(pp
, MVNETA_RXQ_TIME_COAL_REG(rxq
->id
), val
);
1593 rxq
->time_coal
= value
;
1596 /* Set threshold for TX_DONE pkts coalescing */
1597 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port
*pp
,
1598 struct mvneta_tx_queue
*txq
, u32 value
)
1602 val
= mvreg_read(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
));
1604 val
&= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK
;
1605 val
|= MVNETA_TXQ_SENT_THRESH_MASK(value
);
1607 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), val
);
1609 txq
->done_pkts_coal
= value
;
1612 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1613 static void mvneta_rx_desc_fill(struct mvneta_rx_desc
*rx_desc
,
1614 u32 phys_addr
, void *virt_addr
,
1615 struct mvneta_rx_queue
*rxq
)
1619 rx_desc
->buf_phys_addr
= phys_addr
;
1620 i
= rx_desc
- rxq
->descs
;
1621 rxq
->buf_virt_addr
[i
] = virt_addr
;
1624 /* Decrement sent descriptors counter */
1625 static void mvneta_txq_sent_desc_dec(struct mvneta_port
*pp
,
1626 struct mvneta_tx_queue
*txq
,
1631 /* Only 255 TX descriptors can be updated at once */
1632 while (sent_desc
> 0xff) {
1633 val
= 0xff << MVNETA_TXQ_DEC_SENT_SHIFT
;
1634 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1635 sent_desc
= sent_desc
- 0xff;
1638 val
= sent_desc
<< MVNETA_TXQ_DEC_SENT_SHIFT
;
1639 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1642 /* Get number of TX descriptors already sent by HW */
1643 static int mvneta_txq_sent_desc_num_get(struct mvneta_port
*pp
,
1644 struct mvneta_tx_queue
*txq
)
1649 val
= mvreg_read(pp
, MVNETA_TXQ_STATUS_REG(txq
->id
));
1650 sent_desc
= (val
& MVNETA_TXQ_SENT_DESC_MASK
) >>
1651 MVNETA_TXQ_SENT_DESC_SHIFT
;
1656 /* Get number of sent descriptors and decrement counter.
1657 * The number of sent descriptors is returned.
1659 static int mvneta_txq_sent_desc_proc(struct mvneta_port
*pp
,
1660 struct mvneta_tx_queue
*txq
)
1664 /* Get number of sent descriptors */
1665 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1667 /* Decrement sent descriptors counter */
1669 mvneta_txq_sent_desc_dec(pp
, txq
, sent_desc
);
1674 /* Set TXQ descriptors fields relevant for CSUM calculation */
1675 static u32
mvneta_txq_desc_csum(int l3_offs
, int l3_proto
,
1676 int ip_hdr_len
, int l4_proto
)
1680 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1681 * G_L4_chk, L4_type; required only for checksum
1684 command
= l3_offs
<< MVNETA_TX_L3_OFF_SHIFT
;
1685 command
|= ip_hdr_len
<< MVNETA_TX_IP_HLEN_SHIFT
;
1687 if (l3_proto
== htons(ETH_P_IP
))
1688 command
|= MVNETA_TXD_IP_CSUM
;
1690 command
|= MVNETA_TX_L3_IP6
;
1692 if (l4_proto
== IPPROTO_TCP
)
1693 command
|= MVNETA_TX_L4_CSUM_FULL
;
1694 else if (l4_proto
== IPPROTO_UDP
)
1695 command
|= MVNETA_TX_L4_UDP
| MVNETA_TX_L4_CSUM_FULL
;
1697 command
|= MVNETA_TX_L4_CSUM_NOT
;
1703 /* Display more error info */
1704 static void mvneta_rx_error(struct mvneta_port
*pp
,
1705 struct mvneta_rx_desc
*rx_desc
)
1707 u32 status
= rx_desc
->status
;
1709 if (!mvneta_rxq_desc_is_first_last(status
)) {
1711 "bad rx status %08x (buffer oversize), size=%d\n",
1712 status
, rx_desc
->data_size
);
1716 switch (status
& MVNETA_RXD_ERR_CODE_MASK
) {
1717 case MVNETA_RXD_ERR_CRC
:
1718 netdev_err(pp
->dev
, "bad rx status %08x (crc error), size=%d\n",
1719 status
, rx_desc
->data_size
);
1721 case MVNETA_RXD_ERR_OVERRUN
:
1722 netdev_err(pp
->dev
, "bad rx status %08x (overrun error), size=%d\n",
1723 status
, rx_desc
->data_size
);
1725 case MVNETA_RXD_ERR_LEN
:
1726 netdev_err(pp
->dev
, "bad rx status %08x (max frame length error), size=%d\n",
1727 status
, rx_desc
->data_size
);
1729 case MVNETA_RXD_ERR_RESOURCE
:
1730 netdev_err(pp
->dev
, "bad rx status %08x (resource error), size=%d\n",
1731 status
, rx_desc
->data_size
);
1736 /* Handle RX checksum offload based on the descriptor's status */
1737 static void mvneta_rx_csum(struct mvneta_port
*pp
, u32 status
,
1738 struct sk_buff
*skb
)
1740 if ((status
& MVNETA_RXD_L3_IP4
) &&
1741 (status
& MVNETA_RXD_L4_CSUM_OK
)) {
1743 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1747 skb
->ip_summed
= CHECKSUM_NONE
;
1750 /* Return tx queue pointer (find last set bit) according to <cause> returned
1751 * form tx_done reg. <cause> must not be null. The return value is always a
1752 * valid queue for matching the first one found in <cause>.
1754 static struct mvneta_tx_queue
*mvneta_tx_done_policy(struct mvneta_port
*pp
,
1757 int queue
= fls(cause
) - 1;
1759 return &pp
->txqs
[queue
];
1762 /* Free tx queue skbuffs */
1763 static void mvneta_txq_bufs_free(struct mvneta_port
*pp
,
1764 struct mvneta_tx_queue
*txq
, int num
,
1765 struct netdev_queue
*nq
)
1767 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1770 for (i
= 0; i
< num
; i
++) {
1771 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+
1773 struct sk_buff
*skb
= txq
->tx_skb
[txq
->txq_get_index
];
1776 bytes_compl
+= skb
->len
;
1780 mvneta_txq_inc_get(txq
);
1782 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
))
1783 dma_unmap_single(pp
->dev
->dev
.parent
,
1784 tx_desc
->buf_phys_addr
,
1785 tx_desc
->data_size
, DMA_TO_DEVICE
);
1788 dev_kfree_skb_any(skb
);
1791 netdev_tx_completed_queue(nq
, pkts_compl
, bytes_compl
);
1794 /* Handle end of transmission */
1795 static void mvneta_txq_done(struct mvneta_port
*pp
,
1796 struct mvneta_tx_queue
*txq
)
1798 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1801 tx_done
= mvneta_txq_sent_desc_proc(pp
, txq
);
1805 mvneta_txq_bufs_free(pp
, txq
, tx_done
, nq
);
1807 txq
->count
-= tx_done
;
1809 if (netif_tx_queue_stopped(nq
)) {
1810 if (txq
->count
<= txq
->tx_wake_threshold
)
1811 netif_tx_wake_queue(nq
);
1815 void *mvneta_frag_alloc(unsigned int frag_size
)
1817 if (likely(frag_size
<= PAGE_SIZE
))
1818 return netdev_alloc_frag(frag_size
);
1820 return kmalloc(frag_size
, GFP_ATOMIC
);
1822 EXPORT_SYMBOL_GPL(mvneta_frag_alloc
);
1824 void mvneta_frag_free(unsigned int frag_size
, void *data
)
1826 if (likely(frag_size
<= PAGE_SIZE
))
1827 skb_free_frag(data
);
1831 EXPORT_SYMBOL_GPL(mvneta_frag_free
);
1833 /* Refill processing for SW buffer management */
1834 static int mvneta_rx_refill(struct mvneta_port
*pp
,
1835 struct mvneta_rx_desc
*rx_desc
,
1836 struct mvneta_rx_queue
*rxq
)
1839 dma_addr_t phys_addr
;
1842 data
= mvneta_frag_alloc(pp
->frag_size
);
1846 phys_addr
= dma_map_single(pp
->dev
->dev
.parent
, data
,
1847 MVNETA_RX_BUF_SIZE(pp
->pkt_size
),
1849 if (unlikely(dma_mapping_error(pp
->dev
->dev
.parent
, phys_addr
))) {
1850 mvneta_frag_free(pp
->frag_size
, data
);
1854 phys_addr
+= pp
->rx_offset_correction
;
1855 mvneta_rx_desc_fill(rx_desc
, phys_addr
, data
, rxq
);
1859 /* Handle tx checksum */
1860 static u32
mvneta_skb_tx_csum(struct mvneta_port
*pp
, struct sk_buff
*skb
)
1862 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1864 __be16 l3_proto
= vlan_get_protocol(skb
);
1867 if (l3_proto
== htons(ETH_P_IP
)) {
1868 struct iphdr
*ip4h
= ip_hdr(skb
);
1870 /* Calculate IPv4 checksum and L4 checksum */
1871 ip_hdr_len
= ip4h
->ihl
;
1872 l4_proto
= ip4h
->protocol
;
1873 } else if (l3_proto
== htons(ETH_P_IPV6
)) {
1874 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1876 /* Read l4_protocol from one of IPv6 extra headers */
1877 if (skb_network_header_len(skb
) > 0)
1878 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
1879 l4_proto
= ip6h
->nexthdr
;
1881 return MVNETA_TX_L4_CSUM_NOT
;
1883 return mvneta_txq_desc_csum(skb_network_offset(skb
),
1884 l3_proto
, ip_hdr_len
, l4_proto
);
1887 return MVNETA_TX_L4_CSUM_NOT
;
1890 /* Drop packets received by the RXQ and free buffers */
1891 static void mvneta_rxq_drop_pkts(struct mvneta_port
*pp
,
1892 struct mvneta_rx_queue
*rxq
)
1896 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1898 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1901 for (i
= 0; i
< rx_done
; i
++) {
1902 struct mvneta_rx_desc
*rx_desc
=
1903 mvneta_rxq_next_desc_get(rxq
);
1904 u8 pool_id
= MVNETA_RX_GET_BM_POOL_ID(rx_desc
);
1905 struct mvneta_bm_pool
*bm_pool
;
1907 bm_pool
= &pp
->bm_priv
->bm_pools
[pool_id
];
1908 /* Return dropped buffer to the pool */
1909 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
1910 rx_desc
->buf_phys_addr
);
1915 for (i
= 0; i
< rxq
->size
; i
++) {
1916 struct mvneta_rx_desc
*rx_desc
= rxq
->descs
+ i
;
1917 void *data
= rxq
->buf_virt_addr
[i
];
1919 dma_unmap_single(pp
->dev
->dev
.parent
, rx_desc
->buf_phys_addr
,
1920 MVNETA_RX_BUF_SIZE(pp
->pkt_size
), DMA_FROM_DEVICE
);
1921 mvneta_frag_free(pp
->frag_size
, data
);
1925 /* Main rx processing when using software buffer management */
1926 static int mvneta_rx_swbm(struct mvneta_port
*pp
, int rx_todo
,
1927 struct mvneta_rx_queue
*rxq
)
1929 struct mvneta_pcpu_port
*port
= this_cpu_ptr(pp
->ports
);
1930 struct net_device
*dev
= pp
->dev
;
1935 /* Get number of received packets */
1936 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1938 if (rx_todo
> rx_done
)
1943 /* Fairness NAPI loop */
1944 while (rx_done
< rx_todo
) {
1945 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
1946 struct sk_buff
*skb
;
1947 unsigned char *data
;
1948 dma_addr_t phys_addr
;
1949 u32 rx_status
, frag_size
;
1950 int rx_bytes
, err
, index
;
1953 rx_status
= rx_desc
->status
;
1954 rx_bytes
= rx_desc
->data_size
- (ETH_FCS_LEN
+ MVNETA_MH_SIZE
);
1955 index
= rx_desc
- rxq
->descs
;
1956 data
= rxq
->buf_virt_addr
[index
];
1957 phys_addr
= rx_desc
->buf_phys_addr
;
1959 if (!mvneta_rxq_desc_is_first_last(rx_status
) ||
1960 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
1962 dev
->stats
.rx_errors
++;
1963 mvneta_rx_error(pp
, rx_desc
);
1964 /* leave the descriptor untouched */
1968 if (rx_bytes
<= rx_copybreak
) {
1969 /* better copy a small frame and not unmap the DMA region */
1970 skb
= netdev_alloc_skb_ip_align(dev
, rx_bytes
);
1972 goto err_drop_frame
;
1974 dma_sync_single_range_for_cpu(dev
->dev
.parent
,
1976 MVNETA_MH_SIZE
+ NET_SKB_PAD
,
1979 skb_put_data(skb
, data
+ MVNETA_MH_SIZE
+ NET_SKB_PAD
,
1982 skb
->protocol
= eth_type_trans(skb
, dev
);
1983 mvneta_rx_csum(pp
, rx_status
, skb
);
1984 napi_gro_receive(&port
->napi
, skb
);
1987 rcvd_bytes
+= rx_bytes
;
1989 /* leave the descriptor and buffer untouched */
1993 /* Refill processing */
1994 err
= mvneta_rx_refill(pp
, rx_desc
, rxq
);
1996 netdev_err(dev
, "Linux processing - Can't refill\n");
1998 goto err_drop_frame
;
2001 frag_size
= pp
->frag_size
;
2003 skb
= build_skb(data
, frag_size
> PAGE_SIZE
? 0 : frag_size
);
2005 /* After refill old buffer has to be unmapped regardless
2006 * the skb is successfully built or not.
2008 dma_unmap_single(dev
->dev
.parent
, phys_addr
,
2009 MVNETA_RX_BUF_SIZE(pp
->pkt_size
),
2013 goto err_drop_frame
;
2016 rcvd_bytes
+= rx_bytes
;
2018 /* Linux processing */
2019 skb_reserve(skb
, MVNETA_MH_SIZE
+ NET_SKB_PAD
);
2020 skb_put(skb
, rx_bytes
);
2022 skb
->protocol
= eth_type_trans(skb
, dev
);
2024 mvneta_rx_csum(pp
, rx_status
, skb
);
2026 napi_gro_receive(&port
->napi
, skb
);
2030 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2032 u64_stats_update_begin(&stats
->syncp
);
2033 stats
->rx_packets
+= rcvd_pkts
;
2034 stats
->rx_bytes
+= rcvd_bytes
;
2035 u64_stats_update_end(&stats
->syncp
);
2038 /* Update rxq management counters */
2039 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
2044 /* Main rx processing when using hardware buffer management */
2045 static int mvneta_rx_hwbm(struct mvneta_port
*pp
, int rx_todo
,
2046 struct mvneta_rx_queue
*rxq
)
2048 struct mvneta_pcpu_port
*port
= this_cpu_ptr(pp
->ports
);
2049 struct net_device
*dev
= pp
->dev
;
2054 /* Get number of received packets */
2055 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
2057 if (rx_todo
> rx_done
)
2062 /* Fairness NAPI loop */
2063 while (rx_done
< rx_todo
) {
2064 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
2065 struct mvneta_bm_pool
*bm_pool
= NULL
;
2066 struct sk_buff
*skb
;
2067 unsigned char *data
;
2068 dma_addr_t phys_addr
;
2069 u32 rx_status
, frag_size
;
2074 rx_status
= rx_desc
->status
;
2075 rx_bytes
= rx_desc
->data_size
- (ETH_FCS_LEN
+ MVNETA_MH_SIZE
);
2076 data
= (u8
*)(uintptr_t)rx_desc
->buf_cookie
;
2077 phys_addr
= rx_desc
->buf_phys_addr
;
2078 pool_id
= MVNETA_RX_GET_BM_POOL_ID(rx_desc
);
2079 bm_pool
= &pp
->bm_priv
->bm_pools
[pool_id
];
2081 if (!mvneta_rxq_desc_is_first_last(rx_status
) ||
2082 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
2083 err_drop_frame_ret_pool
:
2084 /* Return the buffer to the pool */
2085 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
2086 rx_desc
->buf_phys_addr
);
2088 dev
->stats
.rx_errors
++;
2089 mvneta_rx_error(pp
, rx_desc
);
2090 /* leave the descriptor untouched */
2094 if (rx_bytes
<= rx_copybreak
) {
2095 /* better copy a small frame and not unmap the DMA region */
2096 skb
= netdev_alloc_skb_ip_align(dev
, rx_bytes
);
2098 goto err_drop_frame_ret_pool
;
2100 dma_sync_single_range_for_cpu(dev
->dev
.parent
,
2101 rx_desc
->buf_phys_addr
,
2102 MVNETA_MH_SIZE
+ NET_SKB_PAD
,
2105 skb_put_data(skb
, data
+ MVNETA_MH_SIZE
+ NET_SKB_PAD
,
2108 skb
->protocol
= eth_type_trans(skb
, dev
);
2109 mvneta_rx_csum(pp
, rx_status
, skb
);
2110 napi_gro_receive(&port
->napi
, skb
);
2113 rcvd_bytes
+= rx_bytes
;
2115 /* Return the buffer to the pool */
2116 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
2117 rx_desc
->buf_phys_addr
);
2119 /* leave the descriptor and buffer untouched */
2123 /* Refill processing */
2124 err
= hwbm_pool_refill(&bm_pool
->hwbm_pool
, GFP_ATOMIC
);
2126 netdev_err(dev
, "Linux processing - Can't refill\n");
2128 goto err_drop_frame_ret_pool
;
2131 frag_size
= bm_pool
->hwbm_pool
.frag_size
;
2133 skb
= build_skb(data
, frag_size
> PAGE_SIZE
? 0 : frag_size
);
2135 /* After refill old buffer has to be unmapped regardless
2136 * the skb is successfully built or not.
2138 dma_unmap_single(&pp
->bm_priv
->pdev
->dev
, phys_addr
,
2139 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
2141 goto err_drop_frame
;
2144 rcvd_bytes
+= rx_bytes
;
2146 /* Linux processing */
2147 skb_reserve(skb
, MVNETA_MH_SIZE
+ NET_SKB_PAD
);
2148 skb_put(skb
, rx_bytes
);
2150 skb
->protocol
= eth_type_trans(skb
, dev
);
2152 mvneta_rx_csum(pp
, rx_status
, skb
);
2154 napi_gro_receive(&port
->napi
, skb
);
2158 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2160 u64_stats_update_begin(&stats
->syncp
);
2161 stats
->rx_packets
+= rcvd_pkts
;
2162 stats
->rx_bytes
+= rcvd_bytes
;
2163 u64_stats_update_end(&stats
->syncp
);
2166 /* Update rxq management counters */
2167 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
2173 mvneta_tso_put_hdr(struct sk_buff
*skb
,
2174 struct mvneta_port
*pp
, struct mvneta_tx_queue
*txq
)
2176 struct mvneta_tx_desc
*tx_desc
;
2177 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2179 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
2180 tx_desc
= mvneta_txq_next_desc_get(txq
);
2181 tx_desc
->data_size
= hdr_len
;
2182 tx_desc
->command
= mvneta_skb_tx_csum(pp
, skb
);
2183 tx_desc
->command
|= MVNETA_TXD_F_DESC
;
2184 tx_desc
->buf_phys_addr
= txq
->tso_hdrs_phys
+
2185 txq
->txq_put_index
* TSO_HEADER_SIZE
;
2186 mvneta_txq_inc_put(txq
);
2190 mvneta_tso_put_data(struct net_device
*dev
, struct mvneta_tx_queue
*txq
,
2191 struct sk_buff
*skb
, char *data
, int size
,
2192 bool last_tcp
, bool is_last
)
2194 struct mvneta_tx_desc
*tx_desc
;
2196 tx_desc
= mvneta_txq_next_desc_get(txq
);
2197 tx_desc
->data_size
= size
;
2198 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, data
,
2199 size
, DMA_TO_DEVICE
);
2200 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
2201 tx_desc
->buf_phys_addr
))) {
2202 mvneta_txq_desc_put(txq
);
2206 tx_desc
->command
= 0;
2207 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
2210 /* last descriptor in the TCP packet */
2211 tx_desc
->command
= MVNETA_TXD_L_DESC
;
2213 /* last descriptor in SKB */
2215 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
2217 mvneta_txq_inc_put(txq
);
2221 static int mvneta_tx_tso(struct sk_buff
*skb
, struct net_device
*dev
,
2222 struct mvneta_tx_queue
*txq
)
2224 int total_len
, data_left
;
2226 struct mvneta_port
*pp
= netdev_priv(dev
);
2228 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2231 /* Count needed descriptors */
2232 if ((txq
->count
+ tso_count_descs(skb
)) >= txq
->size
)
2235 if (skb_headlen(skb
) < (skb_transport_offset(skb
) + tcp_hdrlen(skb
))) {
2236 pr_info("*** Is this even possible???!?!?\n");
2240 /* Initialize the TSO handler, and prepare the first payload */
2241 tso_start(skb
, &tso
);
2243 total_len
= skb
->len
- hdr_len
;
2244 while (total_len
> 0) {
2247 data_left
= min_t(int, skb_shinfo(skb
)->gso_size
, total_len
);
2248 total_len
-= data_left
;
2251 /* prepare packet headers: MAC + IP + TCP */
2252 hdr
= txq
->tso_hdrs
+ txq
->txq_put_index
* TSO_HEADER_SIZE
;
2253 tso_build_hdr(skb
, hdr
, &tso
, data_left
, total_len
== 0);
2255 mvneta_tso_put_hdr(skb
, pp
, txq
);
2257 while (data_left
> 0) {
2261 size
= min_t(int, tso
.size
, data_left
);
2263 if (mvneta_tso_put_data(dev
, txq
, skb
,
2270 tso_build_data(skb
, &tso
, size
);
2277 /* Release all used data descriptors; header descriptors must not
2280 for (i
= desc_count
- 1; i
>= 0; i
--) {
2281 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+ i
;
2282 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
))
2283 dma_unmap_single(pp
->dev
->dev
.parent
,
2284 tx_desc
->buf_phys_addr
,
2287 mvneta_txq_desc_put(txq
);
2292 /* Handle tx fragmentation processing */
2293 static int mvneta_tx_frag_process(struct mvneta_port
*pp
, struct sk_buff
*skb
,
2294 struct mvneta_tx_queue
*txq
)
2296 struct mvneta_tx_desc
*tx_desc
;
2297 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
2299 for (i
= 0; i
< nr_frags
; i
++) {
2300 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2301 void *addr
= page_address(frag
->page
.p
) + frag
->page_offset
;
2303 tx_desc
= mvneta_txq_next_desc_get(txq
);
2304 tx_desc
->data_size
= frag
->size
;
2306 tx_desc
->buf_phys_addr
=
2307 dma_map_single(pp
->dev
->dev
.parent
, addr
,
2308 tx_desc
->data_size
, DMA_TO_DEVICE
);
2310 if (dma_mapping_error(pp
->dev
->dev
.parent
,
2311 tx_desc
->buf_phys_addr
)) {
2312 mvneta_txq_desc_put(txq
);
2316 if (i
== nr_frags
- 1) {
2317 /* Last descriptor */
2318 tx_desc
->command
= MVNETA_TXD_L_DESC
| MVNETA_TXD_Z_PAD
;
2319 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
2321 /* Descriptor in the middle: Not First, Not Last */
2322 tx_desc
->command
= 0;
2323 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
2325 mvneta_txq_inc_put(txq
);
2331 /* Release all descriptors that were used to map fragments of
2332 * this packet, as well as the corresponding DMA mappings
2334 for (i
= i
- 1; i
>= 0; i
--) {
2335 tx_desc
= txq
->descs
+ i
;
2336 dma_unmap_single(pp
->dev
->dev
.parent
,
2337 tx_desc
->buf_phys_addr
,
2340 mvneta_txq_desc_put(txq
);
2346 /* Main tx processing */
2347 static int mvneta_tx(struct sk_buff
*skb
, struct net_device
*dev
)
2349 struct mvneta_port
*pp
= netdev_priv(dev
);
2350 u16 txq_id
= skb_get_queue_mapping(skb
);
2351 struct mvneta_tx_queue
*txq
= &pp
->txqs
[txq_id
];
2352 struct mvneta_tx_desc
*tx_desc
;
2357 if (!netif_running(dev
))
2360 if (skb_is_gso(skb
)) {
2361 frags
= mvneta_tx_tso(skb
, dev
, txq
);
2365 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
2367 /* Get a descriptor for the first part of the packet */
2368 tx_desc
= mvneta_txq_next_desc_get(txq
);
2370 tx_cmd
= mvneta_skb_tx_csum(pp
, skb
);
2372 tx_desc
->data_size
= skb_headlen(skb
);
2374 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
2377 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
2378 tx_desc
->buf_phys_addr
))) {
2379 mvneta_txq_desc_put(txq
);
2385 /* First and Last descriptor */
2386 tx_cmd
|= MVNETA_TXD_FLZ_DESC
;
2387 tx_desc
->command
= tx_cmd
;
2388 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
2389 mvneta_txq_inc_put(txq
);
2391 /* First but not Last */
2392 tx_cmd
|= MVNETA_TXD_F_DESC
;
2393 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
2394 mvneta_txq_inc_put(txq
);
2395 tx_desc
->command
= tx_cmd
;
2396 /* Continue with other skb fragments */
2397 if (mvneta_tx_frag_process(pp
, skb
, txq
)) {
2398 dma_unmap_single(dev
->dev
.parent
,
2399 tx_desc
->buf_phys_addr
,
2402 mvneta_txq_desc_put(txq
);
2410 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2411 struct netdev_queue
*nq
= netdev_get_tx_queue(dev
, txq_id
);
2413 netdev_tx_sent_queue(nq
, len
);
2415 txq
->count
+= frags
;
2416 if (txq
->count
>= txq
->tx_stop_threshold
)
2417 netif_tx_stop_queue(nq
);
2419 if (!skb
->xmit_more
|| netif_xmit_stopped(nq
) ||
2420 txq
->pending
+ frags
> MVNETA_TXQ_DEC_SENT_MASK
)
2421 mvneta_txq_pend_desc_add(pp
, txq
, frags
);
2423 txq
->pending
+= frags
;
2425 u64_stats_update_begin(&stats
->syncp
);
2426 stats
->tx_packets
++;
2427 stats
->tx_bytes
+= len
;
2428 u64_stats_update_end(&stats
->syncp
);
2430 dev
->stats
.tx_dropped
++;
2431 dev_kfree_skb_any(skb
);
2434 return NETDEV_TX_OK
;
2438 /* Free tx resources, when resetting a port */
2439 static void mvneta_txq_done_force(struct mvneta_port
*pp
,
2440 struct mvneta_tx_queue
*txq
)
2443 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2444 int tx_done
= txq
->count
;
2446 mvneta_txq_bufs_free(pp
, txq
, tx_done
, nq
);
2450 txq
->txq_put_index
= 0;
2451 txq
->txq_get_index
= 0;
2454 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2455 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2457 static void mvneta_tx_done_gbe(struct mvneta_port
*pp
, u32 cause_tx_done
)
2459 struct mvneta_tx_queue
*txq
;
2460 struct netdev_queue
*nq
;
2462 while (cause_tx_done
) {
2463 txq
= mvneta_tx_done_policy(pp
, cause_tx_done
);
2465 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2466 __netif_tx_lock(nq
, smp_processor_id());
2469 mvneta_txq_done(pp
, txq
);
2471 __netif_tx_unlock(nq
);
2472 cause_tx_done
&= ~((1 << txq
->id
));
2476 /* Compute crc8 of the specified address, using a unique algorithm ,
2477 * according to hw spec, different than generic crc8 algorithm
2479 static int mvneta_addr_crc(unsigned char *addr
)
2484 for (i
= 0; i
< ETH_ALEN
; i
++) {
2487 crc
= (crc
^ addr
[i
]) << 8;
2488 for (j
= 7; j
>= 0; j
--) {
2489 if (crc
& (0x100 << j
))
2497 /* This method controls the net device special MAC multicast support.
2498 * The Special Multicast Table for MAC addresses supports MAC of the form
2499 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2500 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2501 * Table entries in the DA-Filter table. This method set the Special
2502 * Multicast Table appropriate entry.
2504 static void mvneta_set_special_mcast_addr(struct mvneta_port
*pp
,
2505 unsigned char last_byte
,
2508 unsigned int smc_table_reg
;
2509 unsigned int tbl_offset
;
2510 unsigned int reg_offset
;
2512 /* Register offset from SMC table base */
2513 tbl_offset
= (last_byte
/ 4);
2514 /* Entry offset within the above reg */
2515 reg_offset
= last_byte
% 4;
2517 smc_table_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_SPEC_MCAST
2521 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
2523 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
2524 smc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
2527 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ tbl_offset
* 4,
2531 /* This method controls the network device Other MAC multicast support.
2532 * The Other Multicast Table is used for multicast of another type.
2533 * A CRC-8 is used as an index to the Other Multicast Table entries
2534 * in the DA-Filter table.
2535 * The method gets the CRC-8 value from the calling routine and
2536 * sets the Other Multicast Table appropriate entry according to the
2539 static void mvneta_set_other_mcast_addr(struct mvneta_port
*pp
,
2543 unsigned int omc_table_reg
;
2544 unsigned int tbl_offset
;
2545 unsigned int reg_offset
;
2547 tbl_offset
= (crc8
/ 4) * 4; /* Register offset from OMC table base */
2548 reg_offset
= crc8
% 4; /* Entry offset within the above reg */
2550 omc_table_reg
= mvreg_read(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
);
2553 /* Clear accepts frame bit at specified Other DA table entry */
2554 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
2556 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
2557 omc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
2560 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
, omc_table_reg
);
2563 /* The network device supports multicast using two tables:
2564 * 1) Special Multicast Table for MAC addresses of the form
2565 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2566 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2567 * Table entries in the DA-Filter table.
2568 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2569 * is used as an index to the Other Multicast Table entries in the
2572 static int mvneta_mcast_addr_set(struct mvneta_port
*pp
, unsigned char *p_addr
,
2575 unsigned char crc_result
= 0;
2577 if (memcmp(p_addr
, "\x01\x00\x5e\x00\x00", 5) == 0) {
2578 mvneta_set_special_mcast_addr(pp
, p_addr
[5], queue
);
2582 crc_result
= mvneta_addr_crc(p_addr
);
2584 if (pp
->mcast_count
[crc_result
] == 0) {
2585 netdev_info(pp
->dev
, "No valid Mcast for crc8=0x%02x\n",
2590 pp
->mcast_count
[crc_result
]--;
2591 if (pp
->mcast_count
[crc_result
] != 0) {
2592 netdev_info(pp
->dev
,
2593 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2594 pp
->mcast_count
[crc_result
], crc_result
);
2598 pp
->mcast_count
[crc_result
]++;
2600 mvneta_set_other_mcast_addr(pp
, crc_result
, queue
);
2605 /* Configure Fitering mode of Ethernet port */
2606 static void mvneta_rx_unicast_promisc_set(struct mvneta_port
*pp
,
2609 u32 port_cfg_reg
, val
;
2611 port_cfg_reg
= mvreg_read(pp
, MVNETA_PORT_CONFIG
);
2613 val
= mvreg_read(pp
, MVNETA_TYPE_PRIO
);
2615 /* Set / Clear UPM bit in port configuration register */
2617 /* Accept all Unicast addresses */
2618 port_cfg_reg
|= MVNETA_UNI_PROMISC_MODE
;
2619 val
|= MVNETA_FORCE_UNI
;
2620 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, 0xffff);
2621 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, 0xffffffff);
2623 /* Reject all Unicast addresses */
2624 port_cfg_reg
&= ~MVNETA_UNI_PROMISC_MODE
;
2625 val
&= ~MVNETA_FORCE_UNI
;
2628 mvreg_write(pp
, MVNETA_PORT_CONFIG
, port_cfg_reg
);
2629 mvreg_write(pp
, MVNETA_TYPE_PRIO
, val
);
2632 /* register unicast and multicast addresses */
2633 static void mvneta_set_rx_mode(struct net_device
*dev
)
2635 struct mvneta_port
*pp
= netdev_priv(dev
);
2636 struct netdev_hw_addr
*ha
;
2638 if (dev
->flags
& IFF_PROMISC
) {
2639 /* Accept all: Multicast + Unicast */
2640 mvneta_rx_unicast_promisc_set(pp
, 1);
2641 mvneta_set_ucast_table(pp
, pp
->rxq_def
);
2642 mvneta_set_special_mcast_table(pp
, pp
->rxq_def
);
2643 mvneta_set_other_mcast_table(pp
, pp
->rxq_def
);
2645 /* Accept single Unicast */
2646 mvneta_rx_unicast_promisc_set(pp
, 0);
2647 mvneta_set_ucast_table(pp
, -1);
2648 mvneta_mac_addr_set(pp
, dev
->dev_addr
, pp
->rxq_def
);
2650 if (dev
->flags
& IFF_ALLMULTI
) {
2651 /* Accept all multicast */
2652 mvneta_set_special_mcast_table(pp
, pp
->rxq_def
);
2653 mvneta_set_other_mcast_table(pp
, pp
->rxq_def
);
2655 /* Accept only initialized multicast */
2656 mvneta_set_special_mcast_table(pp
, -1);
2657 mvneta_set_other_mcast_table(pp
, -1);
2659 if (!netdev_mc_empty(dev
)) {
2660 netdev_for_each_mc_addr(ha
, dev
) {
2661 mvneta_mcast_addr_set(pp
, ha
->addr
,
2669 /* Interrupt handling - the callback for request_irq() */
2670 static irqreturn_t
mvneta_isr(int irq
, void *dev_id
)
2672 struct mvneta_port
*pp
= (struct mvneta_port
*)dev_id
;
2674 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
2675 napi_schedule(&pp
->napi
);
2680 /* Interrupt handling - the callback for request_percpu_irq() */
2681 static irqreturn_t
mvneta_percpu_isr(int irq
, void *dev_id
)
2683 struct mvneta_pcpu_port
*port
= (struct mvneta_pcpu_port
*)dev_id
;
2685 disable_percpu_irq(port
->pp
->dev
->irq
);
2686 napi_schedule(&port
->napi
);
2691 static int mvneta_fixed_link_update(struct mvneta_port
*pp
,
2692 struct phy_device
*phy
)
2694 struct fixed_phy_status status
;
2695 struct fixed_phy_status changed
= {};
2696 u32 gmac_stat
= mvreg_read(pp
, MVNETA_GMAC_STATUS
);
2698 status
.link
= !!(gmac_stat
& MVNETA_GMAC_LINK_UP
);
2699 if (gmac_stat
& MVNETA_GMAC_SPEED_1000
)
2700 status
.speed
= SPEED_1000
;
2701 else if (gmac_stat
& MVNETA_GMAC_SPEED_100
)
2702 status
.speed
= SPEED_100
;
2704 status
.speed
= SPEED_10
;
2705 status
.duplex
= !!(gmac_stat
& MVNETA_GMAC_FULL_DUPLEX
);
2709 fixed_phy_update_state(phy
, &status
, &changed
);
2714 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2715 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2716 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2717 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2718 * Each CPU has its own causeRxTx register
2720 static int mvneta_poll(struct napi_struct
*napi
, int budget
)
2725 struct mvneta_port
*pp
= netdev_priv(napi
->dev
);
2726 struct net_device
*ndev
= pp
->dev
;
2727 struct mvneta_pcpu_port
*port
= this_cpu_ptr(pp
->ports
);
2729 if (!netif_running(pp
->dev
)) {
2730 napi_complete(napi
);
2734 /* Read cause register */
2735 cause_rx_tx
= mvreg_read(pp
, MVNETA_INTR_NEW_CAUSE
);
2736 if (cause_rx_tx
& MVNETA_MISCINTR_INTR_MASK
) {
2737 u32 cause_misc
= mvreg_read(pp
, MVNETA_INTR_MISC_CAUSE
);
2739 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
2740 if (pp
->use_inband_status
&& (cause_misc
&
2741 (MVNETA_CAUSE_PHY_STATUS_CHANGE
|
2742 MVNETA_CAUSE_LINK_CHANGE
|
2743 MVNETA_CAUSE_PSC_SYNC_CHANGE
))) {
2744 mvneta_fixed_link_update(pp
, ndev
->phydev
);
2748 /* Release Tx descriptors */
2749 if (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
) {
2750 mvneta_tx_done_gbe(pp
, (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
));
2751 cause_rx_tx
&= ~MVNETA_TX_INTR_MASK_ALL
;
2754 /* For the case where the last mvneta_poll did not process all
2757 rx_queue
= fls(((cause_rx_tx
>> 8) & 0xff));
2759 cause_rx_tx
|= pp
->neta_armada3700
? pp
->cause_rx_tx
:
2763 rx_queue
= rx_queue
- 1;
2765 rx_done
= mvneta_rx_hwbm(pp
, budget
, &pp
->rxqs
[rx_queue
]);
2767 rx_done
= mvneta_rx_swbm(pp
, budget
, &pp
->rxqs
[rx_queue
]);
2770 if (rx_done
< budget
) {
2772 napi_complete_done(napi
, rx_done
);
2774 if (pp
->neta_armada3700
) {
2775 unsigned long flags
;
2777 local_irq_save(flags
);
2778 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
2779 MVNETA_RX_INTR_MASK(rxq_number
) |
2780 MVNETA_TX_INTR_MASK(txq_number
) |
2781 MVNETA_MISCINTR_INTR_MASK
);
2782 local_irq_restore(flags
);
2784 enable_percpu_irq(pp
->dev
->irq
, 0);
2788 if (pp
->neta_armada3700
)
2789 pp
->cause_rx_tx
= cause_rx_tx
;
2791 port
->cause_rx_tx
= cause_rx_tx
;
2796 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2797 static int mvneta_rxq_fill(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
2802 for (i
= 0; i
< num
; i
++) {
2803 memset(rxq
->descs
+ i
, 0, sizeof(struct mvneta_rx_desc
));
2804 if (mvneta_rx_refill(pp
, rxq
->descs
+ i
, rxq
) != 0) {
2805 netdev_err(pp
->dev
, "%s:rxq %d, %d of %d buffs filled\n",
2806 __func__
, rxq
->id
, i
, num
);
2811 /* Add this number of RX descriptors as non occupied (ready to
2814 mvneta_rxq_non_occup_desc_add(pp
, rxq
, i
);
2819 /* Free all packets pending transmit from all TXQs and reset TX port */
2820 static void mvneta_tx_reset(struct mvneta_port
*pp
)
2824 /* free the skb's in the tx ring */
2825 for (queue
= 0; queue
< txq_number
; queue
++)
2826 mvneta_txq_done_force(pp
, &pp
->txqs
[queue
]);
2828 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
2829 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
2832 static void mvneta_rx_reset(struct mvneta_port
*pp
)
2834 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
2835 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
2838 /* Rx/Tx queue initialization/cleanup methods */
2840 /* Create a specified RX queue */
2841 static int mvneta_rxq_init(struct mvneta_port
*pp
,
2842 struct mvneta_rx_queue
*rxq
)
2845 rxq
->size
= pp
->rx_ring_size
;
2847 /* Allocate memory for RX descriptors */
2848 rxq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2849 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2850 &rxq
->descs_phys
, GFP_KERNEL
);
2854 rxq
->last_desc
= rxq
->size
- 1;
2856 /* Set Rx descriptors queue starting address */
2857 mvreg_write(pp
, MVNETA_RXQ_BASE_ADDR_REG(rxq
->id
), rxq
->descs_phys
);
2858 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), rxq
->size
);
2861 mvneta_rxq_offset_set(pp
, rxq
, NET_SKB_PAD
- pp
->rx_offset_correction
);
2863 /* Set coalescing pkts and time */
2864 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
2865 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
2868 /* Fill RXQ with buffers from RX pool */
2869 mvneta_rxq_buf_size_set(pp
, rxq
,
2870 MVNETA_RX_BUF_SIZE(pp
->pkt_size
));
2871 mvneta_rxq_bm_disable(pp
, rxq
);
2872 mvneta_rxq_fill(pp
, rxq
, rxq
->size
);
2874 mvneta_rxq_bm_enable(pp
, rxq
);
2875 mvneta_rxq_long_pool_set(pp
, rxq
);
2876 mvneta_rxq_short_pool_set(pp
, rxq
);
2877 mvneta_rxq_non_occup_desc_add(pp
, rxq
, rxq
->size
);
2883 /* Cleanup Rx queue */
2884 static void mvneta_rxq_deinit(struct mvneta_port
*pp
,
2885 struct mvneta_rx_queue
*rxq
)
2887 mvneta_rxq_drop_pkts(pp
, rxq
);
2890 dma_free_coherent(pp
->dev
->dev
.parent
,
2891 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2897 rxq
->next_desc_to_proc
= 0;
2898 rxq
->descs_phys
= 0;
2901 /* Create and initialize a tx queue */
2902 static int mvneta_txq_init(struct mvneta_port
*pp
,
2903 struct mvneta_tx_queue
*txq
)
2907 txq
->size
= pp
->tx_ring_size
;
2909 /* A queue must always have room for at least one skb.
2910 * Therefore, stop the queue when the free entries reaches
2911 * the maximum number of descriptors per skb.
2913 txq
->tx_stop_threshold
= txq
->size
- MVNETA_MAX_SKB_DESCS
;
2914 txq
->tx_wake_threshold
= txq
->tx_stop_threshold
/ 2;
2917 /* Allocate memory for TX descriptors */
2918 txq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2919 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2920 &txq
->descs_phys
, GFP_KERNEL
);
2924 txq
->last_desc
= txq
->size
- 1;
2926 /* Set maximum bandwidth for enabled TXQs */
2927 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0x03ffffff);
2928 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0x3fffffff);
2930 /* Set Tx descriptors queue starting address */
2931 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), txq
->descs_phys
);
2932 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), txq
->size
);
2934 txq
->tx_skb
= kmalloc_array(txq
->size
, sizeof(*txq
->tx_skb
),
2937 dma_free_coherent(pp
->dev
->dev
.parent
,
2938 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2939 txq
->descs
, txq
->descs_phys
);
2943 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2944 txq
->tso_hdrs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2945 txq
->size
* TSO_HEADER_SIZE
,
2946 &txq
->tso_hdrs_phys
, GFP_KERNEL
);
2947 if (!txq
->tso_hdrs
) {
2949 dma_free_coherent(pp
->dev
->dev
.parent
,
2950 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2951 txq
->descs
, txq
->descs_phys
);
2954 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
2956 /* Setup XPS mapping */
2958 cpu
= txq
->id
% num_present_cpus();
2960 cpu
= pp
->rxq_def
% num_present_cpus();
2961 cpumask_set_cpu(cpu
, &txq
->affinity_mask
);
2962 netif_set_xps_queue(pp
->dev
, &txq
->affinity_mask
, txq
->id
);
2967 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2968 static void mvneta_txq_deinit(struct mvneta_port
*pp
,
2969 struct mvneta_tx_queue
*txq
)
2971 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2976 dma_free_coherent(pp
->dev
->dev
.parent
,
2977 txq
->size
* TSO_HEADER_SIZE
,
2978 txq
->tso_hdrs
, txq
->tso_hdrs_phys
);
2980 dma_free_coherent(pp
->dev
->dev
.parent
,
2981 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2982 txq
->descs
, txq
->descs_phys
);
2984 netdev_tx_reset_queue(nq
);
2988 txq
->next_desc_to_proc
= 0;
2989 txq
->descs_phys
= 0;
2991 /* Set minimum bandwidth for disabled TXQs */
2992 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0);
2993 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0);
2995 /* Set Tx descriptors queue starting address and size */
2996 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), 0);
2997 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), 0);
3000 /* Cleanup all Tx queues */
3001 static void mvneta_cleanup_txqs(struct mvneta_port
*pp
)
3005 for (queue
= 0; queue
< txq_number
; queue
++)
3006 mvneta_txq_deinit(pp
, &pp
->txqs
[queue
]);
3009 /* Cleanup all Rx queues */
3010 static void mvneta_cleanup_rxqs(struct mvneta_port
*pp
)
3014 for (queue
= 0; queue
< txq_number
; queue
++)
3015 mvneta_rxq_deinit(pp
, &pp
->rxqs
[queue
]);
3019 /* Init all Rx queues */
3020 static int mvneta_setup_rxqs(struct mvneta_port
*pp
)
3024 for (queue
= 0; queue
< rxq_number
; queue
++) {
3025 int err
= mvneta_rxq_init(pp
, &pp
->rxqs
[queue
]);
3028 netdev_err(pp
->dev
, "%s: can't create rxq=%d\n",
3030 mvneta_cleanup_rxqs(pp
);
3038 /* Init all tx queues */
3039 static int mvneta_setup_txqs(struct mvneta_port
*pp
)
3043 for (queue
= 0; queue
< txq_number
; queue
++) {
3044 int err
= mvneta_txq_init(pp
, &pp
->txqs
[queue
]);
3046 netdev_err(pp
->dev
, "%s: can't create txq=%d\n",
3048 mvneta_cleanup_txqs(pp
);
3056 static void mvneta_start_dev(struct mvneta_port
*pp
)
3059 struct net_device
*ndev
= pp
->dev
;
3061 mvneta_max_rx_size_set(pp
, pp
->pkt_size
);
3062 mvneta_txq_max_tx_size_set(pp
, pp
->pkt_size
);
3064 /* start the Rx/Tx activity */
3065 mvneta_port_enable(pp
);
3067 if (!pp
->neta_armada3700
) {
3068 /* Enable polling on the port */
3069 for_each_online_cpu(cpu
) {
3070 struct mvneta_pcpu_port
*port
=
3071 per_cpu_ptr(pp
->ports
, cpu
);
3073 napi_enable(&port
->napi
);
3076 napi_enable(&pp
->napi
);
3079 /* Unmask interrupts. It has to be done from each CPU */
3080 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
3082 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
3083 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3084 MVNETA_CAUSE_LINK_CHANGE
|
3085 MVNETA_CAUSE_PSC_SYNC_CHANGE
);
3087 phy_start(ndev
->phydev
);
3088 netif_tx_start_all_queues(pp
->dev
);
3091 static void mvneta_stop_dev(struct mvneta_port
*pp
)
3094 struct net_device
*ndev
= pp
->dev
;
3096 phy_stop(ndev
->phydev
);
3098 if (!pp
->neta_armada3700
) {
3099 for_each_online_cpu(cpu
) {
3100 struct mvneta_pcpu_port
*port
=
3101 per_cpu_ptr(pp
->ports
, cpu
);
3103 napi_disable(&port
->napi
);
3106 napi_disable(&pp
->napi
);
3109 netif_carrier_off(pp
->dev
);
3111 mvneta_port_down(pp
);
3112 netif_tx_stop_all_queues(pp
->dev
);
3114 /* Stop the port activity */
3115 mvneta_port_disable(pp
);
3117 /* Clear all ethernet port interrupts */
3118 on_each_cpu(mvneta_percpu_clear_intr_cause
, pp
, true);
3120 /* Mask all ethernet port interrupts */
3121 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
3123 mvneta_tx_reset(pp
);
3124 mvneta_rx_reset(pp
);
3127 static void mvneta_percpu_enable(void *arg
)
3129 struct mvneta_port
*pp
= arg
;
3131 enable_percpu_irq(pp
->dev
->irq
, IRQ_TYPE_NONE
);
3134 static void mvneta_percpu_disable(void *arg
)
3136 struct mvneta_port
*pp
= arg
;
3138 disable_percpu_irq(pp
->dev
->irq
);
3141 /* Change the device mtu */
3142 static int mvneta_change_mtu(struct net_device
*dev
, int mtu
)
3144 struct mvneta_port
*pp
= netdev_priv(dev
);
3147 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu
), 8)) {
3148 netdev_info(dev
, "Illegal MTU value %d, rounding to %d\n",
3149 mtu
, ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8));
3150 mtu
= ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8);
3155 if (!netif_running(dev
)) {
3157 mvneta_bm_update_mtu(pp
, mtu
);
3159 netdev_update_features(dev
);
3163 /* The interface is running, so we have to force a
3164 * reallocation of the queues
3166 mvneta_stop_dev(pp
);
3167 on_each_cpu(mvneta_percpu_disable
, pp
, true);
3169 mvneta_cleanup_txqs(pp
);
3170 mvneta_cleanup_rxqs(pp
);
3173 mvneta_bm_update_mtu(pp
, mtu
);
3175 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(dev
->mtu
);
3176 pp
->frag_size
= SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp
->pkt_size
)) +
3177 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
3179 ret
= mvneta_setup_rxqs(pp
);
3181 netdev_err(dev
, "unable to setup rxqs after MTU change\n");
3185 ret
= mvneta_setup_txqs(pp
);
3187 netdev_err(dev
, "unable to setup txqs after MTU change\n");
3191 on_each_cpu(mvneta_percpu_enable
, pp
, true);
3192 mvneta_start_dev(pp
);
3195 netdev_update_features(dev
);
3200 static netdev_features_t
mvneta_fix_features(struct net_device
*dev
,
3201 netdev_features_t features
)
3203 struct mvneta_port
*pp
= netdev_priv(dev
);
3205 if (pp
->tx_csum_limit
&& dev
->mtu
> pp
->tx_csum_limit
) {
3206 features
&= ~(NETIF_F_IP_CSUM
| NETIF_F_TSO
);
3208 "Disable IP checksum for MTU greater than %dB\n",
3215 /* Get mac address */
3216 static void mvneta_get_mac_addr(struct mvneta_port
*pp
, unsigned char *addr
)
3218 u32 mac_addr_l
, mac_addr_h
;
3220 mac_addr_l
= mvreg_read(pp
, MVNETA_MAC_ADDR_LOW
);
3221 mac_addr_h
= mvreg_read(pp
, MVNETA_MAC_ADDR_HIGH
);
3222 addr
[0] = (mac_addr_h
>> 24) & 0xFF;
3223 addr
[1] = (mac_addr_h
>> 16) & 0xFF;
3224 addr
[2] = (mac_addr_h
>> 8) & 0xFF;
3225 addr
[3] = mac_addr_h
& 0xFF;
3226 addr
[4] = (mac_addr_l
>> 8) & 0xFF;
3227 addr
[5] = mac_addr_l
& 0xFF;
3230 /* Handle setting mac address */
3231 static int mvneta_set_mac_addr(struct net_device
*dev
, void *addr
)
3233 struct mvneta_port
*pp
= netdev_priv(dev
);
3234 struct sockaddr
*sockaddr
= addr
;
3237 ret
= eth_prepare_mac_addr_change(dev
, addr
);
3240 /* Remove previous address table entry */
3241 mvneta_mac_addr_set(pp
, dev
->dev_addr
, -1);
3243 /* Set new addr in hw */
3244 mvneta_mac_addr_set(pp
, sockaddr
->sa_data
, pp
->rxq_def
);
3246 eth_commit_mac_addr_change(dev
, addr
);
3250 static void mvneta_adjust_link(struct net_device
*ndev
)
3252 struct mvneta_port
*pp
= netdev_priv(ndev
);
3253 struct phy_device
*phydev
= ndev
->phydev
;
3254 int status_change
= 0;
3257 if ((pp
->speed
!= phydev
->speed
) ||
3258 (pp
->duplex
!= phydev
->duplex
)) {
3261 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3262 val
&= ~(MVNETA_GMAC_CONFIG_MII_SPEED
|
3263 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3264 MVNETA_GMAC_CONFIG_FULL_DUPLEX
);
3267 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
3269 if (phydev
->speed
== SPEED_1000
)
3270 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
3271 else if (phydev
->speed
== SPEED_100
)
3272 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
3274 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
3276 pp
->duplex
= phydev
->duplex
;
3277 pp
->speed
= phydev
->speed
;
3281 if (phydev
->link
!= pp
->link
) {
3282 if (!phydev
->link
) {
3287 pp
->link
= phydev
->link
;
3291 if (status_change
) {
3293 if (!pp
->use_inband_status
) {
3294 u32 val
= mvreg_read(pp
,
3295 MVNETA_GMAC_AUTONEG_CONFIG
);
3296 val
&= ~MVNETA_GMAC_FORCE_LINK_DOWN
;
3297 val
|= MVNETA_GMAC_FORCE_LINK_PASS
;
3298 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3303 if (!pp
->use_inband_status
) {
3304 u32 val
= mvreg_read(pp
,
3305 MVNETA_GMAC_AUTONEG_CONFIG
);
3306 val
&= ~MVNETA_GMAC_FORCE_LINK_PASS
;
3307 val
|= MVNETA_GMAC_FORCE_LINK_DOWN
;
3308 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3311 mvneta_port_down(pp
);
3313 phy_print_status(phydev
);
3317 static int mvneta_mdio_probe(struct mvneta_port
*pp
)
3319 struct phy_device
*phy_dev
;
3320 struct ethtool_wolinfo wol
= { .cmd
= ETHTOOL_GWOL
};
3322 phy_dev
= of_phy_connect(pp
->dev
, pp
->phy_node
, mvneta_adjust_link
, 0,
3325 netdev_err(pp
->dev
, "could not find the PHY\n");
3329 phy_ethtool_get_wol(phy_dev
, &wol
);
3330 device_set_wakeup_capable(&pp
->dev
->dev
, !!wol
.supported
);
3332 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
3333 phy_dev
->advertising
= phy_dev
->supported
;
3342 static void mvneta_mdio_remove(struct mvneta_port
*pp
)
3344 struct net_device
*ndev
= pp
->dev
;
3346 phy_disconnect(ndev
->phydev
);
3349 /* Electing a CPU must be done in an atomic way: it should be done
3350 * after or before the removal/insertion of a CPU and this function is
3353 static void mvneta_percpu_elect(struct mvneta_port
*pp
)
3355 int elected_cpu
= 0, max_cpu
, cpu
, i
= 0;
3357 /* Use the cpu associated to the rxq when it is online, in all
3358 * the other cases, use the cpu 0 which can't be offline.
3360 if (cpu_online(pp
->rxq_def
))
3361 elected_cpu
= pp
->rxq_def
;
3363 max_cpu
= num_present_cpus();
3365 for_each_online_cpu(cpu
) {
3366 int rxq_map
= 0, txq_map
= 0;
3369 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
3370 if ((rxq
% max_cpu
) == cpu
)
3371 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(rxq
);
3373 if (cpu
== elected_cpu
)
3374 /* Map the default receive queue queue to the
3377 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(pp
->rxq_def
);
3379 /* We update the TX queue map only if we have one
3380 * queue. In this case we associate the TX queue to
3381 * the CPU bound to the default RX queue
3383 if (txq_number
== 1)
3384 txq_map
= (cpu
== elected_cpu
) ?
3385 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3387 txq_map
= mvreg_read(pp
, MVNETA_CPU_MAP(cpu
)) &
3388 MVNETA_CPU_TXQ_ACCESS_ALL_MASK
;
3390 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
), rxq_map
| txq_map
);
3392 /* Update the interrupt mask on each CPU according the
3395 smp_call_function_single(cpu
, mvneta_percpu_unmask_interrupt
,
3402 static int mvneta_cpu_online(unsigned int cpu
, struct hlist_node
*node
)
3405 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
3407 struct mvneta_pcpu_port
*port
= per_cpu_ptr(pp
->ports
, cpu
);
3410 spin_lock(&pp
->lock
);
3412 * Configuring the driver for a new CPU while the driver is
3413 * stopping is racy, so just avoid it.
3415 if (pp
->is_stopped
) {
3416 spin_unlock(&pp
->lock
);
3419 netif_tx_stop_all_queues(pp
->dev
);
3422 * We have to synchronise on tha napi of each CPU except the one
3423 * just being woken up
3425 for_each_online_cpu(other_cpu
) {
3426 if (other_cpu
!= cpu
) {
3427 struct mvneta_pcpu_port
*other_port
=
3428 per_cpu_ptr(pp
->ports
, other_cpu
);
3430 napi_synchronize(&other_port
->napi
);
3434 /* Mask all ethernet port interrupts */
3435 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
3436 napi_enable(&port
->napi
);
3439 * Enable per-CPU interrupts on the CPU that is
3442 mvneta_percpu_enable(pp
);
3445 * Enable per-CPU interrupt on the one CPU we care
3448 mvneta_percpu_elect(pp
);
3450 /* Unmask all ethernet port interrupts */
3451 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
3452 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
3453 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3454 MVNETA_CAUSE_LINK_CHANGE
|
3455 MVNETA_CAUSE_PSC_SYNC_CHANGE
);
3456 netif_tx_start_all_queues(pp
->dev
);
3457 spin_unlock(&pp
->lock
);
3461 static int mvneta_cpu_down_prepare(unsigned int cpu
, struct hlist_node
*node
)
3463 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
3465 struct mvneta_pcpu_port
*port
= per_cpu_ptr(pp
->ports
, cpu
);
3468 * Thanks to this lock we are sure that any pending cpu election is
3471 spin_lock(&pp
->lock
);
3472 /* Mask all ethernet port interrupts */
3473 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
3474 spin_unlock(&pp
->lock
);
3476 napi_synchronize(&port
->napi
);
3477 napi_disable(&port
->napi
);
3478 /* Disable per-CPU interrupts on the CPU that is brought down. */
3479 mvneta_percpu_disable(pp
);
3483 static int mvneta_cpu_dead(unsigned int cpu
, struct hlist_node
*node
)
3485 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
3488 /* Check if a new CPU must be elected now this on is down */
3489 spin_lock(&pp
->lock
);
3490 mvneta_percpu_elect(pp
);
3491 spin_unlock(&pp
->lock
);
3492 /* Unmask all ethernet port interrupts */
3493 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
3494 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
3495 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3496 MVNETA_CAUSE_LINK_CHANGE
|
3497 MVNETA_CAUSE_PSC_SYNC_CHANGE
);
3498 netif_tx_start_all_queues(pp
->dev
);
3502 static int mvneta_open(struct net_device
*dev
)
3504 struct mvneta_port
*pp
= netdev_priv(dev
);
3507 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
);
3508 pp
->frag_size
= SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp
->pkt_size
)) +
3509 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
3511 ret
= mvneta_setup_rxqs(pp
);
3515 ret
= mvneta_setup_txqs(pp
);
3517 goto err_cleanup_rxqs
;
3519 /* Connect to port interrupt line */
3520 if (pp
->neta_armada3700
)
3521 ret
= request_irq(pp
->dev
->irq
, mvneta_isr
, 0,
3524 ret
= request_percpu_irq(pp
->dev
->irq
, mvneta_percpu_isr
,
3525 dev
->name
, pp
->ports
);
3527 netdev_err(pp
->dev
, "cannot request irq %d\n", pp
->dev
->irq
);
3528 goto err_cleanup_txqs
;
3531 if (!pp
->neta_armada3700
) {
3532 /* Enable per-CPU interrupt on all the CPU to handle our RX
3535 on_each_cpu(mvneta_percpu_enable
, pp
, true);
3537 pp
->is_stopped
= false;
3538 /* Register a CPU notifier to handle the case where our CPU
3539 * might be taken offline.
3541 ret
= cpuhp_state_add_instance_nocalls(online_hpstate
,
3546 ret
= cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
3549 goto err_free_online_hp
;
3552 /* In default link is down */
3553 netif_carrier_off(pp
->dev
);
3555 ret
= mvneta_mdio_probe(pp
);
3557 netdev_err(dev
, "cannot probe MDIO bus\n");
3558 goto err_free_dead_hp
;
3561 mvneta_start_dev(pp
);
3566 if (!pp
->neta_armada3700
)
3567 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
3570 if (!pp
->neta_armada3700
)
3571 cpuhp_state_remove_instance_nocalls(online_hpstate
,
3574 if (pp
->neta_armada3700
) {
3575 free_irq(pp
->dev
->irq
, pp
);
3577 on_each_cpu(mvneta_percpu_disable
, pp
, true);
3578 free_percpu_irq(pp
->dev
->irq
, pp
->ports
);
3581 mvneta_cleanup_txqs(pp
);
3583 mvneta_cleanup_rxqs(pp
);
3587 /* Stop the port, free port interrupt line */
3588 static int mvneta_stop(struct net_device
*dev
)
3590 struct mvneta_port
*pp
= netdev_priv(dev
);
3592 if (!pp
->neta_armada3700
) {
3593 /* Inform that we are stopping so we don't want to setup the
3594 * driver for new CPUs in the notifiers. The code of the
3595 * notifier for CPU online is protected by the same spinlock,
3596 * so when we get the lock, the notifer work is done.
3598 spin_lock(&pp
->lock
);
3599 pp
->is_stopped
= true;
3600 spin_unlock(&pp
->lock
);
3602 mvneta_stop_dev(pp
);
3603 mvneta_mdio_remove(pp
);
3605 cpuhp_state_remove_instance_nocalls(online_hpstate
,
3607 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
3609 on_each_cpu(mvneta_percpu_disable
, pp
, true);
3610 free_percpu_irq(dev
->irq
, pp
->ports
);
3612 mvneta_stop_dev(pp
);
3613 mvneta_mdio_remove(pp
);
3614 free_irq(dev
->irq
, pp
);
3617 mvneta_cleanup_rxqs(pp
);
3618 mvneta_cleanup_txqs(pp
);
3623 static int mvneta_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3628 return phy_mii_ioctl(dev
->phydev
, ifr
, cmd
);
3631 /* Ethtool methods */
3633 /* Set link ksettings (phy address, speed) for ethtools */
3635 mvneta_ethtool_set_link_ksettings(struct net_device
*ndev
,
3636 const struct ethtool_link_ksettings
*cmd
)
3638 struct mvneta_port
*pp
= netdev_priv(ndev
);
3639 struct phy_device
*phydev
= ndev
->phydev
;
3644 if ((cmd
->base
.autoneg
== AUTONEG_ENABLE
) != pp
->use_inband_status
) {
3647 mvneta_set_autoneg(pp
, cmd
->base
.autoneg
== AUTONEG_ENABLE
);
3649 if (cmd
->base
.autoneg
== AUTONEG_DISABLE
) {
3650 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3651 val
&= ~(MVNETA_GMAC_CONFIG_MII_SPEED
|
3652 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3653 MVNETA_GMAC_CONFIG_FULL_DUPLEX
);
3656 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
3658 if (phydev
->speed
== SPEED_1000
)
3659 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
3660 else if (phydev
->speed
== SPEED_100
)
3661 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
3663 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
3666 pp
->use_inband_status
= (cmd
->base
.autoneg
== AUTONEG_ENABLE
);
3667 netdev_info(pp
->dev
, "autoneg status set to %i\n",
3668 pp
->use_inband_status
);
3670 if (netif_running(ndev
)) {
3671 mvneta_port_down(pp
);
3676 return phy_ethtool_ksettings_set(ndev
->phydev
, cmd
);
3679 /* Set interrupt coalescing for ethtools */
3680 static int mvneta_ethtool_set_coalesce(struct net_device
*dev
,
3681 struct ethtool_coalesce
*c
)
3683 struct mvneta_port
*pp
= netdev_priv(dev
);
3686 for (queue
= 0; queue
< rxq_number
; queue
++) {
3687 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
3688 rxq
->time_coal
= c
->rx_coalesce_usecs
;
3689 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
3690 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
3691 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
3694 for (queue
= 0; queue
< txq_number
; queue
++) {
3695 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
3696 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
3697 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
3703 /* get coalescing for ethtools */
3704 static int mvneta_ethtool_get_coalesce(struct net_device
*dev
,
3705 struct ethtool_coalesce
*c
)
3707 struct mvneta_port
*pp
= netdev_priv(dev
);
3709 c
->rx_coalesce_usecs
= pp
->rxqs
[0].time_coal
;
3710 c
->rx_max_coalesced_frames
= pp
->rxqs
[0].pkts_coal
;
3712 c
->tx_max_coalesced_frames
= pp
->txqs
[0].done_pkts_coal
;
3717 static void mvneta_ethtool_get_drvinfo(struct net_device
*dev
,
3718 struct ethtool_drvinfo
*drvinfo
)
3720 strlcpy(drvinfo
->driver
, MVNETA_DRIVER_NAME
,
3721 sizeof(drvinfo
->driver
));
3722 strlcpy(drvinfo
->version
, MVNETA_DRIVER_VERSION
,
3723 sizeof(drvinfo
->version
));
3724 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
3725 sizeof(drvinfo
->bus_info
));
3729 static void mvneta_ethtool_get_ringparam(struct net_device
*netdev
,
3730 struct ethtool_ringparam
*ring
)
3732 struct mvneta_port
*pp
= netdev_priv(netdev
);
3734 ring
->rx_max_pending
= MVNETA_MAX_RXD
;
3735 ring
->tx_max_pending
= MVNETA_MAX_TXD
;
3736 ring
->rx_pending
= pp
->rx_ring_size
;
3737 ring
->tx_pending
= pp
->tx_ring_size
;
3740 static int mvneta_ethtool_set_ringparam(struct net_device
*dev
,
3741 struct ethtool_ringparam
*ring
)
3743 struct mvneta_port
*pp
= netdev_priv(dev
);
3745 if ((ring
->rx_pending
== 0) || (ring
->tx_pending
== 0))
3747 pp
->rx_ring_size
= ring
->rx_pending
< MVNETA_MAX_RXD
?
3748 ring
->rx_pending
: MVNETA_MAX_RXD
;
3750 pp
->tx_ring_size
= clamp_t(u16
, ring
->tx_pending
,
3751 MVNETA_MAX_SKB_DESCS
* 2, MVNETA_MAX_TXD
);
3752 if (pp
->tx_ring_size
!= ring
->tx_pending
)
3753 netdev_warn(dev
, "TX queue size set to %u (requested %u)\n",
3754 pp
->tx_ring_size
, ring
->tx_pending
);
3756 if (netif_running(dev
)) {
3758 if (mvneta_open(dev
)) {
3760 "error on opening device after ring param change\n");
3768 static void mvneta_ethtool_get_strings(struct net_device
*netdev
, u32 sset
,
3771 if (sset
== ETH_SS_STATS
) {
3774 for (i
= 0; i
< ARRAY_SIZE(mvneta_statistics
); i
++)
3775 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3776 mvneta_statistics
[i
].name
, ETH_GSTRING_LEN
);
3780 static void mvneta_ethtool_update_stats(struct mvneta_port
*pp
)
3782 const struct mvneta_statistic
*s
;
3783 void __iomem
*base
= pp
->base
;
3788 for (i
= 0, s
= mvneta_statistics
;
3789 s
< mvneta_statistics
+ ARRAY_SIZE(mvneta_statistics
);
3793 val
= readl_relaxed(base
+ s
->offset
);
3794 pp
->ethtool_stats
[i
] += val
;
3797 /* Docs say to read low 32-bit then high */
3798 low
= readl_relaxed(base
+ s
->offset
);
3799 high
= readl_relaxed(base
+ s
->offset
+ 4);
3800 val64
= (u64
)high
<< 32 | low
;
3801 pp
->ethtool_stats
[i
] += val64
;
3807 static void mvneta_ethtool_get_stats(struct net_device
*dev
,
3808 struct ethtool_stats
*stats
, u64
*data
)
3810 struct mvneta_port
*pp
= netdev_priv(dev
);
3813 mvneta_ethtool_update_stats(pp
);
3815 for (i
= 0; i
< ARRAY_SIZE(mvneta_statistics
); i
++)
3816 *data
++ = pp
->ethtool_stats
[i
];
3819 static int mvneta_ethtool_get_sset_count(struct net_device
*dev
, int sset
)
3821 if (sset
== ETH_SS_STATS
)
3822 return ARRAY_SIZE(mvneta_statistics
);
3826 static u32
mvneta_ethtool_get_rxfh_indir_size(struct net_device
*dev
)
3828 return MVNETA_RSS_LU_TABLE_SIZE
;
3831 static int mvneta_ethtool_get_rxnfc(struct net_device
*dev
,
3832 struct ethtool_rxnfc
*info
,
3833 u32
*rules __always_unused
)
3835 switch (info
->cmd
) {
3836 case ETHTOOL_GRXRINGS
:
3837 info
->data
= rxq_number
;
3846 static int mvneta_config_rss(struct mvneta_port
*pp
)
3851 netif_tx_stop_all_queues(pp
->dev
);
3853 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
3855 /* We have to synchronise on the napi of each CPU */
3856 for_each_online_cpu(cpu
) {
3857 struct mvneta_pcpu_port
*pcpu_port
=
3858 per_cpu_ptr(pp
->ports
, cpu
);
3860 napi_synchronize(&pcpu_port
->napi
);
3861 napi_disable(&pcpu_port
->napi
);
3864 pp
->rxq_def
= pp
->indir
[0];
3866 /* Update unicast mapping */
3867 mvneta_set_rx_mode(pp
->dev
);
3869 /* Update val of portCfg register accordingly with all RxQueue types */
3870 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(pp
->rxq_def
);
3871 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
3873 /* Update the elected CPU matching the new rxq_def */
3874 spin_lock(&pp
->lock
);
3875 mvneta_percpu_elect(pp
);
3876 spin_unlock(&pp
->lock
);
3878 /* We have to synchronise on the napi of each CPU */
3879 for_each_online_cpu(cpu
) {
3880 struct mvneta_pcpu_port
*pcpu_port
=
3881 per_cpu_ptr(pp
->ports
, cpu
);
3883 napi_enable(&pcpu_port
->napi
);
3886 netif_tx_start_all_queues(pp
->dev
);
3891 static int mvneta_ethtool_set_rxfh(struct net_device
*dev
, const u32
*indir
,
3892 const u8
*key
, const u8 hfunc
)
3894 struct mvneta_port
*pp
= netdev_priv(dev
);
3896 /* Current code for Armada 3700 doesn't support RSS features yet */
3897 if (pp
->neta_armada3700
)
3900 /* We require at least one supported parameter to be changed
3901 * and no change in any of the unsupported parameters
3904 (hfunc
!= ETH_RSS_HASH_NO_CHANGE
&& hfunc
!= ETH_RSS_HASH_TOP
))
3910 memcpy(pp
->indir
, indir
, MVNETA_RSS_LU_TABLE_SIZE
);
3912 return mvneta_config_rss(pp
);
3915 static int mvneta_ethtool_get_rxfh(struct net_device
*dev
, u32
*indir
, u8
*key
,
3918 struct mvneta_port
*pp
= netdev_priv(dev
);
3920 /* Current code for Armada 3700 doesn't support RSS features yet */
3921 if (pp
->neta_armada3700
)
3925 *hfunc
= ETH_RSS_HASH_TOP
;
3930 memcpy(indir
, pp
->indir
, MVNETA_RSS_LU_TABLE_SIZE
);
3935 static void mvneta_ethtool_get_wol(struct net_device
*dev
,
3936 struct ethtool_wolinfo
*wol
)
3942 phy_ethtool_get_wol(dev
->phydev
, wol
);
3945 static int mvneta_ethtool_set_wol(struct net_device
*dev
,
3946 struct ethtool_wolinfo
*wol
)
3953 ret
= phy_ethtool_set_wol(dev
->phydev
, wol
);
3955 device_set_wakeup_enable(&dev
->dev
, !!wol
->wolopts
);
3960 static const struct net_device_ops mvneta_netdev_ops
= {
3961 .ndo_open
= mvneta_open
,
3962 .ndo_stop
= mvneta_stop
,
3963 .ndo_start_xmit
= mvneta_tx
,
3964 .ndo_set_rx_mode
= mvneta_set_rx_mode
,
3965 .ndo_set_mac_address
= mvneta_set_mac_addr
,
3966 .ndo_change_mtu
= mvneta_change_mtu
,
3967 .ndo_fix_features
= mvneta_fix_features
,
3968 .ndo_get_stats64
= mvneta_get_stats64
,
3969 .ndo_do_ioctl
= mvneta_ioctl
,
3972 static const struct ethtool_ops mvneta_eth_tool_ops
= {
3973 .nway_reset
= phy_ethtool_nway_reset
,
3974 .get_link
= ethtool_op_get_link
,
3975 .set_coalesce
= mvneta_ethtool_set_coalesce
,
3976 .get_coalesce
= mvneta_ethtool_get_coalesce
,
3977 .get_drvinfo
= mvneta_ethtool_get_drvinfo
,
3978 .get_ringparam
= mvneta_ethtool_get_ringparam
,
3979 .set_ringparam
= mvneta_ethtool_set_ringparam
,
3980 .get_strings
= mvneta_ethtool_get_strings
,
3981 .get_ethtool_stats
= mvneta_ethtool_get_stats
,
3982 .get_sset_count
= mvneta_ethtool_get_sset_count
,
3983 .get_rxfh_indir_size
= mvneta_ethtool_get_rxfh_indir_size
,
3984 .get_rxnfc
= mvneta_ethtool_get_rxnfc
,
3985 .get_rxfh
= mvneta_ethtool_get_rxfh
,
3986 .set_rxfh
= mvneta_ethtool_set_rxfh
,
3987 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
3988 .set_link_ksettings
= mvneta_ethtool_set_link_ksettings
,
3989 .get_wol
= mvneta_ethtool_get_wol
,
3990 .set_wol
= mvneta_ethtool_set_wol
,
3994 static int mvneta_init(struct device
*dev
, struct mvneta_port
*pp
)
3999 mvneta_port_disable(pp
);
4001 /* Set port default values */
4002 mvneta_defaults_set(pp
);
4004 pp
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(*pp
->txqs
), GFP_KERNEL
);
4008 /* Initialize TX descriptor rings */
4009 for (queue
= 0; queue
< txq_number
; queue
++) {
4010 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
4012 txq
->size
= pp
->tx_ring_size
;
4013 txq
->done_pkts_coal
= MVNETA_TXDONE_COAL_PKTS
;
4016 pp
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(*pp
->rxqs
), GFP_KERNEL
);
4020 /* Create Rx descriptor rings */
4021 for (queue
= 0; queue
< rxq_number
; queue
++) {
4022 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
4024 rxq
->size
= pp
->rx_ring_size
;
4025 rxq
->pkts_coal
= MVNETA_RX_COAL_PKTS
;
4026 rxq
->time_coal
= MVNETA_RX_COAL_USEC
;
4028 = devm_kmalloc_array(pp
->dev
->dev
.parent
,
4030 sizeof(*rxq
->buf_virt_addr
),
4032 if (!rxq
->buf_virt_addr
)
4039 /* platform glue : initialize decoding windows */
4040 static void mvneta_conf_mbus_windows(struct mvneta_port
*pp
,
4041 const struct mbus_dram_target_info
*dram
)
4047 for (i
= 0; i
< 6; i
++) {
4048 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
4049 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
4052 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
4059 for (i
= 0; i
< dram
->num_cs
; i
++) {
4060 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
4062 mvreg_write(pp
, MVNETA_WIN_BASE(i
),
4063 (cs
->base
& 0xffff0000) |
4064 (cs
->mbus_attr
<< 8) |
4065 dram
->mbus_dram_target_id
);
4067 mvreg_write(pp
, MVNETA_WIN_SIZE(i
),
4068 (cs
->size
- 1) & 0xffff0000);
4070 win_enable
&= ~(1 << i
);
4071 win_protect
|= 3 << (2 * i
);
4074 /* For Armada3700 open default 4GB Mbus window, leaving
4075 * arbitration of target/attribute to a different layer
4078 mvreg_write(pp
, MVNETA_WIN_SIZE(0), 0xffff0000);
4079 win_enable
&= ~BIT(0);
4083 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
4084 mvreg_write(pp
, MVNETA_ACCESS_PROTECT_ENABLE
, win_protect
);
4087 /* Power up the port */
4088 static int mvneta_port_power_up(struct mvneta_port
*pp
, int phy_mode
)
4092 /* MAC Cause register should be cleared */
4093 mvreg_write(pp
, MVNETA_UNIT_INTR_CAUSE
, 0);
4095 ctrl
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
4097 /* Even though it might look weird, when we're configured in
4098 * SGMII or QSGMII mode, the RGMII bit needs to be set.
4101 case PHY_INTERFACE_MODE_QSGMII
:
4102 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_QSGMII_SERDES_PROTO
);
4103 ctrl
|= MVNETA_GMAC2_PCS_ENABLE
| MVNETA_GMAC2_PORT_RGMII
;
4105 case PHY_INTERFACE_MODE_SGMII
:
4106 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_SGMII_SERDES_PROTO
);
4107 ctrl
|= MVNETA_GMAC2_PCS_ENABLE
| MVNETA_GMAC2_PORT_RGMII
;
4109 case PHY_INTERFACE_MODE_RGMII
:
4110 case PHY_INTERFACE_MODE_RGMII_ID
:
4111 case PHY_INTERFACE_MODE_RGMII_RXID
:
4112 case PHY_INTERFACE_MODE_RGMII_TXID
:
4113 ctrl
|= MVNETA_GMAC2_PORT_RGMII
;
4119 /* Cancel Port Reset */
4120 ctrl
&= ~MVNETA_GMAC2_PORT_RESET
;
4121 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, ctrl
);
4123 while ((mvreg_read(pp
, MVNETA_GMAC_CTRL_2
) &
4124 MVNETA_GMAC2_PORT_RESET
) != 0)
4130 /* Device initialization routine */
4131 static int mvneta_probe(struct platform_device
*pdev
)
4133 struct resource
*res
;
4134 struct device_node
*dn
= pdev
->dev
.of_node
;
4135 struct device_node
*phy_node
;
4136 struct device_node
*bm_node
;
4137 struct mvneta_port
*pp
;
4138 struct net_device
*dev
;
4139 const char *dt_mac_addr
;
4140 char hw_mac_addr
[ETH_ALEN
];
4141 const char *mac_from
;
4142 const char *managed
;
4148 dev
= alloc_etherdev_mqs(sizeof(struct mvneta_port
), txq_number
, rxq_number
);
4152 dev
->irq
= irq_of_parse_and_map(dn
, 0);
4153 if (dev
->irq
== 0) {
4155 goto err_free_netdev
;
4158 phy_node
= of_parse_phandle(dn
, "phy", 0);
4160 if (!of_phy_is_fixed_link(dn
)) {
4161 dev_err(&pdev
->dev
, "no PHY specified\n");
4166 err
= of_phy_register_fixed_link(dn
);
4168 dev_err(&pdev
->dev
, "cannot register fixed PHY\n");
4172 /* In the case of a fixed PHY, the DT node associated
4173 * to the PHY is the Ethernet MAC DT node.
4175 phy_node
= of_node_get(dn
);
4178 phy_mode
= of_get_phy_mode(dn
);
4180 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
4182 goto err_put_phy_node
;
4185 dev
->tx_queue_len
= MVNETA_MAX_TXD
;
4186 dev
->watchdog_timeo
= 5 * HZ
;
4187 dev
->netdev_ops
= &mvneta_netdev_ops
;
4189 dev
->ethtool_ops
= &mvneta_eth_tool_ops
;
4191 pp
= netdev_priv(dev
);
4192 spin_lock_init(&pp
->lock
);
4193 pp
->phy_node
= phy_node
;
4194 pp
->phy_interface
= phy_mode
;
4196 err
= of_property_read_string(dn
, "managed", &managed
);
4197 pp
->use_inband_status
= (err
== 0 &&
4198 strcmp(managed
, "in-band-status") == 0);
4200 pp
->rxq_def
= rxq_def
;
4202 /* Set RX packet offset correction for platforms, whose
4203 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
4204 * platforms and 0B for 32-bit ones.
4206 pp
->rx_offset_correction
=
4207 max(0, NET_SKB_PAD
- MVNETA_RX_PKT_OFFSET_CORRECTION
);
4209 pp
->indir
[0] = rxq_def
;
4211 /* Get special SoC configurations */
4212 if (of_device_is_compatible(dn
, "marvell,armada-3700-neta"))
4213 pp
->neta_armada3700
= true;
4215 pp
->clk
= devm_clk_get(&pdev
->dev
, "core");
4216 if (IS_ERR(pp
->clk
))
4217 pp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
4218 if (IS_ERR(pp
->clk
)) {
4219 err
= PTR_ERR(pp
->clk
);
4220 goto err_put_phy_node
;
4223 clk_prepare_enable(pp
->clk
);
4225 pp
->clk_bus
= devm_clk_get(&pdev
->dev
, "bus");
4226 if (!IS_ERR(pp
->clk_bus
))
4227 clk_prepare_enable(pp
->clk_bus
);
4229 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
4230 pp
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
4231 if (IS_ERR(pp
->base
)) {
4232 err
= PTR_ERR(pp
->base
);
4236 /* Alloc per-cpu port structure */
4237 pp
->ports
= alloc_percpu(struct mvneta_pcpu_port
);
4243 /* Alloc per-cpu stats */
4244 pp
->stats
= netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats
);
4247 goto err_free_ports
;
4250 dt_mac_addr
= of_get_mac_address(dn
);
4252 mac_from
= "device tree";
4253 memcpy(dev
->dev_addr
, dt_mac_addr
, ETH_ALEN
);
4255 mvneta_get_mac_addr(pp
, hw_mac_addr
);
4256 if (is_valid_ether_addr(hw_mac_addr
)) {
4257 mac_from
= "hardware";
4258 memcpy(dev
->dev_addr
, hw_mac_addr
, ETH_ALEN
);
4260 mac_from
= "random";
4261 eth_hw_addr_random(dev
);
4265 if (!of_property_read_u32(dn
, "tx-csum-limit", &tx_csum_limit
)) {
4266 if (tx_csum_limit
< 0 ||
4267 tx_csum_limit
> MVNETA_TX_CSUM_MAX_SIZE
) {
4268 tx_csum_limit
= MVNETA_TX_CSUM_DEF_SIZE
;
4269 dev_info(&pdev
->dev
,
4270 "Wrong TX csum limit in DT, set to %dB\n",
4271 MVNETA_TX_CSUM_DEF_SIZE
);
4273 } else if (of_device_is_compatible(dn
, "marvell,armada-370-neta")) {
4274 tx_csum_limit
= MVNETA_TX_CSUM_DEF_SIZE
;
4276 tx_csum_limit
= MVNETA_TX_CSUM_MAX_SIZE
;
4279 pp
->tx_csum_limit
= tx_csum_limit
;
4281 pp
->dram_target_info
= mv_mbus_dram_info();
4282 /* Armada3700 requires setting default configuration of Mbus
4283 * windows, however without using filled mbus_dram_target_info
4286 if (pp
->dram_target_info
|| pp
->neta_armada3700
)
4287 mvneta_conf_mbus_windows(pp
, pp
->dram_target_info
);
4289 pp
->tx_ring_size
= MVNETA_MAX_TXD
;
4290 pp
->rx_ring_size
= MVNETA_MAX_RXD
;
4293 SET_NETDEV_DEV(dev
, &pdev
->dev
);
4295 pp
->id
= global_port_id
++;
4297 /* Obtain access to BM resources if enabled and already initialized */
4298 bm_node
= of_parse_phandle(dn
, "buffer-manager", 0);
4299 if (bm_node
&& bm_node
->data
) {
4300 pp
->bm_priv
= bm_node
->data
;
4301 err
= mvneta_bm_port_init(pdev
, pp
);
4303 dev_info(&pdev
->dev
, "use SW buffer management\n");
4307 of_node_put(bm_node
);
4309 err
= mvneta_init(&pdev
->dev
, pp
);
4313 err
= mvneta_port_power_up(pp
, phy_mode
);
4315 dev_err(&pdev
->dev
, "can't power up port\n");
4319 /* Armada3700 network controller does not support per-cpu
4320 * operation, so only single NAPI should be initialized.
4322 if (pp
->neta_armada3700
) {
4323 netif_napi_add(dev
, &pp
->napi
, mvneta_poll
, NAPI_POLL_WEIGHT
);
4325 for_each_present_cpu(cpu
) {
4326 struct mvneta_pcpu_port
*port
=
4327 per_cpu_ptr(pp
->ports
, cpu
);
4329 netif_napi_add(dev
, &port
->napi
, mvneta_poll
,
4335 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO
;
4336 dev
->hw_features
|= dev
->features
;
4337 dev
->vlan_features
|= dev
->features
;
4338 dev
->priv_flags
|= IFF_LIVE_ADDR_CHANGE
;
4339 dev
->gso_max_segs
= MVNETA_MAX_TSO_SEGS
;
4341 /* MTU range: 68 - 9676 */
4342 dev
->min_mtu
= ETH_MIN_MTU
;
4343 /* 9676 == 9700 - 20 and rounding to 8 */
4344 dev
->max_mtu
= 9676;
4346 err
= register_netdev(dev
);
4348 dev_err(&pdev
->dev
, "failed to register\n");
4349 goto err_free_stats
;
4352 netdev_info(dev
, "Using %s mac address %pM\n", mac_from
,
4355 platform_set_drvdata(pdev
, pp
->dev
);
4357 if (pp
->use_inband_status
) {
4358 struct phy_device
*phy
= of_phy_find_device(dn
);
4360 mvneta_fixed_link_update(pp
, phy
);
4362 put_device(&phy
->mdio
.dev
);
4368 unregister_netdev(dev
);
4370 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
4371 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
,
4375 free_percpu(pp
->stats
);
4377 free_percpu(pp
->ports
);
4379 clk_disable_unprepare(pp
->clk_bus
);
4380 clk_disable_unprepare(pp
->clk
);
4382 of_node_put(phy_node
);
4383 if (of_phy_is_fixed_link(dn
))
4384 of_phy_deregister_fixed_link(dn
);
4386 irq_dispose_mapping(dev
->irq
);
4392 /* Device removal routine */
4393 static int mvneta_remove(struct platform_device
*pdev
)
4395 struct net_device
*dev
= platform_get_drvdata(pdev
);
4396 struct device_node
*dn
= pdev
->dev
.of_node
;
4397 struct mvneta_port
*pp
= netdev_priv(dev
);
4399 unregister_netdev(dev
);
4400 clk_disable_unprepare(pp
->clk_bus
);
4401 clk_disable_unprepare(pp
->clk
);
4402 free_percpu(pp
->ports
);
4403 free_percpu(pp
->stats
);
4404 if (of_phy_is_fixed_link(dn
))
4405 of_phy_deregister_fixed_link(dn
);
4406 irq_dispose_mapping(dev
->irq
);
4407 of_node_put(pp
->phy_node
);
4411 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
4412 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
,
4419 #ifdef CONFIG_PM_SLEEP
4420 static int mvneta_suspend(struct device
*device
)
4422 struct net_device
*dev
= dev_get_drvdata(device
);
4423 struct mvneta_port
*pp
= netdev_priv(dev
);
4425 if (netif_running(dev
))
4427 netif_device_detach(dev
);
4428 clk_disable_unprepare(pp
->clk_bus
);
4429 clk_disable_unprepare(pp
->clk
);
4433 static int mvneta_resume(struct device
*device
)
4435 struct platform_device
*pdev
= to_platform_device(device
);
4436 struct net_device
*dev
= dev_get_drvdata(device
);
4437 struct mvneta_port
*pp
= netdev_priv(dev
);
4440 clk_prepare_enable(pp
->clk
);
4441 if (!IS_ERR(pp
->clk_bus
))
4442 clk_prepare_enable(pp
->clk_bus
);
4443 if (pp
->dram_target_info
|| pp
->neta_armada3700
)
4444 mvneta_conf_mbus_windows(pp
, pp
->dram_target_info
);
4446 err
= mvneta_bm_port_init(pdev
, pp
);
4448 dev_info(&pdev
->dev
, "use SW buffer management\n");
4452 mvneta_defaults_set(pp
);
4453 err
= mvneta_port_power_up(pp
, pp
->phy_interface
);
4455 dev_err(device
, "can't power up port\n");
4459 if (pp
->use_inband_status
)
4460 mvneta_fixed_link_update(pp
, dev
->phydev
);
4462 netif_device_attach(dev
);
4463 if (netif_running(dev
)) {
4465 mvneta_set_rx_mode(dev
);
4472 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops
, mvneta_suspend
, mvneta_resume
);
4474 static const struct of_device_id mvneta_match
[] = {
4475 { .compatible
= "marvell,armada-370-neta" },
4476 { .compatible
= "marvell,armada-xp-neta" },
4477 { .compatible
= "marvell,armada-3700-neta" },
4480 MODULE_DEVICE_TABLE(of
, mvneta_match
);
4482 static struct platform_driver mvneta_driver
= {
4483 .probe
= mvneta_probe
,
4484 .remove
= mvneta_remove
,
4486 .name
= MVNETA_DRIVER_NAME
,
4487 .of_match_table
= mvneta_match
,
4488 .pm
= &mvneta_pm_ops
,
4492 static int __init
mvneta_driver_init(void)
4496 ret
= cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN
, "net/mvmeta:online",
4498 mvneta_cpu_down_prepare
);
4501 online_hpstate
= ret
;
4502 ret
= cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD
, "net/mvneta:dead",
4503 NULL
, mvneta_cpu_dead
);
4507 ret
= platform_driver_register(&mvneta_driver
);
4513 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD
);
4515 cpuhp_remove_multi_state(online_hpstate
);
4519 module_init(mvneta_driver_init
);
4521 static void __exit
mvneta_driver_exit(void)
4523 platform_driver_unregister(&mvneta_driver
);
4524 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD
);
4525 cpuhp_remove_multi_state(online_hpstate
);
4527 module_exit(mvneta_driver_exit
);
4529 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4530 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4531 MODULE_LICENSE("GPL");
4533 module_param(rxq_number
, int, S_IRUGO
);
4534 module_param(txq_number
, int, S_IRUGO
);
4536 module_param(rxq_def
, int, S_IRUGO
);
4537 module_param(rx_copybreak
, int, S_IRUGO
| S_IWUSR
);