2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/if_vlan.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_address.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
37 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
38 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
39 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
40 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
41 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
42 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
43 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
44 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
45 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
46 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
47 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
48 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
49 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
50 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
51 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
52 #define MVNETA_PORT_RX_RESET 0x1cc0
53 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
54 #define MVNETA_PHY_ADDR 0x2000
55 #define MVNETA_PHY_ADDR_MASK 0x1f
56 #define MVNETA_MBUS_RETRY 0x2010
57 #define MVNETA_UNIT_INTR_CAUSE 0x2080
58 #define MVNETA_UNIT_CONTROL 0x20B0
59 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
60 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
61 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
62 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
63 #define MVNETA_BASE_ADDR_ENABLE 0x2290
64 #define MVNETA_PORT_CONFIG 0x2400
65 #define MVNETA_UNI_PROMISC_MODE BIT(0)
66 #define MVNETA_DEF_RXQ(q) ((q) << 1)
67 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
68 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
69 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
70 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
71 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
72 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
73 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
74 MVNETA_DEF_RXQ_ARP(q) | \
75 MVNETA_DEF_RXQ_TCP(q) | \
76 MVNETA_DEF_RXQ_UDP(q) | \
77 MVNETA_DEF_RXQ_BPDU(q) | \
78 MVNETA_TX_UNSET_ERR_SUM | \
79 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
80 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
81 #define MVNETA_MAC_ADDR_LOW 0x2414
82 #define MVNETA_MAC_ADDR_HIGH 0x2418
83 #define MVNETA_SDMA_CONFIG 0x241c
84 #define MVNETA_SDMA_BRST_SIZE_16 4
85 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
86 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
87 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
88 #define MVNETA_DESC_SWAP BIT(6)
89 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
90 #define MVNETA_PORT_STATUS 0x2444
91 #define MVNETA_TX_IN_PRGRS BIT(1)
92 #define MVNETA_TX_FIFO_EMPTY BIT(8)
93 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
94 #define MVNETA_SERDES_CFG 0x24A0
95 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
96 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
97 #define MVNETA_TYPE_PRIO 0x24bc
98 #define MVNETA_FORCE_UNI BIT(21)
99 #define MVNETA_TXQ_CMD_1 0x24e4
100 #define MVNETA_TXQ_CMD 0x2448
101 #define MVNETA_TXQ_DISABLE_SHIFT 8
102 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
103 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
104 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
105 #define MVNETA_ACC_MODE 0x2500
106 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
107 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
108 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
109 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
111 /* Exception Interrupt Port/Queue Cause register */
113 #define MVNETA_INTR_NEW_CAUSE 0x25a0
114 #define MVNETA_INTR_NEW_MASK 0x25a4
116 /* bits 0..7 = TXQ SENT, one bit per queue.
117 * bits 8..15 = RXQ OCCUP, one bit per queue.
118 * bits 16..23 = RXQ FREE, one bit per queue.
119 * bit 29 = OLD_REG_SUM, see old reg ?
120 * bit 30 = TX_ERR_SUM, one bit for 4 ports
121 * bit 31 = MISC_SUM, one bit for 4 ports
123 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
124 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
125 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
126 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
127 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
129 #define MVNETA_INTR_OLD_CAUSE 0x25a8
130 #define MVNETA_INTR_OLD_MASK 0x25ac
132 /* Data Path Port/Queue Cause Register */
133 #define MVNETA_INTR_MISC_CAUSE 0x25b0
134 #define MVNETA_INTR_MISC_MASK 0x25b4
136 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
137 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
138 #define MVNETA_CAUSE_PTP BIT(4)
140 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
141 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
142 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
143 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
144 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
145 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
146 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
147 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
149 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
150 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
151 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
153 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
154 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
155 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
157 #define MVNETA_INTR_ENABLE 0x25b8
158 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
159 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF
161 #define MVNETA_RXQ_CMD 0x2680
162 #define MVNETA_RXQ_DISABLE_SHIFT 8
163 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
164 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
165 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
166 #define MVNETA_GMAC_CTRL_0 0x2c00
167 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
168 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
169 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
170 #define MVNETA_GMAC_CTRL_2 0x2c08
171 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
172 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
173 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
174 #define MVNETA_GMAC2_PORT_RESET BIT(6)
175 #define MVNETA_GMAC_STATUS 0x2c10
176 #define MVNETA_GMAC_LINK_UP BIT(0)
177 #define MVNETA_GMAC_SPEED_1000 BIT(1)
178 #define MVNETA_GMAC_SPEED_100 BIT(2)
179 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
180 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
181 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
182 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
183 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
184 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
185 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
186 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
187 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
188 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
189 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
190 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
191 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
192 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
193 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
194 #define MVNETA_MIB_COUNTERS_BASE 0x3080
195 #define MVNETA_MIB_LATE_COLLISION 0x7c
196 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
197 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
198 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
199 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
200 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
201 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
202 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
203 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
204 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
205 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
206 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
207 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
208 #define MVNETA_PORT_TX_RESET 0x3cf0
209 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
210 #define MVNETA_TX_MTU 0x3e0c
211 #define MVNETA_TX_TOKEN_SIZE 0x3e14
212 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
213 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
214 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
216 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
218 /* Descriptor ring Macros */
219 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
220 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
222 /* Various constants */
225 #define MVNETA_TXDONE_COAL_PKTS 1
226 #define MVNETA_RX_COAL_PKTS 32
227 #define MVNETA_RX_COAL_USEC 100
229 /* The two bytes Marvell header. Either contains a special value used
230 * by Marvell switches when a specific hardware mode is enabled (not
231 * supported by this driver) or is filled automatically by zeroes on
232 * the RX side. Those two bytes being at the front of the Ethernet
233 * header, they allow to have the IP header aligned on a 4 bytes
234 * boundary automatically: the hardware skips those two bytes on its
237 #define MVNETA_MH_SIZE 2
239 #define MVNETA_VLAN_TAG_LEN 4
241 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
242 #define MVNETA_TX_CSUM_MAX_SIZE 9800
243 #define MVNETA_ACC_MODE_EXT 1
245 /* Timeout constants */
246 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
247 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
248 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
250 #define MVNETA_TX_MTU_MAX 0x3ffff
252 /* TSO header size */
253 #define TSO_HEADER_SIZE 128
255 /* Max number of Rx descriptors */
256 #define MVNETA_MAX_RXD 128
258 /* Max number of Tx descriptors */
259 #define MVNETA_MAX_TXD 532
261 /* Max number of allowed TCP segments for software TSO */
262 #define MVNETA_MAX_TSO_SEGS 100
264 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
266 /* descriptor aligned size */
267 #define MVNETA_DESC_ALIGNED_SIZE 32
269 #define MVNETA_RX_PKT_SIZE(mtu) \
270 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
271 ETH_HLEN + ETH_FCS_LEN, \
272 MVNETA_CPU_D_CACHE_LINE_SIZE)
274 #define IS_TSO_HEADER(txq, addr) \
275 ((addr >= txq->tso_hdrs_phys) && \
276 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
278 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
280 struct mvneta_pcpu_stats
{
281 struct u64_stats_sync syncp
;
290 unsigned int frag_size
;
292 struct mvneta_rx_queue
*rxqs
;
293 struct mvneta_tx_queue
*txqs
;
294 struct net_device
*dev
;
297 struct napi_struct napi
;
304 struct mvneta_pcpu_stats
*stats
;
306 struct mii_bus
*mii_bus
;
307 struct phy_device
*phy_dev
;
308 phy_interface_t phy_interface
;
309 struct device_node
*phy_node
;
313 unsigned int tx_csum_limit
;
314 int use_inband_status
:1;
317 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
318 * layout of the transmit and reception DMA descriptors, and their
319 * layout is therefore defined by the hardware design
322 #define MVNETA_TX_L3_OFF_SHIFT 0
323 #define MVNETA_TX_IP_HLEN_SHIFT 8
324 #define MVNETA_TX_L4_UDP BIT(16)
325 #define MVNETA_TX_L3_IP6 BIT(17)
326 #define MVNETA_TXD_IP_CSUM BIT(18)
327 #define MVNETA_TXD_Z_PAD BIT(19)
328 #define MVNETA_TXD_L_DESC BIT(20)
329 #define MVNETA_TXD_F_DESC BIT(21)
330 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
331 MVNETA_TXD_L_DESC | \
333 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
334 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
336 #define MVNETA_RXD_ERR_CRC 0x0
337 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
338 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
339 #define MVNETA_RXD_ERR_LEN BIT(18)
340 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
341 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
342 #define MVNETA_RXD_L3_IP4 BIT(25)
343 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
344 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
346 #if defined(__LITTLE_ENDIAN)
347 struct mvneta_tx_desc
{
348 u32 command
; /* Options used by HW for packet transmitting.*/
349 u16 reserverd1
; /* csum_l4 (for future use) */
350 u16 data_size
; /* Data size of transmitted packet in bytes */
351 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
352 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
353 u32 reserved3
[4]; /* Reserved - (for future use) */
356 struct mvneta_rx_desc
{
357 u32 status
; /* Info about received packet */
358 u16 reserved1
; /* pnc_info - (for future use, PnC) */
359 u16 data_size
; /* Size of received packet in bytes */
361 u32 buf_phys_addr
; /* Physical address of the buffer */
362 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
364 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
365 u16 reserved3
; /* prefetch_cmd, for future use */
366 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
368 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
369 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
372 struct mvneta_tx_desc
{
373 u16 data_size
; /* Data size of transmitted packet in bytes */
374 u16 reserverd1
; /* csum_l4 (for future use) */
375 u32 command
; /* Options used by HW for packet transmitting.*/
376 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
377 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
378 u32 reserved3
[4]; /* Reserved - (for future use) */
381 struct mvneta_rx_desc
{
382 u16 data_size
; /* Size of received packet in bytes */
383 u16 reserved1
; /* pnc_info - (for future use, PnC) */
384 u32 status
; /* Info about received packet */
386 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
387 u32 buf_phys_addr
; /* Physical address of the buffer */
389 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
390 u16 reserved3
; /* prefetch_cmd, for future use */
391 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
393 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
394 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
398 struct mvneta_tx_queue
{
399 /* Number of this TX queue, in the range 0-7 */
402 /* Number of TX DMA descriptors in the descriptor ring */
405 /* Number of currently used TX DMA descriptor in the
409 int tx_stop_threshold
;
410 int tx_wake_threshold
;
412 /* Array of transmitted skb */
413 struct sk_buff
**tx_skb
;
415 /* Index of last TX DMA descriptor that was inserted */
418 /* Index of the TX DMA descriptor to be cleaned up */
423 /* Virtual address of the TX DMA descriptors array */
424 struct mvneta_tx_desc
*descs
;
426 /* DMA address of the TX DMA descriptors array */
427 dma_addr_t descs_phys
;
429 /* Index of the last TX DMA descriptor */
432 /* Index of the next TX DMA descriptor to process */
433 int next_desc_to_proc
;
435 /* DMA buffers for TSO headers */
438 /* DMA address of TSO headers */
439 dma_addr_t tso_hdrs_phys
;
442 struct mvneta_rx_queue
{
443 /* rx queue number, in the range 0-7 */
446 /* num of rx descriptors in the rx descriptor ring */
449 /* counter of times when mvneta_refill() failed */
455 /* Virtual address of the RX DMA descriptors array */
456 struct mvneta_rx_desc
*descs
;
458 /* DMA address of the RX DMA descriptors array */
459 dma_addr_t descs_phys
;
461 /* Index of the last RX DMA descriptor */
464 /* Index of the next RX DMA descriptor to process */
465 int next_desc_to_proc
;
468 /* The hardware supports eight (8) rx queues, but we are only allowing
469 * the first one to be used. Therefore, let's just allocate one queue.
471 static int rxq_number
= 1;
472 static int txq_number
= 8;
476 static int rx_copybreak __read_mostly
= 256;
478 #define MVNETA_DRIVER_NAME "mvneta"
479 #define MVNETA_DRIVER_VERSION "1.0"
481 /* Utility/helper methods */
483 /* Write helper method */
484 static void mvreg_write(struct mvneta_port
*pp
, u32 offset
, u32 data
)
486 writel(data
, pp
->base
+ offset
);
489 /* Read helper method */
490 static u32
mvreg_read(struct mvneta_port
*pp
, u32 offset
)
492 return readl(pp
->base
+ offset
);
495 /* Increment txq get counter */
496 static void mvneta_txq_inc_get(struct mvneta_tx_queue
*txq
)
498 txq
->txq_get_index
++;
499 if (txq
->txq_get_index
== txq
->size
)
500 txq
->txq_get_index
= 0;
503 /* Increment txq put counter */
504 static void mvneta_txq_inc_put(struct mvneta_tx_queue
*txq
)
506 txq
->txq_put_index
++;
507 if (txq
->txq_put_index
== txq
->size
)
508 txq
->txq_put_index
= 0;
512 /* Clear all MIB counters */
513 static void mvneta_mib_counters_clear(struct mvneta_port
*pp
)
518 /* Perform dummy reads from MIB counters */
519 for (i
= 0; i
< MVNETA_MIB_LATE_COLLISION
; i
+= 4)
520 dummy
= mvreg_read(pp
, (MVNETA_MIB_COUNTERS_BASE
+ i
));
523 /* Get System Network Statistics */
524 struct rtnl_link_stats64
*mvneta_get_stats64(struct net_device
*dev
,
525 struct rtnl_link_stats64
*stats
)
527 struct mvneta_port
*pp
= netdev_priv(dev
);
531 for_each_possible_cpu(cpu
) {
532 struct mvneta_pcpu_stats
*cpu_stats
;
538 cpu_stats
= per_cpu_ptr(pp
->stats
, cpu
);
540 start
= u64_stats_fetch_begin_irq(&cpu_stats
->syncp
);
541 rx_packets
= cpu_stats
->rx_packets
;
542 rx_bytes
= cpu_stats
->rx_bytes
;
543 tx_packets
= cpu_stats
->tx_packets
;
544 tx_bytes
= cpu_stats
->tx_bytes
;
545 } while (u64_stats_fetch_retry_irq(&cpu_stats
->syncp
, start
));
547 stats
->rx_packets
+= rx_packets
;
548 stats
->rx_bytes
+= rx_bytes
;
549 stats
->tx_packets
+= tx_packets
;
550 stats
->tx_bytes
+= tx_bytes
;
553 stats
->rx_errors
= dev
->stats
.rx_errors
;
554 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
556 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
561 /* Rx descriptors helper methods */
563 /* Checks whether the RX descriptor having this status is both the first
564 * and the last descriptor for the RX packet. Each RX packet is currently
565 * received through a single RX descriptor, so not having each RX
566 * descriptor with its first and last bits set is an error
568 static int mvneta_rxq_desc_is_first_last(u32 status
)
570 return (status
& MVNETA_RXD_FIRST_LAST_DESC
) ==
571 MVNETA_RXD_FIRST_LAST_DESC
;
574 /* Add number of descriptors ready to receive new packets */
575 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port
*pp
,
576 struct mvneta_rx_queue
*rxq
,
579 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
582 while (ndescs
> MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
) {
583 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
584 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
<<
585 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
586 ndescs
-= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
;
589 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
590 (ndescs
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
593 /* Get number of RX descriptors occupied by received packets */
594 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port
*pp
,
595 struct mvneta_rx_queue
*rxq
)
599 val
= mvreg_read(pp
, MVNETA_RXQ_STATUS_REG(rxq
->id
));
600 return val
& MVNETA_RXQ_OCCUPIED_ALL_MASK
;
603 /* Update num of rx desc called upon return from rx path or
604 * from mvneta_rxq_drop_pkts().
606 static void mvneta_rxq_desc_num_update(struct mvneta_port
*pp
,
607 struct mvneta_rx_queue
*rxq
,
608 int rx_done
, int rx_filled
)
612 if ((rx_done
<= 0xff) && (rx_filled
<= 0xff)) {
614 (rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
);
615 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
619 /* Only 255 descriptors can be added at once */
620 while ((rx_done
> 0) || (rx_filled
> 0)) {
621 if (rx_done
<= 0xff) {
628 if (rx_filled
<= 0xff) {
629 val
|= rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
632 val
|= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
635 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
639 /* Get pointer to next RX descriptor to be processed by SW */
640 static struct mvneta_rx_desc
*
641 mvneta_rxq_next_desc_get(struct mvneta_rx_queue
*rxq
)
643 int rx_desc
= rxq
->next_desc_to_proc
;
645 rxq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(rxq
, rx_desc
);
646 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
647 return rxq
->descs
+ rx_desc
;
650 /* Change maximum receive size of the port. */
651 static void mvneta_max_rx_size_set(struct mvneta_port
*pp
, int max_rx_size
)
655 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
656 val
&= ~MVNETA_GMAC_MAX_RX_SIZE_MASK
;
657 val
|= ((max_rx_size
- MVNETA_MH_SIZE
) / 2) <<
658 MVNETA_GMAC_MAX_RX_SIZE_SHIFT
;
659 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
663 /* Set rx queue offset */
664 static void mvneta_rxq_offset_set(struct mvneta_port
*pp
,
665 struct mvneta_rx_queue
*rxq
,
670 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
671 val
&= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK
;
674 val
|= MVNETA_RXQ_PKT_OFFSET_MASK(offset
>> 3);
675 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
679 /* Tx descriptors helper methods */
681 /* Update HW with number of TX descriptors to be sent */
682 static void mvneta_txq_pend_desc_add(struct mvneta_port
*pp
,
683 struct mvneta_tx_queue
*txq
,
688 /* Only 255 descriptors can be added at once ; Assume caller
689 * process TX desriptors in quanta less than 256
692 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
695 /* Get pointer to next TX descriptor to be processed (send) by HW */
696 static struct mvneta_tx_desc
*
697 mvneta_txq_next_desc_get(struct mvneta_tx_queue
*txq
)
699 int tx_desc
= txq
->next_desc_to_proc
;
701 txq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(txq
, tx_desc
);
702 return txq
->descs
+ tx_desc
;
705 /* Release the last allocated TX descriptor. Useful to handle DMA
706 * mapping failures in the TX path.
708 static void mvneta_txq_desc_put(struct mvneta_tx_queue
*txq
)
710 if (txq
->next_desc_to_proc
== 0)
711 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
713 txq
->next_desc_to_proc
--;
716 /* Set rxq buf size */
717 static void mvneta_rxq_buf_size_set(struct mvneta_port
*pp
,
718 struct mvneta_rx_queue
*rxq
,
723 val
= mvreg_read(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
));
725 val
&= ~MVNETA_RXQ_BUF_SIZE_MASK
;
726 val
|= ((buf_size
>> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT
);
728 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), val
);
731 /* Disable buffer management (BM) */
732 static void mvneta_rxq_bm_disable(struct mvneta_port
*pp
,
733 struct mvneta_rx_queue
*rxq
)
737 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
738 val
&= ~MVNETA_RXQ_HW_BUF_ALLOC
;
739 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
742 /* Start the Ethernet port RX and TX activity */
743 static void mvneta_port_up(struct mvneta_port
*pp
)
748 /* Enable all initialized TXs. */
749 mvneta_mib_counters_clear(pp
);
751 for (queue
= 0; queue
< txq_number
; queue
++) {
752 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
753 if (txq
->descs
!= NULL
)
754 q_map
|= (1 << queue
);
756 mvreg_write(pp
, MVNETA_TXQ_CMD
, q_map
);
758 /* Enable all initialized RXQs. */
760 for (queue
= 0; queue
< rxq_number
; queue
++) {
761 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
762 if (rxq
->descs
!= NULL
)
763 q_map
|= (1 << queue
);
766 mvreg_write(pp
, MVNETA_RXQ_CMD
, q_map
);
769 /* Stop the Ethernet port activity */
770 static void mvneta_port_down(struct mvneta_port
*pp
)
775 /* Stop Rx port activity. Check port Rx activity. */
776 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
) & MVNETA_RXQ_ENABLE_MASK
;
778 /* Issue stop command for active channels only */
780 mvreg_write(pp
, MVNETA_RXQ_CMD
,
781 val
<< MVNETA_RXQ_DISABLE_SHIFT
);
783 /* Wait for all Rx activity to terminate. */
786 if (count
++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC
) {
788 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
794 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
);
795 } while (val
& 0xff);
797 /* Stop Tx port activity. Check port Tx activity. Issue stop
798 * command for active channels only
800 val
= (mvreg_read(pp
, MVNETA_TXQ_CMD
)) & MVNETA_TXQ_ENABLE_MASK
;
803 mvreg_write(pp
, MVNETA_TXQ_CMD
,
804 (val
<< MVNETA_TXQ_DISABLE_SHIFT
));
806 /* Wait for all Tx activity to terminate. */
809 if (count
++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC
) {
811 "TIMEOUT for TX stopped status=0x%08x\n",
817 /* Check TX Command reg that all Txqs are stopped */
818 val
= mvreg_read(pp
, MVNETA_TXQ_CMD
);
820 } while (val
& 0xff);
822 /* Double check to verify that TX FIFO is empty */
825 if (count
++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT
) {
827 "TX FIFO empty timeout status=0x08%x\n",
833 val
= mvreg_read(pp
, MVNETA_PORT_STATUS
);
834 } while (!(val
& MVNETA_TX_FIFO_EMPTY
) &&
835 (val
& MVNETA_TX_IN_PRGRS
));
840 /* Enable the port by setting the port enable bit of the MAC control register */
841 static void mvneta_port_enable(struct mvneta_port
*pp
)
846 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
847 val
|= MVNETA_GMAC0_PORT_ENABLE
;
848 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
851 /* Disable the port and wait for about 200 usec before retuning */
852 static void mvneta_port_disable(struct mvneta_port
*pp
)
856 /* Reset the Enable bit in the Serial Control Register */
857 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
858 val
&= ~MVNETA_GMAC0_PORT_ENABLE
;
859 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
864 /* Multicast tables methods */
866 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
867 static void mvneta_set_ucast_table(struct mvneta_port
*pp
, int queue
)
875 val
= 0x1 | (queue
<< 1);
876 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
879 for (offset
= 0; offset
<= 0xc; offset
+= 4)
880 mvreg_write(pp
, MVNETA_DA_FILT_UCAST_BASE
+ offset
, val
);
883 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
884 static void mvneta_set_special_mcast_table(struct mvneta_port
*pp
, int queue
)
892 val
= 0x1 | (queue
<< 1);
893 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
896 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
897 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ offset
, val
);
901 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
902 static void mvneta_set_other_mcast_table(struct mvneta_port
*pp
, int queue
)
908 memset(pp
->mcast_count
, 0, sizeof(pp
->mcast_count
));
911 memset(pp
->mcast_count
, 1, sizeof(pp
->mcast_count
));
912 val
= 0x1 | (queue
<< 1);
913 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
916 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
917 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ offset
, val
);
920 /* This method sets defaults to the NETA port:
921 * Clears interrupt Cause and Mask registers.
922 * Clears all MAC tables.
923 * Sets defaults to all registers.
924 * Resets RX and TX descriptor rings.
926 * This method can be called after mvneta_port_down() to return the port
927 * settings to defaults.
929 static void mvneta_defaults_set(struct mvneta_port
*pp
)
935 /* Clear all Cause registers */
936 mvreg_write(pp
, MVNETA_INTR_NEW_CAUSE
, 0);
937 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
938 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
940 /* Mask all interrupts */
941 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
942 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
943 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
944 mvreg_write(pp
, MVNETA_INTR_ENABLE
, 0);
946 /* Enable MBUS Retry bit16 */
947 mvreg_write(pp
, MVNETA_MBUS_RETRY
, 0x20);
949 /* Set CPU queue access map - all CPUs have access to all RX
950 * queues and to all TX queues
952 for (cpu
= 0; cpu
< CONFIG_NR_CPUS
; cpu
++)
953 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
),
954 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK
|
955 MVNETA_CPU_TXQ_ACCESS_ALL_MASK
));
957 /* Reset RX and TX DMAs */
958 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
959 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
961 /* Disable Legacy WRR, Disable EJP, Release from reset */
962 mvreg_write(pp
, MVNETA_TXQ_CMD_1
, 0);
963 for (queue
= 0; queue
< txq_number
; queue
++) {
964 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(queue
), 0);
965 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(queue
), 0);
968 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
969 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
971 /* Set Port Acceleration Mode */
972 val
= MVNETA_ACC_MODE_EXT
;
973 mvreg_write(pp
, MVNETA_ACC_MODE
, val
);
975 /* Update val of portCfg register accordingly with all RxQueue types */
976 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def
);
977 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
980 mvreg_write(pp
, MVNETA_PORT_CONFIG_EXTEND
, val
);
981 mvreg_write(pp
, MVNETA_RX_MIN_FRAME_SIZE
, 64);
983 /* Build PORT_SDMA_CONFIG_REG */
986 /* Default burst size */
987 val
|= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
988 val
|= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
989 val
|= MVNETA_RX_NO_DATA_SWAP
| MVNETA_TX_NO_DATA_SWAP
;
991 #if defined(__BIG_ENDIAN)
992 val
|= MVNETA_DESC_SWAP
;
995 /* Assign port SDMA configuration */
996 mvreg_write(pp
, MVNETA_SDMA_CONFIG
, val
);
998 /* Disable PHY polling in hardware, since we're using the
999 * kernel phylib to do this.
1001 val
= mvreg_read(pp
, MVNETA_UNIT_CONTROL
);
1002 val
&= ~MVNETA_PHY_POLLING_ENABLE
;
1003 mvreg_write(pp
, MVNETA_UNIT_CONTROL
, val
);
1005 if (pp
->use_inband_status
) {
1006 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
1007 val
&= ~(MVNETA_GMAC_FORCE_LINK_PASS
|
1008 MVNETA_GMAC_FORCE_LINK_DOWN
|
1009 MVNETA_GMAC_AN_FLOW_CTRL_EN
);
1010 val
|= MVNETA_GMAC_INBAND_AN_ENABLE
|
1011 MVNETA_GMAC_AN_SPEED_EN
|
1012 MVNETA_GMAC_AN_DUPLEX_EN
;
1013 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1014 val
= mvreg_read(pp
, MVNETA_GMAC_CLOCK_DIVIDER
);
1015 val
|= MVNETA_GMAC_1MS_CLOCK_ENABLE
;
1016 mvreg_write(pp
, MVNETA_GMAC_CLOCK_DIVIDER
, val
);
1018 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
1019 val
&= ~(MVNETA_GMAC_INBAND_AN_ENABLE
|
1020 MVNETA_GMAC_AN_SPEED_EN
|
1021 MVNETA_GMAC_AN_DUPLEX_EN
);
1022 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
1025 mvneta_set_ucast_table(pp
, -1);
1026 mvneta_set_special_mcast_table(pp
, -1);
1027 mvneta_set_other_mcast_table(pp
, -1);
1029 /* Set port interrupt enable register - default enable all */
1030 mvreg_write(pp
, MVNETA_INTR_ENABLE
,
1031 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1032 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK
));
1035 /* Set max sizes for tx queues */
1036 static void mvneta_txq_max_tx_size_set(struct mvneta_port
*pp
, int max_tx_size
)
1042 mtu
= max_tx_size
* 8;
1043 if (mtu
> MVNETA_TX_MTU_MAX
)
1044 mtu
= MVNETA_TX_MTU_MAX
;
1047 val
= mvreg_read(pp
, MVNETA_TX_MTU
);
1048 val
&= ~MVNETA_TX_MTU_MAX
;
1050 mvreg_write(pp
, MVNETA_TX_MTU
, val
);
1052 /* TX token size and all TXQs token size must be larger that MTU */
1053 val
= mvreg_read(pp
, MVNETA_TX_TOKEN_SIZE
);
1055 size
= val
& MVNETA_TX_TOKEN_SIZE_MAX
;
1058 val
&= ~MVNETA_TX_TOKEN_SIZE_MAX
;
1060 mvreg_write(pp
, MVNETA_TX_TOKEN_SIZE
, val
);
1062 for (queue
= 0; queue
< txq_number
; queue
++) {
1063 val
= mvreg_read(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
));
1065 size
= val
& MVNETA_TXQ_TOKEN_SIZE_MAX
;
1068 val
&= ~MVNETA_TXQ_TOKEN_SIZE_MAX
;
1070 mvreg_write(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
), val
);
1075 /* Set unicast address */
1076 static void mvneta_set_ucast_addr(struct mvneta_port
*pp
, u8 last_nibble
,
1079 unsigned int unicast_reg
;
1080 unsigned int tbl_offset
;
1081 unsigned int reg_offset
;
1083 /* Locate the Unicast table entry */
1084 last_nibble
= (0xf & last_nibble
);
1086 /* offset from unicast tbl base */
1087 tbl_offset
= (last_nibble
/ 4) * 4;
1089 /* offset within the above reg */
1090 reg_offset
= last_nibble
% 4;
1092 unicast_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
));
1095 /* Clear accepts frame bit at specified unicast DA tbl entry */
1096 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1098 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1099 unicast_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1102 mvreg_write(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
), unicast_reg
);
1105 /* Set mac address */
1106 static void mvneta_mac_addr_set(struct mvneta_port
*pp
, unsigned char *addr
,
1113 mac_l
= (addr
[4] << 8) | (addr
[5]);
1114 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) |
1115 (addr
[2] << 8) | (addr
[3] << 0);
1117 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, mac_l
);
1118 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, mac_h
);
1121 /* Accept frames of this address */
1122 mvneta_set_ucast_addr(pp
, addr
[5], queue
);
1125 /* Set the number of packets that will be received before RX interrupt
1126 * will be generated by HW.
1128 static void mvneta_rx_pkts_coal_set(struct mvneta_port
*pp
,
1129 struct mvneta_rx_queue
*rxq
, u32 value
)
1131 mvreg_write(pp
, MVNETA_RXQ_THRESHOLD_REG(rxq
->id
),
1132 value
| MVNETA_RXQ_NON_OCCUPIED(0));
1133 rxq
->pkts_coal
= value
;
1136 /* Set the time delay in usec before RX interrupt will be generated by
1139 static void mvneta_rx_time_coal_set(struct mvneta_port
*pp
,
1140 struct mvneta_rx_queue
*rxq
, u32 value
)
1143 unsigned long clk_rate
;
1145 clk_rate
= clk_get_rate(pp
->clk
);
1146 val
= (clk_rate
/ 1000000) * value
;
1148 mvreg_write(pp
, MVNETA_RXQ_TIME_COAL_REG(rxq
->id
), val
);
1149 rxq
->time_coal
= value
;
1152 /* Set threshold for TX_DONE pkts coalescing */
1153 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port
*pp
,
1154 struct mvneta_tx_queue
*txq
, u32 value
)
1158 val
= mvreg_read(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
));
1160 val
&= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK
;
1161 val
|= MVNETA_TXQ_SENT_THRESH_MASK(value
);
1163 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), val
);
1165 txq
->done_pkts_coal
= value
;
1168 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1169 static void mvneta_rx_desc_fill(struct mvneta_rx_desc
*rx_desc
,
1170 u32 phys_addr
, u32 cookie
)
1172 rx_desc
->buf_cookie
= cookie
;
1173 rx_desc
->buf_phys_addr
= phys_addr
;
1176 /* Decrement sent descriptors counter */
1177 static void mvneta_txq_sent_desc_dec(struct mvneta_port
*pp
,
1178 struct mvneta_tx_queue
*txq
,
1183 /* Only 255 TX descriptors can be updated at once */
1184 while (sent_desc
> 0xff) {
1185 val
= 0xff << MVNETA_TXQ_DEC_SENT_SHIFT
;
1186 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1187 sent_desc
= sent_desc
- 0xff;
1190 val
= sent_desc
<< MVNETA_TXQ_DEC_SENT_SHIFT
;
1191 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1194 /* Get number of TX descriptors already sent by HW */
1195 static int mvneta_txq_sent_desc_num_get(struct mvneta_port
*pp
,
1196 struct mvneta_tx_queue
*txq
)
1201 val
= mvreg_read(pp
, MVNETA_TXQ_STATUS_REG(txq
->id
));
1202 sent_desc
= (val
& MVNETA_TXQ_SENT_DESC_MASK
) >>
1203 MVNETA_TXQ_SENT_DESC_SHIFT
;
1208 /* Get number of sent descriptors and decrement counter.
1209 * The number of sent descriptors is returned.
1211 static int mvneta_txq_sent_desc_proc(struct mvneta_port
*pp
,
1212 struct mvneta_tx_queue
*txq
)
1216 /* Get number of sent descriptors */
1217 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1219 /* Decrement sent descriptors counter */
1221 mvneta_txq_sent_desc_dec(pp
, txq
, sent_desc
);
1226 /* Set TXQ descriptors fields relevant for CSUM calculation */
1227 static u32
mvneta_txq_desc_csum(int l3_offs
, int l3_proto
,
1228 int ip_hdr_len
, int l4_proto
)
1232 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1233 * G_L4_chk, L4_type; required only for checksum
1236 command
= l3_offs
<< MVNETA_TX_L3_OFF_SHIFT
;
1237 command
|= ip_hdr_len
<< MVNETA_TX_IP_HLEN_SHIFT
;
1239 if (l3_proto
== htons(ETH_P_IP
))
1240 command
|= MVNETA_TXD_IP_CSUM
;
1242 command
|= MVNETA_TX_L3_IP6
;
1244 if (l4_proto
== IPPROTO_TCP
)
1245 command
|= MVNETA_TX_L4_CSUM_FULL
;
1246 else if (l4_proto
== IPPROTO_UDP
)
1247 command
|= MVNETA_TX_L4_UDP
| MVNETA_TX_L4_CSUM_FULL
;
1249 command
|= MVNETA_TX_L4_CSUM_NOT
;
1255 /* Display more error info */
1256 static void mvneta_rx_error(struct mvneta_port
*pp
,
1257 struct mvneta_rx_desc
*rx_desc
)
1259 u32 status
= rx_desc
->status
;
1261 if (!mvneta_rxq_desc_is_first_last(status
)) {
1263 "bad rx status %08x (buffer oversize), size=%d\n",
1264 status
, rx_desc
->data_size
);
1268 switch (status
& MVNETA_RXD_ERR_CODE_MASK
) {
1269 case MVNETA_RXD_ERR_CRC
:
1270 netdev_err(pp
->dev
, "bad rx status %08x (crc error), size=%d\n",
1271 status
, rx_desc
->data_size
);
1273 case MVNETA_RXD_ERR_OVERRUN
:
1274 netdev_err(pp
->dev
, "bad rx status %08x (overrun error), size=%d\n",
1275 status
, rx_desc
->data_size
);
1277 case MVNETA_RXD_ERR_LEN
:
1278 netdev_err(pp
->dev
, "bad rx status %08x (max frame length error), size=%d\n",
1279 status
, rx_desc
->data_size
);
1281 case MVNETA_RXD_ERR_RESOURCE
:
1282 netdev_err(pp
->dev
, "bad rx status %08x (resource error), size=%d\n",
1283 status
, rx_desc
->data_size
);
1288 /* Handle RX checksum offload based on the descriptor's status */
1289 static void mvneta_rx_csum(struct mvneta_port
*pp
, u32 status
,
1290 struct sk_buff
*skb
)
1292 if ((status
& MVNETA_RXD_L3_IP4
) &&
1293 (status
& MVNETA_RXD_L4_CSUM_OK
)) {
1295 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1299 skb
->ip_summed
= CHECKSUM_NONE
;
1302 /* Return tx queue pointer (find last set bit) according to <cause> returned
1303 * form tx_done reg. <cause> must not be null. The return value is always a
1304 * valid queue for matching the first one found in <cause>.
1306 static struct mvneta_tx_queue
*mvneta_tx_done_policy(struct mvneta_port
*pp
,
1309 int queue
= fls(cause
) - 1;
1311 return &pp
->txqs
[queue
];
1314 /* Free tx queue skbuffs */
1315 static void mvneta_txq_bufs_free(struct mvneta_port
*pp
,
1316 struct mvneta_tx_queue
*txq
, int num
)
1320 for (i
= 0; i
< num
; i
++) {
1321 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+
1323 struct sk_buff
*skb
= txq
->tx_skb
[txq
->txq_get_index
];
1325 mvneta_txq_inc_get(txq
);
1327 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
))
1328 dma_unmap_single(pp
->dev
->dev
.parent
,
1329 tx_desc
->buf_phys_addr
,
1330 tx_desc
->data_size
, DMA_TO_DEVICE
);
1333 dev_kfree_skb_any(skb
);
1337 /* Handle end of transmission */
1338 static void mvneta_txq_done(struct mvneta_port
*pp
,
1339 struct mvneta_tx_queue
*txq
)
1341 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1344 tx_done
= mvneta_txq_sent_desc_proc(pp
, txq
);
1348 mvneta_txq_bufs_free(pp
, txq
, tx_done
);
1350 txq
->count
-= tx_done
;
1352 if (netif_tx_queue_stopped(nq
)) {
1353 if (txq
->count
<= txq
->tx_wake_threshold
)
1354 netif_tx_wake_queue(nq
);
1358 static void *mvneta_frag_alloc(const struct mvneta_port
*pp
)
1360 if (likely(pp
->frag_size
<= PAGE_SIZE
))
1361 return netdev_alloc_frag(pp
->frag_size
);
1363 return kmalloc(pp
->frag_size
, GFP_ATOMIC
);
1366 static void mvneta_frag_free(const struct mvneta_port
*pp
, void *data
)
1368 if (likely(pp
->frag_size
<= PAGE_SIZE
))
1369 skb_free_frag(data
);
1374 /* Refill processing */
1375 static int mvneta_rx_refill(struct mvneta_port
*pp
,
1376 struct mvneta_rx_desc
*rx_desc
)
1379 dma_addr_t phys_addr
;
1382 data
= mvneta_frag_alloc(pp
);
1386 phys_addr
= dma_map_single(pp
->dev
->dev
.parent
, data
,
1387 MVNETA_RX_BUF_SIZE(pp
->pkt_size
),
1389 if (unlikely(dma_mapping_error(pp
->dev
->dev
.parent
, phys_addr
))) {
1390 mvneta_frag_free(pp
, data
);
1394 mvneta_rx_desc_fill(rx_desc
, phys_addr
, (u32
)data
);
1398 /* Handle tx checksum */
1399 static u32
mvneta_skb_tx_csum(struct mvneta_port
*pp
, struct sk_buff
*skb
)
1401 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1403 __be16 l3_proto
= vlan_get_protocol(skb
);
1406 if (l3_proto
== htons(ETH_P_IP
)) {
1407 struct iphdr
*ip4h
= ip_hdr(skb
);
1409 /* Calculate IPv4 checksum and L4 checksum */
1410 ip_hdr_len
= ip4h
->ihl
;
1411 l4_proto
= ip4h
->protocol
;
1412 } else if (l3_proto
== htons(ETH_P_IPV6
)) {
1413 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1415 /* Read l4_protocol from one of IPv6 extra headers */
1416 if (skb_network_header_len(skb
) > 0)
1417 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
1418 l4_proto
= ip6h
->nexthdr
;
1420 return MVNETA_TX_L4_CSUM_NOT
;
1422 return mvneta_txq_desc_csum(skb_network_offset(skb
),
1423 l3_proto
, ip_hdr_len
, l4_proto
);
1426 return MVNETA_TX_L4_CSUM_NOT
;
1429 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1432 static struct mvneta_rx_queue
*mvneta_rx_policy(struct mvneta_port
*pp
,
1435 int queue
= fls(cause
>> 8) - 1;
1437 return (queue
< 0 || queue
>= rxq_number
) ? NULL
: &pp
->rxqs
[queue
];
1440 /* Drop packets received by the RXQ and free buffers */
1441 static void mvneta_rxq_drop_pkts(struct mvneta_port
*pp
,
1442 struct mvneta_rx_queue
*rxq
)
1446 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1447 for (i
= 0; i
< rxq
->size
; i
++) {
1448 struct mvneta_rx_desc
*rx_desc
= rxq
->descs
+ i
;
1449 void *data
= (void *)rx_desc
->buf_cookie
;
1451 mvneta_frag_free(pp
, data
);
1452 dma_unmap_single(pp
->dev
->dev
.parent
, rx_desc
->buf_phys_addr
,
1453 MVNETA_RX_BUF_SIZE(pp
->pkt_size
), DMA_FROM_DEVICE
);
1457 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1460 /* Main rx processing */
1461 static int mvneta_rx(struct mvneta_port
*pp
, int rx_todo
,
1462 struct mvneta_rx_queue
*rxq
)
1464 struct net_device
*dev
= pp
->dev
;
1469 /* Get number of received packets */
1470 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1472 if (rx_todo
> rx_done
)
1477 /* Fairness NAPI loop */
1478 while (rx_done
< rx_todo
) {
1479 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
1480 struct sk_buff
*skb
;
1481 unsigned char *data
;
1486 rx_status
= rx_desc
->status
;
1487 rx_bytes
= rx_desc
->data_size
- (ETH_FCS_LEN
+ MVNETA_MH_SIZE
);
1488 data
= (unsigned char *)rx_desc
->buf_cookie
;
1490 if (!mvneta_rxq_desc_is_first_last(rx_status
) ||
1491 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
1493 dev
->stats
.rx_errors
++;
1494 mvneta_rx_error(pp
, rx_desc
);
1495 /* leave the descriptor untouched */
1499 if (rx_bytes
<= rx_copybreak
) {
1500 /* better copy a small frame and not unmap the DMA region */
1501 skb
= netdev_alloc_skb_ip_align(dev
, rx_bytes
);
1503 goto err_drop_frame
;
1505 dma_sync_single_range_for_cpu(dev
->dev
.parent
,
1506 rx_desc
->buf_phys_addr
,
1507 MVNETA_MH_SIZE
+ NET_SKB_PAD
,
1510 memcpy(skb_put(skb
, rx_bytes
),
1511 data
+ MVNETA_MH_SIZE
+ NET_SKB_PAD
,
1514 skb
->protocol
= eth_type_trans(skb
, dev
);
1515 mvneta_rx_csum(pp
, rx_status
, skb
);
1516 napi_gro_receive(&pp
->napi
, skb
);
1519 rcvd_bytes
+= rx_bytes
;
1521 /* leave the descriptor and buffer untouched */
1525 /* Refill processing */
1526 err
= mvneta_rx_refill(pp
, rx_desc
);
1528 netdev_err(dev
, "Linux processing - Can't refill\n");
1530 goto err_drop_frame
;
1533 skb
= build_skb(data
, pp
->frag_size
> PAGE_SIZE
? 0 : pp
->frag_size
);
1535 goto err_drop_frame
;
1537 dma_unmap_single(dev
->dev
.parent
, rx_desc
->buf_phys_addr
,
1538 MVNETA_RX_BUF_SIZE(pp
->pkt_size
), DMA_FROM_DEVICE
);
1541 rcvd_bytes
+= rx_bytes
;
1543 /* Linux processing */
1544 skb_reserve(skb
, MVNETA_MH_SIZE
+ NET_SKB_PAD
);
1545 skb_put(skb
, rx_bytes
);
1547 skb
->protocol
= eth_type_trans(skb
, dev
);
1549 mvneta_rx_csum(pp
, rx_status
, skb
);
1551 napi_gro_receive(&pp
->napi
, skb
);
1555 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
1557 u64_stats_update_begin(&stats
->syncp
);
1558 stats
->rx_packets
+= rcvd_pkts
;
1559 stats
->rx_bytes
+= rcvd_bytes
;
1560 u64_stats_update_end(&stats
->syncp
);
1563 /* Update rxq management counters */
1564 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1570 mvneta_tso_put_hdr(struct sk_buff
*skb
,
1571 struct mvneta_port
*pp
, struct mvneta_tx_queue
*txq
)
1573 struct mvneta_tx_desc
*tx_desc
;
1574 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
1576 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
1577 tx_desc
= mvneta_txq_next_desc_get(txq
);
1578 tx_desc
->data_size
= hdr_len
;
1579 tx_desc
->command
= mvneta_skb_tx_csum(pp
, skb
);
1580 tx_desc
->command
|= MVNETA_TXD_F_DESC
;
1581 tx_desc
->buf_phys_addr
= txq
->tso_hdrs_phys
+
1582 txq
->txq_put_index
* TSO_HEADER_SIZE
;
1583 mvneta_txq_inc_put(txq
);
1587 mvneta_tso_put_data(struct net_device
*dev
, struct mvneta_tx_queue
*txq
,
1588 struct sk_buff
*skb
, char *data
, int size
,
1589 bool last_tcp
, bool is_last
)
1591 struct mvneta_tx_desc
*tx_desc
;
1593 tx_desc
= mvneta_txq_next_desc_get(txq
);
1594 tx_desc
->data_size
= size
;
1595 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, data
,
1596 size
, DMA_TO_DEVICE
);
1597 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
1598 tx_desc
->buf_phys_addr
))) {
1599 mvneta_txq_desc_put(txq
);
1603 tx_desc
->command
= 0;
1604 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
1607 /* last descriptor in the TCP packet */
1608 tx_desc
->command
= MVNETA_TXD_L_DESC
;
1610 /* last descriptor in SKB */
1612 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
1614 mvneta_txq_inc_put(txq
);
1618 static int mvneta_tx_tso(struct sk_buff
*skb
, struct net_device
*dev
,
1619 struct mvneta_tx_queue
*txq
)
1621 int total_len
, data_left
;
1623 struct mvneta_port
*pp
= netdev_priv(dev
);
1625 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
1628 /* Count needed descriptors */
1629 if ((txq
->count
+ tso_count_descs(skb
)) >= txq
->size
)
1632 if (skb_headlen(skb
) < (skb_transport_offset(skb
) + tcp_hdrlen(skb
))) {
1633 pr_info("*** Is this even possible???!?!?\n");
1637 /* Initialize the TSO handler, and prepare the first payload */
1638 tso_start(skb
, &tso
);
1640 total_len
= skb
->len
- hdr_len
;
1641 while (total_len
> 0) {
1644 data_left
= min_t(int, skb_shinfo(skb
)->gso_size
, total_len
);
1645 total_len
-= data_left
;
1648 /* prepare packet headers: MAC + IP + TCP */
1649 hdr
= txq
->tso_hdrs
+ txq
->txq_put_index
* TSO_HEADER_SIZE
;
1650 tso_build_hdr(skb
, hdr
, &tso
, data_left
, total_len
== 0);
1652 mvneta_tso_put_hdr(skb
, pp
, txq
);
1654 while (data_left
> 0) {
1658 size
= min_t(int, tso
.size
, data_left
);
1660 if (mvneta_tso_put_data(dev
, txq
, skb
,
1667 tso_build_data(skb
, &tso
, size
);
1674 /* Release all used data descriptors; header descriptors must not
1677 for (i
= desc_count
- 1; i
>= 0; i
--) {
1678 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+ i
;
1679 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
))
1680 dma_unmap_single(pp
->dev
->dev
.parent
,
1681 tx_desc
->buf_phys_addr
,
1684 mvneta_txq_desc_put(txq
);
1689 /* Handle tx fragmentation processing */
1690 static int mvneta_tx_frag_process(struct mvneta_port
*pp
, struct sk_buff
*skb
,
1691 struct mvneta_tx_queue
*txq
)
1693 struct mvneta_tx_desc
*tx_desc
;
1694 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1696 for (i
= 0; i
< nr_frags
; i
++) {
1697 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1698 void *addr
= page_address(frag
->page
.p
) + frag
->page_offset
;
1700 tx_desc
= mvneta_txq_next_desc_get(txq
);
1701 tx_desc
->data_size
= frag
->size
;
1703 tx_desc
->buf_phys_addr
=
1704 dma_map_single(pp
->dev
->dev
.parent
, addr
,
1705 tx_desc
->data_size
, DMA_TO_DEVICE
);
1707 if (dma_mapping_error(pp
->dev
->dev
.parent
,
1708 tx_desc
->buf_phys_addr
)) {
1709 mvneta_txq_desc_put(txq
);
1713 if (i
== nr_frags
- 1) {
1714 /* Last descriptor */
1715 tx_desc
->command
= MVNETA_TXD_L_DESC
| MVNETA_TXD_Z_PAD
;
1716 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
1718 /* Descriptor in the middle: Not First, Not Last */
1719 tx_desc
->command
= 0;
1720 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
1722 mvneta_txq_inc_put(txq
);
1728 /* Release all descriptors that were used to map fragments of
1729 * this packet, as well as the corresponding DMA mappings
1731 for (i
= i
- 1; i
>= 0; i
--) {
1732 tx_desc
= txq
->descs
+ i
;
1733 dma_unmap_single(pp
->dev
->dev
.parent
,
1734 tx_desc
->buf_phys_addr
,
1737 mvneta_txq_desc_put(txq
);
1743 /* Main tx processing */
1744 static int mvneta_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1746 struct mvneta_port
*pp
= netdev_priv(dev
);
1747 u16 txq_id
= skb_get_queue_mapping(skb
);
1748 struct mvneta_tx_queue
*txq
= &pp
->txqs
[txq_id
];
1749 struct mvneta_tx_desc
*tx_desc
;
1754 if (!netif_running(dev
))
1757 if (skb_is_gso(skb
)) {
1758 frags
= mvneta_tx_tso(skb
, dev
, txq
);
1762 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
1764 /* Get a descriptor for the first part of the packet */
1765 tx_desc
= mvneta_txq_next_desc_get(txq
);
1767 tx_cmd
= mvneta_skb_tx_csum(pp
, skb
);
1769 tx_desc
->data_size
= skb_headlen(skb
);
1771 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
1774 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
1775 tx_desc
->buf_phys_addr
))) {
1776 mvneta_txq_desc_put(txq
);
1782 /* First and Last descriptor */
1783 tx_cmd
|= MVNETA_TXD_FLZ_DESC
;
1784 tx_desc
->command
= tx_cmd
;
1785 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
1786 mvneta_txq_inc_put(txq
);
1788 /* First but not Last */
1789 tx_cmd
|= MVNETA_TXD_F_DESC
;
1790 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
1791 mvneta_txq_inc_put(txq
);
1792 tx_desc
->command
= tx_cmd
;
1793 /* Continue with other skb fragments */
1794 if (mvneta_tx_frag_process(pp
, skb
, txq
)) {
1795 dma_unmap_single(dev
->dev
.parent
,
1796 tx_desc
->buf_phys_addr
,
1799 mvneta_txq_desc_put(txq
);
1807 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
1808 struct netdev_queue
*nq
= netdev_get_tx_queue(dev
, txq_id
);
1810 txq
->count
+= frags
;
1811 mvneta_txq_pend_desc_add(pp
, txq
, frags
);
1813 if (txq
->count
>= txq
->tx_stop_threshold
)
1814 netif_tx_stop_queue(nq
);
1816 u64_stats_update_begin(&stats
->syncp
);
1817 stats
->tx_packets
++;
1818 stats
->tx_bytes
+= len
;
1819 u64_stats_update_end(&stats
->syncp
);
1821 dev
->stats
.tx_dropped
++;
1822 dev_kfree_skb_any(skb
);
1825 return NETDEV_TX_OK
;
1829 /* Free tx resources, when resetting a port */
1830 static void mvneta_txq_done_force(struct mvneta_port
*pp
,
1831 struct mvneta_tx_queue
*txq
)
1834 int tx_done
= txq
->count
;
1836 mvneta_txq_bufs_free(pp
, txq
, tx_done
);
1840 txq
->txq_put_index
= 0;
1841 txq
->txq_get_index
= 0;
1844 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1845 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1847 static void mvneta_tx_done_gbe(struct mvneta_port
*pp
, u32 cause_tx_done
)
1849 struct mvneta_tx_queue
*txq
;
1850 struct netdev_queue
*nq
;
1852 while (cause_tx_done
) {
1853 txq
= mvneta_tx_done_policy(pp
, cause_tx_done
);
1855 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1856 __netif_tx_lock(nq
, smp_processor_id());
1859 mvneta_txq_done(pp
, txq
);
1861 __netif_tx_unlock(nq
);
1862 cause_tx_done
&= ~((1 << txq
->id
));
1866 /* Compute crc8 of the specified address, using a unique algorithm ,
1867 * according to hw spec, different than generic crc8 algorithm
1869 static int mvneta_addr_crc(unsigned char *addr
)
1874 for (i
= 0; i
< ETH_ALEN
; i
++) {
1877 crc
= (crc
^ addr
[i
]) << 8;
1878 for (j
= 7; j
>= 0; j
--) {
1879 if (crc
& (0x100 << j
))
1887 /* This method controls the net device special MAC multicast support.
1888 * The Special Multicast Table for MAC addresses supports MAC of the form
1889 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1890 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1891 * Table entries in the DA-Filter table. This method set the Special
1892 * Multicast Table appropriate entry.
1894 static void mvneta_set_special_mcast_addr(struct mvneta_port
*pp
,
1895 unsigned char last_byte
,
1898 unsigned int smc_table_reg
;
1899 unsigned int tbl_offset
;
1900 unsigned int reg_offset
;
1902 /* Register offset from SMC table base */
1903 tbl_offset
= (last_byte
/ 4);
1904 /* Entry offset within the above reg */
1905 reg_offset
= last_byte
% 4;
1907 smc_table_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_SPEC_MCAST
1911 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
1913 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
1914 smc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1917 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ tbl_offset
* 4,
1921 /* This method controls the network device Other MAC multicast support.
1922 * The Other Multicast Table is used for multicast of another type.
1923 * A CRC-8 is used as an index to the Other Multicast Table entries
1924 * in the DA-Filter table.
1925 * The method gets the CRC-8 value from the calling routine and
1926 * sets the Other Multicast Table appropriate entry according to the
1929 static void mvneta_set_other_mcast_addr(struct mvneta_port
*pp
,
1933 unsigned int omc_table_reg
;
1934 unsigned int tbl_offset
;
1935 unsigned int reg_offset
;
1937 tbl_offset
= (crc8
/ 4) * 4; /* Register offset from OMC table base */
1938 reg_offset
= crc8
% 4; /* Entry offset within the above reg */
1940 omc_table_reg
= mvreg_read(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
);
1943 /* Clear accepts frame bit at specified Other DA table entry */
1944 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
1946 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
1947 omc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1950 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
, omc_table_reg
);
1953 /* The network device supports multicast using two tables:
1954 * 1) Special Multicast Table for MAC addresses of the form
1955 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1956 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1957 * Table entries in the DA-Filter table.
1958 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1959 * is used as an index to the Other Multicast Table entries in the
1962 static int mvneta_mcast_addr_set(struct mvneta_port
*pp
, unsigned char *p_addr
,
1965 unsigned char crc_result
= 0;
1967 if (memcmp(p_addr
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1968 mvneta_set_special_mcast_addr(pp
, p_addr
[5], queue
);
1972 crc_result
= mvneta_addr_crc(p_addr
);
1974 if (pp
->mcast_count
[crc_result
] == 0) {
1975 netdev_info(pp
->dev
, "No valid Mcast for crc8=0x%02x\n",
1980 pp
->mcast_count
[crc_result
]--;
1981 if (pp
->mcast_count
[crc_result
] != 0) {
1982 netdev_info(pp
->dev
,
1983 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1984 pp
->mcast_count
[crc_result
], crc_result
);
1988 pp
->mcast_count
[crc_result
]++;
1990 mvneta_set_other_mcast_addr(pp
, crc_result
, queue
);
1995 /* Configure Fitering mode of Ethernet port */
1996 static void mvneta_rx_unicast_promisc_set(struct mvneta_port
*pp
,
1999 u32 port_cfg_reg
, val
;
2001 port_cfg_reg
= mvreg_read(pp
, MVNETA_PORT_CONFIG
);
2003 val
= mvreg_read(pp
, MVNETA_TYPE_PRIO
);
2005 /* Set / Clear UPM bit in port configuration register */
2007 /* Accept all Unicast addresses */
2008 port_cfg_reg
|= MVNETA_UNI_PROMISC_MODE
;
2009 val
|= MVNETA_FORCE_UNI
;
2010 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, 0xffff);
2011 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, 0xffffffff);
2013 /* Reject all Unicast addresses */
2014 port_cfg_reg
&= ~MVNETA_UNI_PROMISC_MODE
;
2015 val
&= ~MVNETA_FORCE_UNI
;
2018 mvreg_write(pp
, MVNETA_PORT_CONFIG
, port_cfg_reg
);
2019 mvreg_write(pp
, MVNETA_TYPE_PRIO
, val
);
2022 /* register unicast and multicast addresses */
2023 static void mvneta_set_rx_mode(struct net_device
*dev
)
2025 struct mvneta_port
*pp
= netdev_priv(dev
);
2026 struct netdev_hw_addr
*ha
;
2028 if (dev
->flags
& IFF_PROMISC
) {
2029 /* Accept all: Multicast + Unicast */
2030 mvneta_rx_unicast_promisc_set(pp
, 1);
2031 mvneta_set_ucast_table(pp
, rxq_def
);
2032 mvneta_set_special_mcast_table(pp
, rxq_def
);
2033 mvneta_set_other_mcast_table(pp
, rxq_def
);
2035 /* Accept single Unicast */
2036 mvneta_rx_unicast_promisc_set(pp
, 0);
2037 mvneta_set_ucast_table(pp
, -1);
2038 mvneta_mac_addr_set(pp
, dev
->dev_addr
, rxq_def
);
2040 if (dev
->flags
& IFF_ALLMULTI
) {
2041 /* Accept all multicast */
2042 mvneta_set_special_mcast_table(pp
, rxq_def
);
2043 mvneta_set_other_mcast_table(pp
, rxq_def
);
2045 /* Accept only initialized multicast */
2046 mvneta_set_special_mcast_table(pp
, -1);
2047 mvneta_set_other_mcast_table(pp
, -1);
2049 if (!netdev_mc_empty(dev
)) {
2050 netdev_for_each_mc_addr(ha
, dev
) {
2051 mvneta_mcast_addr_set(pp
, ha
->addr
,
2059 /* Interrupt handling - the callback for request_irq() */
2060 static irqreturn_t
mvneta_isr(int irq
, void *dev_id
)
2062 struct mvneta_port
*pp
= (struct mvneta_port
*)dev_id
;
2064 /* Mask all interrupts */
2065 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
2067 napi_schedule(&pp
->napi
);
2072 static int mvneta_fixed_link_update(struct mvneta_port
*pp
,
2073 struct phy_device
*phy
)
2075 struct fixed_phy_status status
;
2076 struct fixed_phy_status changed
= {};
2077 u32 gmac_stat
= mvreg_read(pp
, MVNETA_GMAC_STATUS
);
2079 status
.link
= !!(gmac_stat
& MVNETA_GMAC_LINK_UP
);
2080 if (gmac_stat
& MVNETA_GMAC_SPEED_1000
)
2081 status
.speed
= SPEED_1000
;
2082 else if (gmac_stat
& MVNETA_GMAC_SPEED_100
)
2083 status
.speed
= SPEED_100
;
2085 status
.speed
= SPEED_10
;
2086 status
.duplex
= !!(gmac_stat
& MVNETA_GMAC_FULL_DUPLEX
);
2090 fixed_phy_update_state(phy
, &status
, &changed
);
2095 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2096 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2097 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2098 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2099 * Each CPU has its own causeRxTx register
2101 static int mvneta_poll(struct napi_struct
*napi
, int budget
)
2105 unsigned long flags
;
2106 struct mvneta_port
*pp
= netdev_priv(napi
->dev
);
2108 if (!netif_running(pp
->dev
)) {
2109 napi_complete(napi
);
2113 /* Read cause register */
2114 cause_rx_tx
= mvreg_read(pp
, MVNETA_INTR_NEW_CAUSE
);
2115 if (cause_rx_tx
& MVNETA_MISCINTR_INTR_MASK
) {
2116 u32 cause_misc
= mvreg_read(pp
, MVNETA_INTR_MISC_CAUSE
);
2118 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
2119 if (pp
->use_inband_status
&& (cause_misc
&
2120 (MVNETA_CAUSE_PHY_STATUS_CHANGE
|
2121 MVNETA_CAUSE_LINK_CHANGE
|
2122 MVNETA_CAUSE_PSC_SYNC_CHANGE
))) {
2123 mvneta_fixed_link_update(pp
, pp
->phy_dev
);
2127 /* Release Tx descriptors */
2128 if (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
) {
2129 mvneta_tx_done_gbe(pp
, (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
));
2130 cause_rx_tx
&= ~MVNETA_TX_INTR_MASK_ALL
;
2133 /* For the case where the last mvneta_poll did not process all
2136 cause_rx_tx
|= pp
->cause_rx_tx
;
2137 if (rxq_number
> 1) {
2138 while ((cause_rx_tx
& MVNETA_RX_INTR_MASK_ALL
) && (budget
> 0)) {
2140 struct mvneta_rx_queue
*rxq
;
2141 /* get rx queue number from cause_rx_tx */
2142 rxq
= mvneta_rx_policy(pp
, cause_rx_tx
);
2146 /* process the packet in that rx queue */
2147 count
= mvneta_rx(pp
, budget
, rxq
);
2151 /* set off the rx bit of the
2152 * corresponding bit in the cause rx
2153 * tx register, so that next iteration
2154 * will find the next rx queue where
2155 * packets are received on
2157 cause_rx_tx
&= ~((1 << rxq
->id
) << 8);
2161 rx_done
= mvneta_rx(pp
, budget
, &pp
->rxqs
[rxq_def
]);
2167 napi_complete(napi
);
2168 local_irq_save(flags
);
2169 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
2170 MVNETA_RX_INTR_MASK(rxq_number
) |
2171 MVNETA_TX_INTR_MASK(txq_number
) |
2172 MVNETA_MISCINTR_INTR_MASK
);
2173 local_irq_restore(flags
);
2176 pp
->cause_rx_tx
= cause_rx_tx
;
2180 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2181 static int mvneta_rxq_fill(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
2186 for (i
= 0; i
< num
; i
++) {
2187 memset(rxq
->descs
+ i
, 0, sizeof(struct mvneta_rx_desc
));
2188 if (mvneta_rx_refill(pp
, rxq
->descs
+ i
) != 0) {
2189 netdev_err(pp
->dev
, "%s:rxq %d, %d of %d buffs filled\n",
2190 __func__
, rxq
->id
, i
, num
);
2195 /* Add this number of RX descriptors as non occupied (ready to
2198 mvneta_rxq_non_occup_desc_add(pp
, rxq
, i
);
2203 /* Free all packets pending transmit from all TXQs and reset TX port */
2204 static void mvneta_tx_reset(struct mvneta_port
*pp
)
2208 /* free the skb's in the tx ring */
2209 for (queue
= 0; queue
< txq_number
; queue
++)
2210 mvneta_txq_done_force(pp
, &pp
->txqs
[queue
]);
2212 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
2213 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
2216 static void mvneta_rx_reset(struct mvneta_port
*pp
)
2218 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
2219 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
2222 /* Rx/Tx queue initialization/cleanup methods */
2224 /* Create a specified RX queue */
2225 static int mvneta_rxq_init(struct mvneta_port
*pp
,
2226 struct mvneta_rx_queue
*rxq
)
2229 rxq
->size
= pp
->rx_ring_size
;
2231 /* Allocate memory for RX descriptors */
2232 rxq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2233 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2234 &rxq
->descs_phys
, GFP_KERNEL
);
2235 if (rxq
->descs
== NULL
)
2238 BUG_ON(rxq
->descs
!=
2239 PTR_ALIGN(rxq
->descs
, MVNETA_CPU_D_CACHE_LINE_SIZE
));
2241 rxq
->last_desc
= rxq
->size
- 1;
2243 /* Set Rx descriptors queue starting address */
2244 mvreg_write(pp
, MVNETA_RXQ_BASE_ADDR_REG(rxq
->id
), rxq
->descs_phys
);
2245 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), rxq
->size
);
2248 mvneta_rxq_offset_set(pp
, rxq
, NET_SKB_PAD
);
2250 /* Set coalescing pkts and time */
2251 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
2252 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
2254 /* Fill RXQ with buffers from RX pool */
2255 mvneta_rxq_buf_size_set(pp
, rxq
, MVNETA_RX_BUF_SIZE(pp
->pkt_size
));
2256 mvneta_rxq_bm_disable(pp
, rxq
);
2257 mvneta_rxq_fill(pp
, rxq
, rxq
->size
);
2262 /* Cleanup Rx queue */
2263 static void mvneta_rxq_deinit(struct mvneta_port
*pp
,
2264 struct mvneta_rx_queue
*rxq
)
2266 mvneta_rxq_drop_pkts(pp
, rxq
);
2269 dma_free_coherent(pp
->dev
->dev
.parent
,
2270 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2276 rxq
->next_desc_to_proc
= 0;
2277 rxq
->descs_phys
= 0;
2280 /* Create and initialize a tx queue */
2281 static int mvneta_txq_init(struct mvneta_port
*pp
,
2282 struct mvneta_tx_queue
*txq
)
2284 txq
->size
= pp
->tx_ring_size
;
2286 /* A queue must always have room for at least one skb.
2287 * Therefore, stop the queue when the free entries reaches
2288 * the maximum number of descriptors per skb.
2290 txq
->tx_stop_threshold
= txq
->size
- MVNETA_MAX_SKB_DESCS
;
2291 txq
->tx_wake_threshold
= txq
->tx_stop_threshold
/ 2;
2294 /* Allocate memory for TX descriptors */
2295 txq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2296 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2297 &txq
->descs_phys
, GFP_KERNEL
);
2298 if (txq
->descs
== NULL
)
2301 /* Make sure descriptor address is cache line size aligned */
2302 BUG_ON(txq
->descs
!=
2303 PTR_ALIGN(txq
->descs
, MVNETA_CPU_D_CACHE_LINE_SIZE
));
2305 txq
->last_desc
= txq
->size
- 1;
2307 /* Set maximum bandwidth for enabled TXQs */
2308 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0x03ffffff);
2309 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0x3fffffff);
2311 /* Set Tx descriptors queue starting address */
2312 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), txq
->descs_phys
);
2313 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), txq
->size
);
2315 txq
->tx_skb
= kmalloc(txq
->size
* sizeof(*txq
->tx_skb
), GFP_KERNEL
);
2316 if (txq
->tx_skb
== NULL
) {
2317 dma_free_coherent(pp
->dev
->dev
.parent
,
2318 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2319 txq
->descs
, txq
->descs_phys
);
2323 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2324 txq
->tso_hdrs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2325 txq
->size
* TSO_HEADER_SIZE
,
2326 &txq
->tso_hdrs_phys
, GFP_KERNEL
);
2327 if (txq
->tso_hdrs
== NULL
) {
2329 dma_free_coherent(pp
->dev
->dev
.parent
,
2330 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2331 txq
->descs
, txq
->descs_phys
);
2334 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
2339 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2340 static void mvneta_txq_deinit(struct mvneta_port
*pp
,
2341 struct mvneta_tx_queue
*txq
)
2346 dma_free_coherent(pp
->dev
->dev
.parent
,
2347 txq
->size
* TSO_HEADER_SIZE
,
2348 txq
->tso_hdrs
, txq
->tso_hdrs_phys
);
2350 dma_free_coherent(pp
->dev
->dev
.parent
,
2351 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2352 txq
->descs
, txq
->descs_phys
);
2356 txq
->next_desc_to_proc
= 0;
2357 txq
->descs_phys
= 0;
2359 /* Set minimum bandwidth for disabled TXQs */
2360 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0);
2361 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0);
2363 /* Set Tx descriptors queue starting address and size */
2364 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), 0);
2365 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), 0);
2368 /* Cleanup all Tx queues */
2369 static void mvneta_cleanup_txqs(struct mvneta_port
*pp
)
2373 for (queue
= 0; queue
< txq_number
; queue
++)
2374 mvneta_txq_deinit(pp
, &pp
->txqs
[queue
]);
2377 /* Cleanup all Rx queues */
2378 static void mvneta_cleanup_rxqs(struct mvneta_port
*pp
)
2382 for (queue
= 0; queue
< rxq_number
; queue
++)
2383 mvneta_rxq_deinit(pp
, &pp
->rxqs
[queue
]);
2387 /* Init all Rx queues */
2388 static int mvneta_setup_rxqs(struct mvneta_port
*pp
)
2392 for (queue
= 0; queue
< rxq_number
; queue
++) {
2393 int err
= mvneta_rxq_init(pp
, &pp
->rxqs
[queue
]);
2395 netdev_err(pp
->dev
, "%s: can't create rxq=%d\n",
2397 mvneta_cleanup_rxqs(pp
);
2405 /* Init all tx queues */
2406 static int mvneta_setup_txqs(struct mvneta_port
*pp
)
2410 for (queue
= 0; queue
< txq_number
; queue
++) {
2411 int err
= mvneta_txq_init(pp
, &pp
->txqs
[queue
]);
2413 netdev_err(pp
->dev
, "%s: can't create txq=%d\n",
2415 mvneta_cleanup_txqs(pp
);
2423 static void mvneta_start_dev(struct mvneta_port
*pp
)
2425 mvneta_max_rx_size_set(pp
, pp
->pkt_size
);
2426 mvneta_txq_max_tx_size_set(pp
, pp
->pkt_size
);
2428 /* start the Rx/Tx activity */
2429 mvneta_port_enable(pp
);
2431 /* Enable polling on the port */
2432 napi_enable(&pp
->napi
);
2434 /* Unmask interrupts */
2435 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
2436 MVNETA_RX_INTR_MASK(rxq_number
) |
2437 MVNETA_TX_INTR_MASK(txq_number
) |
2438 MVNETA_MISCINTR_INTR_MASK
);
2439 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
2440 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
2441 MVNETA_CAUSE_LINK_CHANGE
|
2442 MVNETA_CAUSE_PSC_SYNC_CHANGE
);
2444 phy_start(pp
->phy_dev
);
2445 netif_tx_start_all_queues(pp
->dev
);
2448 static void mvneta_stop_dev(struct mvneta_port
*pp
)
2450 phy_stop(pp
->phy_dev
);
2452 napi_disable(&pp
->napi
);
2454 netif_carrier_off(pp
->dev
);
2456 mvneta_port_down(pp
);
2457 netif_tx_stop_all_queues(pp
->dev
);
2459 /* Stop the port activity */
2460 mvneta_port_disable(pp
);
2462 /* Clear all ethernet port interrupts */
2463 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
2464 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
2466 /* Mask all ethernet port interrupts */
2467 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
2468 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
2469 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
2471 mvneta_tx_reset(pp
);
2472 mvneta_rx_reset(pp
);
2475 /* Return positive if MTU is valid */
2476 static int mvneta_check_mtu_valid(struct net_device
*dev
, int mtu
)
2479 netdev_err(dev
, "cannot change mtu to less than 68\n");
2483 /* 9676 == 9700 - 20 and rounding to 8 */
2485 netdev_info(dev
, "Illegal MTU value %d, round to 9676\n", mtu
);
2489 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu
), 8)) {
2490 netdev_info(dev
, "Illegal MTU value %d, rounding to %d\n",
2491 mtu
, ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8));
2492 mtu
= ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8);
2498 /* Change the device mtu */
2499 static int mvneta_change_mtu(struct net_device
*dev
, int mtu
)
2501 struct mvneta_port
*pp
= netdev_priv(dev
);
2504 mtu
= mvneta_check_mtu_valid(dev
, mtu
);
2510 if (!netif_running(dev
)) {
2511 netdev_update_features(dev
);
2515 /* The interface is running, so we have to force a
2516 * reallocation of the queues
2518 mvneta_stop_dev(pp
);
2520 mvneta_cleanup_txqs(pp
);
2521 mvneta_cleanup_rxqs(pp
);
2523 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(dev
->mtu
);
2524 pp
->frag_size
= SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp
->pkt_size
)) +
2525 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2527 ret
= mvneta_setup_rxqs(pp
);
2529 netdev_err(dev
, "unable to setup rxqs after MTU change\n");
2533 ret
= mvneta_setup_txqs(pp
);
2535 netdev_err(dev
, "unable to setup txqs after MTU change\n");
2539 mvneta_start_dev(pp
);
2542 netdev_update_features(dev
);
2547 static netdev_features_t
mvneta_fix_features(struct net_device
*dev
,
2548 netdev_features_t features
)
2550 struct mvneta_port
*pp
= netdev_priv(dev
);
2552 if (pp
->tx_csum_limit
&& dev
->mtu
> pp
->tx_csum_limit
) {
2553 features
&= ~(NETIF_F_IP_CSUM
| NETIF_F_TSO
);
2555 "Disable IP checksum for MTU greater than %dB\n",
2562 /* Get mac address */
2563 static void mvneta_get_mac_addr(struct mvneta_port
*pp
, unsigned char *addr
)
2565 u32 mac_addr_l
, mac_addr_h
;
2567 mac_addr_l
= mvreg_read(pp
, MVNETA_MAC_ADDR_LOW
);
2568 mac_addr_h
= mvreg_read(pp
, MVNETA_MAC_ADDR_HIGH
);
2569 addr
[0] = (mac_addr_h
>> 24) & 0xFF;
2570 addr
[1] = (mac_addr_h
>> 16) & 0xFF;
2571 addr
[2] = (mac_addr_h
>> 8) & 0xFF;
2572 addr
[3] = mac_addr_h
& 0xFF;
2573 addr
[4] = (mac_addr_l
>> 8) & 0xFF;
2574 addr
[5] = mac_addr_l
& 0xFF;
2577 /* Handle setting mac address */
2578 static int mvneta_set_mac_addr(struct net_device
*dev
, void *addr
)
2580 struct mvneta_port
*pp
= netdev_priv(dev
);
2581 struct sockaddr
*sockaddr
= addr
;
2584 ret
= eth_prepare_mac_addr_change(dev
, addr
);
2587 /* Remove previous address table entry */
2588 mvneta_mac_addr_set(pp
, dev
->dev_addr
, -1);
2590 /* Set new addr in hw */
2591 mvneta_mac_addr_set(pp
, sockaddr
->sa_data
, rxq_def
);
2593 eth_commit_mac_addr_change(dev
, addr
);
2597 static void mvneta_adjust_link(struct net_device
*ndev
)
2599 struct mvneta_port
*pp
= netdev_priv(ndev
);
2600 struct phy_device
*phydev
= pp
->phy_dev
;
2601 int status_change
= 0;
2604 if ((pp
->speed
!= phydev
->speed
) ||
2605 (pp
->duplex
!= phydev
->duplex
)) {
2608 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
2609 val
&= ~(MVNETA_GMAC_CONFIG_MII_SPEED
|
2610 MVNETA_GMAC_CONFIG_GMII_SPEED
|
2611 MVNETA_GMAC_CONFIG_FULL_DUPLEX
);
2614 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
2616 if (phydev
->speed
== SPEED_1000
)
2617 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
2618 else if (phydev
->speed
== SPEED_100
)
2619 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
2621 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
2623 pp
->duplex
= phydev
->duplex
;
2624 pp
->speed
= phydev
->speed
;
2628 if (phydev
->link
!= pp
->link
) {
2629 if (!phydev
->link
) {
2634 pp
->link
= phydev
->link
;
2638 if (status_change
) {
2640 if (!pp
->use_inband_status
) {
2641 u32 val
= mvreg_read(pp
,
2642 MVNETA_GMAC_AUTONEG_CONFIG
);
2643 val
&= ~MVNETA_GMAC_FORCE_LINK_DOWN
;
2644 val
|= MVNETA_GMAC_FORCE_LINK_PASS
;
2645 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
2650 if (!pp
->use_inband_status
) {
2651 u32 val
= mvreg_read(pp
,
2652 MVNETA_GMAC_AUTONEG_CONFIG
);
2653 val
&= ~MVNETA_GMAC_FORCE_LINK_PASS
;
2654 val
|= MVNETA_GMAC_FORCE_LINK_DOWN
;
2655 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
2658 mvneta_port_down(pp
);
2660 phy_print_status(phydev
);
2664 static int mvneta_mdio_probe(struct mvneta_port
*pp
)
2666 struct phy_device
*phy_dev
;
2668 phy_dev
= of_phy_connect(pp
->dev
, pp
->phy_node
, mvneta_adjust_link
, 0,
2671 netdev_err(pp
->dev
, "could not find the PHY\n");
2675 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
2676 phy_dev
->advertising
= phy_dev
->supported
;
2678 pp
->phy_dev
= phy_dev
;
2686 static void mvneta_mdio_remove(struct mvneta_port
*pp
)
2688 phy_disconnect(pp
->phy_dev
);
2692 static int mvneta_open(struct net_device
*dev
)
2694 struct mvneta_port
*pp
= netdev_priv(dev
);
2697 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
);
2698 pp
->frag_size
= SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp
->pkt_size
)) +
2699 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2701 ret
= mvneta_setup_rxqs(pp
);
2705 ret
= mvneta_setup_txqs(pp
);
2707 goto err_cleanup_rxqs
;
2709 /* Connect to port interrupt line */
2710 ret
= request_irq(pp
->dev
->irq
, mvneta_isr
, 0,
2711 MVNETA_DRIVER_NAME
, pp
);
2713 netdev_err(pp
->dev
, "cannot request irq %d\n", pp
->dev
->irq
);
2714 goto err_cleanup_txqs
;
2717 /* In default link is down */
2718 netif_carrier_off(pp
->dev
);
2720 ret
= mvneta_mdio_probe(pp
);
2722 netdev_err(dev
, "cannot probe MDIO bus\n");
2726 mvneta_start_dev(pp
);
2731 free_irq(pp
->dev
->irq
, pp
);
2733 mvneta_cleanup_txqs(pp
);
2735 mvneta_cleanup_rxqs(pp
);
2739 /* Stop the port, free port interrupt line */
2740 static int mvneta_stop(struct net_device
*dev
)
2742 struct mvneta_port
*pp
= netdev_priv(dev
);
2744 mvneta_stop_dev(pp
);
2745 mvneta_mdio_remove(pp
);
2746 free_irq(dev
->irq
, pp
);
2747 mvneta_cleanup_rxqs(pp
);
2748 mvneta_cleanup_txqs(pp
);
2753 static int mvneta_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2755 struct mvneta_port
*pp
= netdev_priv(dev
);
2760 return phy_mii_ioctl(pp
->phy_dev
, ifr
, cmd
);
2763 /* Ethtool methods */
2765 /* Get settings (phy address, speed) for ethtools */
2766 int mvneta_ethtool_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2768 struct mvneta_port
*pp
= netdev_priv(dev
);
2773 return phy_ethtool_gset(pp
->phy_dev
, cmd
);
2776 /* Set settings (phy address, speed) for ethtools */
2777 int mvneta_ethtool_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2779 struct mvneta_port
*pp
= netdev_priv(dev
);
2784 return phy_ethtool_sset(pp
->phy_dev
, cmd
);
2787 /* Set interrupt coalescing for ethtools */
2788 static int mvneta_ethtool_set_coalesce(struct net_device
*dev
,
2789 struct ethtool_coalesce
*c
)
2791 struct mvneta_port
*pp
= netdev_priv(dev
);
2794 for (queue
= 0; queue
< rxq_number
; queue
++) {
2795 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
2796 rxq
->time_coal
= c
->rx_coalesce_usecs
;
2797 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
2798 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
2799 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
2802 for (queue
= 0; queue
< txq_number
; queue
++) {
2803 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
2804 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
2805 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
2811 /* get coalescing for ethtools */
2812 static int mvneta_ethtool_get_coalesce(struct net_device
*dev
,
2813 struct ethtool_coalesce
*c
)
2815 struct mvneta_port
*pp
= netdev_priv(dev
);
2817 c
->rx_coalesce_usecs
= pp
->rxqs
[0].time_coal
;
2818 c
->rx_max_coalesced_frames
= pp
->rxqs
[0].pkts_coal
;
2820 c
->tx_max_coalesced_frames
= pp
->txqs
[0].done_pkts_coal
;
2825 static void mvneta_ethtool_get_drvinfo(struct net_device
*dev
,
2826 struct ethtool_drvinfo
*drvinfo
)
2828 strlcpy(drvinfo
->driver
, MVNETA_DRIVER_NAME
,
2829 sizeof(drvinfo
->driver
));
2830 strlcpy(drvinfo
->version
, MVNETA_DRIVER_VERSION
,
2831 sizeof(drvinfo
->version
));
2832 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
2833 sizeof(drvinfo
->bus_info
));
2837 static void mvneta_ethtool_get_ringparam(struct net_device
*netdev
,
2838 struct ethtool_ringparam
*ring
)
2840 struct mvneta_port
*pp
= netdev_priv(netdev
);
2842 ring
->rx_max_pending
= MVNETA_MAX_RXD
;
2843 ring
->tx_max_pending
= MVNETA_MAX_TXD
;
2844 ring
->rx_pending
= pp
->rx_ring_size
;
2845 ring
->tx_pending
= pp
->tx_ring_size
;
2848 static int mvneta_ethtool_set_ringparam(struct net_device
*dev
,
2849 struct ethtool_ringparam
*ring
)
2851 struct mvneta_port
*pp
= netdev_priv(dev
);
2853 if ((ring
->rx_pending
== 0) || (ring
->tx_pending
== 0))
2855 pp
->rx_ring_size
= ring
->rx_pending
< MVNETA_MAX_RXD
?
2856 ring
->rx_pending
: MVNETA_MAX_RXD
;
2858 pp
->tx_ring_size
= clamp_t(u16
, ring
->tx_pending
,
2859 MVNETA_MAX_SKB_DESCS
* 2, MVNETA_MAX_TXD
);
2860 if (pp
->tx_ring_size
!= ring
->tx_pending
)
2861 netdev_warn(dev
, "TX queue size set to %u (requested %u)\n",
2862 pp
->tx_ring_size
, ring
->tx_pending
);
2864 if (netif_running(dev
)) {
2866 if (mvneta_open(dev
)) {
2868 "error on opening device after ring param change\n");
2876 static const struct net_device_ops mvneta_netdev_ops
= {
2877 .ndo_open
= mvneta_open
,
2878 .ndo_stop
= mvneta_stop
,
2879 .ndo_start_xmit
= mvneta_tx
,
2880 .ndo_set_rx_mode
= mvneta_set_rx_mode
,
2881 .ndo_set_mac_address
= mvneta_set_mac_addr
,
2882 .ndo_change_mtu
= mvneta_change_mtu
,
2883 .ndo_fix_features
= mvneta_fix_features
,
2884 .ndo_get_stats64
= mvneta_get_stats64
,
2885 .ndo_do_ioctl
= mvneta_ioctl
,
2888 const struct ethtool_ops mvneta_eth_tool_ops
= {
2889 .get_link
= ethtool_op_get_link
,
2890 .get_settings
= mvneta_ethtool_get_settings
,
2891 .set_settings
= mvneta_ethtool_set_settings
,
2892 .set_coalesce
= mvneta_ethtool_set_coalesce
,
2893 .get_coalesce
= mvneta_ethtool_get_coalesce
,
2894 .get_drvinfo
= mvneta_ethtool_get_drvinfo
,
2895 .get_ringparam
= mvneta_ethtool_get_ringparam
,
2896 .set_ringparam
= mvneta_ethtool_set_ringparam
,
2900 static int mvneta_init(struct device
*dev
, struct mvneta_port
*pp
)
2905 mvneta_port_disable(pp
);
2907 /* Set port default values */
2908 mvneta_defaults_set(pp
);
2910 pp
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(struct mvneta_tx_queue
),
2915 /* Initialize TX descriptor rings */
2916 for (queue
= 0; queue
< txq_number
; queue
++) {
2917 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
2919 txq
->size
= pp
->tx_ring_size
;
2920 txq
->done_pkts_coal
= MVNETA_TXDONE_COAL_PKTS
;
2923 pp
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(struct mvneta_rx_queue
),
2928 /* Create Rx descriptor rings */
2929 for (queue
= 0; queue
< rxq_number
; queue
++) {
2930 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
2932 rxq
->size
= pp
->rx_ring_size
;
2933 rxq
->pkts_coal
= MVNETA_RX_COAL_PKTS
;
2934 rxq
->time_coal
= MVNETA_RX_COAL_USEC
;
2940 /* platform glue : initialize decoding windows */
2941 static void mvneta_conf_mbus_windows(struct mvneta_port
*pp
,
2942 const struct mbus_dram_target_info
*dram
)
2948 for (i
= 0; i
< 6; i
++) {
2949 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
2950 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
2953 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
2959 for (i
= 0; i
< dram
->num_cs
; i
++) {
2960 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2961 mvreg_write(pp
, MVNETA_WIN_BASE(i
), (cs
->base
& 0xffff0000) |
2962 (cs
->mbus_attr
<< 8) | dram
->mbus_dram_target_id
);
2964 mvreg_write(pp
, MVNETA_WIN_SIZE(i
),
2965 (cs
->size
- 1) & 0xffff0000);
2967 win_enable
&= ~(1 << i
);
2968 win_protect
|= 3 << (2 * i
);
2971 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
2974 /* Power up the port */
2975 static int mvneta_port_power_up(struct mvneta_port
*pp
, int phy_mode
)
2979 /* MAC Cause register should be cleared */
2980 mvreg_write(pp
, MVNETA_UNIT_INTR_CAUSE
, 0);
2982 ctrl
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
2984 /* Even though it might look weird, when we're configured in
2985 * SGMII or QSGMII mode, the RGMII bit needs to be set.
2988 case PHY_INTERFACE_MODE_QSGMII
:
2989 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_QSGMII_SERDES_PROTO
);
2990 ctrl
|= MVNETA_GMAC2_PCS_ENABLE
| MVNETA_GMAC2_PORT_RGMII
;
2992 case PHY_INTERFACE_MODE_SGMII
:
2993 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_SGMII_SERDES_PROTO
);
2994 ctrl
|= MVNETA_GMAC2_PCS_ENABLE
| MVNETA_GMAC2_PORT_RGMII
;
2996 case PHY_INTERFACE_MODE_RGMII
:
2997 case PHY_INTERFACE_MODE_RGMII_ID
:
2998 ctrl
|= MVNETA_GMAC2_PORT_RGMII
;
3004 if (pp
->use_inband_status
)
3005 ctrl
|= MVNETA_GMAC2_INBAND_AN_ENABLE
;
3007 /* Cancel Port Reset */
3008 ctrl
&= ~MVNETA_GMAC2_PORT_RESET
;
3009 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, ctrl
);
3011 while ((mvreg_read(pp
, MVNETA_GMAC_CTRL_2
) &
3012 MVNETA_GMAC2_PORT_RESET
) != 0)
3018 /* Device initialization routine */
3019 static int mvneta_probe(struct platform_device
*pdev
)
3021 const struct mbus_dram_target_info
*dram_target_info
;
3022 struct resource
*res
;
3023 struct device_node
*dn
= pdev
->dev
.of_node
;
3024 struct device_node
*phy_node
;
3025 struct mvneta_port
*pp
;
3026 struct net_device
*dev
;
3027 const char *dt_mac_addr
;
3028 char hw_mac_addr
[ETH_ALEN
];
3029 const char *mac_from
;
3030 const char *managed
;
3034 /* Our multiqueue support is not complete, so for now, only
3035 * allow the usage of the first RX queue
3038 dev_err(&pdev
->dev
, "Invalid rxq_def argument: %d\n", rxq_def
);
3042 dev
= alloc_etherdev_mqs(sizeof(struct mvneta_port
), txq_number
, rxq_number
);
3046 dev
->irq
= irq_of_parse_and_map(dn
, 0);
3047 if (dev
->irq
== 0) {
3049 goto err_free_netdev
;
3052 phy_node
= of_parse_phandle(dn
, "phy", 0);
3054 if (!of_phy_is_fixed_link(dn
)) {
3055 dev_err(&pdev
->dev
, "no PHY specified\n");
3060 err
= of_phy_register_fixed_link(dn
);
3062 dev_err(&pdev
->dev
, "cannot register fixed PHY\n");
3066 /* In the case of a fixed PHY, the DT node associated
3067 * to the PHY is the Ethernet MAC DT node.
3069 phy_node
= of_node_get(dn
);
3072 phy_mode
= of_get_phy_mode(dn
);
3074 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
3076 goto err_put_phy_node
;
3079 dev
->tx_queue_len
= MVNETA_MAX_TXD
;
3080 dev
->watchdog_timeo
= 5 * HZ
;
3081 dev
->netdev_ops
= &mvneta_netdev_ops
;
3083 dev
->ethtool_ops
= &mvneta_eth_tool_ops
;
3085 pp
= netdev_priv(dev
);
3086 pp
->phy_node
= phy_node
;
3087 pp
->phy_interface
= phy_mode
;
3089 err
= of_property_read_string(dn
, "managed", &managed
);
3090 pp
->use_inband_status
= (err
== 0 &&
3091 strcmp(managed
, "in-band-status") == 0);
3093 pp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
3094 if (IS_ERR(pp
->clk
)) {
3095 err
= PTR_ERR(pp
->clk
);
3096 goto err_put_phy_node
;
3099 clk_prepare_enable(pp
->clk
);
3101 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3102 pp
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
3103 if (IS_ERR(pp
->base
)) {
3104 err
= PTR_ERR(pp
->base
);
3108 /* Alloc per-cpu stats */
3109 pp
->stats
= netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats
);
3115 dt_mac_addr
= of_get_mac_address(dn
);
3117 mac_from
= "device tree";
3118 memcpy(dev
->dev_addr
, dt_mac_addr
, ETH_ALEN
);
3120 mvneta_get_mac_addr(pp
, hw_mac_addr
);
3121 if (is_valid_ether_addr(hw_mac_addr
)) {
3122 mac_from
= "hardware";
3123 memcpy(dev
->dev_addr
, hw_mac_addr
, ETH_ALEN
);
3125 mac_from
= "random";
3126 eth_hw_addr_random(dev
);
3130 if (of_device_is_compatible(dn
, "marvell,armada-370-neta"))
3131 pp
->tx_csum_limit
= 1600;
3133 pp
->tx_ring_size
= MVNETA_MAX_TXD
;
3134 pp
->rx_ring_size
= MVNETA_MAX_RXD
;
3137 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3139 err
= mvneta_init(&pdev
->dev
, pp
);
3141 goto err_free_stats
;
3143 err
= mvneta_port_power_up(pp
, phy_mode
);
3145 dev_err(&pdev
->dev
, "can't power up port\n");
3146 goto err_free_stats
;
3149 dram_target_info
= mv_mbus_dram_info();
3150 if (dram_target_info
)
3151 mvneta_conf_mbus_windows(pp
, dram_target_info
);
3153 netif_napi_add(dev
, &pp
->napi
, mvneta_poll
, NAPI_POLL_WEIGHT
);
3155 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
;
3156 dev
->hw_features
|= dev
->features
;
3157 dev
->vlan_features
|= dev
->features
;
3158 dev
->priv_flags
|= IFF_UNICAST_FLT
;
3159 dev
->gso_max_segs
= MVNETA_MAX_TSO_SEGS
;
3161 err
= register_netdev(dev
);
3163 dev_err(&pdev
->dev
, "failed to register\n");
3164 goto err_free_stats
;
3167 netdev_info(dev
, "Using %s mac address %pM\n", mac_from
,
3170 platform_set_drvdata(pdev
, pp
->dev
);
3172 if (pp
->use_inband_status
) {
3173 struct phy_device
*phy
= of_phy_find_device(dn
);
3175 mvneta_fixed_link_update(pp
, phy
);
3181 free_percpu(pp
->stats
);
3183 clk_disable_unprepare(pp
->clk
);
3185 of_node_put(phy_node
);
3187 irq_dispose_mapping(dev
->irq
);
3193 /* Device removal routine */
3194 static int mvneta_remove(struct platform_device
*pdev
)
3196 struct net_device
*dev
= platform_get_drvdata(pdev
);
3197 struct mvneta_port
*pp
= netdev_priv(dev
);
3199 unregister_netdev(dev
);
3200 clk_disable_unprepare(pp
->clk
);
3201 free_percpu(pp
->stats
);
3202 irq_dispose_mapping(dev
->irq
);
3203 of_node_put(pp
->phy_node
);
3209 static const struct of_device_id mvneta_match
[] = {
3210 { .compatible
= "marvell,armada-370-neta" },
3211 { .compatible
= "marvell,armada-xp-neta" },
3214 MODULE_DEVICE_TABLE(of
, mvneta_match
);
3216 static struct platform_driver mvneta_driver
= {
3217 .probe
= mvneta_probe
,
3218 .remove
= mvneta_remove
,
3220 .name
= MVNETA_DRIVER_NAME
,
3221 .of_match_table
= mvneta_match
,
3225 module_platform_driver(mvneta_driver
);
3227 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3228 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3229 MODULE_LICENSE("GPL");
3231 module_param(rxq_number
, int, S_IRUGO
);
3232 module_param(txq_number
, int, S_IRUGO
);
3234 module_param(rxq_def
, int, S_IRUGO
);
3235 module_param(rx_copybreak
, int, S_IRUGO
| S_IWUSR
);