2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy.h>
32 #include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
36 #include "mvneta_bm.h"
40 #include <net/page_pool.h>
41 #include <linux/bpf_trace.h>
44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
66 #define MVNETA_PORT_RX_RESET 0x1cc0
67 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
68 #define MVNETA_PHY_ADDR 0x2000
69 #define MVNETA_PHY_ADDR_MASK 0x1f
70 #define MVNETA_MBUS_RETRY 0x2010
71 #define MVNETA_UNIT_INTR_CAUSE 0x2080
72 #define MVNETA_UNIT_CONTROL 0x20B0
73 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
77 #define MVNETA_BASE_ADDR_ENABLE 0x2290
78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
79 #define MVNETA_PORT_CONFIG 0x2400
80 #define MVNETA_UNI_PROMISC_MODE BIT(0)
81 #define MVNETA_DEF_RXQ(q) ((q) << 1)
82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
89 MVNETA_DEF_RXQ_ARP(q) | \
90 MVNETA_DEF_RXQ_TCP(q) | \
91 MVNETA_DEF_RXQ_UDP(q) | \
92 MVNETA_DEF_RXQ_BPDU(q) | \
93 MVNETA_TX_UNSET_ERR_SUM | \
94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
96 #define MVNETA_MAC_ADDR_LOW 0x2414
97 #define MVNETA_MAC_ADDR_HIGH 0x2418
98 #define MVNETA_SDMA_CONFIG 0x241c
99 #define MVNETA_SDMA_BRST_SIZE_16 4
100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
101 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
102 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
103 #define MVNETA_DESC_SWAP BIT(6)
104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
105 #define MVNETA_PORT_STATUS 0x2444
106 #define MVNETA_TX_IN_PRGRS BIT(1)
107 #define MVNETA_TX_FIFO_EMPTY BIT(8)
108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
109 #define MVNETA_SERDES_CFG 0x24A0
110 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
111 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
112 #define MVNETA_TYPE_PRIO 0x24bc
113 #define MVNETA_FORCE_UNI BIT(21)
114 #define MVNETA_TXQ_CMD_1 0x24e4
115 #define MVNETA_TXQ_CMD 0x2448
116 #define MVNETA_TXQ_DISABLE_SHIFT 8
117 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
118 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
119 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
120 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
121 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
122 #define MVNETA_ACC_MODE 0x2500
123 #define MVNETA_BM_ADDRESS 0x2504
124 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
125 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
126 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
127 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
128 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
129 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
131 /* Exception Interrupt Port/Queue Cause register
133 * Their behavior depend of the mapping done using the PCPX2Q
134 * registers. For a given CPU if the bit associated to a queue is not
135 * set, then for the register a read from this CPU will always return
136 * 0 and a write won't do anything
139 #define MVNETA_INTR_NEW_CAUSE 0x25a0
140 #define MVNETA_INTR_NEW_MASK 0x25a4
142 /* bits 0..7 = TXQ SENT, one bit per queue.
143 * bits 8..15 = RXQ OCCUP, one bit per queue.
144 * bits 16..23 = RXQ FREE, one bit per queue.
145 * bit 29 = OLD_REG_SUM, see old reg ?
146 * bit 30 = TX_ERR_SUM, one bit for 4 ports
147 * bit 31 = MISC_SUM, one bit for 4 ports
149 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
150 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
151 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
152 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
153 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
155 #define MVNETA_INTR_OLD_CAUSE 0x25a8
156 #define MVNETA_INTR_OLD_MASK 0x25ac
158 /* Data Path Port/Queue Cause Register */
159 #define MVNETA_INTR_MISC_CAUSE 0x25b0
160 #define MVNETA_INTR_MISC_MASK 0x25b4
162 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
163 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
164 #define MVNETA_CAUSE_PTP BIT(4)
166 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
167 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
168 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
169 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
170 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
171 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
172 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
173 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
175 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
176 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
179 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
180 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
181 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
183 #define MVNETA_INTR_ENABLE 0x25b8
184 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
185 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
187 #define MVNETA_RXQ_CMD 0x2680
188 #define MVNETA_RXQ_DISABLE_SHIFT 8
189 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
190 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
191 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
192 #define MVNETA_GMAC_CTRL_0 0x2c00
193 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
194 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
195 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
196 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
197 #define MVNETA_GMAC_CTRL_2 0x2c08
198 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
199 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
200 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
201 #define MVNETA_GMAC2_PORT_RESET BIT(6)
202 #define MVNETA_GMAC_STATUS 0x2c10
203 #define MVNETA_GMAC_LINK_UP BIT(0)
204 #define MVNETA_GMAC_SPEED_1000 BIT(1)
205 #define MVNETA_GMAC_SPEED_100 BIT(2)
206 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
207 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
208 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
209 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
210 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
211 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
212 #define MVNETA_GMAC_SYNC_OK BIT(14)
213 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
214 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
215 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
216 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
217 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
218 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
219 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
220 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
221 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
222 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
223 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
224 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
225 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
226 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
227 #define MVNETA_GMAC_CTRL_4 0x2c90
228 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
229 #define MVNETA_MIB_COUNTERS_BASE 0x3000
230 #define MVNETA_MIB_LATE_COLLISION 0x7c
231 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
232 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
233 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
234 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
235 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
236 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
237 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
238 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
239 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
240 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
241 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
242 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
243 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
244 #define MVNETA_PORT_TX_RESET 0x3cf0
245 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
246 #define MVNETA_TX_MTU 0x3e0c
247 #define MVNETA_TX_TOKEN_SIZE 0x3e14
248 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
249 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
250 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
252 #define MVNETA_LPI_CTRL_0 0x2cc0
253 #define MVNETA_LPI_CTRL_1 0x2cc4
254 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
255 #define MVNETA_LPI_CTRL_2 0x2cc8
256 #define MVNETA_LPI_STATUS 0x2ccc
258 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
260 /* Descriptor ring Macros */
261 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
262 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
264 /* Various constants */
267 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
268 #define MVNETA_RX_COAL_PKTS 32
269 #define MVNETA_RX_COAL_USEC 100
271 /* The two bytes Marvell header. Either contains a special value used
272 * by Marvell switches when a specific hardware mode is enabled (not
273 * supported by this driver) or is filled automatically by zeroes on
274 * the RX side. Those two bytes being at the front of the Ethernet
275 * header, they allow to have the IP header aligned on a 4 bytes
276 * boundary automatically: the hardware skips those two bytes on its
279 #define MVNETA_MH_SIZE 2
281 #define MVNETA_VLAN_TAG_LEN 4
283 #define MVNETA_TX_CSUM_DEF_SIZE 1600
284 #define MVNETA_TX_CSUM_MAX_SIZE 9800
285 #define MVNETA_ACC_MODE_EXT1 1
286 #define MVNETA_ACC_MODE_EXT2 2
288 #define MVNETA_MAX_DECODE_WIN 6
290 /* Timeout constants */
291 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
292 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
293 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
295 #define MVNETA_TX_MTU_MAX 0x3ffff
297 /* The RSS lookup table actually has 256 entries but we do not use
300 #define MVNETA_RSS_LU_TABLE_SIZE 1
302 /* Max number of Rx descriptors */
303 #define MVNETA_MAX_RXD 512
305 /* Max number of Tx descriptors */
306 #define MVNETA_MAX_TXD 1024
308 /* Max number of allowed TCP segments for software TSO */
309 #define MVNETA_MAX_TSO_SEGS 100
311 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
313 /* descriptor aligned size */
314 #define MVNETA_DESC_ALIGNED_SIZE 32
316 /* Number of bytes to be taken into account by HW when putting incoming data
317 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
318 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
320 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
322 #define MVNETA_RX_PKT_SIZE(mtu) \
323 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
324 ETH_HLEN + ETH_FCS_LEN, \
327 #define MVNETA_SKB_HEADROOM max(XDP_PACKET_HEADROOM, NET_SKB_PAD)
328 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
329 MVNETA_SKB_HEADROOM))
330 #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD)
331 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
333 #define IS_TSO_HEADER(txq, addr) \
334 ((addr >= txq->tso_hdrs_phys) && \
335 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
337 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
338 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
341 ETHTOOL_STAT_EEE_WAKEUP
,
342 ETHTOOL_STAT_SKB_ALLOC_ERR
,
343 ETHTOOL_STAT_REFILL_ERR
,
344 ETHTOOL_XDP_REDIRECT
,
350 ETHTOOL_XDP_XMIT_ERR
,
354 struct mvneta_statistic
{
355 unsigned short offset
;
357 const char name
[ETH_GSTRING_LEN
];
364 #define MVNETA_XDP_PASS 0
365 #define MVNETA_XDP_DROPPED BIT(0)
366 #define MVNETA_XDP_TX BIT(1)
367 #define MVNETA_XDP_REDIR BIT(2)
369 static const struct mvneta_statistic mvneta_statistics
[] = {
370 { 0x3000, T_REG_64
, "good_octets_received", },
371 { 0x3010, T_REG_32
, "good_frames_received", },
372 { 0x3008, T_REG_32
, "bad_octets_received", },
373 { 0x3014, T_REG_32
, "bad_frames_received", },
374 { 0x3018, T_REG_32
, "broadcast_frames_received", },
375 { 0x301c, T_REG_32
, "multicast_frames_received", },
376 { 0x3050, T_REG_32
, "unrec_mac_control_received", },
377 { 0x3058, T_REG_32
, "good_fc_received", },
378 { 0x305c, T_REG_32
, "bad_fc_received", },
379 { 0x3060, T_REG_32
, "undersize_received", },
380 { 0x3064, T_REG_32
, "fragments_received", },
381 { 0x3068, T_REG_32
, "oversize_received", },
382 { 0x306c, T_REG_32
, "jabber_received", },
383 { 0x3070, T_REG_32
, "mac_receive_error", },
384 { 0x3074, T_REG_32
, "bad_crc_event", },
385 { 0x3078, T_REG_32
, "collision", },
386 { 0x307c, T_REG_32
, "late_collision", },
387 { 0x2484, T_REG_32
, "rx_discard", },
388 { 0x2488, T_REG_32
, "rx_overrun", },
389 { 0x3020, T_REG_32
, "frames_64_octets", },
390 { 0x3024, T_REG_32
, "frames_65_to_127_octets", },
391 { 0x3028, T_REG_32
, "frames_128_to_255_octets", },
392 { 0x302c, T_REG_32
, "frames_256_to_511_octets", },
393 { 0x3030, T_REG_32
, "frames_512_to_1023_octets", },
394 { 0x3034, T_REG_32
, "frames_1024_to_max_octets", },
395 { 0x3038, T_REG_64
, "good_octets_sent", },
396 { 0x3040, T_REG_32
, "good_frames_sent", },
397 { 0x3044, T_REG_32
, "excessive_collision", },
398 { 0x3048, T_REG_32
, "multicast_frames_sent", },
399 { 0x304c, T_REG_32
, "broadcast_frames_sent", },
400 { 0x3054, T_REG_32
, "fc_sent", },
401 { 0x300c, T_REG_32
, "internal_mac_transmit_err", },
402 { ETHTOOL_STAT_EEE_WAKEUP
, T_SW
, "eee_wakeup_errors", },
403 { ETHTOOL_STAT_SKB_ALLOC_ERR
, T_SW
, "skb_alloc_errors", },
404 { ETHTOOL_STAT_REFILL_ERR
, T_SW
, "refill_errors", },
405 { ETHTOOL_XDP_REDIRECT
, T_SW
, "rx_xdp_redirect", },
406 { ETHTOOL_XDP_PASS
, T_SW
, "rx_xdp_pass", },
407 { ETHTOOL_XDP_DROP
, T_SW
, "rx_xdp_drop", },
408 { ETHTOOL_XDP_TX
, T_SW
, "rx_xdp_tx", },
409 { ETHTOOL_XDP_TX_ERR
, T_SW
, "rx_xdp_tx_errors", },
410 { ETHTOOL_XDP_XMIT
, T_SW
, "tx_xdp_xmit", },
411 { ETHTOOL_XDP_XMIT_ERR
, T_SW
, "tx_xdp_xmit_errors", },
414 struct mvneta_stats
{
429 struct mvneta_ethtool_stats
{
430 struct mvneta_stats ps
;
435 struct mvneta_pcpu_stats
{
436 struct u64_stats_sync syncp
;
438 struct mvneta_ethtool_stats es
;
443 struct mvneta_pcpu_port
{
444 /* Pointer to the shared port */
445 struct mvneta_port
*pp
;
447 /* Pointer to the CPU-local NAPI struct */
448 struct napi_struct napi
;
450 /* Cause of the previous interrupt */
456 struct mvneta_pcpu_port __percpu
*ports
;
457 struct mvneta_pcpu_stats __percpu
*stats
;
461 struct mvneta_rx_queue
*rxqs
;
462 struct mvneta_tx_queue
*txqs
;
463 struct net_device
*dev
;
464 struct hlist_node node_online
;
465 struct hlist_node node_dead
;
467 /* Protect the access to the percpu interrupt registers,
468 * ensuring that the configuration remains coherent.
474 struct napi_struct napi
;
476 struct bpf_prog
*xdp_prog
;
486 phy_interface_t phy_interface
;
487 struct device_node
*dn
;
488 unsigned int tx_csum_limit
;
489 struct phylink
*phylink
;
490 struct phylink_config phylink_config
;
493 struct mvneta_bm
*bm_priv
;
494 struct mvneta_bm_pool
*pool_long
;
495 struct mvneta_bm_pool
*pool_short
;
502 u64 ethtool_stats
[ARRAY_SIZE(mvneta_statistics
)];
504 u32 indir
[MVNETA_RSS_LU_TABLE_SIZE
];
506 /* Flags for special SoC configurations */
507 bool neta_armada3700
;
508 u16 rx_offset_correction
;
509 const struct mbus_dram_target_info
*dram_target_info
;
512 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
513 * layout of the transmit and reception DMA descriptors, and their
514 * layout is therefore defined by the hardware design
517 #define MVNETA_TX_L3_OFF_SHIFT 0
518 #define MVNETA_TX_IP_HLEN_SHIFT 8
519 #define MVNETA_TX_L4_UDP BIT(16)
520 #define MVNETA_TX_L3_IP6 BIT(17)
521 #define MVNETA_TXD_IP_CSUM BIT(18)
522 #define MVNETA_TXD_Z_PAD BIT(19)
523 #define MVNETA_TXD_L_DESC BIT(20)
524 #define MVNETA_TXD_F_DESC BIT(21)
525 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
526 MVNETA_TXD_L_DESC | \
528 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
529 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
531 #define MVNETA_RXD_ERR_CRC 0x0
532 #define MVNETA_RXD_BM_POOL_SHIFT 13
533 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
534 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
535 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
536 #define MVNETA_RXD_ERR_LEN BIT(18)
537 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
538 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
539 #define MVNETA_RXD_L3_IP4 BIT(25)
540 #define MVNETA_RXD_LAST_DESC BIT(26)
541 #define MVNETA_RXD_FIRST_DESC BIT(27)
542 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
543 MVNETA_RXD_LAST_DESC)
544 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
546 #if defined(__LITTLE_ENDIAN)
547 struct mvneta_tx_desc
{
548 u32 command
; /* Options used by HW for packet transmitting.*/
549 u16 reserved1
; /* csum_l4 (for future use) */
550 u16 data_size
; /* Data size of transmitted packet in bytes */
551 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
552 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
553 u32 reserved3
[4]; /* Reserved - (for future use) */
556 struct mvneta_rx_desc
{
557 u32 status
; /* Info about received packet */
558 u16 reserved1
; /* pnc_info - (for future use, PnC) */
559 u16 data_size
; /* Size of received packet in bytes */
561 u32 buf_phys_addr
; /* Physical address of the buffer */
562 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
564 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
565 u16 reserved3
; /* prefetch_cmd, for future use */
566 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
568 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
569 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
572 struct mvneta_tx_desc
{
573 u16 data_size
; /* Data size of transmitted packet in bytes */
574 u16 reserved1
; /* csum_l4 (for future use) */
575 u32 command
; /* Options used by HW for packet transmitting.*/
576 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
577 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
578 u32 reserved3
[4]; /* Reserved - (for future use) */
581 struct mvneta_rx_desc
{
582 u16 data_size
; /* Size of received packet in bytes */
583 u16 reserved1
; /* pnc_info - (for future use, PnC) */
584 u32 status
; /* Info about received packet */
586 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
587 u32 buf_phys_addr
; /* Physical address of the buffer */
589 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
590 u16 reserved3
; /* prefetch_cmd, for future use */
591 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
593 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
594 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
598 enum mvneta_tx_buf_type
{
604 struct mvneta_tx_buf
{
605 enum mvneta_tx_buf_type type
;
607 struct xdp_frame
*xdpf
;
612 struct mvneta_tx_queue
{
613 /* Number of this TX queue, in the range 0-7 */
616 /* Number of TX DMA descriptors in the descriptor ring */
619 /* Number of currently used TX DMA descriptor in the
624 int tx_stop_threshold
;
625 int tx_wake_threshold
;
627 /* Array of transmitted buffers */
628 struct mvneta_tx_buf
*buf
;
630 /* Index of last TX DMA descriptor that was inserted */
633 /* Index of the TX DMA descriptor to be cleaned up */
638 /* Virtual address of the TX DMA descriptors array */
639 struct mvneta_tx_desc
*descs
;
641 /* DMA address of the TX DMA descriptors array */
642 dma_addr_t descs_phys
;
644 /* Index of the last TX DMA descriptor */
647 /* Index of the next TX DMA descriptor to process */
648 int next_desc_to_proc
;
650 /* DMA buffers for TSO headers */
653 /* DMA address of TSO headers */
654 dma_addr_t tso_hdrs_phys
;
656 /* Affinity mask for CPUs*/
657 cpumask_t affinity_mask
;
660 struct mvneta_rx_queue
{
661 /* rx queue number, in the range 0-7 */
664 /* num of rx descriptors in the rx descriptor ring */
671 struct page_pool
*page_pool
;
672 struct xdp_rxq_info xdp_rxq
;
674 /* Virtual address of the RX buffer */
675 void **buf_virt_addr
;
677 /* Virtual address of the RX DMA descriptors array */
678 struct mvneta_rx_desc
*descs
;
680 /* DMA address of the RX DMA descriptors array */
681 dma_addr_t descs_phys
;
683 /* Index of the last RX DMA descriptor */
686 /* Index of the next RX DMA descriptor to process */
687 int next_desc_to_proc
;
689 /* Index of first RX DMA descriptor to refill */
693 /* pointer to uncomplete skb buffer */
698 static enum cpuhp_state online_hpstate
;
699 /* The hardware supports eight (8) rx queues, but we are only allowing
700 * the first one to be used. Therefore, let's just allocate one queue.
702 static int rxq_number
= 8;
703 static int txq_number
= 8;
707 static int rx_copybreak __read_mostly
= 256;
709 /* HW BM need that each port be identify by a unique ID */
710 static int global_port_id
;
712 #define MVNETA_DRIVER_NAME "mvneta"
713 #define MVNETA_DRIVER_VERSION "1.0"
715 /* Utility/helper methods */
717 /* Write helper method */
718 static void mvreg_write(struct mvneta_port
*pp
, u32 offset
, u32 data
)
720 writel(data
, pp
->base
+ offset
);
723 /* Read helper method */
724 static u32
mvreg_read(struct mvneta_port
*pp
, u32 offset
)
726 return readl(pp
->base
+ offset
);
729 /* Increment txq get counter */
730 static void mvneta_txq_inc_get(struct mvneta_tx_queue
*txq
)
732 txq
->txq_get_index
++;
733 if (txq
->txq_get_index
== txq
->size
)
734 txq
->txq_get_index
= 0;
737 /* Increment txq put counter */
738 static void mvneta_txq_inc_put(struct mvneta_tx_queue
*txq
)
740 txq
->txq_put_index
++;
741 if (txq
->txq_put_index
== txq
->size
)
742 txq
->txq_put_index
= 0;
746 /* Clear all MIB counters */
747 static void mvneta_mib_counters_clear(struct mvneta_port
*pp
)
752 /* Perform dummy reads from MIB counters */
753 for (i
= 0; i
< MVNETA_MIB_LATE_COLLISION
; i
+= 4)
754 dummy
= mvreg_read(pp
, (MVNETA_MIB_COUNTERS_BASE
+ i
));
755 dummy
= mvreg_read(pp
, MVNETA_RX_DISCARD_FRAME_COUNT
);
756 dummy
= mvreg_read(pp
, MVNETA_OVERRUN_FRAME_COUNT
);
759 /* Get System Network Statistics */
761 mvneta_get_stats64(struct net_device
*dev
,
762 struct rtnl_link_stats64
*stats
)
764 struct mvneta_port
*pp
= netdev_priv(dev
);
768 for_each_possible_cpu(cpu
) {
769 struct mvneta_pcpu_stats
*cpu_stats
;
777 cpu_stats
= per_cpu_ptr(pp
->stats
, cpu
);
779 start
= u64_stats_fetch_begin_irq(&cpu_stats
->syncp
);
780 rx_packets
= cpu_stats
->es
.ps
.rx_packets
;
781 rx_bytes
= cpu_stats
->es
.ps
.rx_bytes
;
782 rx_dropped
= cpu_stats
->rx_dropped
;
783 rx_errors
= cpu_stats
->rx_errors
;
784 tx_packets
= cpu_stats
->es
.ps
.tx_packets
;
785 tx_bytes
= cpu_stats
->es
.ps
.tx_bytes
;
786 } while (u64_stats_fetch_retry_irq(&cpu_stats
->syncp
, start
));
788 stats
->rx_packets
+= rx_packets
;
789 stats
->rx_bytes
+= rx_bytes
;
790 stats
->rx_dropped
+= rx_dropped
;
791 stats
->rx_errors
+= rx_errors
;
792 stats
->tx_packets
+= tx_packets
;
793 stats
->tx_bytes
+= tx_bytes
;
796 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
799 /* Rx descriptors helper methods */
801 /* Checks whether the RX descriptor having this status is both the first
802 * and the last descriptor for the RX packet. Each RX packet is currently
803 * received through a single RX descriptor, so not having each RX
804 * descriptor with its first and last bits set is an error
806 static int mvneta_rxq_desc_is_first_last(u32 status
)
808 return (status
& MVNETA_RXD_FIRST_LAST_DESC
) ==
809 MVNETA_RXD_FIRST_LAST_DESC
;
812 /* Add number of descriptors ready to receive new packets */
813 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port
*pp
,
814 struct mvneta_rx_queue
*rxq
,
817 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
820 while (ndescs
> MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
) {
821 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
822 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
<<
823 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
824 ndescs
-= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
;
827 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
828 (ndescs
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
831 /* Get number of RX descriptors occupied by received packets */
832 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port
*pp
,
833 struct mvneta_rx_queue
*rxq
)
837 val
= mvreg_read(pp
, MVNETA_RXQ_STATUS_REG(rxq
->id
));
838 return val
& MVNETA_RXQ_OCCUPIED_ALL_MASK
;
841 /* Update num of rx desc called upon return from rx path or
842 * from mvneta_rxq_drop_pkts().
844 static void mvneta_rxq_desc_num_update(struct mvneta_port
*pp
,
845 struct mvneta_rx_queue
*rxq
,
846 int rx_done
, int rx_filled
)
850 if ((rx_done
<= 0xff) && (rx_filled
<= 0xff)) {
852 (rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
);
853 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
857 /* Only 255 descriptors can be added at once */
858 while ((rx_done
> 0) || (rx_filled
> 0)) {
859 if (rx_done
<= 0xff) {
866 if (rx_filled
<= 0xff) {
867 val
|= rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
870 val
|= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
873 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
877 /* Get pointer to next RX descriptor to be processed by SW */
878 static struct mvneta_rx_desc
*
879 mvneta_rxq_next_desc_get(struct mvneta_rx_queue
*rxq
)
881 int rx_desc
= rxq
->next_desc_to_proc
;
883 rxq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(rxq
, rx_desc
);
884 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
885 return rxq
->descs
+ rx_desc
;
888 /* Change maximum receive size of the port. */
889 static void mvneta_max_rx_size_set(struct mvneta_port
*pp
, int max_rx_size
)
893 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
894 val
&= ~MVNETA_GMAC_MAX_RX_SIZE_MASK
;
895 val
|= ((max_rx_size
- MVNETA_MH_SIZE
) / 2) <<
896 MVNETA_GMAC_MAX_RX_SIZE_SHIFT
;
897 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
901 /* Set rx queue offset */
902 static void mvneta_rxq_offset_set(struct mvneta_port
*pp
,
903 struct mvneta_rx_queue
*rxq
,
908 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
909 val
&= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK
;
912 val
|= MVNETA_RXQ_PKT_OFFSET_MASK(offset
>> 3);
913 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
917 /* Tx descriptors helper methods */
919 /* Update HW with number of TX descriptors to be sent */
920 static void mvneta_txq_pend_desc_add(struct mvneta_port
*pp
,
921 struct mvneta_tx_queue
*txq
,
926 pend_desc
+= txq
->pending
;
928 /* Only 255 Tx descriptors can be added at once */
930 val
= min(pend_desc
, 255);
931 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
933 } while (pend_desc
> 0);
937 /* Get pointer to next TX descriptor to be processed (send) by HW */
938 static struct mvneta_tx_desc
*
939 mvneta_txq_next_desc_get(struct mvneta_tx_queue
*txq
)
941 int tx_desc
= txq
->next_desc_to_proc
;
943 txq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(txq
, tx_desc
);
944 return txq
->descs
+ tx_desc
;
947 /* Release the last allocated TX descriptor. Useful to handle DMA
948 * mapping failures in the TX path.
950 static void mvneta_txq_desc_put(struct mvneta_tx_queue
*txq
)
952 if (txq
->next_desc_to_proc
== 0)
953 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
955 txq
->next_desc_to_proc
--;
958 /* Set rxq buf size */
959 static void mvneta_rxq_buf_size_set(struct mvneta_port
*pp
,
960 struct mvneta_rx_queue
*rxq
,
965 val
= mvreg_read(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
));
967 val
&= ~MVNETA_RXQ_BUF_SIZE_MASK
;
968 val
|= ((buf_size
>> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT
);
970 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), val
);
973 /* Disable buffer management (BM) */
974 static void mvneta_rxq_bm_disable(struct mvneta_port
*pp
,
975 struct mvneta_rx_queue
*rxq
)
979 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
980 val
&= ~MVNETA_RXQ_HW_BUF_ALLOC
;
981 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
984 /* Enable buffer management (BM) */
985 static void mvneta_rxq_bm_enable(struct mvneta_port
*pp
,
986 struct mvneta_rx_queue
*rxq
)
990 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
991 val
|= MVNETA_RXQ_HW_BUF_ALLOC
;
992 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
995 /* Notify HW about port's assignment of pool for bigger packets */
996 static void mvneta_rxq_long_pool_set(struct mvneta_port
*pp
,
997 struct mvneta_rx_queue
*rxq
)
1001 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
1002 val
&= ~MVNETA_RXQ_LONG_POOL_ID_MASK
;
1003 val
|= (pp
->pool_long
->id
<< MVNETA_RXQ_LONG_POOL_ID_SHIFT
);
1005 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
1008 /* Notify HW about port's assignment of pool for smaller packets */
1009 static void mvneta_rxq_short_pool_set(struct mvneta_port
*pp
,
1010 struct mvneta_rx_queue
*rxq
)
1014 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
1015 val
&= ~MVNETA_RXQ_SHORT_POOL_ID_MASK
;
1016 val
|= (pp
->pool_short
->id
<< MVNETA_RXQ_SHORT_POOL_ID_SHIFT
);
1018 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
1021 /* Set port's receive buffer size for assigned BM pool */
1022 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port
*pp
,
1028 if (!IS_ALIGNED(buf_size
, 8)) {
1029 dev_warn(pp
->dev
->dev
.parent
,
1030 "illegal buf_size value %d, round to %d\n",
1031 buf_size
, ALIGN(buf_size
, 8));
1032 buf_size
= ALIGN(buf_size
, 8);
1035 val
= mvreg_read(pp
, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id
));
1036 val
|= buf_size
& MVNETA_PORT_POOL_BUFFER_SZ_MASK
;
1037 mvreg_write(pp
, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id
), val
);
1040 /* Configure MBUS window in order to enable access BM internal SRAM */
1041 static int mvneta_mbus_io_win_set(struct mvneta_port
*pp
, u32 base
, u32 wsize
,
1044 u32 win_enable
, win_protect
;
1047 win_enable
= mvreg_read(pp
, MVNETA_BASE_ADDR_ENABLE
);
1049 if (pp
->bm_win_id
< 0) {
1050 /* Find first not occupied window */
1051 for (i
= 0; i
< MVNETA_MAX_DECODE_WIN
; i
++) {
1052 if (win_enable
& (1 << i
)) {
1057 if (i
== MVNETA_MAX_DECODE_WIN
)
1063 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
1064 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
1067 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
1069 mvreg_write(pp
, MVNETA_WIN_BASE(i
), (base
& 0xffff0000) |
1070 (attr
<< 8) | target
);
1072 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), (wsize
- 1) & 0xffff0000);
1074 win_protect
= mvreg_read(pp
, MVNETA_ACCESS_PROTECT_ENABLE
);
1075 win_protect
|= 3 << (2 * i
);
1076 mvreg_write(pp
, MVNETA_ACCESS_PROTECT_ENABLE
, win_protect
);
1078 win_enable
&= ~(1 << i
);
1079 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
1084 static int mvneta_bm_port_mbus_init(struct mvneta_port
*pp
)
1090 /* Get BM window information */
1091 err
= mvebu_mbus_get_io_win_info(pp
->bm_priv
->bppi_phys_addr
, &wsize
,
1098 /* Open NETA -> BM window */
1099 err
= mvneta_mbus_io_win_set(pp
, pp
->bm_priv
->bppi_phys_addr
, wsize
,
1102 netdev_info(pp
->dev
, "fail to configure mbus window to BM\n");
1108 /* Assign and initialize pools for port. In case of fail
1109 * buffer manager will remain disabled for current port.
1111 static int mvneta_bm_port_init(struct platform_device
*pdev
,
1112 struct mvneta_port
*pp
)
1114 struct device_node
*dn
= pdev
->dev
.of_node
;
1115 u32 long_pool_id
, short_pool_id
;
1117 if (!pp
->neta_armada3700
) {
1120 ret
= mvneta_bm_port_mbus_init(pp
);
1125 if (of_property_read_u32(dn
, "bm,pool-long", &long_pool_id
)) {
1126 netdev_info(pp
->dev
, "missing long pool id\n");
1130 /* Create port's long pool depending on mtu */
1131 pp
->pool_long
= mvneta_bm_pool_use(pp
->bm_priv
, long_pool_id
,
1132 MVNETA_BM_LONG
, pp
->id
,
1133 MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
));
1134 if (!pp
->pool_long
) {
1135 netdev_info(pp
->dev
, "fail to obtain long pool for port\n");
1139 pp
->pool_long
->port_map
|= 1 << pp
->id
;
1141 mvneta_bm_pool_bufsize_set(pp
, pp
->pool_long
->buf_size
,
1144 /* If short pool id is not defined, assume using single pool */
1145 if (of_property_read_u32(dn
, "bm,pool-short", &short_pool_id
))
1146 short_pool_id
= long_pool_id
;
1148 /* Create port's short pool */
1149 pp
->pool_short
= mvneta_bm_pool_use(pp
->bm_priv
, short_pool_id
,
1150 MVNETA_BM_SHORT
, pp
->id
,
1151 MVNETA_BM_SHORT_PKT_SIZE
);
1152 if (!pp
->pool_short
) {
1153 netdev_info(pp
->dev
, "fail to obtain short pool for port\n");
1154 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
1158 if (short_pool_id
!= long_pool_id
) {
1159 pp
->pool_short
->port_map
|= 1 << pp
->id
;
1160 mvneta_bm_pool_bufsize_set(pp
, pp
->pool_short
->buf_size
,
1161 pp
->pool_short
->id
);
1167 /* Update settings of a pool for bigger packets */
1168 static void mvneta_bm_update_mtu(struct mvneta_port
*pp
, int mtu
)
1170 struct mvneta_bm_pool
*bm_pool
= pp
->pool_long
;
1171 struct hwbm_pool
*hwbm_pool
= &bm_pool
->hwbm_pool
;
1174 /* Release all buffers from long pool */
1175 mvneta_bm_bufs_free(pp
->bm_priv
, bm_pool
, 1 << pp
->id
);
1176 if (hwbm_pool
->buf_num
) {
1177 WARN(1, "cannot free all buffers in pool %d\n",
1182 bm_pool
->pkt_size
= MVNETA_RX_PKT_SIZE(mtu
);
1183 bm_pool
->buf_size
= MVNETA_RX_BUF_SIZE(bm_pool
->pkt_size
);
1184 hwbm_pool
->frag_size
= SKB_DATA_ALIGN(sizeof(struct skb_shared_info
)) +
1185 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool
->pkt_size
));
1187 /* Fill entire long pool */
1188 num
= hwbm_pool_add(hwbm_pool
, hwbm_pool
->size
);
1189 if (num
!= hwbm_pool
->size
) {
1190 WARN(1, "pool %d: %d of %d allocated\n",
1191 bm_pool
->id
, num
, hwbm_pool
->size
);
1194 mvneta_bm_pool_bufsize_set(pp
, bm_pool
->buf_size
, bm_pool
->id
);
1199 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
1200 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
, 1 << pp
->id
);
1203 pp
->rx_offset_correction
= MVNETA_SKB_HEADROOM
;
1204 mvreg_write(pp
, MVNETA_ACC_MODE
, MVNETA_ACC_MODE_EXT1
);
1205 netdev_info(pp
->dev
, "fail to update MTU, fall back to software BM\n");
1208 /* Start the Ethernet port RX and TX activity */
1209 static void mvneta_port_up(struct mvneta_port
*pp
)
1214 /* Enable all initialized TXs. */
1216 for (queue
= 0; queue
< txq_number
; queue
++) {
1217 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
1219 q_map
|= (1 << queue
);
1221 mvreg_write(pp
, MVNETA_TXQ_CMD
, q_map
);
1224 /* Enable all initialized RXQs. */
1225 for (queue
= 0; queue
< rxq_number
; queue
++) {
1226 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
1229 q_map
|= (1 << queue
);
1231 mvreg_write(pp
, MVNETA_RXQ_CMD
, q_map
);
1234 /* Stop the Ethernet port activity */
1235 static void mvneta_port_down(struct mvneta_port
*pp
)
1240 /* Stop Rx port activity. Check port Rx activity. */
1241 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
) & MVNETA_RXQ_ENABLE_MASK
;
1243 /* Issue stop command for active channels only */
1245 mvreg_write(pp
, MVNETA_RXQ_CMD
,
1246 val
<< MVNETA_RXQ_DISABLE_SHIFT
);
1248 /* Wait for all Rx activity to terminate. */
1251 if (count
++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC
) {
1252 netdev_warn(pp
->dev
,
1253 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1259 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
);
1260 } while (val
& MVNETA_RXQ_ENABLE_MASK
);
1262 /* Stop Tx port activity. Check port Tx activity. Issue stop
1263 * command for active channels only
1265 val
= (mvreg_read(pp
, MVNETA_TXQ_CMD
)) & MVNETA_TXQ_ENABLE_MASK
;
1268 mvreg_write(pp
, MVNETA_TXQ_CMD
,
1269 (val
<< MVNETA_TXQ_DISABLE_SHIFT
));
1271 /* Wait for all Tx activity to terminate. */
1274 if (count
++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC
) {
1275 netdev_warn(pp
->dev
,
1276 "TIMEOUT for TX stopped status=0x%08x\n",
1282 /* Check TX Command reg that all Txqs are stopped */
1283 val
= mvreg_read(pp
, MVNETA_TXQ_CMD
);
1285 } while (val
& MVNETA_TXQ_ENABLE_MASK
);
1287 /* Double check to verify that TX FIFO is empty */
1290 if (count
++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT
) {
1291 netdev_warn(pp
->dev
,
1292 "TX FIFO empty timeout status=0x%08x\n",
1298 val
= mvreg_read(pp
, MVNETA_PORT_STATUS
);
1299 } while (!(val
& MVNETA_TX_FIFO_EMPTY
) &&
1300 (val
& MVNETA_TX_IN_PRGRS
));
1305 /* Enable the port by setting the port enable bit of the MAC control register */
1306 static void mvneta_port_enable(struct mvneta_port
*pp
)
1311 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
1312 val
|= MVNETA_GMAC0_PORT_ENABLE
;
1313 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
1316 /* Disable the port and wait for about 200 usec before retuning */
1317 static void mvneta_port_disable(struct mvneta_port
*pp
)
1321 /* Reset the Enable bit in the Serial Control Register */
1322 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
1323 val
&= ~MVNETA_GMAC0_PORT_ENABLE
;
1324 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
1329 /* Multicast tables methods */
1331 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1332 static void mvneta_set_ucast_table(struct mvneta_port
*pp
, int queue
)
1340 val
= 0x1 | (queue
<< 1);
1341 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1344 for (offset
= 0; offset
<= 0xc; offset
+= 4)
1345 mvreg_write(pp
, MVNETA_DA_FILT_UCAST_BASE
+ offset
, val
);
1348 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1349 static void mvneta_set_special_mcast_table(struct mvneta_port
*pp
, int queue
)
1357 val
= 0x1 | (queue
<< 1);
1358 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1361 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
1362 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ offset
, val
);
1366 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1367 static void mvneta_set_other_mcast_table(struct mvneta_port
*pp
, int queue
)
1373 memset(pp
->mcast_count
, 0, sizeof(pp
->mcast_count
));
1376 memset(pp
->mcast_count
, 1, sizeof(pp
->mcast_count
));
1377 val
= 0x1 | (queue
<< 1);
1378 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
1381 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
1382 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ offset
, val
);
1385 static void mvneta_percpu_unmask_interrupt(void *arg
)
1387 struct mvneta_port
*pp
= arg
;
1389 /* All the queue are unmasked, but actually only the ones
1390 * mapped to this CPU will be unmasked
1392 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
1393 MVNETA_RX_INTR_MASK_ALL
|
1394 MVNETA_TX_INTR_MASK_ALL
|
1395 MVNETA_MISCINTR_INTR_MASK
);
1398 static void mvneta_percpu_mask_interrupt(void *arg
)
1400 struct mvneta_port
*pp
= arg
;
1402 /* All the queue are masked, but actually only the ones
1403 * mapped to this CPU will be masked
1405 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
1406 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
1407 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
1410 static void mvneta_percpu_clear_intr_cause(void *arg
)
1412 struct mvneta_port
*pp
= arg
;
1414 /* All the queue are cleared, but actually only the ones
1415 * mapped to this CPU will be cleared
1417 mvreg_write(pp
, MVNETA_INTR_NEW_CAUSE
, 0);
1418 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
1419 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
1422 /* This method sets defaults to the NETA port:
1423 * Clears interrupt Cause and Mask registers.
1424 * Clears all MAC tables.
1425 * Sets defaults to all registers.
1426 * Resets RX and TX descriptor rings.
1428 * This method can be called after mvneta_port_down() to return the port
1429 * settings to defaults.
1431 static void mvneta_defaults_set(struct mvneta_port
*pp
)
1436 int max_cpu
= num_present_cpus();
1438 /* Clear all Cause registers */
1439 on_each_cpu(mvneta_percpu_clear_intr_cause
, pp
, true);
1441 /* Mask all interrupts */
1442 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
1443 mvreg_write(pp
, MVNETA_INTR_ENABLE
, 0);
1445 /* Enable MBUS Retry bit16 */
1446 mvreg_write(pp
, MVNETA_MBUS_RETRY
, 0x20);
1448 /* Set CPU queue access map. CPUs are assigned to the RX and
1449 * TX queues modulo their number. If there is only one TX
1450 * queue then it is assigned to the CPU associated to the
1453 for_each_present_cpu(cpu
) {
1454 int rxq_map
= 0, txq_map
= 0;
1456 if (!pp
->neta_armada3700
) {
1457 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
1458 if ((rxq
% max_cpu
) == cpu
)
1459 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(rxq
);
1461 for (txq
= 0; txq
< txq_number
; txq
++)
1462 if ((txq
% max_cpu
) == cpu
)
1463 txq_map
|= MVNETA_CPU_TXQ_ACCESS(txq
);
1465 /* With only one TX queue we configure a special case
1466 * which will allow to get all the irq on a single
1469 if (txq_number
== 1)
1470 txq_map
= (cpu
== pp
->rxq_def
) ?
1471 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1474 txq_map
= MVNETA_CPU_TXQ_ACCESS_ALL_MASK
;
1475 rxq_map
= MVNETA_CPU_RXQ_ACCESS_ALL_MASK
;
1478 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
), rxq_map
| txq_map
);
1481 /* Reset RX and TX DMAs */
1482 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
1483 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
1485 /* Disable Legacy WRR, Disable EJP, Release from reset */
1486 mvreg_write(pp
, MVNETA_TXQ_CMD_1
, 0);
1487 for (queue
= 0; queue
< txq_number
; queue
++) {
1488 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(queue
), 0);
1489 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(queue
), 0);
1492 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
1493 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
1495 /* Set Port Acceleration Mode */
1497 /* HW buffer management + legacy parser */
1498 val
= MVNETA_ACC_MODE_EXT2
;
1500 /* SW buffer management + legacy parser */
1501 val
= MVNETA_ACC_MODE_EXT1
;
1502 mvreg_write(pp
, MVNETA_ACC_MODE
, val
);
1505 mvreg_write(pp
, MVNETA_BM_ADDRESS
, pp
->bm_priv
->bppi_phys_addr
);
1507 /* Update val of portCfg register accordingly with all RxQueue types */
1508 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(pp
->rxq_def
);
1509 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
1512 mvreg_write(pp
, MVNETA_PORT_CONFIG_EXTEND
, val
);
1513 mvreg_write(pp
, MVNETA_RX_MIN_FRAME_SIZE
, 64);
1515 /* Build PORT_SDMA_CONFIG_REG */
1518 /* Default burst size */
1519 val
|= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
1520 val
|= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
1521 val
|= MVNETA_RX_NO_DATA_SWAP
| MVNETA_TX_NO_DATA_SWAP
;
1523 #if defined(__BIG_ENDIAN)
1524 val
|= MVNETA_DESC_SWAP
;
1527 /* Assign port SDMA configuration */
1528 mvreg_write(pp
, MVNETA_SDMA_CONFIG
, val
);
1530 /* Disable PHY polling in hardware, since we're using the
1531 * kernel phylib to do this.
1533 val
= mvreg_read(pp
, MVNETA_UNIT_CONTROL
);
1534 val
&= ~MVNETA_PHY_POLLING_ENABLE
;
1535 mvreg_write(pp
, MVNETA_UNIT_CONTROL
, val
);
1537 mvneta_set_ucast_table(pp
, -1);
1538 mvneta_set_special_mcast_table(pp
, -1);
1539 mvneta_set_other_mcast_table(pp
, -1);
1541 /* Set port interrupt enable register - default enable all */
1542 mvreg_write(pp
, MVNETA_INTR_ENABLE
,
1543 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1544 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK
));
1546 mvneta_mib_counters_clear(pp
);
1549 /* Set max sizes for tx queues */
1550 static void mvneta_txq_max_tx_size_set(struct mvneta_port
*pp
, int max_tx_size
)
1556 mtu
= max_tx_size
* 8;
1557 if (mtu
> MVNETA_TX_MTU_MAX
)
1558 mtu
= MVNETA_TX_MTU_MAX
;
1561 val
= mvreg_read(pp
, MVNETA_TX_MTU
);
1562 val
&= ~MVNETA_TX_MTU_MAX
;
1564 mvreg_write(pp
, MVNETA_TX_MTU
, val
);
1566 /* TX token size and all TXQs token size must be larger that MTU */
1567 val
= mvreg_read(pp
, MVNETA_TX_TOKEN_SIZE
);
1569 size
= val
& MVNETA_TX_TOKEN_SIZE_MAX
;
1572 val
&= ~MVNETA_TX_TOKEN_SIZE_MAX
;
1574 mvreg_write(pp
, MVNETA_TX_TOKEN_SIZE
, val
);
1576 for (queue
= 0; queue
< txq_number
; queue
++) {
1577 val
= mvreg_read(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
));
1579 size
= val
& MVNETA_TXQ_TOKEN_SIZE_MAX
;
1582 val
&= ~MVNETA_TXQ_TOKEN_SIZE_MAX
;
1584 mvreg_write(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
), val
);
1589 /* Set unicast address */
1590 static void mvneta_set_ucast_addr(struct mvneta_port
*pp
, u8 last_nibble
,
1593 unsigned int unicast_reg
;
1594 unsigned int tbl_offset
;
1595 unsigned int reg_offset
;
1597 /* Locate the Unicast table entry */
1598 last_nibble
= (0xf & last_nibble
);
1600 /* offset from unicast tbl base */
1601 tbl_offset
= (last_nibble
/ 4) * 4;
1603 /* offset within the above reg */
1604 reg_offset
= last_nibble
% 4;
1606 unicast_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
));
1609 /* Clear accepts frame bit at specified unicast DA tbl entry */
1610 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1612 unicast_reg
&= ~(0xff << (8 * reg_offset
));
1613 unicast_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1616 mvreg_write(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
), unicast_reg
);
1619 /* Set mac address */
1620 static void mvneta_mac_addr_set(struct mvneta_port
*pp
, unsigned char *addr
,
1627 mac_l
= (addr
[4] << 8) | (addr
[5]);
1628 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) |
1629 (addr
[2] << 8) | (addr
[3] << 0);
1631 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, mac_l
);
1632 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, mac_h
);
1635 /* Accept frames of this address */
1636 mvneta_set_ucast_addr(pp
, addr
[5], queue
);
1639 /* Set the number of packets that will be received before RX interrupt
1640 * will be generated by HW.
1642 static void mvneta_rx_pkts_coal_set(struct mvneta_port
*pp
,
1643 struct mvneta_rx_queue
*rxq
, u32 value
)
1645 mvreg_write(pp
, MVNETA_RXQ_THRESHOLD_REG(rxq
->id
),
1646 value
| MVNETA_RXQ_NON_OCCUPIED(0));
1649 /* Set the time delay in usec before RX interrupt will be generated by
1652 static void mvneta_rx_time_coal_set(struct mvneta_port
*pp
,
1653 struct mvneta_rx_queue
*rxq
, u32 value
)
1656 unsigned long clk_rate
;
1658 clk_rate
= clk_get_rate(pp
->clk
);
1659 val
= (clk_rate
/ 1000000) * value
;
1661 mvreg_write(pp
, MVNETA_RXQ_TIME_COAL_REG(rxq
->id
), val
);
1664 /* Set threshold for TX_DONE pkts coalescing */
1665 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port
*pp
,
1666 struct mvneta_tx_queue
*txq
, u32 value
)
1670 val
= mvreg_read(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
));
1672 val
&= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK
;
1673 val
|= MVNETA_TXQ_SENT_THRESH_MASK(value
);
1675 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), val
);
1678 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1679 static void mvneta_rx_desc_fill(struct mvneta_rx_desc
*rx_desc
,
1680 u32 phys_addr
, void *virt_addr
,
1681 struct mvneta_rx_queue
*rxq
)
1685 rx_desc
->buf_phys_addr
= phys_addr
;
1686 i
= rx_desc
- rxq
->descs
;
1687 rxq
->buf_virt_addr
[i
] = virt_addr
;
1690 /* Decrement sent descriptors counter */
1691 static void mvneta_txq_sent_desc_dec(struct mvneta_port
*pp
,
1692 struct mvneta_tx_queue
*txq
,
1697 /* Only 255 TX descriptors can be updated at once */
1698 while (sent_desc
> 0xff) {
1699 val
= 0xff << MVNETA_TXQ_DEC_SENT_SHIFT
;
1700 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1701 sent_desc
= sent_desc
- 0xff;
1704 val
= sent_desc
<< MVNETA_TXQ_DEC_SENT_SHIFT
;
1705 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1708 /* Get number of TX descriptors already sent by HW */
1709 static int mvneta_txq_sent_desc_num_get(struct mvneta_port
*pp
,
1710 struct mvneta_tx_queue
*txq
)
1715 val
= mvreg_read(pp
, MVNETA_TXQ_STATUS_REG(txq
->id
));
1716 sent_desc
= (val
& MVNETA_TXQ_SENT_DESC_MASK
) >>
1717 MVNETA_TXQ_SENT_DESC_SHIFT
;
1722 /* Get number of sent descriptors and decrement counter.
1723 * The number of sent descriptors is returned.
1725 static int mvneta_txq_sent_desc_proc(struct mvneta_port
*pp
,
1726 struct mvneta_tx_queue
*txq
)
1730 /* Get number of sent descriptors */
1731 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1733 /* Decrement sent descriptors counter */
1735 mvneta_txq_sent_desc_dec(pp
, txq
, sent_desc
);
1740 /* Set TXQ descriptors fields relevant for CSUM calculation */
1741 static u32
mvneta_txq_desc_csum(int l3_offs
, int l3_proto
,
1742 int ip_hdr_len
, int l4_proto
)
1746 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1747 * G_L4_chk, L4_type; required only for checksum
1750 command
= l3_offs
<< MVNETA_TX_L3_OFF_SHIFT
;
1751 command
|= ip_hdr_len
<< MVNETA_TX_IP_HLEN_SHIFT
;
1753 if (l3_proto
== htons(ETH_P_IP
))
1754 command
|= MVNETA_TXD_IP_CSUM
;
1756 command
|= MVNETA_TX_L3_IP6
;
1758 if (l4_proto
== IPPROTO_TCP
)
1759 command
|= MVNETA_TX_L4_CSUM_FULL
;
1760 else if (l4_proto
== IPPROTO_UDP
)
1761 command
|= MVNETA_TX_L4_UDP
| MVNETA_TX_L4_CSUM_FULL
;
1763 command
|= MVNETA_TX_L4_CSUM_NOT
;
1769 /* Display more error info */
1770 static void mvneta_rx_error(struct mvneta_port
*pp
,
1771 struct mvneta_rx_desc
*rx_desc
)
1773 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
1774 u32 status
= rx_desc
->status
;
1776 /* update per-cpu counter */
1777 u64_stats_update_begin(&stats
->syncp
);
1779 u64_stats_update_end(&stats
->syncp
);
1781 switch (status
& MVNETA_RXD_ERR_CODE_MASK
) {
1782 case MVNETA_RXD_ERR_CRC
:
1783 netdev_err(pp
->dev
, "bad rx status %08x (crc error), size=%d\n",
1784 status
, rx_desc
->data_size
);
1786 case MVNETA_RXD_ERR_OVERRUN
:
1787 netdev_err(pp
->dev
, "bad rx status %08x (overrun error), size=%d\n",
1788 status
, rx_desc
->data_size
);
1790 case MVNETA_RXD_ERR_LEN
:
1791 netdev_err(pp
->dev
, "bad rx status %08x (max frame length error), size=%d\n",
1792 status
, rx_desc
->data_size
);
1794 case MVNETA_RXD_ERR_RESOURCE
:
1795 netdev_err(pp
->dev
, "bad rx status %08x (resource error), size=%d\n",
1796 status
, rx_desc
->data_size
);
1801 /* Handle RX checksum offload based on the descriptor's status */
1802 static void mvneta_rx_csum(struct mvneta_port
*pp
, u32 status
,
1803 struct sk_buff
*skb
)
1805 if ((pp
->dev
->features
& NETIF_F_RXCSUM
) &&
1806 (status
& MVNETA_RXD_L3_IP4
) &&
1807 (status
& MVNETA_RXD_L4_CSUM_OK
)) {
1809 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1813 skb
->ip_summed
= CHECKSUM_NONE
;
1816 /* Return tx queue pointer (find last set bit) according to <cause> returned
1817 * form tx_done reg. <cause> must not be null. The return value is always a
1818 * valid queue for matching the first one found in <cause>.
1820 static struct mvneta_tx_queue
*mvneta_tx_done_policy(struct mvneta_port
*pp
,
1823 int queue
= fls(cause
) - 1;
1825 return &pp
->txqs
[queue
];
1828 /* Free tx queue skbuffs */
1829 static void mvneta_txq_bufs_free(struct mvneta_port
*pp
,
1830 struct mvneta_tx_queue
*txq
, int num
,
1831 struct netdev_queue
*nq
)
1833 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1836 for (i
= 0; i
< num
; i
++) {
1837 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_get_index
];
1838 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+
1841 mvneta_txq_inc_get(txq
);
1843 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
) &&
1844 buf
->type
!= MVNETA_TYPE_XDP_TX
)
1845 dma_unmap_single(pp
->dev
->dev
.parent
,
1846 tx_desc
->buf_phys_addr
,
1847 tx_desc
->data_size
, DMA_TO_DEVICE
);
1848 if (buf
->type
== MVNETA_TYPE_SKB
&& buf
->skb
) {
1849 bytes_compl
+= buf
->skb
->len
;
1851 dev_kfree_skb_any(buf
->skb
);
1852 } else if (buf
->type
== MVNETA_TYPE_XDP_TX
||
1853 buf
->type
== MVNETA_TYPE_XDP_NDO
) {
1854 xdp_return_frame(buf
->xdpf
);
1858 netdev_tx_completed_queue(nq
, pkts_compl
, bytes_compl
);
1861 /* Handle end of transmission */
1862 static void mvneta_txq_done(struct mvneta_port
*pp
,
1863 struct mvneta_tx_queue
*txq
)
1865 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1868 tx_done
= mvneta_txq_sent_desc_proc(pp
, txq
);
1872 mvneta_txq_bufs_free(pp
, txq
, tx_done
, nq
);
1874 txq
->count
-= tx_done
;
1876 if (netif_tx_queue_stopped(nq
)) {
1877 if (txq
->count
<= txq
->tx_wake_threshold
)
1878 netif_tx_wake_queue(nq
);
1882 /* Refill processing for SW buffer management */
1883 /* Allocate page per descriptor */
1884 static int mvneta_rx_refill(struct mvneta_port
*pp
,
1885 struct mvneta_rx_desc
*rx_desc
,
1886 struct mvneta_rx_queue
*rxq
,
1889 dma_addr_t phys_addr
;
1892 page
= page_pool_alloc_pages(rxq
->page_pool
,
1893 gfp_mask
| __GFP_NOWARN
);
1897 phys_addr
= page_pool_get_dma_addr(page
) + pp
->rx_offset_correction
;
1898 mvneta_rx_desc_fill(rx_desc
, phys_addr
, page
, rxq
);
1903 /* Handle tx checksum */
1904 static u32
mvneta_skb_tx_csum(struct mvneta_port
*pp
, struct sk_buff
*skb
)
1906 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1908 __be16 l3_proto
= vlan_get_protocol(skb
);
1911 if (l3_proto
== htons(ETH_P_IP
)) {
1912 struct iphdr
*ip4h
= ip_hdr(skb
);
1914 /* Calculate IPv4 checksum and L4 checksum */
1915 ip_hdr_len
= ip4h
->ihl
;
1916 l4_proto
= ip4h
->protocol
;
1917 } else if (l3_proto
== htons(ETH_P_IPV6
)) {
1918 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1920 /* Read l4_protocol from one of IPv6 extra headers */
1921 if (skb_network_header_len(skb
) > 0)
1922 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
1923 l4_proto
= ip6h
->nexthdr
;
1925 return MVNETA_TX_L4_CSUM_NOT
;
1927 return mvneta_txq_desc_csum(skb_network_offset(skb
),
1928 l3_proto
, ip_hdr_len
, l4_proto
);
1931 return MVNETA_TX_L4_CSUM_NOT
;
1934 /* Drop packets received by the RXQ and free buffers */
1935 static void mvneta_rxq_drop_pkts(struct mvneta_port
*pp
,
1936 struct mvneta_rx_queue
*rxq
)
1940 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1942 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1945 for (i
= 0; i
< rx_done
; i
++) {
1946 struct mvneta_rx_desc
*rx_desc
=
1947 mvneta_rxq_next_desc_get(rxq
);
1948 u8 pool_id
= MVNETA_RX_GET_BM_POOL_ID(rx_desc
);
1949 struct mvneta_bm_pool
*bm_pool
;
1951 bm_pool
= &pp
->bm_priv
->bm_pools
[pool_id
];
1952 /* Return dropped buffer to the pool */
1953 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
1954 rx_desc
->buf_phys_addr
);
1959 for (i
= 0; i
< rxq
->size
; i
++) {
1960 struct mvneta_rx_desc
*rx_desc
= rxq
->descs
+ i
;
1961 void *data
= rxq
->buf_virt_addr
[i
];
1962 if (!data
|| !(rx_desc
->buf_phys_addr
))
1965 page_pool_put_full_page(rxq
->page_pool
, data
, false);
1967 if (xdp_rxq_info_is_reg(&rxq
->xdp_rxq
))
1968 xdp_rxq_info_unreg(&rxq
->xdp_rxq
);
1969 page_pool_destroy(rxq
->page_pool
);
1970 rxq
->page_pool
= NULL
;
1974 mvneta_update_stats(struct mvneta_port
*pp
,
1975 struct mvneta_stats
*ps
)
1977 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
1979 u64_stats_update_begin(&stats
->syncp
);
1980 stats
->es
.ps
.rx_packets
+= ps
->rx_packets
;
1981 stats
->es
.ps
.rx_bytes
+= ps
->rx_bytes
;
1983 stats
->es
.ps
.xdp_redirect
+= ps
->xdp_redirect
;
1984 stats
->es
.ps
.xdp_pass
+= ps
->xdp_pass
;
1985 stats
->es
.ps
.xdp_drop
+= ps
->xdp_drop
;
1986 u64_stats_update_end(&stats
->syncp
);
1990 int mvneta_rx_refill_queue(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
)
1992 struct mvneta_rx_desc
*rx_desc
;
1993 int curr_desc
= rxq
->first_to_refill
;
1996 for (i
= 0; (i
< rxq
->refill_num
) && (i
< 64); i
++) {
1997 rx_desc
= rxq
->descs
+ curr_desc
;
1998 if (!(rx_desc
->buf_phys_addr
)) {
1999 if (mvneta_rx_refill(pp
, rx_desc
, rxq
, GFP_ATOMIC
)) {
2000 struct mvneta_pcpu_stats
*stats
;
2002 pr_err("Can't refill queue %d. Done %d from %d\n",
2003 rxq
->id
, i
, rxq
->refill_num
);
2005 stats
= this_cpu_ptr(pp
->stats
);
2006 u64_stats_update_begin(&stats
->syncp
);
2007 stats
->es
.refill_error
++;
2008 u64_stats_update_end(&stats
->syncp
);
2012 curr_desc
= MVNETA_QUEUE_NEXT_DESC(rxq
, curr_desc
);
2014 rxq
->refill_num
-= i
;
2015 rxq
->first_to_refill
= curr_desc
;
2021 mvneta_xdp_submit_frame(struct mvneta_port
*pp
, struct mvneta_tx_queue
*txq
,
2022 struct xdp_frame
*xdpf
, bool dma_map
)
2024 struct mvneta_tx_desc
*tx_desc
;
2025 struct mvneta_tx_buf
*buf
;
2026 dma_addr_t dma_addr
;
2028 if (txq
->count
>= txq
->tx_stop_threshold
)
2029 return MVNETA_XDP_DROPPED
;
2031 tx_desc
= mvneta_txq_next_desc_get(txq
);
2033 buf
= &txq
->buf
[txq
->txq_put_index
];
2036 dma_addr
= dma_map_single(pp
->dev
->dev
.parent
, xdpf
->data
,
2037 xdpf
->len
, DMA_TO_DEVICE
);
2038 if (dma_mapping_error(pp
->dev
->dev
.parent
, dma_addr
)) {
2039 mvneta_txq_desc_put(txq
);
2040 return MVNETA_XDP_DROPPED
;
2042 buf
->type
= MVNETA_TYPE_XDP_NDO
;
2044 struct page
*page
= virt_to_page(xdpf
->data
);
2046 dma_addr
= page_pool_get_dma_addr(page
) +
2047 sizeof(*xdpf
) + xdpf
->headroom
;
2048 dma_sync_single_for_device(pp
->dev
->dev
.parent
, dma_addr
,
2049 xdpf
->len
, DMA_BIDIRECTIONAL
);
2050 buf
->type
= MVNETA_TYPE_XDP_TX
;
2054 tx_desc
->command
= MVNETA_TXD_FLZ_DESC
;
2055 tx_desc
->buf_phys_addr
= dma_addr
;
2056 tx_desc
->data_size
= xdpf
->len
;
2058 mvneta_txq_inc_put(txq
);
2062 return MVNETA_XDP_TX
;
2066 mvneta_xdp_xmit_back(struct mvneta_port
*pp
, struct xdp_buff
*xdp
)
2068 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2069 struct mvneta_tx_queue
*txq
;
2070 struct netdev_queue
*nq
;
2071 struct xdp_frame
*xdpf
;
2075 xdpf
= convert_to_xdp_frame(xdp
);
2076 if (unlikely(!xdpf
))
2077 return MVNETA_XDP_DROPPED
;
2079 cpu
= smp_processor_id();
2080 txq
= &pp
->txqs
[cpu
% txq_number
];
2081 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2083 __netif_tx_lock(nq
, cpu
);
2084 ret
= mvneta_xdp_submit_frame(pp
, txq
, xdpf
, false);
2085 if (ret
== MVNETA_XDP_TX
) {
2086 u64_stats_update_begin(&stats
->syncp
);
2087 stats
->es
.ps
.tx_bytes
+= xdpf
->len
;
2088 stats
->es
.ps
.tx_packets
++;
2089 stats
->es
.ps
.xdp_tx
++;
2090 u64_stats_update_end(&stats
->syncp
);
2092 mvneta_txq_pend_desc_add(pp
, txq
, 0);
2094 u64_stats_update_begin(&stats
->syncp
);
2095 stats
->es
.ps
.xdp_tx_err
++;
2096 u64_stats_update_end(&stats
->syncp
);
2098 __netif_tx_unlock(nq
);
2104 mvneta_xdp_xmit(struct net_device
*dev
, int num_frame
,
2105 struct xdp_frame
**frames
, u32 flags
)
2107 struct mvneta_port
*pp
= netdev_priv(dev
);
2108 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2109 int i
, nxmit_byte
= 0, nxmit
= num_frame
;
2110 int cpu
= smp_processor_id();
2111 struct mvneta_tx_queue
*txq
;
2112 struct netdev_queue
*nq
;
2115 if (unlikely(flags
& ~XDP_XMIT_FLAGS_MASK
))
2118 txq
= &pp
->txqs
[cpu
% txq_number
];
2119 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2121 __netif_tx_lock(nq
, cpu
);
2122 for (i
= 0; i
< num_frame
; i
++) {
2123 ret
= mvneta_xdp_submit_frame(pp
, txq
, frames
[i
], true);
2124 if (ret
== MVNETA_XDP_TX
) {
2125 nxmit_byte
+= frames
[i
]->len
;
2127 xdp_return_frame_rx_napi(frames
[i
]);
2132 if (unlikely(flags
& XDP_XMIT_FLUSH
))
2133 mvneta_txq_pend_desc_add(pp
, txq
, 0);
2134 __netif_tx_unlock(nq
);
2136 u64_stats_update_begin(&stats
->syncp
);
2137 stats
->es
.ps
.tx_bytes
+= nxmit_byte
;
2138 stats
->es
.ps
.tx_packets
+= nxmit
;
2139 stats
->es
.ps
.xdp_xmit
+= nxmit
;
2140 stats
->es
.ps
.xdp_xmit_err
+= num_frame
- nxmit
;
2141 u64_stats_update_end(&stats
->syncp
);
2147 mvneta_run_xdp(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
2148 struct bpf_prog
*prog
, struct xdp_buff
*xdp
,
2149 struct mvneta_stats
*stats
)
2151 unsigned int len
, sync
;
2155 len
= xdp
->data_end
- xdp
->data_hard_start
- pp
->rx_offset_correction
;
2156 act
= bpf_prog_run_xdp(prog
, xdp
);
2158 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
2159 sync
= xdp
->data_end
- xdp
->data_hard_start
- pp
->rx_offset_correction
;
2160 sync
= max(sync
, len
);
2165 return MVNETA_XDP_PASS
;
2166 case XDP_REDIRECT
: {
2169 err
= xdp_do_redirect(pp
->dev
, xdp
, prog
);
2170 if (unlikely(err
)) {
2171 ret
= MVNETA_XDP_DROPPED
;
2172 page
= virt_to_head_page(xdp
->data
);
2173 page_pool_put_page(rxq
->page_pool
, page
, sync
, true);
2175 ret
= MVNETA_XDP_REDIR
;
2176 stats
->xdp_redirect
++;
2181 ret
= mvneta_xdp_xmit_back(pp
, xdp
);
2182 if (ret
!= MVNETA_XDP_TX
) {
2183 page
= virt_to_head_page(xdp
->data
);
2184 page_pool_put_page(rxq
->page_pool
, page
, sync
, true);
2188 bpf_warn_invalid_xdp_action(act
);
2191 trace_xdp_exception(pp
->dev
, prog
, act
);
2194 page
= virt_to_head_page(xdp
->data
);
2195 page_pool_put_page(rxq
->page_pool
, page
, sync
, true);
2196 ret
= MVNETA_XDP_DROPPED
;
2201 stats
->rx_bytes
+= xdp
->data_end
- xdp
->data
;
2202 stats
->rx_packets
++;
2208 mvneta_swbm_rx_frame(struct mvneta_port
*pp
,
2209 struct mvneta_rx_desc
*rx_desc
,
2210 struct mvneta_rx_queue
*rxq
,
2211 struct xdp_buff
*xdp
,
2212 struct bpf_prog
*xdp_prog
,
2214 struct mvneta_stats
*stats
)
2216 unsigned char *data
= page_address(page
);
2217 int data_len
= -MVNETA_MH_SIZE
, len
;
2218 struct net_device
*dev
= pp
->dev
;
2219 enum dma_data_direction dma_dir
;
2222 if (MVNETA_SKB_SIZE(rx_desc
->data_size
) > PAGE_SIZE
) {
2223 len
= MVNETA_MAX_RX_BUF_SIZE
;
2226 len
= rx_desc
->data_size
;
2227 data_len
+= len
- ETH_FCS_LEN
;
2230 dma_dir
= page_pool_get_dma_dir(rxq
->page_pool
);
2231 dma_sync_single_for_cpu(dev
->dev
.parent
,
2232 rx_desc
->buf_phys_addr
,
2235 /* Prefetch header */
2238 xdp
->data_hard_start
= data
;
2239 xdp
->data
= data
+ pp
->rx_offset_correction
+ MVNETA_MH_SIZE
;
2240 xdp
->data_end
= xdp
->data
+ data_len
;
2241 xdp_set_data_meta_invalid(xdp
);
2244 ret
= mvneta_run_xdp(pp
, rxq
, xdp_prog
, xdp
, stats
);
2249 rxq
->skb
= build_skb(xdp
->data_hard_start
, PAGE_SIZE
);
2250 if (unlikely(!rxq
->skb
)) {
2251 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2253 netdev_err(dev
, "Can't allocate skb on queue %d\n", rxq
->id
);
2255 u64_stats_update_begin(&stats
->syncp
);
2256 stats
->es
.skb_alloc_error
++;
2257 stats
->rx_dropped
++;
2258 u64_stats_update_end(&stats
->syncp
);
2262 page_pool_release_page(rxq
->page_pool
, page
);
2264 skb_reserve(rxq
->skb
,
2265 xdp
->data
- xdp
->data_hard_start
);
2266 skb_put(rxq
->skb
, xdp
->data_end
- xdp
->data
);
2267 mvneta_rx_csum(pp
, rx_desc
->status
, rxq
->skb
);
2269 rxq
->left_size
= rx_desc
->data_size
- len
;
2272 rx_desc
->buf_phys_addr
= 0;
2278 mvneta_swbm_add_rx_fragment(struct mvneta_port
*pp
,
2279 struct mvneta_rx_desc
*rx_desc
,
2280 struct mvneta_rx_queue
*rxq
,
2283 struct net_device
*dev
= pp
->dev
;
2284 enum dma_data_direction dma_dir
;
2287 if (rxq
->left_size
> MVNETA_MAX_RX_BUF_SIZE
) {
2288 len
= MVNETA_MAX_RX_BUF_SIZE
;
2291 len
= rxq
->left_size
;
2292 data_len
= len
- ETH_FCS_LEN
;
2294 dma_dir
= page_pool_get_dma_dir(rxq
->page_pool
);
2295 dma_sync_single_for_cpu(dev
->dev
.parent
,
2296 rx_desc
->buf_phys_addr
,
2299 /* refill descriptor with new buffer later */
2300 skb_add_rx_frag(rxq
->skb
,
2301 skb_shinfo(rxq
->skb
)->nr_frags
,
2302 page
, pp
->rx_offset_correction
, data_len
,
2305 page_pool_release_page(rxq
->page_pool
, page
);
2306 rx_desc
->buf_phys_addr
= 0;
2307 rxq
->left_size
-= len
;
2310 /* Main rx processing when using software buffer management */
2311 static int mvneta_rx_swbm(struct napi_struct
*napi
,
2312 struct mvneta_port
*pp
, int budget
,
2313 struct mvneta_rx_queue
*rxq
)
2315 int rx_proc
= 0, rx_todo
, refill
;
2316 struct net_device
*dev
= pp
->dev
;
2317 struct mvneta_stats ps
= {};
2318 struct bpf_prog
*xdp_prog
;
2319 struct xdp_buff xdp_buf
;
2321 /* Get number of received packets */
2322 rx_todo
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
2325 xdp_prog
= READ_ONCE(pp
->xdp_prog
);
2326 xdp_buf
.rxq
= &rxq
->xdp_rxq
;
2327 xdp_buf
.frame_sz
= PAGE_SIZE
;
2329 /* Fairness NAPI loop */
2330 while (rx_proc
< budget
&& rx_proc
< rx_todo
) {
2331 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
2332 u32 rx_status
, index
;
2335 index
= rx_desc
- rxq
->descs
;
2336 page
= (struct page
*)rxq
->buf_virt_addr
[index
];
2338 rx_status
= rx_desc
->status
;
2342 if (rx_status
& MVNETA_RXD_FIRST_DESC
) {
2345 /* Check errors only for FIRST descriptor */
2346 if (rx_status
& MVNETA_RXD_ERR_SUMMARY
) {
2347 mvneta_rx_error(pp
, rx_desc
);
2348 /* leave the descriptor untouched */
2352 err
= mvneta_swbm_rx_frame(pp
, rx_desc
, rxq
, &xdp_buf
,
2353 xdp_prog
, page
, &ps
);
2357 if (unlikely(!rxq
->skb
)) {
2358 pr_debug("no skb for rx_status 0x%x\n",
2362 mvneta_swbm_add_rx_fragment(pp
, rx_desc
, rxq
, page
);
2363 } /* Middle or Last descriptor */
2365 if (!(rx_status
& MVNETA_RXD_LAST_DESC
))
2366 /* no last descriptor this time */
2369 if (rxq
->left_size
) {
2370 pr_err("get last desc, but left_size (%d) != 0\n",
2372 dev_kfree_skb_any(rxq
->skb
);
2378 ps
.rx_bytes
+= rxq
->skb
->len
;
2381 /* Linux processing */
2382 rxq
->skb
->protocol
= eth_type_trans(rxq
->skb
, dev
);
2384 napi_gro_receive(napi
, rxq
->skb
);
2386 /* clean uncomplete skb pointer in queue */
2391 if (ps
.xdp_redirect
)
2395 mvneta_update_stats(pp
, &ps
);
2397 /* return some buffers to hardware queue, one at a time is too slow */
2398 refill
= mvneta_rx_refill_queue(pp
, rxq
);
2400 /* Update rxq management counters */
2401 mvneta_rxq_desc_num_update(pp
, rxq
, rx_proc
, refill
);
2403 return ps
.rx_packets
;
2406 /* Main rx processing when using hardware buffer management */
2407 static int mvneta_rx_hwbm(struct napi_struct
*napi
,
2408 struct mvneta_port
*pp
, int rx_todo
,
2409 struct mvneta_rx_queue
*rxq
)
2411 struct net_device
*dev
= pp
->dev
;
2416 /* Get number of received packets */
2417 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
2419 if (rx_todo
> rx_done
)
2424 /* Fairness NAPI loop */
2425 while (rx_done
< rx_todo
) {
2426 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
2427 struct mvneta_bm_pool
*bm_pool
= NULL
;
2428 struct sk_buff
*skb
;
2429 unsigned char *data
;
2430 dma_addr_t phys_addr
;
2431 u32 rx_status
, frag_size
;
2436 rx_status
= rx_desc
->status
;
2437 rx_bytes
= rx_desc
->data_size
- (ETH_FCS_LEN
+ MVNETA_MH_SIZE
);
2438 data
= (u8
*)(uintptr_t)rx_desc
->buf_cookie
;
2439 phys_addr
= rx_desc
->buf_phys_addr
;
2440 pool_id
= MVNETA_RX_GET_BM_POOL_ID(rx_desc
);
2441 bm_pool
= &pp
->bm_priv
->bm_pools
[pool_id
];
2443 if (!mvneta_rxq_desc_is_first_last(rx_status
) ||
2444 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
2445 err_drop_frame_ret_pool
:
2446 /* Return the buffer to the pool */
2447 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
2448 rx_desc
->buf_phys_addr
);
2450 mvneta_rx_error(pp
, rx_desc
);
2451 /* leave the descriptor untouched */
2455 if (rx_bytes
<= rx_copybreak
) {
2456 /* better copy a small frame and not unmap the DMA region */
2457 skb
= netdev_alloc_skb_ip_align(dev
, rx_bytes
);
2459 goto err_drop_frame_ret_pool
;
2461 dma_sync_single_range_for_cpu(&pp
->bm_priv
->pdev
->dev
,
2462 rx_desc
->buf_phys_addr
,
2463 MVNETA_MH_SIZE
+ NET_SKB_PAD
,
2466 skb_put_data(skb
, data
+ MVNETA_MH_SIZE
+ NET_SKB_PAD
,
2469 skb
->protocol
= eth_type_trans(skb
, dev
);
2470 mvneta_rx_csum(pp
, rx_status
, skb
);
2471 napi_gro_receive(napi
, skb
);
2474 rcvd_bytes
+= rx_bytes
;
2476 /* Return the buffer to the pool */
2477 mvneta_bm_pool_put_bp(pp
->bm_priv
, bm_pool
,
2478 rx_desc
->buf_phys_addr
);
2480 /* leave the descriptor and buffer untouched */
2484 /* Refill processing */
2485 err
= hwbm_pool_refill(&bm_pool
->hwbm_pool
, GFP_ATOMIC
);
2487 struct mvneta_pcpu_stats
*stats
;
2489 netdev_err(dev
, "Linux processing - Can't refill\n");
2491 stats
= this_cpu_ptr(pp
->stats
);
2492 u64_stats_update_begin(&stats
->syncp
);
2493 stats
->es
.refill_error
++;
2494 u64_stats_update_end(&stats
->syncp
);
2496 goto err_drop_frame_ret_pool
;
2499 frag_size
= bm_pool
->hwbm_pool
.frag_size
;
2501 skb
= build_skb(data
, frag_size
> PAGE_SIZE
? 0 : frag_size
);
2503 /* After refill old buffer has to be unmapped regardless
2504 * the skb is successfully built or not.
2506 dma_unmap_single(&pp
->bm_priv
->pdev
->dev
, phys_addr
,
2507 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
2509 goto err_drop_frame
;
2512 rcvd_bytes
+= rx_bytes
;
2514 /* Linux processing */
2515 skb_reserve(skb
, MVNETA_MH_SIZE
+ NET_SKB_PAD
);
2516 skb_put(skb
, rx_bytes
);
2518 skb
->protocol
= eth_type_trans(skb
, dev
);
2520 mvneta_rx_csum(pp
, rx_status
, skb
);
2522 napi_gro_receive(napi
, skb
);
2526 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2528 u64_stats_update_begin(&stats
->syncp
);
2529 stats
->es
.ps
.rx_packets
+= rcvd_pkts
;
2530 stats
->es
.ps
.rx_bytes
+= rcvd_bytes
;
2531 u64_stats_update_end(&stats
->syncp
);
2534 /* Update rxq management counters */
2535 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
2541 mvneta_tso_put_hdr(struct sk_buff
*skb
,
2542 struct mvneta_port
*pp
, struct mvneta_tx_queue
*txq
)
2544 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2545 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2546 struct mvneta_tx_desc
*tx_desc
;
2548 tx_desc
= mvneta_txq_next_desc_get(txq
);
2549 tx_desc
->data_size
= hdr_len
;
2550 tx_desc
->command
= mvneta_skb_tx_csum(pp
, skb
);
2551 tx_desc
->command
|= MVNETA_TXD_F_DESC
;
2552 tx_desc
->buf_phys_addr
= txq
->tso_hdrs_phys
+
2553 txq
->txq_put_index
* TSO_HEADER_SIZE
;
2554 buf
->type
= MVNETA_TYPE_SKB
;
2557 mvneta_txq_inc_put(txq
);
2561 mvneta_tso_put_data(struct net_device
*dev
, struct mvneta_tx_queue
*txq
,
2562 struct sk_buff
*skb
, char *data
, int size
,
2563 bool last_tcp
, bool is_last
)
2565 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2566 struct mvneta_tx_desc
*tx_desc
;
2568 tx_desc
= mvneta_txq_next_desc_get(txq
);
2569 tx_desc
->data_size
= size
;
2570 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, data
,
2571 size
, DMA_TO_DEVICE
);
2572 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
2573 tx_desc
->buf_phys_addr
))) {
2574 mvneta_txq_desc_put(txq
);
2578 tx_desc
->command
= 0;
2579 buf
->type
= MVNETA_TYPE_SKB
;
2583 /* last descriptor in the TCP packet */
2584 tx_desc
->command
= MVNETA_TXD_L_DESC
;
2586 /* last descriptor in SKB */
2590 mvneta_txq_inc_put(txq
);
2594 static int mvneta_tx_tso(struct sk_buff
*skb
, struct net_device
*dev
,
2595 struct mvneta_tx_queue
*txq
)
2597 int total_len
, data_left
;
2599 struct mvneta_port
*pp
= netdev_priv(dev
);
2601 int hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
2604 /* Count needed descriptors */
2605 if ((txq
->count
+ tso_count_descs(skb
)) >= txq
->size
)
2608 if (skb_headlen(skb
) < (skb_transport_offset(skb
) + tcp_hdrlen(skb
))) {
2609 pr_info("*** Is this even possible???!?!?\n");
2613 /* Initialize the TSO handler, and prepare the first payload */
2614 tso_start(skb
, &tso
);
2616 total_len
= skb
->len
- hdr_len
;
2617 while (total_len
> 0) {
2620 data_left
= min_t(int, skb_shinfo(skb
)->gso_size
, total_len
);
2621 total_len
-= data_left
;
2624 /* prepare packet headers: MAC + IP + TCP */
2625 hdr
= txq
->tso_hdrs
+ txq
->txq_put_index
* TSO_HEADER_SIZE
;
2626 tso_build_hdr(skb
, hdr
, &tso
, data_left
, total_len
== 0);
2628 mvneta_tso_put_hdr(skb
, pp
, txq
);
2630 while (data_left
> 0) {
2634 size
= min_t(int, tso
.size
, data_left
);
2636 if (mvneta_tso_put_data(dev
, txq
, skb
,
2643 tso_build_data(skb
, &tso
, size
);
2650 /* Release all used data descriptors; header descriptors must not
2653 for (i
= desc_count
- 1; i
>= 0; i
--) {
2654 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+ i
;
2655 if (!IS_TSO_HEADER(txq
, tx_desc
->buf_phys_addr
))
2656 dma_unmap_single(pp
->dev
->dev
.parent
,
2657 tx_desc
->buf_phys_addr
,
2660 mvneta_txq_desc_put(txq
);
2665 /* Handle tx fragmentation processing */
2666 static int mvneta_tx_frag_process(struct mvneta_port
*pp
, struct sk_buff
*skb
,
2667 struct mvneta_tx_queue
*txq
)
2669 struct mvneta_tx_desc
*tx_desc
;
2670 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
2672 for (i
= 0; i
< nr_frags
; i
++) {
2673 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2674 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2675 void *addr
= skb_frag_address(frag
);
2677 tx_desc
= mvneta_txq_next_desc_get(txq
);
2678 tx_desc
->data_size
= skb_frag_size(frag
);
2680 tx_desc
->buf_phys_addr
=
2681 dma_map_single(pp
->dev
->dev
.parent
, addr
,
2682 tx_desc
->data_size
, DMA_TO_DEVICE
);
2684 if (dma_mapping_error(pp
->dev
->dev
.parent
,
2685 tx_desc
->buf_phys_addr
)) {
2686 mvneta_txq_desc_put(txq
);
2690 if (i
== nr_frags
- 1) {
2691 /* Last descriptor */
2692 tx_desc
->command
= MVNETA_TXD_L_DESC
| MVNETA_TXD_Z_PAD
;
2695 /* Descriptor in the middle: Not First, Not Last */
2696 tx_desc
->command
= 0;
2699 buf
->type
= MVNETA_TYPE_SKB
;
2700 mvneta_txq_inc_put(txq
);
2706 /* Release all descriptors that were used to map fragments of
2707 * this packet, as well as the corresponding DMA mappings
2709 for (i
= i
- 1; i
>= 0; i
--) {
2710 tx_desc
= txq
->descs
+ i
;
2711 dma_unmap_single(pp
->dev
->dev
.parent
,
2712 tx_desc
->buf_phys_addr
,
2715 mvneta_txq_desc_put(txq
);
2721 /* Main tx processing */
2722 static netdev_tx_t
mvneta_tx(struct sk_buff
*skb
, struct net_device
*dev
)
2724 struct mvneta_port
*pp
= netdev_priv(dev
);
2725 u16 txq_id
= skb_get_queue_mapping(skb
);
2726 struct mvneta_tx_queue
*txq
= &pp
->txqs
[txq_id
];
2727 struct mvneta_tx_buf
*buf
= &txq
->buf
[txq
->txq_put_index
];
2728 struct mvneta_tx_desc
*tx_desc
;
2733 if (!netif_running(dev
))
2736 if (skb_is_gso(skb
)) {
2737 frags
= mvneta_tx_tso(skb
, dev
, txq
);
2741 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
2743 /* Get a descriptor for the first part of the packet */
2744 tx_desc
= mvneta_txq_next_desc_get(txq
);
2746 tx_cmd
= mvneta_skb_tx_csum(pp
, skb
);
2748 tx_desc
->data_size
= skb_headlen(skb
);
2750 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
2753 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
2754 tx_desc
->buf_phys_addr
))) {
2755 mvneta_txq_desc_put(txq
);
2760 buf
->type
= MVNETA_TYPE_SKB
;
2762 /* First and Last descriptor */
2763 tx_cmd
|= MVNETA_TXD_FLZ_DESC
;
2764 tx_desc
->command
= tx_cmd
;
2766 mvneta_txq_inc_put(txq
);
2768 /* First but not Last */
2769 tx_cmd
|= MVNETA_TXD_F_DESC
;
2771 mvneta_txq_inc_put(txq
);
2772 tx_desc
->command
= tx_cmd
;
2773 /* Continue with other skb fragments */
2774 if (mvneta_tx_frag_process(pp
, skb
, txq
)) {
2775 dma_unmap_single(dev
->dev
.parent
,
2776 tx_desc
->buf_phys_addr
,
2779 mvneta_txq_desc_put(txq
);
2787 struct netdev_queue
*nq
= netdev_get_tx_queue(dev
, txq_id
);
2788 struct mvneta_pcpu_stats
*stats
= this_cpu_ptr(pp
->stats
);
2790 netdev_tx_sent_queue(nq
, len
);
2792 txq
->count
+= frags
;
2793 if (txq
->count
>= txq
->tx_stop_threshold
)
2794 netif_tx_stop_queue(nq
);
2796 if (!netdev_xmit_more() || netif_xmit_stopped(nq
) ||
2797 txq
->pending
+ frags
> MVNETA_TXQ_DEC_SENT_MASK
)
2798 mvneta_txq_pend_desc_add(pp
, txq
, frags
);
2800 txq
->pending
+= frags
;
2802 u64_stats_update_begin(&stats
->syncp
);
2803 stats
->es
.ps
.tx_bytes
+= len
;
2804 stats
->es
.ps
.tx_packets
++;
2805 u64_stats_update_end(&stats
->syncp
);
2807 dev
->stats
.tx_dropped
++;
2808 dev_kfree_skb_any(skb
);
2811 return NETDEV_TX_OK
;
2815 /* Free tx resources, when resetting a port */
2816 static void mvneta_txq_done_force(struct mvneta_port
*pp
,
2817 struct mvneta_tx_queue
*txq
)
2820 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2821 int tx_done
= txq
->count
;
2823 mvneta_txq_bufs_free(pp
, txq
, tx_done
, nq
);
2827 txq
->txq_put_index
= 0;
2828 txq
->txq_get_index
= 0;
2831 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2832 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2834 static void mvneta_tx_done_gbe(struct mvneta_port
*pp
, u32 cause_tx_done
)
2836 struct mvneta_tx_queue
*txq
;
2837 struct netdev_queue
*nq
;
2838 int cpu
= smp_processor_id();
2840 while (cause_tx_done
) {
2841 txq
= mvneta_tx_done_policy(pp
, cause_tx_done
);
2843 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
2844 __netif_tx_lock(nq
, cpu
);
2847 mvneta_txq_done(pp
, txq
);
2849 __netif_tx_unlock(nq
);
2850 cause_tx_done
&= ~((1 << txq
->id
));
2854 /* Compute crc8 of the specified address, using a unique algorithm ,
2855 * according to hw spec, different than generic crc8 algorithm
2857 static int mvneta_addr_crc(unsigned char *addr
)
2862 for (i
= 0; i
< ETH_ALEN
; i
++) {
2865 crc
= (crc
^ addr
[i
]) << 8;
2866 for (j
= 7; j
>= 0; j
--) {
2867 if (crc
& (0x100 << j
))
2875 /* This method controls the net device special MAC multicast support.
2876 * The Special Multicast Table for MAC addresses supports MAC of the form
2877 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2878 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2879 * Table entries in the DA-Filter table. This method set the Special
2880 * Multicast Table appropriate entry.
2882 static void mvneta_set_special_mcast_addr(struct mvneta_port
*pp
,
2883 unsigned char last_byte
,
2886 unsigned int smc_table_reg
;
2887 unsigned int tbl_offset
;
2888 unsigned int reg_offset
;
2890 /* Register offset from SMC table base */
2891 tbl_offset
= (last_byte
/ 4);
2892 /* Entry offset within the above reg */
2893 reg_offset
= last_byte
% 4;
2895 smc_table_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_SPEC_MCAST
2899 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
2901 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
2902 smc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
2905 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ tbl_offset
* 4,
2909 /* This method controls the network device Other MAC multicast support.
2910 * The Other Multicast Table is used for multicast of another type.
2911 * A CRC-8 is used as an index to the Other Multicast Table entries
2912 * in the DA-Filter table.
2913 * The method gets the CRC-8 value from the calling routine and
2914 * sets the Other Multicast Table appropriate entry according to the
2917 static void mvneta_set_other_mcast_addr(struct mvneta_port
*pp
,
2921 unsigned int omc_table_reg
;
2922 unsigned int tbl_offset
;
2923 unsigned int reg_offset
;
2925 tbl_offset
= (crc8
/ 4) * 4; /* Register offset from OMC table base */
2926 reg_offset
= crc8
% 4; /* Entry offset within the above reg */
2928 omc_table_reg
= mvreg_read(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
);
2931 /* Clear accepts frame bit at specified Other DA table entry */
2932 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
2934 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
2935 omc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
2938 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
, omc_table_reg
);
2941 /* The network device supports multicast using two tables:
2942 * 1) Special Multicast Table for MAC addresses of the form
2943 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2944 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2945 * Table entries in the DA-Filter table.
2946 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2947 * is used as an index to the Other Multicast Table entries in the
2950 static int mvneta_mcast_addr_set(struct mvneta_port
*pp
, unsigned char *p_addr
,
2953 unsigned char crc_result
= 0;
2955 if (memcmp(p_addr
, "\x01\x00\x5e\x00\x00", 5) == 0) {
2956 mvneta_set_special_mcast_addr(pp
, p_addr
[5], queue
);
2960 crc_result
= mvneta_addr_crc(p_addr
);
2962 if (pp
->mcast_count
[crc_result
] == 0) {
2963 netdev_info(pp
->dev
, "No valid Mcast for crc8=0x%02x\n",
2968 pp
->mcast_count
[crc_result
]--;
2969 if (pp
->mcast_count
[crc_result
] != 0) {
2970 netdev_info(pp
->dev
,
2971 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2972 pp
->mcast_count
[crc_result
], crc_result
);
2976 pp
->mcast_count
[crc_result
]++;
2978 mvneta_set_other_mcast_addr(pp
, crc_result
, queue
);
2983 /* Configure Fitering mode of Ethernet port */
2984 static void mvneta_rx_unicast_promisc_set(struct mvneta_port
*pp
,
2987 u32 port_cfg_reg
, val
;
2989 port_cfg_reg
= mvreg_read(pp
, MVNETA_PORT_CONFIG
);
2991 val
= mvreg_read(pp
, MVNETA_TYPE_PRIO
);
2993 /* Set / Clear UPM bit in port configuration register */
2995 /* Accept all Unicast addresses */
2996 port_cfg_reg
|= MVNETA_UNI_PROMISC_MODE
;
2997 val
|= MVNETA_FORCE_UNI
;
2998 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, 0xffff);
2999 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, 0xffffffff);
3001 /* Reject all Unicast addresses */
3002 port_cfg_reg
&= ~MVNETA_UNI_PROMISC_MODE
;
3003 val
&= ~MVNETA_FORCE_UNI
;
3006 mvreg_write(pp
, MVNETA_PORT_CONFIG
, port_cfg_reg
);
3007 mvreg_write(pp
, MVNETA_TYPE_PRIO
, val
);
3010 /* register unicast and multicast addresses */
3011 static void mvneta_set_rx_mode(struct net_device
*dev
)
3013 struct mvneta_port
*pp
= netdev_priv(dev
);
3014 struct netdev_hw_addr
*ha
;
3016 if (dev
->flags
& IFF_PROMISC
) {
3017 /* Accept all: Multicast + Unicast */
3018 mvneta_rx_unicast_promisc_set(pp
, 1);
3019 mvneta_set_ucast_table(pp
, pp
->rxq_def
);
3020 mvneta_set_special_mcast_table(pp
, pp
->rxq_def
);
3021 mvneta_set_other_mcast_table(pp
, pp
->rxq_def
);
3023 /* Accept single Unicast */
3024 mvneta_rx_unicast_promisc_set(pp
, 0);
3025 mvneta_set_ucast_table(pp
, -1);
3026 mvneta_mac_addr_set(pp
, dev
->dev_addr
, pp
->rxq_def
);
3028 if (dev
->flags
& IFF_ALLMULTI
) {
3029 /* Accept all multicast */
3030 mvneta_set_special_mcast_table(pp
, pp
->rxq_def
);
3031 mvneta_set_other_mcast_table(pp
, pp
->rxq_def
);
3033 /* Accept only initialized multicast */
3034 mvneta_set_special_mcast_table(pp
, -1);
3035 mvneta_set_other_mcast_table(pp
, -1);
3037 if (!netdev_mc_empty(dev
)) {
3038 netdev_for_each_mc_addr(ha
, dev
) {
3039 mvneta_mcast_addr_set(pp
, ha
->addr
,
3047 /* Interrupt handling - the callback for request_irq() */
3048 static irqreturn_t
mvneta_isr(int irq
, void *dev_id
)
3050 struct mvneta_port
*pp
= (struct mvneta_port
*)dev_id
;
3052 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
3053 napi_schedule(&pp
->napi
);
3058 /* Interrupt handling - the callback for request_percpu_irq() */
3059 static irqreturn_t
mvneta_percpu_isr(int irq
, void *dev_id
)
3061 struct mvneta_pcpu_port
*port
= (struct mvneta_pcpu_port
*)dev_id
;
3063 disable_percpu_irq(port
->pp
->dev
->irq
);
3064 napi_schedule(&port
->napi
);
3069 static void mvneta_link_change(struct mvneta_port
*pp
)
3071 u32 gmac_stat
= mvreg_read(pp
, MVNETA_GMAC_STATUS
);
3073 phylink_mac_change(pp
->phylink
, !!(gmac_stat
& MVNETA_GMAC_LINK_UP
));
3077 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
3078 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
3079 * Bits 8 -15 of the cause Rx Tx register indicate that are received
3080 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
3081 * Each CPU has its own causeRxTx register
3083 static int mvneta_poll(struct napi_struct
*napi
, int budget
)
3088 struct mvneta_port
*pp
= netdev_priv(napi
->dev
);
3089 struct mvneta_pcpu_port
*port
= this_cpu_ptr(pp
->ports
);
3091 if (!netif_running(pp
->dev
)) {
3092 napi_complete(napi
);
3096 /* Read cause register */
3097 cause_rx_tx
= mvreg_read(pp
, MVNETA_INTR_NEW_CAUSE
);
3098 if (cause_rx_tx
& MVNETA_MISCINTR_INTR_MASK
) {
3099 u32 cause_misc
= mvreg_read(pp
, MVNETA_INTR_MISC_CAUSE
);
3101 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
3103 if (cause_misc
& (MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3104 MVNETA_CAUSE_LINK_CHANGE
))
3105 mvneta_link_change(pp
);
3108 /* Release Tx descriptors */
3109 if (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
) {
3110 mvneta_tx_done_gbe(pp
, (cause_rx_tx
& MVNETA_TX_INTR_MASK_ALL
));
3111 cause_rx_tx
&= ~MVNETA_TX_INTR_MASK_ALL
;
3114 /* For the case where the last mvneta_poll did not process all
3117 cause_rx_tx
|= pp
->neta_armada3700
? pp
->cause_rx_tx
:
3120 rx_queue
= fls(((cause_rx_tx
>> 8) & 0xff));
3122 rx_queue
= rx_queue
- 1;
3124 rx_done
= mvneta_rx_hwbm(napi
, pp
, budget
,
3125 &pp
->rxqs
[rx_queue
]);
3127 rx_done
= mvneta_rx_swbm(napi
, pp
, budget
,
3128 &pp
->rxqs
[rx_queue
]);
3131 if (rx_done
< budget
) {
3133 napi_complete_done(napi
, rx_done
);
3135 if (pp
->neta_armada3700
) {
3136 unsigned long flags
;
3138 local_irq_save(flags
);
3139 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
3140 MVNETA_RX_INTR_MASK(rxq_number
) |
3141 MVNETA_TX_INTR_MASK(txq_number
) |
3142 MVNETA_MISCINTR_INTR_MASK
);
3143 local_irq_restore(flags
);
3145 enable_percpu_irq(pp
->dev
->irq
, 0);
3149 if (pp
->neta_armada3700
)
3150 pp
->cause_rx_tx
= cause_rx_tx
;
3152 port
->cause_rx_tx
= cause_rx_tx
;
3157 static int mvneta_create_page_pool(struct mvneta_port
*pp
,
3158 struct mvneta_rx_queue
*rxq
, int size
)
3160 struct bpf_prog
*xdp_prog
= READ_ONCE(pp
->xdp_prog
);
3161 struct page_pool_params pp_params
= {
3163 .flags
= PP_FLAG_DMA_MAP
| PP_FLAG_DMA_SYNC_DEV
,
3165 .nid
= NUMA_NO_NODE
,
3166 .dev
= pp
->dev
->dev
.parent
,
3167 .dma_dir
= xdp_prog
? DMA_BIDIRECTIONAL
: DMA_FROM_DEVICE
,
3168 .offset
= pp
->rx_offset_correction
,
3169 .max_len
= MVNETA_MAX_RX_BUF_SIZE
,
3173 rxq
->page_pool
= page_pool_create(&pp_params
);
3174 if (IS_ERR(rxq
->page_pool
)) {
3175 err
= PTR_ERR(rxq
->page_pool
);
3176 rxq
->page_pool
= NULL
;
3180 err
= xdp_rxq_info_reg(&rxq
->xdp_rxq
, pp
->dev
, rxq
->id
);
3184 err
= xdp_rxq_info_reg_mem_model(&rxq
->xdp_rxq
, MEM_TYPE_PAGE_POOL
,
3187 goto err_unregister_rxq
;
3192 xdp_rxq_info_unreg(&rxq
->xdp_rxq
);
3194 page_pool_destroy(rxq
->page_pool
);
3195 rxq
->page_pool
= NULL
;
3199 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
3200 static int mvneta_rxq_fill(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
3205 err
= mvneta_create_page_pool(pp
, rxq
, num
);
3209 for (i
= 0; i
< num
; i
++) {
3210 memset(rxq
->descs
+ i
, 0, sizeof(struct mvneta_rx_desc
));
3211 if (mvneta_rx_refill(pp
, rxq
->descs
+ i
, rxq
,
3214 "%s:rxq %d, %d of %d buffs filled\n",
3215 __func__
, rxq
->id
, i
, num
);
3220 /* Add this number of RX descriptors as non occupied (ready to
3223 mvneta_rxq_non_occup_desc_add(pp
, rxq
, i
);
3228 /* Free all packets pending transmit from all TXQs and reset TX port */
3229 static void mvneta_tx_reset(struct mvneta_port
*pp
)
3233 /* free the skb's in the tx ring */
3234 for (queue
= 0; queue
< txq_number
; queue
++)
3235 mvneta_txq_done_force(pp
, &pp
->txqs
[queue
]);
3237 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
3238 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
3241 static void mvneta_rx_reset(struct mvneta_port
*pp
)
3243 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
3244 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
3247 /* Rx/Tx queue initialization/cleanup methods */
3249 static int mvneta_rxq_sw_init(struct mvneta_port
*pp
,
3250 struct mvneta_rx_queue
*rxq
)
3252 rxq
->size
= pp
->rx_ring_size
;
3254 /* Allocate memory for RX descriptors */
3255 rxq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
3256 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3257 &rxq
->descs_phys
, GFP_KERNEL
);
3261 rxq
->last_desc
= rxq
->size
- 1;
3266 static void mvneta_rxq_hw_init(struct mvneta_port
*pp
,
3267 struct mvneta_rx_queue
*rxq
)
3269 /* Set Rx descriptors queue starting address */
3270 mvreg_write(pp
, MVNETA_RXQ_BASE_ADDR_REG(rxq
->id
), rxq
->descs_phys
);
3271 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), rxq
->size
);
3273 /* Set coalescing pkts and time */
3274 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
3275 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
3279 mvneta_rxq_offset_set(pp
, rxq
, 0);
3280 mvneta_rxq_buf_size_set(pp
, rxq
, PAGE_SIZE
< SZ_64K
?
3281 MVNETA_MAX_RX_BUF_SIZE
:
3282 MVNETA_RX_BUF_SIZE(pp
->pkt_size
));
3283 mvneta_rxq_bm_disable(pp
, rxq
);
3284 mvneta_rxq_fill(pp
, rxq
, rxq
->size
);
3287 mvneta_rxq_offset_set(pp
, rxq
,
3288 NET_SKB_PAD
- pp
->rx_offset_correction
);
3290 mvneta_rxq_bm_enable(pp
, rxq
);
3291 /* Fill RXQ with buffers from RX pool */
3292 mvneta_rxq_long_pool_set(pp
, rxq
);
3293 mvneta_rxq_short_pool_set(pp
, rxq
);
3294 mvneta_rxq_non_occup_desc_add(pp
, rxq
, rxq
->size
);
3298 /* Create a specified RX queue */
3299 static int mvneta_rxq_init(struct mvneta_port
*pp
,
3300 struct mvneta_rx_queue
*rxq
)
3305 ret
= mvneta_rxq_sw_init(pp
, rxq
);
3309 mvneta_rxq_hw_init(pp
, rxq
);
3314 /* Cleanup Rx queue */
3315 static void mvneta_rxq_deinit(struct mvneta_port
*pp
,
3316 struct mvneta_rx_queue
*rxq
)
3318 mvneta_rxq_drop_pkts(pp
, rxq
);
3321 dev_kfree_skb_any(rxq
->skb
);
3324 dma_free_coherent(pp
->dev
->dev
.parent
,
3325 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3331 rxq
->next_desc_to_proc
= 0;
3332 rxq
->descs_phys
= 0;
3333 rxq
->first_to_refill
= 0;
3334 rxq
->refill_num
= 0;
3339 static int mvneta_txq_sw_init(struct mvneta_port
*pp
,
3340 struct mvneta_tx_queue
*txq
)
3344 txq
->size
= pp
->tx_ring_size
;
3346 /* A queue must always have room for at least one skb.
3347 * Therefore, stop the queue when the free entries reaches
3348 * the maximum number of descriptors per skb.
3350 txq
->tx_stop_threshold
= txq
->size
- MVNETA_MAX_SKB_DESCS
;
3351 txq
->tx_wake_threshold
= txq
->tx_stop_threshold
/ 2;
3353 /* Allocate memory for TX descriptors */
3354 txq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
3355 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3356 &txq
->descs_phys
, GFP_KERNEL
);
3360 txq
->last_desc
= txq
->size
- 1;
3362 txq
->buf
= kmalloc_array(txq
->size
, sizeof(*txq
->buf
), GFP_KERNEL
);
3364 dma_free_coherent(pp
->dev
->dev
.parent
,
3365 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3366 txq
->descs
, txq
->descs_phys
);
3370 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3371 txq
->tso_hdrs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
3372 txq
->size
* TSO_HEADER_SIZE
,
3373 &txq
->tso_hdrs_phys
, GFP_KERNEL
);
3374 if (!txq
->tso_hdrs
) {
3376 dma_free_coherent(pp
->dev
->dev
.parent
,
3377 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3378 txq
->descs
, txq
->descs_phys
);
3382 /* Setup XPS mapping */
3384 cpu
= txq
->id
% num_present_cpus();
3386 cpu
= pp
->rxq_def
% num_present_cpus();
3387 cpumask_set_cpu(cpu
, &txq
->affinity_mask
);
3388 netif_set_xps_queue(pp
->dev
, &txq
->affinity_mask
, txq
->id
);
3393 static void mvneta_txq_hw_init(struct mvneta_port
*pp
,
3394 struct mvneta_tx_queue
*txq
)
3396 /* Set maximum bandwidth for enabled TXQs */
3397 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0x03ffffff);
3398 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0x3fffffff);
3400 /* Set Tx descriptors queue starting address */
3401 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), txq
->descs_phys
);
3402 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), txq
->size
);
3404 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
3407 /* Create and initialize a tx queue */
3408 static int mvneta_txq_init(struct mvneta_port
*pp
,
3409 struct mvneta_tx_queue
*txq
)
3413 ret
= mvneta_txq_sw_init(pp
, txq
);
3417 mvneta_txq_hw_init(pp
, txq
);
3422 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3423 static void mvneta_txq_sw_deinit(struct mvneta_port
*pp
,
3424 struct mvneta_tx_queue
*txq
)
3426 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
3431 dma_free_coherent(pp
->dev
->dev
.parent
,
3432 txq
->size
* TSO_HEADER_SIZE
,
3433 txq
->tso_hdrs
, txq
->tso_hdrs_phys
);
3435 dma_free_coherent(pp
->dev
->dev
.parent
,
3436 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
3437 txq
->descs
, txq
->descs_phys
);
3439 netdev_tx_reset_queue(nq
);
3443 txq
->next_desc_to_proc
= 0;
3444 txq
->descs_phys
= 0;
3447 static void mvneta_txq_hw_deinit(struct mvneta_port
*pp
,
3448 struct mvneta_tx_queue
*txq
)
3450 /* Set minimum bandwidth for disabled TXQs */
3451 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0);
3452 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0);
3454 /* Set Tx descriptors queue starting address and size */
3455 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), 0);
3456 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), 0);
3459 static void mvneta_txq_deinit(struct mvneta_port
*pp
,
3460 struct mvneta_tx_queue
*txq
)
3462 mvneta_txq_sw_deinit(pp
, txq
);
3463 mvneta_txq_hw_deinit(pp
, txq
);
3466 /* Cleanup all Tx queues */
3467 static void mvneta_cleanup_txqs(struct mvneta_port
*pp
)
3471 for (queue
= 0; queue
< txq_number
; queue
++)
3472 mvneta_txq_deinit(pp
, &pp
->txqs
[queue
]);
3475 /* Cleanup all Rx queues */
3476 static void mvneta_cleanup_rxqs(struct mvneta_port
*pp
)
3480 for (queue
= 0; queue
< rxq_number
; queue
++)
3481 mvneta_rxq_deinit(pp
, &pp
->rxqs
[queue
]);
3485 /* Init all Rx queues */
3486 static int mvneta_setup_rxqs(struct mvneta_port
*pp
)
3490 for (queue
= 0; queue
< rxq_number
; queue
++) {
3491 int err
= mvneta_rxq_init(pp
, &pp
->rxqs
[queue
]);
3494 netdev_err(pp
->dev
, "%s: can't create rxq=%d\n",
3496 mvneta_cleanup_rxqs(pp
);
3504 /* Init all tx queues */
3505 static int mvneta_setup_txqs(struct mvneta_port
*pp
)
3509 for (queue
= 0; queue
< txq_number
; queue
++) {
3510 int err
= mvneta_txq_init(pp
, &pp
->txqs
[queue
]);
3512 netdev_err(pp
->dev
, "%s: can't create txq=%d\n",
3514 mvneta_cleanup_txqs(pp
);
3522 static int mvneta_comphy_init(struct mvneta_port
*pp
)
3529 ret
= phy_set_mode_ext(pp
->comphy
, PHY_MODE_ETHERNET
,
3534 return phy_power_on(pp
->comphy
);
3537 static void mvneta_start_dev(struct mvneta_port
*pp
)
3541 WARN_ON(mvneta_comphy_init(pp
));
3543 mvneta_max_rx_size_set(pp
, pp
->pkt_size
);
3544 mvneta_txq_max_tx_size_set(pp
, pp
->pkt_size
);
3546 /* start the Rx/Tx activity */
3547 mvneta_port_enable(pp
);
3549 if (!pp
->neta_armada3700
) {
3550 /* Enable polling on the port */
3551 for_each_online_cpu(cpu
) {
3552 struct mvneta_pcpu_port
*port
=
3553 per_cpu_ptr(pp
->ports
, cpu
);
3555 napi_enable(&port
->napi
);
3558 napi_enable(&pp
->napi
);
3561 /* Unmask interrupts. It has to be done from each CPU */
3562 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
3564 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
3565 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
3566 MVNETA_CAUSE_LINK_CHANGE
);
3568 phylink_start(pp
->phylink
);
3569 netif_tx_start_all_queues(pp
->dev
);
3572 static void mvneta_stop_dev(struct mvneta_port
*pp
)
3576 phylink_stop(pp
->phylink
);
3578 if (!pp
->neta_armada3700
) {
3579 for_each_online_cpu(cpu
) {
3580 struct mvneta_pcpu_port
*port
=
3581 per_cpu_ptr(pp
->ports
, cpu
);
3583 napi_disable(&port
->napi
);
3586 napi_disable(&pp
->napi
);
3589 netif_carrier_off(pp
->dev
);
3591 mvneta_port_down(pp
);
3592 netif_tx_stop_all_queues(pp
->dev
);
3594 /* Stop the port activity */
3595 mvneta_port_disable(pp
);
3597 /* Clear all ethernet port interrupts */
3598 on_each_cpu(mvneta_percpu_clear_intr_cause
, pp
, true);
3600 /* Mask all ethernet port interrupts */
3601 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
3603 mvneta_tx_reset(pp
);
3604 mvneta_rx_reset(pp
);
3606 WARN_ON(phy_power_off(pp
->comphy
));
3609 static void mvneta_percpu_enable(void *arg
)
3611 struct mvneta_port
*pp
= arg
;
3613 enable_percpu_irq(pp
->dev
->irq
, IRQ_TYPE_NONE
);
3616 static void mvneta_percpu_disable(void *arg
)
3618 struct mvneta_port
*pp
= arg
;
3620 disable_percpu_irq(pp
->dev
->irq
);
3623 /* Change the device mtu */
3624 static int mvneta_change_mtu(struct net_device
*dev
, int mtu
)
3626 struct mvneta_port
*pp
= netdev_priv(dev
);
3629 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu
), 8)) {
3630 netdev_info(dev
, "Illegal MTU value %d, rounding to %d\n",
3631 mtu
, ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8));
3632 mtu
= ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8);
3635 if (pp
->xdp_prog
&& mtu
> MVNETA_MAX_RX_BUF_SIZE
) {
3636 netdev_info(dev
, "Illegal MTU value %d for XDP mode\n", mtu
);
3642 if (!netif_running(dev
)) {
3644 mvneta_bm_update_mtu(pp
, mtu
);
3646 netdev_update_features(dev
);
3650 /* The interface is running, so we have to force a
3651 * reallocation of the queues
3653 mvneta_stop_dev(pp
);
3654 on_each_cpu(mvneta_percpu_disable
, pp
, true);
3656 mvneta_cleanup_txqs(pp
);
3657 mvneta_cleanup_rxqs(pp
);
3660 mvneta_bm_update_mtu(pp
, mtu
);
3662 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(dev
->mtu
);
3664 ret
= mvneta_setup_rxqs(pp
);
3666 netdev_err(dev
, "unable to setup rxqs after MTU change\n");
3670 ret
= mvneta_setup_txqs(pp
);
3672 netdev_err(dev
, "unable to setup txqs after MTU change\n");
3676 on_each_cpu(mvneta_percpu_enable
, pp
, true);
3677 mvneta_start_dev(pp
);
3679 netdev_update_features(dev
);
3684 static netdev_features_t
mvneta_fix_features(struct net_device
*dev
,
3685 netdev_features_t features
)
3687 struct mvneta_port
*pp
= netdev_priv(dev
);
3689 if (pp
->tx_csum_limit
&& dev
->mtu
> pp
->tx_csum_limit
) {
3690 features
&= ~(NETIF_F_IP_CSUM
| NETIF_F_TSO
);
3692 "Disable IP checksum for MTU greater than %dB\n",
3699 /* Get mac address */
3700 static void mvneta_get_mac_addr(struct mvneta_port
*pp
, unsigned char *addr
)
3702 u32 mac_addr_l
, mac_addr_h
;
3704 mac_addr_l
= mvreg_read(pp
, MVNETA_MAC_ADDR_LOW
);
3705 mac_addr_h
= mvreg_read(pp
, MVNETA_MAC_ADDR_HIGH
);
3706 addr
[0] = (mac_addr_h
>> 24) & 0xFF;
3707 addr
[1] = (mac_addr_h
>> 16) & 0xFF;
3708 addr
[2] = (mac_addr_h
>> 8) & 0xFF;
3709 addr
[3] = mac_addr_h
& 0xFF;
3710 addr
[4] = (mac_addr_l
>> 8) & 0xFF;
3711 addr
[5] = mac_addr_l
& 0xFF;
3714 /* Handle setting mac address */
3715 static int mvneta_set_mac_addr(struct net_device
*dev
, void *addr
)
3717 struct mvneta_port
*pp
= netdev_priv(dev
);
3718 struct sockaddr
*sockaddr
= addr
;
3721 ret
= eth_prepare_mac_addr_change(dev
, addr
);
3724 /* Remove previous address table entry */
3725 mvneta_mac_addr_set(pp
, dev
->dev_addr
, -1);
3727 /* Set new addr in hw */
3728 mvneta_mac_addr_set(pp
, sockaddr
->sa_data
, pp
->rxq_def
);
3730 eth_commit_mac_addr_change(dev
, addr
);
3734 static void mvneta_validate(struct phylink_config
*config
,
3735 unsigned long *supported
,
3736 struct phylink_link_state
*state
)
3738 struct net_device
*ndev
= to_net_dev(config
->dev
);
3739 struct mvneta_port
*pp
= netdev_priv(ndev
);
3740 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
3742 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3743 if (state
->interface
!= PHY_INTERFACE_MODE_NA
&&
3744 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
3745 state
->interface
!= PHY_INTERFACE_MODE_SGMII
&&
3746 !phy_interface_mode_is_8023z(state
->interface
) &&
3747 !phy_interface_mode_is_rgmii(state
->interface
)) {
3748 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
3752 /* Allow all the expected bits */
3753 phylink_set(mask
, Autoneg
);
3754 phylink_set_port_modes(mask
);
3756 /* Asymmetric pause is unsupported */
3757 phylink_set(mask
, Pause
);
3759 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3760 if (pp
->comphy
|| state
->interface
!= PHY_INTERFACE_MODE_2500BASEX
) {
3761 phylink_set(mask
, 1000baseT_Full
);
3762 phylink_set(mask
, 1000baseX_Full
);
3764 if (pp
->comphy
|| state
->interface
== PHY_INTERFACE_MODE_2500BASEX
) {
3765 phylink_set(mask
, 2500baseT_Full
);
3766 phylink_set(mask
, 2500baseX_Full
);
3769 if (!phy_interface_mode_is_8023z(state
->interface
)) {
3770 /* 10M and 100M are only supported in non-802.3z mode */
3771 phylink_set(mask
, 10baseT_Half
);
3772 phylink_set(mask
, 10baseT_Full
);
3773 phylink_set(mask
, 100baseT_Half
);
3774 phylink_set(mask
, 100baseT_Full
);
3777 bitmap_and(supported
, supported
, mask
,
3778 __ETHTOOL_LINK_MODE_MASK_NBITS
);
3779 bitmap_and(state
->advertising
, state
->advertising
, mask
,
3780 __ETHTOOL_LINK_MODE_MASK_NBITS
);
3782 /* We can only operate at 2500BaseX or 1000BaseX. If requested
3783 * to advertise both, only report advertising at 2500BaseX.
3785 phylink_helper_basex_speed(state
);
3788 static void mvneta_mac_pcs_get_state(struct phylink_config
*config
,
3789 struct phylink_link_state
*state
)
3791 struct net_device
*ndev
= to_net_dev(config
->dev
);
3792 struct mvneta_port
*pp
= netdev_priv(ndev
);
3795 gmac_stat
= mvreg_read(pp
, MVNETA_GMAC_STATUS
);
3797 if (gmac_stat
& MVNETA_GMAC_SPEED_1000
)
3799 state
->interface
== PHY_INTERFACE_MODE_2500BASEX
?
3800 SPEED_2500
: SPEED_1000
;
3801 else if (gmac_stat
& MVNETA_GMAC_SPEED_100
)
3802 state
->speed
= SPEED_100
;
3804 state
->speed
= SPEED_10
;
3806 state
->an_complete
= !!(gmac_stat
& MVNETA_GMAC_AN_COMPLETE
);
3807 state
->link
= !!(gmac_stat
& MVNETA_GMAC_LINK_UP
);
3808 state
->duplex
= !!(gmac_stat
& MVNETA_GMAC_FULL_DUPLEX
);
3811 if (gmac_stat
& MVNETA_GMAC_RX_FLOW_CTRL_ENABLE
)
3812 state
->pause
|= MLO_PAUSE_RX
;
3813 if (gmac_stat
& MVNETA_GMAC_TX_FLOW_CTRL_ENABLE
)
3814 state
->pause
|= MLO_PAUSE_TX
;
3817 static void mvneta_mac_an_restart(struct phylink_config
*config
)
3819 struct net_device
*ndev
= to_net_dev(config
->dev
);
3820 struct mvneta_port
*pp
= netdev_priv(ndev
);
3821 u32 gmac_an
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3823 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3824 gmac_an
| MVNETA_GMAC_INBAND_RESTART_AN
);
3825 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3826 gmac_an
& ~MVNETA_GMAC_INBAND_RESTART_AN
);
3829 static void mvneta_mac_config(struct phylink_config
*config
, unsigned int mode
,
3830 const struct phylink_link_state
*state
)
3832 struct net_device
*ndev
= to_net_dev(config
->dev
);
3833 struct mvneta_port
*pp
= netdev_priv(ndev
);
3834 u32 new_ctrl0
, gmac_ctrl0
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
3835 u32 new_ctrl2
, gmac_ctrl2
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
3836 u32 new_ctrl4
, gmac_ctrl4
= mvreg_read(pp
, MVNETA_GMAC_CTRL_4
);
3837 u32 new_clk
, gmac_clk
= mvreg_read(pp
, MVNETA_GMAC_CLOCK_DIVIDER
);
3838 u32 new_an
, gmac_an
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3840 new_ctrl0
= gmac_ctrl0
& ~MVNETA_GMAC0_PORT_1000BASE_X
;
3841 new_ctrl2
= gmac_ctrl2
& ~(MVNETA_GMAC2_INBAND_AN_ENABLE
|
3842 MVNETA_GMAC2_PORT_RESET
);
3843 new_ctrl4
= gmac_ctrl4
& ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE
);
3844 new_clk
= gmac_clk
& ~MVNETA_GMAC_1MS_CLOCK_ENABLE
;
3845 new_an
= gmac_an
& ~(MVNETA_GMAC_INBAND_AN_ENABLE
|
3846 MVNETA_GMAC_INBAND_RESTART_AN
|
3847 MVNETA_GMAC_AN_SPEED_EN
|
3848 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL
|
3849 MVNETA_GMAC_AN_FLOW_CTRL_EN
|
3850 MVNETA_GMAC_AN_DUPLEX_EN
);
3852 /* Even though it might look weird, when we're configured in
3853 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3855 new_ctrl2
|= MVNETA_GMAC2_PORT_RGMII
;
3857 if (state
->interface
== PHY_INTERFACE_MODE_QSGMII
||
3858 state
->interface
== PHY_INTERFACE_MODE_SGMII
||
3859 phy_interface_mode_is_8023z(state
->interface
))
3860 new_ctrl2
|= MVNETA_GMAC2_PCS_ENABLE
;
3862 if (phylink_test(state
->advertising
, Pause
))
3863 new_an
|= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL
;
3865 if (!phylink_autoneg_inband(mode
)) {
3866 /* Phy or fixed speed - nothing to do, leave the
3867 * configured speed, duplex and flow control as-is.
3869 } else if (state
->interface
== PHY_INTERFACE_MODE_SGMII
) {
3870 /* SGMII mode receives the state from the PHY */
3871 new_ctrl2
|= MVNETA_GMAC2_INBAND_AN_ENABLE
;
3872 new_clk
|= MVNETA_GMAC_1MS_CLOCK_ENABLE
;
3873 new_an
= (new_an
& ~(MVNETA_GMAC_FORCE_LINK_DOWN
|
3874 MVNETA_GMAC_FORCE_LINK_PASS
|
3875 MVNETA_GMAC_CONFIG_MII_SPEED
|
3876 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3877 MVNETA_GMAC_CONFIG_FULL_DUPLEX
)) |
3878 MVNETA_GMAC_INBAND_AN_ENABLE
|
3879 MVNETA_GMAC_AN_SPEED_EN
|
3880 MVNETA_GMAC_AN_DUPLEX_EN
;
3882 /* 802.3z negotiation - only 1000base-X */
3883 new_ctrl0
|= MVNETA_GMAC0_PORT_1000BASE_X
;
3884 new_clk
|= MVNETA_GMAC_1MS_CLOCK_ENABLE
;
3885 new_an
= (new_an
& ~(MVNETA_GMAC_FORCE_LINK_DOWN
|
3886 MVNETA_GMAC_FORCE_LINK_PASS
|
3887 MVNETA_GMAC_CONFIG_MII_SPEED
)) |
3888 MVNETA_GMAC_INBAND_AN_ENABLE
|
3889 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3890 /* The MAC only supports FD mode */
3891 MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
3893 if (state
->pause
& MLO_PAUSE_AN
&& state
->an_enabled
)
3894 new_an
|= MVNETA_GMAC_AN_FLOW_CTRL_EN
;
3897 /* Armada 370 documentation says we can only change the port mode
3898 * and in-band enable when the link is down, so force it down
3899 * while making these changes. We also do this for GMAC_CTRL2 */
3900 if ((new_ctrl0
^ gmac_ctrl0
) & MVNETA_GMAC0_PORT_1000BASE_X
||
3901 (new_ctrl2
^ gmac_ctrl2
) & MVNETA_GMAC2_INBAND_AN_ENABLE
||
3902 (new_an
^ gmac_an
) & MVNETA_GMAC_INBAND_AN_ENABLE
) {
3903 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
,
3904 (gmac_an
& ~MVNETA_GMAC_FORCE_LINK_PASS
) |
3905 MVNETA_GMAC_FORCE_LINK_DOWN
);
3909 /* When at 2.5G, the link partner can send frames with shortened
3912 if (state
->speed
== SPEED_2500
)
3913 new_ctrl4
|= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE
;
3915 if (pp
->comphy
&& pp
->phy_interface
!= state
->interface
&&
3916 (state
->interface
== PHY_INTERFACE_MODE_SGMII
||
3917 state
->interface
== PHY_INTERFACE_MODE_1000BASEX
||
3918 state
->interface
== PHY_INTERFACE_MODE_2500BASEX
)) {
3919 pp
->phy_interface
= state
->interface
;
3921 WARN_ON(phy_power_off(pp
->comphy
));
3922 WARN_ON(mvneta_comphy_init(pp
));
3925 if (new_ctrl0
!= gmac_ctrl0
)
3926 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, new_ctrl0
);
3927 if (new_ctrl2
!= gmac_ctrl2
)
3928 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, new_ctrl2
);
3929 if (new_ctrl4
!= gmac_ctrl4
)
3930 mvreg_write(pp
, MVNETA_GMAC_CTRL_4
, new_ctrl4
);
3931 if (new_clk
!= gmac_clk
)
3932 mvreg_write(pp
, MVNETA_GMAC_CLOCK_DIVIDER
, new_clk
);
3933 if (new_an
!= gmac_an
)
3934 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, new_an
);
3936 if (gmac_ctrl2
& MVNETA_GMAC2_PORT_RESET
) {
3937 while ((mvreg_read(pp
, MVNETA_GMAC_CTRL_2
) &
3938 MVNETA_GMAC2_PORT_RESET
) != 0)
3943 static void mvneta_set_eee(struct mvneta_port
*pp
, bool enable
)
3947 lpi_ctl1
= mvreg_read(pp
, MVNETA_LPI_CTRL_1
);
3949 lpi_ctl1
|= MVNETA_LPI_REQUEST_ENABLE
;
3951 lpi_ctl1
&= ~MVNETA_LPI_REQUEST_ENABLE
;
3952 mvreg_write(pp
, MVNETA_LPI_CTRL_1
, lpi_ctl1
);
3955 static void mvneta_mac_link_down(struct phylink_config
*config
,
3956 unsigned int mode
, phy_interface_t interface
)
3958 struct net_device
*ndev
= to_net_dev(config
->dev
);
3959 struct mvneta_port
*pp
= netdev_priv(ndev
);
3962 mvneta_port_down(pp
);
3964 if (!phylink_autoneg_inband(mode
)) {
3965 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3966 val
&= ~MVNETA_GMAC_FORCE_LINK_PASS
;
3967 val
|= MVNETA_GMAC_FORCE_LINK_DOWN
;
3968 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
3971 pp
->eee_active
= false;
3972 mvneta_set_eee(pp
, false);
3975 static void mvneta_mac_link_up(struct phylink_config
*config
,
3976 struct phy_device
*phy
,
3977 unsigned int mode
, phy_interface_t interface
,
3978 int speed
, int duplex
,
3979 bool tx_pause
, bool rx_pause
)
3981 struct net_device
*ndev
= to_net_dev(config
->dev
);
3982 struct mvneta_port
*pp
= netdev_priv(ndev
);
3985 if (!phylink_autoneg_inband(mode
)) {
3986 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
3987 val
&= ~(MVNETA_GMAC_FORCE_LINK_DOWN
|
3988 MVNETA_GMAC_CONFIG_MII_SPEED
|
3989 MVNETA_GMAC_CONFIG_GMII_SPEED
|
3990 MVNETA_GMAC_CONFIG_FLOW_CTRL
|
3991 MVNETA_GMAC_CONFIG_FULL_DUPLEX
);
3992 val
|= MVNETA_GMAC_FORCE_LINK_PASS
;
3994 if (speed
== SPEED_1000
|| speed
== SPEED_2500
)
3995 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
3996 else if (speed
== SPEED_100
)
3997 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
3999 if (duplex
== DUPLEX_FULL
)
4000 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
4002 if (tx_pause
|| rx_pause
)
4003 val
|= MVNETA_GMAC_CONFIG_FLOW_CTRL
;
4005 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
4007 /* When inband doesn't cover flow control or flow control is
4008 * disabled, we need to manually configure it. This bit will
4009 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
4011 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
4012 val
&= ~MVNETA_GMAC_CONFIG_FLOW_CTRL
;
4014 if (tx_pause
|| rx_pause
)
4015 val
|= MVNETA_GMAC_CONFIG_FLOW_CTRL
;
4017 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
4022 if (phy
&& pp
->eee_enabled
) {
4023 pp
->eee_active
= phy_init_eee(phy
, 0) >= 0;
4024 mvneta_set_eee(pp
, pp
->eee_active
&& pp
->tx_lpi_enabled
);
4028 static const struct phylink_mac_ops mvneta_phylink_ops
= {
4029 .validate
= mvneta_validate
,
4030 .mac_pcs_get_state
= mvneta_mac_pcs_get_state
,
4031 .mac_an_restart
= mvneta_mac_an_restart
,
4032 .mac_config
= mvneta_mac_config
,
4033 .mac_link_down
= mvneta_mac_link_down
,
4034 .mac_link_up
= mvneta_mac_link_up
,
4037 static int mvneta_mdio_probe(struct mvneta_port
*pp
)
4039 struct ethtool_wolinfo wol
= { .cmd
= ETHTOOL_GWOL
};
4040 int err
= phylink_of_phy_connect(pp
->phylink
, pp
->dn
, 0);
4043 netdev_err(pp
->dev
, "could not attach PHY: %d\n", err
);
4045 phylink_ethtool_get_wol(pp
->phylink
, &wol
);
4046 device_set_wakeup_capable(&pp
->dev
->dev
, !!wol
.supported
);
4051 static void mvneta_mdio_remove(struct mvneta_port
*pp
)
4053 phylink_disconnect_phy(pp
->phylink
);
4056 /* Electing a CPU must be done in an atomic way: it should be done
4057 * after or before the removal/insertion of a CPU and this function is
4060 static void mvneta_percpu_elect(struct mvneta_port
*pp
)
4062 int elected_cpu
= 0, max_cpu
, cpu
, i
= 0;
4064 /* Use the cpu associated to the rxq when it is online, in all
4065 * the other cases, use the cpu 0 which can't be offline.
4067 if (cpu_online(pp
->rxq_def
))
4068 elected_cpu
= pp
->rxq_def
;
4070 max_cpu
= num_present_cpus();
4072 for_each_online_cpu(cpu
) {
4073 int rxq_map
= 0, txq_map
= 0;
4076 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
4077 if ((rxq
% max_cpu
) == cpu
)
4078 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(rxq
);
4080 if (cpu
== elected_cpu
)
4081 /* Map the default receive queue queue to the
4084 rxq_map
|= MVNETA_CPU_RXQ_ACCESS(pp
->rxq_def
);
4086 /* We update the TX queue map only if we have one
4087 * queue. In this case we associate the TX queue to
4088 * the CPU bound to the default RX queue
4090 if (txq_number
== 1)
4091 txq_map
= (cpu
== elected_cpu
) ?
4092 MVNETA_CPU_TXQ_ACCESS(1) : 0;
4094 txq_map
= mvreg_read(pp
, MVNETA_CPU_MAP(cpu
)) &
4095 MVNETA_CPU_TXQ_ACCESS_ALL_MASK
;
4097 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
), rxq_map
| txq_map
);
4099 /* Update the interrupt mask on each CPU according the
4102 smp_call_function_single(cpu
, mvneta_percpu_unmask_interrupt
,
4109 static int mvneta_cpu_online(unsigned int cpu
, struct hlist_node
*node
)
4112 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
4114 struct mvneta_pcpu_port
*port
= per_cpu_ptr(pp
->ports
, cpu
);
4117 spin_lock(&pp
->lock
);
4119 * Configuring the driver for a new CPU while the driver is
4120 * stopping is racy, so just avoid it.
4122 if (pp
->is_stopped
) {
4123 spin_unlock(&pp
->lock
);
4126 netif_tx_stop_all_queues(pp
->dev
);
4129 * We have to synchronise on tha napi of each CPU except the one
4130 * just being woken up
4132 for_each_online_cpu(other_cpu
) {
4133 if (other_cpu
!= cpu
) {
4134 struct mvneta_pcpu_port
*other_port
=
4135 per_cpu_ptr(pp
->ports
, other_cpu
);
4137 napi_synchronize(&other_port
->napi
);
4141 /* Mask all ethernet port interrupts */
4142 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
4143 napi_enable(&port
->napi
);
4146 * Enable per-CPU interrupts on the CPU that is
4149 mvneta_percpu_enable(pp
);
4152 * Enable per-CPU interrupt on the one CPU we care
4155 mvneta_percpu_elect(pp
);
4157 /* Unmask all ethernet port interrupts */
4158 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
4159 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
4160 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
4161 MVNETA_CAUSE_LINK_CHANGE
);
4162 netif_tx_start_all_queues(pp
->dev
);
4163 spin_unlock(&pp
->lock
);
4167 static int mvneta_cpu_down_prepare(unsigned int cpu
, struct hlist_node
*node
)
4169 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
4171 struct mvneta_pcpu_port
*port
= per_cpu_ptr(pp
->ports
, cpu
);
4174 * Thanks to this lock we are sure that any pending cpu election is
4177 spin_lock(&pp
->lock
);
4178 /* Mask all ethernet port interrupts */
4179 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
4180 spin_unlock(&pp
->lock
);
4182 napi_synchronize(&port
->napi
);
4183 napi_disable(&port
->napi
);
4184 /* Disable per-CPU interrupts on the CPU that is brought down. */
4185 mvneta_percpu_disable(pp
);
4189 static int mvneta_cpu_dead(unsigned int cpu
, struct hlist_node
*node
)
4191 struct mvneta_port
*pp
= hlist_entry_safe(node
, struct mvneta_port
,
4194 /* Check if a new CPU must be elected now this on is down */
4195 spin_lock(&pp
->lock
);
4196 mvneta_percpu_elect(pp
);
4197 spin_unlock(&pp
->lock
);
4198 /* Unmask all ethernet port interrupts */
4199 on_each_cpu(mvneta_percpu_unmask_interrupt
, pp
, true);
4200 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
,
4201 MVNETA_CAUSE_PHY_STATUS_CHANGE
|
4202 MVNETA_CAUSE_LINK_CHANGE
);
4203 netif_tx_start_all_queues(pp
->dev
);
4207 static int mvneta_open(struct net_device
*dev
)
4209 struct mvneta_port
*pp
= netdev_priv(dev
);
4212 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
);
4214 ret
= mvneta_setup_rxqs(pp
);
4218 ret
= mvneta_setup_txqs(pp
);
4220 goto err_cleanup_rxqs
;
4222 /* Connect to port interrupt line */
4223 if (pp
->neta_armada3700
)
4224 ret
= request_irq(pp
->dev
->irq
, mvneta_isr
, 0,
4227 ret
= request_percpu_irq(pp
->dev
->irq
, mvneta_percpu_isr
,
4228 dev
->name
, pp
->ports
);
4230 netdev_err(pp
->dev
, "cannot request irq %d\n", pp
->dev
->irq
);
4231 goto err_cleanup_txqs
;
4234 if (!pp
->neta_armada3700
) {
4235 /* Enable per-CPU interrupt on all the CPU to handle our RX
4238 on_each_cpu(mvneta_percpu_enable
, pp
, true);
4240 pp
->is_stopped
= false;
4241 /* Register a CPU notifier to handle the case where our CPU
4242 * might be taken offline.
4244 ret
= cpuhp_state_add_instance_nocalls(online_hpstate
,
4249 ret
= cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
4252 goto err_free_online_hp
;
4255 ret
= mvneta_mdio_probe(pp
);
4257 netdev_err(dev
, "cannot probe MDIO bus\n");
4258 goto err_free_dead_hp
;
4261 mvneta_start_dev(pp
);
4266 if (!pp
->neta_armada3700
)
4267 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
4270 if (!pp
->neta_armada3700
)
4271 cpuhp_state_remove_instance_nocalls(online_hpstate
,
4274 if (pp
->neta_armada3700
) {
4275 free_irq(pp
->dev
->irq
, pp
);
4277 on_each_cpu(mvneta_percpu_disable
, pp
, true);
4278 free_percpu_irq(pp
->dev
->irq
, pp
->ports
);
4281 mvneta_cleanup_txqs(pp
);
4283 mvneta_cleanup_rxqs(pp
);
4287 /* Stop the port, free port interrupt line */
4288 static int mvneta_stop(struct net_device
*dev
)
4290 struct mvneta_port
*pp
= netdev_priv(dev
);
4292 if (!pp
->neta_armada3700
) {
4293 /* Inform that we are stopping so we don't want to setup the
4294 * driver for new CPUs in the notifiers. The code of the
4295 * notifier for CPU online is protected by the same spinlock,
4296 * so when we get the lock, the notifer work is done.
4298 spin_lock(&pp
->lock
);
4299 pp
->is_stopped
= true;
4300 spin_unlock(&pp
->lock
);
4302 mvneta_stop_dev(pp
);
4303 mvneta_mdio_remove(pp
);
4305 cpuhp_state_remove_instance_nocalls(online_hpstate
,
4307 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
4309 on_each_cpu(mvneta_percpu_disable
, pp
, true);
4310 free_percpu_irq(dev
->irq
, pp
->ports
);
4312 mvneta_stop_dev(pp
);
4313 mvneta_mdio_remove(pp
);
4314 free_irq(dev
->irq
, pp
);
4317 mvneta_cleanup_rxqs(pp
);
4318 mvneta_cleanup_txqs(pp
);
4323 static int mvneta_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4325 struct mvneta_port
*pp
= netdev_priv(dev
);
4327 return phylink_mii_ioctl(pp
->phylink
, ifr
, cmd
);
4330 static int mvneta_xdp_setup(struct net_device
*dev
, struct bpf_prog
*prog
,
4331 struct netlink_ext_ack
*extack
)
4333 bool need_update
, running
= netif_running(dev
);
4334 struct mvneta_port
*pp
= netdev_priv(dev
);
4335 struct bpf_prog
*old_prog
;
4337 if (prog
&& dev
->mtu
> MVNETA_MAX_RX_BUF_SIZE
) {
4338 NL_SET_ERR_MSG_MOD(extack
, "Jumbo frames not supported on XDP");
4343 NL_SET_ERR_MSG_MOD(extack
,
4344 "Hardware Buffer Management not supported on XDP");
4348 need_update
= !!pp
->xdp_prog
!= !!prog
;
4349 if (running
&& need_update
)
4352 old_prog
= xchg(&pp
->xdp_prog
, prog
);
4354 bpf_prog_put(old_prog
);
4356 if (running
&& need_update
)
4357 return mvneta_open(dev
);
4362 static int mvneta_xdp(struct net_device
*dev
, struct netdev_bpf
*xdp
)
4364 struct mvneta_port
*pp
= netdev_priv(dev
);
4366 switch (xdp
->command
) {
4367 case XDP_SETUP_PROG
:
4368 return mvneta_xdp_setup(dev
, xdp
->prog
, xdp
->extack
);
4369 case XDP_QUERY_PROG
:
4370 xdp
->prog_id
= pp
->xdp_prog
? pp
->xdp_prog
->aux
->id
: 0;
4377 /* Ethtool methods */
4379 /* Set link ksettings (phy address, speed) for ethtools */
4381 mvneta_ethtool_set_link_ksettings(struct net_device
*ndev
,
4382 const struct ethtool_link_ksettings
*cmd
)
4384 struct mvneta_port
*pp
= netdev_priv(ndev
);
4386 return phylink_ethtool_ksettings_set(pp
->phylink
, cmd
);
4389 /* Get link ksettings for ethtools */
4391 mvneta_ethtool_get_link_ksettings(struct net_device
*ndev
,
4392 struct ethtool_link_ksettings
*cmd
)
4394 struct mvneta_port
*pp
= netdev_priv(ndev
);
4396 return phylink_ethtool_ksettings_get(pp
->phylink
, cmd
);
4399 static int mvneta_ethtool_nway_reset(struct net_device
*dev
)
4401 struct mvneta_port
*pp
= netdev_priv(dev
);
4403 return phylink_ethtool_nway_reset(pp
->phylink
);
4406 /* Set interrupt coalescing for ethtools */
4407 static int mvneta_ethtool_set_coalesce(struct net_device
*dev
,
4408 struct ethtool_coalesce
*c
)
4410 struct mvneta_port
*pp
= netdev_priv(dev
);
4413 for (queue
= 0; queue
< rxq_number
; queue
++) {
4414 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
4415 rxq
->time_coal
= c
->rx_coalesce_usecs
;
4416 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
4417 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
4418 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
4421 for (queue
= 0; queue
< txq_number
; queue
++) {
4422 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
4423 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
4424 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
4430 /* get coalescing for ethtools */
4431 static int mvneta_ethtool_get_coalesce(struct net_device
*dev
,
4432 struct ethtool_coalesce
*c
)
4434 struct mvneta_port
*pp
= netdev_priv(dev
);
4436 c
->rx_coalesce_usecs
= pp
->rxqs
[0].time_coal
;
4437 c
->rx_max_coalesced_frames
= pp
->rxqs
[0].pkts_coal
;
4439 c
->tx_max_coalesced_frames
= pp
->txqs
[0].done_pkts_coal
;
4444 static void mvneta_ethtool_get_drvinfo(struct net_device
*dev
,
4445 struct ethtool_drvinfo
*drvinfo
)
4447 strlcpy(drvinfo
->driver
, MVNETA_DRIVER_NAME
,
4448 sizeof(drvinfo
->driver
));
4449 strlcpy(drvinfo
->version
, MVNETA_DRIVER_VERSION
,
4450 sizeof(drvinfo
->version
));
4451 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
4452 sizeof(drvinfo
->bus_info
));
4456 static void mvneta_ethtool_get_ringparam(struct net_device
*netdev
,
4457 struct ethtool_ringparam
*ring
)
4459 struct mvneta_port
*pp
= netdev_priv(netdev
);
4461 ring
->rx_max_pending
= MVNETA_MAX_RXD
;
4462 ring
->tx_max_pending
= MVNETA_MAX_TXD
;
4463 ring
->rx_pending
= pp
->rx_ring_size
;
4464 ring
->tx_pending
= pp
->tx_ring_size
;
4467 static int mvneta_ethtool_set_ringparam(struct net_device
*dev
,
4468 struct ethtool_ringparam
*ring
)
4470 struct mvneta_port
*pp
= netdev_priv(dev
);
4472 if ((ring
->rx_pending
== 0) || (ring
->tx_pending
== 0))
4474 pp
->rx_ring_size
= ring
->rx_pending
< MVNETA_MAX_RXD
?
4475 ring
->rx_pending
: MVNETA_MAX_RXD
;
4477 pp
->tx_ring_size
= clamp_t(u16
, ring
->tx_pending
,
4478 MVNETA_MAX_SKB_DESCS
* 2, MVNETA_MAX_TXD
);
4479 if (pp
->tx_ring_size
!= ring
->tx_pending
)
4480 netdev_warn(dev
, "TX queue size set to %u (requested %u)\n",
4481 pp
->tx_ring_size
, ring
->tx_pending
);
4483 if (netif_running(dev
)) {
4485 if (mvneta_open(dev
)) {
4487 "error on opening device after ring param change\n");
4495 static void mvneta_ethtool_get_pauseparam(struct net_device
*dev
,
4496 struct ethtool_pauseparam
*pause
)
4498 struct mvneta_port
*pp
= netdev_priv(dev
);
4500 phylink_ethtool_get_pauseparam(pp
->phylink
, pause
);
4503 static int mvneta_ethtool_set_pauseparam(struct net_device
*dev
,
4504 struct ethtool_pauseparam
*pause
)
4506 struct mvneta_port
*pp
= netdev_priv(dev
);
4508 return phylink_ethtool_set_pauseparam(pp
->phylink
, pause
);
4511 static void mvneta_ethtool_get_strings(struct net_device
*netdev
, u32 sset
,
4514 if (sset
== ETH_SS_STATS
) {
4517 for (i
= 0; i
< ARRAY_SIZE(mvneta_statistics
); i
++)
4518 memcpy(data
+ i
* ETH_GSTRING_LEN
,
4519 mvneta_statistics
[i
].name
, ETH_GSTRING_LEN
);
4524 mvneta_ethtool_update_pcpu_stats(struct mvneta_port
*pp
,
4525 struct mvneta_ethtool_stats
*es
)
4530 for_each_possible_cpu(cpu
) {
4531 struct mvneta_pcpu_stats
*stats
;
4532 u64 skb_alloc_error
;
4542 stats
= per_cpu_ptr(pp
->stats
, cpu
);
4544 start
= u64_stats_fetch_begin_irq(&stats
->syncp
);
4545 skb_alloc_error
= stats
->es
.skb_alloc_error
;
4546 refill_error
= stats
->es
.refill_error
;
4547 xdp_redirect
= stats
->es
.ps
.xdp_redirect
;
4548 xdp_pass
= stats
->es
.ps
.xdp_pass
;
4549 xdp_drop
= stats
->es
.ps
.xdp_drop
;
4550 xdp_xmit
= stats
->es
.ps
.xdp_xmit
;
4551 xdp_xmit_err
= stats
->es
.ps
.xdp_xmit_err
;
4552 xdp_tx
= stats
->es
.ps
.xdp_tx
;
4553 xdp_tx_err
= stats
->es
.ps
.xdp_tx_err
;
4554 } while (u64_stats_fetch_retry_irq(&stats
->syncp
, start
));
4556 es
->skb_alloc_error
+= skb_alloc_error
;
4557 es
->refill_error
+= refill_error
;
4558 es
->ps
.xdp_redirect
+= xdp_redirect
;
4559 es
->ps
.xdp_pass
+= xdp_pass
;
4560 es
->ps
.xdp_drop
+= xdp_drop
;
4561 es
->ps
.xdp_xmit
+= xdp_xmit
;
4562 es
->ps
.xdp_xmit_err
+= xdp_xmit_err
;
4563 es
->ps
.xdp_tx
+= xdp_tx
;
4564 es
->ps
.xdp_tx_err
+= xdp_tx_err
;
4568 static void mvneta_ethtool_update_stats(struct mvneta_port
*pp
)
4570 struct mvneta_ethtool_stats stats
= {};
4571 const struct mvneta_statistic
*s
;
4572 void __iomem
*base
= pp
->base
;
4577 mvneta_ethtool_update_pcpu_stats(pp
, &stats
);
4578 for (i
= 0, s
= mvneta_statistics
;
4579 s
< mvneta_statistics
+ ARRAY_SIZE(mvneta_statistics
);
4583 val
= readl_relaxed(base
+ s
->offset
);
4584 pp
->ethtool_stats
[i
] += val
;
4587 /* Docs say to read low 32-bit then high */
4588 low
= readl_relaxed(base
+ s
->offset
);
4589 high
= readl_relaxed(base
+ s
->offset
+ 4);
4590 val
= (u64
)high
<< 32 | low
;
4591 pp
->ethtool_stats
[i
] += val
;
4594 switch (s
->offset
) {
4595 case ETHTOOL_STAT_EEE_WAKEUP
:
4596 val
= phylink_get_eee_err(pp
->phylink
);
4597 pp
->ethtool_stats
[i
] += val
;
4599 case ETHTOOL_STAT_SKB_ALLOC_ERR
:
4600 pp
->ethtool_stats
[i
] = stats
.skb_alloc_error
;
4602 case ETHTOOL_STAT_REFILL_ERR
:
4603 pp
->ethtool_stats
[i
] = stats
.refill_error
;
4605 case ETHTOOL_XDP_REDIRECT
:
4606 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_redirect
;
4608 case ETHTOOL_XDP_PASS
:
4609 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_pass
;
4611 case ETHTOOL_XDP_DROP
:
4612 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_drop
;
4614 case ETHTOOL_XDP_TX
:
4615 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_tx
;
4617 case ETHTOOL_XDP_TX_ERR
:
4618 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_tx_err
;
4620 case ETHTOOL_XDP_XMIT
:
4621 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_xmit
;
4623 case ETHTOOL_XDP_XMIT_ERR
:
4624 pp
->ethtool_stats
[i
] = stats
.ps
.xdp_xmit_err
;
4632 static void mvneta_ethtool_get_stats(struct net_device
*dev
,
4633 struct ethtool_stats
*stats
, u64
*data
)
4635 struct mvneta_port
*pp
= netdev_priv(dev
);
4638 mvneta_ethtool_update_stats(pp
);
4640 for (i
= 0; i
< ARRAY_SIZE(mvneta_statistics
); i
++)
4641 *data
++ = pp
->ethtool_stats
[i
];
4644 static int mvneta_ethtool_get_sset_count(struct net_device
*dev
, int sset
)
4646 if (sset
== ETH_SS_STATS
)
4647 return ARRAY_SIZE(mvneta_statistics
);
4651 static u32
mvneta_ethtool_get_rxfh_indir_size(struct net_device
*dev
)
4653 return MVNETA_RSS_LU_TABLE_SIZE
;
4656 static int mvneta_ethtool_get_rxnfc(struct net_device
*dev
,
4657 struct ethtool_rxnfc
*info
,
4658 u32
*rules __always_unused
)
4660 switch (info
->cmd
) {
4661 case ETHTOOL_GRXRINGS
:
4662 info
->data
= rxq_number
;
4671 static int mvneta_config_rss(struct mvneta_port
*pp
)
4676 netif_tx_stop_all_queues(pp
->dev
);
4678 on_each_cpu(mvneta_percpu_mask_interrupt
, pp
, true);
4680 if (!pp
->neta_armada3700
) {
4681 /* We have to synchronise on the napi of each CPU */
4682 for_each_online_cpu(cpu
) {
4683 struct mvneta_pcpu_port
*pcpu_port
=
4684 per_cpu_ptr(pp
->ports
, cpu
);
4686 napi_synchronize(&pcpu_port
->napi
);
4687 napi_disable(&pcpu_port
->napi
);
4690 napi_synchronize(&pp
->napi
);
4691 napi_disable(&pp
->napi
);
4694 pp
->rxq_def
= pp
->indir
[0];
4696 /* Update unicast mapping */
4697 mvneta_set_rx_mode(pp
->dev
);
4699 /* Update val of portCfg register accordingly with all RxQueue types */
4700 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(pp
->rxq_def
);
4701 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
4703 /* Update the elected CPU matching the new rxq_def */
4704 spin_lock(&pp
->lock
);
4705 mvneta_percpu_elect(pp
);
4706 spin_unlock(&pp
->lock
);
4708 if (!pp
->neta_armada3700
) {
4709 /* We have to synchronise on the napi of each CPU */
4710 for_each_online_cpu(cpu
) {
4711 struct mvneta_pcpu_port
*pcpu_port
=
4712 per_cpu_ptr(pp
->ports
, cpu
);
4714 napi_enable(&pcpu_port
->napi
);
4717 napi_enable(&pp
->napi
);
4720 netif_tx_start_all_queues(pp
->dev
);
4725 static int mvneta_ethtool_set_rxfh(struct net_device
*dev
, const u32
*indir
,
4726 const u8
*key
, const u8 hfunc
)
4728 struct mvneta_port
*pp
= netdev_priv(dev
);
4730 /* Current code for Armada 3700 doesn't support RSS features yet */
4731 if (pp
->neta_armada3700
)
4734 /* We require at least one supported parameter to be changed
4735 * and no change in any of the unsupported parameters
4738 (hfunc
!= ETH_RSS_HASH_NO_CHANGE
&& hfunc
!= ETH_RSS_HASH_TOP
))
4744 memcpy(pp
->indir
, indir
, MVNETA_RSS_LU_TABLE_SIZE
);
4746 return mvneta_config_rss(pp
);
4749 static int mvneta_ethtool_get_rxfh(struct net_device
*dev
, u32
*indir
, u8
*key
,
4752 struct mvneta_port
*pp
= netdev_priv(dev
);
4754 /* Current code for Armada 3700 doesn't support RSS features yet */
4755 if (pp
->neta_armada3700
)
4759 *hfunc
= ETH_RSS_HASH_TOP
;
4764 memcpy(indir
, pp
->indir
, MVNETA_RSS_LU_TABLE_SIZE
);
4769 static void mvneta_ethtool_get_wol(struct net_device
*dev
,
4770 struct ethtool_wolinfo
*wol
)
4772 struct mvneta_port
*pp
= netdev_priv(dev
);
4774 phylink_ethtool_get_wol(pp
->phylink
, wol
);
4777 static int mvneta_ethtool_set_wol(struct net_device
*dev
,
4778 struct ethtool_wolinfo
*wol
)
4780 struct mvneta_port
*pp
= netdev_priv(dev
);
4783 ret
= phylink_ethtool_set_wol(pp
->phylink
, wol
);
4785 device_set_wakeup_enable(&dev
->dev
, !!wol
->wolopts
);
4790 static int mvneta_ethtool_get_eee(struct net_device
*dev
,
4791 struct ethtool_eee
*eee
)
4793 struct mvneta_port
*pp
= netdev_priv(dev
);
4796 lpi_ctl0
= mvreg_read(pp
, MVNETA_LPI_CTRL_0
);
4798 eee
->eee_enabled
= pp
->eee_enabled
;
4799 eee
->eee_active
= pp
->eee_active
;
4800 eee
->tx_lpi_enabled
= pp
->tx_lpi_enabled
;
4801 eee
->tx_lpi_timer
= (lpi_ctl0
) >> 8; // * scale;
4803 return phylink_ethtool_get_eee(pp
->phylink
, eee
);
4806 static int mvneta_ethtool_set_eee(struct net_device
*dev
,
4807 struct ethtool_eee
*eee
)
4809 struct mvneta_port
*pp
= netdev_priv(dev
);
4812 /* The Armada 37x documents do not give limits for this other than
4813 * it being an 8-bit register. */
4814 if (eee
->tx_lpi_enabled
&& eee
->tx_lpi_timer
> 255)
4817 lpi_ctl0
= mvreg_read(pp
, MVNETA_LPI_CTRL_0
);
4818 lpi_ctl0
&= ~(0xff << 8);
4819 lpi_ctl0
|= eee
->tx_lpi_timer
<< 8;
4820 mvreg_write(pp
, MVNETA_LPI_CTRL_0
, lpi_ctl0
);
4822 pp
->eee_enabled
= eee
->eee_enabled
;
4823 pp
->tx_lpi_enabled
= eee
->tx_lpi_enabled
;
4825 mvneta_set_eee(pp
, eee
->tx_lpi_enabled
&& eee
->eee_enabled
);
4827 return phylink_ethtool_set_eee(pp
->phylink
, eee
);
4830 static const struct net_device_ops mvneta_netdev_ops
= {
4831 .ndo_open
= mvneta_open
,
4832 .ndo_stop
= mvneta_stop
,
4833 .ndo_start_xmit
= mvneta_tx
,
4834 .ndo_set_rx_mode
= mvneta_set_rx_mode
,
4835 .ndo_set_mac_address
= mvneta_set_mac_addr
,
4836 .ndo_change_mtu
= mvneta_change_mtu
,
4837 .ndo_fix_features
= mvneta_fix_features
,
4838 .ndo_get_stats64
= mvneta_get_stats64
,
4839 .ndo_do_ioctl
= mvneta_ioctl
,
4840 .ndo_bpf
= mvneta_xdp
,
4841 .ndo_xdp_xmit
= mvneta_xdp_xmit
,
4844 static const struct ethtool_ops mvneta_eth_tool_ops
= {
4845 .supported_coalesce_params
= ETHTOOL_COALESCE_RX_USECS
|
4846 ETHTOOL_COALESCE_MAX_FRAMES
,
4847 .nway_reset
= mvneta_ethtool_nway_reset
,
4848 .get_link
= ethtool_op_get_link
,
4849 .set_coalesce
= mvneta_ethtool_set_coalesce
,
4850 .get_coalesce
= mvneta_ethtool_get_coalesce
,
4851 .get_drvinfo
= mvneta_ethtool_get_drvinfo
,
4852 .get_ringparam
= mvneta_ethtool_get_ringparam
,
4853 .set_ringparam
= mvneta_ethtool_set_ringparam
,
4854 .get_pauseparam
= mvneta_ethtool_get_pauseparam
,
4855 .set_pauseparam
= mvneta_ethtool_set_pauseparam
,
4856 .get_strings
= mvneta_ethtool_get_strings
,
4857 .get_ethtool_stats
= mvneta_ethtool_get_stats
,
4858 .get_sset_count
= mvneta_ethtool_get_sset_count
,
4859 .get_rxfh_indir_size
= mvneta_ethtool_get_rxfh_indir_size
,
4860 .get_rxnfc
= mvneta_ethtool_get_rxnfc
,
4861 .get_rxfh
= mvneta_ethtool_get_rxfh
,
4862 .set_rxfh
= mvneta_ethtool_set_rxfh
,
4863 .get_link_ksettings
= mvneta_ethtool_get_link_ksettings
,
4864 .set_link_ksettings
= mvneta_ethtool_set_link_ksettings
,
4865 .get_wol
= mvneta_ethtool_get_wol
,
4866 .set_wol
= mvneta_ethtool_set_wol
,
4867 .get_eee
= mvneta_ethtool_get_eee
,
4868 .set_eee
= mvneta_ethtool_set_eee
,
4872 static int mvneta_init(struct device
*dev
, struct mvneta_port
*pp
)
4877 mvneta_port_disable(pp
);
4879 /* Set port default values */
4880 mvneta_defaults_set(pp
);
4882 pp
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(*pp
->txqs
), GFP_KERNEL
);
4886 /* Initialize TX descriptor rings */
4887 for (queue
= 0; queue
< txq_number
; queue
++) {
4888 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
4890 txq
->size
= pp
->tx_ring_size
;
4891 txq
->done_pkts_coal
= MVNETA_TXDONE_COAL_PKTS
;
4894 pp
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(*pp
->rxqs
), GFP_KERNEL
);
4898 /* Create Rx descriptor rings */
4899 for (queue
= 0; queue
< rxq_number
; queue
++) {
4900 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
4902 rxq
->size
= pp
->rx_ring_size
;
4903 rxq
->pkts_coal
= MVNETA_RX_COAL_PKTS
;
4904 rxq
->time_coal
= MVNETA_RX_COAL_USEC
;
4906 = devm_kmalloc_array(pp
->dev
->dev
.parent
,
4908 sizeof(*rxq
->buf_virt_addr
),
4910 if (!rxq
->buf_virt_addr
)
4917 /* platform glue : initialize decoding windows */
4918 static void mvneta_conf_mbus_windows(struct mvneta_port
*pp
,
4919 const struct mbus_dram_target_info
*dram
)
4925 for (i
= 0; i
< 6; i
++) {
4926 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
4927 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
4930 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
4937 for (i
= 0; i
< dram
->num_cs
; i
++) {
4938 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
4940 mvreg_write(pp
, MVNETA_WIN_BASE(i
),
4941 (cs
->base
& 0xffff0000) |
4942 (cs
->mbus_attr
<< 8) |
4943 dram
->mbus_dram_target_id
);
4945 mvreg_write(pp
, MVNETA_WIN_SIZE(i
),
4946 (cs
->size
- 1) & 0xffff0000);
4948 win_enable
&= ~(1 << i
);
4949 win_protect
|= 3 << (2 * i
);
4952 /* For Armada3700 open default 4GB Mbus window, leaving
4953 * arbitration of target/attribute to a different layer
4956 mvreg_write(pp
, MVNETA_WIN_SIZE(0), 0xffff0000);
4957 win_enable
&= ~BIT(0);
4961 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
4962 mvreg_write(pp
, MVNETA_ACCESS_PROTECT_ENABLE
, win_protect
);
4965 /* Power up the port */
4966 static int mvneta_port_power_up(struct mvneta_port
*pp
, int phy_mode
)
4968 /* MAC Cause register should be cleared */
4969 mvreg_write(pp
, MVNETA_UNIT_INTR_CAUSE
, 0);
4971 if (phy_mode
== PHY_INTERFACE_MODE_QSGMII
)
4972 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_QSGMII_SERDES_PROTO
);
4973 else if (phy_mode
== PHY_INTERFACE_MODE_SGMII
||
4974 phy_interface_mode_is_8023z(phy_mode
))
4975 mvreg_write(pp
, MVNETA_SERDES_CFG
, MVNETA_SGMII_SERDES_PROTO
);
4976 else if (!phy_interface_mode_is_rgmii(phy_mode
))
4982 /* Device initialization routine */
4983 static int mvneta_probe(struct platform_device
*pdev
)
4985 struct device_node
*dn
= pdev
->dev
.of_node
;
4986 struct device_node
*bm_node
;
4987 struct mvneta_port
*pp
;
4988 struct net_device
*dev
;
4989 struct phylink
*phylink
;
4991 const char *dt_mac_addr
;
4992 char hw_mac_addr
[ETH_ALEN
];
4993 phy_interface_t phy_mode
;
4994 const char *mac_from
;
4999 dev
= devm_alloc_etherdev_mqs(&pdev
->dev
, sizeof(struct mvneta_port
),
5000 txq_number
, rxq_number
);
5004 dev
->irq
= irq_of_parse_and_map(dn
, 0);
5008 err
= of_get_phy_mode(dn
, &phy_mode
);
5010 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
5014 comphy
= devm_of_phy_get(&pdev
->dev
, dn
, NULL
);
5015 if (comphy
== ERR_PTR(-EPROBE_DEFER
)) {
5016 err
= -EPROBE_DEFER
;
5018 } else if (IS_ERR(comphy
)) {
5022 pp
= netdev_priv(dev
);
5023 spin_lock_init(&pp
->lock
);
5025 pp
->phylink_config
.dev
= &dev
->dev
;
5026 pp
->phylink_config
.type
= PHYLINK_NETDEV
;
5028 phylink
= phylink_create(&pp
->phylink_config
, pdev
->dev
.fwnode
,
5029 phy_mode
, &mvneta_phylink_ops
);
5030 if (IS_ERR(phylink
)) {
5031 err
= PTR_ERR(phylink
);
5035 dev
->tx_queue_len
= MVNETA_MAX_TXD
;
5036 dev
->watchdog_timeo
= 5 * HZ
;
5037 dev
->netdev_ops
= &mvneta_netdev_ops
;
5039 dev
->ethtool_ops
= &mvneta_eth_tool_ops
;
5041 pp
->phylink
= phylink
;
5042 pp
->comphy
= comphy
;
5043 pp
->phy_interface
= phy_mode
;
5046 pp
->rxq_def
= rxq_def
;
5047 pp
->indir
[0] = rxq_def
;
5049 /* Get special SoC configurations */
5050 if (of_device_is_compatible(dn
, "marvell,armada-3700-neta"))
5051 pp
->neta_armada3700
= true;
5053 pp
->clk
= devm_clk_get(&pdev
->dev
, "core");
5054 if (IS_ERR(pp
->clk
))
5055 pp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
5056 if (IS_ERR(pp
->clk
)) {
5057 err
= PTR_ERR(pp
->clk
);
5058 goto err_free_phylink
;
5061 clk_prepare_enable(pp
->clk
);
5063 pp
->clk_bus
= devm_clk_get(&pdev
->dev
, "bus");
5064 if (!IS_ERR(pp
->clk_bus
))
5065 clk_prepare_enable(pp
->clk_bus
);
5067 pp
->base
= devm_platform_ioremap_resource(pdev
, 0);
5068 if (IS_ERR(pp
->base
)) {
5069 err
= PTR_ERR(pp
->base
);
5073 /* Alloc per-cpu port structure */
5074 pp
->ports
= alloc_percpu(struct mvneta_pcpu_port
);
5080 /* Alloc per-cpu stats */
5081 pp
->stats
= netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats
);
5084 goto err_free_ports
;
5087 dt_mac_addr
= of_get_mac_address(dn
);
5088 if (!IS_ERR(dt_mac_addr
)) {
5089 mac_from
= "device tree";
5090 ether_addr_copy(dev
->dev_addr
, dt_mac_addr
);
5092 mvneta_get_mac_addr(pp
, hw_mac_addr
);
5093 if (is_valid_ether_addr(hw_mac_addr
)) {
5094 mac_from
= "hardware";
5095 memcpy(dev
->dev_addr
, hw_mac_addr
, ETH_ALEN
);
5097 mac_from
= "random";
5098 eth_hw_addr_random(dev
);
5102 if (!of_property_read_u32(dn
, "tx-csum-limit", &tx_csum_limit
)) {
5103 if (tx_csum_limit
< 0 ||
5104 tx_csum_limit
> MVNETA_TX_CSUM_MAX_SIZE
) {
5105 tx_csum_limit
= MVNETA_TX_CSUM_DEF_SIZE
;
5106 dev_info(&pdev
->dev
,
5107 "Wrong TX csum limit in DT, set to %dB\n",
5108 MVNETA_TX_CSUM_DEF_SIZE
);
5110 } else if (of_device_is_compatible(dn
, "marvell,armada-370-neta")) {
5111 tx_csum_limit
= MVNETA_TX_CSUM_DEF_SIZE
;
5113 tx_csum_limit
= MVNETA_TX_CSUM_MAX_SIZE
;
5116 pp
->tx_csum_limit
= tx_csum_limit
;
5118 pp
->dram_target_info
= mv_mbus_dram_info();
5119 /* Armada3700 requires setting default configuration of Mbus
5120 * windows, however without using filled mbus_dram_target_info
5123 if (pp
->dram_target_info
|| pp
->neta_armada3700
)
5124 mvneta_conf_mbus_windows(pp
, pp
->dram_target_info
);
5126 pp
->tx_ring_size
= MVNETA_MAX_TXD
;
5127 pp
->rx_ring_size
= MVNETA_MAX_RXD
;
5130 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5132 pp
->id
= global_port_id
++;
5134 /* Obtain access to BM resources if enabled and already initialized */
5135 bm_node
= of_parse_phandle(dn
, "buffer-manager", 0);
5137 pp
->bm_priv
= mvneta_bm_get(bm_node
);
5139 err
= mvneta_bm_port_init(pdev
, pp
);
5141 dev_info(&pdev
->dev
,
5142 "use SW buffer management\n");
5143 mvneta_bm_put(pp
->bm_priv
);
5147 /* Set RX packet offset correction for platforms, whose
5148 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
5149 * platforms and 0B for 32-bit ones.
5151 pp
->rx_offset_correction
= max(0,
5153 MVNETA_RX_PKT_OFFSET_CORRECTION
);
5155 of_node_put(bm_node
);
5157 /* sw buffer management */
5159 pp
->rx_offset_correction
= MVNETA_SKB_HEADROOM
;
5161 err
= mvneta_init(&pdev
->dev
, pp
);
5165 err
= mvneta_port_power_up(pp
, phy_mode
);
5167 dev_err(&pdev
->dev
, "can't power up port\n");
5171 /* Armada3700 network controller does not support per-cpu
5172 * operation, so only single NAPI should be initialized.
5174 if (pp
->neta_armada3700
) {
5175 netif_napi_add(dev
, &pp
->napi
, mvneta_poll
, NAPI_POLL_WEIGHT
);
5177 for_each_present_cpu(cpu
) {
5178 struct mvneta_pcpu_port
*port
=
5179 per_cpu_ptr(pp
->ports
, cpu
);
5181 netif_napi_add(dev
, &port
->napi
, mvneta_poll
,
5187 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
5188 NETIF_F_TSO
| NETIF_F_RXCSUM
;
5189 dev
->hw_features
|= dev
->features
;
5190 dev
->vlan_features
|= dev
->features
;
5191 dev
->priv_flags
|= IFF_LIVE_ADDR_CHANGE
;
5192 dev
->gso_max_segs
= MVNETA_MAX_TSO_SEGS
;
5194 /* MTU range: 68 - 9676 */
5195 dev
->min_mtu
= ETH_MIN_MTU
;
5196 /* 9676 == 9700 - 20 and rounding to 8 */
5197 dev
->max_mtu
= 9676;
5199 err
= register_netdev(dev
);
5201 dev_err(&pdev
->dev
, "failed to register\n");
5205 netdev_info(dev
, "Using %s mac address %pM\n", mac_from
,
5208 platform_set_drvdata(pdev
, pp
->dev
);
5214 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
5215 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
,
5217 mvneta_bm_put(pp
->bm_priv
);
5219 free_percpu(pp
->stats
);
5221 free_percpu(pp
->ports
);
5223 clk_disable_unprepare(pp
->clk_bus
);
5224 clk_disable_unprepare(pp
->clk
);
5227 phylink_destroy(pp
->phylink
);
5229 irq_dispose_mapping(dev
->irq
);
5233 /* Device removal routine */
5234 static int mvneta_remove(struct platform_device
*pdev
)
5236 struct net_device
*dev
= platform_get_drvdata(pdev
);
5237 struct mvneta_port
*pp
= netdev_priv(dev
);
5239 unregister_netdev(dev
);
5240 clk_disable_unprepare(pp
->clk_bus
);
5241 clk_disable_unprepare(pp
->clk
);
5242 free_percpu(pp
->ports
);
5243 free_percpu(pp
->stats
);
5244 irq_dispose_mapping(dev
->irq
);
5245 phylink_destroy(pp
->phylink
);
5248 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_long
, 1 << pp
->id
);
5249 mvneta_bm_pool_destroy(pp
->bm_priv
, pp
->pool_short
,
5251 mvneta_bm_put(pp
->bm_priv
);
5257 #ifdef CONFIG_PM_SLEEP
5258 static int mvneta_suspend(struct device
*device
)
5261 struct net_device
*dev
= dev_get_drvdata(device
);
5262 struct mvneta_port
*pp
= netdev_priv(dev
);
5264 if (!netif_running(dev
))
5267 if (!pp
->neta_armada3700
) {
5268 spin_lock(&pp
->lock
);
5269 pp
->is_stopped
= true;
5270 spin_unlock(&pp
->lock
);
5272 cpuhp_state_remove_instance_nocalls(online_hpstate
,
5274 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
5279 mvneta_stop_dev(pp
);
5282 for (queue
= 0; queue
< rxq_number
; queue
++) {
5283 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
5285 mvneta_rxq_drop_pkts(pp
, rxq
);
5288 for (queue
= 0; queue
< txq_number
; queue
++) {
5289 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
5291 mvneta_txq_hw_deinit(pp
, txq
);
5295 netif_device_detach(dev
);
5296 clk_disable_unprepare(pp
->clk_bus
);
5297 clk_disable_unprepare(pp
->clk
);
5302 static int mvneta_resume(struct device
*device
)
5304 struct platform_device
*pdev
= to_platform_device(device
);
5305 struct net_device
*dev
= dev_get_drvdata(device
);
5306 struct mvneta_port
*pp
= netdev_priv(dev
);
5309 clk_prepare_enable(pp
->clk
);
5310 if (!IS_ERR(pp
->clk_bus
))
5311 clk_prepare_enable(pp
->clk_bus
);
5312 if (pp
->dram_target_info
|| pp
->neta_armada3700
)
5313 mvneta_conf_mbus_windows(pp
, pp
->dram_target_info
);
5315 err
= mvneta_bm_port_init(pdev
, pp
);
5317 dev_info(&pdev
->dev
, "use SW buffer management\n");
5318 pp
->rx_offset_correction
= MVNETA_SKB_HEADROOM
;
5322 mvneta_defaults_set(pp
);
5323 err
= mvneta_port_power_up(pp
, pp
->phy_interface
);
5325 dev_err(device
, "can't power up port\n");
5329 netif_device_attach(dev
);
5331 if (!netif_running(dev
))
5334 for (queue
= 0; queue
< rxq_number
; queue
++) {
5335 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
5337 rxq
->next_desc_to_proc
= 0;
5338 mvneta_rxq_hw_init(pp
, rxq
);
5341 for (queue
= 0; queue
< txq_number
; queue
++) {
5342 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
5344 txq
->next_desc_to_proc
= 0;
5345 mvneta_txq_hw_init(pp
, txq
);
5348 if (!pp
->neta_armada3700
) {
5349 spin_lock(&pp
->lock
);
5350 pp
->is_stopped
= false;
5351 spin_unlock(&pp
->lock
);
5352 cpuhp_state_add_instance_nocalls(online_hpstate
,
5354 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD
,
5359 mvneta_start_dev(pp
);
5361 mvneta_set_rx_mode(dev
);
5367 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops
, mvneta_suspend
, mvneta_resume
);
5369 static const struct of_device_id mvneta_match
[] = {
5370 { .compatible
= "marvell,armada-370-neta" },
5371 { .compatible
= "marvell,armada-xp-neta" },
5372 { .compatible
= "marvell,armada-3700-neta" },
5375 MODULE_DEVICE_TABLE(of
, mvneta_match
);
5377 static struct platform_driver mvneta_driver
= {
5378 .probe
= mvneta_probe
,
5379 .remove
= mvneta_remove
,
5381 .name
= MVNETA_DRIVER_NAME
,
5382 .of_match_table
= mvneta_match
,
5383 .pm
= &mvneta_pm_ops
,
5387 static int __init
mvneta_driver_init(void)
5391 ret
= cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN
, "net/mvneta:online",
5393 mvneta_cpu_down_prepare
);
5396 online_hpstate
= ret
;
5397 ret
= cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD
, "net/mvneta:dead",
5398 NULL
, mvneta_cpu_dead
);
5402 ret
= platform_driver_register(&mvneta_driver
);
5408 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD
);
5410 cpuhp_remove_multi_state(online_hpstate
);
5414 module_init(mvneta_driver_init
);
5416 static void __exit
mvneta_driver_exit(void)
5418 platform_driver_unregister(&mvneta_driver
);
5419 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD
);
5420 cpuhp_remove_multi_state(online_hpstate
);
5422 module_exit(mvneta_driver_exit
);
5424 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
5425 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
5426 MODULE_LICENSE("GPL");
5428 module_param(rxq_number
, int, 0444);
5429 module_param(txq_number
, int, 0444);
5431 module_param(rxq_def
, int, 0444);
5432 module_param(rx_copybreak
, int, 0644);