2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_NO_DESC_SWAP 0x0
83 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
84 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
85 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_TYPE_PRIO 0x24bc
92 #define MVNETA_FORCE_UNI BIT(21)
93 #define MVNETA_TXQ_CMD_1 0x24e4
94 #define MVNETA_TXQ_CMD 0x2448
95 #define MVNETA_TXQ_DISABLE_SHIFT 8
96 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
97 #define MVNETA_ACC_MODE 0x2500
98 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
99 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
100 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
101 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
102 #define MVNETA_INTR_NEW_CAUSE 0x25a0
103 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
104 #define MVNETA_INTR_NEW_MASK 0x25a4
105 #define MVNETA_INTR_OLD_CAUSE 0x25a8
106 #define MVNETA_INTR_OLD_MASK 0x25ac
107 #define MVNETA_INTR_MISC_CAUSE 0x25b0
108 #define MVNETA_INTR_MISC_MASK 0x25b4
109 #define MVNETA_INTR_ENABLE 0x25b8
110 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
111 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000
112 #define MVNETA_RXQ_CMD 0x2680
113 #define MVNETA_RXQ_DISABLE_SHIFT 8
114 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
115 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
116 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
117 #define MVNETA_GMAC_CTRL_0 0x2c00
118 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
119 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
120 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
121 #define MVNETA_GMAC_CTRL_2 0x2c08
122 #define MVNETA_GMAC2_PSC_ENABLE BIT(3)
123 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
124 #define MVNETA_GMAC2_PORT_RESET BIT(6)
125 #define MVNETA_GMAC_STATUS 0x2c10
126 #define MVNETA_GMAC_LINK_UP BIT(0)
127 #define MVNETA_GMAC_SPEED_1000 BIT(1)
128 #define MVNETA_GMAC_SPEED_100 BIT(2)
129 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
130 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
131 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
132 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
133 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
134 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
135 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
136 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
137 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
138 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
139 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
140 #define MVNETA_MIB_COUNTERS_BASE 0x3080
141 #define MVNETA_MIB_LATE_COLLISION 0x7c
142 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
143 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
144 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
145 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
146 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
147 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
148 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
149 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
150 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
151 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
152 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
153 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
154 #define MVNETA_PORT_TX_RESET 0x3cf0
155 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
156 #define MVNETA_TX_MTU 0x3e0c
157 #define MVNETA_TX_TOKEN_SIZE 0x3e14
158 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
159 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
160 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
162 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
164 /* Descriptor ring Macros */
165 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
166 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
168 /* Various constants */
171 #define MVNETA_TXDONE_COAL_PKTS 16
172 #define MVNETA_RX_COAL_PKTS 32
173 #define MVNETA_RX_COAL_USEC 100
176 #define MVNETA_TX_DONE_TIMER_PERIOD 10
178 /* Napi polling weight */
179 #define MVNETA_RX_POLL_WEIGHT 64
181 /* The two bytes Marvell header. Either contains a special value used
182 * by Marvell switches when a specific hardware mode is enabled (not
183 * supported by this driver) or is filled automatically by zeroes on
184 * the RX side. Those two bytes being at the front of the Ethernet
185 * header, they allow to have the IP header aligned on a 4 bytes
186 * boundary automatically: the hardware skips those two bytes on its
189 #define MVNETA_MH_SIZE 2
191 #define MVNETA_VLAN_TAG_LEN 4
193 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
194 #define MVNETA_TX_CSUM_MAX_SIZE 9800
195 #define MVNETA_ACC_MODE_EXT 1
197 /* Timeout constants */
198 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
199 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
200 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
202 #define MVNETA_TX_MTU_MAX 0x3ffff
204 /* Max number of Rx descriptors */
205 #define MVNETA_MAX_RXD 128
207 /* Max number of Tx descriptors */
208 #define MVNETA_MAX_TXD 532
210 /* descriptor aligned size */
211 #define MVNETA_DESC_ALIGNED_SIZE 32
213 #define MVNETA_RX_PKT_SIZE(mtu) \
214 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
215 ETH_HLEN + ETH_FCS_LEN, \
216 MVNETA_CPU_D_CACHE_LINE_SIZE)
218 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
220 struct mvneta_stats
{
221 struct u64_stats_sync syncp
;
229 struct mvneta_rx_queue
*rxqs
;
230 struct mvneta_tx_queue
*txqs
;
231 struct timer_list tx_done_timer
;
232 struct net_device
*dev
;
235 struct napi_struct napi
;
239 #define MVNETA_F_TX_DONE_TIMER_BIT 0
249 struct mvneta_stats tx_stats
;
250 struct mvneta_stats rx_stats
;
252 struct mii_bus
*mii_bus
;
253 struct phy_device
*phy_dev
;
254 phy_interface_t phy_interface
;
255 struct device_node
*phy_node
;
261 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
262 * layout of the transmit and reception DMA descriptors, and their
263 * layout is therefore defined by the hardware design
265 struct mvneta_tx_desc
{
266 u32 command
; /* Options used by HW for packet transmitting.*/
267 #define MVNETA_TX_L3_OFF_SHIFT 0
268 #define MVNETA_TX_IP_HLEN_SHIFT 8
269 #define MVNETA_TX_L4_UDP BIT(16)
270 #define MVNETA_TX_L3_IP6 BIT(17)
271 #define MVNETA_TXD_IP_CSUM BIT(18)
272 #define MVNETA_TXD_Z_PAD BIT(19)
273 #define MVNETA_TXD_L_DESC BIT(20)
274 #define MVNETA_TXD_F_DESC BIT(21)
275 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
276 MVNETA_TXD_L_DESC | \
278 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
279 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
281 u16 reserverd1
; /* csum_l4 (for future use) */
282 u16 data_size
; /* Data size of transmitted packet in bytes */
283 u32 buf_phys_addr
; /* Physical addr of transmitted buffer */
284 u32 reserved2
; /* hw_cmd - (for future use, PMT) */
285 u32 reserved3
[4]; /* Reserved - (for future use) */
288 struct mvneta_rx_desc
{
289 u32 status
; /* Info about received packet */
290 #define MVNETA_RXD_ERR_CRC 0x0
291 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
292 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
293 #define MVNETA_RXD_ERR_LEN BIT(18)
294 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
295 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
296 #define MVNETA_RXD_L3_IP4 BIT(25)
297 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
298 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
300 u16 reserved1
; /* pnc_info - (for future use, PnC) */
301 u16 data_size
; /* Size of received packet in bytes */
302 u32 buf_phys_addr
; /* Physical address of the buffer */
303 u32 reserved2
; /* pnc_flow_id (for future use, PnC) */
304 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
305 u16 reserved3
; /* prefetch_cmd, for future use */
306 u16 reserved4
; /* csum_l4 - (for future use, PnC) */
307 u32 reserved5
; /* pnc_extra PnC (for future use, PnC) */
308 u32 reserved6
; /* hw_cmd (for future use, PnC and HWF) */
311 struct mvneta_tx_queue
{
312 /* Number of this TX queue, in the range 0-7 */
315 /* Number of TX DMA descriptors in the descriptor ring */
318 /* Number of currently used TX DMA descriptor in the
323 /* Array of transmitted skb */
324 struct sk_buff
**tx_skb
;
326 /* Index of last TX DMA descriptor that was inserted */
329 /* Index of the TX DMA descriptor to be cleaned up */
334 /* Virtual address of the TX DMA descriptors array */
335 struct mvneta_tx_desc
*descs
;
337 /* DMA address of the TX DMA descriptors array */
338 dma_addr_t descs_phys
;
340 /* Index of the last TX DMA descriptor */
343 /* Index of the next TX DMA descriptor to process */
344 int next_desc_to_proc
;
347 struct mvneta_rx_queue
{
348 /* rx queue number, in the range 0-7 */
351 /* num of rx descriptors in the rx descriptor ring */
354 /* counter of times when mvneta_refill() failed */
360 /* Virtual address of the RX DMA descriptors array */
361 struct mvneta_rx_desc
*descs
;
363 /* DMA address of the RX DMA descriptors array */
364 dma_addr_t descs_phys
;
366 /* Index of the last RX DMA descriptor */
369 /* Index of the next RX DMA descriptor to process */
370 int next_desc_to_proc
;
373 static int rxq_number
= 8;
374 static int txq_number
= 8;
378 #define MVNETA_DRIVER_NAME "mvneta"
379 #define MVNETA_DRIVER_VERSION "1.0"
381 /* Utility/helper methods */
383 /* Write helper method */
384 static void mvreg_write(struct mvneta_port
*pp
, u32 offset
, u32 data
)
386 writel(data
, pp
->base
+ offset
);
389 /* Read helper method */
390 static u32
mvreg_read(struct mvneta_port
*pp
, u32 offset
)
392 return readl(pp
->base
+ offset
);
395 /* Increment txq get counter */
396 static void mvneta_txq_inc_get(struct mvneta_tx_queue
*txq
)
398 txq
->txq_get_index
++;
399 if (txq
->txq_get_index
== txq
->size
)
400 txq
->txq_get_index
= 0;
403 /* Increment txq put counter */
404 static void mvneta_txq_inc_put(struct mvneta_tx_queue
*txq
)
406 txq
->txq_put_index
++;
407 if (txq
->txq_put_index
== txq
->size
)
408 txq
->txq_put_index
= 0;
412 /* Clear all MIB counters */
413 static void mvneta_mib_counters_clear(struct mvneta_port
*pp
)
418 /* Perform dummy reads from MIB counters */
419 for (i
= 0; i
< MVNETA_MIB_LATE_COLLISION
; i
+= 4)
420 dummy
= mvreg_read(pp
, (MVNETA_MIB_COUNTERS_BASE
+ i
));
423 /* Get System Network Statistics */
424 struct rtnl_link_stats64
*mvneta_get_stats64(struct net_device
*dev
,
425 struct rtnl_link_stats64
*stats
)
427 struct mvneta_port
*pp
= netdev_priv(dev
);
430 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
433 start
= u64_stats_fetch_begin_bh(&pp
->rx_stats
.syncp
);
434 stats
->rx_packets
= pp
->rx_stats
.packets
;
435 stats
->rx_bytes
= pp
->rx_stats
.bytes
;
436 } while (u64_stats_fetch_retry_bh(&pp
->rx_stats
.syncp
, start
));
440 start
= u64_stats_fetch_begin_bh(&pp
->tx_stats
.syncp
);
441 stats
->tx_packets
= pp
->tx_stats
.packets
;
442 stats
->tx_bytes
= pp
->tx_stats
.bytes
;
443 } while (u64_stats_fetch_retry_bh(&pp
->tx_stats
.syncp
, start
));
445 stats
->rx_errors
= dev
->stats
.rx_errors
;
446 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
448 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
453 /* Rx descriptors helper methods */
455 /* Checks whether the given RX descriptor is both the first and the
456 * last descriptor for the RX packet. Each RX packet is currently
457 * received through a single RX descriptor, so not having each RX
458 * descriptor with its first and last bits set is an error
460 static int mvneta_rxq_desc_is_first_last(struct mvneta_rx_desc
*desc
)
462 return (desc
->status
& MVNETA_RXD_FIRST_LAST_DESC
) ==
463 MVNETA_RXD_FIRST_LAST_DESC
;
466 /* Add number of descriptors ready to receive new packets */
467 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port
*pp
,
468 struct mvneta_rx_queue
*rxq
,
471 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
474 while (ndescs
> MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
) {
475 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
476 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
<<
477 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
478 ndescs
-= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX
;
481 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
),
482 (ndescs
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
));
485 /* Get number of RX descriptors occupied by received packets */
486 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port
*pp
,
487 struct mvneta_rx_queue
*rxq
)
491 val
= mvreg_read(pp
, MVNETA_RXQ_STATUS_REG(rxq
->id
));
492 return val
& MVNETA_RXQ_OCCUPIED_ALL_MASK
;
495 /* Update num of rx desc called upon return from rx path or
496 * from mvneta_rxq_drop_pkts().
498 static void mvneta_rxq_desc_num_update(struct mvneta_port
*pp
,
499 struct mvneta_rx_queue
*rxq
,
500 int rx_done
, int rx_filled
)
504 if ((rx_done
<= 0xff) && (rx_filled
<= 0xff)) {
506 (rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
);
507 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
511 /* Only 255 descriptors can be added at once */
512 while ((rx_done
> 0) || (rx_filled
> 0)) {
513 if (rx_done
<= 0xff) {
520 if (rx_filled
<= 0xff) {
521 val
|= rx_filled
<< MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
524 val
|= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT
;
527 mvreg_write(pp
, MVNETA_RXQ_STATUS_UPDATE_REG(rxq
->id
), val
);
531 /* Get pointer to next RX descriptor to be processed by SW */
532 static struct mvneta_rx_desc
*
533 mvneta_rxq_next_desc_get(struct mvneta_rx_queue
*rxq
)
535 int rx_desc
= rxq
->next_desc_to_proc
;
537 rxq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(rxq
, rx_desc
);
538 return rxq
->descs
+ rx_desc
;
541 /* Change maximum receive size of the port. */
542 static void mvneta_max_rx_size_set(struct mvneta_port
*pp
, int max_rx_size
)
546 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
547 val
&= ~MVNETA_GMAC_MAX_RX_SIZE_MASK
;
548 val
|= ((max_rx_size
- MVNETA_MH_SIZE
) / 2) <<
549 MVNETA_GMAC_MAX_RX_SIZE_SHIFT
;
550 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
554 /* Set rx queue offset */
555 static void mvneta_rxq_offset_set(struct mvneta_port
*pp
,
556 struct mvneta_rx_queue
*rxq
,
561 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
562 val
&= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK
;
565 val
|= MVNETA_RXQ_PKT_OFFSET_MASK(offset
>> 3);
566 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
570 /* Tx descriptors helper methods */
572 /* Update HW with number of TX descriptors to be sent */
573 static void mvneta_txq_pend_desc_add(struct mvneta_port
*pp
,
574 struct mvneta_tx_queue
*txq
,
579 /* Only 255 descriptors can be added at once ; Assume caller
580 * process TX desriptors in quanta less than 256
583 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
586 /* Get pointer to next TX descriptor to be processed (send) by HW */
587 static struct mvneta_tx_desc
*
588 mvneta_txq_next_desc_get(struct mvneta_tx_queue
*txq
)
590 int tx_desc
= txq
->next_desc_to_proc
;
592 txq
->next_desc_to_proc
= MVNETA_QUEUE_NEXT_DESC(txq
, tx_desc
);
593 return txq
->descs
+ tx_desc
;
596 /* Release the last allocated TX descriptor. Useful to handle DMA
597 * mapping failures in the TX path.
599 static void mvneta_txq_desc_put(struct mvneta_tx_queue
*txq
)
601 if (txq
->next_desc_to_proc
== 0)
602 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
604 txq
->next_desc_to_proc
--;
607 /* Set rxq buf size */
608 static void mvneta_rxq_buf_size_set(struct mvneta_port
*pp
,
609 struct mvneta_rx_queue
*rxq
,
614 val
= mvreg_read(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
));
616 val
&= ~MVNETA_RXQ_BUF_SIZE_MASK
;
617 val
|= ((buf_size
>> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT
);
619 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), val
);
622 /* Disable buffer management (BM) */
623 static void mvneta_rxq_bm_disable(struct mvneta_port
*pp
,
624 struct mvneta_rx_queue
*rxq
)
628 val
= mvreg_read(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
));
629 val
&= ~MVNETA_RXQ_HW_BUF_ALLOC
;
630 mvreg_write(pp
, MVNETA_RXQ_CONFIG_REG(rxq
->id
), val
);
635 /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */
636 static void mvneta_gmac_rgmii_set(struct mvneta_port
*pp
, int enable
)
640 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
643 val
|= MVNETA_GMAC2_PORT_RGMII
;
645 val
&= ~MVNETA_GMAC2_PORT_RGMII
;
647 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, val
);
650 /* Config SGMII port */
651 static void mvneta_port_sgmii_config(struct mvneta_port
*pp
)
655 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
656 val
|= MVNETA_GMAC2_PSC_ENABLE
;
657 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, val
);
660 /* Start the Ethernet port RX and TX activity */
661 static void mvneta_port_up(struct mvneta_port
*pp
)
666 /* Enable all initialized TXs. */
667 mvneta_mib_counters_clear(pp
);
669 for (queue
= 0; queue
< txq_number
; queue
++) {
670 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
671 if (txq
->descs
!= NULL
)
672 q_map
|= (1 << queue
);
674 mvreg_write(pp
, MVNETA_TXQ_CMD
, q_map
);
676 /* Enable all initialized RXQs. */
678 for (queue
= 0; queue
< rxq_number
; queue
++) {
679 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
680 if (rxq
->descs
!= NULL
)
681 q_map
|= (1 << queue
);
684 mvreg_write(pp
, MVNETA_RXQ_CMD
, q_map
);
687 /* Stop the Ethernet port activity */
688 static void mvneta_port_down(struct mvneta_port
*pp
)
693 /* Stop Rx port activity. Check port Rx activity. */
694 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
) & MVNETA_RXQ_ENABLE_MASK
;
696 /* Issue stop command for active channels only */
698 mvreg_write(pp
, MVNETA_RXQ_CMD
,
699 val
<< MVNETA_RXQ_DISABLE_SHIFT
);
701 /* Wait for all Rx activity to terminate. */
704 if (count
++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC
) {
706 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
712 val
= mvreg_read(pp
, MVNETA_RXQ_CMD
);
713 } while (val
& 0xff);
715 /* Stop Tx port activity. Check port Tx activity. Issue stop
716 * command for active channels only
718 val
= (mvreg_read(pp
, MVNETA_TXQ_CMD
)) & MVNETA_TXQ_ENABLE_MASK
;
721 mvreg_write(pp
, MVNETA_TXQ_CMD
,
722 (val
<< MVNETA_TXQ_DISABLE_SHIFT
));
724 /* Wait for all Tx activity to terminate. */
727 if (count
++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC
) {
729 "TIMEOUT for TX stopped status=0x%08x\n",
735 /* Check TX Command reg that all Txqs are stopped */
736 val
= mvreg_read(pp
, MVNETA_TXQ_CMD
);
738 } while (val
& 0xff);
740 /* Double check to verify that TX FIFO is empty */
743 if (count
++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT
) {
745 "TX FIFO empty timeout status=0x08%x\n",
751 val
= mvreg_read(pp
, MVNETA_PORT_STATUS
);
752 } while (!(val
& MVNETA_TX_FIFO_EMPTY
) &&
753 (val
& MVNETA_TX_IN_PRGRS
));
758 /* Enable the port by setting the port enable bit of the MAC control register */
759 static void mvneta_port_enable(struct mvneta_port
*pp
)
764 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
765 val
|= MVNETA_GMAC0_PORT_ENABLE
;
766 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
769 /* Disable the port and wait for about 200 usec before retuning */
770 static void mvneta_port_disable(struct mvneta_port
*pp
)
774 /* Reset the Enable bit in the Serial Control Register */
775 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_0
);
776 val
&= ~MVNETA_GMAC0_PORT_ENABLE
;
777 mvreg_write(pp
, MVNETA_GMAC_CTRL_0
, val
);
782 /* Multicast tables methods */
784 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
785 static void mvneta_set_ucast_table(struct mvneta_port
*pp
, int queue
)
793 val
= 0x1 | (queue
<< 1);
794 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
797 for (offset
= 0; offset
<= 0xc; offset
+= 4)
798 mvreg_write(pp
, MVNETA_DA_FILT_UCAST_BASE
+ offset
, val
);
801 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
802 static void mvneta_set_special_mcast_table(struct mvneta_port
*pp
, int queue
)
810 val
= 0x1 | (queue
<< 1);
811 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
814 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
815 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ offset
, val
);
819 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
820 static void mvneta_set_other_mcast_table(struct mvneta_port
*pp
, int queue
)
826 memset(pp
->mcast_count
, 0, sizeof(pp
->mcast_count
));
829 memset(pp
->mcast_count
, 1, sizeof(pp
->mcast_count
));
830 val
= 0x1 | (queue
<< 1);
831 val
|= (val
<< 24) | (val
<< 16) | (val
<< 8);
834 for (offset
= 0; offset
<= 0xfc; offset
+= 4)
835 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ offset
, val
);
838 /* This method sets defaults to the NETA port:
839 * Clears interrupt Cause and Mask registers.
840 * Clears all MAC tables.
841 * Sets defaults to all registers.
842 * Resets RX and TX descriptor rings.
844 * This method can be called after mvneta_port_down() to return the port
845 * settings to defaults.
847 static void mvneta_defaults_set(struct mvneta_port
*pp
)
853 /* Clear all Cause registers */
854 mvreg_write(pp
, MVNETA_INTR_NEW_CAUSE
, 0);
855 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
856 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
858 /* Mask all interrupts */
859 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
860 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
861 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
862 mvreg_write(pp
, MVNETA_INTR_ENABLE
, 0);
864 /* Enable MBUS Retry bit16 */
865 mvreg_write(pp
, MVNETA_MBUS_RETRY
, 0x20);
867 /* Set CPU queue access map - all CPUs have access to all RX
868 * queues and to all TX queues
870 for (cpu
= 0; cpu
< CONFIG_NR_CPUS
; cpu
++)
871 mvreg_write(pp
, MVNETA_CPU_MAP(cpu
),
872 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK
|
873 MVNETA_CPU_TXQ_ACCESS_ALL_MASK
));
875 /* Reset RX and TX DMAs */
876 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
877 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
879 /* Disable Legacy WRR, Disable EJP, Release from reset */
880 mvreg_write(pp
, MVNETA_TXQ_CMD_1
, 0);
881 for (queue
= 0; queue
< txq_number
; queue
++) {
882 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(queue
), 0);
883 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(queue
), 0);
886 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
887 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
889 /* Set Port Acceleration Mode */
890 val
= MVNETA_ACC_MODE_EXT
;
891 mvreg_write(pp
, MVNETA_ACC_MODE
, val
);
893 /* Update val of portCfg register accordingly with all RxQueue types */
894 val
= MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def
);
895 mvreg_write(pp
, MVNETA_PORT_CONFIG
, val
);
898 mvreg_write(pp
, MVNETA_PORT_CONFIG_EXTEND
, val
);
899 mvreg_write(pp
, MVNETA_RX_MIN_FRAME_SIZE
, 64);
901 /* Build PORT_SDMA_CONFIG_REG */
904 /* Default burst size */
905 val
|= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
906 val
|= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16
);
908 val
|= (MVNETA_RX_NO_DATA_SWAP
| MVNETA_TX_NO_DATA_SWAP
|
909 MVNETA_NO_DESC_SWAP
);
911 /* Assign port SDMA configuration */
912 mvreg_write(pp
, MVNETA_SDMA_CONFIG
, val
);
914 mvneta_set_ucast_table(pp
, -1);
915 mvneta_set_special_mcast_table(pp
, -1);
916 mvneta_set_other_mcast_table(pp
, -1);
918 /* Set port interrupt enable register - default enable all */
919 mvreg_write(pp
, MVNETA_INTR_ENABLE
,
920 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
921 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK
));
924 /* Set max sizes for tx queues */
925 static void mvneta_txq_max_tx_size_set(struct mvneta_port
*pp
, int max_tx_size
)
931 mtu
= max_tx_size
* 8;
932 if (mtu
> MVNETA_TX_MTU_MAX
)
933 mtu
= MVNETA_TX_MTU_MAX
;
936 val
= mvreg_read(pp
, MVNETA_TX_MTU
);
937 val
&= ~MVNETA_TX_MTU_MAX
;
939 mvreg_write(pp
, MVNETA_TX_MTU
, val
);
941 /* TX token size and all TXQs token size must be larger that MTU */
942 val
= mvreg_read(pp
, MVNETA_TX_TOKEN_SIZE
);
944 size
= val
& MVNETA_TX_TOKEN_SIZE_MAX
;
947 val
&= ~MVNETA_TX_TOKEN_SIZE_MAX
;
949 mvreg_write(pp
, MVNETA_TX_TOKEN_SIZE
, val
);
951 for (queue
= 0; queue
< txq_number
; queue
++) {
952 val
= mvreg_read(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
));
954 size
= val
& MVNETA_TXQ_TOKEN_SIZE_MAX
;
957 val
&= ~MVNETA_TXQ_TOKEN_SIZE_MAX
;
959 mvreg_write(pp
, MVNETA_TXQ_TOKEN_SIZE_REG(queue
), val
);
964 /* Set unicast address */
965 static void mvneta_set_ucast_addr(struct mvneta_port
*pp
, u8 last_nibble
,
968 unsigned int unicast_reg
;
969 unsigned int tbl_offset
;
970 unsigned int reg_offset
;
972 /* Locate the Unicast table entry */
973 last_nibble
= (0xf & last_nibble
);
975 /* offset from unicast tbl base */
976 tbl_offset
= (last_nibble
/ 4) * 4;
978 /* offset within the above reg */
979 reg_offset
= last_nibble
% 4;
981 unicast_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
));
984 /* Clear accepts frame bit at specified unicast DA tbl entry */
985 unicast_reg
&= ~(0xff << (8 * reg_offset
));
987 unicast_reg
&= ~(0xff << (8 * reg_offset
));
988 unicast_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
991 mvreg_write(pp
, (MVNETA_DA_FILT_UCAST_BASE
+ tbl_offset
), unicast_reg
);
994 /* Set mac address */
995 static void mvneta_mac_addr_set(struct mvneta_port
*pp
, unsigned char *addr
,
1002 mac_l
= (addr
[4] << 8) | (addr
[5]);
1003 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) |
1004 (addr
[2] << 8) | (addr
[3] << 0);
1006 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, mac_l
);
1007 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, mac_h
);
1010 /* Accept frames of this address */
1011 mvneta_set_ucast_addr(pp
, addr
[5], queue
);
1014 /* Set the number of packets that will be received before RX interrupt
1015 * will be generated by HW.
1017 static void mvneta_rx_pkts_coal_set(struct mvneta_port
*pp
,
1018 struct mvneta_rx_queue
*rxq
, u32 value
)
1020 mvreg_write(pp
, MVNETA_RXQ_THRESHOLD_REG(rxq
->id
),
1021 value
| MVNETA_RXQ_NON_OCCUPIED(0));
1022 rxq
->pkts_coal
= value
;
1025 /* Set the time delay in usec before RX interrupt will be generated by
1028 static void mvneta_rx_time_coal_set(struct mvneta_port
*pp
,
1029 struct mvneta_rx_queue
*rxq
, u32 value
)
1032 unsigned long clk_rate
;
1034 clk_rate
= clk_get_rate(pp
->clk
);
1035 val
= (clk_rate
/ 1000000) * value
;
1037 mvreg_write(pp
, MVNETA_RXQ_TIME_COAL_REG(rxq
->id
), val
);
1038 rxq
->time_coal
= value
;
1041 /* Set threshold for TX_DONE pkts coalescing */
1042 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port
*pp
,
1043 struct mvneta_tx_queue
*txq
, u32 value
)
1047 val
= mvreg_read(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
));
1049 val
&= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK
;
1050 val
|= MVNETA_TXQ_SENT_THRESH_MASK(value
);
1052 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), val
);
1054 txq
->done_pkts_coal
= value
;
1057 /* Trigger tx done timer in MVNETA_TX_DONE_TIMER_PERIOD msecs */
1058 static void mvneta_add_tx_done_timer(struct mvneta_port
*pp
)
1060 if (test_and_set_bit(MVNETA_F_TX_DONE_TIMER_BIT
, &pp
->flags
) == 0) {
1061 pp
->tx_done_timer
.expires
= jiffies
+
1062 msecs_to_jiffies(MVNETA_TX_DONE_TIMER_PERIOD
);
1063 add_timer(&pp
->tx_done_timer
);
1068 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1069 static void mvneta_rx_desc_fill(struct mvneta_rx_desc
*rx_desc
,
1070 u32 phys_addr
, u32 cookie
)
1072 rx_desc
->buf_cookie
= cookie
;
1073 rx_desc
->buf_phys_addr
= phys_addr
;
1076 /* Decrement sent descriptors counter */
1077 static void mvneta_txq_sent_desc_dec(struct mvneta_port
*pp
,
1078 struct mvneta_tx_queue
*txq
,
1083 /* Only 255 TX descriptors can be updated at once */
1084 while (sent_desc
> 0xff) {
1085 val
= 0xff << MVNETA_TXQ_DEC_SENT_SHIFT
;
1086 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1087 sent_desc
= sent_desc
- 0xff;
1090 val
= sent_desc
<< MVNETA_TXQ_DEC_SENT_SHIFT
;
1091 mvreg_write(pp
, MVNETA_TXQ_UPDATE_REG(txq
->id
), val
);
1094 /* Get number of TX descriptors already sent by HW */
1095 static int mvneta_txq_sent_desc_num_get(struct mvneta_port
*pp
,
1096 struct mvneta_tx_queue
*txq
)
1101 val
= mvreg_read(pp
, MVNETA_TXQ_STATUS_REG(txq
->id
));
1102 sent_desc
= (val
& MVNETA_TXQ_SENT_DESC_MASK
) >>
1103 MVNETA_TXQ_SENT_DESC_SHIFT
;
1108 /* Get number of sent descriptors and decrement counter.
1109 * The number of sent descriptors is returned.
1111 static int mvneta_txq_sent_desc_proc(struct mvneta_port
*pp
,
1112 struct mvneta_tx_queue
*txq
)
1116 /* Get number of sent descriptors */
1117 sent_desc
= mvneta_txq_sent_desc_num_get(pp
, txq
);
1119 /* Decrement sent descriptors counter */
1121 mvneta_txq_sent_desc_dec(pp
, txq
, sent_desc
);
1126 /* Set TXQ descriptors fields relevant for CSUM calculation */
1127 static u32
mvneta_txq_desc_csum(int l3_offs
, int l3_proto
,
1128 int ip_hdr_len
, int l4_proto
)
1132 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1133 * G_L4_chk, L4_type; required only for checksum
1136 command
= l3_offs
<< MVNETA_TX_L3_OFF_SHIFT
;
1137 command
|= ip_hdr_len
<< MVNETA_TX_IP_HLEN_SHIFT
;
1139 if (l3_proto
== swab16(ETH_P_IP
))
1140 command
|= MVNETA_TXD_IP_CSUM
;
1142 command
|= MVNETA_TX_L3_IP6
;
1144 if (l4_proto
== IPPROTO_TCP
)
1145 command
|= MVNETA_TX_L4_CSUM_FULL
;
1146 else if (l4_proto
== IPPROTO_UDP
)
1147 command
|= MVNETA_TX_L4_UDP
| MVNETA_TX_L4_CSUM_FULL
;
1149 command
|= MVNETA_TX_L4_CSUM_NOT
;
1155 /* Display more error info */
1156 static void mvneta_rx_error(struct mvneta_port
*pp
,
1157 struct mvneta_rx_desc
*rx_desc
)
1159 u32 status
= rx_desc
->status
;
1161 if (!mvneta_rxq_desc_is_first_last(rx_desc
)) {
1163 "bad rx status %08x (buffer oversize), size=%d\n",
1164 rx_desc
->status
, rx_desc
->data_size
);
1168 switch (status
& MVNETA_RXD_ERR_CODE_MASK
) {
1169 case MVNETA_RXD_ERR_CRC
:
1170 netdev_err(pp
->dev
, "bad rx status %08x (crc error), size=%d\n",
1171 status
, rx_desc
->data_size
);
1173 case MVNETA_RXD_ERR_OVERRUN
:
1174 netdev_err(pp
->dev
, "bad rx status %08x (overrun error), size=%d\n",
1175 status
, rx_desc
->data_size
);
1177 case MVNETA_RXD_ERR_LEN
:
1178 netdev_err(pp
->dev
, "bad rx status %08x (max frame length error), size=%d\n",
1179 status
, rx_desc
->data_size
);
1181 case MVNETA_RXD_ERR_RESOURCE
:
1182 netdev_err(pp
->dev
, "bad rx status %08x (resource error), size=%d\n",
1183 status
, rx_desc
->data_size
);
1188 /* Handle RX checksum offload */
1189 static void mvneta_rx_csum(struct mvneta_port
*pp
,
1190 struct mvneta_rx_desc
*rx_desc
,
1191 struct sk_buff
*skb
)
1193 if ((rx_desc
->status
& MVNETA_RXD_L3_IP4
) &&
1194 (rx_desc
->status
& MVNETA_RXD_L4_CSUM_OK
)) {
1196 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1200 skb
->ip_summed
= CHECKSUM_NONE
;
1203 /* Return tx queue pointer (find last set bit) according to causeTxDone reg */
1204 static struct mvneta_tx_queue
*mvneta_tx_done_policy(struct mvneta_port
*pp
,
1207 int queue
= fls(cause
) - 1;
1209 return (queue
< 0 || queue
>= txq_number
) ? NULL
: &pp
->txqs
[queue
];
1212 /* Free tx queue skbuffs */
1213 static void mvneta_txq_bufs_free(struct mvneta_port
*pp
,
1214 struct mvneta_tx_queue
*txq
, int num
)
1218 for (i
= 0; i
< num
; i
++) {
1219 struct mvneta_tx_desc
*tx_desc
= txq
->descs
+
1221 struct sk_buff
*skb
= txq
->tx_skb
[txq
->txq_get_index
];
1223 mvneta_txq_inc_get(txq
);
1228 dma_unmap_single(pp
->dev
->dev
.parent
, tx_desc
->buf_phys_addr
,
1229 tx_desc
->data_size
, DMA_TO_DEVICE
);
1230 dev_kfree_skb_any(skb
);
1234 /* Handle end of transmission */
1235 static int mvneta_txq_done(struct mvneta_port
*pp
,
1236 struct mvneta_tx_queue
*txq
)
1238 struct netdev_queue
*nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1241 tx_done
= mvneta_txq_sent_desc_proc(pp
, txq
);
1244 mvneta_txq_bufs_free(pp
, txq
, tx_done
);
1246 txq
->count
-= tx_done
;
1248 if (netif_tx_queue_stopped(nq
)) {
1249 if (txq
->size
- txq
->count
>= MAX_SKB_FRAGS
+ 1)
1250 netif_tx_wake_queue(nq
);
1256 /* Refill processing */
1257 static int mvneta_rx_refill(struct mvneta_port
*pp
,
1258 struct mvneta_rx_desc
*rx_desc
)
1261 dma_addr_t phys_addr
;
1262 struct sk_buff
*skb
;
1264 skb
= netdev_alloc_skb(pp
->dev
, pp
->pkt_size
);
1268 phys_addr
= dma_map_single(pp
->dev
->dev
.parent
, skb
->head
,
1269 MVNETA_RX_BUF_SIZE(pp
->pkt_size
),
1271 if (unlikely(dma_mapping_error(pp
->dev
->dev
.parent
, phys_addr
))) {
1276 mvneta_rx_desc_fill(rx_desc
, phys_addr
, (u32
)skb
);
1281 /* Handle tx checksum */
1282 static u32
mvneta_skb_tx_csum(struct mvneta_port
*pp
, struct sk_buff
*skb
)
1284 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1288 if (skb
->protocol
== htons(ETH_P_IP
)) {
1289 struct iphdr
*ip4h
= ip_hdr(skb
);
1291 /* Calculate IPv4 checksum and L4 checksum */
1292 ip_hdr_len
= ip4h
->ihl
;
1293 l4_proto
= ip4h
->protocol
;
1294 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
1295 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1297 /* Read l4_protocol from one of IPv6 extra headers */
1298 if (skb_network_header_len(skb
) > 0)
1299 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
1300 l4_proto
= ip6h
->nexthdr
;
1302 return MVNETA_TX_L4_CSUM_NOT
;
1304 return mvneta_txq_desc_csum(skb_network_offset(skb
),
1305 skb
->protocol
, ip_hdr_len
, l4_proto
);
1308 return MVNETA_TX_L4_CSUM_NOT
;
1311 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1314 static struct mvneta_rx_queue
*mvneta_rx_policy(struct mvneta_port
*pp
,
1317 int queue
= fls(cause
>> 8) - 1;
1319 return (queue
< 0 || queue
>= rxq_number
) ? NULL
: &pp
->rxqs
[queue
];
1322 /* Drop packets received by the RXQ and free buffers */
1323 static void mvneta_rxq_drop_pkts(struct mvneta_port
*pp
,
1324 struct mvneta_rx_queue
*rxq
)
1328 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1329 for (i
= 0; i
< rxq
->size
; i
++) {
1330 struct mvneta_rx_desc
*rx_desc
= rxq
->descs
+ i
;
1331 struct sk_buff
*skb
= (struct sk_buff
*)rx_desc
->buf_cookie
;
1333 dev_kfree_skb_any(skb
);
1334 dma_unmap_single(pp
->dev
->dev
.parent
, rx_desc
->buf_phys_addr
,
1335 rx_desc
->data_size
, DMA_FROM_DEVICE
);
1339 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_done
);
1342 /* Main rx processing */
1343 static int mvneta_rx(struct mvneta_port
*pp
, int rx_todo
,
1344 struct mvneta_rx_queue
*rxq
)
1346 struct net_device
*dev
= pp
->dev
;
1347 int rx_done
, rx_filled
;
1349 /* Get number of received packets */
1350 rx_done
= mvneta_rxq_busy_desc_num_get(pp
, rxq
);
1352 if (rx_todo
> rx_done
)
1358 /* Fairness NAPI loop */
1359 while (rx_done
< rx_todo
) {
1360 struct mvneta_rx_desc
*rx_desc
= mvneta_rxq_next_desc_get(rxq
);
1361 struct sk_buff
*skb
;
1368 rx_status
= rx_desc
->status
;
1369 skb
= (struct sk_buff
*)rx_desc
->buf_cookie
;
1371 if (!mvneta_rxq_desc_is_first_last(rx_desc
) ||
1372 (rx_status
& MVNETA_RXD_ERR_SUMMARY
)) {
1373 dev
->stats
.rx_errors
++;
1374 mvneta_rx_error(pp
, rx_desc
);
1375 mvneta_rx_desc_fill(rx_desc
, rx_desc
->buf_phys_addr
,
1380 dma_unmap_single(pp
->dev
->dev
.parent
, rx_desc
->buf_phys_addr
,
1381 rx_desc
->data_size
, DMA_FROM_DEVICE
);
1383 rx_bytes
= rx_desc
->data_size
-
1384 (ETH_FCS_LEN
+ MVNETA_MH_SIZE
);
1385 u64_stats_update_begin(&pp
->rx_stats
.syncp
);
1386 pp
->rx_stats
.packets
++;
1387 pp
->rx_stats
.bytes
+= rx_bytes
;
1388 u64_stats_update_end(&pp
->rx_stats
.syncp
);
1390 /* Linux processing */
1391 skb_reserve(skb
, MVNETA_MH_SIZE
);
1392 skb_put(skb
, rx_bytes
);
1394 skb
->protocol
= eth_type_trans(skb
, dev
);
1396 mvneta_rx_csum(pp
, rx_desc
, skb
);
1398 napi_gro_receive(&pp
->napi
, skb
);
1400 /* Refill processing */
1401 err
= mvneta_rx_refill(pp
, rx_desc
);
1403 netdev_err(pp
->dev
, "Linux processing - Can't refill\n");
1409 /* Update rxq management counters */
1410 mvneta_rxq_desc_num_update(pp
, rxq
, rx_done
, rx_filled
);
1415 /* Handle tx fragmentation processing */
1416 static int mvneta_tx_frag_process(struct mvneta_port
*pp
, struct sk_buff
*skb
,
1417 struct mvneta_tx_queue
*txq
)
1419 struct mvneta_tx_desc
*tx_desc
;
1422 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1423 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1424 void *addr
= page_address(frag
->page
.p
) + frag
->page_offset
;
1426 tx_desc
= mvneta_txq_next_desc_get(txq
);
1427 tx_desc
->data_size
= frag
->size
;
1429 tx_desc
->buf_phys_addr
=
1430 dma_map_single(pp
->dev
->dev
.parent
, addr
,
1431 tx_desc
->data_size
, DMA_TO_DEVICE
);
1433 if (dma_mapping_error(pp
->dev
->dev
.parent
,
1434 tx_desc
->buf_phys_addr
)) {
1435 mvneta_txq_desc_put(txq
);
1439 if (i
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1440 /* Last descriptor */
1441 tx_desc
->command
= MVNETA_TXD_L_DESC
| MVNETA_TXD_Z_PAD
;
1443 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
1445 mvneta_txq_inc_put(txq
);
1447 /* Descriptor in the middle: Not First, Not Last */
1448 tx_desc
->command
= 0;
1450 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
1451 mvneta_txq_inc_put(txq
);
1458 /* Release all descriptors that were used to map fragments of
1459 * this packet, as well as the corresponding DMA mappings
1461 for (i
= i
- 1; i
>= 0; i
--) {
1462 tx_desc
= txq
->descs
+ i
;
1463 dma_unmap_single(pp
->dev
->dev
.parent
,
1464 tx_desc
->buf_phys_addr
,
1467 mvneta_txq_desc_put(txq
);
1473 /* Main tx processing */
1474 static int mvneta_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1476 struct mvneta_port
*pp
= netdev_priv(dev
);
1477 u16 txq_id
= skb_get_queue_mapping(skb
);
1478 struct mvneta_tx_queue
*txq
= &pp
->txqs
[txq_id
];
1479 struct mvneta_tx_desc
*tx_desc
;
1480 struct netdev_queue
*nq
;
1484 if (!netif_running(dev
))
1487 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
1488 nq
= netdev_get_tx_queue(dev
, txq_id
);
1490 /* Get a descriptor for the first part of the packet */
1491 tx_desc
= mvneta_txq_next_desc_get(txq
);
1493 tx_cmd
= mvneta_skb_tx_csum(pp
, skb
);
1495 tx_desc
->data_size
= skb_headlen(skb
);
1497 tx_desc
->buf_phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
1500 if (unlikely(dma_mapping_error(dev
->dev
.parent
,
1501 tx_desc
->buf_phys_addr
))) {
1502 mvneta_txq_desc_put(txq
);
1508 /* First and Last descriptor */
1509 tx_cmd
|= MVNETA_TXD_FLZ_DESC
;
1510 tx_desc
->command
= tx_cmd
;
1511 txq
->tx_skb
[txq
->txq_put_index
] = skb
;
1512 mvneta_txq_inc_put(txq
);
1514 /* First but not Last */
1515 tx_cmd
|= MVNETA_TXD_F_DESC
;
1516 txq
->tx_skb
[txq
->txq_put_index
] = NULL
;
1517 mvneta_txq_inc_put(txq
);
1518 tx_desc
->command
= tx_cmd
;
1519 /* Continue with other skb fragments */
1520 if (mvneta_tx_frag_process(pp
, skb
, txq
)) {
1521 dma_unmap_single(dev
->dev
.parent
,
1522 tx_desc
->buf_phys_addr
,
1525 mvneta_txq_desc_put(txq
);
1531 txq
->count
+= frags
;
1532 mvneta_txq_pend_desc_add(pp
, txq
, frags
);
1534 if (txq
->size
- txq
->count
< MAX_SKB_FRAGS
+ 1)
1535 netif_tx_stop_queue(nq
);
1539 u64_stats_update_begin(&pp
->tx_stats
.syncp
);
1540 pp
->tx_stats
.packets
++;
1541 pp
->tx_stats
.bytes
+= skb
->len
;
1542 u64_stats_update_end(&pp
->tx_stats
.syncp
);
1545 dev
->stats
.tx_dropped
++;
1546 dev_kfree_skb_any(skb
);
1549 if (txq
->count
>= MVNETA_TXDONE_COAL_PKTS
)
1550 mvneta_txq_done(pp
, txq
);
1552 /* If after calling mvneta_txq_done, count equals
1553 * frags, we need to set the timer
1555 if (txq
->count
== frags
&& frags
> 0)
1556 mvneta_add_tx_done_timer(pp
);
1558 return NETDEV_TX_OK
;
1562 /* Free tx resources, when resetting a port */
1563 static void mvneta_txq_done_force(struct mvneta_port
*pp
,
1564 struct mvneta_tx_queue
*txq
)
1567 int tx_done
= txq
->count
;
1569 mvneta_txq_bufs_free(pp
, txq
, tx_done
);
1573 txq
->txq_put_index
= 0;
1574 txq
->txq_get_index
= 0;
1577 /* handle tx done - called from tx done timer callback */
1578 static u32
mvneta_tx_done_gbe(struct mvneta_port
*pp
, u32 cause_tx_done
,
1581 struct mvneta_tx_queue
*txq
;
1583 struct netdev_queue
*nq
;
1586 while (cause_tx_done
!= 0) {
1587 txq
= mvneta_tx_done_policy(pp
, cause_tx_done
);
1591 nq
= netdev_get_tx_queue(pp
->dev
, txq
->id
);
1592 __netif_tx_lock(nq
, smp_processor_id());
1595 tx_done
+= mvneta_txq_done(pp
, txq
);
1596 *tx_todo
+= txq
->count
;
1599 __netif_tx_unlock(nq
);
1600 cause_tx_done
&= ~((1 << txq
->id
));
1606 /* Compute crc8 of the specified address, using a unique algorithm ,
1607 * according to hw spec, different than generic crc8 algorithm
1609 static int mvneta_addr_crc(unsigned char *addr
)
1614 for (i
= 0; i
< ETH_ALEN
; i
++) {
1617 crc
= (crc
^ addr
[i
]) << 8;
1618 for (j
= 7; j
>= 0; j
--) {
1619 if (crc
& (0x100 << j
))
1627 /* This method controls the net device special MAC multicast support.
1628 * The Special Multicast Table for MAC addresses supports MAC of the form
1629 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1630 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1631 * Table entries in the DA-Filter table. This method set the Special
1632 * Multicast Table appropriate entry.
1634 static void mvneta_set_special_mcast_addr(struct mvneta_port
*pp
,
1635 unsigned char last_byte
,
1638 unsigned int smc_table_reg
;
1639 unsigned int tbl_offset
;
1640 unsigned int reg_offset
;
1642 /* Register offset from SMC table base */
1643 tbl_offset
= (last_byte
/ 4);
1644 /* Entry offset within the above reg */
1645 reg_offset
= last_byte
% 4;
1647 smc_table_reg
= mvreg_read(pp
, (MVNETA_DA_FILT_SPEC_MCAST
1651 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
1653 smc_table_reg
&= ~(0xff << (8 * reg_offset
));
1654 smc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1657 mvreg_write(pp
, MVNETA_DA_FILT_SPEC_MCAST
+ tbl_offset
* 4,
1661 /* This method controls the network device Other MAC multicast support.
1662 * The Other Multicast Table is used for multicast of another type.
1663 * A CRC-8 is used as an index to the Other Multicast Table entries
1664 * in the DA-Filter table.
1665 * The method gets the CRC-8 value from the calling routine and
1666 * sets the Other Multicast Table appropriate entry according to the
1669 static void mvneta_set_other_mcast_addr(struct mvneta_port
*pp
,
1673 unsigned int omc_table_reg
;
1674 unsigned int tbl_offset
;
1675 unsigned int reg_offset
;
1677 tbl_offset
= (crc8
/ 4) * 4; /* Register offset from OMC table base */
1678 reg_offset
= crc8
% 4; /* Entry offset within the above reg */
1680 omc_table_reg
= mvreg_read(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
);
1683 /* Clear accepts frame bit at specified Other DA table entry */
1684 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
1686 omc_table_reg
&= ~(0xff << (8 * reg_offset
));
1687 omc_table_reg
|= ((0x01 | (queue
<< 1)) << (8 * reg_offset
));
1690 mvreg_write(pp
, MVNETA_DA_FILT_OTH_MCAST
+ tbl_offset
, omc_table_reg
);
1693 /* The network device supports multicast using two tables:
1694 * 1) Special Multicast Table for MAC addresses of the form
1695 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1696 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1697 * Table entries in the DA-Filter table.
1698 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1699 * is used as an index to the Other Multicast Table entries in the
1702 static int mvneta_mcast_addr_set(struct mvneta_port
*pp
, unsigned char *p_addr
,
1705 unsigned char crc_result
= 0;
1707 if (memcmp(p_addr
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1708 mvneta_set_special_mcast_addr(pp
, p_addr
[5], queue
);
1712 crc_result
= mvneta_addr_crc(p_addr
);
1714 if (pp
->mcast_count
[crc_result
] == 0) {
1715 netdev_info(pp
->dev
, "No valid Mcast for crc8=0x%02x\n",
1720 pp
->mcast_count
[crc_result
]--;
1721 if (pp
->mcast_count
[crc_result
] != 0) {
1722 netdev_info(pp
->dev
,
1723 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1724 pp
->mcast_count
[crc_result
], crc_result
);
1728 pp
->mcast_count
[crc_result
]++;
1730 mvneta_set_other_mcast_addr(pp
, crc_result
, queue
);
1735 /* Configure Fitering mode of Ethernet port */
1736 static void mvneta_rx_unicast_promisc_set(struct mvneta_port
*pp
,
1739 u32 port_cfg_reg
, val
;
1741 port_cfg_reg
= mvreg_read(pp
, MVNETA_PORT_CONFIG
);
1743 val
= mvreg_read(pp
, MVNETA_TYPE_PRIO
);
1745 /* Set / Clear UPM bit in port configuration register */
1747 /* Accept all Unicast addresses */
1748 port_cfg_reg
|= MVNETA_UNI_PROMISC_MODE
;
1749 val
|= MVNETA_FORCE_UNI
;
1750 mvreg_write(pp
, MVNETA_MAC_ADDR_LOW
, 0xffff);
1751 mvreg_write(pp
, MVNETA_MAC_ADDR_HIGH
, 0xffffffff);
1753 /* Reject all Unicast addresses */
1754 port_cfg_reg
&= ~MVNETA_UNI_PROMISC_MODE
;
1755 val
&= ~MVNETA_FORCE_UNI
;
1758 mvreg_write(pp
, MVNETA_PORT_CONFIG
, port_cfg_reg
);
1759 mvreg_write(pp
, MVNETA_TYPE_PRIO
, val
);
1762 /* register unicast and multicast addresses */
1763 static void mvneta_set_rx_mode(struct net_device
*dev
)
1765 struct mvneta_port
*pp
= netdev_priv(dev
);
1766 struct netdev_hw_addr
*ha
;
1768 if (dev
->flags
& IFF_PROMISC
) {
1769 /* Accept all: Multicast + Unicast */
1770 mvneta_rx_unicast_promisc_set(pp
, 1);
1771 mvneta_set_ucast_table(pp
, rxq_def
);
1772 mvneta_set_special_mcast_table(pp
, rxq_def
);
1773 mvneta_set_other_mcast_table(pp
, rxq_def
);
1775 /* Accept single Unicast */
1776 mvneta_rx_unicast_promisc_set(pp
, 0);
1777 mvneta_set_ucast_table(pp
, -1);
1778 mvneta_mac_addr_set(pp
, dev
->dev_addr
, rxq_def
);
1780 if (dev
->flags
& IFF_ALLMULTI
) {
1781 /* Accept all multicast */
1782 mvneta_set_special_mcast_table(pp
, rxq_def
);
1783 mvneta_set_other_mcast_table(pp
, rxq_def
);
1785 /* Accept only initialized multicast */
1786 mvneta_set_special_mcast_table(pp
, -1);
1787 mvneta_set_other_mcast_table(pp
, -1);
1789 if (!netdev_mc_empty(dev
)) {
1790 netdev_for_each_mc_addr(ha
, dev
) {
1791 mvneta_mcast_addr_set(pp
, ha
->addr
,
1799 /* Interrupt handling - the callback for request_irq() */
1800 static irqreturn_t
mvneta_isr(int irq
, void *dev_id
)
1802 struct mvneta_port
*pp
= (struct mvneta_port
*)dev_id
;
1804 /* Mask all interrupts */
1805 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
1807 napi_schedule(&pp
->napi
);
1813 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1814 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1815 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1816 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1817 * Each CPU has its own causeRxTx register
1819 static int mvneta_poll(struct napi_struct
*napi
, int budget
)
1823 unsigned long flags
;
1824 struct mvneta_port
*pp
= netdev_priv(napi
->dev
);
1826 if (!netif_running(pp
->dev
)) {
1827 napi_complete(napi
);
1831 /* Read cause register */
1832 cause_rx_tx
= mvreg_read(pp
, MVNETA_INTR_NEW_CAUSE
) &
1833 MVNETA_RX_INTR_MASK(rxq_number
);
1835 /* For the case where the last mvneta_poll did not process all
1838 cause_rx_tx
|= pp
->cause_rx_tx
;
1839 if (rxq_number
> 1) {
1840 while ((cause_rx_tx
!= 0) && (budget
> 0)) {
1842 struct mvneta_rx_queue
*rxq
;
1843 /* get rx queue number from cause_rx_tx */
1844 rxq
= mvneta_rx_policy(pp
, cause_rx_tx
);
1848 /* process the packet in that rx queue */
1849 count
= mvneta_rx(pp
, budget
, rxq
);
1853 /* set off the rx bit of the
1854 * corresponding bit in the cause rx
1855 * tx register, so that next iteration
1856 * will find the next rx queue where
1857 * packets are received on
1859 cause_rx_tx
&= ~((1 << rxq
->id
) << 8);
1863 rx_done
= mvneta_rx(pp
, budget
, &pp
->rxqs
[rxq_def
]);
1869 napi_complete(napi
);
1870 local_irq_save(flags
);
1871 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
1872 MVNETA_RX_INTR_MASK(rxq_number
));
1873 local_irq_restore(flags
);
1876 pp
->cause_rx_tx
= cause_rx_tx
;
1880 /* tx done timer callback */
1881 static void mvneta_tx_done_timer_callback(unsigned long data
)
1883 struct net_device
*dev
= (struct net_device
*)data
;
1884 struct mvneta_port
*pp
= netdev_priv(dev
);
1885 int tx_done
= 0, tx_todo
= 0;
1887 if (!netif_running(dev
))
1890 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT
, &pp
->flags
);
1892 tx_done
= mvneta_tx_done_gbe(pp
,
1893 (((1 << txq_number
) - 1) &
1894 MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK
),
1897 mvneta_add_tx_done_timer(pp
);
1900 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1901 static int mvneta_rxq_fill(struct mvneta_port
*pp
, struct mvneta_rx_queue
*rxq
,
1904 struct net_device
*dev
= pp
->dev
;
1907 for (i
= 0; i
< num
; i
++) {
1908 struct sk_buff
*skb
;
1909 struct mvneta_rx_desc
*rx_desc
;
1910 unsigned long phys_addr
;
1912 skb
= dev_alloc_skb(pp
->pkt_size
);
1914 netdev_err(dev
, "%s:rxq %d, %d of %d buffs filled\n",
1915 __func__
, rxq
->id
, i
, num
);
1919 rx_desc
= rxq
->descs
+ i
;
1920 memset(rx_desc
, 0, sizeof(struct mvneta_rx_desc
));
1921 phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->head
,
1922 MVNETA_RX_BUF_SIZE(pp
->pkt_size
),
1924 if (unlikely(dma_mapping_error(dev
->dev
.parent
, phys_addr
))) {
1929 mvneta_rx_desc_fill(rx_desc
, phys_addr
, (u32
)skb
);
1932 /* Add this number of RX descriptors as non occupied (ready to
1935 mvneta_rxq_non_occup_desc_add(pp
, rxq
, i
);
1940 /* Free all packets pending transmit from all TXQs and reset TX port */
1941 static void mvneta_tx_reset(struct mvneta_port
*pp
)
1945 /* free the skb's in the hal tx ring */
1946 for (queue
= 0; queue
< txq_number
; queue
++)
1947 mvneta_txq_done_force(pp
, &pp
->txqs
[queue
]);
1949 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, MVNETA_PORT_TX_DMA_RESET
);
1950 mvreg_write(pp
, MVNETA_PORT_TX_RESET
, 0);
1953 static void mvneta_rx_reset(struct mvneta_port
*pp
)
1955 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, MVNETA_PORT_RX_DMA_RESET
);
1956 mvreg_write(pp
, MVNETA_PORT_RX_RESET
, 0);
1959 /* Rx/Tx queue initialization/cleanup methods */
1961 /* Create a specified RX queue */
1962 static int mvneta_rxq_init(struct mvneta_port
*pp
,
1963 struct mvneta_rx_queue
*rxq
)
1966 rxq
->size
= pp
->rx_ring_size
;
1968 /* Allocate memory for RX descriptors */
1969 rxq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
1970 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
1971 &rxq
->descs_phys
, GFP_KERNEL
);
1972 if (rxq
->descs
== NULL
) {
1974 "rxq=%d: Can't allocate %d bytes for %d RX descr\n",
1975 rxq
->id
, rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
1980 BUG_ON(rxq
->descs
!=
1981 PTR_ALIGN(rxq
->descs
, MVNETA_CPU_D_CACHE_LINE_SIZE
));
1983 rxq
->last_desc
= rxq
->size
- 1;
1985 /* Set Rx descriptors queue starting address */
1986 mvreg_write(pp
, MVNETA_RXQ_BASE_ADDR_REG(rxq
->id
), rxq
->descs_phys
);
1987 mvreg_write(pp
, MVNETA_RXQ_SIZE_REG(rxq
->id
), rxq
->size
);
1990 mvneta_rxq_offset_set(pp
, rxq
, NET_SKB_PAD
);
1992 /* Set coalescing pkts and time */
1993 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
1994 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
1996 /* Fill RXQ with buffers from RX pool */
1997 mvneta_rxq_buf_size_set(pp
, rxq
, MVNETA_RX_BUF_SIZE(pp
->pkt_size
));
1998 mvneta_rxq_bm_disable(pp
, rxq
);
1999 mvneta_rxq_fill(pp
, rxq
, rxq
->size
);
2004 /* Cleanup Rx queue */
2005 static void mvneta_rxq_deinit(struct mvneta_port
*pp
,
2006 struct mvneta_rx_queue
*rxq
)
2008 mvneta_rxq_drop_pkts(pp
, rxq
);
2011 dma_free_coherent(pp
->dev
->dev
.parent
,
2012 rxq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2018 rxq
->next_desc_to_proc
= 0;
2019 rxq
->descs_phys
= 0;
2022 /* Create and initialize a tx queue */
2023 static int mvneta_txq_init(struct mvneta_port
*pp
,
2024 struct mvneta_tx_queue
*txq
)
2026 txq
->size
= pp
->tx_ring_size
;
2028 /* Allocate memory for TX descriptors */
2029 txq
->descs
= dma_alloc_coherent(pp
->dev
->dev
.parent
,
2030 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2031 &txq
->descs_phys
, GFP_KERNEL
);
2032 if (txq
->descs
== NULL
) {
2034 "txQ=%d: Can't allocate %d bytes for %d TX descr\n",
2035 txq
->id
, txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2040 /* Make sure descriptor address is cache line size aligned */
2041 BUG_ON(txq
->descs
!=
2042 PTR_ALIGN(txq
->descs
, MVNETA_CPU_D_CACHE_LINE_SIZE
));
2044 txq
->last_desc
= txq
->size
- 1;
2046 /* Set maximum bandwidth for enabled TXQs */
2047 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0x03ffffff);
2048 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0x3fffffff);
2050 /* Set Tx descriptors queue starting address */
2051 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), txq
->descs_phys
);
2052 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), txq
->size
);
2054 txq
->tx_skb
= kmalloc(txq
->size
* sizeof(*txq
->tx_skb
), GFP_KERNEL
);
2055 if (txq
->tx_skb
== NULL
) {
2056 dma_free_coherent(pp
->dev
->dev
.parent
,
2057 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2058 txq
->descs
, txq
->descs_phys
);
2061 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
2066 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2067 static void mvneta_txq_deinit(struct mvneta_port
*pp
,
2068 struct mvneta_tx_queue
*txq
)
2073 dma_free_coherent(pp
->dev
->dev
.parent
,
2074 txq
->size
* MVNETA_DESC_ALIGNED_SIZE
,
2075 txq
->descs
, txq
->descs_phys
);
2079 txq
->next_desc_to_proc
= 0;
2080 txq
->descs_phys
= 0;
2082 /* Set minimum bandwidth for disabled TXQs */
2083 mvreg_write(pp
, MVETH_TXQ_TOKEN_CFG_REG(txq
->id
), 0);
2084 mvreg_write(pp
, MVETH_TXQ_TOKEN_COUNT_REG(txq
->id
), 0);
2086 /* Set Tx descriptors queue starting address and size */
2087 mvreg_write(pp
, MVNETA_TXQ_BASE_ADDR_REG(txq
->id
), 0);
2088 mvreg_write(pp
, MVNETA_TXQ_SIZE_REG(txq
->id
), 0);
2091 /* Cleanup all Tx queues */
2092 static void mvneta_cleanup_txqs(struct mvneta_port
*pp
)
2096 for (queue
= 0; queue
< txq_number
; queue
++)
2097 mvneta_txq_deinit(pp
, &pp
->txqs
[queue
]);
2100 /* Cleanup all Rx queues */
2101 static void mvneta_cleanup_rxqs(struct mvneta_port
*pp
)
2105 for (queue
= 0; queue
< rxq_number
; queue
++)
2106 mvneta_rxq_deinit(pp
, &pp
->rxqs
[queue
]);
2110 /* Init all Rx queues */
2111 static int mvneta_setup_rxqs(struct mvneta_port
*pp
)
2115 for (queue
= 0; queue
< rxq_number
; queue
++) {
2116 int err
= mvneta_rxq_init(pp
, &pp
->rxqs
[queue
]);
2118 netdev_err(pp
->dev
, "%s: can't create rxq=%d\n",
2120 mvneta_cleanup_rxqs(pp
);
2128 /* Init all tx queues */
2129 static int mvneta_setup_txqs(struct mvneta_port
*pp
)
2133 for (queue
= 0; queue
< txq_number
; queue
++) {
2134 int err
= mvneta_txq_init(pp
, &pp
->txqs
[queue
]);
2136 netdev_err(pp
->dev
, "%s: can't create txq=%d\n",
2138 mvneta_cleanup_txqs(pp
);
2146 static void mvneta_start_dev(struct mvneta_port
*pp
)
2148 mvneta_max_rx_size_set(pp
, pp
->pkt_size
);
2149 mvneta_txq_max_tx_size_set(pp
, pp
->pkt_size
);
2151 /* start the Rx/Tx activity */
2152 mvneta_port_enable(pp
);
2154 /* Enable polling on the port */
2155 napi_enable(&pp
->napi
);
2157 /* Unmask interrupts */
2158 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
,
2159 MVNETA_RX_INTR_MASK(rxq_number
));
2161 phy_start(pp
->phy_dev
);
2162 netif_tx_start_all_queues(pp
->dev
);
2165 static void mvneta_stop_dev(struct mvneta_port
*pp
)
2167 phy_stop(pp
->phy_dev
);
2169 napi_disable(&pp
->napi
);
2171 netif_carrier_off(pp
->dev
);
2173 mvneta_port_down(pp
);
2174 netif_tx_stop_all_queues(pp
->dev
);
2176 /* Stop the port activity */
2177 mvneta_port_disable(pp
);
2179 /* Clear all ethernet port interrupts */
2180 mvreg_write(pp
, MVNETA_INTR_MISC_CAUSE
, 0);
2181 mvreg_write(pp
, MVNETA_INTR_OLD_CAUSE
, 0);
2183 /* Mask all ethernet port interrupts */
2184 mvreg_write(pp
, MVNETA_INTR_NEW_MASK
, 0);
2185 mvreg_write(pp
, MVNETA_INTR_OLD_MASK
, 0);
2186 mvreg_write(pp
, MVNETA_INTR_MISC_MASK
, 0);
2188 mvneta_tx_reset(pp
);
2189 mvneta_rx_reset(pp
);
2192 /* tx timeout callback - display a message and stop/start the network device */
2193 static void mvneta_tx_timeout(struct net_device
*dev
)
2195 struct mvneta_port
*pp
= netdev_priv(dev
);
2197 netdev_info(dev
, "tx timeout\n");
2198 mvneta_stop_dev(pp
);
2199 mvneta_start_dev(pp
);
2202 /* Return positive if MTU is valid */
2203 static int mvneta_check_mtu_valid(struct net_device
*dev
, int mtu
)
2206 netdev_err(dev
, "cannot change mtu to less than 68\n");
2210 /* 9676 == 9700 - 20 and rounding to 8 */
2212 netdev_info(dev
, "Illegal MTU value %d, round to 9676\n", mtu
);
2216 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu
), 8)) {
2217 netdev_info(dev
, "Illegal MTU value %d, rounding to %d\n",
2218 mtu
, ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8));
2219 mtu
= ALIGN(MVNETA_RX_PKT_SIZE(mtu
), 8);
2225 /* Change the device mtu */
2226 static int mvneta_change_mtu(struct net_device
*dev
, int mtu
)
2228 struct mvneta_port
*pp
= netdev_priv(dev
);
2231 mtu
= mvneta_check_mtu_valid(dev
, mtu
);
2237 if (!netif_running(dev
))
2240 /* The interface is running, so we have to force a
2241 * reallocation of the RXQs
2243 mvneta_stop_dev(pp
);
2245 mvneta_cleanup_txqs(pp
);
2246 mvneta_cleanup_rxqs(pp
);
2248 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
);
2250 ret
= mvneta_setup_rxqs(pp
);
2252 netdev_err(pp
->dev
, "unable to setup rxqs after MTU change\n");
2256 mvneta_setup_txqs(pp
);
2258 mvneta_start_dev(pp
);
2264 /* Handle setting mac address */
2265 static int mvneta_set_mac_addr(struct net_device
*dev
, void *addr
)
2267 struct mvneta_port
*pp
= netdev_priv(dev
);
2271 if (netif_running(dev
))
2274 /* Remove previous address table entry */
2275 mvneta_mac_addr_set(pp
, dev
->dev_addr
, -1);
2277 /* Set new addr in hw */
2278 mvneta_mac_addr_set(pp
, mac
, rxq_def
);
2280 /* Set addr in the device */
2281 for (i
= 0; i
< ETH_ALEN
; i
++)
2282 dev
->dev_addr
[i
] = mac
[i
];
2287 static void mvneta_adjust_link(struct net_device
*ndev
)
2289 struct mvneta_port
*pp
= netdev_priv(ndev
);
2290 struct phy_device
*phydev
= pp
->phy_dev
;
2291 int status_change
= 0;
2294 if ((pp
->speed
!= phydev
->speed
) ||
2295 (pp
->duplex
!= phydev
->duplex
)) {
2298 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
2299 val
&= ~(MVNETA_GMAC_CONFIG_MII_SPEED
|
2300 MVNETA_GMAC_CONFIG_GMII_SPEED
|
2301 MVNETA_GMAC_CONFIG_FULL_DUPLEX
);
2304 val
|= MVNETA_GMAC_CONFIG_FULL_DUPLEX
;
2306 if (phydev
->speed
== SPEED_1000
)
2307 val
|= MVNETA_GMAC_CONFIG_GMII_SPEED
;
2309 val
|= MVNETA_GMAC_CONFIG_MII_SPEED
;
2311 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
2313 pp
->duplex
= phydev
->duplex
;
2314 pp
->speed
= phydev
->speed
;
2318 if (phydev
->link
!= pp
->link
) {
2319 if (!phydev
->link
) {
2324 pp
->link
= phydev
->link
;
2328 if (status_change
) {
2330 u32 val
= mvreg_read(pp
, MVNETA_GMAC_AUTONEG_CONFIG
);
2331 val
|= (MVNETA_GMAC_FORCE_LINK_PASS
|
2332 MVNETA_GMAC_FORCE_LINK_DOWN
);
2333 mvreg_write(pp
, MVNETA_GMAC_AUTONEG_CONFIG
, val
);
2335 netdev_info(pp
->dev
, "link up\n");
2337 mvneta_port_down(pp
);
2338 netdev_info(pp
->dev
, "link down\n");
2343 static int mvneta_mdio_probe(struct mvneta_port
*pp
)
2345 struct phy_device
*phy_dev
;
2347 phy_dev
= of_phy_connect(pp
->dev
, pp
->phy_node
, mvneta_adjust_link
, 0,
2350 netdev_err(pp
->dev
, "could not find the PHY\n");
2354 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
2355 phy_dev
->advertising
= phy_dev
->supported
;
2357 pp
->phy_dev
= phy_dev
;
2365 static void mvneta_mdio_remove(struct mvneta_port
*pp
)
2367 phy_disconnect(pp
->phy_dev
);
2371 static int mvneta_open(struct net_device
*dev
)
2373 struct mvneta_port
*pp
= netdev_priv(dev
);
2376 mvneta_mac_addr_set(pp
, dev
->dev_addr
, rxq_def
);
2378 pp
->pkt_size
= MVNETA_RX_PKT_SIZE(pp
->dev
->mtu
);
2380 ret
= mvneta_setup_rxqs(pp
);
2384 ret
= mvneta_setup_txqs(pp
);
2386 goto err_cleanup_rxqs
;
2388 /* Connect to port interrupt line */
2389 ret
= request_irq(pp
->dev
->irq
, mvneta_isr
, 0,
2390 MVNETA_DRIVER_NAME
, pp
);
2392 netdev_err(pp
->dev
, "cannot request irq %d\n", pp
->dev
->irq
);
2393 goto err_cleanup_txqs
;
2396 /* In default link is down */
2397 netif_carrier_off(pp
->dev
);
2399 ret
= mvneta_mdio_probe(pp
);
2401 netdev_err(dev
, "cannot probe MDIO bus\n");
2405 mvneta_start_dev(pp
);
2410 free_irq(pp
->dev
->irq
, pp
);
2412 mvneta_cleanup_txqs(pp
);
2414 mvneta_cleanup_rxqs(pp
);
2418 /* Stop the port, free port interrupt line */
2419 static int mvneta_stop(struct net_device
*dev
)
2421 struct mvneta_port
*pp
= netdev_priv(dev
);
2423 mvneta_stop_dev(pp
);
2424 mvneta_mdio_remove(pp
);
2425 free_irq(dev
->irq
, pp
);
2426 mvneta_cleanup_rxqs(pp
);
2427 mvneta_cleanup_txqs(pp
);
2428 del_timer(&pp
->tx_done_timer
);
2429 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT
, &pp
->flags
);
2434 /* Ethtool methods */
2436 /* Get settings (phy address, speed) for ethtools */
2437 int mvneta_ethtool_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2439 struct mvneta_port
*pp
= netdev_priv(dev
);
2444 return phy_ethtool_gset(pp
->phy_dev
, cmd
);
2447 /* Set settings (phy address, speed) for ethtools */
2448 int mvneta_ethtool_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2450 struct mvneta_port
*pp
= netdev_priv(dev
);
2455 return phy_ethtool_sset(pp
->phy_dev
, cmd
);
2458 /* Set interrupt coalescing for ethtools */
2459 static int mvneta_ethtool_set_coalesce(struct net_device
*dev
,
2460 struct ethtool_coalesce
*c
)
2462 struct mvneta_port
*pp
= netdev_priv(dev
);
2465 for (queue
= 0; queue
< rxq_number
; queue
++) {
2466 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
2467 rxq
->time_coal
= c
->rx_coalesce_usecs
;
2468 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
2469 mvneta_rx_pkts_coal_set(pp
, rxq
, rxq
->pkts_coal
);
2470 mvneta_rx_time_coal_set(pp
, rxq
, rxq
->time_coal
);
2473 for (queue
= 0; queue
< txq_number
; queue
++) {
2474 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
2475 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
2476 mvneta_tx_done_pkts_coal_set(pp
, txq
, txq
->done_pkts_coal
);
2482 /* get coalescing for ethtools */
2483 static int mvneta_ethtool_get_coalesce(struct net_device
*dev
,
2484 struct ethtool_coalesce
*c
)
2486 struct mvneta_port
*pp
= netdev_priv(dev
);
2488 c
->rx_coalesce_usecs
= pp
->rxqs
[0].time_coal
;
2489 c
->rx_max_coalesced_frames
= pp
->rxqs
[0].pkts_coal
;
2491 c
->tx_max_coalesced_frames
= pp
->txqs
[0].done_pkts_coal
;
2496 static void mvneta_ethtool_get_drvinfo(struct net_device
*dev
,
2497 struct ethtool_drvinfo
*drvinfo
)
2499 strlcpy(drvinfo
->driver
, MVNETA_DRIVER_NAME
,
2500 sizeof(drvinfo
->driver
));
2501 strlcpy(drvinfo
->version
, MVNETA_DRIVER_VERSION
,
2502 sizeof(drvinfo
->version
));
2503 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
2504 sizeof(drvinfo
->bus_info
));
2508 static void mvneta_ethtool_get_ringparam(struct net_device
*netdev
,
2509 struct ethtool_ringparam
*ring
)
2511 struct mvneta_port
*pp
= netdev_priv(netdev
);
2513 ring
->rx_max_pending
= MVNETA_MAX_RXD
;
2514 ring
->tx_max_pending
= MVNETA_MAX_TXD
;
2515 ring
->rx_pending
= pp
->rx_ring_size
;
2516 ring
->tx_pending
= pp
->tx_ring_size
;
2519 static int mvneta_ethtool_set_ringparam(struct net_device
*dev
,
2520 struct ethtool_ringparam
*ring
)
2522 struct mvneta_port
*pp
= netdev_priv(dev
);
2524 if ((ring
->rx_pending
== 0) || (ring
->tx_pending
== 0))
2526 pp
->rx_ring_size
= ring
->rx_pending
< MVNETA_MAX_RXD
?
2527 ring
->rx_pending
: MVNETA_MAX_RXD
;
2528 pp
->tx_ring_size
= ring
->tx_pending
< MVNETA_MAX_TXD
?
2529 ring
->tx_pending
: MVNETA_MAX_TXD
;
2531 if (netif_running(dev
)) {
2533 if (mvneta_open(dev
)) {
2535 "error on opening device after ring param change\n");
2543 static const struct net_device_ops mvneta_netdev_ops
= {
2544 .ndo_open
= mvneta_open
,
2545 .ndo_stop
= mvneta_stop
,
2546 .ndo_start_xmit
= mvneta_tx
,
2547 .ndo_set_rx_mode
= mvneta_set_rx_mode
,
2548 .ndo_set_mac_address
= mvneta_set_mac_addr
,
2549 .ndo_change_mtu
= mvneta_change_mtu
,
2550 .ndo_tx_timeout
= mvneta_tx_timeout
,
2551 .ndo_get_stats64
= mvneta_get_stats64
,
2554 const struct ethtool_ops mvneta_eth_tool_ops
= {
2555 .get_link
= ethtool_op_get_link
,
2556 .get_settings
= mvneta_ethtool_get_settings
,
2557 .set_settings
= mvneta_ethtool_set_settings
,
2558 .set_coalesce
= mvneta_ethtool_set_coalesce
,
2559 .get_coalesce
= mvneta_ethtool_get_coalesce
,
2560 .get_drvinfo
= mvneta_ethtool_get_drvinfo
,
2561 .get_ringparam
= mvneta_ethtool_get_ringparam
,
2562 .set_ringparam
= mvneta_ethtool_set_ringparam
,
2566 static int mvneta_init(struct mvneta_port
*pp
, int phy_addr
)
2571 mvneta_port_disable(pp
);
2573 /* Set port default values */
2574 mvneta_defaults_set(pp
);
2576 pp
->txqs
= kzalloc(txq_number
* sizeof(struct mvneta_tx_queue
),
2581 /* Initialize TX descriptor rings */
2582 for (queue
= 0; queue
< txq_number
; queue
++) {
2583 struct mvneta_tx_queue
*txq
= &pp
->txqs
[queue
];
2585 txq
->size
= pp
->tx_ring_size
;
2586 txq
->done_pkts_coal
= MVNETA_TXDONE_COAL_PKTS
;
2589 pp
->rxqs
= kzalloc(rxq_number
* sizeof(struct mvneta_rx_queue
),
2596 /* Create Rx descriptor rings */
2597 for (queue
= 0; queue
< rxq_number
; queue
++) {
2598 struct mvneta_rx_queue
*rxq
= &pp
->rxqs
[queue
];
2600 rxq
->size
= pp
->rx_ring_size
;
2601 rxq
->pkts_coal
= MVNETA_RX_COAL_PKTS
;
2602 rxq
->time_coal
= MVNETA_RX_COAL_USEC
;
2608 static void mvneta_deinit(struct mvneta_port
*pp
)
2614 /* platform glue : initialize decoding windows */
2615 static void mvneta_conf_mbus_windows(struct mvneta_port
*pp
,
2616 const struct mbus_dram_target_info
*dram
)
2622 for (i
= 0; i
< 6; i
++) {
2623 mvreg_write(pp
, MVNETA_WIN_BASE(i
), 0);
2624 mvreg_write(pp
, MVNETA_WIN_SIZE(i
), 0);
2627 mvreg_write(pp
, MVNETA_WIN_REMAP(i
), 0);
2633 for (i
= 0; i
< dram
->num_cs
; i
++) {
2634 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2635 mvreg_write(pp
, MVNETA_WIN_BASE(i
), (cs
->base
& 0xffff0000) |
2636 (cs
->mbus_attr
<< 8) | dram
->mbus_dram_target_id
);
2638 mvreg_write(pp
, MVNETA_WIN_SIZE(i
),
2639 (cs
->size
- 1) & 0xffff0000);
2641 win_enable
&= ~(1 << i
);
2642 win_protect
|= 3 << (2 * i
);
2645 mvreg_write(pp
, MVNETA_BASE_ADDR_ENABLE
, win_enable
);
2648 /* Power up the port */
2649 static void mvneta_port_power_up(struct mvneta_port
*pp
, int phy_mode
)
2653 /* MAC Cause register should be cleared */
2654 mvreg_write(pp
, MVNETA_UNIT_INTR_CAUSE
, 0);
2656 if (phy_mode
== PHY_INTERFACE_MODE_SGMII
)
2657 mvneta_port_sgmii_config(pp
);
2659 mvneta_gmac_rgmii_set(pp
, 1);
2661 /* Cancel Port Reset */
2662 val
= mvreg_read(pp
, MVNETA_GMAC_CTRL_2
);
2663 val
&= ~MVNETA_GMAC2_PORT_RESET
;
2664 mvreg_write(pp
, MVNETA_GMAC_CTRL_2
, val
);
2666 while ((mvreg_read(pp
, MVNETA_GMAC_CTRL_2
) &
2667 MVNETA_GMAC2_PORT_RESET
) != 0)
2671 /* Device initialization routine */
2672 static int mvneta_probe(struct platform_device
*pdev
)
2674 const struct mbus_dram_target_info
*dram_target_info
;
2675 struct device_node
*dn
= pdev
->dev
.of_node
;
2676 struct device_node
*phy_node
;
2678 struct mvneta_port
*pp
;
2679 struct net_device
*dev
;
2680 const char *mac_addr
;
2684 /* Our multiqueue support is not complete, so for now, only
2685 * allow the usage of the first RX queue
2688 dev_err(&pdev
->dev
, "Invalid rxq_def argument: %d\n", rxq_def
);
2692 dev
= alloc_etherdev_mqs(sizeof(struct mvneta_port
), txq_number
, rxq_number
);
2696 dev
->irq
= irq_of_parse_and_map(dn
, 0);
2697 if (dev
->irq
== 0) {
2699 goto err_free_netdev
;
2702 phy_node
= of_parse_phandle(dn
, "phy", 0);
2704 dev_err(&pdev
->dev
, "no associated PHY\n");
2709 phy_mode
= of_get_phy_mode(dn
);
2711 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
2716 mac_addr
= of_get_mac_address(dn
);
2718 if (!mac_addr
|| !is_valid_ether_addr(mac_addr
))
2719 eth_hw_addr_random(dev
);
2721 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
2723 dev
->tx_queue_len
= MVNETA_MAX_TXD
;
2724 dev
->watchdog_timeo
= 5 * HZ
;
2725 dev
->netdev_ops
= &mvneta_netdev_ops
;
2727 SET_ETHTOOL_OPS(dev
, &mvneta_eth_tool_ops
);
2729 pp
= netdev_priv(dev
);
2731 pp
->tx_done_timer
.function
= mvneta_tx_done_timer_callback
;
2732 init_timer(&pp
->tx_done_timer
);
2733 clear_bit(MVNETA_F_TX_DONE_TIMER_BIT
, &pp
->flags
);
2735 pp
->weight
= MVNETA_RX_POLL_WEIGHT
;
2736 pp
->phy_node
= phy_node
;
2737 pp
->phy_interface
= phy_mode
;
2739 pp
->base
= of_iomap(dn
, 0);
2740 if (pp
->base
== NULL
) {
2745 pp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
2746 if (IS_ERR(pp
->clk
)) {
2747 err
= PTR_ERR(pp
->clk
);
2751 clk_prepare_enable(pp
->clk
);
2753 pp
->tx_done_timer
.data
= (unsigned long)dev
;
2755 pp
->tx_ring_size
= MVNETA_MAX_TXD
;
2756 pp
->rx_ring_size
= MVNETA_MAX_RXD
;
2759 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2761 err
= mvneta_init(pp
, phy_addr
);
2763 dev_err(&pdev
->dev
, "can't init eth hal\n");
2766 mvneta_port_power_up(pp
, phy_mode
);
2768 dram_target_info
= mv_mbus_dram_info();
2769 if (dram_target_info
)
2770 mvneta_conf_mbus_windows(pp
, dram_target_info
);
2772 netif_napi_add(dev
, &pp
->napi
, mvneta_poll
, pp
->weight
);
2774 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2775 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2776 dev
->vlan_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2777 dev
->priv_flags
|= IFF_UNICAST_FLT
;
2779 err
= register_netdev(dev
);
2781 dev_err(&pdev
->dev
, "failed to register\n");
2785 netdev_info(dev
, "mac: %pM\n", dev
->dev_addr
);
2787 platform_set_drvdata(pdev
, pp
->dev
);
2794 clk_disable_unprepare(pp
->clk
);
2798 irq_dispose_mapping(dev
->irq
);
2804 /* Device removal routine */
2805 static int mvneta_remove(struct platform_device
*pdev
)
2807 struct net_device
*dev
= platform_get_drvdata(pdev
);
2808 struct mvneta_port
*pp
= netdev_priv(dev
);
2810 unregister_netdev(dev
);
2812 clk_disable_unprepare(pp
->clk
);
2814 irq_dispose_mapping(dev
->irq
);
2817 platform_set_drvdata(pdev
, NULL
);
2822 static const struct of_device_id mvneta_match
[] = {
2823 { .compatible
= "marvell,armada-370-neta" },
2826 MODULE_DEVICE_TABLE(of
, mvneta_match
);
2828 static struct platform_driver mvneta_driver
= {
2829 .probe
= mvneta_probe
,
2830 .remove
= mvneta_remove
,
2832 .name
= MVNETA_DRIVER_NAME
,
2833 .of_match_table
= mvneta_match
,
2837 module_platform_driver(mvneta_driver
);
2839 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2840 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2841 MODULE_LICENSE("GPL");
2843 module_param(rxq_number
, int, S_IRUGO
);
2844 module_param(txq_number
, int, S_IRUGO
);
2846 module_param(rxq_def
, int, S_IRUGO
);