2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/skbuff.h>
18 #include <linux/inetdevice.h>
19 #include <linux/mbus.h>
20 #include <linux/module.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/interrupt.h>
23 #include <linux/cpumask.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/phy.h>
31 #include <linux/phy/phy.h>
32 #include <linux/clk.h>
33 #include <linux/hrtimer.h>
34 #include <linux/ktime.h>
35 #include <linux/regmap.h>
36 #include <uapi/linux/ppp_defs.h>
42 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
43 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
44 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
45 #define MVPP2_RX_FIFO_INIT_REG 0x64
46 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
48 /* RX DMA Top Registers */
49 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
50 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
51 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
52 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
53 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
54 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
55 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
56 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
57 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
58 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
59 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
60 #define MVPP2_RXQ_POOL_LONG_OFFS 24
61 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
62 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
63 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
64 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
65 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
67 /* Parser Registers */
68 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
69 #define MVPP2_PRS_PORT_LU_MAX 0xf
70 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
71 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
72 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
73 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
74 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
75 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
76 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
77 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
78 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
79 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
80 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
81 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
82 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
83 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
84 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
87 #define MVPP22_RSS_INDEX 0x1500
88 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) ((idx) << 8)
89 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8)
90 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16)
91 #define MVPP22_RSS_TABLE_ENTRY 0x1508
92 #define MVPP22_RSS_TABLE 0x1510
93 #define MVPP22_RSS_TABLE_POINTER(p) (p)
94 #define MVPP22_RSS_WIDTH 0x150c
96 /* Classifier Registers */
97 #define MVPP2_CLS_MODE_REG 0x1800
98 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
99 #define MVPP2_CLS_PORT_WAY_REG 0x1810
100 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
101 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
102 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
103 #define MVPP2_CLS_LKP_TBL_REG 0x1818
104 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
105 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
106 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
107 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
108 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
109 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
110 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
111 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
112 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
113 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
114 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
115 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
117 /* Descriptor Manager Top Registers */
118 #define MVPP2_RXQ_NUM_REG 0x2040
119 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
120 #define MVPP22_DESC_ADDR_OFFS 8
121 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
122 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
123 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
124 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
125 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
126 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
127 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
128 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
129 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
130 #define MVPP2_RXQ_THRESH_REG 0x204c
131 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
132 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
133 #define MVPP2_RXQ_INDEX_REG 0x2050
134 #define MVPP2_TXQ_NUM_REG 0x2080
135 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
136 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
137 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
138 #define MVPP2_TXQ_THRESH_REG 0x2094
139 #define MVPP2_TXQ_THRESH_OFFSET 16
140 #define MVPP2_TXQ_THRESH_MASK 0x3fff
141 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
142 #define MVPP2_TXQ_INDEX_REG 0x2098
143 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
144 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
145 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
146 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
147 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
148 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
149 #define MVPP2_TXQ_PENDING_REG 0x20a0
150 #define MVPP2_TXQ_PENDING_MASK 0x3fff
151 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
152 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
153 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
154 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
155 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
156 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
157 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
158 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
159 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
160 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
161 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
162 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
163 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
164 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
165 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
166 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
167 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
169 /* MBUS bridge registers */
170 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
171 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
172 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
173 #define MVPP2_BASE_ADDR_ENABLE 0x4060
175 /* AXI Bridge Registers */
176 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
177 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
178 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
179 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
180 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
181 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
182 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
183 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
184 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
185 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
186 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
187 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
189 /* Values for AXI Bridge registers */
190 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
191 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
193 #define MVPP22_AXI_CODE_CACHE_OFFS 0
194 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
196 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
197 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
198 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
200 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
201 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
203 /* Interrupt Cause and Mask registers */
204 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))
205 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0
207 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
208 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
209 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
211 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
212 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
213 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
214 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
216 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
217 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
219 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
220 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
221 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
222 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
224 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
225 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
226 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
227 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
228 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
229 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
230 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16
231 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
232 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
233 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
234 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
235 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
236 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
237 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
238 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
239 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
240 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
241 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
242 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
244 /* Buffer Manager registers */
245 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
246 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
247 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
248 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
249 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
250 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
251 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
252 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
253 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
254 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
255 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
256 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
257 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
258 #define MVPP2_BM_START_MASK BIT(0)
259 #define MVPP2_BM_STOP_MASK BIT(1)
260 #define MVPP2_BM_STATE_MASK BIT(4)
261 #define MVPP2_BM_LOW_THRESH_OFFS 8
262 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
263 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
264 MVPP2_BM_LOW_THRESH_OFFS)
265 #define MVPP2_BM_HIGH_THRESH_OFFS 16
266 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
267 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
268 MVPP2_BM_HIGH_THRESH_OFFS)
269 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
270 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
271 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
272 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
273 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
274 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
275 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
276 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
277 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
278 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
279 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444
280 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff
281 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00
282 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8
283 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
284 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
285 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
286 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
287 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
288 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
289 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
290 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
291 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
293 /* TX Scheduler registers */
294 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
295 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
296 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
297 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
298 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
299 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
300 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
301 #define MVPP2_TXP_MTU_MAX 0x7FFFF
302 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
303 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
304 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
305 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
306 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
307 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
308 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
309 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
310 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
311 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
312 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
313 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
314 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
315 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
317 /* TX general registers */
318 #define MVPP2_TX_SNOOP_REG 0x8800
319 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
320 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
323 #define MVPP2_SRC_ADDR_MIDDLE 0x24
324 #define MVPP2_SRC_ADDR_HIGH 0x28
325 #define MVPP2_PHY_AN_CFG0_REG 0x34
326 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
327 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
328 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
330 /* Per-port registers */
331 #define MVPP2_GMAC_CTRL_0_REG 0x0
332 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
333 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
334 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
335 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
336 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
337 #define MVPP2_GMAC_CTRL_1_REG 0x4
338 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
339 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
340 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
341 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
342 #define MVPP2_GMAC_SA_LOW_OFFS 7
343 #define MVPP2_GMAC_CTRL_2_REG 0x8
344 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
345 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1)
346 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
347 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4)
348 #define MVPP2_GMAC_DISABLE_PADDING BIT(5)
349 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
350 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
351 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
352 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
353 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2)
354 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3)
355 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
356 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
357 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
358 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
359 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11)
360 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
361 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
362 #define MVPP2_GMAC_STATUS0 0x10
363 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
364 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
365 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
366 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
367 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
368 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
369 #define MVPP22_GMAC_INT_STAT 0x20
370 #define MVPP22_GMAC_INT_STAT_LINK BIT(1)
371 #define MVPP22_GMAC_INT_MASK 0x24
372 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1)
373 #define MVPP22_GMAC_CTRL_4_REG 0x90
374 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
375 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5)
376 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6)
377 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7)
378 #define MVPP22_GMAC_INT_SUM_MASK 0xa4
379 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
381 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
382 * relative to port->base.
384 #define MVPP22_XLG_CTRL0_REG 0x100
385 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
386 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1)
387 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7)
388 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14)
389 #define MVPP22_XLG_CTRL1_REG 0x104
390 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
391 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
392 #define MVPP22_XLG_STATUS 0x10c
393 #define MVPP22_XLG_STATUS_LINK_UP BIT(0)
394 #define MVPP22_XLG_INT_STAT 0x114
395 #define MVPP22_XLG_INT_STAT_LINK BIT(1)
396 #define MVPP22_XLG_INT_MASK 0x118
397 #define MVPP22_XLG_INT_MASK_LINK BIT(1)
398 #define MVPP22_XLG_CTRL3_REG 0x11c
399 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
400 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
401 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13)
402 #define MVPP22_XLG_EXT_INT_MASK 0x15c
403 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1)
404 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2)
405 #define MVPP22_XLG_CTRL4_REG 0x184
406 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5)
407 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6)
408 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
410 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */
411 #define MVPP22_SMI_MISC_CFG_REG 0x1204
412 #define MVPP22_SMI_POLLING_EN BIT(10)
414 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
416 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
418 /* Descriptor ring Macros */
419 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
420 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
422 /* XPCS registers. PPv2.2 only */
423 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
424 #define MVPP22_MPCS_CTRL 0x14
425 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)
426 #define MVPP22_MPCS_CLK_RESET 0x14c
427 #define MAC_CLK_RESET_SD_TX BIT(0)
428 #define MAC_CLK_RESET_SD_RX BIT(1)
429 #define MAC_CLK_RESET_MAC BIT(2)
430 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
431 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
433 /* XPCS registers. PPv2.2 only */
434 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
435 #define MVPP22_XPCS_CFG0 0x0
436 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3)
437 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5)
439 /* System controller registers. Accessed through a regmap. */
440 #define GENCONF_SOFT_RESET1 0x1108
441 #define GENCONF_SOFT_RESET1_GOP BIT(6)
442 #define GENCONF_PORT_CTRL0 0x1110
443 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1)
444 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29)
445 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31)
446 #define GENCONF_PORT_CTRL1 0x1114
447 #define GENCONF_PORT_CTRL1_EN(p) BIT(p)
448 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28)
449 #define GENCONF_CTRL0 0x1120
450 #define GENCONF_CTRL0_PORT0_RGMII BIT(0)
451 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1)
452 #define GENCONF_CTRL0_PORT1_RGMII BIT(2)
454 /* Various constants */
457 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
458 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
459 #define MVPP2_TXDONE_COAL_USEC 1000
460 #define MVPP2_RX_COAL_PKTS 32
461 #define MVPP2_RX_COAL_USEC 100
463 /* The two bytes Marvell header. Either contains a special value used
464 * by Marvell switches when a specific hardware mode is enabled (not
465 * supported by this driver) or is filled automatically by zeroes on
466 * the RX side. Those two bytes being at the front of the Ethernet
467 * header, they allow to have the IP header aligned on a 4 bytes
468 * boundary automatically: the hardware skips those two bytes on its
471 #define MVPP2_MH_SIZE 2
472 #define MVPP2_ETH_TYPE_LEN 2
473 #define MVPP2_PPPOE_HDR_SIZE 8
474 #define MVPP2_VLAN_TAG_LEN 4
476 /* Lbtd 802.3 type */
477 #define MVPP2_IP_LBDT_TYPE 0xfffa
479 #define MVPP2_TX_CSUM_MAX_SIZE 9800
481 /* Timeout constants */
482 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
483 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
485 #define MVPP2_TX_MTU_MAX 0x7ffff
487 /* Maximum number of T-CONTs of PON port */
488 #define MVPP2_MAX_TCONT 16
490 /* Maximum number of supported ports */
491 #define MVPP2_MAX_PORTS 4
493 /* Maximum number of TXQs used by single port */
494 #define MVPP2_MAX_TXQ 8
496 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO
497 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data),
498 * multiply this value by two to count the maximum number of skb descs needed.
500 #define MVPP2_MAX_TSO_SEGS 300
501 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
503 /* Dfault number of RXQs in use */
504 #define MVPP2_DEFAULT_RXQ 4
506 /* Max number of Rx descriptors */
507 #define MVPP2_MAX_RXD 128
509 /* Max number of Tx descriptors */
510 #define MVPP2_MAX_TXD 1024
512 /* Amount of Tx descriptors that can be reserved at once by CPU */
513 #define MVPP2_CPU_DESC_CHUNK 64
515 /* Max number of Tx descriptors in each aggregated queue */
516 #define MVPP2_AGGR_TXQ_SIZE 256
518 /* Descriptor aligned size */
519 #define MVPP2_DESC_ALIGNED_SIZE 32
521 /* Descriptor alignment mask */
522 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
524 /* RX FIFO constants */
525 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000
526 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000
527 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000
528 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200
529 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80
530 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40
531 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
533 /* TX FIFO constants */
534 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa
535 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3
537 /* RX buffer constants */
538 #define MVPP2_SKB_SHINFO_SIZE \
539 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
541 #define MVPP2_RX_PKT_SIZE(mtu) \
542 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
543 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
545 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
546 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
547 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
548 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
550 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
552 /* IPv6 max L3 address size */
553 #define MVPP2_MAX_L3_ADDR_SIZE 16
556 #define MVPP2_F_LOOPBACK BIT(0)
558 /* Marvell tag types */
559 enum mvpp2_tag_type
{
560 MVPP2_TAG_TYPE_NONE
= 0,
561 MVPP2_TAG_TYPE_MH
= 1,
562 MVPP2_TAG_TYPE_DSA
= 2,
563 MVPP2_TAG_TYPE_EDSA
= 3,
564 MVPP2_TAG_TYPE_VLAN
= 4,
565 MVPP2_TAG_TYPE_LAST
= 5
568 /* Parser constants */
569 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
570 #define MVPP2_PRS_TCAM_WORDS 6
571 #define MVPP2_PRS_SRAM_WORDS 4
572 #define MVPP2_PRS_FLOW_ID_SIZE 64
573 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
574 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
575 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
576 #define MVPP2_PRS_IPV4_HEAD 0x40
577 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
578 #define MVPP2_PRS_IPV4_MC 0xe0
579 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
580 #define MVPP2_PRS_IPV4_BC_MASK 0xff
581 #define MVPP2_PRS_IPV4_IHL 0x5
582 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
583 #define MVPP2_PRS_IPV6_MC 0xff
584 #define MVPP2_PRS_IPV6_MC_MASK 0xff
585 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
586 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
587 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
588 #define MVPP2_PRS_DBL_VLANS_MAX 100
591 * - lookup ID - 4 bits
593 * - additional information - 1 byte
594 * - header data - 8 bytes
595 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
597 #define MVPP2_PRS_AI_BITS 8
598 #define MVPP2_PRS_PORT_MASK 0xff
599 #define MVPP2_PRS_LU_MASK 0xf
600 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
601 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
602 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
603 (((offs) * 2) - ((offs) % 2) + 2)
604 #define MVPP2_PRS_TCAM_AI_BYTE 16
605 #define MVPP2_PRS_TCAM_PORT_BYTE 17
606 #define MVPP2_PRS_TCAM_LU_BYTE 20
607 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
608 #define MVPP2_PRS_TCAM_INV_WORD 5
609 /* Tcam entries ID */
610 #define MVPP2_PE_DROP_ALL 0
611 #define MVPP2_PE_FIRST_FREE_TID 1
612 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
613 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
614 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
615 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
616 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
617 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
618 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
619 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
620 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
621 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
622 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
623 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
624 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
625 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
626 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
627 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
628 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
629 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
630 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
631 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
632 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
633 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
634 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
635 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
636 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
639 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
641 #define MVPP2_PRS_SRAM_RI_OFFS 0
642 #define MVPP2_PRS_SRAM_RI_WORD 0
643 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
644 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
645 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
646 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
647 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
648 #define MVPP2_PRS_SRAM_UDF_OFFS 73
649 #define MVPP2_PRS_SRAM_UDF_BITS 8
650 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
651 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
652 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
653 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
654 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
655 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
656 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
657 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
658 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
659 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
660 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
661 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
662 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
663 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
664 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
665 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
666 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
667 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
668 #define MVPP2_PRS_SRAM_AI_OFFS 90
669 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
670 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
671 #define MVPP2_PRS_SRAM_AI_MASK 0xff
672 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
673 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
674 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
675 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
677 /* Sram result info bits assignment */
678 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
679 #define MVPP2_PRS_RI_DSA_MASK 0x2
680 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
681 #define MVPP2_PRS_RI_VLAN_NONE 0x0
682 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
683 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
684 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
685 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
686 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
687 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
688 #define MVPP2_PRS_RI_L2_UCAST 0x0
689 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
690 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
691 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
692 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
693 #define MVPP2_PRS_RI_L3_UN 0x0
694 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
695 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
696 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
697 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
698 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
699 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
700 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
701 #define MVPP2_PRS_RI_L3_UCAST 0x0
702 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
703 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
704 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
705 #define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17)
706 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
707 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
708 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
709 #define MVPP2_PRS_RI_L4_TCP BIT(22)
710 #define MVPP2_PRS_RI_L4_UDP BIT(23)
711 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
712 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
713 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
714 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
716 /* Sram additional info bits assignment */
717 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
718 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
719 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
720 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
721 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
722 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
723 #define MVPP2_PRS_SINGLE_VLAN_AI 0
724 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
727 #define MVPP2_PRS_TAGGED true
728 #define MVPP2_PRS_UNTAGGED false
729 #define MVPP2_PRS_EDSA true
730 #define MVPP2_PRS_DSA false
732 /* MAC entries, shadow udf */
734 MVPP2_PRS_UDF_MAC_DEF
,
735 MVPP2_PRS_UDF_MAC_RANGE
,
736 MVPP2_PRS_UDF_L2_DEF
,
737 MVPP2_PRS_UDF_L2_DEF_COPY
,
738 MVPP2_PRS_UDF_L2_USER
,
742 enum mvpp2_prs_lookup
{
756 enum mvpp2_prs_l3_cast
{
757 MVPP2_PRS_L3_UNI_CAST
,
758 MVPP2_PRS_L3_MULTI_CAST
,
759 MVPP2_PRS_L3_BROAD_CAST
762 /* Classifier constants */
763 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
764 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
765 #define MVPP2_CLS_LKP_TBL_SIZE 64
766 #define MVPP2_CLS_RX_QUEUES 256
769 #define MVPP22_RSS_TABLE_ENTRIES 32
772 #define MVPP2_BM_POOLS_NUM 8
773 #define MVPP2_BM_LONG_BUF_NUM 1024
774 #define MVPP2_BM_SHORT_BUF_NUM 2048
775 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
776 #define MVPP2_BM_POOL_PTR_ALIGN 128
777 #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port)
778 #define MVPP2_BM_SWF_SHORT_POOL 3
780 /* BM cookie (32 bits) definition */
781 #define MVPP2_BM_COOKIE_POOL_OFFS 8
782 #define MVPP2_BM_COOKIE_CPU_OFFS 24
784 /* BM short pool packet size
785 * These value assure that for SWF the total number
786 * of bytes allocated for each buffer will be 512
788 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
790 #define MVPP21_ADDR_SPACE_SZ 0
791 #define MVPP22_ADDR_SPACE_SZ SZ_64K
793 #define MVPP2_MAX_THREADS 8
794 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS
802 /* GMAC MIB Counters register definitions */
803 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000
804 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400
805 #define MVPP22_MIB_COUNTERS_OFFSET 0x0
806 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100
808 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0
809 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8
810 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc
811 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10
812 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18
813 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c
814 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20
815 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24
816 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28
817 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c
818 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30
819 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
820 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38
821 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40
822 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48
823 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c
824 #define MVPP2_MIB_FC_SENT 0x54
825 #define MVPP2_MIB_FC_RCVD 0x58
826 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c
827 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60
828 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64
829 #define MVPP2_MIB_OVERSIZE_RCVD 0x68
830 #define MVPP2_MIB_JABBER_RCVD 0x6c
831 #define MVPP2_MIB_MAC_RCV_ERROR 0x70
832 #define MVPP2_MIB_BAD_CRC_EVENT 0x74
833 #define MVPP2_MIB_COLLISION 0x78
834 #define MVPP2_MIB_LATE_COLLISION 0x7c
836 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ)
840 /* Shared Packet Processor resources */
842 /* Shared registers' base addresses */
843 void __iomem
*lms_base
;
844 void __iomem
*iface_base
;
846 /* On PPv2.2, each "software thread" can access the base
847 * register through a separate address space, each 64 KB apart
848 * from each other. Typically, such address spaces will be
851 void __iomem
*swth_base
[MVPP2_MAX_THREADS
];
853 /* On PPv2.2, some port control registers are located into the system
854 * controller space. These registers are accessible through a regmap.
856 struct regmap
*sysctrl_base
;
864 /* List of pointers to port structures */
866 struct mvpp2_port
**port_list
;
868 /* Aggregated TXQs */
869 struct mvpp2_tx_queue
*aggr_txqs
;
872 struct mvpp2_bm_pool
*bm_pools
;
874 /* PRS shadow table */
875 struct mvpp2_prs_shadow
*prs_shadow
;
876 /* PRS auxiliary table for double vlan entries control */
877 bool *prs_double_vlans
;
883 enum { MVPP21
, MVPP22
} hw_version
;
885 /* Maximum number of RXQs per port */
886 unsigned int max_port_rxqs
;
888 /* Workqueue to gather hardware statistics */
890 struct workqueue_struct
*stats_queue
;
893 struct mvpp2_pcpu_stats
{
894 struct u64_stats_sync syncp
;
901 /* Per-CPU port control */
902 struct mvpp2_port_pcpu
{
903 struct hrtimer tx_done_timer
;
904 bool timer_scheduled
;
905 /* Tasklet for egress finalization */
906 struct tasklet_struct tx_done_tasklet
;
909 struct mvpp2_queue_vector
{
911 struct napi_struct napi
;
912 enum { MVPP2_QUEUE_VECTOR_SHARED
, MVPP2_QUEUE_VECTOR_PRIVATE
} type
;
917 u32 pending_cause_rx
;
918 struct mvpp2_port
*port
;
924 /* Index of the port from the "group of ports" complex point
933 /* Per-port registers' base address */
935 void __iomem
*stats_base
;
937 struct mvpp2_rx_queue
**rxqs
;
939 struct mvpp2_tx_queue
**txqs
;
941 struct net_device
*dev
;
945 /* Per-CPU port control */
946 struct mvpp2_port_pcpu __percpu
*pcpu
;
953 struct mvpp2_pcpu_stats __percpu
*stats
;
956 /* Per-port work and its lock to gather hardware statistics */
957 struct mutex gather_stats_lock
;
958 struct delayed_work stats_work
;
960 phy_interface_t phy_interface
;
961 struct device_node
*phy_node
;
967 struct mvpp2_bm_pool
*pool_long
;
968 struct mvpp2_bm_pool
*pool_short
;
970 /* Index of first port's physical RXQ */
973 struct mvpp2_queue_vector qvecs
[MVPP2_MAX_QVECS
];
980 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
981 * layout of the transmit and reception DMA descriptors, and their
982 * layout is therefore defined by the hardware design
985 #define MVPP2_TXD_L3_OFF_SHIFT 0
986 #define MVPP2_TXD_IP_HLEN_SHIFT 8
987 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
988 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
989 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
990 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
991 #define MVPP2_TXD_L4_UDP BIT(24)
992 #define MVPP2_TXD_L3_IP6 BIT(26)
993 #define MVPP2_TXD_L_DESC BIT(28)
994 #define MVPP2_TXD_F_DESC BIT(29)
996 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
997 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
998 #define MVPP2_RXD_ERR_CRC 0x0
999 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1000 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1001 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1002 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1003 #define MVPP2_RXD_HWF_SYNC BIT(21)
1004 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1005 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1006 #define MVPP2_RXD_L4_TCP BIT(25)
1007 #define MVPP2_RXD_L4_UDP BIT(26)
1008 #define MVPP2_RXD_L3_IP4 BIT(28)
1009 #define MVPP2_RXD_L3_IP6 BIT(30)
1010 #define MVPP2_RXD_BUF_HDR BIT(31)
1012 /* HW TX descriptor for PPv2.1 */
1013 struct mvpp21_tx_desc
{
1014 u32 command
; /* Options used by HW for packet transmitting.*/
1015 u8 packet_offset
; /* the offset from the buffer beginning */
1016 u8 phys_txq
; /* destination queue ID */
1017 u16 data_size
; /* data size of transmitted packet in bytes */
1018 u32 buf_dma_addr
; /* physical addr of transmitted buffer */
1019 u32 buf_cookie
; /* cookie for access to TX buffer in tx path */
1020 u32 reserved1
[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1021 u32 reserved2
; /* reserved (for future use) */
1024 /* HW RX descriptor for PPv2.1 */
1025 struct mvpp21_rx_desc
{
1026 u32 status
; /* info about received packet */
1027 u16 reserved1
; /* parser_info (for future use, PnC) */
1028 u16 data_size
; /* size of received packet in bytes */
1029 u32 buf_dma_addr
; /* physical address of the buffer */
1030 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
1031 u16 reserved2
; /* gem_port_id (for future use, PON) */
1032 u16 reserved3
; /* csum_l4 (for future use, PnC) */
1033 u8 reserved4
; /* bm_qset (for future use, BM) */
1035 u16 reserved6
; /* classify_info (for future use, PnC) */
1036 u32 reserved7
; /* flow_id (for future use, PnC) */
1040 /* HW TX descriptor for PPv2.2 */
1041 struct mvpp22_tx_desc
{
1047 u64 buf_dma_addr_ptp
;
1048 u64 buf_cookie_misc
;
1051 /* HW RX descriptor for PPv2.2 */
1052 struct mvpp22_rx_desc
{
1058 u64 buf_dma_addr_key_hash
;
1059 u64 buf_cookie_misc
;
1062 /* Opaque type used by the driver to manipulate the HW TX and RX
1065 struct mvpp2_tx_desc
{
1067 struct mvpp21_tx_desc pp21
;
1068 struct mvpp22_tx_desc pp22
;
1072 struct mvpp2_rx_desc
{
1074 struct mvpp21_rx_desc pp21
;
1075 struct mvpp22_rx_desc pp22
;
1079 struct mvpp2_txq_pcpu_buf
{
1080 /* Transmitted SKB */
1081 struct sk_buff
*skb
;
1083 /* Physical address of transmitted buffer */
1086 /* Size transmitted */
1090 /* Per-CPU Tx queue control */
1091 struct mvpp2_txq_pcpu
{
1094 /* Number of Tx DMA descriptors in the descriptor ring */
1097 /* Number of currently used Tx DMA descriptor in the
1105 /* Number of Tx DMA descriptors reserved for each CPU */
1108 /* Infos about transmitted buffers */
1109 struct mvpp2_txq_pcpu_buf
*buffs
;
1111 /* Index of last TX DMA descriptor that was inserted */
1114 /* Index of the TX DMA descriptor to be cleaned up */
1117 /* DMA buffer for TSO headers */
1119 dma_addr_t tso_headers_dma
;
1122 struct mvpp2_tx_queue
{
1123 /* Physical number of this Tx queue */
1126 /* Logical number of this Tx queue */
1129 /* Number of Tx DMA descriptors in the descriptor ring */
1132 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1135 /* Per-CPU control of physical Tx queues */
1136 struct mvpp2_txq_pcpu __percpu
*pcpu
;
1140 /* Virtual address of thex Tx DMA descriptors array */
1141 struct mvpp2_tx_desc
*descs
;
1143 /* DMA address of the Tx DMA descriptors array */
1144 dma_addr_t descs_dma
;
1146 /* Index of the last Tx DMA descriptor */
1149 /* Index of the next Tx DMA descriptor to process */
1150 int next_desc_to_proc
;
1153 struct mvpp2_rx_queue
{
1154 /* RX queue number, in the range 0-31 for physical RXQs */
1157 /* Num of rx descriptors in the rx descriptor ring */
1163 /* Virtual address of the RX DMA descriptors array */
1164 struct mvpp2_rx_desc
*descs
;
1166 /* DMA address of the RX DMA descriptors array */
1167 dma_addr_t descs_dma
;
1169 /* Index of the last RX DMA descriptor */
1172 /* Index of the next RX DMA descriptor to process */
1173 int next_desc_to_proc
;
1175 /* ID of port to which physical RXQ is mapped */
1178 /* Port's logic RXQ number to which physical RXQ is mapped */
1182 union mvpp2_prs_tcam_entry
{
1183 u32 word
[MVPP2_PRS_TCAM_WORDS
];
1184 u8 byte
[MVPP2_PRS_TCAM_WORDS
* 4];
1187 union mvpp2_prs_sram_entry
{
1188 u32 word
[MVPP2_PRS_SRAM_WORDS
];
1189 u8 byte
[MVPP2_PRS_SRAM_WORDS
* 4];
1192 struct mvpp2_prs_entry
{
1194 union mvpp2_prs_tcam_entry tcam
;
1195 union mvpp2_prs_sram_entry sram
;
1198 struct mvpp2_prs_shadow
{
1205 /* User defined offset */
1213 struct mvpp2_cls_flow_entry
{
1215 u32 data
[MVPP2_CLS_FLOWS_TBL_DATA_WORDS
];
1218 struct mvpp2_cls_lookup_entry
{
1224 struct mvpp2_bm_pool
{
1225 /* Pool number in the range 0-7 */
1227 enum mvpp2_bm_type type
;
1229 /* Buffer Pointers Pool External (BPPE) size */
1231 /* BPPE size in bytes */
1233 /* Number of buffers for this pool */
1235 /* Pool buffer size */
1241 /* BPPE virtual base address */
1243 /* BPPE DMA base address */
1244 dma_addr_t dma_addr
;
1246 /* Ports using BM pool */
1250 #define IS_TSO_HEADER(txq_pcpu, addr) \
1251 ((addr) >= (txq_pcpu)->tso_headers_dma && \
1252 (addr) < (txq_pcpu)->tso_headers_dma + \
1253 (txq_pcpu)->size * TSO_HEADER_SIZE)
1256 #define MVPP2_QDIST_SINGLE_MODE 0
1257 #define MVPP2_QDIST_MULTI_MODE 1
1259 static int queue_mode
= MVPP2_QDIST_SINGLE_MODE
;
1261 module_param(queue_mode
, int, 0444);
1262 MODULE_PARM_DESC(queue_mode
, "Set queue_mode (single=0, multi=1)");
1264 #define MVPP2_DRIVER_NAME "mvpp2"
1265 #define MVPP2_DRIVER_VERSION "1.0"
1267 /* Utility/helper methods */
1269 static void mvpp2_write(struct mvpp2
*priv
, u32 offset
, u32 data
)
1271 writel(data
, priv
->swth_base
[0] + offset
);
1274 static u32
mvpp2_read(struct mvpp2
*priv
, u32 offset
)
1276 return readl(priv
->swth_base
[0] + offset
);
1279 /* These accessors should be used to access:
1281 * - per-CPU registers, where each CPU has its own copy of the
1284 * MVPP2_BM_VIRT_ALLOC_REG
1285 * MVPP2_BM_ADDR_HIGH_ALLOC
1286 * MVPP22_BM_ADDR_HIGH_RLS_REG
1287 * MVPP2_BM_VIRT_RLS_REG
1288 * MVPP2_ISR_RX_TX_CAUSE_REG
1289 * MVPP2_ISR_RX_TX_MASK_REG
1291 * MVPP2_AGGR_TXQ_UPDATE_REG
1292 * MVPP2_TXQ_RSVD_REQ_REG
1293 * MVPP2_TXQ_RSVD_RSLT_REG
1294 * MVPP2_TXQ_SENT_REG
1297 * - global registers that must be accessed through a specific CPU
1298 * window, because they are related to an access to a per-CPU
1301 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
1302 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
1303 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
1304 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
1305 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
1306 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
1307 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
1308 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
1309 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
1310 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
1311 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
1312 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
1313 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
1315 static void mvpp2_percpu_write(struct mvpp2
*priv
, int cpu
,
1316 u32 offset
, u32 data
)
1318 writel(data
, priv
->swth_base
[cpu
] + offset
);
1321 static u32
mvpp2_percpu_read(struct mvpp2
*priv
, int cpu
,
1324 return readl(priv
->swth_base
[cpu
] + offset
);
1327 static dma_addr_t
mvpp2_txdesc_dma_addr_get(struct mvpp2_port
*port
,
1328 struct mvpp2_tx_desc
*tx_desc
)
1330 if (port
->priv
->hw_version
== MVPP21
)
1331 return tx_desc
->pp21
.buf_dma_addr
;
1333 return tx_desc
->pp22
.buf_dma_addr_ptp
& GENMASK_ULL(40, 0);
1336 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port
*port
,
1337 struct mvpp2_tx_desc
*tx_desc
,
1338 dma_addr_t dma_addr
)
1340 dma_addr_t addr
, offset
;
1342 addr
= dma_addr
& ~MVPP2_TX_DESC_ALIGN
;
1343 offset
= dma_addr
& MVPP2_TX_DESC_ALIGN
;
1345 if (port
->priv
->hw_version
== MVPP21
) {
1346 tx_desc
->pp21
.buf_dma_addr
= addr
;
1347 tx_desc
->pp21
.packet_offset
= offset
;
1349 u64 val
= (u64
)addr
;
1351 tx_desc
->pp22
.buf_dma_addr_ptp
&= ~GENMASK_ULL(40, 0);
1352 tx_desc
->pp22
.buf_dma_addr_ptp
|= val
;
1353 tx_desc
->pp22
.packet_offset
= offset
;
1357 static size_t mvpp2_txdesc_size_get(struct mvpp2_port
*port
,
1358 struct mvpp2_tx_desc
*tx_desc
)
1360 if (port
->priv
->hw_version
== MVPP21
)
1361 return tx_desc
->pp21
.data_size
;
1363 return tx_desc
->pp22
.data_size
;
1366 static void mvpp2_txdesc_size_set(struct mvpp2_port
*port
,
1367 struct mvpp2_tx_desc
*tx_desc
,
1370 if (port
->priv
->hw_version
== MVPP21
)
1371 tx_desc
->pp21
.data_size
= size
;
1373 tx_desc
->pp22
.data_size
= size
;
1376 static void mvpp2_txdesc_txq_set(struct mvpp2_port
*port
,
1377 struct mvpp2_tx_desc
*tx_desc
,
1380 if (port
->priv
->hw_version
== MVPP21
)
1381 tx_desc
->pp21
.phys_txq
= txq
;
1383 tx_desc
->pp22
.phys_txq
= txq
;
1386 static void mvpp2_txdesc_cmd_set(struct mvpp2_port
*port
,
1387 struct mvpp2_tx_desc
*tx_desc
,
1388 unsigned int command
)
1390 if (port
->priv
->hw_version
== MVPP21
)
1391 tx_desc
->pp21
.command
= command
;
1393 tx_desc
->pp22
.command
= command
;
1396 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port
*port
,
1397 struct mvpp2_tx_desc
*tx_desc
)
1399 if (port
->priv
->hw_version
== MVPP21
)
1400 return tx_desc
->pp21
.packet_offset
;
1402 return tx_desc
->pp22
.packet_offset
;
1405 static dma_addr_t
mvpp2_rxdesc_dma_addr_get(struct mvpp2_port
*port
,
1406 struct mvpp2_rx_desc
*rx_desc
)
1408 if (port
->priv
->hw_version
== MVPP21
)
1409 return rx_desc
->pp21
.buf_dma_addr
;
1411 return rx_desc
->pp22
.buf_dma_addr_key_hash
& GENMASK_ULL(40, 0);
1414 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port
*port
,
1415 struct mvpp2_rx_desc
*rx_desc
)
1417 if (port
->priv
->hw_version
== MVPP21
)
1418 return rx_desc
->pp21
.buf_cookie
;
1420 return rx_desc
->pp22
.buf_cookie_misc
& GENMASK_ULL(40, 0);
1423 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port
*port
,
1424 struct mvpp2_rx_desc
*rx_desc
)
1426 if (port
->priv
->hw_version
== MVPP21
)
1427 return rx_desc
->pp21
.data_size
;
1429 return rx_desc
->pp22
.data_size
;
1432 static u32
mvpp2_rxdesc_status_get(struct mvpp2_port
*port
,
1433 struct mvpp2_rx_desc
*rx_desc
)
1435 if (port
->priv
->hw_version
== MVPP21
)
1436 return rx_desc
->pp21
.status
;
1438 return rx_desc
->pp22
.status
;
1441 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu
*txq_pcpu
)
1443 txq_pcpu
->txq_get_index
++;
1444 if (txq_pcpu
->txq_get_index
== txq_pcpu
->size
)
1445 txq_pcpu
->txq_get_index
= 0;
1448 static void mvpp2_txq_inc_put(struct mvpp2_port
*port
,
1449 struct mvpp2_txq_pcpu
*txq_pcpu
,
1450 struct sk_buff
*skb
,
1451 struct mvpp2_tx_desc
*tx_desc
)
1453 struct mvpp2_txq_pcpu_buf
*tx_buf
=
1454 txq_pcpu
->buffs
+ txq_pcpu
->txq_put_index
;
1456 tx_buf
->size
= mvpp2_txdesc_size_get(port
, tx_desc
);
1457 tx_buf
->dma
= mvpp2_txdesc_dma_addr_get(port
, tx_desc
) +
1458 mvpp2_txdesc_offset_get(port
, tx_desc
);
1459 txq_pcpu
->txq_put_index
++;
1460 if (txq_pcpu
->txq_put_index
== txq_pcpu
->size
)
1461 txq_pcpu
->txq_put_index
= 0;
1464 /* Get number of physical egress port */
1465 static inline int mvpp2_egress_port(struct mvpp2_port
*port
)
1467 return MVPP2_MAX_TCONT
+ port
->id
;
1470 /* Get number of physical TXQ */
1471 static inline int mvpp2_txq_phys(int port
, int txq
)
1473 return (MVPP2_MAX_TCONT
+ port
) * MVPP2_MAX_TXQ
+ txq
;
1476 /* Parser configuration routines */
1478 /* Update parser tcam and sram hw entries */
1479 static int mvpp2_prs_hw_write(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1483 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1486 /* Clear entry invalidation bit */
1487 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] &= ~MVPP2_PRS_TCAM_INV_MASK
;
1489 /* Write tcam index - indirect access */
1490 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1491 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1492 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), pe
->tcam
.word
[i
]);
1494 /* Write sram index - indirect access */
1495 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1496 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1497 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), pe
->sram
.word
[i
]);
1502 /* Read tcam entry from hw */
1503 static int mvpp2_prs_hw_read(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1507 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1510 /* Write tcam index - indirect access */
1511 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1513 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] = mvpp2_read(priv
,
1514 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
));
1515 if (pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] & MVPP2_PRS_TCAM_INV_MASK
)
1516 return MVPP2_PRS_TCAM_ENTRY_INVALID
;
1518 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1519 pe
->tcam
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_TCAM_DATA_REG(i
));
1521 /* Write sram index - indirect access */
1522 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1523 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1524 pe
->sram
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_SRAM_DATA_REG(i
));
1529 /* Invalidate tcam hw entry */
1530 static void mvpp2_prs_hw_inv(struct mvpp2
*priv
, int index
)
1532 /* Write index - indirect access */
1533 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
1534 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
),
1535 MVPP2_PRS_TCAM_INV_MASK
);
1538 /* Enable shadow table entry and set its lookup ID */
1539 static void mvpp2_prs_shadow_set(struct mvpp2
*priv
, int index
, int lu
)
1541 priv
->prs_shadow
[index
].valid
= true;
1542 priv
->prs_shadow
[index
].lu
= lu
;
1545 /* Update ri fields in shadow table entry */
1546 static void mvpp2_prs_shadow_ri_set(struct mvpp2
*priv
, int index
,
1547 unsigned int ri
, unsigned int ri_mask
)
1549 priv
->prs_shadow
[index
].ri_mask
= ri_mask
;
1550 priv
->prs_shadow
[index
].ri
= ri
;
1553 /* Update lookup field in tcam sw entry */
1554 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry
*pe
, unsigned int lu
)
1556 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE
);
1558 pe
->tcam
.byte
[MVPP2_PRS_TCAM_LU_BYTE
] = lu
;
1559 pe
->tcam
.byte
[enable_off
] = MVPP2_PRS_LU_MASK
;
1562 /* Update mask for single port in tcam sw entry */
1563 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry
*pe
,
1564 unsigned int port
, bool add
)
1566 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1569 pe
->tcam
.byte
[enable_off
] &= ~(1 << port
);
1571 pe
->tcam
.byte
[enable_off
] |= 1 << port
;
1574 /* Update port map in tcam sw entry */
1575 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry
*pe
,
1578 unsigned char port_mask
= MVPP2_PRS_PORT_MASK
;
1579 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1581 pe
->tcam
.byte
[MVPP2_PRS_TCAM_PORT_BYTE
] = 0;
1582 pe
->tcam
.byte
[enable_off
] &= ~port_mask
;
1583 pe
->tcam
.byte
[enable_off
] |= ~ports
& MVPP2_PRS_PORT_MASK
;
1586 /* Obtain port map from tcam sw entry */
1587 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry
*pe
)
1589 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1591 return ~(pe
->tcam
.byte
[enable_off
]) & MVPP2_PRS_PORT_MASK
;
1594 /* Set byte of data and its enable bits in tcam sw entry */
1595 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry
*pe
,
1596 unsigned int offs
, unsigned char byte
,
1597 unsigned char enable
)
1599 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)] = byte
;
1600 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)] = enable
;
1603 /* Get byte of data and its enable bits from tcam sw entry */
1604 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry
*pe
,
1605 unsigned int offs
, unsigned char *byte
,
1606 unsigned char *enable
)
1608 *byte
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)];
1609 *enable
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)];
1612 /* Compare tcam data bytes with a pattern */
1613 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry
*pe
, int offs
,
1616 int off
= MVPP2_PRS_TCAM_DATA_BYTE(offs
);
1619 tcam_data
= (pe
->tcam
.byte
[off
+ 1] << 8) | pe
->tcam
.byte
[off
];
1620 if (tcam_data
!= data
)
1625 /* Update ai bits in tcam sw entry */
1626 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry
*pe
,
1627 unsigned int bits
, unsigned int enable
)
1629 int i
, ai_idx
= MVPP2_PRS_TCAM_AI_BYTE
;
1631 for (i
= 0; i
< MVPP2_PRS_AI_BITS
; i
++) {
1633 if (!(enable
& BIT(i
)))
1637 pe
->tcam
.byte
[ai_idx
] |= 1 << i
;
1639 pe
->tcam
.byte
[ai_idx
] &= ~(1 << i
);
1642 pe
->tcam
.byte
[MVPP2_PRS_TCAM_EN_OFFS(ai_idx
)] |= enable
;
1645 /* Get ai bits from tcam sw entry */
1646 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry
*pe
)
1648 return pe
->tcam
.byte
[MVPP2_PRS_TCAM_AI_BYTE
];
1651 /* Set ethertype in tcam sw entry */
1652 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry
*pe
, int offset
,
1653 unsigned short ethertype
)
1655 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 0, ethertype
>> 8, 0xff);
1656 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 1, ethertype
& 0xff, 0xff);
1659 /* Set bits in sram sw entry */
1660 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry
*pe
, int bit_num
,
1663 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] |= (val
<< (bit_num
% 8));
1666 /* Clear bits in sram sw entry */
1667 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry
*pe
, int bit_num
,
1670 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] &= ~(val
<< (bit_num
% 8));
1673 /* Update ri bits in sram sw entry */
1674 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry
*pe
,
1675 unsigned int bits
, unsigned int mask
)
1679 for (i
= 0; i
< MVPP2_PRS_SRAM_RI_CTRL_BITS
; i
++) {
1680 int ri_off
= MVPP2_PRS_SRAM_RI_OFFS
;
1682 if (!(mask
& BIT(i
)))
1686 mvpp2_prs_sram_bits_set(pe
, ri_off
+ i
, 1);
1688 mvpp2_prs_sram_bits_clear(pe
, ri_off
+ i
, 1);
1690 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_RI_CTRL_OFFS
+ i
, 1);
1694 /* Obtain ri bits from sram sw entry */
1695 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry
*pe
)
1697 return pe
->sram
.word
[MVPP2_PRS_SRAM_RI_WORD
];
1700 /* Update ai bits in sram sw entry */
1701 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry
*pe
,
1702 unsigned int bits
, unsigned int mask
)
1705 int ai_off
= MVPP2_PRS_SRAM_AI_OFFS
;
1707 for (i
= 0; i
< MVPP2_PRS_SRAM_AI_CTRL_BITS
; i
++) {
1709 if (!(mask
& BIT(i
)))
1713 mvpp2_prs_sram_bits_set(pe
, ai_off
+ i
, 1);
1715 mvpp2_prs_sram_bits_clear(pe
, ai_off
+ i
, 1);
1717 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_AI_CTRL_OFFS
+ i
, 1);
1721 /* Read ai bits from sram sw entry */
1722 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry
*pe
)
1725 int ai_off
= MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS
);
1726 int ai_en_off
= ai_off
+ 1;
1727 int ai_shift
= MVPP2_PRS_SRAM_AI_OFFS
% 8;
1729 bits
= (pe
->sram
.byte
[ai_off
] >> ai_shift
) |
1730 (pe
->sram
.byte
[ai_en_off
] << (8 - ai_shift
));
1735 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1738 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry
*pe
,
1741 int sram_next_off
= MVPP2_PRS_SRAM_NEXT_LU_OFFS
;
1743 mvpp2_prs_sram_bits_clear(pe
, sram_next_off
,
1744 MVPP2_PRS_SRAM_NEXT_LU_MASK
);
1745 mvpp2_prs_sram_bits_set(pe
, sram_next_off
, lu
);
1748 /* In the sram sw entry set sign and value of the next lookup offset
1749 * and the offset value generated to the classifier
1751 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry
*pe
, int shift
,
1756 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1759 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1763 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS
)] =
1764 (unsigned char)shift
;
1766 /* Reset and set operation */
1767 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
,
1768 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
);
1769 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
, op
);
1771 /* Set base offset as current */
1772 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1775 /* In the sram sw entry set sign and value of the user defined offset
1776 * generated to the classifier
1778 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry
*pe
,
1779 unsigned int type
, int offset
,
1784 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1785 offset
= 0 - offset
;
1787 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1791 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_OFFS
,
1792 MVPP2_PRS_SRAM_UDF_MASK
);
1793 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_OFFS
, offset
);
1794 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1795 MVPP2_PRS_SRAM_UDF_BITS
)] &=
1796 ~(MVPP2_PRS_SRAM_UDF_MASK
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1797 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1798 MVPP2_PRS_SRAM_UDF_BITS
)] |=
1799 (offset
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1801 /* Set offset type */
1802 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
,
1803 MVPP2_PRS_SRAM_UDF_TYPE_MASK
);
1804 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
, type
);
1806 /* Set offset operation */
1807 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
,
1808 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
);
1809 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
, op
);
1811 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1812 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] &=
1813 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
>>
1814 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1816 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1817 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] |=
1818 (op
>> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1820 /* Set base offset as current */
1821 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1824 /* Find parser flow entry */
1825 static struct mvpp2_prs_entry
*mvpp2_prs_flow_find(struct mvpp2
*priv
, int flow
)
1827 struct mvpp2_prs_entry
*pe
;
1830 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1833 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
1835 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1836 for (tid
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1; tid
>= 0; tid
--) {
1839 if (!priv
->prs_shadow
[tid
].valid
||
1840 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_FLOWS
)
1844 mvpp2_prs_hw_read(priv
, pe
);
1845 bits
= mvpp2_prs_sram_ai_get(pe
);
1847 /* Sram store classification lookup ID in AI bits [5:0] */
1848 if ((bits
& MVPP2_PRS_FLOW_ID_MASK
) == flow
)
1856 /* Return first free tcam index, seeking from start to end */
1857 static int mvpp2_prs_tcam_first_free(struct mvpp2
*priv
, unsigned char start
,
1865 if (end
>= MVPP2_PRS_TCAM_SRAM_SIZE
)
1866 end
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1;
1868 for (tid
= start
; tid
<= end
; tid
++) {
1869 if (!priv
->prs_shadow
[tid
].valid
)
1876 /* Enable/disable dropping all mac da's */
1877 static void mvpp2_prs_mac_drop_all_set(struct mvpp2
*priv
, int port
, bool add
)
1879 struct mvpp2_prs_entry pe
;
1881 if (priv
->prs_shadow
[MVPP2_PE_DROP_ALL
].valid
) {
1882 /* Entry exist - update port only */
1883 pe
.index
= MVPP2_PE_DROP_ALL
;
1884 mvpp2_prs_hw_read(priv
, &pe
);
1886 /* Entry doesn't exist - create new */
1887 memset(&pe
, 0, sizeof(pe
));
1888 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1889 pe
.index
= MVPP2_PE_DROP_ALL
;
1891 /* Non-promiscuous mode for all ports - DROP unknown packets */
1892 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
1893 MVPP2_PRS_RI_DROP_MASK
);
1895 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1896 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1898 /* Update shadow table */
1899 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1901 /* Mask all ports */
1902 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1905 /* Update port mask */
1906 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1908 mvpp2_prs_hw_write(priv
, &pe
);
1911 /* Set port to promiscuous mode */
1912 static void mvpp2_prs_mac_promisc_set(struct mvpp2
*priv
, int port
, bool add
)
1914 struct mvpp2_prs_entry pe
;
1916 /* Promiscuous mode - Accept unknown packets */
1918 if (priv
->prs_shadow
[MVPP2_PE_MAC_PROMISCUOUS
].valid
) {
1919 /* Entry exist - update port only */
1920 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1921 mvpp2_prs_hw_read(priv
, &pe
);
1923 /* Entry doesn't exist - create new */
1924 memset(&pe
, 0, sizeof(pe
));
1925 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1926 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1928 /* Continue - set next lookup */
1929 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1931 /* Set result info bits */
1932 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_UCAST
,
1933 MVPP2_PRS_RI_L2_CAST_MASK
);
1935 /* Shift to ethertype */
1936 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1937 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1939 /* Mask all ports */
1940 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1942 /* Update shadow table */
1943 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1946 /* Update port mask */
1947 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1949 mvpp2_prs_hw_write(priv
, &pe
);
1952 /* Accept multicast */
1953 static void mvpp2_prs_mac_multi_set(struct mvpp2
*priv
, int port
, int index
,
1956 struct mvpp2_prs_entry pe
;
1957 unsigned char da_mc
;
1959 /* Ethernet multicast address first byte is
1960 * 0x01 for IPv4 and 0x33 for IPv6
1962 da_mc
= (index
== MVPP2_PE_MAC_MC_ALL
) ? 0x01 : 0x33;
1964 if (priv
->prs_shadow
[index
].valid
) {
1965 /* Entry exist - update port only */
1967 mvpp2_prs_hw_read(priv
, &pe
);
1969 /* Entry doesn't exist - create new */
1970 memset(&pe
, 0, sizeof(pe
));
1971 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1974 /* Continue - set next lookup */
1975 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1977 /* Set result info bits */
1978 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_MCAST
,
1979 MVPP2_PRS_RI_L2_CAST_MASK
);
1981 /* Update tcam entry data first byte */
1982 mvpp2_prs_tcam_data_byte_set(&pe
, 0, da_mc
, 0xff);
1984 /* Shift to ethertype */
1985 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1986 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1988 /* Mask all ports */
1989 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1991 /* Update shadow table */
1992 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1995 /* Update port mask */
1996 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1998 mvpp2_prs_hw_write(priv
, &pe
);
2001 /* Set entry for dsa packets */
2002 static void mvpp2_prs_dsa_tag_set(struct mvpp2
*priv
, int port
, bool add
,
2003 bool tagged
, bool extend
)
2005 struct mvpp2_prs_entry pe
;
2009 tid
= tagged
? MVPP2_PE_EDSA_TAGGED
: MVPP2_PE_EDSA_UNTAGGED
;
2012 tid
= tagged
? MVPP2_PE_DSA_TAGGED
: MVPP2_PE_DSA_UNTAGGED
;
2016 if (priv
->prs_shadow
[tid
].valid
) {
2017 /* Entry exist - update port only */
2019 mvpp2_prs_hw_read(priv
, &pe
);
2021 /* Entry doesn't exist - create new */
2022 memset(&pe
, 0, sizeof(pe
));
2023 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
2026 /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/
2027 mvpp2_prs_sram_shift_set(&pe
, shift
,
2028 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2030 /* Update shadow table */
2031 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_DSA
);
2034 /* Set tagged bit in DSA tag */
2035 mvpp2_prs_tcam_data_byte_set(&pe
, 0,
2036 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
,
2037 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
);
2038 /* Clear all ai bits for next iteration */
2039 mvpp2_prs_sram_ai_update(&pe
, 0,
2040 MVPP2_PRS_SRAM_AI_MASK
);
2041 /* If packet is tagged continue check vlans */
2042 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
2044 /* Set result info bits to 'no vlans' */
2045 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_NONE
,
2046 MVPP2_PRS_RI_VLAN_MASK
);
2047 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2050 /* Mask all ports */
2051 mvpp2_prs_tcam_port_map_set(&pe
, 0);
2054 /* Update port mask */
2055 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
2057 mvpp2_prs_hw_write(priv
, &pe
);
2060 /* Set entry for dsa ethertype */
2061 static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2
*priv
, int port
,
2062 bool add
, bool tagged
, bool extend
)
2064 struct mvpp2_prs_entry pe
;
2065 int tid
, shift
, port_mask
;
2068 tid
= tagged
? MVPP2_PE_ETYPE_EDSA_TAGGED
:
2069 MVPP2_PE_ETYPE_EDSA_UNTAGGED
;
2073 tid
= tagged
? MVPP2_PE_ETYPE_DSA_TAGGED
:
2074 MVPP2_PE_ETYPE_DSA_UNTAGGED
;
2075 port_mask
= MVPP2_PRS_PORT_MASK
;
2079 if (priv
->prs_shadow
[tid
].valid
) {
2080 /* Entry exist - update port only */
2082 mvpp2_prs_hw_read(priv
, &pe
);
2084 /* Entry doesn't exist - create new */
2085 memset(&pe
, 0, sizeof(pe
));
2086 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
2090 mvpp2_prs_match_etype(&pe
, 0, ETH_P_EDSA
);
2091 mvpp2_prs_match_etype(&pe
, 2, 0);
2093 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DSA_MASK
,
2094 MVPP2_PRS_RI_DSA_MASK
);
2095 /* Shift ethertype + 2 byte reserved + tag*/
2096 mvpp2_prs_sram_shift_set(&pe
, 2 + MVPP2_ETH_TYPE_LEN
+ shift
,
2097 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2099 /* Update shadow table */
2100 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_DSA
);
2103 /* Set tagged bit in DSA tag */
2104 mvpp2_prs_tcam_data_byte_set(&pe
,
2105 MVPP2_ETH_TYPE_LEN
+ 2 + 3,
2106 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
,
2107 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
);
2108 /* Clear all ai bits for next iteration */
2109 mvpp2_prs_sram_ai_update(&pe
, 0,
2110 MVPP2_PRS_SRAM_AI_MASK
);
2111 /* If packet is tagged continue check vlans */
2112 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
2114 /* Set result info bits to 'no vlans' */
2115 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_NONE
,
2116 MVPP2_PRS_RI_VLAN_MASK
);
2117 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2119 /* Mask/unmask all ports, depending on dsa type */
2120 mvpp2_prs_tcam_port_map_set(&pe
, port_mask
);
2123 /* Update port mask */
2124 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
2126 mvpp2_prs_hw_write(priv
, &pe
);
2129 /* Search for existing single/triple vlan entry */
2130 static struct mvpp2_prs_entry
*mvpp2_prs_vlan_find(struct mvpp2
*priv
,
2131 unsigned short tpid
, int ai
)
2133 struct mvpp2_prs_entry
*pe
;
2136 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2139 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
2141 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
2142 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
2143 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
2144 unsigned int ri_bits
, ai_bits
;
2147 if (!priv
->prs_shadow
[tid
].valid
||
2148 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_VLAN
)
2153 mvpp2_prs_hw_read(priv
, pe
);
2154 match
= mvpp2_prs_tcam_data_cmp(pe
, 0, swab16(tpid
));
2159 ri_bits
= mvpp2_prs_sram_ri_get(pe
);
2160 ri_bits
&= MVPP2_PRS_RI_VLAN_MASK
;
2162 /* Get current ai value from tcam */
2163 ai_bits
= mvpp2_prs_tcam_ai_get(pe
);
2164 /* Clear double vlan bit */
2165 ai_bits
&= ~MVPP2_PRS_DBL_VLAN_AI_BIT
;
2170 if (ri_bits
== MVPP2_PRS_RI_VLAN_SINGLE
||
2171 ri_bits
== MVPP2_PRS_RI_VLAN_TRIPLE
)
2179 /* Add/update single/triple vlan entry */
2180 static int mvpp2_prs_vlan_add(struct mvpp2
*priv
, unsigned short tpid
, int ai
,
2181 unsigned int port_map
)
2183 struct mvpp2_prs_entry
*pe
;
2187 pe
= mvpp2_prs_vlan_find(priv
, tpid
, ai
);
2190 /* Create new tcam entry */
2191 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_LAST_FREE_TID
,
2192 MVPP2_PE_FIRST_FREE_TID
);
2196 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2200 /* Get last double vlan tid */
2201 for (tid_aux
= MVPP2_PE_LAST_FREE_TID
;
2202 tid_aux
>= MVPP2_PE_FIRST_FREE_TID
; tid_aux
--) {
2203 unsigned int ri_bits
;
2205 if (!priv
->prs_shadow
[tid_aux
].valid
||
2206 priv
->prs_shadow
[tid_aux
].lu
!= MVPP2_PRS_LU_VLAN
)
2209 pe
->index
= tid_aux
;
2210 mvpp2_prs_hw_read(priv
, pe
);
2211 ri_bits
= mvpp2_prs_sram_ri_get(pe
);
2212 if ((ri_bits
& MVPP2_PRS_RI_VLAN_MASK
) ==
2213 MVPP2_PRS_RI_VLAN_DOUBLE
)
2217 if (tid
<= tid_aux
) {
2222 memset(pe
, 0, sizeof(*pe
));
2223 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
2226 mvpp2_prs_match_etype(pe
, 0, tpid
);
2228 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_L2
);
2229 /* Shift 4 bytes - skip 1 vlan tag */
2230 mvpp2_prs_sram_shift_set(pe
, MVPP2_VLAN_TAG_LEN
,
2231 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2232 /* Clear all ai bits for next iteration */
2233 mvpp2_prs_sram_ai_update(pe
, 0, MVPP2_PRS_SRAM_AI_MASK
);
2235 if (ai
== MVPP2_PRS_SINGLE_VLAN_AI
) {
2236 mvpp2_prs_sram_ri_update(pe
, MVPP2_PRS_RI_VLAN_SINGLE
,
2237 MVPP2_PRS_RI_VLAN_MASK
);
2239 ai
|= MVPP2_PRS_DBL_VLAN_AI_BIT
;
2240 mvpp2_prs_sram_ri_update(pe
, MVPP2_PRS_RI_VLAN_TRIPLE
,
2241 MVPP2_PRS_RI_VLAN_MASK
);
2243 mvpp2_prs_tcam_ai_update(pe
, ai
, MVPP2_PRS_SRAM_AI_MASK
);
2245 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_VLAN
);
2247 /* Update ports' mask */
2248 mvpp2_prs_tcam_port_map_set(pe
, port_map
);
2250 mvpp2_prs_hw_write(priv
, pe
);
2257 /* Get first free double vlan ai number */
2258 static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2
*priv
)
2262 for (i
= 1; i
< MVPP2_PRS_DBL_VLANS_MAX
; i
++) {
2263 if (!priv
->prs_double_vlans
[i
])
2270 /* Search for existing double vlan entry */
2271 static struct mvpp2_prs_entry
*mvpp2_prs_double_vlan_find(struct mvpp2
*priv
,
2272 unsigned short tpid1
,
2273 unsigned short tpid2
)
2275 struct mvpp2_prs_entry
*pe
;
2278 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2281 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
2283 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
2284 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
2285 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
2286 unsigned int ri_mask
;
2289 if (!priv
->prs_shadow
[tid
].valid
||
2290 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_VLAN
)
2294 mvpp2_prs_hw_read(priv
, pe
);
2296 match
= mvpp2_prs_tcam_data_cmp(pe
, 0, swab16(tpid1
))
2297 && mvpp2_prs_tcam_data_cmp(pe
, 4, swab16(tpid2
));
2302 ri_mask
= mvpp2_prs_sram_ri_get(pe
) & MVPP2_PRS_RI_VLAN_MASK
;
2303 if (ri_mask
== MVPP2_PRS_RI_VLAN_DOUBLE
)
2311 /* Add or update double vlan entry */
2312 static int mvpp2_prs_double_vlan_add(struct mvpp2
*priv
, unsigned short tpid1
,
2313 unsigned short tpid2
,
2314 unsigned int port_map
)
2316 struct mvpp2_prs_entry
*pe
;
2317 int tid_aux
, tid
, ai
, ret
= 0;
2319 pe
= mvpp2_prs_double_vlan_find(priv
, tpid1
, tpid2
);
2322 /* Create new tcam entry */
2323 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2324 MVPP2_PE_LAST_FREE_TID
);
2328 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2332 /* Set ai value for new double vlan entry */
2333 ai
= mvpp2_prs_double_vlan_ai_free_get(priv
);
2339 /* Get first single/triple vlan tid */
2340 for (tid_aux
= MVPP2_PE_FIRST_FREE_TID
;
2341 tid_aux
<= MVPP2_PE_LAST_FREE_TID
; tid_aux
++) {
2342 unsigned int ri_bits
;
2344 if (!priv
->prs_shadow
[tid_aux
].valid
||
2345 priv
->prs_shadow
[tid_aux
].lu
!= MVPP2_PRS_LU_VLAN
)
2348 pe
->index
= tid_aux
;
2349 mvpp2_prs_hw_read(priv
, pe
);
2350 ri_bits
= mvpp2_prs_sram_ri_get(pe
);
2351 ri_bits
&= MVPP2_PRS_RI_VLAN_MASK
;
2352 if (ri_bits
== MVPP2_PRS_RI_VLAN_SINGLE
||
2353 ri_bits
== MVPP2_PRS_RI_VLAN_TRIPLE
)
2357 if (tid
>= tid_aux
) {
2362 memset(pe
, 0, sizeof(*pe
));
2363 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
2366 priv
->prs_double_vlans
[ai
] = true;
2368 mvpp2_prs_match_etype(pe
, 0, tpid1
);
2369 mvpp2_prs_match_etype(pe
, 4, tpid2
);
2371 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
2372 /* Shift 8 bytes - skip 2 vlan tags */
2373 mvpp2_prs_sram_shift_set(pe
, 2 * MVPP2_VLAN_TAG_LEN
,
2374 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2375 mvpp2_prs_sram_ri_update(pe
, MVPP2_PRS_RI_VLAN_DOUBLE
,
2376 MVPP2_PRS_RI_VLAN_MASK
);
2377 mvpp2_prs_sram_ai_update(pe
, ai
| MVPP2_PRS_DBL_VLAN_AI_BIT
,
2378 MVPP2_PRS_SRAM_AI_MASK
);
2380 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_VLAN
);
2383 /* Update ports' mask */
2384 mvpp2_prs_tcam_port_map_set(pe
, port_map
);
2385 mvpp2_prs_hw_write(priv
, pe
);
2391 /* IPv4 header parsing for fragmentation and L4 offset */
2392 static int mvpp2_prs_ip4_proto(struct mvpp2
*priv
, unsigned short proto
,
2393 unsigned int ri
, unsigned int ri_mask
)
2395 struct mvpp2_prs_entry pe
;
2398 if ((proto
!= IPPROTO_TCP
) && (proto
!= IPPROTO_UDP
) &&
2399 (proto
!= IPPROTO_IGMP
))
2402 /* Not fragmented packet */
2403 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2404 MVPP2_PE_LAST_FREE_TID
);
2408 memset(&pe
, 0, sizeof(pe
));
2409 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2412 /* Set next lu to IPv4 */
2413 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2414 mvpp2_prs_sram_shift_set(&pe
, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2416 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
2417 sizeof(struct iphdr
) - 4,
2418 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2419 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
2420 MVPP2_PRS_IPV4_DIP_AI_BIT
);
2421 mvpp2_prs_sram_ri_update(&pe
, ri
, ri_mask
| MVPP2_PRS_RI_IP_FRAG_MASK
);
2423 mvpp2_prs_tcam_data_byte_set(&pe
, 2, 0x00,
2424 MVPP2_PRS_TCAM_PROTO_MASK_L
);
2425 mvpp2_prs_tcam_data_byte_set(&pe
, 3, 0x00,
2426 MVPP2_PRS_TCAM_PROTO_MASK
);
2428 mvpp2_prs_tcam_data_byte_set(&pe
, 5, proto
, MVPP2_PRS_TCAM_PROTO_MASK
);
2429 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV4_DIP_AI_BIT
);
2430 /* Unmask all ports */
2431 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2433 /* Update shadow table and hw entry */
2434 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2435 mvpp2_prs_hw_write(priv
, &pe
);
2437 /* Fragmented packet */
2438 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2439 MVPP2_PE_LAST_FREE_TID
);
2444 /* Clear ri before updating */
2445 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
2446 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
2447 mvpp2_prs_sram_ri_update(&pe
, ri
, ri_mask
);
2449 mvpp2_prs_sram_ri_update(&pe
, ri
| MVPP2_PRS_RI_IP_FRAG_TRUE
,
2450 ri_mask
| MVPP2_PRS_RI_IP_FRAG_MASK
);
2452 mvpp2_prs_tcam_data_byte_set(&pe
, 2, 0x00, 0x0);
2453 mvpp2_prs_tcam_data_byte_set(&pe
, 3, 0x00, 0x0);
2455 /* Update shadow table and hw entry */
2456 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2457 mvpp2_prs_hw_write(priv
, &pe
);
2462 /* IPv4 L3 multicast or broadcast */
2463 static int mvpp2_prs_ip4_cast(struct mvpp2
*priv
, unsigned short l3_cast
)
2465 struct mvpp2_prs_entry pe
;
2468 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2469 MVPP2_PE_LAST_FREE_TID
);
2473 memset(&pe
, 0, sizeof(pe
));
2474 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2478 case MVPP2_PRS_L3_MULTI_CAST
:
2479 mvpp2_prs_tcam_data_byte_set(&pe
, 0, MVPP2_PRS_IPV4_MC
,
2480 MVPP2_PRS_IPV4_MC_MASK
);
2481 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_MCAST
,
2482 MVPP2_PRS_RI_L3_ADDR_MASK
);
2484 case MVPP2_PRS_L3_BROAD_CAST
:
2485 mask
= MVPP2_PRS_IPV4_BC_MASK
;
2486 mvpp2_prs_tcam_data_byte_set(&pe
, 0, mask
, mask
);
2487 mvpp2_prs_tcam_data_byte_set(&pe
, 1, mask
, mask
);
2488 mvpp2_prs_tcam_data_byte_set(&pe
, 2, mask
, mask
);
2489 mvpp2_prs_tcam_data_byte_set(&pe
, 3, mask
, mask
);
2490 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_BCAST
,
2491 MVPP2_PRS_RI_L3_ADDR_MASK
);
2497 /* Finished: go to flowid generation */
2498 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2499 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2501 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
2502 MVPP2_PRS_IPV4_DIP_AI_BIT
);
2503 /* Unmask all ports */
2504 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2506 /* Update shadow table and hw entry */
2507 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2508 mvpp2_prs_hw_write(priv
, &pe
);
2513 /* Set entries for protocols over IPv6 */
2514 static int mvpp2_prs_ip6_proto(struct mvpp2
*priv
, unsigned short proto
,
2515 unsigned int ri
, unsigned int ri_mask
)
2517 struct mvpp2_prs_entry pe
;
2520 if ((proto
!= IPPROTO_TCP
) && (proto
!= IPPROTO_UDP
) &&
2521 (proto
!= IPPROTO_ICMPV6
) && (proto
!= IPPROTO_IPIP
))
2524 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2525 MVPP2_PE_LAST_FREE_TID
);
2529 memset(&pe
, 0, sizeof(pe
));
2530 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2533 /* Finished: go to flowid generation */
2534 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2535 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2536 mvpp2_prs_sram_ri_update(&pe
, ri
, ri_mask
);
2537 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
2538 sizeof(struct ipv6hdr
) - 6,
2539 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2541 mvpp2_prs_tcam_data_byte_set(&pe
, 0, proto
, MVPP2_PRS_TCAM_PROTO_MASK
);
2542 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2543 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2544 /* Unmask all ports */
2545 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2548 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP6
);
2549 mvpp2_prs_hw_write(priv
, &pe
);
2554 /* IPv6 L3 multicast entry */
2555 static int mvpp2_prs_ip6_cast(struct mvpp2
*priv
, unsigned short l3_cast
)
2557 struct mvpp2_prs_entry pe
;
2560 if (l3_cast
!= MVPP2_PRS_L3_MULTI_CAST
)
2563 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2564 MVPP2_PE_LAST_FREE_TID
);
2568 memset(&pe
, 0, sizeof(pe
));
2569 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2572 /* Finished: go to flowid generation */
2573 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2574 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_MCAST
,
2575 MVPP2_PRS_RI_L3_ADDR_MASK
);
2576 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2577 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2578 /* Shift back to IPv6 NH */
2579 mvpp2_prs_sram_shift_set(&pe
, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2581 mvpp2_prs_tcam_data_byte_set(&pe
, 0, MVPP2_PRS_IPV6_MC
,
2582 MVPP2_PRS_IPV6_MC_MASK
);
2583 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2584 /* Unmask all ports */
2585 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2587 /* Update shadow table and hw entry */
2588 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP6
);
2589 mvpp2_prs_hw_write(priv
, &pe
);
2594 /* Parser per-port initialization */
2595 static void mvpp2_prs_hw_port_init(struct mvpp2
*priv
, int port
, int lu_first
,
2596 int lu_max
, int offset
)
2601 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_LOOKUP_REG
);
2602 val
&= ~MVPP2_PRS_PORT_LU_MASK(port
);
2603 val
|= MVPP2_PRS_PORT_LU_VAL(port
, lu_first
);
2604 mvpp2_write(priv
, MVPP2_PRS_INIT_LOOKUP_REG
, val
);
2606 /* Set maximum number of loops for packet received from port */
2607 val
= mvpp2_read(priv
, MVPP2_PRS_MAX_LOOP_REG(port
));
2608 val
&= ~MVPP2_PRS_MAX_LOOP_MASK(port
);
2609 val
|= MVPP2_PRS_MAX_LOOP_VAL(port
, lu_max
);
2610 mvpp2_write(priv
, MVPP2_PRS_MAX_LOOP_REG(port
), val
);
2612 /* Set initial offset for packet header extraction for the first
2615 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_OFFS_REG(port
));
2616 val
&= ~MVPP2_PRS_INIT_OFF_MASK(port
);
2617 val
|= MVPP2_PRS_INIT_OFF_VAL(port
, offset
);
2618 mvpp2_write(priv
, MVPP2_PRS_INIT_OFFS_REG(port
), val
);
2621 /* Default flow entries initialization for all ports */
2622 static void mvpp2_prs_def_flow_init(struct mvpp2
*priv
)
2624 struct mvpp2_prs_entry pe
;
2627 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
2628 memset(&pe
, 0, sizeof(pe
));
2629 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2630 pe
.index
= MVPP2_PE_FIRST_DEFAULT_FLOW
- port
;
2632 /* Mask all ports */
2633 mvpp2_prs_tcam_port_map_set(&pe
, 0);
2636 mvpp2_prs_sram_ai_update(&pe
, port
, MVPP2_PRS_FLOW_ID_MASK
);
2637 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
2639 /* Update shadow table and hw entry */
2640 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_FLOWS
);
2641 mvpp2_prs_hw_write(priv
, &pe
);
2645 /* Set default entry for Marvell Header field */
2646 static void mvpp2_prs_mh_init(struct mvpp2
*priv
)
2648 struct mvpp2_prs_entry pe
;
2650 memset(&pe
, 0, sizeof(pe
));
2652 pe
.index
= MVPP2_PE_MH_DEFAULT
;
2653 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MH
);
2654 mvpp2_prs_sram_shift_set(&pe
, MVPP2_MH_SIZE
,
2655 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2656 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
2658 /* Unmask all ports */
2659 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2661 /* Update shadow table and hw entry */
2662 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MH
);
2663 mvpp2_prs_hw_write(priv
, &pe
);
2666 /* Set default entires (place holder) for promiscuous, non-promiscuous and
2667 * multicast MAC addresses
2669 static void mvpp2_prs_mac_init(struct mvpp2
*priv
)
2671 struct mvpp2_prs_entry pe
;
2673 memset(&pe
, 0, sizeof(pe
));
2675 /* Non-promiscuous mode for all ports - DROP unknown packets */
2676 pe
.index
= MVPP2_PE_MAC_NON_PROMISCUOUS
;
2677 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
2679 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
2680 MVPP2_PRS_RI_DROP_MASK
);
2681 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2682 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2684 /* Unmask all ports */
2685 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2687 /* Update shadow table and hw entry */
2688 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
2689 mvpp2_prs_hw_write(priv
, &pe
);
2691 /* place holders only - no ports */
2692 mvpp2_prs_mac_drop_all_set(priv
, 0, false);
2693 mvpp2_prs_mac_promisc_set(priv
, 0, false);
2694 mvpp2_prs_mac_multi_set(priv
, 0, MVPP2_PE_MAC_MC_ALL
, false);
2695 mvpp2_prs_mac_multi_set(priv
, 0, MVPP2_PE_MAC_MC_IP6
, false);
2698 /* Set default entries for various types of dsa packets */
2699 static void mvpp2_prs_dsa_init(struct mvpp2
*priv
)
2701 struct mvpp2_prs_entry pe
;
2703 /* None tagged EDSA entry - place holder */
2704 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_UNTAGGED
,
2707 /* Tagged EDSA entry - place holder */
2708 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
2710 /* None tagged DSA entry - place holder */
2711 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_UNTAGGED
,
2714 /* Tagged DSA entry - place holder */
2715 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
2717 /* None tagged EDSA ethertype entry - place holder*/
2718 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, false,
2719 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
2721 /* Tagged EDSA ethertype entry - place holder*/
2722 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, false,
2723 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
2725 /* None tagged DSA ethertype entry */
2726 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, true,
2727 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
2729 /* Tagged DSA ethertype entry */
2730 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, true,
2731 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
2733 /* Set default entry, in case DSA or EDSA tag not found */
2734 memset(&pe
, 0, sizeof(pe
));
2735 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
2736 pe
.index
= MVPP2_PE_DSA_DEFAULT
;
2737 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
2740 mvpp2_prs_sram_shift_set(&pe
, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2741 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
2743 /* Clear all sram ai bits for next iteration */
2744 mvpp2_prs_sram_ai_update(&pe
, 0, MVPP2_PRS_SRAM_AI_MASK
);
2746 /* Unmask all ports */
2747 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2749 mvpp2_prs_hw_write(priv
, &pe
);
2752 /* Match basic ethertypes */
2753 static int mvpp2_prs_etype_init(struct mvpp2
*priv
)
2755 struct mvpp2_prs_entry pe
;
2758 /* Ethertype: PPPoE */
2759 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2760 MVPP2_PE_LAST_FREE_TID
);
2764 memset(&pe
, 0, sizeof(pe
));
2765 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2768 mvpp2_prs_match_etype(&pe
, 0, ETH_P_PPP_SES
);
2770 mvpp2_prs_sram_shift_set(&pe
, MVPP2_PPPOE_HDR_SIZE
,
2771 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2772 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
2773 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_PPPOE_MASK
,
2774 MVPP2_PRS_RI_PPPOE_MASK
);
2776 /* Update shadow table and hw entry */
2777 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2778 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2779 priv
->prs_shadow
[pe
.index
].finish
= false;
2780 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_PPPOE_MASK
,
2781 MVPP2_PRS_RI_PPPOE_MASK
);
2782 mvpp2_prs_hw_write(priv
, &pe
);
2784 /* Ethertype: ARP */
2785 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2786 MVPP2_PE_LAST_FREE_TID
);
2790 memset(&pe
, 0, sizeof(pe
));
2791 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2794 mvpp2_prs_match_etype(&pe
, 0, ETH_P_ARP
);
2796 /* Generate flow in the next iteration*/
2797 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2798 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2799 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_ARP
,
2800 MVPP2_PRS_RI_L3_PROTO_MASK
);
2802 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2804 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2806 /* Update shadow table and hw entry */
2807 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2808 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2809 priv
->prs_shadow
[pe
.index
].finish
= true;
2810 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_ARP
,
2811 MVPP2_PRS_RI_L3_PROTO_MASK
);
2812 mvpp2_prs_hw_write(priv
, &pe
);
2814 /* Ethertype: LBTD */
2815 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2816 MVPP2_PE_LAST_FREE_TID
);
2820 memset(&pe
, 0, sizeof(pe
));
2821 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2824 mvpp2_prs_match_etype(&pe
, 0, MVPP2_IP_LBDT_TYPE
);
2826 /* Generate flow in the next iteration*/
2827 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2828 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2829 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
2830 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
2831 MVPP2_PRS_RI_CPU_CODE_MASK
|
2832 MVPP2_PRS_RI_UDF3_MASK
);
2834 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2836 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2838 /* Update shadow table and hw entry */
2839 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2840 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2841 priv
->prs_shadow
[pe
.index
].finish
= true;
2842 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
2843 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
2844 MVPP2_PRS_RI_CPU_CODE_MASK
|
2845 MVPP2_PRS_RI_UDF3_MASK
);
2846 mvpp2_prs_hw_write(priv
, &pe
);
2848 /* Ethertype: IPv4 without options */
2849 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2850 MVPP2_PE_LAST_FREE_TID
);
2854 memset(&pe
, 0, sizeof(pe
));
2855 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2858 mvpp2_prs_match_etype(&pe
, 0, ETH_P_IP
);
2859 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
2860 MVPP2_PRS_IPV4_HEAD
| MVPP2_PRS_IPV4_IHL
,
2861 MVPP2_PRS_IPV4_HEAD_MASK
|
2862 MVPP2_PRS_IPV4_IHL_MASK
);
2864 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2865 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4
,
2866 MVPP2_PRS_RI_L3_PROTO_MASK
);
2867 /* Skip eth_type + 4 bytes of IP header */
2868 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
2869 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2871 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2873 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2875 /* Update shadow table and hw entry */
2876 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2877 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2878 priv
->prs_shadow
[pe
.index
].finish
= false;
2879 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4
,
2880 MVPP2_PRS_RI_L3_PROTO_MASK
);
2881 mvpp2_prs_hw_write(priv
, &pe
);
2883 /* Ethertype: IPv4 with options */
2884 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2885 MVPP2_PE_LAST_FREE_TID
);
2891 /* Clear tcam data before updating */
2892 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN
)] = 0x0;
2893 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN
)] = 0x0;
2895 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
2896 MVPP2_PRS_IPV4_HEAD
,
2897 MVPP2_PRS_IPV4_HEAD_MASK
);
2899 /* Clear ri before updating */
2900 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
2901 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
2902 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4_OPT
,
2903 MVPP2_PRS_RI_L3_PROTO_MASK
);
2905 /* Update shadow table and hw entry */
2906 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2907 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2908 priv
->prs_shadow
[pe
.index
].finish
= false;
2909 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4_OPT
,
2910 MVPP2_PRS_RI_L3_PROTO_MASK
);
2911 mvpp2_prs_hw_write(priv
, &pe
);
2913 /* Ethertype: IPv6 without options */
2914 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2915 MVPP2_PE_LAST_FREE_TID
);
2919 memset(&pe
, 0, sizeof(pe
));
2920 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2923 mvpp2_prs_match_etype(&pe
, 0, ETH_P_IPV6
);
2925 /* Skip DIP of IPV6 header */
2926 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 8 +
2927 MVPP2_MAX_L3_ADDR_SIZE
,
2928 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2929 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2930 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP6
,
2931 MVPP2_PRS_RI_L3_PROTO_MASK
);
2933 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2935 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2937 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2938 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2939 priv
->prs_shadow
[pe
.index
].finish
= false;
2940 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP6
,
2941 MVPP2_PRS_RI_L3_PROTO_MASK
);
2942 mvpp2_prs_hw_write(priv
, &pe
);
2944 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2945 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2946 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2947 pe
.index
= MVPP2_PE_ETH_TYPE_UN
;
2949 /* Unmask all ports */
2950 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2952 /* Generate flow in the next iteration*/
2953 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2954 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2955 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
,
2956 MVPP2_PRS_RI_L3_PROTO_MASK
);
2957 /* Set L3 offset even it's unknown L3 */
2958 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2960 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2962 /* Update shadow table and hw entry */
2963 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2964 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2965 priv
->prs_shadow
[pe
.index
].finish
= true;
2966 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_UN
,
2967 MVPP2_PRS_RI_L3_PROTO_MASK
);
2968 mvpp2_prs_hw_write(priv
, &pe
);
2973 /* Configure vlan entries and detect up to 2 successive VLAN tags.
2980 static int mvpp2_prs_vlan_init(struct platform_device
*pdev
, struct mvpp2
*priv
)
2982 struct mvpp2_prs_entry pe
;
2985 priv
->prs_double_vlans
= devm_kcalloc(&pdev
->dev
, sizeof(bool),
2986 MVPP2_PRS_DBL_VLANS_MAX
,
2988 if (!priv
->prs_double_vlans
)
2991 /* Double VLAN: 0x8100, 0x88A8 */
2992 err
= mvpp2_prs_double_vlan_add(priv
, ETH_P_8021Q
, ETH_P_8021AD
,
2993 MVPP2_PRS_PORT_MASK
);
2997 /* Double VLAN: 0x8100, 0x8100 */
2998 err
= mvpp2_prs_double_vlan_add(priv
, ETH_P_8021Q
, ETH_P_8021Q
,
2999 MVPP2_PRS_PORT_MASK
);
3003 /* Single VLAN: 0x88a8 */
3004 err
= mvpp2_prs_vlan_add(priv
, ETH_P_8021AD
, MVPP2_PRS_SINGLE_VLAN_AI
,
3005 MVPP2_PRS_PORT_MASK
);
3009 /* Single VLAN: 0x8100 */
3010 err
= mvpp2_prs_vlan_add(priv
, ETH_P_8021Q
, MVPP2_PRS_SINGLE_VLAN_AI
,
3011 MVPP2_PRS_PORT_MASK
);
3015 /* Set default double vlan entry */
3016 memset(&pe
, 0, sizeof(pe
));
3017 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
3018 pe
.index
= MVPP2_PE_VLAN_DBL
;
3020 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
3021 /* Clear ai for next iterations */
3022 mvpp2_prs_sram_ai_update(&pe
, 0, MVPP2_PRS_SRAM_AI_MASK
);
3023 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_DOUBLE
,
3024 MVPP2_PRS_RI_VLAN_MASK
);
3026 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_DBL_VLAN_AI_BIT
,
3027 MVPP2_PRS_DBL_VLAN_AI_BIT
);
3028 /* Unmask all ports */
3029 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3031 /* Update shadow table and hw entry */
3032 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_VLAN
);
3033 mvpp2_prs_hw_write(priv
, &pe
);
3035 /* Set default vlan none entry */
3036 memset(&pe
, 0, sizeof(pe
));
3037 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
3038 pe
.index
= MVPP2_PE_VLAN_NONE
;
3040 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
3041 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_NONE
,
3042 MVPP2_PRS_RI_VLAN_MASK
);
3044 /* Unmask all ports */
3045 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3047 /* Update shadow table and hw entry */
3048 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_VLAN
);
3049 mvpp2_prs_hw_write(priv
, &pe
);
3054 /* Set entries for PPPoE ethertype */
3055 static int mvpp2_prs_pppoe_init(struct mvpp2
*priv
)
3057 struct mvpp2_prs_entry pe
;
3060 /* IPv4 over PPPoE with options */
3061 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3062 MVPP2_PE_LAST_FREE_TID
);
3066 memset(&pe
, 0, sizeof(pe
));
3067 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
3070 mvpp2_prs_match_etype(&pe
, 0, PPP_IP
);
3072 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
3073 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4_OPT
,
3074 MVPP2_PRS_RI_L3_PROTO_MASK
);
3075 /* Skip eth_type + 4 bytes of IP header */
3076 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
3077 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
3079 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
3081 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
3083 /* Update shadow table and hw entry */
3084 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
3085 mvpp2_prs_hw_write(priv
, &pe
);
3087 /* IPv4 over PPPoE without options */
3088 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3089 MVPP2_PE_LAST_FREE_TID
);
3095 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
3096 MVPP2_PRS_IPV4_HEAD
| MVPP2_PRS_IPV4_IHL
,
3097 MVPP2_PRS_IPV4_HEAD_MASK
|
3098 MVPP2_PRS_IPV4_IHL_MASK
);
3100 /* Clear ri before updating */
3101 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
3102 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
3103 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4
,
3104 MVPP2_PRS_RI_L3_PROTO_MASK
);
3106 /* Update shadow table and hw entry */
3107 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
3108 mvpp2_prs_hw_write(priv
, &pe
);
3110 /* IPv6 over PPPoE */
3111 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3112 MVPP2_PE_LAST_FREE_TID
);
3116 memset(&pe
, 0, sizeof(pe
));
3117 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
3120 mvpp2_prs_match_etype(&pe
, 0, PPP_IPV6
);
3122 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
3123 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP6
,
3124 MVPP2_PRS_RI_L3_PROTO_MASK
);
3125 /* Skip eth_type + 4 bytes of IPv6 header */
3126 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
3127 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
3129 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
3131 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
3133 /* Update shadow table and hw entry */
3134 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
3135 mvpp2_prs_hw_write(priv
, &pe
);
3137 /* Non-IP over PPPoE */
3138 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3139 MVPP2_PE_LAST_FREE_TID
);
3143 memset(&pe
, 0, sizeof(pe
));
3144 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
3147 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
,
3148 MVPP2_PRS_RI_L3_PROTO_MASK
);
3150 /* Finished: go to flowid generation */
3151 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
3152 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
3153 /* Set L3 offset even if it's unknown L3 */
3154 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
3156 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
3158 /* Update shadow table and hw entry */
3159 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
3160 mvpp2_prs_hw_write(priv
, &pe
);
3165 /* Initialize entries for IPv4 */
3166 static int mvpp2_prs_ip4_init(struct mvpp2
*priv
)
3168 struct mvpp2_prs_entry pe
;
3171 /* Set entries for TCP, UDP and IGMP over IPv4 */
3172 err
= mvpp2_prs_ip4_proto(priv
, IPPROTO_TCP
, MVPP2_PRS_RI_L4_TCP
,
3173 MVPP2_PRS_RI_L4_PROTO_MASK
);
3177 err
= mvpp2_prs_ip4_proto(priv
, IPPROTO_UDP
, MVPP2_PRS_RI_L4_UDP
,
3178 MVPP2_PRS_RI_L4_PROTO_MASK
);
3182 err
= mvpp2_prs_ip4_proto(priv
, IPPROTO_IGMP
,
3183 MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
3184 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
3185 MVPP2_PRS_RI_CPU_CODE_MASK
|
3186 MVPP2_PRS_RI_UDF3_MASK
);
3190 /* IPv4 Broadcast */
3191 err
= mvpp2_prs_ip4_cast(priv
, MVPP2_PRS_L3_BROAD_CAST
);
3195 /* IPv4 Multicast */
3196 err
= mvpp2_prs_ip4_cast(priv
, MVPP2_PRS_L3_MULTI_CAST
);
3200 /* Default IPv4 entry for unknown protocols */
3201 memset(&pe
, 0, sizeof(pe
));
3202 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
3203 pe
.index
= MVPP2_PE_IP4_PROTO_UN
;
3205 /* Set next lu to IPv4 */
3206 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
3207 mvpp2_prs_sram_shift_set(&pe
, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
3209 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
3210 sizeof(struct iphdr
) - 4,
3211 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
3212 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
3213 MVPP2_PRS_IPV4_DIP_AI_BIT
);
3214 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L4_OTHER
,
3215 MVPP2_PRS_RI_L4_PROTO_MASK
);
3217 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV4_DIP_AI_BIT
);
3218 /* Unmask all ports */
3219 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3221 /* Update shadow table and hw entry */
3222 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
3223 mvpp2_prs_hw_write(priv
, &pe
);
3225 /* Default IPv4 entry for unicast address */
3226 memset(&pe
, 0, sizeof(pe
));
3227 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
3228 pe
.index
= MVPP2_PE_IP4_ADDR_UN
;
3230 /* Finished: go to flowid generation */
3231 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
3232 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
3233 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UCAST
,
3234 MVPP2_PRS_RI_L3_ADDR_MASK
);
3236 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
3237 MVPP2_PRS_IPV4_DIP_AI_BIT
);
3238 /* Unmask all ports */
3239 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3241 /* Update shadow table and hw entry */
3242 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
3243 mvpp2_prs_hw_write(priv
, &pe
);
3248 /* Initialize entries for IPv6 */
3249 static int mvpp2_prs_ip6_init(struct mvpp2
*priv
)
3251 struct mvpp2_prs_entry pe
;
3254 /* Set entries for TCP, UDP and ICMP over IPv6 */
3255 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_TCP
,
3256 MVPP2_PRS_RI_L4_TCP
,
3257 MVPP2_PRS_RI_L4_PROTO_MASK
);
3261 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_UDP
,
3262 MVPP2_PRS_RI_L4_UDP
,
3263 MVPP2_PRS_RI_L4_PROTO_MASK
);
3267 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_ICMPV6
,
3268 MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
3269 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
3270 MVPP2_PRS_RI_CPU_CODE_MASK
|
3271 MVPP2_PRS_RI_UDF3_MASK
);
3275 /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */
3276 /* Result Info: UDF7=1, DS lite */
3277 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_IPIP
,
3278 MVPP2_PRS_RI_UDF7_IP6_LITE
,
3279 MVPP2_PRS_RI_UDF7_MASK
);
3283 /* IPv6 multicast */
3284 err
= mvpp2_prs_ip6_cast(priv
, MVPP2_PRS_L3_MULTI_CAST
);
3288 /* Entry for checking hop limit */
3289 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3290 MVPP2_PE_LAST_FREE_TID
);
3294 memset(&pe
, 0, sizeof(pe
));
3295 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
3298 /* Finished: go to flowid generation */
3299 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
3300 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
3301 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
|
3302 MVPP2_PRS_RI_DROP_MASK
,
3303 MVPP2_PRS_RI_L3_PROTO_MASK
|
3304 MVPP2_PRS_RI_DROP_MASK
);
3306 mvpp2_prs_tcam_data_byte_set(&pe
, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK
);
3307 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
3308 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
3310 /* Update shadow table and hw entry */
3311 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
3312 mvpp2_prs_hw_write(priv
, &pe
);
3314 /* Default IPv6 entry for unknown protocols */
3315 memset(&pe
, 0, sizeof(pe
));
3316 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
3317 pe
.index
= MVPP2_PE_IP6_PROTO_UN
;
3319 /* Finished: go to flowid generation */
3320 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
3321 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
3322 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L4_OTHER
,
3323 MVPP2_PRS_RI_L4_PROTO_MASK
);
3324 /* Set L4 offset relatively to our current place */
3325 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
3326 sizeof(struct ipv6hdr
) - 4,
3327 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
3329 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
3330 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
3331 /* Unmask all ports */
3332 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3334 /* Update shadow table and hw entry */
3335 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
3336 mvpp2_prs_hw_write(priv
, &pe
);
3338 /* Default IPv6 entry for unknown ext protocols */
3339 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
3340 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
3341 pe
.index
= MVPP2_PE_IP6_EXT_PROTO_UN
;
3343 /* Finished: go to flowid generation */
3344 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
3345 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
3346 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L4_OTHER
,
3347 MVPP2_PRS_RI_L4_PROTO_MASK
);
3349 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_EXT_AI_BIT
,
3350 MVPP2_PRS_IPV6_EXT_AI_BIT
);
3351 /* Unmask all ports */
3352 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3354 /* Update shadow table and hw entry */
3355 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
3356 mvpp2_prs_hw_write(priv
, &pe
);
3358 /* Default IPv6 entry for unicast address */
3359 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
3360 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
3361 pe
.index
= MVPP2_PE_IP6_ADDR_UN
;
3363 /* Finished: go to IPv6 again */
3364 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
3365 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UCAST
,
3366 MVPP2_PRS_RI_L3_ADDR_MASK
);
3367 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
3368 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
3369 /* Shift back to IPV6 NH */
3370 mvpp2_prs_sram_shift_set(&pe
, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
3372 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
3373 /* Unmask all ports */
3374 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
3376 /* Update shadow table and hw entry */
3377 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP6
);
3378 mvpp2_prs_hw_write(priv
, &pe
);
3383 /* Parser default initialization */
3384 static int mvpp2_prs_default_init(struct platform_device
*pdev
,
3389 /* Enable tcam table */
3390 mvpp2_write(priv
, MVPP2_PRS_TCAM_CTRL_REG
, MVPP2_PRS_TCAM_EN_MASK
);
3392 /* Clear all tcam and sram entries */
3393 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++) {
3394 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
3395 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
3396 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), 0);
3398 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, index
);
3399 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
3400 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), 0);
3403 /* Invalidate all tcam entries */
3404 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++)
3405 mvpp2_prs_hw_inv(priv
, index
);
3407 priv
->prs_shadow
= devm_kcalloc(&pdev
->dev
, MVPP2_PRS_TCAM_SRAM_SIZE
,
3408 sizeof(*priv
->prs_shadow
),
3410 if (!priv
->prs_shadow
)
3413 /* Always start from lookup = 0 */
3414 for (index
= 0; index
< MVPP2_MAX_PORTS
; index
++)
3415 mvpp2_prs_hw_port_init(priv
, index
, MVPP2_PRS_LU_MH
,
3416 MVPP2_PRS_PORT_LU_MAX
, 0);
3418 mvpp2_prs_def_flow_init(priv
);
3420 mvpp2_prs_mh_init(priv
);
3422 mvpp2_prs_mac_init(priv
);
3424 mvpp2_prs_dsa_init(priv
);
3426 err
= mvpp2_prs_etype_init(priv
);
3430 err
= mvpp2_prs_vlan_init(pdev
, priv
);
3434 err
= mvpp2_prs_pppoe_init(priv
);
3438 err
= mvpp2_prs_ip6_init(priv
);
3442 err
= mvpp2_prs_ip4_init(priv
);
3449 /* Compare MAC DA with tcam entry data */
3450 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry
*pe
,
3451 const u8
*da
, unsigned char *mask
)
3453 unsigned char tcam_byte
, tcam_mask
;
3456 for (index
= 0; index
< ETH_ALEN
; index
++) {
3457 mvpp2_prs_tcam_data_byte_get(pe
, index
, &tcam_byte
, &tcam_mask
);
3458 if (tcam_mask
!= mask
[index
])
3461 if ((tcam_mask
& tcam_byte
) != (da
[index
] & mask
[index
]))
3468 /* Find tcam entry with matched pair <MAC DA, port> */
3469 static struct mvpp2_prs_entry
*
3470 mvpp2_prs_mac_da_range_find(struct mvpp2
*priv
, int pmap
, const u8
*da
,
3471 unsigned char *mask
, int udf_type
)
3473 struct mvpp2_prs_entry
*pe
;
3476 pe
= kzalloc(sizeof(*pe
), GFP_ATOMIC
);
3479 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
3481 /* Go through the all entires with MVPP2_PRS_LU_MAC */
3482 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
3483 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
3484 unsigned int entry_pmap
;
3486 if (!priv
->prs_shadow
[tid
].valid
||
3487 (priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_MAC
) ||
3488 (priv
->prs_shadow
[tid
].udf
!= udf_type
))
3492 mvpp2_prs_hw_read(priv
, pe
);
3493 entry_pmap
= mvpp2_prs_tcam_port_map_get(pe
);
3495 if (mvpp2_prs_mac_range_equals(pe
, da
, mask
) &&
3504 /* Update parser's mac da entry */
3505 static int mvpp2_prs_mac_da_accept(struct mvpp2
*priv
, int port
,
3506 const u8
*da
, bool add
)
3508 struct mvpp2_prs_entry
*pe
;
3509 unsigned int pmap
, len
, ri
;
3510 unsigned char mask
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3513 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
3514 pe
= mvpp2_prs_mac_da_range_find(priv
, (1 << port
), da
, mask
,
3515 MVPP2_PRS_UDF_MAC_DEF
);
3522 /* Create new TCAM entry */
3523 /* Find first range mac entry*/
3524 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
3525 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++)
3526 if (priv
->prs_shadow
[tid
].valid
&&
3527 (priv
->prs_shadow
[tid
].lu
== MVPP2_PRS_LU_MAC
) &&
3528 (priv
->prs_shadow
[tid
].udf
==
3529 MVPP2_PRS_UDF_MAC_RANGE
))
3532 /* Go through the all entries from first to last */
3533 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3538 pe
= kzalloc(sizeof(*pe
), GFP_ATOMIC
);
3541 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
3544 /* Mask all ports */
3545 mvpp2_prs_tcam_port_map_set(pe
, 0);
3548 /* Update port mask */
3549 mvpp2_prs_tcam_port_set(pe
, port
, add
);
3551 /* Invalidate the entry if no ports are left enabled */
3552 pmap
= mvpp2_prs_tcam_port_map_get(pe
);
3558 mvpp2_prs_hw_inv(priv
, pe
->index
);
3559 priv
->prs_shadow
[pe
->index
].valid
= false;
3564 /* Continue - set next lookup */
3565 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_DSA
);
3567 /* Set match on DA */
3570 mvpp2_prs_tcam_data_byte_set(pe
, len
, da
[len
], 0xff);
3572 /* Set result info bits */
3573 if (is_broadcast_ether_addr(da
))
3574 ri
= MVPP2_PRS_RI_L2_BCAST
;
3575 else if (is_multicast_ether_addr(da
))
3576 ri
= MVPP2_PRS_RI_L2_MCAST
;
3578 ri
= MVPP2_PRS_RI_L2_UCAST
| MVPP2_PRS_RI_MAC_ME_MASK
;
3580 mvpp2_prs_sram_ri_update(pe
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
3581 MVPP2_PRS_RI_MAC_ME_MASK
);
3582 mvpp2_prs_shadow_ri_set(priv
, pe
->index
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
3583 MVPP2_PRS_RI_MAC_ME_MASK
);
3585 /* Shift to ethertype */
3586 mvpp2_prs_sram_shift_set(pe
, 2 * ETH_ALEN
,
3587 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
3589 /* Update shadow table and hw entry */
3590 priv
->prs_shadow
[pe
->index
].udf
= MVPP2_PRS_UDF_MAC_DEF
;
3591 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_MAC
);
3592 mvpp2_prs_hw_write(priv
, pe
);
3599 static int mvpp2_prs_update_mac_da(struct net_device
*dev
, const u8
*da
)
3601 struct mvpp2_port
*port
= netdev_priv(dev
);
3604 /* Remove old parser entry */
3605 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, dev
->dev_addr
,
3610 /* Add new parser entry */
3611 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, da
, true);
3615 /* Set addr in the device */
3616 ether_addr_copy(dev
->dev_addr
, da
);
3621 /* Delete all port's multicast simple (not range) entries */
3622 static void mvpp2_prs_mcast_del_all(struct mvpp2
*priv
, int port
)
3624 struct mvpp2_prs_entry pe
;
3627 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
3628 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
3629 unsigned char da
[ETH_ALEN
], da_mask
[ETH_ALEN
];
3631 if (!priv
->prs_shadow
[tid
].valid
||
3632 (priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_MAC
) ||
3633 (priv
->prs_shadow
[tid
].udf
!= MVPP2_PRS_UDF_MAC_DEF
))
3636 /* Only simple mac entries */
3638 mvpp2_prs_hw_read(priv
, &pe
);
3640 /* Read mac addr from entry */
3641 for (index
= 0; index
< ETH_ALEN
; index
++)
3642 mvpp2_prs_tcam_data_byte_get(&pe
, index
, &da
[index
],
3645 if (is_multicast_ether_addr(da
) && !is_broadcast_ether_addr(da
))
3646 /* Delete this entry */
3647 mvpp2_prs_mac_da_accept(priv
, port
, da
, false);
3651 static int mvpp2_prs_tag_mode_set(struct mvpp2
*priv
, int port
, int type
)
3654 case MVPP2_TAG_TYPE_EDSA
:
3655 /* Add port to EDSA entries */
3656 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3657 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
3658 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3659 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
3660 /* Remove port from DSA entries */
3661 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3662 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
3663 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3664 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
3667 case MVPP2_TAG_TYPE_DSA
:
3668 /* Add port to DSA entries */
3669 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3670 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
3671 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3672 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
3673 /* Remove port from EDSA entries */
3674 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3675 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
3676 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3677 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
3680 case MVPP2_TAG_TYPE_MH
:
3681 case MVPP2_TAG_TYPE_NONE
:
3682 /* Remove port form EDSA and DSA entries */
3683 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3684 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
3685 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3686 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
3687 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3688 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
3689 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3690 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
3694 if ((type
< 0) || (type
> MVPP2_TAG_TYPE_EDSA
))
3701 /* Set prs flow for the port */
3702 static int mvpp2_prs_def_flow(struct mvpp2_port
*port
)
3704 struct mvpp2_prs_entry
*pe
;
3707 pe
= mvpp2_prs_flow_find(port
->priv
, port
->id
);
3709 /* Such entry not exist */
3711 /* Go through the all entires from last to first */
3712 tid
= mvpp2_prs_tcam_first_free(port
->priv
,
3713 MVPP2_PE_LAST_FREE_TID
,
3714 MVPP2_PE_FIRST_FREE_TID
);
3718 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
3722 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
3726 mvpp2_prs_sram_ai_update(pe
, port
->id
, MVPP2_PRS_FLOW_ID_MASK
);
3727 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
3729 /* Update shadow table */
3730 mvpp2_prs_shadow_set(port
->priv
, pe
->index
, MVPP2_PRS_LU_FLOWS
);
3733 mvpp2_prs_tcam_port_map_set(pe
, (1 << port
->id
));
3734 mvpp2_prs_hw_write(port
->priv
, pe
);
3740 /* Classifier configuration routines */
3742 /* Update classification flow table registers */
3743 static void mvpp2_cls_flow_write(struct mvpp2
*priv
,
3744 struct mvpp2_cls_flow_entry
*fe
)
3746 mvpp2_write(priv
, MVPP2_CLS_FLOW_INDEX_REG
, fe
->index
);
3747 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL0_REG
, fe
->data
[0]);
3748 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL1_REG
, fe
->data
[1]);
3749 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL2_REG
, fe
->data
[2]);
3752 /* Update classification lookup table register */
3753 static void mvpp2_cls_lookup_write(struct mvpp2
*priv
,
3754 struct mvpp2_cls_lookup_entry
*le
)
3758 val
= (le
->way
<< MVPP2_CLS_LKP_INDEX_WAY_OFFS
) | le
->lkpid
;
3759 mvpp2_write(priv
, MVPP2_CLS_LKP_INDEX_REG
, val
);
3760 mvpp2_write(priv
, MVPP2_CLS_LKP_TBL_REG
, le
->data
);
3763 /* Classifier default initialization */
3764 static void mvpp2_cls_init(struct mvpp2
*priv
)
3766 struct mvpp2_cls_lookup_entry le
;
3767 struct mvpp2_cls_flow_entry fe
;
3770 /* Enable classifier */
3771 mvpp2_write(priv
, MVPP2_CLS_MODE_REG
, MVPP2_CLS_MODE_ACTIVE_MASK
);
3773 /* Clear classifier flow table */
3774 memset(&fe
.data
, 0, sizeof(fe
.data
));
3775 for (index
= 0; index
< MVPP2_CLS_FLOWS_TBL_SIZE
; index
++) {
3777 mvpp2_cls_flow_write(priv
, &fe
);
3780 /* Clear classifier lookup table */
3782 for (index
= 0; index
< MVPP2_CLS_LKP_TBL_SIZE
; index
++) {
3785 mvpp2_cls_lookup_write(priv
, &le
);
3788 mvpp2_cls_lookup_write(priv
, &le
);
3792 static void mvpp2_cls_port_config(struct mvpp2_port
*port
)
3794 struct mvpp2_cls_lookup_entry le
;
3797 /* Set way for the port */
3798 val
= mvpp2_read(port
->priv
, MVPP2_CLS_PORT_WAY_REG
);
3799 val
&= ~MVPP2_CLS_PORT_WAY_MASK(port
->id
);
3800 mvpp2_write(port
->priv
, MVPP2_CLS_PORT_WAY_REG
, val
);
3802 /* Pick the entry to be accessed in lookup ID decoding table
3803 * according to the way and lkpid.
3805 le
.lkpid
= port
->id
;
3809 /* Set initial CPU queue for receiving packets */
3810 le
.data
&= ~MVPP2_CLS_LKP_TBL_RXQ_MASK
;
3811 le
.data
|= port
->first_rxq
;
3813 /* Disable classification engines */
3814 le
.data
&= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK
;
3816 /* Update lookup ID table entry */
3817 mvpp2_cls_lookup_write(port
->priv
, &le
);
3820 /* Set CPU queue number for oversize packets */
3821 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port
*port
)
3825 mvpp2_write(port
->priv
, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port
->id
),
3826 port
->first_rxq
& MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK
);
3828 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_P2HQ_REG(port
->id
),
3829 (port
->first_rxq
>> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS
));
3831 val
= mvpp2_read(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
);
3832 val
|= MVPP2_CLS_SWFWD_PCTRL_MASK(port
->id
);
3833 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
, val
);
3836 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool
*pool
)
3838 if (likely(pool
->frag_size
<= PAGE_SIZE
))
3839 return netdev_alloc_frag(pool
->frag_size
);
3841 return kmalloc(pool
->frag_size
, GFP_ATOMIC
);
3844 static void mvpp2_frag_free(const struct mvpp2_bm_pool
*pool
, void *data
)
3846 if (likely(pool
->frag_size
<= PAGE_SIZE
))
3847 skb_free_frag(data
);
3852 /* Buffer Manager configuration routines */
3855 static int mvpp2_bm_pool_create(struct platform_device
*pdev
,
3857 struct mvpp2_bm_pool
*bm_pool
, int size
)
3861 /* Number of buffer pointers must be a multiple of 16, as per
3862 * hardware constraints
3864 if (!IS_ALIGNED(size
, 16))
3867 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
3868 * bytes per buffer pointer
3870 if (priv
->hw_version
== MVPP21
)
3871 bm_pool
->size_bytes
= 2 * sizeof(u32
) * size
;
3873 bm_pool
->size_bytes
= 2 * sizeof(u64
) * size
;
3875 bm_pool
->virt_addr
= dma_alloc_coherent(&pdev
->dev
, bm_pool
->size_bytes
,
3878 if (!bm_pool
->virt_addr
)
3881 if (!IS_ALIGNED((unsigned long)bm_pool
->virt_addr
,
3882 MVPP2_BM_POOL_PTR_ALIGN
)) {
3883 dma_free_coherent(&pdev
->dev
, bm_pool
->size_bytes
,
3884 bm_pool
->virt_addr
, bm_pool
->dma_addr
);
3885 dev_err(&pdev
->dev
, "BM pool %d is not %d bytes aligned\n",
3886 bm_pool
->id
, MVPP2_BM_POOL_PTR_ALIGN
);
3890 mvpp2_write(priv
, MVPP2_BM_POOL_BASE_REG(bm_pool
->id
),
3891 lower_32_bits(bm_pool
->dma_addr
));
3892 mvpp2_write(priv
, MVPP2_BM_POOL_SIZE_REG(bm_pool
->id
), size
);
3894 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
3895 val
|= MVPP2_BM_START_MASK
;
3896 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
3898 bm_pool
->type
= MVPP2_BM_FREE
;
3899 bm_pool
->size
= size
;
3900 bm_pool
->pkt_size
= 0;
3901 bm_pool
->buf_num
= 0;
3906 /* Set pool buffer size */
3907 static void mvpp2_bm_pool_bufsize_set(struct mvpp2
*priv
,
3908 struct mvpp2_bm_pool
*bm_pool
,
3913 bm_pool
->buf_size
= buf_size
;
3915 val
= ALIGN(buf_size
, 1 << MVPP2_POOL_BUF_SIZE_OFFSET
);
3916 mvpp2_write(priv
, MVPP2_POOL_BUF_SIZE_REG(bm_pool
->id
), val
);
3919 static void mvpp2_bm_bufs_get_addrs(struct device
*dev
, struct mvpp2
*priv
,
3920 struct mvpp2_bm_pool
*bm_pool
,
3921 dma_addr_t
*dma_addr
,
3922 phys_addr_t
*phys_addr
)
3924 int cpu
= get_cpu();
3926 *dma_addr
= mvpp2_percpu_read(priv
, cpu
,
3927 MVPP2_BM_PHY_ALLOC_REG(bm_pool
->id
));
3928 *phys_addr
= mvpp2_percpu_read(priv
, cpu
, MVPP2_BM_VIRT_ALLOC_REG
);
3930 if (priv
->hw_version
== MVPP22
) {
3932 u32 dma_addr_highbits
, phys_addr_highbits
;
3934 val
= mvpp2_percpu_read(priv
, cpu
, MVPP22_BM_ADDR_HIGH_ALLOC
);
3935 dma_addr_highbits
= (val
& MVPP22_BM_ADDR_HIGH_PHYS_MASK
);
3936 phys_addr_highbits
= (val
& MVPP22_BM_ADDR_HIGH_VIRT_MASK
) >>
3937 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT
;
3939 if (sizeof(dma_addr_t
) == 8)
3940 *dma_addr
|= (u64
)dma_addr_highbits
<< 32;
3942 if (sizeof(phys_addr_t
) == 8)
3943 *phys_addr
|= (u64
)phys_addr_highbits
<< 32;
3949 /* Free all buffers from the pool */
3950 static void mvpp2_bm_bufs_free(struct device
*dev
, struct mvpp2
*priv
,
3951 struct mvpp2_bm_pool
*bm_pool
)
3955 for (i
= 0; i
< bm_pool
->buf_num
; i
++) {
3956 dma_addr_t buf_dma_addr
;
3957 phys_addr_t buf_phys_addr
;
3960 mvpp2_bm_bufs_get_addrs(dev
, priv
, bm_pool
,
3961 &buf_dma_addr
, &buf_phys_addr
);
3963 dma_unmap_single(dev
, buf_dma_addr
,
3964 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
3966 data
= (void *)phys_to_virt(buf_phys_addr
);
3970 mvpp2_frag_free(bm_pool
, data
);
3973 /* Update BM driver with number of buffers removed from pool */
3974 bm_pool
->buf_num
-= i
;
3978 static int mvpp2_bm_pool_destroy(struct platform_device
*pdev
,
3980 struct mvpp2_bm_pool
*bm_pool
)
3984 mvpp2_bm_bufs_free(&pdev
->dev
, priv
, bm_pool
);
3985 if (bm_pool
->buf_num
) {
3986 WARN(1, "cannot free all buffers in pool %d\n", bm_pool
->id
);
3990 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
3991 val
|= MVPP2_BM_STOP_MASK
;
3992 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
3994 dma_free_coherent(&pdev
->dev
, bm_pool
->size_bytes
,
4000 static int mvpp2_bm_pools_init(struct platform_device
*pdev
,
4004 struct mvpp2_bm_pool
*bm_pool
;
4006 /* Create all pools with maximum size */
4007 size
= MVPP2_BM_POOL_SIZE_MAX
;
4008 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
4009 bm_pool
= &priv
->bm_pools
[i
];
4011 err
= mvpp2_bm_pool_create(pdev
, priv
, bm_pool
, size
);
4013 goto err_unroll_pools
;
4014 mvpp2_bm_pool_bufsize_set(priv
, bm_pool
, 0);
4019 dev_err(&pdev
->dev
, "failed to create BM pool %d, size %d\n", i
, size
);
4020 for (i
= i
- 1; i
>= 0; i
--)
4021 mvpp2_bm_pool_destroy(pdev
, priv
, &priv
->bm_pools
[i
]);
4025 static int mvpp2_bm_init(struct platform_device
*pdev
, struct mvpp2
*priv
)
4029 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
4030 /* Mask BM all interrupts */
4031 mvpp2_write(priv
, MVPP2_BM_INTR_MASK_REG(i
), 0);
4032 /* Clear BM cause register */
4033 mvpp2_write(priv
, MVPP2_BM_INTR_CAUSE_REG(i
), 0);
4036 /* Allocate and initialize BM pools */
4037 priv
->bm_pools
= devm_kcalloc(&pdev
->dev
, MVPP2_BM_POOLS_NUM
,
4038 sizeof(*priv
->bm_pools
), GFP_KERNEL
);
4039 if (!priv
->bm_pools
)
4042 err
= mvpp2_bm_pools_init(pdev
, priv
);
4048 /* Attach long pool to rxq */
4049 static void mvpp2_rxq_long_pool_set(struct mvpp2_port
*port
,
4050 int lrxq
, int long_pool
)
4055 /* Get queue physical ID */
4056 prxq
= port
->rxqs
[lrxq
]->id
;
4058 if (port
->priv
->hw_version
== MVPP21
)
4059 mask
= MVPP21_RXQ_POOL_LONG_MASK
;
4061 mask
= MVPP22_RXQ_POOL_LONG_MASK
;
4063 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
4065 val
|= (long_pool
<< MVPP2_RXQ_POOL_LONG_OFFS
) & mask
;
4066 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
4069 /* Attach short pool to rxq */
4070 static void mvpp2_rxq_short_pool_set(struct mvpp2_port
*port
,
4071 int lrxq
, int short_pool
)
4076 /* Get queue physical ID */
4077 prxq
= port
->rxqs
[lrxq
]->id
;
4079 if (port
->priv
->hw_version
== MVPP21
)
4080 mask
= MVPP21_RXQ_POOL_SHORT_MASK
;
4082 mask
= MVPP22_RXQ_POOL_SHORT_MASK
;
4084 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
4086 val
|= (short_pool
<< MVPP2_RXQ_POOL_SHORT_OFFS
) & mask
;
4087 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
4090 static void *mvpp2_buf_alloc(struct mvpp2_port
*port
,
4091 struct mvpp2_bm_pool
*bm_pool
,
4092 dma_addr_t
*buf_dma_addr
,
4093 phys_addr_t
*buf_phys_addr
,
4096 dma_addr_t dma_addr
;
4099 data
= mvpp2_frag_alloc(bm_pool
);
4103 dma_addr
= dma_map_single(port
->dev
->dev
.parent
, data
,
4104 MVPP2_RX_BUF_SIZE(bm_pool
->pkt_size
),
4106 if (unlikely(dma_mapping_error(port
->dev
->dev
.parent
, dma_addr
))) {
4107 mvpp2_frag_free(bm_pool
, data
);
4110 *buf_dma_addr
= dma_addr
;
4111 *buf_phys_addr
= virt_to_phys(data
);
4116 /* Release buffer to BM */
4117 static inline void mvpp2_bm_pool_put(struct mvpp2_port
*port
, int pool
,
4118 dma_addr_t buf_dma_addr
,
4119 phys_addr_t buf_phys_addr
)
4121 int cpu
= get_cpu();
4123 if (port
->priv
->hw_version
== MVPP22
) {
4126 if (sizeof(dma_addr_t
) == 8)
4127 val
|= upper_32_bits(buf_dma_addr
) &
4128 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK
;
4130 if (sizeof(phys_addr_t
) == 8)
4131 val
|= (upper_32_bits(buf_phys_addr
)
4132 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT
) &
4133 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK
;
4135 mvpp2_percpu_write(port
->priv
, cpu
,
4136 MVPP22_BM_ADDR_HIGH_RLS_REG
, val
);
4139 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
4140 * returned in the "cookie" field of the RX
4141 * descriptor. Instead of storing the virtual address, we
4142 * store the physical address
4144 mvpp2_percpu_write(port
->priv
, cpu
,
4145 MVPP2_BM_VIRT_RLS_REG
, buf_phys_addr
);
4146 mvpp2_percpu_write(port
->priv
, cpu
,
4147 MVPP2_BM_PHY_RLS_REG(pool
), buf_dma_addr
);
4152 /* Allocate buffers for the pool */
4153 static int mvpp2_bm_bufs_add(struct mvpp2_port
*port
,
4154 struct mvpp2_bm_pool
*bm_pool
, int buf_num
)
4156 int i
, buf_size
, total_size
;
4157 dma_addr_t dma_addr
;
4158 phys_addr_t phys_addr
;
4161 buf_size
= MVPP2_RX_BUF_SIZE(bm_pool
->pkt_size
);
4162 total_size
= MVPP2_RX_TOTAL_SIZE(buf_size
);
4165 (buf_num
+ bm_pool
->buf_num
> bm_pool
->size
)) {
4166 netdev_err(port
->dev
,
4167 "cannot allocate %d buffers for pool %d\n",
4168 buf_num
, bm_pool
->id
);
4172 for (i
= 0; i
< buf_num
; i
++) {
4173 buf
= mvpp2_buf_alloc(port
, bm_pool
, &dma_addr
,
4174 &phys_addr
, GFP_KERNEL
);
4178 mvpp2_bm_pool_put(port
, bm_pool
->id
, dma_addr
,
4182 /* Update BM driver with number of buffers added to pool */
4183 bm_pool
->buf_num
+= i
;
4185 netdev_dbg(port
->dev
,
4186 "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
4187 bm_pool
->type
== MVPP2_BM_SWF_SHORT
? "short" : " long",
4188 bm_pool
->id
, bm_pool
->pkt_size
, buf_size
, total_size
);
4190 netdev_dbg(port
->dev
,
4191 "%s pool %d: %d of %d buffers added\n",
4192 bm_pool
->type
== MVPP2_BM_SWF_SHORT
? "short" : " long",
4193 bm_pool
->id
, i
, buf_num
);
4197 /* Notify the driver that BM pool is being used as specific type and return the
4198 * pool pointer on success
4200 static struct mvpp2_bm_pool
*
4201 mvpp2_bm_pool_use(struct mvpp2_port
*port
, int pool
, enum mvpp2_bm_type type
,
4204 struct mvpp2_bm_pool
*new_pool
= &port
->priv
->bm_pools
[pool
];
4207 if (new_pool
->type
!= MVPP2_BM_FREE
&& new_pool
->type
!= type
) {
4208 netdev_err(port
->dev
, "mixing pool types is forbidden\n");
4212 if (new_pool
->type
== MVPP2_BM_FREE
)
4213 new_pool
->type
= type
;
4215 /* Allocate buffers in case BM pool is used as long pool, but packet
4216 * size doesn't match MTU or BM pool hasn't being used yet
4218 if (((type
== MVPP2_BM_SWF_LONG
) && (pkt_size
> new_pool
->pkt_size
)) ||
4219 (new_pool
->pkt_size
== 0)) {
4222 /* Set default buffer number or free all the buffers in case
4223 * the pool is not empty
4225 pkts_num
= new_pool
->buf_num
;
4227 pkts_num
= type
== MVPP2_BM_SWF_LONG
?
4228 MVPP2_BM_LONG_BUF_NUM
:
4229 MVPP2_BM_SHORT_BUF_NUM
;
4231 mvpp2_bm_bufs_free(port
->dev
->dev
.parent
,
4232 port
->priv
, new_pool
);
4234 new_pool
->pkt_size
= pkt_size
;
4235 new_pool
->frag_size
=
4236 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size
)) +
4237 MVPP2_SKB_SHINFO_SIZE
;
4239 /* Allocate buffers for this pool */
4240 num
= mvpp2_bm_bufs_add(port
, new_pool
, pkts_num
);
4241 if (num
!= pkts_num
) {
4242 WARN(1, "pool %d: %d of %d allocated\n",
4243 new_pool
->id
, num
, pkts_num
);
4248 mvpp2_bm_pool_bufsize_set(port
->priv
, new_pool
,
4249 MVPP2_RX_BUF_SIZE(new_pool
->pkt_size
));
4254 /* Initialize pools for swf */
4255 static int mvpp2_swf_bm_pool_init(struct mvpp2_port
*port
)
4259 if (!port
->pool_long
) {
4261 mvpp2_bm_pool_use(port
, MVPP2_BM_SWF_LONG_POOL(port
->id
),
4264 if (!port
->pool_long
)
4267 port
->pool_long
->port_map
|= (1 << port
->id
);
4269 for (rxq
= 0; rxq
< port
->nrxqs
; rxq
++)
4270 mvpp2_rxq_long_pool_set(port
, rxq
, port
->pool_long
->id
);
4273 if (!port
->pool_short
) {
4275 mvpp2_bm_pool_use(port
, MVPP2_BM_SWF_SHORT_POOL
,
4277 MVPP2_BM_SHORT_PKT_SIZE
);
4278 if (!port
->pool_short
)
4281 port
->pool_short
->port_map
|= (1 << port
->id
);
4283 for (rxq
= 0; rxq
< port
->nrxqs
; rxq
++)
4284 mvpp2_rxq_short_pool_set(port
, rxq
,
4285 port
->pool_short
->id
);
4291 static int mvpp2_bm_update_mtu(struct net_device
*dev
, int mtu
)
4293 struct mvpp2_port
*port
= netdev_priv(dev
);
4294 struct mvpp2_bm_pool
*port_pool
= port
->pool_long
;
4295 int num
, pkts_num
= port_pool
->buf_num
;
4296 int pkt_size
= MVPP2_RX_PKT_SIZE(mtu
);
4298 /* Update BM pool with new buffer size */
4299 mvpp2_bm_bufs_free(dev
->dev
.parent
, port
->priv
, port_pool
);
4300 if (port_pool
->buf_num
) {
4301 WARN(1, "cannot free all buffers in pool %d\n", port_pool
->id
);
4305 port_pool
->pkt_size
= pkt_size
;
4306 port_pool
->frag_size
= SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size
)) +
4307 MVPP2_SKB_SHINFO_SIZE
;
4308 num
= mvpp2_bm_bufs_add(port
, port_pool
, pkts_num
);
4309 if (num
!= pkts_num
) {
4310 WARN(1, "pool %d: %d of %d allocated\n",
4311 port_pool
->id
, num
, pkts_num
);
4315 mvpp2_bm_pool_bufsize_set(port
->priv
, port_pool
,
4316 MVPP2_RX_BUF_SIZE(port_pool
->pkt_size
));
4318 netdev_update_features(dev
);
4322 static inline void mvpp2_interrupts_enable(struct mvpp2_port
*port
)
4324 int i
, sw_thread_mask
= 0;
4326 for (i
= 0; i
< port
->nqvecs
; i
++)
4327 sw_thread_mask
|= port
->qvecs
[i
].sw_thread_mask
;
4329 mvpp2_write(port
->priv
, MVPP2_ISR_ENABLE_REG(port
->id
),
4330 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask
));
4333 static inline void mvpp2_interrupts_disable(struct mvpp2_port
*port
)
4335 int i
, sw_thread_mask
= 0;
4337 for (i
= 0; i
< port
->nqvecs
; i
++)
4338 sw_thread_mask
|= port
->qvecs
[i
].sw_thread_mask
;
4340 mvpp2_write(port
->priv
, MVPP2_ISR_ENABLE_REG(port
->id
),
4341 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask
));
4344 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector
*qvec
)
4346 struct mvpp2_port
*port
= qvec
->port
;
4348 mvpp2_write(port
->priv
, MVPP2_ISR_ENABLE_REG(port
->id
),
4349 MVPP2_ISR_ENABLE_INTERRUPT(qvec
->sw_thread_mask
));
4352 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector
*qvec
)
4354 struct mvpp2_port
*port
= qvec
->port
;
4356 mvpp2_write(port
->priv
, MVPP2_ISR_ENABLE_REG(port
->id
),
4357 MVPP2_ISR_DISABLE_INTERRUPT(qvec
->sw_thread_mask
));
4360 /* Mask the current CPU's Rx/Tx interrupts
4361 * Called by on_each_cpu(), guaranteed to run with migration disabled,
4362 * using smp_processor_id() is OK.
4364 static void mvpp2_interrupts_mask(void *arg
)
4366 struct mvpp2_port
*port
= arg
;
4368 mvpp2_percpu_write(port
->priv
, smp_processor_id(),
4369 MVPP2_ISR_RX_TX_MASK_REG(port
->id
), 0);
4372 /* Unmask the current CPU's Rx/Tx interrupts.
4373 * Called by on_each_cpu(), guaranteed to run with migration disabled,
4374 * using smp_processor_id() is OK.
4376 static void mvpp2_interrupts_unmask(void *arg
)
4378 struct mvpp2_port
*port
= arg
;
4381 val
= MVPP2_CAUSE_MISC_SUM_MASK
|
4382 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
;
4383 if (port
->has_tx_irqs
)
4384 val
|= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK
;
4386 mvpp2_percpu_write(port
->priv
, smp_processor_id(),
4387 MVPP2_ISR_RX_TX_MASK_REG(port
->id
), val
);
4391 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port
*port
, bool mask
)
4396 if (port
->priv
->hw_version
!= MVPP22
)
4402 val
= MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
;
4404 for (i
= 0; i
< port
->nqvecs
; i
++) {
4405 struct mvpp2_queue_vector
*v
= port
->qvecs
+ i
;
4407 if (v
->type
!= MVPP2_QUEUE_VECTOR_SHARED
)
4410 mvpp2_percpu_write(port
->priv
, v
->sw_thread_id
,
4411 MVPP2_ISR_RX_TX_MASK_REG(port
->id
), val
);
4415 /* Port configuration routines */
4417 static void mvpp22_gop_init_rgmii(struct mvpp2_port
*port
)
4419 struct mvpp2
*priv
= port
->priv
;
4422 regmap_read(priv
->sysctrl_base
, GENCONF_PORT_CTRL0
, &val
);
4423 val
|= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT
;
4424 regmap_write(priv
->sysctrl_base
, GENCONF_PORT_CTRL0
, val
);
4426 regmap_read(priv
->sysctrl_base
, GENCONF_CTRL0
, &val
);
4427 if (port
->gop_id
== 2)
4428 val
|= GENCONF_CTRL0_PORT0_RGMII
| GENCONF_CTRL0_PORT1_RGMII
;
4429 else if (port
->gop_id
== 3)
4430 val
|= GENCONF_CTRL0_PORT1_RGMII_MII
;
4431 regmap_write(priv
->sysctrl_base
, GENCONF_CTRL0
, val
);
4434 static void mvpp22_gop_init_sgmii(struct mvpp2_port
*port
)
4436 struct mvpp2
*priv
= port
->priv
;
4439 regmap_read(priv
->sysctrl_base
, GENCONF_PORT_CTRL0
, &val
);
4440 val
|= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT
|
4441 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE
;
4442 regmap_write(priv
->sysctrl_base
, GENCONF_PORT_CTRL0
, val
);
4444 if (port
->gop_id
> 1) {
4445 regmap_read(priv
->sysctrl_base
, GENCONF_CTRL0
, &val
);
4446 if (port
->gop_id
== 2)
4447 val
&= ~GENCONF_CTRL0_PORT0_RGMII
;
4448 else if (port
->gop_id
== 3)
4449 val
&= ~GENCONF_CTRL0_PORT1_RGMII_MII
;
4450 regmap_write(priv
->sysctrl_base
, GENCONF_CTRL0
, val
);
4454 static void mvpp22_gop_init_10gkr(struct mvpp2_port
*port
)
4456 struct mvpp2
*priv
= port
->priv
;
4457 void __iomem
*mpcs
= priv
->iface_base
+ MVPP22_MPCS_BASE(port
->gop_id
);
4458 void __iomem
*xpcs
= priv
->iface_base
+ MVPP22_XPCS_BASE(port
->gop_id
);
4462 val
= readl(xpcs
+ MVPP22_XPCS_CFG0
);
4463 val
&= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
4464 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
4465 val
|= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
4466 writel(val
, xpcs
+ MVPP22_XPCS_CFG0
);
4469 val
= readl(mpcs
+ MVPP22_MPCS_CTRL
);
4470 val
&= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN
;
4471 writel(val
, mpcs
+ MVPP22_MPCS_CTRL
);
4473 val
= readl(mpcs
+ MVPP22_MPCS_CLK_RESET
);
4474 val
&= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC
|
4475 MAC_CLK_RESET_SD_RX
| MAC_CLK_RESET_SD_TX
);
4476 val
|= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
4477 writel(val
, mpcs
+ MVPP22_MPCS_CLK_RESET
);
4479 val
&= ~MVPP22_MPCS_CLK_RESET_DIV_SET
;
4480 val
|= MAC_CLK_RESET_MAC
| MAC_CLK_RESET_SD_RX
| MAC_CLK_RESET_SD_TX
;
4481 writel(val
, mpcs
+ MVPP22_MPCS_CLK_RESET
);
4484 static int mvpp22_gop_init(struct mvpp2_port
*port
)
4486 struct mvpp2
*priv
= port
->priv
;
4489 if (!priv
->sysctrl_base
)
4492 switch (port
->phy_interface
) {
4493 case PHY_INTERFACE_MODE_RGMII
:
4494 case PHY_INTERFACE_MODE_RGMII_ID
:
4495 case PHY_INTERFACE_MODE_RGMII_RXID
:
4496 case PHY_INTERFACE_MODE_RGMII_TXID
:
4497 if (port
->gop_id
== 0)
4499 mvpp22_gop_init_rgmii(port
);
4501 case PHY_INTERFACE_MODE_SGMII
:
4502 mvpp22_gop_init_sgmii(port
);
4504 case PHY_INTERFACE_MODE_10GKR
:
4505 if (port
->gop_id
!= 0)
4507 mvpp22_gop_init_10gkr(port
);
4510 goto unsupported_conf
;
4513 regmap_read(priv
->sysctrl_base
, GENCONF_PORT_CTRL1
, &val
);
4514 val
|= GENCONF_PORT_CTRL1_RESET(port
->gop_id
) |
4515 GENCONF_PORT_CTRL1_EN(port
->gop_id
);
4516 regmap_write(priv
->sysctrl_base
, GENCONF_PORT_CTRL1
, val
);
4518 regmap_read(priv
->sysctrl_base
, GENCONF_PORT_CTRL0
, &val
);
4519 val
|= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR
;
4520 regmap_write(priv
->sysctrl_base
, GENCONF_PORT_CTRL0
, val
);
4522 regmap_read(priv
->sysctrl_base
, GENCONF_SOFT_RESET1
, &val
);
4523 val
|= GENCONF_SOFT_RESET1_GOP
;
4524 regmap_write(priv
->sysctrl_base
, GENCONF_SOFT_RESET1
, val
);
4530 netdev_err(port
->dev
, "Invalid port configuration\n");
4534 static void mvpp22_gop_unmask_irq(struct mvpp2_port
*port
)
4538 if (phy_interface_mode_is_rgmii(port
->phy_interface
) ||
4539 port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
4540 /* Enable the GMAC link status irq for this port */
4541 val
= readl(port
->base
+ MVPP22_GMAC_INT_SUM_MASK
);
4542 val
|= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT
;
4543 writel(val
, port
->base
+ MVPP22_GMAC_INT_SUM_MASK
);
4546 if (port
->gop_id
== 0) {
4547 /* Enable the XLG/GIG irqs for this port */
4548 val
= readl(port
->base
+ MVPP22_XLG_EXT_INT_MASK
);
4549 if (port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
)
4550 val
|= MVPP22_XLG_EXT_INT_MASK_XLG
;
4552 val
|= MVPP22_XLG_EXT_INT_MASK_GIG
;
4553 writel(val
, port
->base
+ MVPP22_XLG_EXT_INT_MASK
);
4557 static void mvpp22_gop_mask_irq(struct mvpp2_port
*port
)
4561 if (port
->gop_id
== 0) {
4562 val
= readl(port
->base
+ MVPP22_XLG_EXT_INT_MASK
);
4563 val
&= ~(MVPP22_XLG_EXT_INT_MASK_XLG
|
4564 MVPP22_XLG_EXT_INT_MASK_GIG
);
4565 writel(val
, port
->base
+ MVPP22_XLG_EXT_INT_MASK
);
4568 if (phy_interface_mode_is_rgmii(port
->phy_interface
) ||
4569 port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
4570 val
= readl(port
->base
+ MVPP22_GMAC_INT_SUM_MASK
);
4571 val
&= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT
;
4572 writel(val
, port
->base
+ MVPP22_GMAC_INT_SUM_MASK
);
4576 static void mvpp22_gop_setup_irq(struct mvpp2_port
*port
)
4580 if (phy_interface_mode_is_rgmii(port
->phy_interface
) ||
4581 port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
4582 val
= readl(port
->base
+ MVPP22_GMAC_INT_MASK
);
4583 val
|= MVPP22_GMAC_INT_MASK_LINK_STAT
;
4584 writel(val
, port
->base
+ MVPP22_GMAC_INT_MASK
);
4587 if (port
->gop_id
== 0) {
4588 val
= readl(port
->base
+ MVPP22_XLG_INT_MASK
);
4589 val
|= MVPP22_XLG_INT_MASK_LINK
;
4590 writel(val
, port
->base
+ MVPP22_XLG_INT_MASK
);
4593 mvpp22_gop_unmask_irq(port
);
4596 static int mvpp22_comphy_init(struct mvpp2_port
*port
)
4604 switch (port
->phy_interface
) {
4605 case PHY_INTERFACE_MODE_SGMII
:
4606 mode
= PHY_MODE_SGMII
;
4608 case PHY_INTERFACE_MODE_10GKR
:
4609 mode
= PHY_MODE_10GKR
;
4615 ret
= phy_set_mode(port
->comphy
, mode
);
4619 return phy_power_on(port
->comphy
);
4622 static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port
*port
)
4626 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
4627 val
= readl(port
->base
+ MVPP22_GMAC_CTRL_4_REG
);
4628 val
|= MVPP22_CTRL4_SYNC_BYPASS_DIS
| MVPP22_CTRL4_DP_CLK_SEL
|
4629 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE
;
4630 val
&= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL
;
4631 writel(val
, port
->base
+ MVPP22_GMAC_CTRL_4_REG
);
4633 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4634 val
|= MVPP2_GMAC_DISABLE_PADDING
;
4635 val
&= ~MVPP2_GMAC_FLOW_CTRL_MASK
;
4636 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4637 } else if (phy_interface_mode_is_rgmii(port
->phy_interface
)) {
4638 val
= readl(port
->base
+ MVPP22_GMAC_CTRL_4_REG
);
4639 val
|= MVPP22_CTRL4_EXT_PIN_GMII_SEL
|
4640 MVPP22_CTRL4_SYNC_BYPASS_DIS
|
4641 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE
;
4642 val
&= ~MVPP22_CTRL4_DP_CLK_SEL
;
4643 writel(val
, port
->base
+ MVPP22_GMAC_CTRL_4_REG
);
4645 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4646 val
&= ~MVPP2_GMAC_DISABLE_PADDING
;
4647 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4650 /* The port is connected to a copper PHY */
4651 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4652 val
&= ~MVPP2_GMAC_PORT_TYPE_MASK
;
4653 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4655 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4656 val
|= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS
|
4657 MVPP2_GMAC_AN_SPEED_EN
| MVPP2_GMAC_FLOW_CTRL_AUTONEG
|
4658 MVPP2_GMAC_AN_DUPLEX_EN
;
4659 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
4660 val
|= MVPP2_GMAC_IN_BAND_AUTONEG
;
4661 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4664 static void mvpp2_port_mii_gmac_configure(struct mvpp2_port
*port
)
4668 /* Force link down */
4669 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4670 val
&= ~MVPP2_GMAC_FORCE_LINK_PASS
;
4671 val
|= MVPP2_GMAC_FORCE_LINK_DOWN
;
4672 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4674 /* Set the GMAC in a reset state */
4675 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4676 val
|= MVPP2_GMAC_PORT_RESET_MASK
;
4677 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4679 /* Configure the PCS and in-band AN */
4680 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4681 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
4682 val
|= MVPP2_GMAC_INBAND_AN_MASK
| MVPP2_GMAC_PCS_ENABLE_MASK
;
4683 } else if (phy_interface_mode_is_rgmii(port
->phy_interface
)) {
4684 val
&= ~MVPP2_GMAC_PCS_ENABLE_MASK
;
4686 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4688 mvpp2_port_mii_gmac_configure_mode(port
);
4690 /* Unset the GMAC reset state */
4691 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4692 val
&= ~MVPP2_GMAC_PORT_RESET_MASK
;
4693 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4695 /* Stop forcing link down */
4696 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4697 val
&= ~MVPP2_GMAC_FORCE_LINK_DOWN
;
4698 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4701 static void mvpp2_port_mii_xlg_configure(struct mvpp2_port
*port
)
4705 if (port
->gop_id
!= 0)
4708 val
= readl(port
->base
+ MVPP22_XLG_CTRL0_REG
);
4709 val
|= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN
;
4710 writel(val
, port
->base
+ MVPP22_XLG_CTRL0_REG
);
4712 val
= readl(port
->base
+ MVPP22_XLG_CTRL4_REG
);
4713 val
&= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC
;
4714 val
|= MVPP22_XLG_CTRL4_FWD_FC
| MVPP22_XLG_CTRL4_FWD_PFC
;
4715 writel(val
, port
->base
+ MVPP22_XLG_CTRL4_REG
);
4718 static void mvpp22_port_mii_set(struct mvpp2_port
*port
)
4722 /* Only GOP port 0 has an XLG MAC */
4723 if (port
->gop_id
== 0) {
4724 val
= readl(port
->base
+ MVPP22_XLG_CTRL3_REG
);
4725 val
&= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK
;
4727 if (port
->phy_interface
== PHY_INTERFACE_MODE_XAUI
||
4728 port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
)
4729 val
|= MVPP22_XLG_CTRL3_MACMODESELECT_10G
;
4731 val
|= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC
;
4733 writel(val
, port
->base
+ MVPP22_XLG_CTRL3_REG
);
4737 static void mvpp2_port_mii_set(struct mvpp2_port
*port
)
4739 if (port
->priv
->hw_version
== MVPP22
)
4740 mvpp22_port_mii_set(port
);
4742 if (phy_interface_mode_is_rgmii(port
->phy_interface
) ||
4743 port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
4744 mvpp2_port_mii_gmac_configure(port
);
4745 else if (port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
)
4746 mvpp2_port_mii_xlg_configure(port
);
4749 static void mvpp2_port_fc_adv_enable(struct mvpp2_port
*port
)
4753 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4754 val
|= MVPP2_GMAC_FC_ADV_EN
;
4755 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4758 static void mvpp2_port_enable(struct mvpp2_port
*port
)
4762 /* Only GOP port 0 has an XLG MAC */
4763 if (port
->gop_id
== 0 &&
4764 (port
->phy_interface
== PHY_INTERFACE_MODE_XAUI
||
4765 port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
)) {
4766 val
= readl(port
->base
+ MVPP22_XLG_CTRL0_REG
);
4767 val
|= MVPP22_XLG_CTRL0_PORT_EN
|
4768 MVPP22_XLG_CTRL0_MAC_RESET_DIS
;
4769 val
&= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS
;
4770 writel(val
, port
->base
+ MVPP22_XLG_CTRL0_REG
);
4772 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4773 val
|= MVPP2_GMAC_PORT_EN_MASK
;
4774 val
|= MVPP2_GMAC_MIB_CNTR_EN_MASK
;
4775 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4779 static void mvpp2_port_disable(struct mvpp2_port
*port
)
4783 /* Only GOP port 0 has an XLG MAC */
4784 if (port
->gop_id
== 0 &&
4785 (port
->phy_interface
== PHY_INTERFACE_MODE_XAUI
||
4786 port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
)) {
4787 val
= readl(port
->base
+ MVPP22_XLG_CTRL0_REG
);
4788 val
&= ~(MVPP22_XLG_CTRL0_PORT_EN
|
4789 MVPP22_XLG_CTRL0_MAC_RESET_DIS
);
4790 writel(val
, port
->base
+ MVPP22_XLG_CTRL0_REG
);
4792 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4793 val
&= ~(MVPP2_GMAC_PORT_EN_MASK
);
4794 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4798 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
4799 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port
*port
)
4803 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
) &
4804 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK
;
4805 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
4808 /* Configure loopback port */
4809 static void mvpp2_port_loopback_set(struct mvpp2_port
*port
)
4813 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
4815 if (port
->speed
== 1000)
4816 val
|= MVPP2_GMAC_GMII_LB_EN_MASK
;
4818 val
&= ~MVPP2_GMAC_GMII_LB_EN_MASK
;
4820 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
4821 val
|= MVPP2_GMAC_PCS_LB_EN_MASK
;
4823 val
&= ~MVPP2_GMAC_PCS_LB_EN_MASK
;
4825 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
4828 struct mvpp2_ethtool_counter
{
4829 unsigned int offset
;
4830 const char string
[ETH_GSTRING_LEN
];
4834 static u64
mvpp2_read_count(struct mvpp2_port
*port
,
4835 const struct mvpp2_ethtool_counter
*counter
)
4839 val
= readl(port
->stats_base
+ counter
->offset
);
4840 if (counter
->reg_is_64b
)
4841 val
+= (u64
)readl(port
->stats_base
+ counter
->offset
+ 4) << 32;
4846 /* Due to the fact that software statistics and hardware statistics are, by
4847 * design, incremented at different moments in the chain of packet processing,
4848 * it is very likely that incoming packets could have been dropped after being
4849 * counted by hardware but before reaching software statistics (most probably
4850 * multicast packets), and in the oppposite way, during transmission, FCS bytes
4851 * are added in between as well as TSO skb will be split and header bytes added.
4852 * Hence, statistics gathered from userspace with ifconfig (software) and
4853 * ethtool (hardware) cannot be compared.
4855 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs
[] = {
4856 { MVPP2_MIB_GOOD_OCTETS_RCVD
, "good_octets_received", true },
4857 { MVPP2_MIB_BAD_OCTETS_RCVD
, "bad_octets_received" },
4858 { MVPP2_MIB_CRC_ERRORS_SENT
, "crc_errors_sent" },
4859 { MVPP2_MIB_UNICAST_FRAMES_RCVD
, "unicast_frames_received" },
4860 { MVPP2_MIB_BROADCAST_FRAMES_RCVD
, "broadcast_frames_received" },
4861 { MVPP2_MIB_MULTICAST_FRAMES_RCVD
, "multicast_frames_received" },
4862 { MVPP2_MIB_FRAMES_64_OCTETS
, "frames_64_octets" },
4863 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS
, "frames_65_to_127_octet" },
4864 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS
, "frames_128_to_255_octet" },
4865 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS
, "frames_256_to_511_octet" },
4866 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS
, "frames_512_to_1023_octet" },
4867 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS
, "frames_1024_to_max_octet" },
4868 { MVPP2_MIB_GOOD_OCTETS_SENT
, "good_octets_sent", true },
4869 { MVPP2_MIB_UNICAST_FRAMES_SENT
, "unicast_frames_sent" },
4870 { MVPP2_MIB_MULTICAST_FRAMES_SENT
, "multicast_frames_sent" },
4871 { MVPP2_MIB_BROADCAST_FRAMES_SENT
, "broadcast_frames_sent" },
4872 { MVPP2_MIB_FC_SENT
, "fc_sent" },
4873 { MVPP2_MIB_FC_RCVD
, "fc_received" },
4874 { MVPP2_MIB_RX_FIFO_OVERRUN
, "rx_fifo_overrun" },
4875 { MVPP2_MIB_UNDERSIZE_RCVD
, "undersize_received" },
4876 { MVPP2_MIB_FRAGMENTS_RCVD
, "fragments_received" },
4877 { MVPP2_MIB_OVERSIZE_RCVD
, "oversize_received" },
4878 { MVPP2_MIB_JABBER_RCVD
, "jabber_received" },
4879 { MVPP2_MIB_MAC_RCV_ERROR
, "mac_receive_error" },
4880 { MVPP2_MIB_BAD_CRC_EVENT
, "bad_crc_event" },
4881 { MVPP2_MIB_COLLISION
, "collision" },
4882 { MVPP2_MIB_LATE_COLLISION
, "late_collision" },
4885 static void mvpp2_ethtool_get_strings(struct net_device
*netdev
, u32 sset
,
4888 if (sset
== ETH_SS_STATS
) {
4891 for (i
= 0; i
< ARRAY_SIZE(mvpp2_ethtool_regs
); i
++)
4892 memcpy(data
+ i
* ETH_GSTRING_LEN
,
4893 &mvpp2_ethtool_regs
[i
].string
, ETH_GSTRING_LEN
);
4897 static void mvpp2_gather_hw_statistics(struct work_struct
*work
)
4899 struct delayed_work
*del_work
= to_delayed_work(work
);
4900 struct mvpp2_port
*port
= container_of(del_work
, struct mvpp2_port
,
4905 mutex_lock(&port
->gather_stats_lock
);
4907 pstats
= port
->ethtool_stats
;
4908 for (i
= 0; i
< ARRAY_SIZE(mvpp2_ethtool_regs
); i
++)
4909 *pstats
++ += mvpp2_read_count(port
, &mvpp2_ethtool_regs
[i
]);
4911 /* No need to read again the counters right after this function if it
4912 * was called asynchronously by the user (ie. use of ethtool).
4914 cancel_delayed_work(&port
->stats_work
);
4915 queue_delayed_work(port
->priv
->stats_queue
, &port
->stats_work
,
4916 MVPP2_MIB_COUNTERS_STATS_DELAY
);
4918 mutex_unlock(&port
->gather_stats_lock
);
4921 static void mvpp2_ethtool_get_stats(struct net_device
*dev
,
4922 struct ethtool_stats
*stats
, u64
*data
)
4924 struct mvpp2_port
*port
= netdev_priv(dev
);
4926 /* Update statistics for the given port, then take the lock to avoid
4927 * concurrent accesses on the ethtool_stats structure during its copy.
4929 mvpp2_gather_hw_statistics(&port
->stats_work
.work
);
4931 mutex_lock(&port
->gather_stats_lock
);
4932 memcpy(data
, port
->ethtool_stats
,
4933 sizeof(u64
) * ARRAY_SIZE(mvpp2_ethtool_regs
));
4934 mutex_unlock(&port
->gather_stats_lock
);
4937 static int mvpp2_ethtool_get_sset_count(struct net_device
*dev
, int sset
)
4939 if (sset
== ETH_SS_STATS
)
4940 return ARRAY_SIZE(mvpp2_ethtool_regs
);
4945 static void mvpp2_port_reset(struct mvpp2_port
*port
)
4950 /* Read the GOP statistics to reset the hardware counters */
4951 for (i
= 0; i
< ARRAY_SIZE(mvpp2_ethtool_regs
); i
++)
4952 mvpp2_read_count(port
, &mvpp2_ethtool_regs
[i
]);
4954 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
4955 ~MVPP2_GMAC_PORT_RESET_MASK
;
4956 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
4958 while (readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
4959 MVPP2_GMAC_PORT_RESET_MASK
)
4963 /* Change maximum receive size of the port */
4964 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port
*port
)
4968 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4969 val
&= ~MVPP2_GMAC_MAX_RX_SIZE_MASK
;
4970 val
|= (((port
->pkt_size
- MVPP2_MH_SIZE
) / 2) <<
4971 MVPP2_GMAC_MAX_RX_SIZE_OFFS
);
4972 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
4975 /* Change maximum receive size of the port */
4976 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port
*port
)
4980 val
= readl(port
->base
+ MVPP22_XLG_CTRL1_REG
);
4981 val
&= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK
;
4982 val
|= ((port
->pkt_size
- MVPP2_MH_SIZE
) / 2) <<
4983 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS
;
4984 writel(val
, port
->base
+ MVPP22_XLG_CTRL1_REG
);
4987 /* Set defaults to the MVPP2 port */
4988 static void mvpp2_defaults_set(struct mvpp2_port
*port
)
4990 int tx_port_num
, val
, queue
, ptxq
, lrxq
;
4992 if (port
->priv
->hw_version
== MVPP21
) {
4993 /* Configure port to loopback if needed */
4994 if (port
->flags
& MVPP2_F_LOOPBACK
)
4995 mvpp2_port_loopback_set(port
);
4997 /* Update TX FIFO MIN Threshold */
4998 val
= readl(port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
4999 val
&= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK
;
5000 /* Min. TX threshold must be less than minimal packet length */
5001 val
|= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
5002 writel(val
, port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
5005 /* Disable Legacy WRR, Disable EJP, Release from reset */
5006 tx_port_num
= mvpp2_egress_port(port
);
5007 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
,
5009 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_CMD_1_REG
, 0);
5011 /* Close bandwidth for all queues */
5012 for (queue
= 0; queue
< MVPP2_MAX_TXQ
; queue
++) {
5013 ptxq
= mvpp2_txq_phys(port
->id
, queue
);
5014 mvpp2_write(port
->priv
,
5015 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq
), 0);
5018 /* Set refill period to 1 usec, refill tokens
5019 * and bucket size to maximum
5021 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PERIOD_REG
,
5022 port
->priv
->tclk
/ USEC_PER_SEC
);
5023 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
);
5024 val
&= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK
;
5025 val
|= MVPP2_TXP_REFILL_PERIOD_MASK(1);
5026 val
|= MVPP2_TXP_REFILL_TOKENS_ALL_MASK
;
5027 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
, val
);
5028 val
= MVPP2_TXP_TOKEN_SIZE_MAX
;
5029 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
5031 /* Set MaximumLowLatencyPacketSize value to 256 */
5032 mvpp2_write(port
->priv
, MVPP2_RX_CTRL_REG(port
->id
),
5033 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK
|
5034 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
5036 /* Enable Rx cache snoop */
5037 for (lrxq
= 0; lrxq
< port
->nrxqs
; lrxq
++) {
5038 queue
= port
->rxqs
[lrxq
]->id
;
5039 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
5040 val
|= MVPP2_SNOOP_PKT_SIZE_MASK
|
5041 MVPP2_SNOOP_BUF_HDR_MASK
;
5042 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
5045 /* At default, mask all interrupts to all present cpus */
5046 mvpp2_interrupts_disable(port
);
5049 /* Enable/disable receiving packets */
5050 static void mvpp2_ingress_enable(struct mvpp2_port
*port
)
5055 for (lrxq
= 0; lrxq
< port
->nrxqs
; lrxq
++) {
5056 queue
= port
->rxqs
[lrxq
]->id
;
5057 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
5058 val
&= ~MVPP2_RXQ_DISABLE_MASK
;
5059 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
5063 static void mvpp2_ingress_disable(struct mvpp2_port
*port
)
5068 for (lrxq
= 0; lrxq
< port
->nrxqs
; lrxq
++) {
5069 queue
= port
->rxqs
[lrxq
]->id
;
5070 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
5071 val
|= MVPP2_RXQ_DISABLE_MASK
;
5072 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
5076 /* Enable transmit via physical egress queue
5077 * - HW starts take descriptors from DRAM
5079 static void mvpp2_egress_enable(struct mvpp2_port
*port
)
5083 int tx_port_num
= mvpp2_egress_port(port
);
5085 /* Enable all initialized TXs. */
5087 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
5088 struct mvpp2_tx_queue
*txq
= port
->txqs
[queue
];
5091 qmap
|= (1 << queue
);
5094 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
5095 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
, qmap
);
5098 /* Disable transmit via physical egress queue
5099 * - HW doesn't take descriptors from DRAM
5101 static void mvpp2_egress_disable(struct mvpp2_port
*port
)
5105 int tx_port_num
= mvpp2_egress_port(port
);
5107 /* Issue stop command for active channels only */
5108 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
5109 reg_data
= (mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
)) &
5110 MVPP2_TXP_SCHED_ENQ_MASK
;
5112 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
,
5113 (reg_data
<< MVPP2_TXP_SCHED_DISQ_OFFSET
));
5115 /* Wait for all Tx activity to terminate. */
5118 if (delay
>= MVPP2_TX_DISABLE_TIMEOUT_MSEC
) {
5119 netdev_warn(port
->dev
,
5120 "Tx stop timed out, status=0x%08x\n",
5127 /* Check port TX Command register that all
5128 * Tx queues are stopped
5130 reg_data
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
);
5131 } while (reg_data
& MVPP2_TXP_SCHED_ENQ_MASK
);
5134 /* Rx descriptors helper methods */
5136 /* Get number of Rx descriptors occupied by received packets */
5138 mvpp2_rxq_received(struct mvpp2_port
*port
, int rxq_id
)
5140 u32 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq_id
));
5142 return val
& MVPP2_RXQ_OCCUPIED_MASK
;
5145 /* Update Rx queue status with the number of occupied and available
5146 * Rx descriptor slots.
5149 mvpp2_rxq_status_update(struct mvpp2_port
*port
, int rxq_id
,
5150 int used_count
, int free_count
)
5152 /* Decrement the number of used descriptors and increment count
5153 * increment the number of free descriptors.
5155 u32 val
= used_count
| (free_count
<< MVPP2_RXQ_NUM_NEW_OFFSET
);
5157 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id
), val
);
5160 /* Get pointer to next RX descriptor to be processed by SW */
5161 static inline struct mvpp2_rx_desc
*
5162 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue
*rxq
)
5164 int rx_desc
= rxq
->next_desc_to_proc
;
5166 rxq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(rxq
, rx_desc
);
5167 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
5168 return rxq
->descs
+ rx_desc
;
5171 /* Set rx queue offset */
5172 static void mvpp2_rxq_offset_set(struct mvpp2_port
*port
,
5173 int prxq
, int offset
)
5177 /* Convert offset from bytes to units of 32 bytes */
5178 offset
= offset
>> 5;
5180 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
5181 val
&= ~MVPP2_RXQ_PACKET_OFFSET_MASK
;
5184 val
|= ((offset
<< MVPP2_RXQ_PACKET_OFFSET_OFFS
) &
5185 MVPP2_RXQ_PACKET_OFFSET_MASK
);
5187 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
5190 /* Tx descriptors helper methods */
5192 /* Get pointer to next Tx descriptor to be processed (send) by HW */
5193 static struct mvpp2_tx_desc
*
5194 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue
*txq
)
5196 int tx_desc
= txq
->next_desc_to_proc
;
5198 txq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(txq
, tx_desc
);
5199 return txq
->descs
+ tx_desc
;
5202 /* Update HW with number of aggregated Tx descriptors to be sent
5204 * Called only from mvpp2_tx(), so migration is disabled, using
5205 * smp_processor_id() is OK.
5207 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port
*port
, int pending
)
5209 /* aggregated access - relevant TXQ number is written in TX desc */
5210 mvpp2_percpu_write(port
->priv
, smp_processor_id(),
5211 MVPP2_AGGR_TXQ_UPDATE_REG
, pending
);
5215 /* Check if there are enough free descriptors in aggregated txq.
5216 * If not, update the number of occupied descriptors and repeat the check.
5218 * Called only from mvpp2_tx(), so migration is disabled, using
5219 * smp_processor_id() is OK.
5221 static int mvpp2_aggr_desc_num_check(struct mvpp2
*priv
,
5222 struct mvpp2_tx_queue
*aggr_txq
, int num
)
5224 if ((aggr_txq
->count
+ num
) > MVPP2_AGGR_TXQ_SIZE
) {
5225 /* Update number of occupied aggregated Tx descriptors */
5226 int cpu
= smp_processor_id();
5227 u32 val
= mvpp2_read(priv
, MVPP2_AGGR_TXQ_STATUS_REG(cpu
));
5229 aggr_txq
->count
= val
& MVPP2_AGGR_TXQ_PENDING_MASK
;
5232 if ((aggr_txq
->count
+ num
) > MVPP2_AGGR_TXQ_SIZE
)
5238 /* Reserved Tx descriptors allocation request
5240 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
5241 * only by mvpp2_tx(), so migration is disabled, using
5242 * smp_processor_id() is OK.
5244 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2
*priv
,
5245 struct mvpp2_tx_queue
*txq
, int num
)
5248 int cpu
= smp_processor_id();
5250 val
= (txq
->id
<< MVPP2_TXQ_RSVD_REQ_Q_OFFSET
) | num
;
5251 mvpp2_percpu_write(priv
, cpu
, MVPP2_TXQ_RSVD_REQ_REG
, val
);
5253 val
= mvpp2_percpu_read(priv
, cpu
, MVPP2_TXQ_RSVD_RSLT_REG
);
5255 return val
& MVPP2_TXQ_RSVD_RSLT_MASK
;
5258 /* Check if there are enough reserved descriptors for transmission.
5259 * If not, request chunk of reserved descriptors and check again.
5261 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2
*priv
,
5262 struct mvpp2_tx_queue
*txq
,
5263 struct mvpp2_txq_pcpu
*txq_pcpu
,
5266 int req
, cpu
, desc_count
;
5268 if (txq_pcpu
->reserved_num
>= num
)
5271 /* Not enough descriptors reserved! Update the reserved descriptor
5272 * count and check again.
5276 /* Compute total of used descriptors */
5277 for_each_present_cpu(cpu
) {
5278 struct mvpp2_txq_pcpu
*txq_pcpu_aux
;
5280 txq_pcpu_aux
= per_cpu_ptr(txq
->pcpu
, cpu
);
5281 desc_count
+= txq_pcpu_aux
->count
;
5282 desc_count
+= txq_pcpu_aux
->reserved_num
;
5285 req
= max(MVPP2_CPU_DESC_CHUNK
, num
- txq_pcpu
->reserved_num
);
5289 (txq
->size
- (num_present_cpus() * MVPP2_CPU_DESC_CHUNK
)))
5292 txq_pcpu
->reserved_num
+= mvpp2_txq_alloc_reserved_desc(priv
, txq
, req
);
5294 /* OK, the descriptor cound has been updated: check again. */
5295 if (txq_pcpu
->reserved_num
< num
)
5300 /* Release the last allocated Tx descriptor. Useful to handle DMA
5301 * mapping failures in the Tx path.
5303 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue
*txq
)
5305 if (txq
->next_desc_to_proc
== 0)
5306 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
5308 txq
->next_desc_to_proc
--;
5311 /* Set Tx descriptors fields relevant for CSUM calculation */
5312 static u32
mvpp2_txq_desc_csum(int l3_offs
, int l3_proto
,
5313 int ip_hdr_len
, int l4_proto
)
5317 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
5318 * G_L4_chk, L4_type required only for checksum calculation
5320 command
= (l3_offs
<< MVPP2_TXD_L3_OFF_SHIFT
);
5321 command
|= (ip_hdr_len
<< MVPP2_TXD_IP_HLEN_SHIFT
);
5322 command
|= MVPP2_TXD_IP_CSUM_DISABLE
;
5324 if (l3_proto
== swab16(ETH_P_IP
)) {
5325 command
&= ~MVPP2_TXD_IP_CSUM_DISABLE
; /* enable IPv4 csum */
5326 command
&= ~MVPP2_TXD_L3_IP6
; /* enable IPv4 */
5328 command
|= MVPP2_TXD_L3_IP6
; /* enable IPv6 */
5331 if (l4_proto
== IPPROTO_TCP
) {
5332 command
&= ~MVPP2_TXD_L4_UDP
; /* enable TCP */
5333 command
&= ~MVPP2_TXD_L4_CSUM_FRAG
; /* generate L4 csum */
5334 } else if (l4_proto
== IPPROTO_UDP
) {
5335 command
|= MVPP2_TXD_L4_UDP
; /* enable UDP */
5336 command
&= ~MVPP2_TXD_L4_CSUM_FRAG
; /* generate L4 csum */
5338 command
|= MVPP2_TXD_L4_CSUM_NOT
;
5344 /* Get number of sent descriptors and decrement counter.
5345 * The number of sent descriptors is returned.
5348 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
5349 * (migration disabled) and from the TX completion tasklet (migration
5350 * disabled) so using smp_processor_id() is OK.
5352 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port
*port
,
5353 struct mvpp2_tx_queue
*txq
)
5357 /* Reading status reg resets transmitted descriptor counter */
5358 val
= mvpp2_percpu_read(port
->priv
, smp_processor_id(),
5359 MVPP2_TXQ_SENT_REG(txq
->id
));
5361 return (val
& MVPP2_TRANSMITTED_COUNT_MASK
) >>
5362 MVPP2_TRANSMITTED_COUNT_OFFSET
;
5365 /* Called through on_each_cpu(), so runs on all CPUs, with migration
5366 * disabled, therefore using smp_processor_id() is OK.
5368 static void mvpp2_txq_sent_counter_clear(void *arg
)
5370 struct mvpp2_port
*port
= arg
;
5373 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
5374 int id
= port
->txqs
[queue
]->id
;
5376 mvpp2_percpu_read(port
->priv
, smp_processor_id(),
5377 MVPP2_TXQ_SENT_REG(id
));
5381 /* Set max sizes for Tx queues */
5382 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port
*port
)
5385 int txq
, tx_port_num
;
5387 mtu
= port
->pkt_size
* 8;
5388 if (mtu
> MVPP2_TXP_MTU_MAX
)
5389 mtu
= MVPP2_TXP_MTU_MAX
;
5391 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
5394 /* Indirect access to registers */
5395 tx_port_num
= mvpp2_egress_port(port
);
5396 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
5399 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
);
5400 val
&= ~MVPP2_TXP_MTU_MAX
;
5402 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
, val
);
5404 /* TXP token size and all TXQs token size must be larger that MTU */
5405 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
);
5406 size
= val
& MVPP2_TXP_TOKEN_SIZE_MAX
;
5409 val
&= ~MVPP2_TXP_TOKEN_SIZE_MAX
;
5411 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
5414 for (txq
= 0; txq
< port
->ntxqs
; txq
++) {
5415 val
= mvpp2_read(port
->priv
,
5416 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
));
5417 size
= val
& MVPP2_TXQ_TOKEN_SIZE_MAX
;
5421 val
&= ~MVPP2_TXQ_TOKEN_SIZE_MAX
;
5423 mvpp2_write(port
->priv
,
5424 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
),
5430 /* Set the number of packets that will be received before Rx interrupt
5431 * will be generated by HW.
5433 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port
*port
,
5434 struct mvpp2_rx_queue
*rxq
)
5436 int cpu
= get_cpu();
5438 if (rxq
->pkts_coal
> MVPP2_OCCUPIED_THRESH_MASK
)
5439 rxq
->pkts_coal
= MVPP2_OCCUPIED_THRESH_MASK
;
5441 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
5442 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_THRESH_REG
,
5448 /* For some reason in the LSP this is done on each CPU. Why ? */
5449 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port
*port
,
5450 struct mvpp2_tx_queue
*txq
)
5452 int cpu
= get_cpu();
5455 if (txq
->done_pkts_coal
> MVPP2_TXQ_THRESH_MASK
)
5456 txq
->done_pkts_coal
= MVPP2_TXQ_THRESH_MASK
;
5458 val
= (txq
->done_pkts_coal
<< MVPP2_TXQ_THRESH_OFFSET
);
5459 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_NUM_REG
, txq
->id
);
5460 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_THRESH_REG
, val
);
5465 static u32
mvpp2_usec_to_cycles(u32 usec
, unsigned long clk_hz
)
5467 u64 tmp
= (u64
)clk_hz
* usec
;
5469 do_div(tmp
, USEC_PER_SEC
);
5471 return tmp
> U32_MAX
? U32_MAX
: tmp
;
5474 static u32
mvpp2_cycles_to_usec(u32 cycles
, unsigned long clk_hz
)
5476 u64 tmp
= (u64
)cycles
* USEC_PER_SEC
;
5478 do_div(tmp
, clk_hz
);
5480 return tmp
> U32_MAX
? U32_MAX
: tmp
;
5483 /* Set the time delay in usec before Rx interrupt */
5484 static void mvpp2_rx_time_coal_set(struct mvpp2_port
*port
,
5485 struct mvpp2_rx_queue
*rxq
)
5487 unsigned long freq
= port
->priv
->tclk
;
5488 u32 val
= mvpp2_usec_to_cycles(rxq
->time_coal
, freq
);
5490 if (val
> MVPP2_MAX_ISR_RX_THRESHOLD
) {
5492 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD
, freq
);
5494 /* re-evaluate to get actual register value */
5495 val
= mvpp2_usec_to_cycles(rxq
->time_coal
, freq
);
5498 mvpp2_write(port
->priv
, MVPP2_ISR_RX_THRESHOLD_REG(rxq
->id
), val
);
5501 static void mvpp2_tx_time_coal_set(struct mvpp2_port
*port
)
5503 unsigned long freq
= port
->priv
->tclk
;
5504 u32 val
= mvpp2_usec_to_cycles(port
->tx_time_coal
, freq
);
5506 if (val
> MVPP2_MAX_ISR_TX_THRESHOLD
) {
5507 port
->tx_time_coal
=
5508 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD
, freq
);
5510 /* re-evaluate to get actual register value */
5511 val
= mvpp2_usec_to_cycles(port
->tx_time_coal
, freq
);
5514 mvpp2_write(port
->priv
, MVPP2_ISR_TX_THRESHOLD_REG(port
->id
), val
);
5517 /* Free Tx queue skbuffs */
5518 static void mvpp2_txq_bufs_free(struct mvpp2_port
*port
,
5519 struct mvpp2_tx_queue
*txq
,
5520 struct mvpp2_txq_pcpu
*txq_pcpu
, int num
)
5524 for (i
= 0; i
< num
; i
++) {
5525 struct mvpp2_txq_pcpu_buf
*tx_buf
=
5526 txq_pcpu
->buffs
+ txq_pcpu
->txq_get_index
;
5528 if (!IS_TSO_HEADER(txq_pcpu
, tx_buf
->dma
))
5529 dma_unmap_single(port
->dev
->dev
.parent
, tx_buf
->dma
,
5530 tx_buf
->size
, DMA_TO_DEVICE
);
5532 dev_kfree_skb_any(tx_buf
->skb
);
5534 mvpp2_txq_inc_get(txq_pcpu
);
5538 static inline struct mvpp2_rx_queue
*mvpp2_get_rx_queue(struct mvpp2_port
*port
,
5541 int queue
= fls(cause
) - 1;
5543 return port
->rxqs
[queue
];
5546 static inline struct mvpp2_tx_queue
*mvpp2_get_tx_queue(struct mvpp2_port
*port
,
5549 int queue
= fls(cause
) - 1;
5551 return port
->txqs
[queue
];
5554 /* Handle end of transmission */
5555 static void mvpp2_txq_done(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
,
5556 struct mvpp2_txq_pcpu
*txq_pcpu
)
5558 struct netdev_queue
*nq
= netdev_get_tx_queue(port
->dev
, txq
->log_id
);
5561 if (txq_pcpu
->cpu
!= smp_processor_id())
5562 netdev_err(port
->dev
, "wrong cpu on the end of Tx processing\n");
5564 tx_done
= mvpp2_txq_sent_desc_proc(port
, txq
);
5567 mvpp2_txq_bufs_free(port
, txq
, txq_pcpu
, tx_done
);
5569 txq_pcpu
->count
-= tx_done
;
5571 if (netif_tx_queue_stopped(nq
))
5572 if (txq_pcpu
->count
<= txq_pcpu
->wake_threshold
)
5573 netif_tx_wake_queue(nq
);
5576 static unsigned int mvpp2_tx_done(struct mvpp2_port
*port
, u32 cause
,
5579 struct mvpp2_tx_queue
*txq
;
5580 struct mvpp2_txq_pcpu
*txq_pcpu
;
5581 unsigned int tx_todo
= 0;
5584 txq
= mvpp2_get_tx_queue(port
, cause
);
5588 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
5590 if (txq_pcpu
->count
) {
5591 mvpp2_txq_done(port
, txq
, txq_pcpu
);
5592 tx_todo
+= txq_pcpu
->count
;
5595 cause
&= ~(1 << txq
->log_id
);
5600 /* Rx/Tx queue initialization/cleanup methods */
5602 /* Allocate and initialize descriptors for aggr TXQ */
5603 static int mvpp2_aggr_txq_init(struct platform_device
*pdev
,
5604 struct mvpp2_tx_queue
*aggr_txq
, int cpu
,
5609 /* Allocate memory for TX descriptors */
5610 aggr_txq
->descs
= dma_alloc_coherent(&pdev
->dev
,
5611 MVPP2_AGGR_TXQ_SIZE
* MVPP2_DESC_ALIGNED_SIZE
,
5612 &aggr_txq
->descs_dma
, GFP_KERNEL
);
5613 if (!aggr_txq
->descs
)
5616 aggr_txq
->last_desc
= MVPP2_AGGR_TXQ_SIZE
- 1;
5618 /* Aggr TXQ no reset WA */
5619 aggr_txq
->next_desc_to_proc
= mvpp2_read(priv
,
5620 MVPP2_AGGR_TXQ_INDEX_REG(cpu
));
5622 /* Set Tx descriptors queue starting address indirect
5625 if (priv
->hw_version
== MVPP21
)
5626 txq_dma
= aggr_txq
->descs_dma
;
5628 txq_dma
= aggr_txq
->descs_dma
>>
5629 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS
;
5631 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu
), txq_dma
);
5632 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu
),
5633 MVPP2_AGGR_TXQ_SIZE
);
5638 /* Create a specified Rx queue */
5639 static int mvpp2_rxq_init(struct mvpp2_port
*port
,
5640 struct mvpp2_rx_queue
*rxq
)
5646 rxq
->size
= port
->rx_ring_size
;
5648 /* Allocate memory for RX descriptors */
5649 rxq
->descs
= dma_alloc_coherent(port
->dev
->dev
.parent
,
5650 rxq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
5651 &rxq
->descs_dma
, GFP_KERNEL
);
5655 rxq
->last_desc
= rxq
->size
- 1;
5657 /* Zero occupied and non-occupied counters - direct access */
5658 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
5660 /* Set Rx descriptors queue starting address - indirect access */
5662 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
5663 if (port
->priv
->hw_version
== MVPP21
)
5664 rxq_dma
= rxq
->descs_dma
;
5666 rxq_dma
= rxq
->descs_dma
>> MVPP22_DESC_ADDR_OFFS
;
5667 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_DESC_ADDR_REG
, rxq_dma
);
5668 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_DESC_SIZE_REG
, rxq
->size
);
5669 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_INDEX_REG
, 0);
5673 mvpp2_rxq_offset_set(port
, rxq
->id
, NET_SKB_PAD
);
5675 /* Set coalescing pkts and time */
5676 mvpp2_rx_pkts_coal_set(port
, rxq
);
5677 mvpp2_rx_time_coal_set(port
, rxq
);
5679 /* Add number of descriptors ready for receiving packets */
5680 mvpp2_rxq_status_update(port
, rxq
->id
, 0, rxq
->size
);
5685 /* Push packets received by the RXQ to BM pool */
5686 static void mvpp2_rxq_drop_pkts(struct mvpp2_port
*port
,
5687 struct mvpp2_rx_queue
*rxq
)
5691 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
5695 for (i
= 0; i
< rx_received
; i
++) {
5696 struct mvpp2_rx_desc
*rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
5697 u32 status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
5700 pool
= (status
& MVPP2_RXD_BM_POOL_ID_MASK
) >>
5701 MVPP2_RXD_BM_POOL_ID_OFFS
;
5703 mvpp2_bm_pool_put(port
, pool
,
5704 mvpp2_rxdesc_dma_addr_get(port
, rx_desc
),
5705 mvpp2_rxdesc_cookie_get(port
, rx_desc
));
5707 mvpp2_rxq_status_update(port
, rxq
->id
, rx_received
, rx_received
);
5710 /* Cleanup Rx queue */
5711 static void mvpp2_rxq_deinit(struct mvpp2_port
*port
,
5712 struct mvpp2_rx_queue
*rxq
)
5716 mvpp2_rxq_drop_pkts(port
, rxq
);
5719 dma_free_coherent(port
->dev
->dev
.parent
,
5720 rxq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
5726 rxq
->next_desc_to_proc
= 0;
5729 /* Clear Rx descriptors queue starting address and size;
5730 * free descriptor number
5732 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
5734 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
5735 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_DESC_ADDR_REG
, 0);
5736 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_RXQ_DESC_SIZE_REG
, 0);
5740 /* Create and initialize a Tx queue */
5741 static int mvpp2_txq_init(struct mvpp2_port
*port
,
5742 struct mvpp2_tx_queue
*txq
)
5745 int cpu
, desc
, desc_per_txq
, tx_port_num
;
5746 struct mvpp2_txq_pcpu
*txq_pcpu
;
5748 txq
->size
= port
->tx_ring_size
;
5750 /* Allocate memory for Tx descriptors */
5751 txq
->descs
= dma_alloc_coherent(port
->dev
->dev
.parent
,
5752 txq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
5753 &txq
->descs_dma
, GFP_KERNEL
);
5757 txq
->last_desc
= txq
->size
- 1;
5759 /* Set Tx descriptors queue starting address - indirect access */
5761 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_NUM_REG
, txq
->id
);
5762 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_DESC_ADDR_REG
,
5764 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_DESC_SIZE_REG
,
5765 txq
->size
& MVPP2_TXQ_DESC_SIZE_MASK
);
5766 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_INDEX_REG
, 0);
5767 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_RSVD_CLR_REG
,
5768 txq
->id
<< MVPP2_TXQ_RSVD_CLR_OFFSET
);
5769 val
= mvpp2_percpu_read(port
->priv
, cpu
, MVPP2_TXQ_PENDING_REG
);
5770 val
&= ~MVPP2_TXQ_PENDING_MASK
;
5771 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_PENDING_REG
, val
);
5773 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
5774 * for each existing TXQ.
5775 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
5776 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
5779 desc
= (port
->id
* MVPP2_MAX_TXQ
* desc_per_txq
) +
5780 (txq
->log_id
* desc_per_txq
);
5782 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_PREF_BUF_REG
,
5783 MVPP2_PREF_BUF_PTR(desc
) | MVPP2_PREF_BUF_SIZE_16
|
5784 MVPP2_PREF_BUF_THRESH(desc_per_txq
/ 2));
5787 /* WRR / EJP configuration - indirect access */
5788 tx_port_num
= mvpp2_egress_port(port
);
5789 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
5791 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
));
5792 val
&= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK
;
5793 val
|= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
5794 val
|= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK
;
5795 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
), val
);
5797 val
= MVPP2_TXQ_TOKEN_SIZE_MAX
;
5798 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
->log_id
),
5801 for_each_present_cpu(cpu
) {
5802 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
5803 txq_pcpu
->size
= txq
->size
;
5804 txq_pcpu
->buffs
= kmalloc_array(txq_pcpu
->size
,
5805 sizeof(*txq_pcpu
->buffs
),
5807 if (!txq_pcpu
->buffs
)
5810 txq_pcpu
->count
= 0;
5811 txq_pcpu
->reserved_num
= 0;
5812 txq_pcpu
->txq_put_index
= 0;
5813 txq_pcpu
->txq_get_index
= 0;
5815 txq_pcpu
->stop_threshold
= txq
->size
- MVPP2_MAX_SKB_DESCS
;
5816 txq_pcpu
->wake_threshold
= txq_pcpu
->stop_threshold
/ 2;
5818 txq_pcpu
->tso_headers
=
5819 dma_alloc_coherent(port
->dev
->dev
.parent
,
5820 txq_pcpu
->size
* TSO_HEADER_SIZE
,
5821 &txq_pcpu
->tso_headers_dma
,
5823 if (!txq_pcpu
->tso_headers
)
5829 for_each_present_cpu(cpu
) {
5830 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
5831 kfree(txq_pcpu
->buffs
);
5833 dma_free_coherent(port
->dev
->dev
.parent
,
5834 txq_pcpu
->size
* TSO_HEADER_SIZE
,
5835 txq_pcpu
->tso_headers
,
5836 txq_pcpu
->tso_headers_dma
);
5839 dma_free_coherent(port
->dev
->dev
.parent
,
5840 txq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
5841 txq
->descs
, txq
->descs_dma
);
5846 /* Free allocated TXQ resources */
5847 static void mvpp2_txq_deinit(struct mvpp2_port
*port
,
5848 struct mvpp2_tx_queue
*txq
)
5850 struct mvpp2_txq_pcpu
*txq_pcpu
;
5853 for_each_present_cpu(cpu
) {
5854 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
5855 kfree(txq_pcpu
->buffs
);
5857 dma_free_coherent(port
->dev
->dev
.parent
,
5858 txq_pcpu
->size
* TSO_HEADER_SIZE
,
5859 txq_pcpu
->tso_headers
,
5860 txq_pcpu
->tso_headers_dma
);
5864 dma_free_coherent(port
->dev
->dev
.parent
,
5865 txq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
5866 txq
->descs
, txq
->descs_dma
);
5870 txq
->next_desc_to_proc
= 0;
5873 /* Set minimum bandwidth for disabled TXQs */
5874 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq
->id
), 0);
5876 /* Set Tx descriptors queue starting address and size */
5878 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_NUM_REG
, txq
->id
);
5879 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_DESC_ADDR_REG
, 0);
5880 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_DESC_SIZE_REG
, 0);
5884 /* Cleanup Tx ports */
5885 static void mvpp2_txq_clean(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
)
5887 struct mvpp2_txq_pcpu
*txq_pcpu
;
5888 int delay
, pending
, cpu
;
5892 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_NUM_REG
, txq
->id
);
5893 val
= mvpp2_percpu_read(port
->priv
, cpu
, MVPP2_TXQ_PREF_BUF_REG
);
5894 val
|= MVPP2_TXQ_DRAIN_EN_MASK
;
5895 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_PREF_BUF_REG
, val
);
5897 /* The napi queue has been stopped so wait for all packets
5898 * to be transmitted.
5902 if (delay
>= MVPP2_TX_PENDING_TIMEOUT_MSEC
) {
5903 netdev_warn(port
->dev
,
5904 "port %d: cleaning queue %d timed out\n",
5905 port
->id
, txq
->log_id
);
5911 pending
= mvpp2_percpu_read(port
->priv
, cpu
,
5912 MVPP2_TXQ_PENDING_REG
);
5913 pending
&= MVPP2_TXQ_PENDING_MASK
;
5916 val
&= ~MVPP2_TXQ_DRAIN_EN_MASK
;
5917 mvpp2_percpu_write(port
->priv
, cpu
, MVPP2_TXQ_PREF_BUF_REG
, val
);
5920 for_each_present_cpu(cpu
) {
5921 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
5923 /* Release all packets */
5924 mvpp2_txq_bufs_free(port
, txq
, txq_pcpu
, txq_pcpu
->count
);
5927 txq_pcpu
->count
= 0;
5928 txq_pcpu
->txq_put_index
= 0;
5929 txq_pcpu
->txq_get_index
= 0;
5933 /* Cleanup all Tx queues */
5934 static void mvpp2_cleanup_txqs(struct mvpp2_port
*port
)
5936 struct mvpp2_tx_queue
*txq
;
5940 val
= mvpp2_read(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
);
5942 /* Reset Tx ports and delete Tx queues */
5943 val
|= MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
5944 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
5946 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
5947 txq
= port
->txqs
[queue
];
5948 mvpp2_txq_clean(port
, txq
);
5949 mvpp2_txq_deinit(port
, txq
);
5952 on_each_cpu(mvpp2_txq_sent_counter_clear
, port
, 1);
5954 val
&= ~MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
5955 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
5958 /* Cleanup all Rx queues */
5959 static void mvpp2_cleanup_rxqs(struct mvpp2_port
*port
)
5963 for (queue
= 0; queue
< port
->nrxqs
; queue
++)
5964 mvpp2_rxq_deinit(port
, port
->rxqs
[queue
]);
5967 /* Init all Rx queues for port */
5968 static int mvpp2_setup_rxqs(struct mvpp2_port
*port
)
5972 for (queue
= 0; queue
< port
->nrxqs
; queue
++) {
5973 err
= mvpp2_rxq_init(port
, port
->rxqs
[queue
]);
5980 mvpp2_cleanup_rxqs(port
);
5984 /* Init all tx queues for port */
5985 static int mvpp2_setup_txqs(struct mvpp2_port
*port
)
5987 struct mvpp2_tx_queue
*txq
;
5990 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
5991 txq
= port
->txqs
[queue
];
5992 err
= mvpp2_txq_init(port
, txq
);
5997 if (port
->has_tx_irqs
) {
5998 mvpp2_tx_time_coal_set(port
);
5999 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
6000 txq
= port
->txqs
[queue
];
6001 mvpp2_tx_pkts_coal_set(port
, txq
);
6005 on_each_cpu(mvpp2_txq_sent_counter_clear
, port
, 1);
6009 mvpp2_cleanup_txqs(port
);
6013 /* The callback for per-port interrupt */
6014 static irqreturn_t
mvpp2_isr(int irq
, void *dev_id
)
6016 struct mvpp2_queue_vector
*qv
= dev_id
;
6018 mvpp2_qvec_interrupt_disable(qv
);
6020 napi_schedule(&qv
->napi
);
6025 /* Per-port interrupt for link status changes */
6026 static irqreturn_t
mvpp2_link_status_isr(int irq
, void *dev_id
)
6028 struct mvpp2_port
*port
= (struct mvpp2_port
*)dev_id
;
6029 struct net_device
*dev
= port
->dev
;
6030 bool event
= false, link
= false;
6033 mvpp22_gop_mask_irq(port
);
6035 if (port
->gop_id
== 0 &&
6036 port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
) {
6037 val
= readl(port
->base
+ MVPP22_XLG_INT_STAT
);
6038 if (val
& MVPP22_XLG_INT_STAT_LINK
) {
6040 val
= readl(port
->base
+ MVPP22_XLG_STATUS
);
6041 if (val
& MVPP22_XLG_STATUS_LINK_UP
)
6044 } else if (phy_interface_mode_is_rgmii(port
->phy_interface
) ||
6045 port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
6046 val
= readl(port
->base
+ MVPP22_GMAC_INT_STAT
);
6047 if (val
& MVPP22_GMAC_INT_STAT_LINK
) {
6049 val
= readl(port
->base
+ MVPP2_GMAC_STATUS0
);
6050 if (val
& MVPP2_GMAC_STATUS0_LINK_UP
)
6055 if (!netif_running(dev
) || !event
)
6059 mvpp2_interrupts_enable(port
);
6061 mvpp2_egress_enable(port
);
6062 mvpp2_ingress_enable(port
);
6063 netif_carrier_on(dev
);
6064 netif_tx_wake_all_queues(dev
);
6066 netif_tx_stop_all_queues(dev
);
6067 netif_carrier_off(dev
);
6068 mvpp2_ingress_disable(port
);
6069 mvpp2_egress_disable(port
);
6071 mvpp2_interrupts_disable(port
);
6075 mvpp22_gop_unmask_irq(port
);
6079 static void mvpp2_gmac_set_autoneg(struct mvpp2_port
*port
,
6080 struct phy_device
*phydev
)
6084 if (port
->phy_interface
!= PHY_INTERFACE_MODE_RGMII
&&
6085 port
->phy_interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
6086 port
->phy_interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
6087 port
->phy_interface
!= PHY_INTERFACE_MODE_RGMII_TXID
&&
6088 port
->phy_interface
!= PHY_INTERFACE_MODE_SGMII
)
6091 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
6092 val
&= ~(MVPP2_GMAC_CONFIG_MII_SPEED
|
6093 MVPP2_GMAC_CONFIG_GMII_SPEED
|
6094 MVPP2_GMAC_CONFIG_FULL_DUPLEX
|
6095 MVPP2_GMAC_AN_SPEED_EN
|
6096 MVPP2_GMAC_AN_DUPLEX_EN
);
6099 val
|= MVPP2_GMAC_CONFIG_FULL_DUPLEX
;
6101 if (phydev
->speed
== SPEED_1000
)
6102 val
|= MVPP2_GMAC_CONFIG_GMII_SPEED
;
6103 else if (phydev
->speed
== SPEED_100
)
6104 val
|= MVPP2_GMAC_CONFIG_MII_SPEED
;
6106 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
6110 static void mvpp2_link_event(struct net_device
*dev
)
6112 struct mvpp2_port
*port
= netdev_priv(dev
);
6113 struct phy_device
*phydev
= dev
->phydev
;
6114 bool link_reconfigured
= false;
6118 if (port
->phy_interface
!= phydev
->interface
&& port
->comphy
) {
6119 /* disable current port for reconfiguration */
6120 mvpp2_interrupts_disable(port
);
6121 netif_carrier_off(port
->dev
);
6122 mvpp2_port_disable(port
);
6123 phy_power_off(port
->comphy
);
6125 /* comphy reconfiguration */
6126 port
->phy_interface
= phydev
->interface
;
6127 mvpp22_comphy_init(port
);
6129 /* gop/mac reconfiguration */
6130 mvpp22_gop_init(port
);
6131 mvpp2_port_mii_set(port
);
6133 link_reconfigured
= true;
6136 if ((port
->speed
!= phydev
->speed
) ||
6137 (port
->duplex
!= phydev
->duplex
)) {
6138 mvpp2_gmac_set_autoneg(port
, phydev
);
6140 port
->duplex
= phydev
->duplex
;
6141 port
->speed
= phydev
->speed
;
6145 if (phydev
->link
!= port
->link
|| link_reconfigured
) {
6146 port
->link
= phydev
->link
;
6149 if (port
->phy_interface
== PHY_INTERFACE_MODE_RGMII
||
6150 port
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
||
6151 port
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
||
6152 port
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
||
6153 port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
) {
6154 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
6155 val
|= (MVPP2_GMAC_FORCE_LINK_PASS
|
6156 MVPP2_GMAC_FORCE_LINK_DOWN
);
6157 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
6160 mvpp2_interrupts_enable(port
);
6161 mvpp2_port_enable(port
);
6163 mvpp2_egress_enable(port
);
6164 mvpp2_ingress_enable(port
);
6165 netif_carrier_on(dev
);
6166 netif_tx_wake_all_queues(dev
);
6171 netif_tx_stop_all_queues(dev
);
6172 netif_carrier_off(dev
);
6173 mvpp2_ingress_disable(port
);
6174 mvpp2_egress_disable(port
);
6176 mvpp2_port_disable(port
);
6177 mvpp2_interrupts_disable(port
);
6180 phy_print_status(phydev
);
6184 static void mvpp2_timer_set(struct mvpp2_port_pcpu
*port_pcpu
)
6188 if (!port_pcpu
->timer_scheduled
) {
6189 port_pcpu
->timer_scheduled
= true;
6190 interval
= MVPP2_TXDONE_HRTIMER_PERIOD_NS
;
6191 hrtimer_start(&port_pcpu
->tx_done_timer
, interval
,
6192 HRTIMER_MODE_REL_PINNED
);
6196 static void mvpp2_tx_proc_cb(unsigned long data
)
6198 struct net_device
*dev
= (struct net_device
*)data
;
6199 struct mvpp2_port
*port
= netdev_priv(dev
);
6200 struct mvpp2_port_pcpu
*port_pcpu
= this_cpu_ptr(port
->pcpu
);
6201 unsigned int tx_todo
, cause
;
6203 if (!netif_running(dev
))
6205 port_pcpu
->timer_scheduled
= false;
6207 /* Process all the Tx queues */
6208 cause
= (1 << port
->ntxqs
) - 1;
6209 tx_todo
= mvpp2_tx_done(port
, cause
, smp_processor_id());
6211 /* Set the timer in case not all the packets were processed */
6213 mvpp2_timer_set(port_pcpu
);
6216 static enum hrtimer_restart
mvpp2_hr_timer_cb(struct hrtimer
*timer
)
6218 struct mvpp2_port_pcpu
*port_pcpu
= container_of(timer
,
6219 struct mvpp2_port_pcpu
,
6222 tasklet_schedule(&port_pcpu
->tx_done_tasklet
);
6224 return HRTIMER_NORESTART
;
6227 /* Main RX/TX processing routines */
6229 /* Display more error info */
6230 static void mvpp2_rx_error(struct mvpp2_port
*port
,
6231 struct mvpp2_rx_desc
*rx_desc
)
6233 u32 status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
6234 size_t sz
= mvpp2_rxdesc_size_get(port
, rx_desc
);
6236 switch (status
& MVPP2_RXD_ERR_CODE_MASK
) {
6237 case MVPP2_RXD_ERR_CRC
:
6238 netdev_err(port
->dev
, "bad rx status %08x (crc error), size=%zu\n",
6241 case MVPP2_RXD_ERR_OVERRUN
:
6242 netdev_err(port
->dev
, "bad rx status %08x (overrun error), size=%zu\n",
6245 case MVPP2_RXD_ERR_RESOURCE
:
6246 netdev_err(port
->dev
, "bad rx status %08x (resource error), size=%zu\n",
6252 /* Handle RX checksum offload */
6253 static void mvpp2_rx_csum(struct mvpp2_port
*port
, u32 status
,
6254 struct sk_buff
*skb
)
6256 if (((status
& MVPP2_RXD_L3_IP4
) &&
6257 !(status
& MVPP2_RXD_IP4_HEADER_ERR
)) ||
6258 (status
& MVPP2_RXD_L3_IP6
))
6259 if (((status
& MVPP2_RXD_L4_UDP
) ||
6260 (status
& MVPP2_RXD_L4_TCP
)) &&
6261 (status
& MVPP2_RXD_L4_CSUM_OK
)) {
6263 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6267 skb
->ip_summed
= CHECKSUM_NONE
;
6270 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
6271 static int mvpp2_rx_refill(struct mvpp2_port
*port
,
6272 struct mvpp2_bm_pool
*bm_pool
, int pool
)
6274 dma_addr_t dma_addr
;
6275 phys_addr_t phys_addr
;
6278 /* No recycle or too many buffers are in use, so allocate a new skb */
6279 buf
= mvpp2_buf_alloc(port
, bm_pool
, &dma_addr
, &phys_addr
,
6284 mvpp2_bm_pool_put(port
, pool
, dma_addr
, phys_addr
);
6289 /* Handle tx checksum */
6290 static u32
mvpp2_skb_tx_csum(struct mvpp2_port
*port
, struct sk_buff
*skb
)
6292 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6296 if (skb
->protocol
== htons(ETH_P_IP
)) {
6297 struct iphdr
*ip4h
= ip_hdr(skb
);
6299 /* Calculate IPv4 checksum and L4 checksum */
6300 ip_hdr_len
= ip4h
->ihl
;
6301 l4_proto
= ip4h
->protocol
;
6302 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
6303 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
6305 /* Read l4_protocol from one of IPv6 extra headers */
6306 if (skb_network_header_len(skb
) > 0)
6307 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
6308 l4_proto
= ip6h
->nexthdr
;
6310 return MVPP2_TXD_L4_CSUM_NOT
;
6313 return mvpp2_txq_desc_csum(skb_network_offset(skb
),
6314 skb
->protocol
, ip_hdr_len
, l4_proto
);
6317 return MVPP2_TXD_L4_CSUM_NOT
| MVPP2_TXD_IP_CSUM_DISABLE
;
6320 /* Main rx processing */
6321 static int mvpp2_rx(struct mvpp2_port
*port
, struct napi_struct
*napi
,
6322 int rx_todo
, struct mvpp2_rx_queue
*rxq
)
6324 struct net_device
*dev
= port
->dev
;
6330 /* Get number of received packets and clamp the to-do */
6331 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
6332 if (rx_todo
> rx_received
)
6333 rx_todo
= rx_received
;
6335 while (rx_done
< rx_todo
) {
6336 struct mvpp2_rx_desc
*rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
6337 struct mvpp2_bm_pool
*bm_pool
;
6338 struct sk_buff
*skb
;
6339 unsigned int frag_size
;
6340 dma_addr_t dma_addr
;
6341 phys_addr_t phys_addr
;
6343 int pool
, rx_bytes
, err
;
6347 rx_status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
6348 rx_bytes
= mvpp2_rxdesc_size_get(port
, rx_desc
);
6349 rx_bytes
-= MVPP2_MH_SIZE
;
6350 dma_addr
= mvpp2_rxdesc_dma_addr_get(port
, rx_desc
);
6351 phys_addr
= mvpp2_rxdesc_cookie_get(port
, rx_desc
);
6352 data
= (void *)phys_to_virt(phys_addr
);
6354 pool
= (rx_status
& MVPP2_RXD_BM_POOL_ID_MASK
) >>
6355 MVPP2_RXD_BM_POOL_ID_OFFS
;
6356 bm_pool
= &port
->priv
->bm_pools
[pool
];
6358 /* In case of an error, release the requested buffer pointer
6359 * to the Buffer Manager. This request process is controlled
6360 * by the hardware, and the information about the buffer is
6361 * comprised by the RX descriptor.
6363 if (rx_status
& MVPP2_RXD_ERR_SUMMARY
) {
6365 dev
->stats
.rx_errors
++;
6366 mvpp2_rx_error(port
, rx_desc
);
6367 /* Return the buffer to the pool */
6368 mvpp2_bm_pool_put(port
, pool
, dma_addr
, phys_addr
);
6372 if (bm_pool
->frag_size
> PAGE_SIZE
)
6375 frag_size
= bm_pool
->frag_size
;
6377 skb
= build_skb(data
, frag_size
);
6379 netdev_warn(port
->dev
, "skb build failed\n");
6380 goto err_drop_frame
;
6383 err
= mvpp2_rx_refill(port
, bm_pool
, pool
);
6385 netdev_err(port
->dev
, "failed to refill BM pools\n");
6386 goto err_drop_frame
;
6389 dma_unmap_single(dev
->dev
.parent
, dma_addr
,
6390 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
6393 rcvd_bytes
+= rx_bytes
;
6395 skb_reserve(skb
, MVPP2_MH_SIZE
+ NET_SKB_PAD
);
6396 skb_put(skb
, rx_bytes
);
6397 skb
->protocol
= eth_type_trans(skb
, dev
);
6398 mvpp2_rx_csum(port
, rx_status
, skb
);
6400 napi_gro_receive(napi
, skb
);
6404 struct mvpp2_pcpu_stats
*stats
= this_cpu_ptr(port
->stats
);
6406 u64_stats_update_begin(&stats
->syncp
);
6407 stats
->rx_packets
+= rcvd_pkts
;
6408 stats
->rx_bytes
+= rcvd_bytes
;
6409 u64_stats_update_end(&stats
->syncp
);
6412 /* Update Rx queue management counters */
6414 mvpp2_rxq_status_update(port
, rxq
->id
, rx_done
, rx_done
);
6420 tx_desc_unmap_put(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
,
6421 struct mvpp2_tx_desc
*desc
)
6423 struct mvpp2_txq_pcpu
*txq_pcpu
= this_cpu_ptr(txq
->pcpu
);
6425 dma_addr_t buf_dma_addr
=
6426 mvpp2_txdesc_dma_addr_get(port
, desc
);
6428 mvpp2_txdesc_size_get(port
, desc
);
6429 if (!IS_TSO_HEADER(txq_pcpu
, buf_dma_addr
))
6430 dma_unmap_single(port
->dev
->dev
.parent
, buf_dma_addr
,
6431 buf_sz
, DMA_TO_DEVICE
);
6432 mvpp2_txq_desc_put(txq
);
6435 /* Handle tx fragmentation processing */
6436 static int mvpp2_tx_frag_process(struct mvpp2_port
*port
, struct sk_buff
*skb
,
6437 struct mvpp2_tx_queue
*aggr_txq
,
6438 struct mvpp2_tx_queue
*txq
)
6440 struct mvpp2_txq_pcpu
*txq_pcpu
= this_cpu_ptr(txq
->pcpu
);
6441 struct mvpp2_tx_desc
*tx_desc
;
6443 dma_addr_t buf_dma_addr
;
6445 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6446 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6447 void *addr
= page_address(frag
->page
.p
) + frag
->page_offset
;
6449 tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
6450 mvpp2_txdesc_txq_set(port
, tx_desc
, txq
->id
);
6451 mvpp2_txdesc_size_set(port
, tx_desc
, frag
->size
);
6453 buf_dma_addr
= dma_map_single(port
->dev
->dev
.parent
, addr
,
6456 if (dma_mapping_error(port
->dev
->dev
.parent
, buf_dma_addr
)) {
6457 mvpp2_txq_desc_put(txq
);
6461 mvpp2_txdesc_dma_addr_set(port
, tx_desc
, buf_dma_addr
);
6463 if (i
== (skb_shinfo(skb
)->nr_frags
- 1)) {
6464 /* Last descriptor */
6465 mvpp2_txdesc_cmd_set(port
, tx_desc
,
6467 mvpp2_txq_inc_put(port
, txq_pcpu
, skb
, tx_desc
);
6469 /* Descriptor in the middle: Not First, Not Last */
6470 mvpp2_txdesc_cmd_set(port
, tx_desc
, 0);
6471 mvpp2_txq_inc_put(port
, txq_pcpu
, NULL
, tx_desc
);
6477 /* Release all descriptors that were used to map fragments of
6478 * this packet, as well as the corresponding DMA mappings
6480 for (i
= i
- 1; i
>= 0; i
--) {
6481 tx_desc
= txq
->descs
+ i
;
6482 tx_desc_unmap_put(port
, txq
, tx_desc
);
6488 static inline void mvpp2_tso_put_hdr(struct sk_buff
*skb
,
6489 struct net_device
*dev
,
6490 struct mvpp2_tx_queue
*txq
,
6491 struct mvpp2_tx_queue
*aggr_txq
,
6492 struct mvpp2_txq_pcpu
*txq_pcpu
,
6495 struct mvpp2_port
*port
= netdev_priv(dev
);
6496 struct mvpp2_tx_desc
*tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
6499 mvpp2_txdesc_txq_set(port
, tx_desc
, txq
->id
);
6500 mvpp2_txdesc_size_set(port
, tx_desc
, hdr_sz
);
6502 addr
= txq_pcpu
->tso_headers_dma
+
6503 txq_pcpu
->txq_put_index
* TSO_HEADER_SIZE
;
6504 mvpp2_txdesc_dma_addr_set(port
, tx_desc
, addr
);
6506 mvpp2_txdesc_cmd_set(port
, tx_desc
, mvpp2_skb_tx_csum(port
, skb
) |
6508 MVPP2_TXD_PADDING_DISABLE
);
6509 mvpp2_txq_inc_put(port
, txq_pcpu
, NULL
, tx_desc
);
6512 static inline int mvpp2_tso_put_data(struct sk_buff
*skb
,
6513 struct net_device
*dev
, struct tso_t
*tso
,
6514 struct mvpp2_tx_queue
*txq
,
6515 struct mvpp2_tx_queue
*aggr_txq
,
6516 struct mvpp2_txq_pcpu
*txq_pcpu
,
6517 int sz
, bool left
, bool last
)
6519 struct mvpp2_port
*port
= netdev_priv(dev
);
6520 struct mvpp2_tx_desc
*tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
6521 dma_addr_t buf_dma_addr
;
6523 mvpp2_txdesc_txq_set(port
, tx_desc
, txq
->id
);
6524 mvpp2_txdesc_size_set(port
, tx_desc
, sz
);
6526 buf_dma_addr
= dma_map_single(dev
->dev
.parent
, tso
->data
, sz
,
6528 if (unlikely(dma_mapping_error(dev
->dev
.parent
, buf_dma_addr
))) {
6529 mvpp2_txq_desc_put(txq
);
6533 mvpp2_txdesc_dma_addr_set(port
, tx_desc
, buf_dma_addr
);
6536 mvpp2_txdesc_cmd_set(port
, tx_desc
, MVPP2_TXD_L_DESC
);
6538 mvpp2_txq_inc_put(port
, txq_pcpu
, skb
, tx_desc
);
6542 mvpp2_txdesc_cmd_set(port
, tx_desc
, 0);
6545 mvpp2_txq_inc_put(port
, txq_pcpu
, NULL
, tx_desc
);
6549 static int mvpp2_tx_tso(struct sk_buff
*skb
, struct net_device
*dev
,
6550 struct mvpp2_tx_queue
*txq
,
6551 struct mvpp2_tx_queue
*aggr_txq
,
6552 struct mvpp2_txq_pcpu
*txq_pcpu
)
6554 struct mvpp2_port
*port
= netdev_priv(dev
);
6556 int hdr_sz
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
6557 int i
, len
, descs
= 0;
6559 /* Check number of available descriptors */
6560 if (mvpp2_aggr_desc_num_check(port
->priv
, aggr_txq
,
6561 tso_count_descs(skb
)) ||
6562 mvpp2_txq_reserved_desc_num_proc(port
->priv
, txq
, txq_pcpu
,
6563 tso_count_descs(skb
)))
6566 tso_start(skb
, &tso
);
6567 len
= skb
->len
- hdr_sz
;
6569 int left
= min_t(int, skb_shinfo(skb
)->gso_size
, len
);
6570 char *hdr
= txq_pcpu
->tso_headers
+
6571 txq_pcpu
->txq_put_index
* TSO_HEADER_SIZE
;
6576 tso_build_hdr(skb
, hdr
, &tso
, left
, len
== 0);
6577 mvpp2_tso_put_hdr(skb
, dev
, txq
, aggr_txq
, txq_pcpu
, hdr_sz
);
6580 int sz
= min_t(int, tso
.size
, left
);
6584 if (mvpp2_tso_put_data(skb
, dev
, &tso
, txq
, aggr_txq
,
6585 txq_pcpu
, sz
, left
, len
== 0))
6587 tso_build_data(skb
, &tso
, sz
);
6594 for (i
= descs
- 1; i
>= 0; i
--) {
6595 struct mvpp2_tx_desc
*tx_desc
= txq
->descs
+ i
;
6596 tx_desc_unmap_put(port
, txq
, tx_desc
);
6601 /* Main tx processing */
6602 static int mvpp2_tx(struct sk_buff
*skb
, struct net_device
*dev
)
6604 struct mvpp2_port
*port
= netdev_priv(dev
);
6605 struct mvpp2_tx_queue
*txq
, *aggr_txq
;
6606 struct mvpp2_txq_pcpu
*txq_pcpu
;
6607 struct mvpp2_tx_desc
*tx_desc
;
6608 dma_addr_t buf_dma_addr
;
6613 txq_id
= skb_get_queue_mapping(skb
);
6614 txq
= port
->txqs
[txq_id
];
6615 txq_pcpu
= this_cpu_ptr(txq
->pcpu
);
6616 aggr_txq
= &port
->priv
->aggr_txqs
[smp_processor_id()];
6618 if (skb_is_gso(skb
)) {
6619 frags
= mvpp2_tx_tso(skb
, dev
, txq
, aggr_txq
, txq_pcpu
);
6622 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
6624 /* Check number of available descriptors */
6625 if (mvpp2_aggr_desc_num_check(port
->priv
, aggr_txq
, frags
) ||
6626 mvpp2_txq_reserved_desc_num_proc(port
->priv
, txq
,
6632 /* Get a descriptor for the first part of the packet */
6633 tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
6634 mvpp2_txdesc_txq_set(port
, tx_desc
, txq
->id
);
6635 mvpp2_txdesc_size_set(port
, tx_desc
, skb_headlen(skb
));
6637 buf_dma_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
6638 skb_headlen(skb
), DMA_TO_DEVICE
);
6639 if (unlikely(dma_mapping_error(dev
->dev
.parent
, buf_dma_addr
))) {
6640 mvpp2_txq_desc_put(txq
);
6645 mvpp2_txdesc_dma_addr_set(port
, tx_desc
, buf_dma_addr
);
6647 tx_cmd
= mvpp2_skb_tx_csum(port
, skb
);
6650 /* First and Last descriptor */
6651 tx_cmd
|= MVPP2_TXD_F_DESC
| MVPP2_TXD_L_DESC
;
6652 mvpp2_txdesc_cmd_set(port
, tx_desc
, tx_cmd
);
6653 mvpp2_txq_inc_put(port
, txq_pcpu
, skb
, tx_desc
);
6655 /* First but not Last */
6656 tx_cmd
|= MVPP2_TXD_F_DESC
| MVPP2_TXD_PADDING_DISABLE
;
6657 mvpp2_txdesc_cmd_set(port
, tx_desc
, tx_cmd
);
6658 mvpp2_txq_inc_put(port
, txq_pcpu
, NULL
, tx_desc
);
6660 /* Continue with other skb fragments */
6661 if (mvpp2_tx_frag_process(port
, skb
, aggr_txq
, txq
)) {
6662 tx_desc_unmap_put(port
, txq
, tx_desc
);
6669 struct mvpp2_pcpu_stats
*stats
= this_cpu_ptr(port
->stats
);
6670 struct netdev_queue
*nq
= netdev_get_tx_queue(dev
, txq_id
);
6672 txq_pcpu
->reserved_num
-= frags
;
6673 txq_pcpu
->count
+= frags
;
6674 aggr_txq
->count
+= frags
;
6676 /* Enable transmit */
6678 mvpp2_aggr_txq_pend_desc_add(port
, frags
);
6680 if (txq_pcpu
->count
>= txq_pcpu
->stop_threshold
)
6681 netif_tx_stop_queue(nq
);
6683 u64_stats_update_begin(&stats
->syncp
);
6684 stats
->tx_packets
++;
6685 stats
->tx_bytes
+= skb
->len
;
6686 u64_stats_update_end(&stats
->syncp
);
6688 dev
->stats
.tx_dropped
++;
6689 dev_kfree_skb_any(skb
);
6692 /* Finalize TX processing */
6693 if (!port
->has_tx_irqs
&& txq_pcpu
->count
>= txq
->done_pkts_coal
)
6694 mvpp2_txq_done(port
, txq
, txq_pcpu
);
6696 /* Set the timer in case not all frags were processed */
6697 if (!port
->has_tx_irqs
&& txq_pcpu
->count
<= frags
&&
6698 txq_pcpu
->count
> 0) {
6699 struct mvpp2_port_pcpu
*port_pcpu
= this_cpu_ptr(port
->pcpu
);
6701 mvpp2_timer_set(port_pcpu
);
6704 return NETDEV_TX_OK
;
6707 static inline void mvpp2_cause_error(struct net_device
*dev
, int cause
)
6709 if (cause
& MVPP2_CAUSE_FCS_ERR_MASK
)
6710 netdev_err(dev
, "FCS error\n");
6711 if (cause
& MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK
)
6712 netdev_err(dev
, "rx fifo overrun error\n");
6713 if (cause
& MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK
)
6714 netdev_err(dev
, "tx fifo underrun error\n");
6717 static int mvpp2_poll(struct napi_struct
*napi
, int budget
)
6719 u32 cause_rx_tx
, cause_rx
, cause_tx
, cause_misc
;
6721 struct mvpp2_port
*port
= netdev_priv(napi
->dev
);
6722 struct mvpp2_queue_vector
*qv
;
6723 int cpu
= smp_processor_id();
6725 qv
= container_of(napi
, struct mvpp2_queue_vector
, napi
);
6727 /* Rx/Tx cause register
6729 * Bits 0-15: each bit indicates received packets on the Rx queue
6730 * (bit 0 is for Rx queue 0).
6732 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
6733 * (bit 16 is for Tx queue 0).
6735 * Each CPU has its own Rx/Tx cause register
6737 cause_rx_tx
= mvpp2_percpu_read(port
->priv
, qv
->sw_thread_id
,
6738 MVPP2_ISR_RX_TX_CAUSE_REG(port
->id
));
6740 cause_misc
= cause_rx_tx
& MVPP2_CAUSE_MISC_SUM_MASK
;
6742 mvpp2_cause_error(port
->dev
, cause_misc
);
6744 /* Clear the cause register */
6745 mvpp2_write(port
->priv
, MVPP2_ISR_MISC_CAUSE_REG
, 0);
6746 mvpp2_percpu_write(port
->priv
, cpu
,
6747 MVPP2_ISR_RX_TX_CAUSE_REG(port
->id
),
6748 cause_rx_tx
& ~MVPP2_CAUSE_MISC_SUM_MASK
);
6751 cause_tx
= cause_rx_tx
& MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK
;
6753 cause_tx
>>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET
;
6754 mvpp2_tx_done(port
, cause_tx
, qv
->sw_thread_id
);
6757 /* Process RX packets */
6758 cause_rx
= cause_rx_tx
& MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
;
6759 cause_rx
<<= qv
->first_rxq
;
6760 cause_rx
|= qv
->pending_cause_rx
;
6761 while (cause_rx
&& budget
> 0) {
6763 struct mvpp2_rx_queue
*rxq
;
6765 rxq
= mvpp2_get_rx_queue(port
, cause_rx
);
6769 count
= mvpp2_rx(port
, napi
, budget
, rxq
);
6773 /* Clear the bit associated to this Rx queue
6774 * so that next iteration will continue from
6775 * the next Rx queue.
6777 cause_rx
&= ~(1 << rxq
->logic_rxq
);
6783 napi_complete_done(napi
, rx_done
);
6785 mvpp2_qvec_interrupt_enable(qv
);
6787 qv
->pending_cause_rx
= cause_rx
;
6791 /* Set hw internals when starting port */
6792 static void mvpp2_start_dev(struct mvpp2_port
*port
)
6794 struct net_device
*ndev
= port
->dev
;
6797 if (port
->gop_id
== 0 &&
6798 (port
->phy_interface
== PHY_INTERFACE_MODE_XAUI
||
6799 port
->phy_interface
== PHY_INTERFACE_MODE_10GKR
))
6800 mvpp2_xlg_max_rx_size_set(port
);
6802 mvpp2_gmac_max_rx_size_set(port
);
6804 mvpp2_txp_max_tx_size_set(port
);
6806 for (i
= 0; i
< port
->nqvecs
; i
++)
6807 napi_enable(&port
->qvecs
[i
].napi
);
6809 /* Enable interrupts on all CPUs */
6810 mvpp2_interrupts_enable(port
);
6812 if (port
->priv
->hw_version
== MVPP22
) {
6813 mvpp22_comphy_init(port
);
6814 mvpp22_gop_init(port
);
6817 mvpp2_port_mii_set(port
);
6818 mvpp2_port_enable(port
);
6820 phy_start(ndev
->phydev
);
6821 netif_tx_start_all_queues(port
->dev
);
6824 /* Set hw internals when stopping port */
6825 static void mvpp2_stop_dev(struct mvpp2_port
*port
)
6827 struct net_device
*ndev
= port
->dev
;
6830 /* Stop new packets from arriving to RXQs */
6831 mvpp2_ingress_disable(port
);
6835 /* Disable interrupts on all CPUs */
6836 mvpp2_interrupts_disable(port
);
6838 for (i
= 0; i
< port
->nqvecs
; i
++)
6839 napi_disable(&port
->qvecs
[i
].napi
);
6841 netif_carrier_off(port
->dev
);
6842 netif_tx_stop_all_queues(port
->dev
);
6844 mvpp2_egress_disable(port
);
6845 mvpp2_port_disable(port
);
6847 phy_stop(ndev
->phydev
);
6848 phy_power_off(port
->comphy
);
6851 static int mvpp2_check_ringparam_valid(struct net_device
*dev
,
6852 struct ethtool_ringparam
*ring
)
6854 u16 new_rx_pending
= ring
->rx_pending
;
6855 u16 new_tx_pending
= ring
->tx_pending
;
6857 if (ring
->rx_pending
== 0 || ring
->tx_pending
== 0)
6860 if (ring
->rx_pending
> MVPP2_MAX_RXD
)
6861 new_rx_pending
= MVPP2_MAX_RXD
;
6862 else if (!IS_ALIGNED(ring
->rx_pending
, 16))
6863 new_rx_pending
= ALIGN(ring
->rx_pending
, 16);
6865 if (ring
->tx_pending
> MVPP2_MAX_TXD
)
6866 new_tx_pending
= MVPP2_MAX_TXD
;
6867 else if (!IS_ALIGNED(ring
->tx_pending
, 32))
6868 new_tx_pending
= ALIGN(ring
->tx_pending
, 32);
6870 if (ring
->rx_pending
!= new_rx_pending
) {
6871 netdev_info(dev
, "illegal Rx ring size value %d, round to %d\n",
6872 ring
->rx_pending
, new_rx_pending
);
6873 ring
->rx_pending
= new_rx_pending
;
6876 if (ring
->tx_pending
!= new_tx_pending
) {
6877 netdev_info(dev
, "illegal Tx ring size value %d, round to %d\n",
6878 ring
->tx_pending
, new_tx_pending
);
6879 ring
->tx_pending
= new_tx_pending
;
6885 static void mvpp21_get_mac_address(struct mvpp2_port
*port
, unsigned char *addr
)
6887 u32 mac_addr_l
, mac_addr_m
, mac_addr_h
;
6889 mac_addr_l
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
6890 mac_addr_m
= readl(port
->priv
->lms_base
+ MVPP2_SRC_ADDR_MIDDLE
);
6891 mac_addr_h
= readl(port
->priv
->lms_base
+ MVPP2_SRC_ADDR_HIGH
);
6892 addr
[0] = (mac_addr_h
>> 24) & 0xFF;
6893 addr
[1] = (mac_addr_h
>> 16) & 0xFF;
6894 addr
[2] = (mac_addr_h
>> 8) & 0xFF;
6895 addr
[3] = mac_addr_h
& 0xFF;
6896 addr
[4] = mac_addr_m
& 0xFF;
6897 addr
[5] = (mac_addr_l
>> MVPP2_GMAC_SA_LOW_OFFS
) & 0xFF;
6900 static int mvpp2_phy_connect(struct mvpp2_port
*port
)
6902 struct phy_device
*phy_dev
;
6904 /* No PHY is attached */
6905 if (!port
->phy_node
)
6908 phy_dev
= of_phy_connect(port
->dev
, port
->phy_node
, mvpp2_link_event
, 0,
6909 port
->phy_interface
);
6911 netdev_err(port
->dev
, "cannot connect to phy\n");
6914 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
6915 phy_dev
->advertising
= phy_dev
->supported
;
6924 static void mvpp2_phy_disconnect(struct mvpp2_port
*port
)
6926 struct net_device
*ndev
= port
->dev
;
6931 phy_disconnect(ndev
->phydev
);
6934 static int mvpp2_irqs_init(struct mvpp2_port
*port
)
6938 for (i
= 0; i
< port
->nqvecs
; i
++) {
6939 struct mvpp2_queue_vector
*qv
= port
->qvecs
+ i
;
6941 if (qv
->type
== MVPP2_QUEUE_VECTOR_PRIVATE
)
6942 irq_set_status_flags(qv
->irq
, IRQ_NO_BALANCING
);
6944 err
= request_irq(qv
->irq
, mvpp2_isr
, 0, port
->dev
->name
, qv
);
6948 if (qv
->type
== MVPP2_QUEUE_VECTOR_PRIVATE
)
6949 irq_set_affinity_hint(qv
->irq
,
6950 cpumask_of(qv
->sw_thread_id
));
6955 for (i
= 0; i
< port
->nqvecs
; i
++) {
6956 struct mvpp2_queue_vector
*qv
= port
->qvecs
+ i
;
6958 irq_set_affinity_hint(qv
->irq
, NULL
);
6959 free_irq(qv
->irq
, qv
);
6965 static void mvpp2_irqs_deinit(struct mvpp2_port
*port
)
6969 for (i
= 0; i
< port
->nqvecs
; i
++) {
6970 struct mvpp2_queue_vector
*qv
= port
->qvecs
+ i
;
6972 irq_set_affinity_hint(qv
->irq
, NULL
);
6973 irq_clear_status_flags(qv
->irq
, IRQ_NO_BALANCING
);
6974 free_irq(qv
->irq
, qv
);
6978 static void mvpp22_init_rss(struct mvpp2_port
*port
)
6980 struct mvpp2
*priv
= port
->priv
;
6983 /* Set the table width: replace the whole classifier Rx queue number
6984 * with the ones configured in RSS table entries.
6986 mvpp2_write(priv
, MVPP22_RSS_INDEX
, MVPP22_RSS_INDEX_TABLE(0));
6987 mvpp2_write(priv
, MVPP22_RSS_WIDTH
, 8);
6989 /* Loop through the classifier Rx Queues and map them to a RSS table.
6990 * Map them all to the first table (0) by default.
6992 for (i
= 0; i
< MVPP2_CLS_RX_QUEUES
; i
++) {
6993 mvpp2_write(priv
, MVPP22_RSS_INDEX
, MVPP22_RSS_INDEX_QUEUE(i
));
6994 mvpp2_write(priv
, MVPP22_RSS_TABLE
,
6995 MVPP22_RSS_TABLE_POINTER(0));
6998 /* Configure the first table to evenly distribute the packets across
6999 * real Rx Queues. The table entries map a hash to an port Rx Queue.
7001 for (i
= 0; i
< MVPP22_RSS_TABLE_ENTRIES
; i
++) {
7002 u32 sel
= MVPP22_RSS_INDEX_TABLE(0) |
7003 MVPP22_RSS_INDEX_TABLE_ENTRY(i
);
7004 mvpp2_write(priv
, MVPP22_RSS_INDEX
, sel
);
7006 mvpp2_write(priv
, MVPP22_RSS_TABLE_ENTRY
, i
% port
->nrxqs
);
7011 static int mvpp2_open(struct net_device
*dev
)
7013 struct mvpp2_port
*port
= netdev_priv(dev
);
7014 struct mvpp2
*priv
= port
->priv
;
7015 unsigned char mac_bcast
[ETH_ALEN
] = {
7016 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
7019 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, mac_bcast
, true);
7021 netdev_err(dev
, "mvpp2_prs_mac_da_accept BC failed\n");
7024 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
,
7025 dev
->dev_addr
, true);
7027 netdev_err(dev
, "mvpp2_prs_mac_da_accept MC failed\n");
7030 err
= mvpp2_prs_tag_mode_set(port
->priv
, port
->id
, MVPP2_TAG_TYPE_MH
);
7032 netdev_err(dev
, "mvpp2_prs_tag_mode_set failed\n");
7035 err
= mvpp2_prs_def_flow(port
);
7037 netdev_err(dev
, "mvpp2_prs_def_flow failed\n");
7041 /* Allocate the Rx/Tx queues */
7042 err
= mvpp2_setup_rxqs(port
);
7044 netdev_err(port
->dev
, "cannot allocate Rx queues\n");
7048 err
= mvpp2_setup_txqs(port
);
7050 netdev_err(port
->dev
, "cannot allocate Tx queues\n");
7051 goto err_cleanup_rxqs
;
7054 err
= mvpp2_irqs_init(port
);
7056 netdev_err(port
->dev
, "cannot init IRQs\n");
7057 goto err_cleanup_txqs
;
7060 if (priv
->hw_version
== MVPP22
&& !port
->phy_node
&& port
->link_irq
) {
7061 err
= request_irq(port
->link_irq
, mvpp2_link_status_isr
, 0,
7064 netdev_err(port
->dev
, "cannot request link IRQ %d\n",
7069 mvpp22_gop_setup_irq(port
);
7072 /* In default link is down */
7073 netif_carrier_off(port
->dev
);
7075 err
= mvpp2_phy_connect(port
);
7077 goto err_free_link_irq
;
7079 /* Unmask interrupts on all CPUs */
7080 on_each_cpu(mvpp2_interrupts_unmask
, port
, 1);
7081 mvpp2_shared_interrupt_mask_unmask(port
, false);
7083 mvpp2_start_dev(port
);
7085 if (priv
->hw_version
== MVPP22
)
7086 mvpp22_init_rss(port
);
7088 /* Start hardware statistics gathering */
7089 queue_delayed_work(priv
->stats_queue
, &port
->stats_work
,
7090 MVPP2_MIB_COUNTERS_STATS_DELAY
);
7095 if (priv
->hw_version
== MVPP22
&& !port
->phy_node
&& port
->link_irq
)
7096 free_irq(port
->link_irq
, port
);
7098 mvpp2_irqs_deinit(port
);
7100 mvpp2_cleanup_txqs(port
);
7102 mvpp2_cleanup_rxqs(port
);
7106 static int mvpp2_stop(struct net_device
*dev
)
7108 struct mvpp2_port
*port
= netdev_priv(dev
);
7109 struct mvpp2_port_pcpu
*port_pcpu
;
7110 struct mvpp2
*priv
= port
->priv
;
7113 mvpp2_stop_dev(port
);
7114 mvpp2_phy_disconnect(port
);
7116 /* Mask interrupts on all CPUs */
7117 on_each_cpu(mvpp2_interrupts_mask
, port
, 1);
7118 mvpp2_shared_interrupt_mask_unmask(port
, true);
7120 if (priv
->hw_version
== MVPP22
&& !port
->phy_node
&& port
->link_irq
)
7121 free_irq(port
->link_irq
, port
);
7123 mvpp2_irqs_deinit(port
);
7124 if (!port
->has_tx_irqs
) {
7125 for_each_present_cpu(cpu
) {
7126 port_pcpu
= per_cpu_ptr(port
->pcpu
, cpu
);
7128 hrtimer_cancel(&port_pcpu
->tx_done_timer
);
7129 port_pcpu
->timer_scheduled
= false;
7130 tasklet_kill(&port_pcpu
->tx_done_tasklet
);
7133 mvpp2_cleanup_rxqs(port
);
7134 mvpp2_cleanup_txqs(port
);
7136 cancel_delayed_work_sync(&port
->stats_work
);
7141 static void mvpp2_set_rx_mode(struct net_device
*dev
)
7143 struct mvpp2_port
*port
= netdev_priv(dev
);
7144 struct mvpp2
*priv
= port
->priv
;
7145 struct netdev_hw_addr
*ha
;
7147 bool allmulti
= dev
->flags
& IFF_ALLMULTI
;
7149 mvpp2_prs_mac_promisc_set(priv
, id
, dev
->flags
& IFF_PROMISC
);
7150 mvpp2_prs_mac_multi_set(priv
, id
, MVPP2_PE_MAC_MC_ALL
, allmulti
);
7151 mvpp2_prs_mac_multi_set(priv
, id
, MVPP2_PE_MAC_MC_IP6
, allmulti
);
7153 /* Remove all port->id's mcast enries */
7154 mvpp2_prs_mcast_del_all(priv
, id
);
7156 if (allmulti
&& !netdev_mc_empty(dev
)) {
7157 netdev_for_each_mc_addr(ha
, dev
)
7158 mvpp2_prs_mac_da_accept(priv
, id
, ha
->addr
, true);
7162 static int mvpp2_set_mac_address(struct net_device
*dev
, void *p
)
7164 struct mvpp2_port
*port
= netdev_priv(dev
);
7165 const struct sockaddr
*addr
= p
;
7168 if (!is_valid_ether_addr(addr
->sa_data
)) {
7169 err
= -EADDRNOTAVAIL
;
7173 if (!netif_running(dev
)) {
7174 err
= mvpp2_prs_update_mac_da(dev
, addr
->sa_data
);
7177 /* Reconfigure parser to accept the original MAC address */
7178 err
= mvpp2_prs_update_mac_da(dev
, dev
->dev_addr
);
7183 mvpp2_stop_dev(port
);
7185 err
= mvpp2_prs_update_mac_da(dev
, addr
->sa_data
);
7189 /* Reconfigure parser accept the original MAC address */
7190 err
= mvpp2_prs_update_mac_da(dev
, dev
->dev_addr
);
7194 mvpp2_start_dev(port
);
7195 mvpp2_egress_enable(port
);
7196 mvpp2_ingress_enable(port
);
7199 netdev_err(dev
, "failed to change MAC address\n");
7203 static int mvpp2_change_mtu(struct net_device
*dev
, int mtu
)
7205 struct mvpp2_port
*port
= netdev_priv(dev
);
7208 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu
), 8)) {
7209 netdev_info(dev
, "illegal MTU value %d, round to %d\n", mtu
,
7210 ALIGN(MVPP2_RX_PKT_SIZE(mtu
), 8));
7211 mtu
= ALIGN(MVPP2_RX_PKT_SIZE(mtu
), 8);
7214 if (!netif_running(dev
)) {
7215 err
= mvpp2_bm_update_mtu(dev
, mtu
);
7217 port
->pkt_size
= MVPP2_RX_PKT_SIZE(mtu
);
7221 /* Reconfigure BM to the original MTU */
7222 err
= mvpp2_bm_update_mtu(dev
, dev
->mtu
);
7227 mvpp2_stop_dev(port
);
7229 err
= mvpp2_bm_update_mtu(dev
, mtu
);
7231 port
->pkt_size
= MVPP2_RX_PKT_SIZE(mtu
);
7235 /* Reconfigure BM to the original MTU */
7236 err
= mvpp2_bm_update_mtu(dev
, dev
->mtu
);
7241 mvpp2_start_dev(port
);
7242 mvpp2_egress_enable(port
);
7243 mvpp2_ingress_enable(port
);
7247 netdev_err(dev
, "failed to change MTU\n");
7252 mvpp2_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
7254 struct mvpp2_port
*port
= netdev_priv(dev
);
7258 for_each_possible_cpu(cpu
) {
7259 struct mvpp2_pcpu_stats
*cpu_stats
;
7265 cpu_stats
= per_cpu_ptr(port
->stats
, cpu
);
7267 start
= u64_stats_fetch_begin_irq(&cpu_stats
->syncp
);
7268 rx_packets
= cpu_stats
->rx_packets
;
7269 rx_bytes
= cpu_stats
->rx_bytes
;
7270 tx_packets
= cpu_stats
->tx_packets
;
7271 tx_bytes
= cpu_stats
->tx_bytes
;
7272 } while (u64_stats_fetch_retry_irq(&cpu_stats
->syncp
, start
));
7274 stats
->rx_packets
+= rx_packets
;
7275 stats
->rx_bytes
+= rx_bytes
;
7276 stats
->tx_packets
+= tx_packets
;
7277 stats
->tx_bytes
+= tx_bytes
;
7280 stats
->rx_errors
= dev
->stats
.rx_errors
;
7281 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
7282 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
7285 static int mvpp2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7292 ret
= phy_mii_ioctl(dev
->phydev
, ifr
, cmd
);
7294 mvpp2_link_event(dev
);
7299 /* Ethtool methods */
7301 /* Set interrupt coalescing for ethtools */
7302 static int mvpp2_ethtool_set_coalesce(struct net_device
*dev
,
7303 struct ethtool_coalesce
*c
)
7305 struct mvpp2_port
*port
= netdev_priv(dev
);
7308 for (queue
= 0; queue
< port
->nrxqs
; queue
++) {
7309 struct mvpp2_rx_queue
*rxq
= port
->rxqs
[queue
];
7311 rxq
->time_coal
= c
->rx_coalesce_usecs
;
7312 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
7313 mvpp2_rx_pkts_coal_set(port
, rxq
);
7314 mvpp2_rx_time_coal_set(port
, rxq
);
7317 if (port
->has_tx_irqs
) {
7318 port
->tx_time_coal
= c
->tx_coalesce_usecs
;
7319 mvpp2_tx_time_coal_set(port
);
7322 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
7323 struct mvpp2_tx_queue
*txq
= port
->txqs
[queue
];
7325 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
7327 if (port
->has_tx_irqs
)
7328 mvpp2_tx_pkts_coal_set(port
, txq
);
7334 /* get coalescing for ethtools */
7335 static int mvpp2_ethtool_get_coalesce(struct net_device
*dev
,
7336 struct ethtool_coalesce
*c
)
7338 struct mvpp2_port
*port
= netdev_priv(dev
);
7340 c
->rx_coalesce_usecs
= port
->rxqs
[0]->time_coal
;
7341 c
->rx_max_coalesced_frames
= port
->rxqs
[0]->pkts_coal
;
7342 c
->tx_max_coalesced_frames
= port
->txqs
[0]->done_pkts_coal
;
7346 static void mvpp2_ethtool_get_drvinfo(struct net_device
*dev
,
7347 struct ethtool_drvinfo
*drvinfo
)
7349 strlcpy(drvinfo
->driver
, MVPP2_DRIVER_NAME
,
7350 sizeof(drvinfo
->driver
));
7351 strlcpy(drvinfo
->version
, MVPP2_DRIVER_VERSION
,
7352 sizeof(drvinfo
->version
));
7353 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
7354 sizeof(drvinfo
->bus_info
));
7357 static void mvpp2_ethtool_get_ringparam(struct net_device
*dev
,
7358 struct ethtool_ringparam
*ring
)
7360 struct mvpp2_port
*port
= netdev_priv(dev
);
7362 ring
->rx_max_pending
= MVPP2_MAX_RXD
;
7363 ring
->tx_max_pending
= MVPP2_MAX_TXD
;
7364 ring
->rx_pending
= port
->rx_ring_size
;
7365 ring
->tx_pending
= port
->tx_ring_size
;
7368 static int mvpp2_ethtool_set_ringparam(struct net_device
*dev
,
7369 struct ethtool_ringparam
*ring
)
7371 struct mvpp2_port
*port
= netdev_priv(dev
);
7372 u16 prev_rx_ring_size
= port
->rx_ring_size
;
7373 u16 prev_tx_ring_size
= port
->tx_ring_size
;
7376 err
= mvpp2_check_ringparam_valid(dev
, ring
);
7380 if (!netif_running(dev
)) {
7381 port
->rx_ring_size
= ring
->rx_pending
;
7382 port
->tx_ring_size
= ring
->tx_pending
;
7386 /* The interface is running, so we have to force a
7387 * reallocation of the queues
7389 mvpp2_stop_dev(port
);
7390 mvpp2_cleanup_rxqs(port
);
7391 mvpp2_cleanup_txqs(port
);
7393 port
->rx_ring_size
= ring
->rx_pending
;
7394 port
->tx_ring_size
= ring
->tx_pending
;
7396 err
= mvpp2_setup_rxqs(port
);
7398 /* Reallocate Rx queues with the original ring size */
7399 port
->rx_ring_size
= prev_rx_ring_size
;
7400 ring
->rx_pending
= prev_rx_ring_size
;
7401 err
= mvpp2_setup_rxqs(port
);
7405 err
= mvpp2_setup_txqs(port
);
7407 /* Reallocate Tx queues with the original ring size */
7408 port
->tx_ring_size
= prev_tx_ring_size
;
7409 ring
->tx_pending
= prev_tx_ring_size
;
7410 err
= mvpp2_setup_txqs(port
);
7412 goto err_clean_rxqs
;
7415 mvpp2_start_dev(port
);
7416 mvpp2_egress_enable(port
);
7417 mvpp2_ingress_enable(port
);
7422 mvpp2_cleanup_rxqs(port
);
7424 netdev_err(dev
, "failed to change ring parameters");
7430 static const struct net_device_ops mvpp2_netdev_ops
= {
7431 .ndo_open
= mvpp2_open
,
7432 .ndo_stop
= mvpp2_stop
,
7433 .ndo_start_xmit
= mvpp2_tx
,
7434 .ndo_set_rx_mode
= mvpp2_set_rx_mode
,
7435 .ndo_set_mac_address
= mvpp2_set_mac_address
,
7436 .ndo_change_mtu
= mvpp2_change_mtu
,
7437 .ndo_get_stats64
= mvpp2_get_stats64
,
7438 .ndo_do_ioctl
= mvpp2_ioctl
,
7441 static const struct ethtool_ops mvpp2_eth_tool_ops
= {
7442 .nway_reset
= phy_ethtool_nway_reset
,
7443 .get_link
= ethtool_op_get_link
,
7444 .set_coalesce
= mvpp2_ethtool_set_coalesce
,
7445 .get_coalesce
= mvpp2_ethtool_get_coalesce
,
7446 .get_drvinfo
= mvpp2_ethtool_get_drvinfo
,
7447 .get_ringparam
= mvpp2_ethtool_get_ringparam
,
7448 .set_ringparam
= mvpp2_ethtool_set_ringparam
,
7449 .get_strings
= mvpp2_ethtool_get_strings
,
7450 .get_ethtool_stats
= mvpp2_ethtool_get_stats
,
7451 .get_sset_count
= mvpp2_ethtool_get_sset_count
,
7452 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
7453 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
7456 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
7457 * had a single IRQ defined per-port.
7459 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port
*port
,
7460 struct device_node
*port_node
)
7462 struct mvpp2_queue_vector
*v
= &port
->qvecs
[0];
7465 v
->nrxqs
= port
->nrxqs
;
7466 v
->type
= MVPP2_QUEUE_VECTOR_SHARED
;
7467 v
->sw_thread_id
= 0;
7468 v
->sw_thread_mask
= *cpumask_bits(cpu_online_mask
);
7470 v
->irq
= irq_of_parse_and_map(port_node
, 0);
7473 netif_napi_add(port
->dev
, &v
->napi
, mvpp2_poll
,
7481 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port
*port
,
7482 struct device_node
*port_node
)
7484 struct mvpp2_queue_vector
*v
;
7487 port
->nqvecs
= num_possible_cpus();
7488 if (queue_mode
== MVPP2_QDIST_SINGLE_MODE
)
7491 for (i
= 0; i
< port
->nqvecs
; i
++) {
7494 v
= port
->qvecs
+ i
;
7497 v
->type
= MVPP2_QUEUE_VECTOR_PRIVATE
;
7498 v
->sw_thread_id
= i
;
7499 v
->sw_thread_mask
= BIT(i
);
7501 snprintf(irqname
, sizeof(irqname
), "tx-cpu%d", i
);
7503 if (queue_mode
== MVPP2_QDIST_MULTI_MODE
) {
7504 v
->first_rxq
= i
* MVPP2_DEFAULT_RXQ
;
7505 v
->nrxqs
= MVPP2_DEFAULT_RXQ
;
7506 } else if (queue_mode
== MVPP2_QDIST_SINGLE_MODE
&&
7507 i
== (port
->nqvecs
- 1)) {
7509 v
->nrxqs
= port
->nrxqs
;
7510 v
->type
= MVPP2_QUEUE_VECTOR_SHARED
;
7511 strncpy(irqname
, "rx-shared", sizeof(irqname
));
7514 v
->irq
= of_irq_get_byname(port_node
, irqname
);
7520 netif_napi_add(port
->dev
, &v
->napi
, mvpp2_poll
,
7527 for (i
= 0; i
< port
->nqvecs
; i
++)
7528 irq_dispose_mapping(port
->qvecs
[i
].irq
);
7532 static int mvpp2_queue_vectors_init(struct mvpp2_port
*port
,
7533 struct device_node
*port_node
)
7535 if (port
->has_tx_irqs
)
7536 return mvpp2_multi_queue_vectors_init(port
, port_node
);
7538 return mvpp2_simple_queue_vectors_init(port
, port_node
);
7541 static void mvpp2_queue_vectors_deinit(struct mvpp2_port
*port
)
7545 for (i
= 0; i
< port
->nqvecs
; i
++)
7546 irq_dispose_mapping(port
->qvecs
[i
].irq
);
7549 /* Configure Rx queue group interrupt for this port */
7550 static void mvpp2_rx_irqs_setup(struct mvpp2_port
*port
)
7552 struct mvpp2
*priv
= port
->priv
;
7556 if (priv
->hw_version
== MVPP21
) {
7557 mvpp2_write(priv
, MVPP21_ISR_RXQ_GROUP_REG(port
->id
),
7562 /* Handle the more complicated PPv2.2 case */
7563 for (i
= 0; i
< port
->nqvecs
; i
++) {
7564 struct mvpp2_queue_vector
*qv
= port
->qvecs
+ i
;
7569 val
= qv
->sw_thread_id
;
7570 val
|= port
->id
<< MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET
;
7571 mvpp2_write(priv
, MVPP22_ISR_RXQ_GROUP_INDEX_REG
, val
);
7573 val
= qv
->first_rxq
;
7574 val
|= qv
->nrxqs
<< MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET
;
7575 mvpp2_write(priv
, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG
, val
);
7579 /* Initialize port HW */
7580 static int mvpp2_port_init(struct mvpp2_port
*port
)
7582 struct device
*dev
= port
->dev
->dev
.parent
;
7583 struct mvpp2
*priv
= port
->priv
;
7584 struct mvpp2_txq_pcpu
*txq_pcpu
;
7585 int queue
, cpu
, err
;
7587 /* Checks for hardware constraints */
7588 if (port
->first_rxq
+ port
->nrxqs
>
7589 MVPP2_MAX_PORTS
* priv
->max_port_rxqs
)
7592 if (port
->nrxqs
% 4 || (port
->nrxqs
> priv
->max_port_rxqs
) ||
7593 (port
->ntxqs
> MVPP2_MAX_TXQ
))
7597 mvpp2_egress_disable(port
);
7598 mvpp2_port_disable(port
);
7600 port
->tx_time_coal
= MVPP2_TXDONE_COAL_USEC
;
7602 port
->txqs
= devm_kcalloc(dev
, port
->ntxqs
, sizeof(*port
->txqs
),
7607 /* Associate physical Tx queues to this port and initialize.
7608 * The mapping is predefined.
7610 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
7611 int queue_phy_id
= mvpp2_txq_phys(port
->id
, queue
);
7612 struct mvpp2_tx_queue
*txq
;
7614 txq
= devm_kzalloc(dev
, sizeof(*txq
), GFP_KERNEL
);
7617 goto err_free_percpu
;
7620 txq
->pcpu
= alloc_percpu(struct mvpp2_txq_pcpu
);
7623 goto err_free_percpu
;
7626 txq
->id
= queue_phy_id
;
7627 txq
->log_id
= queue
;
7628 txq
->done_pkts_coal
= MVPP2_TXDONE_COAL_PKTS_THRESH
;
7629 for_each_present_cpu(cpu
) {
7630 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
7631 txq_pcpu
->cpu
= cpu
;
7634 port
->txqs
[queue
] = txq
;
7637 port
->rxqs
= devm_kcalloc(dev
, port
->nrxqs
, sizeof(*port
->rxqs
),
7641 goto err_free_percpu
;
7644 /* Allocate and initialize Rx queue for this port */
7645 for (queue
= 0; queue
< port
->nrxqs
; queue
++) {
7646 struct mvpp2_rx_queue
*rxq
;
7648 /* Map physical Rx queue to port's logical Rx queue */
7649 rxq
= devm_kzalloc(dev
, sizeof(*rxq
), GFP_KERNEL
);
7652 goto err_free_percpu
;
7654 /* Map this Rx queue to a physical queue */
7655 rxq
->id
= port
->first_rxq
+ queue
;
7656 rxq
->port
= port
->id
;
7657 rxq
->logic_rxq
= queue
;
7659 port
->rxqs
[queue
] = rxq
;
7662 mvpp2_rx_irqs_setup(port
);
7664 /* Create Rx descriptor rings */
7665 for (queue
= 0; queue
< port
->nrxqs
; queue
++) {
7666 struct mvpp2_rx_queue
*rxq
= port
->rxqs
[queue
];
7668 rxq
->size
= port
->rx_ring_size
;
7669 rxq
->pkts_coal
= MVPP2_RX_COAL_PKTS
;
7670 rxq
->time_coal
= MVPP2_RX_COAL_USEC
;
7673 mvpp2_ingress_disable(port
);
7675 /* Port default configuration */
7676 mvpp2_defaults_set(port
);
7678 /* Port's classifier configuration */
7679 mvpp2_cls_oversize_rxq_set(port
);
7680 mvpp2_cls_port_config(port
);
7682 /* Provide an initial Rx packet size */
7683 port
->pkt_size
= MVPP2_RX_PKT_SIZE(port
->dev
->mtu
);
7685 /* Initialize pools for swf */
7686 err
= mvpp2_swf_bm_pool_init(port
);
7688 goto err_free_percpu
;
7693 for (queue
= 0; queue
< port
->ntxqs
; queue
++) {
7694 if (!port
->txqs
[queue
])
7696 free_percpu(port
->txqs
[queue
]->pcpu
);
7701 /* Checks if the port DT description has the TX interrupts
7702 * described. On PPv2.1, there are no such interrupts. On PPv2.2,
7703 * there are available, but we need to keep support for old DTs.
7705 static bool mvpp2_port_has_tx_irqs(struct mvpp2
*priv
,
7706 struct device_node
*port_node
)
7708 char *irqs
[5] = { "rx-shared", "tx-cpu0", "tx-cpu1",
7709 "tx-cpu2", "tx-cpu3" };
7712 if (priv
->hw_version
== MVPP21
)
7715 for (i
= 0; i
< 5; i
++) {
7716 ret
= of_property_match_string(port_node
, "interrupt-names",
7725 static void mvpp2_port_copy_mac_addr(struct net_device
*dev
, struct mvpp2
*priv
,
7726 struct device_node
*port_node
,
7729 struct mvpp2_port
*port
= netdev_priv(dev
);
7730 char hw_mac_addr
[ETH_ALEN
] = {0};
7731 const char *dt_mac_addr
;
7733 dt_mac_addr
= of_get_mac_address(port_node
);
7734 if (dt_mac_addr
&& is_valid_ether_addr(dt_mac_addr
)) {
7735 *mac_from
= "device tree";
7736 ether_addr_copy(dev
->dev_addr
, dt_mac_addr
);
7740 if (priv
->hw_version
== MVPP21
) {
7741 mvpp21_get_mac_address(port
, hw_mac_addr
);
7742 if (is_valid_ether_addr(hw_mac_addr
)) {
7743 *mac_from
= "hardware";
7744 ether_addr_copy(dev
->dev_addr
, hw_mac_addr
);
7749 *mac_from
= "random";
7750 eth_hw_addr_random(dev
);
7753 /* Ports initialization */
7754 static int mvpp2_port_probe(struct platform_device
*pdev
,
7755 struct device_node
*port_node
,
7756 struct mvpp2
*priv
, int index
)
7758 struct device_node
*phy_node
;
7760 struct mvpp2_port
*port
;
7761 struct mvpp2_port_pcpu
*port_pcpu
;
7762 struct net_device
*dev
;
7763 struct resource
*res
;
7764 char *mac_from
= "";
7765 unsigned int ntxqs
, nrxqs
;
7772 has_tx_irqs
= mvpp2_port_has_tx_irqs(priv
, port_node
);
7775 queue_mode
= MVPP2_QDIST_SINGLE_MODE
;
7777 ntxqs
= MVPP2_MAX_TXQ
;
7778 if (priv
->hw_version
== MVPP22
&& queue_mode
== MVPP2_QDIST_MULTI_MODE
)
7779 nrxqs
= MVPP2_DEFAULT_RXQ
* num_possible_cpus();
7781 nrxqs
= MVPP2_DEFAULT_RXQ
;
7783 dev
= alloc_etherdev_mqs(sizeof(*port
), ntxqs
, nrxqs
);
7787 phy_node
= of_parse_phandle(port_node
, "phy", 0);
7788 phy_mode
= of_get_phy_mode(port_node
);
7790 dev_err(&pdev
->dev
, "incorrect phy mode\n");
7792 goto err_free_netdev
;
7795 comphy
= devm_of_phy_get(&pdev
->dev
, port_node
, NULL
);
7796 if (IS_ERR(comphy
)) {
7797 if (PTR_ERR(comphy
) == -EPROBE_DEFER
) {
7798 err
= -EPROBE_DEFER
;
7799 goto err_free_netdev
;
7804 if (of_property_read_u32(port_node
, "port-id", &id
)) {
7806 dev_err(&pdev
->dev
, "missing port-id value\n");
7807 goto err_free_netdev
;
7810 dev
->tx_queue_len
= MVPP2_MAX_TXD
;
7811 dev
->watchdog_timeo
= 5 * HZ
;
7812 dev
->netdev_ops
= &mvpp2_netdev_ops
;
7813 dev
->ethtool_ops
= &mvpp2_eth_tool_ops
;
7815 port
= netdev_priv(dev
);
7817 port
->ntxqs
= ntxqs
;
7818 port
->nrxqs
= nrxqs
;
7820 port
->has_tx_irqs
= has_tx_irqs
;
7822 err
= mvpp2_queue_vectors_init(port
, port_node
);
7824 goto err_free_netdev
;
7826 port
->link_irq
= of_irq_get_byname(port_node
, "link");
7827 if (port
->link_irq
== -EPROBE_DEFER
) {
7828 err
= -EPROBE_DEFER
;
7829 goto err_deinit_qvecs
;
7831 if (port
->link_irq
<= 0)
7832 /* the link irq is optional */
7835 if (of_property_read_bool(port_node
, "marvell,loopback"))
7836 port
->flags
|= MVPP2_F_LOOPBACK
;
7839 if (priv
->hw_version
== MVPP21
)
7840 port
->first_rxq
= port
->id
* port
->nrxqs
;
7842 port
->first_rxq
= port
->id
* priv
->max_port_rxqs
;
7844 port
->phy_node
= phy_node
;
7845 port
->phy_interface
= phy_mode
;
7846 port
->comphy
= comphy
;
7848 if (priv
->hw_version
== MVPP21
) {
7849 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2 + id
);
7850 port
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
7851 if (IS_ERR(port
->base
)) {
7852 err
= PTR_ERR(port
->base
);
7856 port
->stats_base
= port
->priv
->lms_base
+
7857 MVPP21_MIB_COUNTERS_OFFSET
+
7858 port
->gop_id
* MVPP21_MIB_COUNTERS_PORT_SZ
;
7860 if (of_property_read_u32(port_node
, "gop-port-id",
7863 dev_err(&pdev
->dev
, "missing gop-port-id value\n");
7864 goto err_deinit_qvecs
;
7867 port
->base
= priv
->iface_base
+ MVPP22_GMAC_BASE(port
->gop_id
);
7868 port
->stats_base
= port
->priv
->iface_base
+
7869 MVPP22_MIB_COUNTERS_OFFSET
+
7870 port
->gop_id
* MVPP22_MIB_COUNTERS_PORT_SZ
;
7873 /* Alloc per-cpu and ethtool stats */
7874 port
->stats
= netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats
);
7880 port
->ethtool_stats
= devm_kcalloc(&pdev
->dev
,
7881 ARRAY_SIZE(mvpp2_ethtool_regs
),
7882 sizeof(u64
), GFP_KERNEL
);
7883 if (!port
->ethtool_stats
) {
7885 goto err_free_stats
;
7888 mutex_init(&port
->gather_stats_lock
);
7889 INIT_DELAYED_WORK(&port
->stats_work
, mvpp2_gather_hw_statistics
);
7891 mvpp2_port_copy_mac_addr(dev
, priv
, port_node
, &mac_from
);
7893 port
->tx_ring_size
= MVPP2_MAX_TXD
;
7894 port
->rx_ring_size
= MVPP2_MAX_RXD
;
7895 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7897 err
= mvpp2_port_init(port
);
7899 dev_err(&pdev
->dev
, "failed to init port %d\n", id
);
7900 goto err_free_stats
;
7903 mvpp2_port_periodic_xon_disable(port
);
7905 if (priv
->hw_version
== MVPP21
)
7906 mvpp2_port_fc_adv_enable(port
);
7908 mvpp2_port_reset(port
);
7910 port
->pcpu
= alloc_percpu(struct mvpp2_port_pcpu
);
7913 goto err_free_txq_pcpu
;
7916 if (!port
->has_tx_irqs
) {
7917 for_each_present_cpu(cpu
) {
7918 port_pcpu
= per_cpu_ptr(port
->pcpu
, cpu
);
7920 hrtimer_init(&port_pcpu
->tx_done_timer
, CLOCK_MONOTONIC
,
7921 HRTIMER_MODE_REL_PINNED
);
7922 port_pcpu
->tx_done_timer
.function
= mvpp2_hr_timer_cb
;
7923 port_pcpu
->timer_scheduled
= false;
7925 tasklet_init(&port_pcpu
->tx_done_tasklet
,
7927 (unsigned long)dev
);
7931 features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
;
7932 dev
->features
= features
| NETIF_F_RXCSUM
;
7933 dev
->hw_features
|= features
| NETIF_F_RXCSUM
| NETIF_F_GRO
;
7934 dev
->vlan_features
|= features
;
7935 dev
->gso_max_segs
= MVPP2_MAX_TSO_SEGS
;
7937 /* MTU range: 68 - 9676 */
7938 dev
->min_mtu
= ETH_MIN_MTU
;
7939 /* 9676 == 9700 - 20 and rounding to 8 */
7940 dev
->max_mtu
= 9676;
7942 err
= register_netdev(dev
);
7944 dev_err(&pdev
->dev
, "failed to register netdev\n");
7945 goto err_free_port_pcpu
;
7947 netdev_info(dev
, "Using %s mac address %pM\n", mac_from
, dev
->dev_addr
);
7949 priv
->port_list
[index
] = port
;
7953 free_percpu(port
->pcpu
);
7955 for (i
= 0; i
< port
->ntxqs
; i
++)
7956 free_percpu(port
->txqs
[i
]->pcpu
);
7958 free_percpu(port
->stats
);
7961 irq_dispose_mapping(port
->link_irq
);
7963 mvpp2_queue_vectors_deinit(port
);
7965 of_node_put(phy_node
);
7970 /* Ports removal routine */
7971 static void mvpp2_port_remove(struct mvpp2_port
*port
)
7975 unregister_netdev(port
->dev
);
7976 of_node_put(port
->phy_node
);
7977 free_percpu(port
->pcpu
);
7978 free_percpu(port
->stats
);
7979 for (i
= 0; i
< port
->ntxqs
; i
++)
7980 free_percpu(port
->txqs
[i
]->pcpu
);
7981 mvpp2_queue_vectors_deinit(port
);
7983 irq_dispose_mapping(port
->link_irq
);
7984 free_netdev(port
->dev
);
7987 /* Initialize decoding windows */
7988 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info
*dram
,
7994 for (i
= 0; i
< 6; i
++) {
7995 mvpp2_write(priv
, MVPP2_WIN_BASE(i
), 0);
7996 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
), 0);
7999 mvpp2_write(priv
, MVPP2_WIN_REMAP(i
), 0);
8004 for (i
= 0; i
< dram
->num_cs
; i
++) {
8005 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
8007 mvpp2_write(priv
, MVPP2_WIN_BASE(i
),
8008 (cs
->base
& 0xffff0000) | (cs
->mbus_attr
<< 8) |
8009 dram
->mbus_dram_target_id
);
8011 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
),
8012 (cs
->size
- 1) & 0xffff0000);
8014 win_enable
|= (1 << i
);
8017 mvpp2_write(priv
, MVPP2_BASE_ADDR_ENABLE
, win_enable
);
8020 /* Initialize Rx FIFO's */
8021 static void mvpp2_rx_fifo_init(struct mvpp2
*priv
)
8025 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
8026 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
8027 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB
);
8028 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
8029 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB
);
8032 mvpp2_write(priv
, MVPP2_RX_MIN_PKT_SIZE_REG
,
8033 MVPP2_RX_FIFO_PORT_MIN_PKT
);
8034 mvpp2_write(priv
, MVPP2_RX_FIFO_INIT_REG
, 0x1);
8037 static void mvpp22_rx_fifo_init(struct mvpp2
*priv
)
8041 /* The FIFO size parameters are set depending on the maximum speed a
8042 * given port can handle:
8045 * - Ports 2 and 3: 1Gbps
8048 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
8049 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB
);
8050 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
8051 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB
);
8053 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
8054 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB
);
8055 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
8056 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB
);
8058 for (port
= 2; port
< MVPP2_MAX_PORTS
; port
++) {
8059 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
8060 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB
);
8061 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
8062 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB
);
8065 mvpp2_write(priv
, MVPP2_RX_MIN_PKT_SIZE_REG
,
8066 MVPP2_RX_FIFO_PORT_MIN_PKT
);
8067 mvpp2_write(priv
, MVPP2_RX_FIFO_INIT_REG
, 0x1);
8070 /* Initialize Tx FIFO's */
8071 static void mvpp22_tx_fifo_init(struct mvpp2
*priv
)
8075 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++)
8076 mvpp2_write(priv
, MVPP22_TX_FIFO_SIZE_REG(port
),
8077 MVPP22_TX_FIFO_DATA_SIZE_3KB
);
8080 static void mvpp2_axi_init(struct mvpp2
*priv
)
8082 u32 val
, rdval
, wrval
;
8084 mvpp2_write(priv
, MVPP22_BM_ADDR_HIGH_RLS_REG
, 0x0);
8086 /* AXI Bridge Configuration */
8088 rdval
= MVPP22_AXI_CODE_CACHE_RD_CACHE
8089 << MVPP22_AXI_ATTR_CACHE_OFFS
;
8090 rdval
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
8091 << MVPP22_AXI_ATTR_DOMAIN_OFFS
;
8093 wrval
= MVPP22_AXI_CODE_CACHE_WR_CACHE
8094 << MVPP22_AXI_ATTR_CACHE_OFFS
;
8095 wrval
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
8096 << MVPP22_AXI_ATTR_DOMAIN_OFFS
;
8099 mvpp2_write(priv
, MVPP22_AXI_BM_WR_ATTR_REG
, wrval
);
8100 mvpp2_write(priv
, MVPP22_AXI_BM_RD_ATTR_REG
, rdval
);
8103 mvpp2_write(priv
, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG
, rdval
);
8104 mvpp2_write(priv
, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG
, wrval
);
8105 mvpp2_write(priv
, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG
, rdval
);
8106 mvpp2_write(priv
, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG
, wrval
);
8109 mvpp2_write(priv
, MVPP22_AXI_TX_DATA_RD_ATTR_REG
, rdval
);
8110 mvpp2_write(priv
, MVPP22_AXI_RX_DATA_WR_ATTR_REG
, wrval
);
8112 val
= MVPP22_AXI_CODE_CACHE_NON_CACHE
8113 << MVPP22_AXI_CODE_CACHE_OFFS
;
8114 val
|= MVPP22_AXI_CODE_DOMAIN_SYSTEM
8115 << MVPP22_AXI_CODE_DOMAIN_OFFS
;
8116 mvpp2_write(priv
, MVPP22_AXI_RD_NORMAL_CODE_REG
, val
);
8117 mvpp2_write(priv
, MVPP22_AXI_WR_NORMAL_CODE_REG
, val
);
8119 val
= MVPP22_AXI_CODE_CACHE_RD_CACHE
8120 << MVPP22_AXI_CODE_CACHE_OFFS
;
8121 val
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
8122 << MVPP22_AXI_CODE_DOMAIN_OFFS
;
8124 mvpp2_write(priv
, MVPP22_AXI_RD_SNOOP_CODE_REG
, val
);
8126 val
= MVPP22_AXI_CODE_CACHE_WR_CACHE
8127 << MVPP22_AXI_CODE_CACHE_OFFS
;
8128 val
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
8129 << MVPP22_AXI_CODE_DOMAIN_OFFS
;
8131 mvpp2_write(priv
, MVPP22_AXI_WR_SNOOP_CODE_REG
, val
);
8134 /* Initialize network controller common part HW */
8135 static int mvpp2_init(struct platform_device
*pdev
, struct mvpp2
*priv
)
8137 const struct mbus_dram_target_info
*dram_target_info
;
8141 /* MBUS windows configuration */
8142 dram_target_info
= mv_mbus_dram_info();
8143 if (dram_target_info
)
8144 mvpp2_conf_mbus_windows(dram_target_info
, priv
);
8146 if (priv
->hw_version
== MVPP22
)
8147 mvpp2_axi_init(priv
);
8149 /* Disable HW PHY polling */
8150 if (priv
->hw_version
== MVPP21
) {
8151 val
= readl(priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
8152 val
|= MVPP2_PHY_AN_STOP_SMI0_MASK
;
8153 writel(val
, priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
8155 val
= readl(priv
->iface_base
+ MVPP22_SMI_MISC_CFG_REG
);
8156 val
&= ~MVPP22_SMI_POLLING_EN
;
8157 writel(val
, priv
->iface_base
+ MVPP22_SMI_MISC_CFG_REG
);
8160 /* Allocate and initialize aggregated TXQs */
8161 priv
->aggr_txqs
= devm_kcalloc(&pdev
->dev
, num_present_cpus(),
8162 sizeof(*priv
->aggr_txqs
),
8164 if (!priv
->aggr_txqs
)
8167 for_each_present_cpu(i
) {
8168 priv
->aggr_txqs
[i
].id
= i
;
8169 priv
->aggr_txqs
[i
].size
= MVPP2_AGGR_TXQ_SIZE
;
8170 err
= mvpp2_aggr_txq_init(pdev
, &priv
->aggr_txqs
[i
], i
, priv
);
8176 if (priv
->hw_version
== MVPP21
) {
8177 mvpp2_rx_fifo_init(priv
);
8179 mvpp22_rx_fifo_init(priv
);
8180 mvpp22_tx_fifo_init(priv
);
8183 if (priv
->hw_version
== MVPP21
)
8184 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT
,
8185 priv
->lms_base
+ MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG
);
8187 /* Allow cache snoop when transmiting packets */
8188 mvpp2_write(priv
, MVPP2_TX_SNOOP_REG
, 0x1);
8190 /* Buffer Manager initialization */
8191 err
= mvpp2_bm_init(pdev
, priv
);
8195 /* Parser default initialization */
8196 err
= mvpp2_prs_default_init(pdev
, priv
);
8200 /* Classifier default initialization */
8201 mvpp2_cls_init(priv
);
8206 static int mvpp2_probe(struct platform_device
*pdev
)
8208 struct device_node
*dn
= pdev
->dev
.of_node
;
8209 struct device_node
*port_node
;
8211 struct resource
*res
;
8216 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
8221 (unsigned long)of_device_get_match_data(&pdev
->dev
);
8223 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
8224 base
= devm_ioremap_resource(&pdev
->dev
, res
);
8226 return PTR_ERR(base
);
8228 if (priv
->hw_version
== MVPP21
) {
8229 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
8230 priv
->lms_base
= devm_ioremap_resource(&pdev
->dev
, res
);
8231 if (IS_ERR(priv
->lms_base
))
8232 return PTR_ERR(priv
->lms_base
);
8234 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
8235 priv
->iface_base
= devm_ioremap_resource(&pdev
->dev
, res
);
8236 if (IS_ERR(priv
->iface_base
))
8237 return PTR_ERR(priv
->iface_base
);
8239 priv
->sysctrl_base
=
8240 syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
8241 "marvell,system-controller");
8242 if (IS_ERR(priv
->sysctrl_base
))
8243 /* The system controller regmap is optional for dt
8244 * compatibility reasons. When not provided, the
8245 * configuration of the GoP relies on the
8246 * firmware/bootloader.
8248 priv
->sysctrl_base
= NULL
;
8251 for (i
= 0; i
< MVPP2_MAX_THREADS
; i
++) {
8254 addr_space_sz
= (priv
->hw_version
== MVPP21
?
8255 MVPP21_ADDR_SPACE_SZ
: MVPP22_ADDR_SPACE_SZ
);
8256 priv
->swth_base
[i
] = base
+ i
* addr_space_sz
;
8259 if (priv
->hw_version
== MVPP21
)
8260 priv
->max_port_rxqs
= 8;
8262 priv
->max_port_rxqs
= 32;
8264 priv
->pp_clk
= devm_clk_get(&pdev
->dev
, "pp_clk");
8265 if (IS_ERR(priv
->pp_clk
))
8266 return PTR_ERR(priv
->pp_clk
);
8267 err
= clk_prepare_enable(priv
->pp_clk
);
8271 priv
->gop_clk
= devm_clk_get(&pdev
->dev
, "gop_clk");
8272 if (IS_ERR(priv
->gop_clk
)) {
8273 err
= PTR_ERR(priv
->gop_clk
);
8276 err
= clk_prepare_enable(priv
->gop_clk
);
8280 if (priv
->hw_version
== MVPP22
) {
8281 priv
->mg_clk
= devm_clk_get(&pdev
->dev
, "mg_clk");
8282 if (IS_ERR(priv
->mg_clk
)) {
8283 err
= PTR_ERR(priv
->mg_clk
);
8287 err
= clk_prepare_enable(priv
->mg_clk
);
8291 priv
->axi_clk
= devm_clk_get(&pdev
->dev
, "axi_clk");
8292 if (IS_ERR(priv
->axi_clk
)) {
8293 err
= PTR_ERR(priv
->axi_clk
);
8294 if (err
== -EPROBE_DEFER
)
8296 priv
->axi_clk
= NULL
;
8298 err
= clk_prepare_enable(priv
->axi_clk
);
8304 /* Get system's tclk rate */
8305 priv
->tclk
= clk_get_rate(priv
->pp_clk
);
8307 if (priv
->hw_version
== MVPP22
) {
8308 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(40));
8311 /* Sadly, the BM pools all share the same register to
8312 * store the high 32 bits of their address. So they
8313 * must all have the same high 32 bits, which forces
8314 * us to restrict coherent memory to DMA_BIT_MASK(32).
8316 err
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
8321 /* Initialize network controller */
8322 err
= mvpp2_init(pdev
, priv
);
8324 dev_err(&pdev
->dev
, "failed to initialize controller\n");
8328 priv
->port_count
= of_get_available_child_count(dn
);
8329 if (priv
->port_count
== 0) {
8330 dev_err(&pdev
->dev
, "no ports enabled\n");
8335 priv
->port_list
= devm_kcalloc(&pdev
->dev
, priv
->port_count
,
8336 sizeof(*priv
->port_list
),
8338 if (!priv
->port_list
) {
8343 /* Initialize ports */
8345 for_each_available_child_of_node(dn
, port_node
) {
8346 err
= mvpp2_port_probe(pdev
, port_node
, priv
, i
);
8352 /* Statistics must be gathered regularly because some of them (like
8353 * packets counters) are 32-bit registers and could overflow quite
8354 * quickly. For instance, a 10Gb link used at full bandwidth with the
8355 * smallest packets (64B) will overflow a 32-bit counter in less than
8356 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
8358 snprintf(priv
->queue_name
, sizeof(priv
->queue_name
),
8359 "stats-wq-%s%s", netdev_name(priv
->port_list
[0]->dev
),
8360 priv
->port_count
> 1 ? "+" : "");
8361 priv
->stats_queue
= create_singlethread_workqueue(priv
->queue_name
);
8362 if (!priv
->stats_queue
) {
8367 platform_set_drvdata(pdev
, priv
);
8371 clk_disable_unprepare(priv
->axi_clk
);
8372 if (priv
->hw_version
== MVPP22
)
8373 clk_disable_unprepare(priv
->mg_clk
);
8375 clk_disable_unprepare(priv
->gop_clk
);
8377 clk_disable_unprepare(priv
->pp_clk
);
8381 static int mvpp2_remove(struct platform_device
*pdev
)
8383 struct mvpp2
*priv
= platform_get_drvdata(pdev
);
8384 struct device_node
*dn
= pdev
->dev
.of_node
;
8385 struct device_node
*port_node
;
8388 flush_workqueue(priv
->stats_queue
);
8389 destroy_workqueue(priv
->stats_queue
);
8391 for_each_available_child_of_node(dn
, port_node
) {
8392 if (priv
->port_list
[i
]) {
8393 mutex_destroy(&priv
->port_list
[i
]->gather_stats_lock
);
8394 mvpp2_port_remove(priv
->port_list
[i
]);
8399 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
8400 struct mvpp2_bm_pool
*bm_pool
= &priv
->bm_pools
[i
];
8402 mvpp2_bm_pool_destroy(pdev
, priv
, bm_pool
);
8405 for_each_present_cpu(i
) {
8406 struct mvpp2_tx_queue
*aggr_txq
= &priv
->aggr_txqs
[i
];
8408 dma_free_coherent(&pdev
->dev
,
8409 MVPP2_AGGR_TXQ_SIZE
* MVPP2_DESC_ALIGNED_SIZE
,
8411 aggr_txq
->descs_dma
);
8414 clk_disable_unprepare(priv
->axi_clk
);
8415 clk_disable_unprepare(priv
->mg_clk
);
8416 clk_disable_unprepare(priv
->pp_clk
);
8417 clk_disable_unprepare(priv
->gop_clk
);
8422 static const struct of_device_id mvpp2_match
[] = {
8424 .compatible
= "marvell,armada-375-pp2",
8425 .data
= (void *)MVPP21
,
8428 .compatible
= "marvell,armada-7k-pp22",
8429 .data
= (void *)MVPP22
,
8433 MODULE_DEVICE_TABLE(of
, mvpp2_match
);
8435 static struct platform_driver mvpp2_driver
= {
8436 .probe
= mvpp2_probe
,
8437 .remove
= mvpp2_remove
,
8439 .name
= MVPP2_DRIVER_NAME
,
8440 .of_match_table
= mvpp2_match
,
8444 module_platform_driver(mvpp2_driver
);
8446 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
8447 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
8448 MODULE_LICENSE("GPL v2");