1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
27 #include "mtk_eth_soc.h"
29 static int mtk_msg_level
= -1;
30 module_param_named(msg_level
, mtk_msg_level
, int, 0);
31 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
33 #define MTK_ETHTOOL_STAT(x) { #x, \
34 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
36 /* strings used by ethtool */
37 static const struct mtk_ethtool_stats
{
38 char str
[ETH_GSTRING_LEN
];
40 } mtk_ethtool_stats
[] = {
41 MTK_ETHTOOL_STAT(tx_bytes
),
42 MTK_ETHTOOL_STAT(tx_packets
),
43 MTK_ETHTOOL_STAT(tx_skip
),
44 MTK_ETHTOOL_STAT(tx_collisions
),
45 MTK_ETHTOOL_STAT(rx_bytes
),
46 MTK_ETHTOOL_STAT(rx_packets
),
47 MTK_ETHTOOL_STAT(rx_overflow
),
48 MTK_ETHTOOL_STAT(rx_fcs_errors
),
49 MTK_ETHTOOL_STAT(rx_short_errors
),
50 MTK_ETHTOOL_STAT(rx_long_errors
),
51 MTK_ETHTOOL_STAT(rx_checksum_errors
),
52 MTK_ETHTOOL_STAT(rx_flow_control_packets
),
55 static const char * const mtk_clks_source_name
[] = {
56 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
57 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
60 void mtk_w32(struct mtk_eth
*eth
, u32 val
, unsigned reg
)
62 __raw_writel(val
, eth
->base
+ reg
);
65 u32
mtk_r32(struct mtk_eth
*eth
, unsigned reg
)
67 return __raw_readl(eth
->base
+ reg
);
70 static int mtk_mdio_busy_wait(struct mtk_eth
*eth
)
72 unsigned long t_start
= jiffies
;
75 if (!(mtk_r32(eth
, MTK_PHY_IAC
) & PHY_IAC_ACCESS
))
77 if (time_after(jiffies
, t_start
+ PHY_IAC_TIMEOUT
))
82 dev_err(eth
->dev
, "mdio: MDIO timeout\n");
86 static u32
_mtk_mdio_write(struct mtk_eth
*eth
, u32 phy_addr
,
87 u32 phy_register
, u32 write_data
)
89 if (mtk_mdio_busy_wait(eth
))
94 mtk_w32(eth
, PHY_IAC_ACCESS
| PHY_IAC_START
| PHY_IAC_WRITE
|
95 (phy_register
<< PHY_IAC_REG_SHIFT
) |
96 (phy_addr
<< PHY_IAC_ADDR_SHIFT
) | write_data
,
99 if (mtk_mdio_busy_wait(eth
))
105 static u32
_mtk_mdio_read(struct mtk_eth
*eth
, int phy_addr
, int phy_reg
)
109 if (mtk_mdio_busy_wait(eth
))
112 mtk_w32(eth
, PHY_IAC_ACCESS
| PHY_IAC_START
| PHY_IAC_READ
|
113 (phy_reg
<< PHY_IAC_REG_SHIFT
) |
114 (phy_addr
<< PHY_IAC_ADDR_SHIFT
),
117 if (mtk_mdio_busy_wait(eth
))
120 d
= mtk_r32(eth
, MTK_PHY_IAC
) & 0xffff;
125 static int mtk_mdio_write(struct mii_bus
*bus
, int phy_addr
,
126 int phy_reg
, u16 val
)
128 struct mtk_eth
*eth
= bus
->priv
;
130 return _mtk_mdio_write(eth
, phy_addr
, phy_reg
, val
);
133 static int mtk_mdio_read(struct mii_bus
*bus
, int phy_addr
, int phy_reg
)
135 struct mtk_eth
*eth
= bus
->priv
;
137 return _mtk_mdio_read(eth
, phy_addr
, phy_reg
);
140 static void mtk_gmac0_rgmii_adjust(struct mtk_eth
*eth
, int speed
)
145 val
= (speed
== SPEED_1000
) ?
146 INTF_MODE_RGMII_1000
: INTF_MODE_RGMII_10_100
;
147 mtk_w32(eth
, val
, INTF_MODE
);
149 regmap_update_bits(eth
->ethsys
, ETHSYS_CLKCFG0
,
150 ETHSYS_TRGMII_CLK_SEL362_5
,
151 ETHSYS_TRGMII_CLK_SEL362_5
);
153 val
= (speed
== SPEED_1000
) ? 250000000 : 500000000;
154 ret
= clk_set_rate(eth
->clks
[MTK_CLK_TRGPLL
], val
);
156 dev_err(eth
->dev
, "Failed to set trgmii pll: %d\n", ret
);
158 val
= (speed
== SPEED_1000
) ?
159 RCK_CTRL_RGMII_1000
: RCK_CTRL_RGMII_10_100
;
160 mtk_w32(eth
, val
, TRGMII_RCK_CTRL
);
162 val
= (speed
== SPEED_1000
) ?
163 TCK_CTRL_RGMII_1000
: TCK_CTRL_RGMII_10_100
;
164 mtk_w32(eth
, val
, TRGMII_TCK_CTRL
);
167 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth
*eth
, int mac_id
)
171 /* Setup the link timer and QPHY power up inside SGMIISYS */
172 regmap_write(eth
->sgmiisys
, SGMSYS_PCS_LINK_TIMER
,
173 SGMII_LINK_TIMER_DEFAULT
);
175 regmap_read(eth
->sgmiisys
, SGMSYS_SGMII_MODE
, &val
);
176 val
|= SGMII_REMOTE_FAULT_DIS
;
177 regmap_write(eth
->sgmiisys
, SGMSYS_SGMII_MODE
, val
);
179 regmap_read(eth
->sgmiisys
, SGMSYS_PCS_CONTROL_1
, &val
);
180 val
|= SGMII_AN_RESTART
;
181 regmap_write(eth
->sgmiisys
, SGMSYS_PCS_CONTROL_1
, val
);
183 regmap_read(eth
->sgmiisys
, SGMSYS_QPHY_PWR_STATE_CTRL
, &val
);
184 val
&= ~SGMII_PHYA_PWD
;
185 regmap_write(eth
->sgmiisys
, SGMSYS_QPHY_PWR_STATE_CTRL
, val
);
187 /* Determine MUX for which GMAC uses the SGMII interface */
188 if (MTK_HAS_CAPS(eth
->soc
->caps
, MTK_DUAL_GMAC_SHARED_SGMII
)) {
189 regmap_read(eth
->ethsys
, ETHSYS_SYSCFG0
, &val
);
190 val
&= ~SYSCFG0_SGMII_MASK
;
191 val
|= !mac_id
? SYSCFG0_SGMII_GMAC1
: SYSCFG0_SGMII_GMAC2
;
192 regmap_write(eth
->ethsys
, ETHSYS_SYSCFG0
, val
);
194 dev_info(eth
->dev
, "setup shared sgmii for gmac=%d\n",
198 /* Setup the GMAC1 going through SGMII path when SoC also support
201 if (MTK_HAS_CAPS(eth
->soc
->caps
, MTK_GMAC1_ESW
| MTK_GMAC1_SGMII
) &&
203 mtk_w32(eth
, 0, MTK_MAC_MISC
);
204 dev_info(eth
->dev
, "setup gmac1 going through sgmii");
208 static void mtk_phy_link_adjust(struct net_device
*dev
)
210 struct mtk_mac
*mac
= netdev_priv(dev
);
211 u16 lcl_adv
= 0, rmt_adv
= 0;
213 u32 mcr
= MAC_MCR_MAX_RX_1536
| MAC_MCR_IPG_CFG
|
214 MAC_MCR_FORCE_MODE
| MAC_MCR_TX_EN
|
215 MAC_MCR_RX_EN
| MAC_MCR_BACKOFF_EN
|
218 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
221 switch (dev
->phydev
->speed
) {
223 mcr
|= MAC_MCR_SPEED_1000
;
226 mcr
|= MAC_MCR_SPEED_100
;
230 if (MTK_HAS_CAPS(mac
->hw
->soc
->caps
, MTK_GMAC1_TRGMII
) &&
231 !mac
->id
&& !mac
->trgmii
)
232 mtk_gmac0_rgmii_adjust(mac
->hw
, dev
->phydev
->speed
);
234 if (dev
->phydev
->link
)
235 mcr
|= MAC_MCR_FORCE_LINK
;
237 if (dev
->phydev
->duplex
) {
238 mcr
|= MAC_MCR_FORCE_DPX
;
240 if (dev
->phydev
->pause
)
241 rmt_adv
= LPA_PAUSE_CAP
;
242 if (dev
->phydev
->asym_pause
)
243 rmt_adv
|= LPA_PAUSE_ASYM
;
245 if (dev
->phydev
->advertising
& ADVERTISED_Pause
)
246 lcl_adv
|= ADVERTISE_PAUSE_CAP
;
247 if (dev
->phydev
->advertising
& ADVERTISED_Asym_Pause
)
248 lcl_adv
|= ADVERTISE_PAUSE_ASYM
;
250 flowctrl
= mii_resolve_flowctrl_fdx(lcl_adv
, rmt_adv
);
252 if (flowctrl
& FLOW_CTRL_TX
)
253 mcr
|= MAC_MCR_FORCE_TX_FC
;
254 if (flowctrl
& FLOW_CTRL_RX
)
255 mcr
|= MAC_MCR_FORCE_RX_FC
;
257 netif_dbg(mac
->hw
, link
, dev
, "rx pause %s, tx pause %s\n",
258 flowctrl
& FLOW_CTRL_RX
? "enabled" : "disabled",
259 flowctrl
& FLOW_CTRL_TX
? "enabled" : "disabled");
262 mtk_w32(mac
->hw
, mcr
, MTK_MAC_MCR(mac
->id
));
264 if (dev
->phydev
->link
)
265 netif_carrier_on(dev
);
267 netif_carrier_off(dev
);
269 if (!of_phy_is_fixed_link(mac
->of_node
))
270 phy_print_status(dev
->phydev
);
273 static int mtk_phy_connect_node(struct mtk_eth
*eth
, struct mtk_mac
*mac
,
274 struct device_node
*phy_node
)
276 struct phy_device
*phydev
;
279 phy_mode
= of_get_phy_mode(phy_node
);
281 dev_err(eth
->dev
, "incorrect phy-mode %d\n", phy_mode
);
285 phydev
= of_phy_connect(eth
->netdev
[mac
->id
], phy_node
,
286 mtk_phy_link_adjust
, 0, phy_mode
);
288 dev_err(eth
->dev
, "could not connect to PHY\n");
293 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
294 mac
->id
, phydev_name(phydev
), phydev
->phy_id
,
300 static int mtk_phy_connect(struct net_device
*dev
)
302 struct mtk_mac
*mac
= netdev_priv(dev
);
304 struct device_node
*np
;
308 np
= of_parse_phandle(mac
->of_node
, "phy-handle", 0);
309 if (!np
&& of_phy_is_fixed_link(mac
->of_node
))
310 if (!of_phy_register_fixed_link(mac
->of_node
))
311 np
= of_node_get(mac
->of_node
);
316 switch (of_get_phy_mode(np
)) {
317 case PHY_INTERFACE_MODE_TRGMII
:
319 case PHY_INTERFACE_MODE_RGMII_TXID
:
320 case PHY_INTERFACE_MODE_RGMII_RXID
:
321 case PHY_INTERFACE_MODE_RGMII_ID
:
322 case PHY_INTERFACE_MODE_RGMII
:
324 case PHY_INTERFACE_MODE_SGMII
:
325 if (MTK_HAS_CAPS(eth
->soc
->caps
, MTK_SGMII
))
326 mtk_gmac_sgmii_hw_setup(eth
, mac
->id
);
328 case PHY_INTERFACE_MODE_MII
:
331 case PHY_INTERFACE_MODE_REVMII
:
334 case PHY_INTERFACE_MODE_RMII
:
343 /* put the gmac into the right mode */
344 regmap_read(eth
->ethsys
, ETHSYS_SYSCFG0
, &val
);
345 val
&= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK
, mac
->id
);
346 val
|= SYSCFG0_GE_MODE(mac
->ge_mode
, mac
->id
);
347 regmap_write(eth
->ethsys
, ETHSYS_SYSCFG0
, val
);
349 /* couple phydev to net_device */
350 if (mtk_phy_connect_node(eth
, mac
, np
))
353 dev
->phydev
->autoneg
= AUTONEG_ENABLE
;
354 dev
->phydev
->speed
= 0;
355 dev
->phydev
->duplex
= 0;
357 if (of_phy_is_fixed_link(mac
->of_node
))
358 dev
->phydev
->supported
|=
359 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
;
361 dev
->phydev
->supported
&= PHY_GBIT_FEATURES
| SUPPORTED_Pause
|
362 SUPPORTED_Asym_Pause
;
363 dev
->phydev
->advertising
= dev
->phydev
->supported
|
365 phy_start_aneg(dev
->phydev
);
372 if (of_phy_is_fixed_link(mac
->of_node
))
373 of_phy_deregister_fixed_link(mac
->of_node
);
375 dev_err(eth
->dev
, "%s: invalid phy\n", __func__
);
379 static int mtk_mdio_init(struct mtk_eth
*eth
)
381 struct device_node
*mii_np
;
384 mii_np
= of_get_child_by_name(eth
->dev
->of_node
, "mdio-bus");
386 dev_err(eth
->dev
, "no %s child node found", "mdio-bus");
390 if (!of_device_is_available(mii_np
)) {
395 eth
->mii_bus
= devm_mdiobus_alloc(eth
->dev
);
401 eth
->mii_bus
->name
= "mdio";
402 eth
->mii_bus
->read
= mtk_mdio_read
;
403 eth
->mii_bus
->write
= mtk_mdio_write
;
404 eth
->mii_bus
->priv
= eth
;
405 eth
->mii_bus
->parent
= eth
->dev
;
407 snprintf(eth
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s", mii_np
->name
);
408 ret
= of_mdiobus_register(eth
->mii_bus
, mii_np
);
415 static void mtk_mdio_cleanup(struct mtk_eth
*eth
)
420 mdiobus_unregister(eth
->mii_bus
);
423 static inline void mtk_tx_irq_disable(struct mtk_eth
*eth
, u32 mask
)
428 spin_lock_irqsave(ð
->tx_irq_lock
, flags
);
429 val
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
430 mtk_w32(eth
, val
& ~mask
, MTK_QDMA_INT_MASK
);
431 spin_unlock_irqrestore(ð
->tx_irq_lock
, flags
);
434 static inline void mtk_tx_irq_enable(struct mtk_eth
*eth
, u32 mask
)
439 spin_lock_irqsave(ð
->tx_irq_lock
, flags
);
440 val
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
441 mtk_w32(eth
, val
| mask
, MTK_QDMA_INT_MASK
);
442 spin_unlock_irqrestore(ð
->tx_irq_lock
, flags
);
445 static inline void mtk_rx_irq_disable(struct mtk_eth
*eth
, u32 mask
)
450 spin_lock_irqsave(ð
->rx_irq_lock
, flags
);
451 val
= mtk_r32(eth
, MTK_PDMA_INT_MASK
);
452 mtk_w32(eth
, val
& ~mask
, MTK_PDMA_INT_MASK
);
453 spin_unlock_irqrestore(ð
->rx_irq_lock
, flags
);
456 static inline void mtk_rx_irq_enable(struct mtk_eth
*eth
, u32 mask
)
461 spin_lock_irqsave(ð
->rx_irq_lock
, flags
);
462 val
= mtk_r32(eth
, MTK_PDMA_INT_MASK
);
463 mtk_w32(eth
, val
| mask
, MTK_PDMA_INT_MASK
);
464 spin_unlock_irqrestore(ð
->rx_irq_lock
, flags
);
467 static int mtk_set_mac_address(struct net_device
*dev
, void *p
)
469 int ret
= eth_mac_addr(dev
, p
);
470 struct mtk_mac
*mac
= netdev_priv(dev
);
471 const char *macaddr
= dev
->dev_addr
;
476 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
479 spin_lock_bh(&mac
->hw
->page_lock
);
480 mtk_w32(mac
->hw
, (macaddr
[0] << 8) | macaddr
[1],
481 MTK_GDMA_MAC_ADRH(mac
->id
));
482 mtk_w32(mac
->hw
, (macaddr
[2] << 24) | (macaddr
[3] << 16) |
483 (macaddr
[4] << 8) | macaddr
[5],
484 MTK_GDMA_MAC_ADRL(mac
->id
));
485 spin_unlock_bh(&mac
->hw
->page_lock
);
490 void mtk_stats_update_mac(struct mtk_mac
*mac
)
492 struct mtk_hw_stats
*hw_stats
= mac
->hw_stats
;
493 unsigned int base
= MTK_GDM1_TX_GBCNT
;
496 base
+= hw_stats
->reg_offset
;
498 u64_stats_update_begin(&hw_stats
->syncp
);
500 hw_stats
->rx_bytes
+= mtk_r32(mac
->hw
, base
);
501 stats
= mtk_r32(mac
->hw
, base
+ 0x04);
503 hw_stats
->rx_bytes
+= (stats
<< 32);
504 hw_stats
->rx_packets
+= mtk_r32(mac
->hw
, base
+ 0x08);
505 hw_stats
->rx_overflow
+= mtk_r32(mac
->hw
, base
+ 0x10);
506 hw_stats
->rx_fcs_errors
+= mtk_r32(mac
->hw
, base
+ 0x14);
507 hw_stats
->rx_short_errors
+= mtk_r32(mac
->hw
, base
+ 0x18);
508 hw_stats
->rx_long_errors
+= mtk_r32(mac
->hw
, base
+ 0x1c);
509 hw_stats
->rx_checksum_errors
+= mtk_r32(mac
->hw
, base
+ 0x20);
510 hw_stats
->rx_flow_control_packets
+=
511 mtk_r32(mac
->hw
, base
+ 0x24);
512 hw_stats
->tx_skip
+= mtk_r32(mac
->hw
, base
+ 0x28);
513 hw_stats
->tx_collisions
+= mtk_r32(mac
->hw
, base
+ 0x2c);
514 hw_stats
->tx_bytes
+= mtk_r32(mac
->hw
, base
+ 0x30);
515 stats
= mtk_r32(mac
->hw
, base
+ 0x34);
517 hw_stats
->tx_bytes
+= (stats
<< 32);
518 hw_stats
->tx_packets
+= mtk_r32(mac
->hw
, base
+ 0x38);
519 u64_stats_update_end(&hw_stats
->syncp
);
522 static void mtk_stats_update(struct mtk_eth
*eth
)
526 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
527 if (!eth
->mac
[i
] || !eth
->mac
[i
]->hw_stats
)
529 if (spin_trylock(ð
->mac
[i
]->hw_stats
->stats_lock
)) {
530 mtk_stats_update_mac(eth
->mac
[i
]);
531 spin_unlock(ð
->mac
[i
]->hw_stats
->stats_lock
);
536 static void mtk_get_stats64(struct net_device
*dev
,
537 struct rtnl_link_stats64
*storage
)
539 struct mtk_mac
*mac
= netdev_priv(dev
);
540 struct mtk_hw_stats
*hw_stats
= mac
->hw_stats
;
543 if (netif_running(dev
) && netif_device_present(dev
)) {
544 if (spin_trylock_bh(&hw_stats
->stats_lock
)) {
545 mtk_stats_update_mac(mac
);
546 spin_unlock_bh(&hw_stats
->stats_lock
);
551 start
= u64_stats_fetch_begin_irq(&hw_stats
->syncp
);
552 storage
->rx_packets
= hw_stats
->rx_packets
;
553 storage
->tx_packets
= hw_stats
->tx_packets
;
554 storage
->rx_bytes
= hw_stats
->rx_bytes
;
555 storage
->tx_bytes
= hw_stats
->tx_bytes
;
556 storage
->collisions
= hw_stats
->tx_collisions
;
557 storage
->rx_length_errors
= hw_stats
->rx_short_errors
+
558 hw_stats
->rx_long_errors
;
559 storage
->rx_over_errors
= hw_stats
->rx_overflow
;
560 storage
->rx_crc_errors
= hw_stats
->rx_fcs_errors
;
561 storage
->rx_errors
= hw_stats
->rx_checksum_errors
;
562 storage
->tx_aborted_errors
= hw_stats
->tx_skip
;
563 } while (u64_stats_fetch_retry_irq(&hw_stats
->syncp
, start
));
565 storage
->tx_errors
= dev
->stats
.tx_errors
;
566 storage
->rx_dropped
= dev
->stats
.rx_dropped
;
567 storage
->tx_dropped
= dev
->stats
.tx_dropped
;
570 static inline int mtk_max_frag_size(int mtu
)
572 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
573 if (mtu
+ MTK_RX_ETH_HLEN
< MTK_MAX_RX_LENGTH
)
574 mtu
= MTK_MAX_RX_LENGTH
- MTK_RX_ETH_HLEN
;
576 return SKB_DATA_ALIGN(MTK_RX_HLEN
+ mtu
) +
577 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
580 static inline int mtk_max_buf_size(int frag_size
)
582 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
583 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
585 WARN_ON(buf_size
< MTK_MAX_RX_LENGTH
);
590 static inline void mtk_rx_get_desc(struct mtk_rx_dma
*rxd
,
591 struct mtk_rx_dma
*dma_rxd
)
593 rxd
->rxd1
= READ_ONCE(dma_rxd
->rxd1
);
594 rxd
->rxd2
= READ_ONCE(dma_rxd
->rxd2
);
595 rxd
->rxd3
= READ_ONCE(dma_rxd
->rxd3
);
596 rxd
->rxd4
= READ_ONCE(dma_rxd
->rxd4
);
599 /* the qdma core needs scratch memory to be setup */
600 static int mtk_init_fq_dma(struct mtk_eth
*eth
)
602 dma_addr_t phy_ring_tail
;
603 int cnt
= MTK_DMA_SIZE
;
607 eth
->scratch_ring
= dma_alloc_coherent(eth
->dev
,
608 cnt
* sizeof(struct mtk_tx_dma
),
609 ð
->phy_scratch_ring
,
610 GFP_ATOMIC
| __GFP_ZERO
);
611 if (unlikely(!eth
->scratch_ring
))
614 eth
->scratch_head
= kcalloc(cnt
, MTK_QDMA_PAGE_SIZE
,
616 if (unlikely(!eth
->scratch_head
))
619 dma_addr
= dma_map_single(eth
->dev
,
620 eth
->scratch_head
, cnt
* MTK_QDMA_PAGE_SIZE
,
622 if (unlikely(dma_mapping_error(eth
->dev
, dma_addr
)))
625 memset(eth
->scratch_ring
, 0x0, sizeof(struct mtk_tx_dma
) * cnt
);
626 phy_ring_tail
= eth
->phy_scratch_ring
+
627 (sizeof(struct mtk_tx_dma
) * (cnt
- 1));
629 for (i
= 0; i
< cnt
; i
++) {
630 eth
->scratch_ring
[i
].txd1
=
631 (dma_addr
+ (i
* MTK_QDMA_PAGE_SIZE
));
633 eth
->scratch_ring
[i
].txd2
= (eth
->phy_scratch_ring
+
634 ((i
+ 1) * sizeof(struct mtk_tx_dma
)));
635 eth
->scratch_ring
[i
].txd3
= TX_DMA_SDL(MTK_QDMA_PAGE_SIZE
);
638 mtk_w32(eth
, eth
->phy_scratch_ring
, MTK_QDMA_FQ_HEAD
);
639 mtk_w32(eth
, phy_ring_tail
, MTK_QDMA_FQ_TAIL
);
640 mtk_w32(eth
, (cnt
<< 16) | cnt
, MTK_QDMA_FQ_CNT
);
641 mtk_w32(eth
, MTK_QDMA_PAGE_SIZE
<< 16, MTK_QDMA_FQ_BLEN
);
646 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring
*ring
, u32 desc
)
648 void *ret
= ring
->dma
;
650 return ret
+ (desc
- ring
->phys
);
653 static inline struct mtk_tx_buf
*mtk_desc_to_tx_buf(struct mtk_tx_ring
*ring
,
654 struct mtk_tx_dma
*txd
)
656 int idx
= txd
- ring
->dma
;
658 return &ring
->buf
[idx
];
661 static void mtk_tx_unmap(struct mtk_eth
*eth
, struct mtk_tx_buf
*tx_buf
)
663 if (tx_buf
->flags
& MTK_TX_FLAGS_SINGLE0
) {
664 dma_unmap_single(eth
->dev
,
665 dma_unmap_addr(tx_buf
, dma_addr0
),
666 dma_unmap_len(tx_buf
, dma_len0
),
668 } else if (tx_buf
->flags
& MTK_TX_FLAGS_PAGE0
) {
669 dma_unmap_page(eth
->dev
,
670 dma_unmap_addr(tx_buf
, dma_addr0
),
671 dma_unmap_len(tx_buf
, dma_len0
),
676 (tx_buf
->skb
!= (struct sk_buff
*)MTK_DMA_DUMMY_DESC
))
677 dev_kfree_skb_any(tx_buf
->skb
);
681 static int mtk_tx_map(struct sk_buff
*skb
, struct net_device
*dev
,
682 int tx_num
, struct mtk_tx_ring
*ring
, bool gso
)
684 struct mtk_mac
*mac
= netdev_priv(dev
);
685 struct mtk_eth
*eth
= mac
->hw
;
686 struct mtk_tx_dma
*itxd
, *txd
;
687 struct mtk_tx_buf
*itx_buf
, *tx_buf
;
688 dma_addr_t mapped_addr
;
689 unsigned int nr_frags
;
693 itxd
= ring
->next_free
;
694 if (itxd
== ring
->last_free
)
697 /* set the forward port */
698 fport
= (mac
->id
+ 1) << TX_DMA_FPORT_SHIFT
;
701 itx_buf
= mtk_desc_to_tx_buf(ring
, itxd
);
702 memset(itx_buf
, 0, sizeof(*itx_buf
));
707 /* TX Checksum offload */
708 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
709 txd4
|= TX_DMA_CHKSUM
;
711 /* VLAN header offload */
712 if (skb_vlan_tag_present(skb
))
713 txd4
|= TX_DMA_INS_VLAN
| skb_vlan_tag_get(skb
);
715 mapped_addr
= dma_map_single(eth
->dev
, skb
->data
,
716 skb_headlen(skb
), DMA_TO_DEVICE
);
717 if (unlikely(dma_mapping_error(eth
->dev
, mapped_addr
)))
720 WRITE_ONCE(itxd
->txd1
, mapped_addr
);
721 itx_buf
->flags
|= MTK_TX_FLAGS_SINGLE0
;
722 itx_buf
->flags
|= (!mac
->id
) ? MTK_TX_FLAGS_FPORT0
:
724 dma_unmap_addr_set(itx_buf
, dma_addr0
, mapped_addr
);
725 dma_unmap_len_set(itx_buf
, dma_len0
, skb_headlen(skb
));
729 nr_frags
= skb_shinfo(skb
)->nr_frags
;
730 for (i
= 0; i
< nr_frags
; i
++) {
731 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
732 unsigned int offset
= 0;
733 int frag_size
= skb_frag_size(frag
);
736 bool last_frag
= false;
737 unsigned int frag_map_size
;
739 txd
= mtk_qdma_phys_to_virt(ring
, txd
->txd2
);
740 if (txd
== ring
->last_free
)
744 frag_map_size
= min(frag_size
, MTK_TX_DMA_BUF_LEN
);
745 mapped_addr
= skb_frag_dma_map(eth
->dev
, frag
, offset
,
748 if (unlikely(dma_mapping_error(eth
->dev
, mapped_addr
)))
751 if (i
== nr_frags
- 1 &&
752 (frag_size
- frag_map_size
) == 0)
755 WRITE_ONCE(txd
->txd1
, mapped_addr
);
756 WRITE_ONCE(txd
->txd3
, (TX_DMA_SWC
|
757 TX_DMA_PLEN0(frag_map_size
) |
758 last_frag
* TX_DMA_LS0
));
759 WRITE_ONCE(txd
->txd4
, fport
);
761 tx_buf
= mtk_desc_to_tx_buf(ring
, txd
);
762 memset(tx_buf
, 0, sizeof(*tx_buf
));
763 tx_buf
->skb
= (struct sk_buff
*)MTK_DMA_DUMMY_DESC
;
764 tx_buf
->flags
|= MTK_TX_FLAGS_PAGE0
;
765 tx_buf
->flags
|= (!mac
->id
) ? MTK_TX_FLAGS_FPORT0
:
768 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
769 dma_unmap_len_set(tx_buf
, dma_len0
, frag_map_size
);
770 frag_size
-= frag_map_size
;
771 offset
+= frag_map_size
;
775 /* store skb to cleanup */
778 WRITE_ONCE(itxd
->txd4
, txd4
);
779 WRITE_ONCE(itxd
->txd3
, (TX_DMA_SWC
| TX_DMA_PLEN0(skb_headlen(skb
)) |
780 (!nr_frags
* TX_DMA_LS0
)));
782 netdev_sent_queue(dev
, skb
->len
);
783 skb_tx_timestamp(skb
);
785 ring
->next_free
= mtk_qdma_phys_to_virt(ring
, txd
->txd2
);
786 atomic_sub(n_desc
, &ring
->free_count
);
788 /* make sure that all changes to the dma ring are flushed before we
793 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !skb
->xmit_more
)
794 mtk_w32(eth
, txd
->txd2
, MTK_QTX_CTX_PTR
);
800 tx_buf
= mtk_desc_to_tx_buf(ring
, itxd
);
803 mtk_tx_unmap(eth
, tx_buf
);
805 itxd
->txd3
= TX_DMA_LS0
| TX_DMA_OWNER_CPU
;
806 itxd
= mtk_qdma_phys_to_virt(ring
, itxd
->txd2
);
807 } while (itxd
!= txd
);
812 static inline int mtk_cal_txd_req(struct sk_buff
*skb
)
815 struct skb_frag_struct
*frag
;
818 if (skb_is_gso(skb
)) {
819 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
820 frag
= &skb_shinfo(skb
)->frags
[i
];
821 nfrags
+= DIV_ROUND_UP(frag
->size
, MTK_TX_DMA_BUF_LEN
);
824 nfrags
+= skb_shinfo(skb
)->nr_frags
;
830 static int mtk_queue_stopped(struct mtk_eth
*eth
)
834 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
837 if (netif_queue_stopped(eth
->netdev
[i
]))
844 static void mtk_wake_queue(struct mtk_eth
*eth
)
848 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
851 netif_wake_queue(eth
->netdev
[i
]);
855 static void mtk_stop_queue(struct mtk_eth
*eth
)
859 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
862 netif_stop_queue(eth
->netdev
[i
]);
866 static int mtk_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
868 struct mtk_mac
*mac
= netdev_priv(dev
);
869 struct mtk_eth
*eth
= mac
->hw
;
870 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
871 struct net_device_stats
*stats
= &dev
->stats
;
875 /* normally we can rely on the stack not calling this more than once,
876 * however we have 2 queues running on the same ring so we need to lock
879 spin_lock(ð
->page_lock
);
881 if (unlikely(test_bit(MTK_RESETTING
, ð
->state
)))
884 tx_num
= mtk_cal_txd_req(skb
);
885 if (unlikely(atomic_read(&ring
->free_count
) <= tx_num
)) {
887 netif_err(eth
, tx_queued
, dev
,
888 "Tx Ring full when queue awake!\n");
889 spin_unlock(ð
->page_lock
);
890 return NETDEV_TX_BUSY
;
893 /* TSO: fill MSS info in tcp checksum field */
894 if (skb_is_gso(skb
)) {
895 if (skb_cow_head(skb
, 0)) {
896 netif_warn(eth
, tx_err
, dev
,
897 "GSO expand head fail.\n");
901 if (skb_shinfo(skb
)->gso_type
&
902 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
904 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
908 if (mtk_tx_map(skb
, dev
, tx_num
, ring
, gso
) < 0)
911 if (unlikely(atomic_read(&ring
->free_count
) <= ring
->thresh
))
914 spin_unlock(ð
->page_lock
);
919 spin_unlock(ð
->page_lock
);
921 dev_kfree_skb_any(skb
);
925 static struct mtk_rx_ring
*mtk_get_rx_ring(struct mtk_eth
*eth
)
928 struct mtk_rx_ring
*ring
;
932 return ð
->rx_ring
[0];
934 for (i
= 0; i
< MTK_MAX_RX_RING_NUM
; i
++) {
935 ring
= ð
->rx_ring
[i
];
936 idx
= NEXT_RX_DESP_IDX(ring
->calc_idx
, ring
->dma_size
);
937 if (ring
->dma
[idx
].rxd2
& RX_DMA_DONE
) {
938 ring
->calc_idx_update
= true;
946 static void mtk_update_rx_cpu_idx(struct mtk_eth
*eth
)
948 struct mtk_rx_ring
*ring
;
952 ring
= ð
->rx_ring
[0];
953 mtk_w32(eth
, ring
->calc_idx
, ring
->crx_idx_reg
);
955 for (i
= 0; i
< MTK_MAX_RX_RING_NUM
; i
++) {
956 ring
= ð
->rx_ring
[i
];
957 if (ring
->calc_idx_update
) {
958 ring
->calc_idx_update
= false;
959 mtk_w32(eth
, ring
->calc_idx
, ring
->crx_idx_reg
);
965 static int mtk_poll_rx(struct napi_struct
*napi
, int budget
,
968 struct mtk_rx_ring
*ring
;
972 struct mtk_rx_dma
*rxd
, trxd
;
975 while (done
< budget
) {
976 struct net_device
*netdev
;
981 ring
= mtk_get_rx_ring(eth
);
985 idx
= NEXT_RX_DESP_IDX(ring
->calc_idx
, ring
->dma_size
);
986 rxd
= &ring
->dma
[idx
];
987 data
= ring
->data
[idx
];
989 mtk_rx_get_desc(&trxd
, rxd
);
990 if (!(trxd
.rxd2
& RX_DMA_DONE
))
993 /* find out which mac the packet come from. values start at 1 */
994 mac
= (trxd
.rxd4
>> RX_DMA_FPORT_SHIFT
) &
998 if (unlikely(mac
< 0 || mac
>= MTK_MAC_COUNT
||
1002 netdev
= eth
->netdev
[mac
];
1004 if (unlikely(test_bit(MTK_RESETTING
, ð
->state
)))
1007 /* alloc new buffer */
1008 new_data
= napi_alloc_frag(ring
->frag_size
);
1009 if (unlikely(!new_data
)) {
1010 netdev
->stats
.rx_dropped
++;
1013 dma_addr
= dma_map_single(eth
->dev
,
1014 new_data
+ NET_SKB_PAD
,
1017 if (unlikely(dma_mapping_error(eth
->dev
, dma_addr
))) {
1018 skb_free_frag(new_data
);
1019 netdev
->stats
.rx_dropped
++;
1024 skb
= build_skb(data
, ring
->frag_size
);
1025 if (unlikely(!skb
)) {
1026 skb_free_frag(new_data
);
1027 netdev
->stats
.rx_dropped
++;
1030 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
1032 dma_unmap_single(eth
->dev
, trxd
.rxd1
,
1033 ring
->buf_size
, DMA_FROM_DEVICE
);
1034 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
1036 skb_put(skb
, pktlen
);
1037 if (trxd
.rxd4
& RX_DMA_L4_VALID
)
1038 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1040 skb_checksum_none_assert(skb
);
1041 skb
->protocol
= eth_type_trans(skb
, netdev
);
1043 if (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
1044 RX_DMA_VID(trxd
.rxd3
))
1045 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
1046 RX_DMA_VID(trxd
.rxd3
));
1047 skb_record_rx_queue(skb
, 0);
1048 napi_gro_receive(napi
, skb
);
1050 ring
->data
[idx
] = new_data
;
1051 rxd
->rxd1
= (unsigned int)dma_addr
;
1054 rxd
->rxd2
= RX_DMA_PLEN0(ring
->buf_size
);
1056 ring
->calc_idx
= idx
;
1063 /* make sure that all changes to the dma ring are flushed before
1067 mtk_update_rx_cpu_idx(eth
);
1073 static int mtk_poll_tx(struct mtk_eth
*eth
, int budget
)
1075 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
1076 struct mtk_tx_dma
*desc
;
1077 struct sk_buff
*skb
;
1078 struct mtk_tx_buf
*tx_buf
;
1079 unsigned int done
[MTK_MAX_DEVS
];
1080 unsigned int bytes
[MTK_MAX_DEVS
];
1084 memset(done
, 0, sizeof(done
));
1085 memset(bytes
, 0, sizeof(bytes
));
1087 cpu
= mtk_r32(eth
, MTK_QTX_CRX_PTR
);
1088 dma
= mtk_r32(eth
, MTK_QTX_DRX_PTR
);
1090 desc
= mtk_qdma_phys_to_virt(ring
, cpu
);
1092 while ((cpu
!= dma
) && budget
) {
1093 u32 next_cpu
= desc
->txd2
;
1096 desc
= mtk_qdma_phys_to_virt(ring
, desc
->txd2
);
1097 if ((desc
->txd3
& TX_DMA_OWNER_CPU
) == 0)
1100 tx_buf
= mtk_desc_to_tx_buf(ring
, desc
);
1101 if (tx_buf
->flags
& MTK_TX_FLAGS_FPORT1
)
1108 if (skb
!= (struct sk_buff
*)MTK_DMA_DUMMY_DESC
) {
1109 bytes
[mac
] += skb
->len
;
1113 mtk_tx_unmap(eth
, tx_buf
);
1115 ring
->last_free
= desc
;
1116 atomic_inc(&ring
->free_count
);
1121 mtk_w32(eth
, cpu
, MTK_QTX_CRX_PTR
);
1123 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
1124 if (!eth
->netdev
[i
] || !done
[i
])
1126 netdev_completed_queue(eth
->netdev
[i
], done
[i
], bytes
[i
]);
1130 if (mtk_queue_stopped(eth
) &&
1131 (atomic_read(&ring
->free_count
) > ring
->thresh
))
1132 mtk_wake_queue(eth
);
1137 static void mtk_handle_status_irq(struct mtk_eth
*eth
)
1139 u32 status2
= mtk_r32(eth
, MTK_INT_STATUS2
);
1141 if (unlikely(status2
& (MTK_GDM1_AF
| MTK_GDM2_AF
))) {
1142 mtk_stats_update(eth
);
1143 mtk_w32(eth
, (MTK_GDM1_AF
| MTK_GDM2_AF
),
1148 static int mtk_napi_tx(struct napi_struct
*napi
, int budget
)
1150 struct mtk_eth
*eth
= container_of(napi
, struct mtk_eth
, tx_napi
);
1154 mtk_handle_status_irq(eth
);
1155 mtk_w32(eth
, MTK_TX_DONE_INT
, MTK_QMTK_INT_STATUS
);
1156 tx_done
= mtk_poll_tx(eth
, budget
);
1158 if (unlikely(netif_msg_intr(eth
))) {
1159 status
= mtk_r32(eth
, MTK_QMTK_INT_STATUS
);
1160 mask
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
1162 "done tx %d, intr 0x%08x/0x%x\n",
1163 tx_done
, status
, mask
);
1166 if (tx_done
== budget
)
1169 status
= mtk_r32(eth
, MTK_QMTK_INT_STATUS
);
1170 if (status
& MTK_TX_DONE_INT
)
1173 napi_complete(napi
);
1174 mtk_tx_irq_enable(eth
, MTK_TX_DONE_INT
);
1179 static int mtk_napi_rx(struct napi_struct
*napi
, int budget
)
1181 struct mtk_eth
*eth
= container_of(napi
, struct mtk_eth
, rx_napi
);
1184 int remain_budget
= budget
;
1186 mtk_handle_status_irq(eth
);
1189 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_PDMA_INT_STATUS
);
1190 rx_done
= mtk_poll_rx(napi
, remain_budget
, eth
);
1192 if (unlikely(netif_msg_intr(eth
))) {
1193 status
= mtk_r32(eth
, MTK_PDMA_INT_STATUS
);
1194 mask
= mtk_r32(eth
, MTK_PDMA_INT_MASK
);
1196 "done rx %d, intr 0x%08x/0x%x\n",
1197 rx_done
, status
, mask
);
1199 if (rx_done
== remain_budget
)
1202 status
= mtk_r32(eth
, MTK_PDMA_INT_STATUS
);
1203 if (status
& MTK_RX_DONE_INT
) {
1204 remain_budget
-= rx_done
;
1207 napi_complete(napi
);
1208 mtk_rx_irq_enable(eth
, MTK_RX_DONE_INT
);
1210 return rx_done
+ budget
- remain_budget
;
1213 static int mtk_tx_alloc(struct mtk_eth
*eth
)
1215 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
1216 int i
, sz
= sizeof(*ring
->dma
);
1218 ring
->buf
= kcalloc(MTK_DMA_SIZE
, sizeof(*ring
->buf
),
1223 ring
->dma
= dma_alloc_coherent(eth
->dev
,
1226 GFP_ATOMIC
| __GFP_ZERO
);
1230 memset(ring
->dma
, 0, MTK_DMA_SIZE
* sz
);
1231 for (i
= 0; i
< MTK_DMA_SIZE
; i
++) {
1232 int next
= (i
+ 1) % MTK_DMA_SIZE
;
1233 u32 next_ptr
= ring
->phys
+ next
* sz
;
1235 ring
->dma
[i
].txd2
= next_ptr
;
1236 ring
->dma
[i
].txd3
= TX_DMA_LS0
| TX_DMA_OWNER_CPU
;
1239 atomic_set(&ring
->free_count
, MTK_DMA_SIZE
- 2);
1240 ring
->next_free
= &ring
->dma
[0];
1241 ring
->last_free
= &ring
->dma
[MTK_DMA_SIZE
- 1];
1242 ring
->thresh
= MAX_SKB_FRAGS
;
1244 /* make sure that all changes to the dma ring are flushed before we
1249 mtk_w32(eth
, ring
->phys
, MTK_QTX_CTX_PTR
);
1250 mtk_w32(eth
, ring
->phys
, MTK_QTX_DTX_PTR
);
1252 ring
->phys
+ ((MTK_DMA_SIZE
- 1) * sz
),
1255 ring
->phys
+ ((MTK_DMA_SIZE
- 1) * sz
),
1257 mtk_w32(eth
, (QDMA_RES_THRES
<< 8) | QDMA_RES_THRES
, MTK_QTX_CFG(0));
1265 static void mtk_tx_clean(struct mtk_eth
*eth
)
1267 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
1271 for (i
= 0; i
< MTK_DMA_SIZE
; i
++)
1272 mtk_tx_unmap(eth
, &ring
->buf
[i
]);
1278 dma_free_coherent(eth
->dev
,
1279 MTK_DMA_SIZE
* sizeof(*ring
->dma
),
1286 static int mtk_rx_alloc(struct mtk_eth
*eth
, int ring_no
, int rx_flag
)
1288 struct mtk_rx_ring
*ring
;
1289 int rx_data_len
, rx_dma_size
;
1293 if (rx_flag
== MTK_RX_FLAGS_QDMA
) {
1296 ring
= ð
->rx_ring_qdma
;
1299 ring
= ð
->rx_ring
[ring_no
];
1302 if (rx_flag
== MTK_RX_FLAGS_HWLRO
) {
1303 rx_data_len
= MTK_MAX_LRO_RX_LENGTH
;
1304 rx_dma_size
= MTK_HW_LRO_DMA_SIZE
;
1306 rx_data_len
= ETH_DATA_LEN
;
1307 rx_dma_size
= MTK_DMA_SIZE
;
1310 ring
->frag_size
= mtk_max_frag_size(rx_data_len
);
1311 ring
->buf_size
= mtk_max_buf_size(ring
->frag_size
);
1312 ring
->data
= kcalloc(rx_dma_size
, sizeof(*ring
->data
),
1317 for (i
= 0; i
< rx_dma_size
; i
++) {
1318 ring
->data
[i
] = netdev_alloc_frag(ring
->frag_size
);
1323 ring
->dma
= dma_alloc_coherent(eth
->dev
,
1324 rx_dma_size
* sizeof(*ring
->dma
),
1326 GFP_ATOMIC
| __GFP_ZERO
);
1330 for (i
= 0; i
< rx_dma_size
; i
++) {
1331 dma_addr_t dma_addr
= dma_map_single(eth
->dev
,
1332 ring
->data
[i
] + NET_SKB_PAD
,
1335 if (unlikely(dma_mapping_error(eth
->dev
, dma_addr
)))
1337 ring
->dma
[i
].rxd1
= (unsigned int)dma_addr
;
1339 ring
->dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->buf_size
);
1341 ring
->dma_size
= rx_dma_size
;
1342 ring
->calc_idx_update
= false;
1343 ring
->calc_idx
= rx_dma_size
- 1;
1344 ring
->crx_idx_reg
= MTK_PRX_CRX_IDX_CFG(ring_no
);
1345 /* make sure that all changes to the dma ring are flushed before we
1350 mtk_w32(eth
, ring
->phys
, MTK_PRX_BASE_PTR_CFG(ring_no
) + offset
);
1351 mtk_w32(eth
, rx_dma_size
, MTK_PRX_MAX_CNT_CFG(ring_no
) + offset
);
1352 mtk_w32(eth
, ring
->calc_idx
, ring
->crx_idx_reg
+ offset
);
1353 mtk_w32(eth
, MTK_PST_DRX_IDX_CFG(ring_no
), MTK_PDMA_RST_IDX
+ offset
);
1358 static void mtk_rx_clean(struct mtk_eth
*eth
, struct mtk_rx_ring
*ring
)
1362 if (ring
->data
&& ring
->dma
) {
1363 for (i
= 0; i
< ring
->dma_size
; i
++) {
1366 if (!ring
->dma
[i
].rxd1
)
1368 dma_unmap_single(eth
->dev
,
1372 skb_free_frag(ring
->data
[i
]);
1379 dma_free_coherent(eth
->dev
,
1380 ring
->dma_size
* sizeof(*ring
->dma
),
1387 static int mtk_hwlro_rx_init(struct mtk_eth
*eth
)
1390 u32 ring_ctrl_dw1
= 0, ring_ctrl_dw2
= 0, ring_ctrl_dw3
= 0;
1391 u32 lro_ctrl_dw0
= 0, lro_ctrl_dw3
= 0;
1393 /* set LRO rings to auto-learn modes */
1394 ring_ctrl_dw2
|= MTK_RING_AUTO_LERAN_MODE
;
1396 /* validate LRO ring */
1397 ring_ctrl_dw2
|= MTK_RING_VLD
;
1399 /* set AGE timer (unit: 20us) */
1400 ring_ctrl_dw2
|= MTK_RING_AGE_TIME_H
;
1401 ring_ctrl_dw1
|= MTK_RING_AGE_TIME_L
;
1403 /* set max AGG timer (unit: 20us) */
1404 ring_ctrl_dw2
|= MTK_RING_MAX_AGG_TIME
;
1406 /* set max LRO AGG count */
1407 ring_ctrl_dw2
|= MTK_RING_MAX_AGG_CNT_L
;
1408 ring_ctrl_dw3
|= MTK_RING_MAX_AGG_CNT_H
;
1410 for (i
= 1; i
< MTK_MAX_RX_RING_NUM
; i
++) {
1411 mtk_w32(eth
, ring_ctrl_dw1
, MTK_LRO_CTRL_DW1_CFG(i
));
1412 mtk_w32(eth
, ring_ctrl_dw2
, MTK_LRO_CTRL_DW2_CFG(i
));
1413 mtk_w32(eth
, ring_ctrl_dw3
, MTK_LRO_CTRL_DW3_CFG(i
));
1416 /* IPv4 checksum update enable */
1417 lro_ctrl_dw0
|= MTK_L3_CKS_UPD_EN
;
1419 /* switch priority comparison to packet count mode */
1420 lro_ctrl_dw0
|= MTK_LRO_ALT_PKT_CNT_MODE
;
1422 /* bandwidth threshold setting */
1423 mtk_w32(eth
, MTK_HW_LRO_BW_THRE
, MTK_PDMA_LRO_CTRL_DW2
);
1425 /* auto-learn score delta setting */
1426 mtk_w32(eth
, MTK_HW_LRO_REPLACE_DELTA
, MTK_PDMA_LRO_ALT_SCORE_DELTA
);
1428 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1429 mtk_w32(eth
, (MTK_HW_LRO_TIMER_UNIT
<< 16) | MTK_HW_LRO_REFRESH_TIME
,
1430 MTK_PDMA_LRO_ALT_REFRESH_TIMER
);
1432 /* set HW LRO mode & the max aggregation count for rx packets */
1433 lro_ctrl_dw3
|= MTK_ADMA_MODE
| (MTK_HW_LRO_MAX_AGG_CNT
& 0xff);
1435 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1436 lro_ctrl_dw3
|= MTK_LRO_MIN_RXD_SDL
;
1439 lro_ctrl_dw0
|= MTK_LRO_EN
;
1441 mtk_w32(eth
, lro_ctrl_dw3
, MTK_PDMA_LRO_CTRL_DW3
);
1442 mtk_w32(eth
, lro_ctrl_dw0
, MTK_PDMA_LRO_CTRL_DW0
);
1447 static void mtk_hwlro_rx_uninit(struct mtk_eth
*eth
)
1452 /* relinquish lro rings, flush aggregated packets */
1453 mtk_w32(eth
, MTK_LRO_RING_RELINQUISH_REQ
, MTK_PDMA_LRO_CTRL_DW0
);
1455 /* wait for relinquishments done */
1456 for (i
= 0; i
< 10; i
++) {
1457 val
= mtk_r32(eth
, MTK_PDMA_LRO_CTRL_DW0
);
1458 if (val
& MTK_LRO_RING_RELINQUISH_DONE
) {
1465 /* invalidate lro rings */
1466 for (i
= 1; i
< MTK_MAX_RX_RING_NUM
; i
++)
1467 mtk_w32(eth
, 0, MTK_LRO_CTRL_DW2_CFG(i
));
1469 /* disable HW LRO */
1470 mtk_w32(eth
, 0, MTK_PDMA_LRO_CTRL_DW0
);
1473 static void mtk_hwlro_val_ipaddr(struct mtk_eth
*eth
, int idx
, __be32 ip
)
1477 reg_val
= mtk_r32(eth
, MTK_LRO_CTRL_DW2_CFG(idx
));
1479 /* invalidate the IP setting */
1480 mtk_w32(eth
, (reg_val
& ~MTK_RING_MYIP_VLD
), MTK_LRO_CTRL_DW2_CFG(idx
));
1482 mtk_w32(eth
, ip
, MTK_LRO_DIP_DW0_CFG(idx
));
1484 /* validate the IP setting */
1485 mtk_w32(eth
, (reg_val
| MTK_RING_MYIP_VLD
), MTK_LRO_CTRL_DW2_CFG(idx
));
1488 static void mtk_hwlro_inval_ipaddr(struct mtk_eth
*eth
, int idx
)
1492 reg_val
= mtk_r32(eth
, MTK_LRO_CTRL_DW2_CFG(idx
));
1494 /* invalidate the IP setting */
1495 mtk_w32(eth
, (reg_val
& ~MTK_RING_MYIP_VLD
), MTK_LRO_CTRL_DW2_CFG(idx
));
1497 mtk_w32(eth
, 0, MTK_LRO_DIP_DW0_CFG(idx
));
1500 static int mtk_hwlro_get_ip_cnt(struct mtk_mac
*mac
)
1505 for (i
= 0; i
< MTK_MAX_LRO_IP_CNT
; i
++) {
1506 if (mac
->hwlro_ip
[i
])
1513 static int mtk_hwlro_add_ipaddr(struct net_device
*dev
,
1514 struct ethtool_rxnfc
*cmd
)
1516 struct ethtool_rx_flow_spec
*fsp
=
1517 (struct ethtool_rx_flow_spec
*)&cmd
->fs
;
1518 struct mtk_mac
*mac
= netdev_priv(dev
);
1519 struct mtk_eth
*eth
= mac
->hw
;
1522 if ((fsp
->flow_type
!= TCP_V4_FLOW
) ||
1523 (!fsp
->h_u
.tcp_ip4_spec
.ip4dst
) ||
1524 (fsp
->location
> 1))
1527 mac
->hwlro_ip
[fsp
->location
] = htonl(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
1528 hwlro_idx
= (mac
->id
* MTK_MAX_LRO_IP_CNT
) + fsp
->location
;
1530 mac
->hwlro_ip_cnt
= mtk_hwlro_get_ip_cnt(mac
);
1532 mtk_hwlro_val_ipaddr(eth
, hwlro_idx
, mac
->hwlro_ip
[fsp
->location
]);
1537 static int mtk_hwlro_del_ipaddr(struct net_device
*dev
,
1538 struct ethtool_rxnfc
*cmd
)
1540 struct ethtool_rx_flow_spec
*fsp
=
1541 (struct ethtool_rx_flow_spec
*)&cmd
->fs
;
1542 struct mtk_mac
*mac
= netdev_priv(dev
);
1543 struct mtk_eth
*eth
= mac
->hw
;
1546 if (fsp
->location
> 1)
1549 mac
->hwlro_ip
[fsp
->location
] = 0;
1550 hwlro_idx
= (mac
->id
* MTK_MAX_LRO_IP_CNT
) + fsp
->location
;
1552 mac
->hwlro_ip_cnt
= mtk_hwlro_get_ip_cnt(mac
);
1554 mtk_hwlro_inval_ipaddr(eth
, hwlro_idx
);
1559 static void mtk_hwlro_netdev_disable(struct net_device
*dev
)
1561 struct mtk_mac
*mac
= netdev_priv(dev
);
1562 struct mtk_eth
*eth
= mac
->hw
;
1565 for (i
= 0; i
< MTK_MAX_LRO_IP_CNT
; i
++) {
1566 mac
->hwlro_ip
[i
] = 0;
1567 hwlro_idx
= (mac
->id
* MTK_MAX_LRO_IP_CNT
) + i
;
1569 mtk_hwlro_inval_ipaddr(eth
, hwlro_idx
);
1572 mac
->hwlro_ip_cnt
= 0;
1575 static int mtk_hwlro_get_fdir_entry(struct net_device
*dev
,
1576 struct ethtool_rxnfc
*cmd
)
1578 struct mtk_mac
*mac
= netdev_priv(dev
);
1579 struct ethtool_rx_flow_spec
*fsp
=
1580 (struct ethtool_rx_flow_spec
*)&cmd
->fs
;
1582 /* only tcp dst ipv4 is meaningful, others are meaningless */
1583 fsp
->flow_type
= TCP_V4_FLOW
;
1584 fsp
->h_u
.tcp_ip4_spec
.ip4dst
= ntohl(mac
->hwlro_ip
[fsp
->location
]);
1585 fsp
->m_u
.tcp_ip4_spec
.ip4dst
= 0;
1587 fsp
->h_u
.tcp_ip4_spec
.ip4src
= 0;
1588 fsp
->m_u
.tcp_ip4_spec
.ip4src
= 0xffffffff;
1589 fsp
->h_u
.tcp_ip4_spec
.psrc
= 0;
1590 fsp
->m_u
.tcp_ip4_spec
.psrc
= 0xffff;
1591 fsp
->h_u
.tcp_ip4_spec
.pdst
= 0;
1592 fsp
->m_u
.tcp_ip4_spec
.pdst
= 0xffff;
1593 fsp
->h_u
.tcp_ip4_spec
.tos
= 0;
1594 fsp
->m_u
.tcp_ip4_spec
.tos
= 0xff;
1599 static int mtk_hwlro_get_fdir_all(struct net_device
*dev
,
1600 struct ethtool_rxnfc
*cmd
,
1603 struct mtk_mac
*mac
= netdev_priv(dev
);
1607 for (i
= 0; i
< MTK_MAX_LRO_IP_CNT
; i
++) {
1608 if (mac
->hwlro_ip
[i
]) {
1614 cmd
->rule_cnt
= cnt
;
1619 static netdev_features_t
mtk_fix_features(struct net_device
*dev
,
1620 netdev_features_t features
)
1622 if (!(features
& NETIF_F_LRO
)) {
1623 struct mtk_mac
*mac
= netdev_priv(dev
);
1624 int ip_cnt
= mtk_hwlro_get_ip_cnt(mac
);
1627 netdev_info(dev
, "RX flow is programmed, LRO should keep on\n");
1629 features
|= NETIF_F_LRO
;
1636 static int mtk_set_features(struct net_device
*dev
, netdev_features_t features
)
1640 if (!((dev
->features
^ features
) & NETIF_F_LRO
))
1643 if (!(features
& NETIF_F_LRO
))
1644 mtk_hwlro_netdev_disable(dev
);
1649 /* wait for DMA to finish whatever it is doing before we start using it again */
1650 static int mtk_dma_busy_wait(struct mtk_eth
*eth
)
1652 unsigned long t_start
= jiffies
;
1655 if (!(mtk_r32(eth
, MTK_QDMA_GLO_CFG
) &
1656 (MTK_RX_DMA_BUSY
| MTK_TX_DMA_BUSY
)))
1658 if (time_after(jiffies
, t_start
+ MTK_DMA_BUSY_TIMEOUT
))
1662 dev_err(eth
->dev
, "DMA init timeout\n");
1666 static int mtk_dma_init(struct mtk_eth
*eth
)
1671 if (mtk_dma_busy_wait(eth
))
1674 /* QDMA needs scratch memory for internal reordering of the
1677 err
= mtk_init_fq_dma(eth
);
1681 err
= mtk_tx_alloc(eth
);
1685 err
= mtk_rx_alloc(eth
, 0, MTK_RX_FLAGS_QDMA
);
1689 err
= mtk_rx_alloc(eth
, 0, MTK_RX_FLAGS_NORMAL
);
1694 for (i
= 1; i
< MTK_MAX_RX_RING_NUM
; i
++) {
1695 err
= mtk_rx_alloc(eth
, i
, MTK_RX_FLAGS_HWLRO
);
1699 err
= mtk_hwlro_rx_init(eth
);
1704 /* Enable random early drop and set drop threshold automatically */
1705 mtk_w32(eth
, FC_THRES_DROP_MODE
| FC_THRES_DROP_EN
| FC_THRES_MIN
,
1707 mtk_w32(eth
, 0x0, MTK_QDMA_HRED2
);
1712 static void mtk_dma_free(struct mtk_eth
*eth
)
1716 for (i
= 0; i
< MTK_MAC_COUNT
; i
++)
1718 netdev_reset_queue(eth
->netdev
[i
]);
1719 if (eth
->scratch_ring
) {
1720 dma_free_coherent(eth
->dev
,
1721 MTK_DMA_SIZE
* sizeof(struct mtk_tx_dma
),
1723 eth
->phy_scratch_ring
);
1724 eth
->scratch_ring
= NULL
;
1725 eth
->phy_scratch_ring
= 0;
1728 mtk_rx_clean(eth
, ð
->rx_ring
[0]);
1729 mtk_rx_clean(eth
, ð
->rx_ring_qdma
);
1732 mtk_hwlro_rx_uninit(eth
);
1733 for (i
= 1; i
< MTK_MAX_RX_RING_NUM
; i
++)
1734 mtk_rx_clean(eth
, ð
->rx_ring
[i
]);
1737 kfree(eth
->scratch_head
);
1740 static void mtk_tx_timeout(struct net_device
*dev
)
1742 struct mtk_mac
*mac
= netdev_priv(dev
);
1743 struct mtk_eth
*eth
= mac
->hw
;
1745 eth
->netdev
[mac
->id
]->stats
.tx_errors
++;
1746 netif_err(eth
, tx_err
, dev
,
1747 "transmit timed out\n");
1748 schedule_work(ð
->pending_work
);
1751 static irqreturn_t
mtk_handle_irq_rx(int irq
, void *_eth
)
1753 struct mtk_eth
*eth
= _eth
;
1755 if (likely(napi_schedule_prep(ð
->rx_napi
))) {
1756 __napi_schedule(ð
->rx_napi
);
1757 mtk_rx_irq_disable(eth
, MTK_RX_DONE_INT
);
1763 static irqreturn_t
mtk_handle_irq_tx(int irq
, void *_eth
)
1765 struct mtk_eth
*eth
= _eth
;
1767 if (likely(napi_schedule_prep(ð
->tx_napi
))) {
1768 __napi_schedule(ð
->tx_napi
);
1769 mtk_tx_irq_disable(eth
, MTK_TX_DONE_INT
);
1775 #ifdef CONFIG_NET_POLL_CONTROLLER
1776 static void mtk_poll_controller(struct net_device
*dev
)
1778 struct mtk_mac
*mac
= netdev_priv(dev
);
1779 struct mtk_eth
*eth
= mac
->hw
;
1781 mtk_tx_irq_disable(eth
, MTK_TX_DONE_INT
);
1782 mtk_rx_irq_disable(eth
, MTK_RX_DONE_INT
);
1783 mtk_handle_irq_rx(eth
->irq
[2], dev
);
1784 mtk_tx_irq_enable(eth
, MTK_TX_DONE_INT
);
1785 mtk_rx_irq_enable(eth
, MTK_RX_DONE_INT
);
1789 static int mtk_start_dma(struct mtk_eth
*eth
)
1791 u32 rx_2b_offset
= (NET_IP_ALIGN
== 2) ? MTK_RX_2B_OFFSET
: 0;
1794 err
= mtk_dma_init(eth
);
1801 MTK_TX_WB_DDONE
| MTK_TX_DMA_EN
|
1802 MTK_DMA_SIZE_16DWORDS
| MTK_NDP_CO_PRO
|
1803 MTK_RX_DMA_EN
| MTK_RX_2B_OFFSET
|
1808 MTK_RX_DMA_EN
| rx_2b_offset
|
1809 MTK_RX_BT_32DWORDS
| MTK_MULTI_EN
,
1815 static int mtk_open(struct net_device
*dev
)
1817 struct mtk_mac
*mac
= netdev_priv(dev
);
1818 struct mtk_eth
*eth
= mac
->hw
;
1820 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1821 if (!refcount_read(ð
->dma_refcnt
)) {
1822 int err
= mtk_start_dma(eth
);
1827 napi_enable(ð
->tx_napi
);
1828 napi_enable(ð
->rx_napi
);
1829 mtk_tx_irq_enable(eth
, MTK_TX_DONE_INT
);
1830 mtk_rx_irq_enable(eth
, MTK_RX_DONE_INT
);
1831 refcount_set(ð
->dma_refcnt
, 1);
1834 refcount_inc(ð
->dma_refcnt
);
1836 phy_start(dev
->phydev
);
1837 netif_start_queue(dev
);
1842 static void mtk_stop_dma(struct mtk_eth
*eth
, u32 glo_cfg
)
1847 /* stop the dma engine */
1848 spin_lock_bh(ð
->page_lock
);
1849 val
= mtk_r32(eth
, glo_cfg
);
1850 mtk_w32(eth
, val
& ~(MTK_TX_WB_DDONE
| MTK_RX_DMA_EN
| MTK_TX_DMA_EN
),
1852 spin_unlock_bh(ð
->page_lock
);
1854 /* wait for dma stop */
1855 for (i
= 0; i
< 10; i
++) {
1856 val
= mtk_r32(eth
, glo_cfg
);
1857 if (val
& (MTK_TX_DMA_BUSY
| MTK_RX_DMA_BUSY
)) {
1865 static int mtk_stop(struct net_device
*dev
)
1867 struct mtk_mac
*mac
= netdev_priv(dev
);
1868 struct mtk_eth
*eth
= mac
->hw
;
1870 netif_tx_disable(dev
);
1871 phy_stop(dev
->phydev
);
1873 /* only shutdown DMA if this is the last user */
1874 if (!refcount_dec_and_test(ð
->dma_refcnt
))
1877 mtk_tx_irq_disable(eth
, MTK_TX_DONE_INT
);
1878 mtk_rx_irq_disable(eth
, MTK_RX_DONE_INT
);
1879 napi_disable(ð
->tx_napi
);
1880 napi_disable(ð
->rx_napi
);
1882 mtk_stop_dma(eth
, MTK_QDMA_GLO_CFG
);
1883 mtk_stop_dma(eth
, MTK_PDMA_GLO_CFG
);
1890 static void ethsys_reset(struct mtk_eth
*eth
, u32 reset_bits
)
1892 regmap_update_bits(eth
->ethsys
, ETHSYS_RSTCTRL
,
1896 usleep_range(1000, 1100);
1897 regmap_update_bits(eth
->ethsys
, ETHSYS_RSTCTRL
,
1903 static void mtk_clk_disable(struct mtk_eth
*eth
)
1907 for (clk
= MTK_CLK_MAX
- 1; clk
>= 0; clk
--)
1908 clk_disable_unprepare(eth
->clks
[clk
]);
1911 static int mtk_clk_enable(struct mtk_eth
*eth
)
1915 for (clk
= 0; clk
< MTK_CLK_MAX
; clk
++) {
1916 ret
= clk_prepare_enable(eth
->clks
[clk
]);
1918 goto err_disable_clks
;
1925 clk_disable_unprepare(eth
->clks
[clk
]);
1930 static int mtk_hw_init(struct mtk_eth
*eth
)
1934 if (test_and_set_bit(MTK_HW_INIT
, ð
->state
))
1937 pm_runtime_enable(eth
->dev
);
1938 pm_runtime_get_sync(eth
->dev
);
1940 ret
= mtk_clk_enable(eth
);
1942 goto err_disable_pm
;
1944 ethsys_reset(eth
, RSTCTRL_FE
);
1945 ethsys_reset(eth
, RSTCTRL_PPE
);
1947 regmap_read(eth
->ethsys
, ETHSYS_SYSCFG0
, &val
);
1948 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
1951 val
&= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK
, eth
->mac
[i
]->id
);
1952 val
|= SYSCFG0_GE_MODE(eth
->mac
[i
]->ge_mode
, eth
->mac
[i
]->id
);
1954 regmap_write(eth
->ethsys
, ETHSYS_SYSCFG0
, val
);
1956 /* Set GE2 driving and slew rate */
1957 regmap_write(eth
->pctl
, GPIO_DRV_SEL10
, 0xa00);
1960 regmap_write(eth
->pctl
, GPIO_OD33_CTRL8
, 0x5);
1963 regmap_write(eth
->pctl
, GPIO_BIAS_CTRL
, 0x0);
1965 /* Set linkdown as the default for each GMAC. Its own MCR would be set
1966 * up with the more appropriate value when mtk_phy_link_adjust call is
1969 for (i
= 0; i
< MTK_MAC_COUNT
; i
++)
1970 mtk_w32(eth
, 0, MTK_MAC_MCR(i
));
1972 /* Indicates CDM to parse the MTK special tag from CPU
1973 * which also is working out for untag packets.
1975 val
= mtk_r32(eth
, MTK_CDMQ_IG_CTRL
);
1976 mtk_w32(eth
, val
| MTK_CDMQ_STAG_EN
, MTK_CDMQ_IG_CTRL
);
1978 /* Enable RX VLan Offloading */
1979 mtk_w32(eth
, 1, MTK_CDMP_EG_CTRL
);
1981 /* enable interrupt delay for RX */
1982 mtk_w32(eth
, MTK_PDMA_DELAY_RX_DELAY
, MTK_PDMA_DELAY_INT
);
1984 /* disable delay and normal interrupt */
1985 mtk_w32(eth
, 0, MTK_QDMA_DELAY_INT
);
1986 mtk_tx_irq_disable(eth
, ~0);
1987 mtk_rx_irq_disable(eth
, ~0);
1988 mtk_w32(eth
, RST_GL_PSE
, MTK_RST_GL
);
1989 mtk_w32(eth
, 0, MTK_RST_GL
);
1991 /* FE int grouping */
1992 mtk_w32(eth
, MTK_TX_DONE_INT
, MTK_PDMA_INT_GRP1
);
1993 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_PDMA_INT_GRP2
);
1994 mtk_w32(eth
, MTK_TX_DONE_INT
, MTK_QDMA_INT_GRP1
);
1995 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_QDMA_INT_GRP2
);
1996 mtk_w32(eth
, 0x21021000, MTK_FE_INT_GRP
);
1998 for (i
= 0; i
< 2; i
++) {
1999 u32 val
= mtk_r32(eth
, MTK_GDMA_FWD_CFG(i
));
2001 /* setup the forward port to send frame to PDMA */
2004 /* Enable RX checksum */
2005 val
|= MTK_GDMA_ICS_EN
| MTK_GDMA_TCS_EN
| MTK_GDMA_UCS_EN
;
2007 /* setup the mac dma */
2008 mtk_w32(eth
, val
, MTK_GDMA_FWD_CFG(i
));
2014 pm_runtime_put_sync(eth
->dev
);
2015 pm_runtime_disable(eth
->dev
);
2020 static int mtk_hw_deinit(struct mtk_eth
*eth
)
2022 if (!test_and_clear_bit(MTK_HW_INIT
, ð
->state
))
2025 mtk_clk_disable(eth
);
2027 pm_runtime_put_sync(eth
->dev
);
2028 pm_runtime_disable(eth
->dev
);
2033 static int __init
mtk_init(struct net_device
*dev
)
2035 struct mtk_mac
*mac
= netdev_priv(dev
);
2036 struct mtk_eth
*eth
= mac
->hw
;
2037 const char *mac_addr
;
2039 mac_addr
= of_get_mac_address(mac
->of_node
);
2041 ether_addr_copy(dev
->dev_addr
, mac_addr
);
2043 /* If the mac address is invalid, use random mac address */
2044 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2045 eth_hw_addr_random(dev
);
2046 dev_err(eth
->dev
, "generated random MAC address %pM\n",
2050 return mtk_phy_connect(dev
);
2053 static void mtk_uninit(struct net_device
*dev
)
2055 struct mtk_mac
*mac
= netdev_priv(dev
);
2056 struct mtk_eth
*eth
= mac
->hw
;
2058 phy_disconnect(dev
->phydev
);
2059 if (of_phy_is_fixed_link(mac
->of_node
))
2060 of_phy_deregister_fixed_link(mac
->of_node
);
2061 mtk_tx_irq_disable(eth
, ~0);
2062 mtk_rx_irq_disable(eth
, ~0);
2065 static int mtk_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2071 return phy_mii_ioctl(dev
->phydev
, ifr
, cmd
);
2079 static void mtk_pending_work(struct work_struct
*work
)
2081 struct mtk_eth
*eth
= container_of(work
, struct mtk_eth
, pending_work
);
2083 unsigned long restart
= 0;
2087 dev_dbg(eth
->dev
, "[%s][%d] reset\n", __func__
, __LINE__
);
2089 while (test_and_set_bit_lock(MTK_RESETTING
, ð
->state
))
2092 dev_dbg(eth
->dev
, "[%s][%d] mtk_stop starts\n", __func__
, __LINE__
);
2093 /* stop all devices to make sure that dma is properly shut down */
2094 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
2095 if (!eth
->netdev
[i
])
2097 mtk_stop(eth
->netdev
[i
]);
2098 __set_bit(i
, &restart
);
2100 dev_dbg(eth
->dev
, "[%s][%d] mtk_stop ends\n", __func__
, __LINE__
);
2102 /* restart underlying hardware such as power, clock, pin mux
2103 * and the connected phy
2108 pinctrl_select_state(eth
->dev
->pins
->p
,
2109 eth
->dev
->pins
->default_state
);
2112 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
2114 of_phy_is_fixed_link(eth
->mac
[i
]->of_node
))
2116 err
= phy_init_hw(eth
->netdev
[i
]->phydev
);
2118 dev_err(eth
->dev
, "%s: PHY init failed.\n",
2119 eth
->netdev
[i
]->name
);
2122 /* restart DMA and enable IRQs */
2123 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
2124 if (!test_bit(i
, &restart
))
2126 err
= mtk_open(eth
->netdev
[i
]);
2128 netif_alert(eth
, ifup
, eth
->netdev
[i
],
2129 "Driver up/down cycle failed, closing device.\n");
2130 dev_close(eth
->netdev
[i
]);
2134 dev_dbg(eth
->dev
, "[%s][%d] reset done\n", __func__
, __LINE__
);
2136 clear_bit_unlock(MTK_RESETTING
, ð
->state
);
2141 static int mtk_free_dev(struct mtk_eth
*eth
)
2145 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
2146 if (!eth
->netdev
[i
])
2148 free_netdev(eth
->netdev
[i
]);
2154 static int mtk_unreg_dev(struct mtk_eth
*eth
)
2158 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
2159 if (!eth
->netdev
[i
])
2161 unregister_netdev(eth
->netdev
[i
]);
2167 static int mtk_cleanup(struct mtk_eth
*eth
)
2171 cancel_work_sync(ð
->pending_work
);
2176 static int mtk_get_link_ksettings(struct net_device
*ndev
,
2177 struct ethtool_link_ksettings
*cmd
)
2179 struct mtk_mac
*mac
= netdev_priv(ndev
);
2181 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
2184 phy_ethtool_ksettings_get(ndev
->phydev
, cmd
);
2189 static int mtk_set_link_ksettings(struct net_device
*ndev
,
2190 const struct ethtool_link_ksettings
*cmd
)
2192 struct mtk_mac
*mac
= netdev_priv(ndev
);
2194 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
2197 return phy_ethtool_ksettings_set(ndev
->phydev
, cmd
);
2200 static void mtk_get_drvinfo(struct net_device
*dev
,
2201 struct ethtool_drvinfo
*info
)
2203 struct mtk_mac
*mac
= netdev_priv(dev
);
2205 strlcpy(info
->driver
, mac
->hw
->dev
->driver
->name
, sizeof(info
->driver
));
2206 strlcpy(info
->bus_info
, dev_name(mac
->hw
->dev
), sizeof(info
->bus_info
));
2207 info
->n_stats
= ARRAY_SIZE(mtk_ethtool_stats
);
2210 static u32
mtk_get_msglevel(struct net_device
*dev
)
2212 struct mtk_mac
*mac
= netdev_priv(dev
);
2214 return mac
->hw
->msg_enable
;
2217 static void mtk_set_msglevel(struct net_device
*dev
, u32 value
)
2219 struct mtk_mac
*mac
= netdev_priv(dev
);
2221 mac
->hw
->msg_enable
= value
;
2224 static int mtk_nway_reset(struct net_device
*dev
)
2226 struct mtk_mac
*mac
= netdev_priv(dev
);
2228 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
2231 return genphy_restart_aneg(dev
->phydev
);
2234 static u32
mtk_get_link(struct net_device
*dev
)
2236 struct mtk_mac
*mac
= netdev_priv(dev
);
2239 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
2242 err
= genphy_update_link(dev
->phydev
);
2244 return ethtool_op_get_link(dev
);
2246 return dev
->phydev
->link
;
2249 static void mtk_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
2253 switch (stringset
) {
2255 for (i
= 0; i
< ARRAY_SIZE(mtk_ethtool_stats
); i
++) {
2256 memcpy(data
, mtk_ethtool_stats
[i
].str
, ETH_GSTRING_LEN
);
2257 data
+= ETH_GSTRING_LEN
;
2263 static int mtk_get_sset_count(struct net_device
*dev
, int sset
)
2267 return ARRAY_SIZE(mtk_ethtool_stats
);
2273 static void mtk_get_ethtool_stats(struct net_device
*dev
,
2274 struct ethtool_stats
*stats
, u64
*data
)
2276 struct mtk_mac
*mac
= netdev_priv(dev
);
2277 struct mtk_hw_stats
*hwstats
= mac
->hw_stats
;
2278 u64
*data_src
, *data_dst
;
2282 if (unlikely(test_bit(MTK_RESETTING
, &mac
->hw
->state
)))
2285 if (netif_running(dev
) && netif_device_present(dev
)) {
2286 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
2287 mtk_stats_update_mac(mac
);
2288 spin_unlock_bh(&hwstats
->stats_lock
);
2292 data_src
= (u64
*)hwstats
;
2296 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
2298 for (i
= 0; i
< ARRAY_SIZE(mtk_ethtool_stats
); i
++)
2299 *data_dst
++ = *(data_src
+ mtk_ethtool_stats
[i
].offset
);
2300 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
2303 static int mtk_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
,
2306 int ret
= -EOPNOTSUPP
;
2309 case ETHTOOL_GRXRINGS
:
2310 if (dev
->hw_features
& NETIF_F_LRO
) {
2311 cmd
->data
= MTK_MAX_RX_RING_NUM
;
2315 case ETHTOOL_GRXCLSRLCNT
:
2316 if (dev
->hw_features
& NETIF_F_LRO
) {
2317 struct mtk_mac
*mac
= netdev_priv(dev
);
2319 cmd
->rule_cnt
= mac
->hwlro_ip_cnt
;
2323 case ETHTOOL_GRXCLSRULE
:
2324 if (dev
->hw_features
& NETIF_F_LRO
)
2325 ret
= mtk_hwlro_get_fdir_entry(dev
, cmd
);
2327 case ETHTOOL_GRXCLSRLALL
:
2328 if (dev
->hw_features
& NETIF_F_LRO
)
2329 ret
= mtk_hwlro_get_fdir_all(dev
, cmd
,
2339 static int mtk_set_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
2341 int ret
= -EOPNOTSUPP
;
2344 case ETHTOOL_SRXCLSRLINS
:
2345 if (dev
->hw_features
& NETIF_F_LRO
)
2346 ret
= mtk_hwlro_add_ipaddr(dev
, cmd
);
2348 case ETHTOOL_SRXCLSRLDEL
:
2349 if (dev
->hw_features
& NETIF_F_LRO
)
2350 ret
= mtk_hwlro_del_ipaddr(dev
, cmd
);
2359 static const struct ethtool_ops mtk_ethtool_ops
= {
2360 .get_link_ksettings
= mtk_get_link_ksettings
,
2361 .set_link_ksettings
= mtk_set_link_ksettings
,
2362 .get_drvinfo
= mtk_get_drvinfo
,
2363 .get_msglevel
= mtk_get_msglevel
,
2364 .set_msglevel
= mtk_set_msglevel
,
2365 .nway_reset
= mtk_nway_reset
,
2366 .get_link
= mtk_get_link
,
2367 .get_strings
= mtk_get_strings
,
2368 .get_sset_count
= mtk_get_sset_count
,
2369 .get_ethtool_stats
= mtk_get_ethtool_stats
,
2370 .get_rxnfc
= mtk_get_rxnfc
,
2371 .set_rxnfc
= mtk_set_rxnfc
,
2374 static const struct net_device_ops mtk_netdev_ops
= {
2375 .ndo_init
= mtk_init
,
2376 .ndo_uninit
= mtk_uninit
,
2377 .ndo_open
= mtk_open
,
2378 .ndo_stop
= mtk_stop
,
2379 .ndo_start_xmit
= mtk_start_xmit
,
2380 .ndo_set_mac_address
= mtk_set_mac_address
,
2381 .ndo_validate_addr
= eth_validate_addr
,
2382 .ndo_do_ioctl
= mtk_do_ioctl
,
2383 .ndo_tx_timeout
= mtk_tx_timeout
,
2384 .ndo_get_stats64
= mtk_get_stats64
,
2385 .ndo_fix_features
= mtk_fix_features
,
2386 .ndo_set_features
= mtk_set_features
,
2387 #ifdef CONFIG_NET_POLL_CONTROLLER
2388 .ndo_poll_controller
= mtk_poll_controller
,
2392 static int mtk_add_mac(struct mtk_eth
*eth
, struct device_node
*np
)
2394 struct mtk_mac
*mac
;
2395 const __be32
*_id
= of_get_property(np
, "reg", NULL
);
2399 dev_err(eth
->dev
, "missing mac id\n");
2403 id
= be32_to_cpup(_id
);
2404 if (id
>= MTK_MAC_COUNT
) {
2405 dev_err(eth
->dev
, "%d is not a valid mac id\n", id
);
2409 if (eth
->netdev
[id
]) {
2410 dev_err(eth
->dev
, "duplicate mac id found: %d\n", id
);
2414 eth
->netdev
[id
] = alloc_etherdev(sizeof(*mac
));
2415 if (!eth
->netdev
[id
]) {
2416 dev_err(eth
->dev
, "alloc_etherdev failed\n");
2419 mac
= netdev_priv(eth
->netdev
[id
]);
2425 memset(mac
->hwlro_ip
, 0, sizeof(mac
->hwlro_ip
));
2426 mac
->hwlro_ip_cnt
= 0;
2428 mac
->hw_stats
= devm_kzalloc(eth
->dev
,
2429 sizeof(*mac
->hw_stats
),
2431 if (!mac
->hw_stats
) {
2432 dev_err(eth
->dev
, "failed to allocate counter memory\n");
2436 spin_lock_init(&mac
->hw_stats
->stats_lock
);
2437 u64_stats_init(&mac
->hw_stats
->syncp
);
2438 mac
->hw_stats
->reg_offset
= id
* MTK_STAT_OFFSET
;
2440 SET_NETDEV_DEV(eth
->netdev
[id
], eth
->dev
);
2441 eth
->netdev
[id
]->watchdog_timeo
= 5 * HZ
;
2442 eth
->netdev
[id
]->netdev_ops
= &mtk_netdev_ops
;
2443 eth
->netdev
[id
]->base_addr
= (unsigned long)eth
->base
;
2445 eth
->netdev
[id
]->hw_features
= MTK_HW_FEATURES
;
2447 eth
->netdev
[id
]->hw_features
|= NETIF_F_LRO
;
2449 eth
->netdev
[id
]->vlan_features
= MTK_HW_FEATURES
&
2450 ~(NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
);
2451 eth
->netdev
[id
]->features
|= MTK_HW_FEATURES
;
2452 eth
->netdev
[id
]->ethtool_ops
= &mtk_ethtool_ops
;
2454 eth
->netdev
[id
]->irq
= eth
->irq
[0];
2455 eth
->netdev
[id
]->dev
.of_node
= np
;
2460 free_netdev(eth
->netdev
[id
]);
2464 static int mtk_get_chip_id(struct mtk_eth
*eth
, u32
*chip_id
)
2468 regmap_read(eth
->ethsys
, ETHSYS_CHIPID0_3
, &val
[0]);
2469 regmap_read(eth
->ethsys
, ETHSYS_CHIPID4_7
, &val
[1]);
2471 id
[3] = ((val
[0] >> 16) & 0xff) - '0';
2472 id
[2] = ((val
[0] >> 24) & 0xff) - '0';
2473 id
[1] = (val
[1] & 0xff) - '0';
2474 id
[0] = ((val
[1] >> 8) & 0xff) - '0';
2476 *chip_id
= (id
[3] * 1000) + (id
[2] * 100) +
2477 (id
[1] * 10) + id
[0];
2480 dev_err(eth
->dev
, "failed to get chip id\n");
2484 dev_info(eth
->dev
, "chip id = %d\n", *chip_id
);
2489 static bool mtk_is_hwlro_supported(struct mtk_eth
*eth
)
2491 switch (eth
->chip_id
) {
2500 static int mtk_probe(struct platform_device
*pdev
)
2502 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2503 struct device_node
*mac_np
;
2504 const struct of_device_id
*match
;
2505 struct mtk_eth
*eth
;
2509 eth
= devm_kzalloc(&pdev
->dev
, sizeof(*eth
), GFP_KERNEL
);
2513 match
= of_match_device(of_mtk_match
, &pdev
->dev
);
2514 eth
->soc
= (struct mtk_soc_data
*)match
->data
;
2516 eth
->dev
= &pdev
->dev
;
2517 eth
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
2518 if (IS_ERR(eth
->base
))
2519 return PTR_ERR(eth
->base
);
2521 spin_lock_init(ð
->page_lock
);
2522 spin_lock_init(ð
->tx_irq_lock
);
2523 spin_lock_init(ð
->rx_irq_lock
);
2525 eth
->ethsys
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
2527 if (IS_ERR(eth
->ethsys
)) {
2528 dev_err(&pdev
->dev
, "no ethsys regmap found\n");
2529 return PTR_ERR(eth
->ethsys
);
2532 if (MTK_HAS_CAPS(eth
->soc
->caps
, MTK_SGMII
)) {
2534 syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
2535 "mediatek,sgmiisys");
2536 if (IS_ERR(eth
->sgmiisys
)) {
2537 dev_err(&pdev
->dev
, "no sgmiisys regmap found\n");
2538 return PTR_ERR(eth
->sgmiisys
);
2542 eth
->pctl
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
2544 if (IS_ERR(eth
->pctl
)) {
2545 dev_err(&pdev
->dev
, "no pctl regmap found\n");
2546 return PTR_ERR(eth
->pctl
);
2549 for (i
= 0; i
< 3; i
++) {
2550 eth
->irq
[i
] = platform_get_irq(pdev
, i
);
2551 if (eth
->irq
[i
] < 0) {
2552 dev_err(&pdev
->dev
, "no IRQ%d resource found\n", i
);
2556 for (i
= 0; i
< ARRAY_SIZE(eth
->clks
); i
++) {
2557 eth
->clks
[i
] = devm_clk_get(eth
->dev
,
2558 mtk_clks_source_name
[i
]);
2559 if (IS_ERR(eth
->clks
[i
])) {
2560 if (PTR_ERR(eth
->clks
[i
]) == -EPROBE_DEFER
)
2561 return -EPROBE_DEFER
;
2562 if (eth
->soc
->required_clks
& BIT(i
)) {
2563 dev_err(&pdev
->dev
, "clock %s not found\n",
2564 mtk_clks_source_name
[i
]);
2567 eth
->clks
[i
] = NULL
;
2571 eth
->msg_enable
= netif_msg_init(mtk_msg_level
, MTK_DEFAULT_MSG_ENABLE
);
2572 INIT_WORK(ð
->pending_work
, mtk_pending_work
);
2574 err
= mtk_hw_init(eth
);
2578 err
= mtk_get_chip_id(eth
, ð
->chip_id
);
2582 eth
->hwlro
= mtk_is_hwlro_supported(eth
);
2584 for_each_child_of_node(pdev
->dev
.of_node
, mac_np
) {
2585 if (!of_device_is_compatible(mac_np
,
2586 "mediatek,eth-mac"))
2589 if (!of_device_is_available(mac_np
))
2592 err
= mtk_add_mac(eth
, mac_np
);
2597 err
= devm_request_irq(eth
->dev
, eth
->irq
[1], mtk_handle_irq_tx
, 0,
2598 dev_name(eth
->dev
), eth
);
2602 err
= devm_request_irq(eth
->dev
, eth
->irq
[2], mtk_handle_irq_rx
, 0,
2603 dev_name(eth
->dev
), eth
);
2607 err
= mtk_mdio_init(eth
);
2611 for (i
= 0; i
< MTK_MAX_DEVS
; i
++) {
2612 if (!eth
->netdev
[i
])
2615 err
= register_netdev(eth
->netdev
[i
]);
2617 dev_err(eth
->dev
, "error bringing up device\n");
2618 goto err_deinit_mdio
;
2620 netif_info(eth
, probe
, eth
->netdev
[i
],
2621 "mediatek frame engine at 0x%08lx, irq %d\n",
2622 eth
->netdev
[i
]->base_addr
, eth
->irq
[0]);
2625 /* we run 2 devices on the same DMA ring so we need a dummy device
2628 init_dummy_netdev(ð
->dummy_dev
);
2629 netif_napi_add(ð
->dummy_dev
, ð
->tx_napi
, mtk_napi_tx
,
2631 netif_napi_add(ð
->dummy_dev
, ð
->rx_napi
, mtk_napi_rx
,
2634 platform_set_drvdata(pdev
, eth
);
2639 mtk_mdio_cleanup(eth
);
2648 static int mtk_remove(struct platform_device
*pdev
)
2650 struct mtk_eth
*eth
= platform_get_drvdata(pdev
);
2653 /* stop all devices to make sure that dma is properly shut down */
2654 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
2655 if (!eth
->netdev
[i
])
2657 mtk_stop(eth
->netdev
[i
]);
2662 netif_napi_del(ð
->tx_napi
);
2663 netif_napi_del(ð
->rx_napi
);
2665 mtk_mdio_cleanup(eth
);
2670 static const struct mtk_soc_data mt2701_data
= {
2671 .caps
= MTK_GMAC1_TRGMII
,
2672 .required_clks
= MT7623_CLKS_BITMAP
2675 static const struct mtk_soc_data mt7622_data
= {
2676 .caps
= MTK_DUAL_GMAC_SHARED_SGMII
| MTK_GMAC1_ESW
,
2677 .required_clks
= MT7622_CLKS_BITMAP
2680 static const struct mtk_soc_data mt7623_data
= {
2681 .caps
= MTK_GMAC1_TRGMII
,
2682 .required_clks
= MT7623_CLKS_BITMAP
2685 const struct of_device_id of_mtk_match
[] = {
2686 { .compatible
= "mediatek,mt2701-eth", .data
= &mt2701_data
},
2687 { .compatible
= "mediatek,mt7622-eth", .data
= &mt7622_data
},
2688 { .compatible
= "mediatek,mt7623-eth", .data
= &mt7623_data
},
2691 MODULE_DEVICE_TABLE(of
, of_mtk_match
);
2693 static struct platform_driver mtk_driver
= {
2695 .remove
= mtk_remove
,
2697 .name
= "mtk_soc_eth",
2698 .of_match_table
= of_mtk_match
,
2702 module_platform_driver(mtk_driver
);
2704 MODULE_LICENSE("GPL");
2705 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2706 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");