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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
45 #include <linux/delay.h>
46
47 #include <asm/io.h>
48
49 #include "mlx4.h"
50 #include "fw.h"
51 #include "fw_qos.h"
52
53 #define CMD_POLL_TOKEN 0xffff
54 #define INBOX_MASK 0xffffffffffffff00ULL
55
56 #define CMD_CHAN_VER 1
57 #define CMD_CHAN_IF_REV 1
58
59 enum {
60 /* command completed successfully: */
61 CMD_STAT_OK = 0x00,
62 /* Internal error (such as a bus error) occurred while processing command: */
63 CMD_STAT_INTERNAL_ERR = 0x01,
64 /* Operation/command not supported or opcode modifier not supported: */
65 CMD_STAT_BAD_OP = 0x02,
66 /* Parameter not supported or parameter out of range: */
67 CMD_STAT_BAD_PARAM = 0x03,
68 /* System not enabled or bad system state: */
69 CMD_STAT_BAD_SYS_STATE = 0x04,
70 /* Attempt to access reserved or unallocaterd resource: */
71 CMD_STAT_BAD_RESOURCE = 0x05,
72 /* Requested resource is currently executing a command, or is otherwise busy: */
73 CMD_STAT_RESOURCE_BUSY = 0x06,
74 /* Required capability exceeds device limits: */
75 CMD_STAT_EXCEED_LIM = 0x08,
76 /* Resource is not in the appropriate state or ownership: */
77 CMD_STAT_BAD_RES_STATE = 0x09,
78 /* Index out of range: */
79 CMD_STAT_BAD_INDEX = 0x0a,
80 /* FW image corrupted: */
81 CMD_STAT_BAD_NVMEM = 0x0b,
82 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
83 CMD_STAT_ICM_ERROR = 0x0c,
84 /* Attempt to modify a QP/EE which is not in the presumed state: */
85 CMD_STAT_BAD_QP_STATE = 0x10,
86 /* Bad segment parameters (Address/Size): */
87 CMD_STAT_BAD_SEG_PARAM = 0x20,
88 /* Memory Region has Memory Windows bound to: */
89 CMD_STAT_REG_BOUND = 0x21,
90 /* HCA local attached memory not present: */
91 CMD_STAT_LAM_NOT_PRE = 0x22,
92 /* Bad management packet (silently discarded): */
93 CMD_STAT_BAD_PKT = 0x30,
94 /* More outstanding CQEs in CQ than new CQ size: */
95 CMD_STAT_BAD_SIZE = 0x40,
96 /* Multi Function device support required: */
97 CMD_STAT_MULTI_FUNC_REQ = 0x50,
98 };
99
100 enum {
101 HCR_IN_PARAM_OFFSET = 0x00,
102 HCR_IN_MODIFIER_OFFSET = 0x08,
103 HCR_OUT_PARAM_OFFSET = 0x0c,
104 HCR_TOKEN_OFFSET = 0x14,
105 HCR_STATUS_OFFSET = 0x18,
106
107 HCR_OPMOD_SHIFT = 12,
108 HCR_T_BIT = 21,
109 HCR_E_BIT = 22,
110 HCR_GO_BIT = 23
111 };
112
113 enum {
114 GO_BIT_TIMEOUT_MSECS = 10000
115 };
116
117 enum mlx4_vlan_transition {
118 MLX4_VLAN_TRANSITION_VST_VST = 0,
119 MLX4_VLAN_TRANSITION_VST_VGT = 1,
120 MLX4_VLAN_TRANSITION_VGT_VST = 2,
121 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
122 };
123
124
125 struct mlx4_cmd_context {
126 struct completion done;
127 int result;
128 int next;
129 u64 out_param;
130 u16 token;
131 u8 fw_status;
132 };
133
134 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
135 struct mlx4_vhcr_cmd *in_vhcr);
136
137 static int mlx4_status_to_errno(u8 status)
138 {
139 static const int trans_table[] = {
140 [CMD_STAT_INTERNAL_ERR] = -EIO,
141 [CMD_STAT_BAD_OP] = -EPERM,
142 [CMD_STAT_BAD_PARAM] = -EINVAL,
143 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
144 [CMD_STAT_BAD_RESOURCE] = -EBADF,
145 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
146 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
147 [CMD_STAT_BAD_RES_STATE] = -EBADF,
148 [CMD_STAT_BAD_INDEX] = -EBADF,
149 [CMD_STAT_BAD_NVMEM] = -EFAULT,
150 [CMD_STAT_ICM_ERROR] = -ENFILE,
151 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
152 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
153 [CMD_STAT_REG_BOUND] = -EBUSY,
154 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
155 [CMD_STAT_BAD_PKT] = -EINVAL,
156 [CMD_STAT_BAD_SIZE] = -ENOMEM,
157 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
158 };
159
160 if (status >= ARRAY_SIZE(trans_table) ||
161 (status != CMD_STAT_OK && trans_table[status] == 0))
162 return -EIO;
163
164 return trans_table[status];
165 }
166
167 static u8 mlx4_errno_to_status(int errno)
168 {
169 switch (errno) {
170 case -EPERM:
171 return CMD_STAT_BAD_OP;
172 case -EINVAL:
173 return CMD_STAT_BAD_PARAM;
174 case -ENXIO:
175 return CMD_STAT_BAD_SYS_STATE;
176 case -EBUSY:
177 return CMD_STAT_RESOURCE_BUSY;
178 case -ENOMEM:
179 return CMD_STAT_EXCEED_LIM;
180 case -ENFILE:
181 return CMD_STAT_ICM_ERROR;
182 default:
183 return CMD_STAT_INTERNAL_ERR;
184 }
185 }
186
187 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
188 u8 op_modifier)
189 {
190 switch (op) {
191 case MLX4_CMD_UNMAP_ICM:
192 case MLX4_CMD_UNMAP_ICM_AUX:
193 case MLX4_CMD_UNMAP_FA:
194 case MLX4_CMD_2RST_QP:
195 case MLX4_CMD_HW2SW_EQ:
196 case MLX4_CMD_HW2SW_CQ:
197 case MLX4_CMD_HW2SW_SRQ:
198 case MLX4_CMD_HW2SW_MPT:
199 case MLX4_CMD_CLOSE_HCA:
200 case MLX4_QP_FLOW_STEERING_DETACH:
201 case MLX4_CMD_FREE_RES:
202 case MLX4_CMD_CLOSE_PORT:
203 return CMD_STAT_OK;
204
205 case MLX4_CMD_QP_ATTACH:
206 /* On Detach case return success */
207 if (op_modifier == 0)
208 return CMD_STAT_OK;
209 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
210
211 default:
212 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
213 }
214 }
215
216 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
217 {
218 /* Any error during the closing commands below is considered fatal */
219 if (op == MLX4_CMD_CLOSE_HCA ||
220 op == MLX4_CMD_HW2SW_EQ ||
221 op == MLX4_CMD_HW2SW_CQ ||
222 op == MLX4_CMD_2RST_QP ||
223 op == MLX4_CMD_HW2SW_SRQ ||
224 op == MLX4_CMD_SYNC_TPT ||
225 op == MLX4_CMD_UNMAP_ICM ||
226 op == MLX4_CMD_UNMAP_ICM_AUX ||
227 op == MLX4_CMD_UNMAP_FA)
228 return 1;
229 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
230 * CMD_STAT_REG_BOUND.
231 * This status indicates that memory region has memory windows bound to it
232 * which may result from invalid user space usage and is not fatal.
233 */
234 if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
235 return 1;
236 return 0;
237 }
238
239 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
240 int err)
241 {
242 /* Only if reset flow is really active return code is based on
243 * command, otherwise current error code is returned.
244 */
245 if (mlx4_internal_err_reset) {
246 mlx4_enter_error_state(dev->persist);
247 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
248 }
249
250 return err;
251 }
252
253 static int comm_pending(struct mlx4_dev *dev)
254 {
255 struct mlx4_priv *priv = mlx4_priv(dev);
256 u32 status = readl(&priv->mfunc.comm->slave_read);
257
258 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
259 }
260
261 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
262 {
263 struct mlx4_priv *priv = mlx4_priv(dev);
264 u32 val;
265
266 /* To avoid writing to unknown addresses after the device state was
267 * changed to internal error and the function was rest,
268 * check the INTERNAL_ERROR flag which is updated under
269 * device_state_mutex lock.
270 */
271 mutex_lock(&dev->persist->device_state_mutex);
272
273 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
274 mutex_unlock(&dev->persist->device_state_mutex);
275 return -EIO;
276 }
277
278 priv->cmd.comm_toggle ^= 1;
279 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
280 __raw_writel((__force u32) cpu_to_be32(val),
281 &priv->mfunc.comm->slave_write);
282 mmiowb();
283 mutex_unlock(&dev->persist->device_state_mutex);
284 return 0;
285 }
286
287 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
288 unsigned long timeout)
289 {
290 struct mlx4_priv *priv = mlx4_priv(dev);
291 unsigned long end;
292 int err = 0;
293 int ret_from_pending = 0;
294
295 /* First, verify that the master reports correct status */
296 if (comm_pending(dev)) {
297 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
298 priv->cmd.comm_toggle, cmd);
299 return -EAGAIN;
300 }
301
302 /* Write command */
303 down(&priv->cmd.poll_sem);
304 if (mlx4_comm_cmd_post(dev, cmd, param)) {
305 /* Only in case the device state is INTERNAL_ERROR,
306 * mlx4_comm_cmd_post returns with an error
307 */
308 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
309 goto out;
310 }
311
312 end = msecs_to_jiffies(timeout) + jiffies;
313 while (comm_pending(dev) && time_before(jiffies, end))
314 cond_resched();
315 ret_from_pending = comm_pending(dev);
316 if (ret_from_pending) {
317 /* check if the slave is trying to boot in the middle of
318 * FLR process. The only non-zero result in the RESET command
319 * is MLX4_DELAY_RESET_SLAVE*/
320 if ((MLX4_COMM_CMD_RESET == cmd)) {
321 err = MLX4_DELAY_RESET_SLAVE;
322 goto out;
323 } else {
324 mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
325 cmd);
326 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
327 }
328 }
329
330 if (err)
331 mlx4_enter_error_state(dev->persist);
332 out:
333 up(&priv->cmd.poll_sem);
334 return err;
335 }
336
337 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
338 u16 param, u16 op, unsigned long timeout)
339 {
340 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
341 struct mlx4_cmd_context *context;
342 unsigned long end;
343 int err = 0;
344
345 down(&cmd->event_sem);
346
347 spin_lock(&cmd->context_lock);
348 BUG_ON(cmd->free_head < 0);
349 context = &cmd->context[cmd->free_head];
350 context->token += cmd->token_mask + 1;
351 cmd->free_head = context->next;
352 spin_unlock(&cmd->context_lock);
353
354 reinit_completion(&context->done);
355
356 if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
357 /* Only in case the device state is INTERNAL_ERROR,
358 * mlx4_comm_cmd_post returns with an error
359 */
360 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
361 goto out;
362 }
363
364 if (!wait_for_completion_timeout(&context->done,
365 msecs_to_jiffies(timeout))) {
366 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
367 vhcr_cmd, op);
368 goto out_reset;
369 }
370
371 err = context->result;
372 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
373 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
374 vhcr_cmd, context->fw_status);
375 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
376 goto out_reset;
377 }
378
379 /* wait for comm channel ready
380 * this is necessary for prevention the race
381 * when switching between event to polling mode
382 * Skipping this section in case the device is in FATAL_ERROR state,
383 * In this state, no commands are sent via the comm channel until
384 * the device has returned from reset.
385 */
386 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
387 end = msecs_to_jiffies(timeout) + jiffies;
388 while (comm_pending(dev) && time_before(jiffies, end))
389 cond_resched();
390 }
391 goto out;
392
393 out_reset:
394 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
395 mlx4_enter_error_state(dev->persist);
396 out:
397 spin_lock(&cmd->context_lock);
398 context->next = cmd->free_head;
399 cmd->free_head = context - cmd->context;
400 spin_unlock(&cmd->context_lock);
401
402 up(&cmd->event_sem);
403 return err;
404 }
405
406 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
407 u16 op, unsigned long timeout)
408 {
409 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
410 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
411
412 if (mlx4_priv(dev)->cmd.use_events)
413 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
414 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
415 }
416
417 static int cmd_pending(struct mlx4_dev *dev)
418 {
419 u32 status;
420
421 if (pci_channel_offline(dev->persist->pdev))
422 return -EIO;
423
424 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
425
426 return (status & swab32(1 << HCR_GO_BIT)) ||
427 (mlx4_priv(dev)->cmd.toggle ==
428 !!(status & swab32(1 << HCR_T_BIT)));
429 }
430
431 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
432 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
433 int event)
434 {
435 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
436 u32 __iomem *hcr = cmd->hcr;
437 int ret = -EIO;
438 unsigned long end;
439
440 mutex_lock(&dev->persist->device_state_mutex);
441 /* To avoid writing to unknown addresses after the device state was
442 * changed to internal error and the chip was reset,
443 * check the INTERNAL_ERROR flag which is updated under
444 * device_state_mutex lock.
445 */
446 if (pci_channel_offline(dev->persist->pdev) ||
447 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
448 /*
449 * Device is going through error recovery
450 * and cannot accept commands.
451 */
452 goto out;
453 }
454
455 end = jiffies;
456 if (event)
457 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
458
459 while (cmd_pending(dev)) {
460 if (pci_channel_offline(dev->persist->pdev)) {
461 /*
462 * Device is going through error recovery
463 * and cannot accept commands.
464 */
465 goto out;
466 }
467
468 if (time_after_eq(jiffies, end)) {
469 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
470 goto out;
471 }
472 cond_resched();
473 }
474
475 /*
476 * We use writel (instead of something like memcpy_toio)
477 * because writes of less than 32 bits to the HCR don't work
478 * (and some architectures such as ia64 implement memcpy_toio
479 * in terms of writeb).
480 */
481 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
482 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
483 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
484 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
485 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
486 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
487
488 /* __raw_writel may not order writes. */
489 wmb();
490
491 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
492 (cmd->toggle << HCR_T_BIT) |
493 (event ? (1 << HCR_E_BIT) : 0) |
494 (op_modifier << HCR_OPMOD_SHIFT) |
495 op), hcr + 6);
496
497 /*
498 * Make sure that our HCR writes don't get mixed in with
499 * writes from another CPU starting a FW command.
500 */
501 mmiowb();
502
503 cmd->toggle = cmd->toggle ^ 1;
504
505 ret = 0;
506
507 out:
508 if (ret)
509 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
510 op, ret, in_param, in_modifier, op_modifier);
511 mutex_unlock(&dev->persist->device_state_mutex);
512
513 return ret;
514 }
515
516 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
517 int out_is_imm, u32 in_modifier, u8 op_modifier,
518 u16 op, unsigned long timeout)
519 {
520 struct mlx4_priv *priv = mlx4_priv(dev);
521 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
522 int ret;
523
524 mutex_lock(&priv->cmd.slave_cmd_mutex);
525
526 vhcr->in_param = cpu_to_be64(in_param);
527 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
528 vhcr->in_modifier = cpu_to_be32(in_modifier);
529 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
530 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
531 vhcr->status = 0;
532 vhcr->flags = !!(priv->cmd.use_events) << 6;
533
534 if (mlx4_is_master(dev)) {
535 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
536 if (!ret) {
537 if (out_is_imm) {
538 if (out_param)
539 *out_param =
540 be64_to_cpu(vhcr->out_param);
541 else {
542 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
543 op);
544 vhcr->status = CMD_STAT_BAD_PARAM;
545 }
546 }
547 ret = mlx4_status_to_errno(vhcr->status);
548 }
549 if (ret &&
550 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
551 ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
552 } else {
553 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
554 MLX4_COMM_TIME + timeout);
555 if (!ret) {
556 if (out_is_imm) {
557 if (out_param)
558 *out_param =
559 be64_to_cpu(vhcr->out_param);
560 else {
561 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
562 op);
563 vhcr->status = CMD_STAT_BAD_PARAM;
564 }
565 }
566 ret = mlx4_status_to_errno(vhcr->status);
567 } else {
568 if (dev->persist->state &
569 MLX4_DEVICE_STATE_INTERNAL_ERROR)
570 ret = mlx4_internal_err_ret_value(dev, op,
571 op_modifier);
572 else
573 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
574 }
575 }
576
577 mutex_unlock(&priv->cmd.slave_cmd_mutex);
578 return ret;
579 }
580
581 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
582 int out_is_imm, u32 in_modifier, u8 op_modifier,
583 u16 op, unsigned long timeout)
584 {
585 struct mlx4_priv *priv = mlx4_priv(dev);
586 void __iomem *hcr = priv->cmd.hcr;
587 int err = 0;
588 unsigned long end;
589 u32 stat;
590
591 down(&priv->cmd.poll_sem);
592
593 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
594 /*
595 * Device is going through error recovery
596 * and cannot accept commands.
597 */
598 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
599 goto out;
600 }
601
602 if (out_is_imm && !out_param) {
603 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
604 op);
605 err = -EINVAL;
606 goto out;
607 }
608
609 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
610 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
611 if (err)
612 goto out_reset;
613
614 end = msecs_to_jiffies(timeout) + jiffies;
615 while (cmd_pending(dev) && time_before(jiffies, end)) {
616 if (pci_channel_offline(dev->persist->pdev)) {
617 /*
618 * Device is going through error recovery
619 * and cannot accept commands.
620 */
621 err = -EIO;
622 goto out_reset;
623 }
624
625 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
626 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
627 goto out;
628 }
629
630 cond_resched();
631 }
632
633 if (cmd_pending(dev)) {
634 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
635 op);
636 err = -EIO;
637 goto out_reset;
638 }
639
640 if (out_is_imm)
641 *out_param =
642 (u64) be32_to_cpu((__force __be32)
643 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
644 (u64) be32_to_cpu((__force __be32)
645 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
646 stat = be32_to_cpu((__force __be32)
647 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
648 err = mlx4_status_to_errno(stat);
649 if (err) {
650 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
651 op, stat);
652 if (mlx4_closing_cmd_fatal_error(op, stat))
653 goto out_reset;
654 goto out;
655 }
656
657 out_reset:
658 if (err)
659 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
660 out:
661 up(&priv->cmd.poll_sem);
662 return err;
663 }
664
665 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
666 {
667 struct mlx4_priv *priv = mlx4_priv(dev);
668 struct mlx4_cmd_context *context =
669 &priv->cmd.context[token & priv->cmd.token_mask];
670
671 /* previously timed out command completing at long last */
672 if (token != context->token)
673 return;
674
675 context->fw_status = status;
676 context->result = mlx4_status_to_errno(status);
677 context->out_param = out_param;
678
679 complete(&context->done);
680 }
681
682 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
683 int out_is_imm, u32 in_modifier, u8 op_modifier,
684 u16 op, unsigned long timeout)
685 {
686 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
687 struct mlx4_cmd_context *context;
688 int err = 0;
689
690 down(&cmd->event_sem);
691
692 spin_lock(&cmd->context_lock);
693 BUG_ON(cmd->free_head < 0);
694 context = &cmd->context[cmd->free_head];
695 context->token += cmd->token_mask + 1;
696 cmd->free_head = context->next;
697 spin_unlock(&cmd->context_lock);
698
699 if (out_is_imm && !out_param) {
700 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
701 op);
702 err = -EINVAL;
703 goto out;
704 }
705
706 reinit_completion(&context->done);
707
708 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
709 in_modifier, op_modifier, op, context->token, 1);
710 if (err)
711 goto out_reset;
712
713 if (!wait_for_completion_timeout(&context->done,
714 msecs_to_jiffies(timeout))) {
715 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
716 op);
717 err = -EIO;
718 goto out_reset;
719 }
720
721 err = context->result;
722 if (err) {
723 /* Since we do not want to have this error message always
724 * displayed at driver start when there are ConnectX2 HCAs
725 * on the host, we deprecate the error message for this
726 * specific command/input_mod/opcode_mod/fw-status to be debug.
727 */
728 if (op == MLX4_CMD_SET_PORT &&
729 (in_modifier == 1 || in_modifier == 2) &&
730 op_modifier == MLX4_SET_PORT_IB_OPCODE &&
731 context->fw_status == CMD_STAT_BAD_SIZE)
732 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
733 op, context->fw_status);
734 else
735 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
736 op, context->fw_status);
737 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
738 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
739 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
740 goto out_reset;
741
742 goto out;
743 }
744
745 if (out_is_imm)
746 *out_param = context->out_param;
747
748 out_reset:
749 if (err)
750 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
751 out:
752 spin_lock(&cmd->context_lock);
753 context->next = cmd->free_head;
754 cmd->free_head = context - cmd->context;
755 spin_unlock(&cmd->context_lock);
756
757 up(&cmd->event_sem);
758 return err;
759 }
760
761 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
762 int out_is_imm, u32 in_modifier, u8 op_modifier,
763 u16 op, unsigned long timeout, int native)
764 {
765 if (pci_channel_offline(dev->persist->pdev))
766 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
767
768 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
769 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
770 return mlx4_internal_err_ret_value(dev, op,
771 op_modifier);
772 if (mlx4_priv(dev)->cmd.use_events)
773 return mlx4_cmd_wait(dev, in_param, out_param,
774 out_is_imm, in_modifier,
775 op_modifier, op, timeout);
776 else
777 return mlx4_cmd_poll(dev, in_param, out_param,
778 out_is_imm, in_modifier,
779 op_modifier, op, timeout);
780 }
781 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
782 in_modifier, op_modifier, op, timeout);
783 }
784 EXPORT_SYMBOL_GPL(__mlx4_cmd);
785
786
787 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
788 {
789 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
790 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
791 }
792
793 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
794 int slave, u64 slave_addr,
795 int size, int is_read)
796 {
797 u64 in_param;
798 u64 out_param;
799
800 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
801 (slave & ~0x7f) | (size & 0xff)) {
802 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
803 slave_addr, master_addr, slave, size);
804 return -EINVAL;
805 }
806
807 if (is_read) {
808 in_param = (u64) slave | slave_addr;
809 out_param = (u64) dev->caps.function | master_addr;
810 } else {
811 in_param = (u64) dev->caps.function | master_addr;
812 out_param = (u64) slave | slave_addr;
813 }
814
815 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
816 MLX4_CMD_ACCESS_MEM,
817 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
818 }
819
820 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
821 struct mlx4_cmd_mailbox *inbox,
822 struct mlx4_cmd_mailbox *outbox)
823 {
824 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
825 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
826 int err;
827 int i;
828
829 if (index & 0x1f)
830 return -EINVAL;
831
832 in_mad->attr_mod = cpu_to_be32(index / 32);
833
834 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
835 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
836 MLX4_CMD_NATIVE);
837 if (err)
838 return err;
839
840 for (i = 0; i < 32; ++i)
841 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
842
843 return err;
844 }
845
846 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
847 struct mlx4_cmd_mailbox *inbox,
848 struct mlx4_cmd_mailbox *outbox)
849 {
850 int i;
851 int err;
852
853 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
854 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
855 if (err)
856 return err;
857 }
858
859 return 0;
860 }
861 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
862 #define PORT_STATE_OFFSET 32
863
864 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
865 {
866 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
867 return IB_PORT_ACTIVE;
868 else
869 return IB_PORT_DOWN;
870 }
871
872 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd)
877 {
878 struct ib_smp *smp = inbox->buf;
879 u32 index;
880 u8 port;
881 u8 opcode_modifier;
882 u16 *table;
883 int err;
884 int vidx, pidx;
885 int network_view;
886 struct mlx4_priv *priv = mlx4_priv(dev);
887 struct ib_smp *outsmp = outbox->buf;
888 __be16 *outtab = (__be16 *)(outsmp->data);
889 __be32 slave_cap_mask;
890 __be64 slave_node_guid;
891
892 port = vhcr->in_modifier;
893
894 /* network-view bit is for driver use only, and should not be passed to FW */
895 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
896 network_view = !!(vhcr->op_modifier & 0x8);
897
898 if (smp->base_version == 1 &&
899 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
900 smp->class_version == 1) {
901 /* host view is paravirtualized */
902 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
903 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
904 index = be32_to_cpu(smp->attr_mod);
905 if (port < 1 || port > dev->caps.num_ports)
906 return -EINVAL;
907 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
908 sizeof(*table) * 32, GFP_KERNEL);
909
910 if (!table)
911 return -ENOMEM;
912 /* need to get the full pkey table because the paravirtualized
913 * pkeys may be scattered among several pkey blocks.
914 */
915 err = get_full_pkey_table(dev, port, table, inbox, outbox);
916 if (!err) {
917 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
918 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
919 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
920 }
921 }
922 kfree(table);
923 return err;
924 }
925 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
926 /*get the slave specific caps:*/
927 /*do the command */
928 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
929 vhcr->in_modifier, opcode_modifier,
930 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
931 /* modify the response for slaves */
932 if (!err && slave != mlx4_master_func_num(dev)) {
933 u8 *state = outsmp->data + PORT_STATE_OFFSET;
934
935 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
936 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
937 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
938 }
939 return err;
940 }
941 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
942 __be64 guid = mlx4_get_admin_guid(dev, slave,
943 port);
944
945 /* set the PF admin guid to the FW/HW burned
946 * GUID, if it wasn't yet set
947 */
948 if (slave == 0 && guid == 0) {
949 smp->attr_mod = 0;
950 err = mlx4_cmd_box(dev,
951 inbox->dma,
952 outbox->dma,
953 vhcr->in_modifier,
954 opcode_modifier,
955 vhcr->op,
956 MLX4_CMD_TIME_CLASS_C,
957 MLX4_CMD_NATIVE);
958 if (err)
959 return err;
960 mlx4_set_admin_guid(dev,
961 *(__be64 *)outsmp->
962 data, slave, port);
963 } else {
964 memcpy(outsmp->data, &guid, 8);
965 }
966
967 /* clean all other gids */
968 memset(outsmp->data + 8, 0, 56);
969 return 0;
970 }
971 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
972 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
973 vhcr->in_modifier, opcode_modifier,
974 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
975 if (!err) {
976 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
977 memcpy(outsmp->data + 12, &slave_node_guid, 8);
978 }
979 return err;
980 }
981 }
982 }
983
984 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
985 * These are the MADs used by ib verbs (such as ib_query_gids).
986 */
987 if (slave != mlx4_master_func_num(dev) &&
988 !mlx4_vf_smi_enabled(dev, slave, port)) {
989 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
990 smp->method == IB_MGMT_METHOD_GET) || network_view) {
991 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
992 slave, smp->method, smp->mgmt_class,
993 network_view ? "Network" : "Host",
994 be16_to_cpu(smp->attr_id));
995 return -EPERM;
996 }
997 }
998
999 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1000 vhcr->in_modifier, opcode_modifier,
1001 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1002 }
1003
1004 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
1005 struct mlx4_vhcr *vhcr,
1006 struct mlx4_cmd_mailbox *inbox,
1007 struct mlx4_cmd_mailbox *outbox,
1008 struct mlx4_cmd_info *cmd)
1009 {
1010 return -EPERM;
1011 }
1012
1013 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd)
1018 {
1019 u64 in_param;
1020 u64 out_param;
1021 int err;
1022
1023 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1024 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1025 if (cmd->encode_slave_id) {
1026 in_param &= 0xffffffffffffff00ll;
1027 in_param |= slave;
1028 }
1029
1030 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1031 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1032 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1033
1034 if (cmd->out_is_imm)
1035 vhcr->out_param = out_param;
1036
1037 return err;
1038 }
1039
1040 static struct mlx4_cmd_info cmd_info[] = {
1041 {
1042 .opcode = MLX4_CMD_QUERY_FW,
1043 .has_inbox = false,
1044 .has_outbox = true,
1045 .out_is_imm = false,
1046 .encode_slave_id = false,
1047 .verify = NULL,
1048 .wrapper = mlx4_QUERY_FW_wrapper
1049 },
1050 {
1051 .opcode = MLX4_CMD_QUERY_HCA,
1052 .has_inbox = false,
1053 .has_outbox = true,
1054 .out_is_imm = false,
1055 .encode_slave_id = false,
1056 .verify = NULL,
1057 .wrapper = NULL
1058 },
1059 {
1060 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1061 .has_inbox = false,
1062 .has_outbox = true,
1063 .out_is_imm = false,
1064 .encode_slave_id = false,
1065 .verify = NULL,
1066 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1067 },
1068 {
1069 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1070 .has_inbox = false,
1071 .has_outbox = true,
1072 .out_is_imm = false,
1073 .encode_slave_id = false,
1074 .verify = NULL,
1075 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1076 },
1077 {
1078 .opcode = MLX4_CMD_QUERY_ADAPTER,
1079 .has_inbox = false,
1080 .has_outbox = true,
1081 .out_is_imm = false,
1082 .encode_slave_id = false,
1083 .verify = NULL,
1084 .wrapper = NULL
1085 },
1086 {
1087 .opcode = MLX4_CMD_INIT_PORT,
1088 .has_inbox = false,
1089 .has_outbox = false,
1090 .out_is_imm = false,
1091 .encode_slave_id = false,
1092 .verify = NULL,
1093 .wrapper = mlx4_INIT_PORT_wrapper
1094 },
1095 {
1096 .opcode = MLX4_CMD_CLOSE_PORT,
1097 .has_inbox = false,
1098 .has_outbox = false,
1099 .out_is_imm = false,
1100 .encode_slave_id = false,
1101 .verify = NULL,
1102 .wrapper = mlx4_CLOSE_PORT_wrapper
1103 },
1104 {
1105 .opcode = MLX4_CMD_QUERY_PORT,
1106 .has_inbox = false,
1107 .has_outbox = true,
1108 .out_is_imm = false,
1109 .encode_slave_id = false,
1110 .verify = NULL,
1111 .wrapper = mlx4_QUERY_PORT_wrapper
1112 },
1113 {
1114 .opcode = MLX4_CMD_SET_PORT,
1115 .has_inbox = true,
1116 .has_outbox = false,
1117 .out_is_imm = false,
1118 .encode_slave_id = false,
1119 .verify = NULL,
1120 .wrapper = mlx4_SET_PORT_wrapper
1121 },
1122 {
1123 .opcode = MLX4_CMD_MAP_EQ,
1124 .has_inbox = false,
1125 .has_outbox = false,
1126 .out_is_imm = false,
1127 .encode_slave_id = false,
1128 .verify = NULL,
1129 .wrapper = mlx4_MAP_EQ_wrapper
1130 },
1131 {
1132 .opcode = MLX4_CMD_SW2HW_EQ,
1133 .has_inbox = true,
1134 .has_outbox = false,
1135 .out_is_imm = false,
1136 .encode_slave_id = true,
1137 .verify = NULL,
1138 .wrapper = mlx4_SW2HW_EQ_wrapper
1139 },
1140 {
1141 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1142 .has_inbox = false,
1143 .has_outbox = false,
1144 .out_is_imm = false,
1145 .encode_slave_id = false,
1146 .verify = NULL,
1147 .wrapper = NULL
1148 },
1149 {
1150 .opcode = MLX4_CMD_NOP,
1151 .has_inbox = false,
1152 .has_outbox = false,
1153 .out_is_imm = false,
1154 .encode_slave_id = false,
1155 .verify = NULL,
1156 .wrapper = NULL
1157 },
1158 {
1159 .opcode = MLX4_CMD_CONFIG_DEV,
1160 .has_inbox = false,
1161 .has_outbox = true,
1162 .out_is_imm = false,
1163 .encode_slave_id = false,
1164 .verify = NULL,
1165 .wrapper = mlx4_CONFIG_DEV_wrapper
1166 },
1167 {
1168 .opcode = MLX4_CMD_ALLOC_RES,
1169 .has_inbox = false,
1170 .has_outbox = false,
1171 .out_is_imm = true,
1172 .encode_slave_id = false,
1173 .verify = NULL,
1174 .wrapper = mlx4_ALLOC_RES_wrapper
1175 },
1176 {
1177 .opcode = MLX4_CMD_FREE_RES,
1178 .has_inbox = false,
1179 .has_outbox = false,
1180 .out_is_imm = false,
1181 .encode_slave_id = false,
1182 .verify = NULL,
1183 .wrapper = mlx4_FREE_RES_wrapper
1184 },
1185 {
1186 .opcode = MLX4_CMD_SW2HW_MPT,
1187 .has_inbox = true,
1188 .has_outbox = false,
1189 .out_is_imm = false,
1190 .encode_slave_id = true,
1191 .verify = NULL,
1192 .wrapper = mlx4_SW2HW_MPT_wrapper
1193 },
1194 {
1195 .opcode = MLX4_CMD_QUERY_MPT,
1196 .has_inbox = false,
1197 .has_outbox = true,
1198 .out_is_imm = false,
1199 .encode_slave_id = false,
1200 .verify = NULL,
1201 .wrapper = mlx4_QUERY_MPT_wrapper
1202 },
1203 {
1204 .opcode = MLX4_CMD_HW2SW_MPT,
1205 .has_inbox = false,
1206 .has_outbox = false,
1207 .out_is_imm = false,
1208 .encode_slave_id = false,
1209 .verify = NULL,
1210 .wrapper = mlx4_HW2SW_MPT_wrapper
1211 },
1212 {
1213 .opcode = MLX4_CMD_READ_MTT,
1214 .has_inbox = false,
1215 .has_outbox = true,
1216 .out_is_imm = false,
1217 .encode_slave_id = false,
1218 .verify = NULL,
1219 .wrapper = NULL
1220 },
1221 {
1222 .opcode = MLX4_CMD_WRITE_MTT,
1223 .has_inbox = true,
1224 .has_outbox = false,
1225 .out_is_imm = false,
1226 .encode_slave_id = false,
1227 .verify = NULL,
1228 .wrapper = mlx4_WRITE_MTT_wrapper
1229 },
1230 {
1231 .opcode = MLX4_CMD_SYNC_TPT,
1232 .has_inbox = true,
1233 .has_outbox = false,
1234 .out_is_imm = false,
1235 .encode_slave_id = false,
1236 .verify = NULL,
1237 .wrapper = NULL
1238 },
1239 {
1240 .opcode = MLX4_CMD_HW2SW_EQ,
1241 .has_inbox = false,
1242 .has_outbox = false,
1243 .out_is_imm = false,
1244 .encode_slave_id = true,
1245 .verify = NULL,
1246 .wrapper = mlx4_HW2SW_EQ_wrapper
1247 },
1248 {
1249 .opcode = MLX4_CMD_QUERY_EQ,
1250 .has_inbox = false,
1251 .has_outbox = true,
1252 .out_is_imm = false,
1253 .encode_slave_id = true,
1254 .verify = NULL,
1255 .wrapper = mlx4_QUERY_EQ_wrapper
1256 },
1257 {
1258 .opcode = MLX4_CMD_SW2HW_CQ,
1259 .has_inbox = true,
1260 .has_outbox = false,
1261 .out_is_imm = false,
1262 .encode_slave_id = true,
1263 .verify = NULL,
1264 .wrapper = mlx4_SW2HW_CQ_wrapper
1265 },
1266 {
1267 .opcode = MLX4_CMD_HW2SW_CQ,
1268 .has_inbox = false,
1269 .has_outbox = false,
1270 .out_is_imm = false,
1271 .encode_slave_id = false,
1272 .verify = NULL,
1273 .wrapper = mlx4_HW2SW_CQ_wrapper
1274 },
1275 {
1276 .opcode = MLX4_CMD_QUERY_CQ,
1277 .has_inbox = false,
1278 .has_outbox = true,
1279 .out_is_imm = false,
1280 .encode_slave_id = false,
1281 .verify = NULL,
1282 .wrapper = mlx4_QUERY_CQ_wrapper
1283 },
1284 {
1285 .opcode = MLX4_CMD_MODIFY_CQ,
1286 .has_inbox = true,
1287 .has_outbox = false,
1288 .out_is_imm = true,
1289 .encode_slave_id = false,
1290 .verify = NULL,
1291 .wrapper = mlx4_MODIFY_CQ_wrapper
1292 },
1293 {
1294 .opcode = MLX4_CMD_SW2HW_SRQ,
1295 .has_inbox = true,
1296 .has_outbox = false,
1297 .out_is_imm = false,
1298 .encode_slave_id = true,
1299 .verify = NULL,
1300 .wrapper = mlx4_SW2HW_SRQ_wrapper
1301 },
1302 {
1303 .opcode = MLX4_CMD_HW2SW_SRQ,
1304 .has_inbox = false,
1305 .has_outbox = false,
1306 .out_is_imm = false,
1307 .encode_slave_id = false,
1308 .verify = NULL,
1309 .wrapper = mlx4_HW2SW_SRQ_wrapper
1310 },
1311 {
1312 .opcode = MLX4_CMD_QUERY_SRQ,
1313 .has_inbox = false,
1314 .has_outbox = true,
1315 .out_is_imm = false,
1316 .encode_slave_id = false,
1317 .verify = NULL,
1318 .wrapper = mlx4_QUERY_SRQ_wrapper
1319 },
1320 {
1321 .opcode = MLX4_CMD_ARM_SRQ,
1322 .has_inbox = false,
1323 .has_outbox = false,
1324 .out_is_imm = false,
1325 .encode_slave_id = false,
1326 .verify = NULL,
1327 .wrapper = mlx4_ARM_SRQ_wrapper
1328 },
1329 {
1330 .opcode = MLX4_CMD_RST2INIT_QP,
1331 .has_inbox = true,
1332 .has_outbox = false,
1333 .out_is_imm = false,
1334 .encode_slave_id = true,
1335 .verify = NULL,
1336 .wrapper = mlx4_RST2INIT_QP_wrapper
1337 },
1338 {
1339 .opcode = MLX4_CMD_INIT2INIT_QP,
1340 .has_inbox = true,
1341 .has_outbox = false,
1342 .out_is_imm = false,
1343 .encode_slave_id = false,
1344 .verify = NULL,
1345 .wrapper = mlx4_INIT2INIT_QP_wrapper
1346 },
1347 {
1348 .opcode = MLX4_CMD_INIT2RTR_QP,
1349 .has_inbox = true,
1350 .has_outbox = false,
1351 .out_is_imm = false,
1352 .encode_slave_id = false,
1353 .verify = NULL,
1354 .wrapper = mlx4_INIT2RTR_QP_wrapper
1355 },
1356 {
1357 .opcode = MLX4_CMD_RTR2RTS_QP,
1358 .has_inbox = true,
1359 .has_outbox = false,
1360 .out_is_imm = false,
1361 .encode_slave_id = false,
1362 .verify = NULL,
1363 .wrapper = mlx4_RTR2RTS_QP_wrapper
1364 },
1365 {
1366 .opcode = MLX4_CMD_RTS2RTS_QP,
1367 .has_inbox = true,
1368 .has_outbox = false,
1369 .out_is_imm = false,
1370 .encode_slave_id = false,
1371 .verify = NULL,
1372 .wrapper = mlx4_RTS2RTS_QP_wrapper
1373 },
1374 {
1375 .opcode = MLX4_CMD_SQERR2RTS_QP,
1376 .has_inbox = true,
1377 .has_outbox = false,
1378 .out_is_imm = false,
1379 .encode_slave_id = false,
1380 .verify = NULL,
1381 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1382 },
1383 {
1384 .opcode = MLX4_CMD_2ERR_QP,
1385 .has_inbox = false,
1386 .has_outbox = false,
1387 .out_is_imm = false,
1388 .encode_slave_id = false,
1389 .verify = NULL,
1390 .wrapper = mlx4_GEN_QP_wrapper
1391 },
1392 {
1393 .opcode = MLX4_CMD_RTS2SQD_QP,
1394 .has_inbox = false,
1395 .has_outbox = false,
1396 .out_is_imm = false,
1397 .encode_slave_id = false,
1398 .verify = NULL,
1399 .wrapper = mlx4_GEN_QP_wrapper
1400 },
1401 {
1402 .opcode = MLX4_CMD_SQD2SQD_QP,
1403 .has_inbox = true,
1404 .has_outbox = false,
1405 .out_is_imm = false,
1406 .encode_slave_id = false,
1407 .verify = NULL,
1408 .wrapper = mlx4_SQD2SQD_QP_wrapper
1409 },
1410 {
1411 .opcode = MLX4_CMD_SQD2RTS_QP,
1412 .has_inbox = true,
1413 .has_outbox = false,
1414 .out_is_imm = false,
1415 .encode_slave_id = false,
1416 .verify = NULL,
1417 .wrapper = mlx4_SQD2RTS_QP_wrapper
1418 },
1419 {
1420 .opcode = MLX4_CMD_2RST_QP,
1421 .has_inbox = false,
1422 .has_outbox = false,
1423 .out_is_imm = false,
1424 .encode_slave_id = false,
1425 .verify = NULL,
1426 .wrapper = mlx4_2RST_QP_wrapper
1427 },
1428 {
1429 .opcode = MLX4_CMD_QUERY_QP,
1430 .has_inbox = false,
1431 .has_outbox = true,
1432 .out_is_imm = false,
1433 .encode_slave_id = false,
1434 .verify = NULL,
1435 .wrapper = mlx4_GEN_QP_wrapper
1436 },
1437 {
1438 .opcode = MLX4_CMD_SUSPEND_QP,
1439 .has_inbox = false,
1440 .has_outbox = false,
1441 .out_is_imm = false,
1442 .encode_slave_id = false,
1443 .verify = NULL,
1444 .wrapper = mlx4_GEN_QP_wrapper
1445 },
1446 {
1447 .opcode = MLX4_CMD_UNSUSPEND_QP,
1448 .has_inbox = false,
1449 .has_outbox = false,
1450 .out_is_imm = false,
1451 .encode_slave_id = false,
1452 .verify = NULL,
1453 .wrapper = mlx4_GEN_QP_wrapper
1454 },
1455 {
1456 .opcode = MLX4_CMD_UPDATE_QP,
1457 .has_inbox = true,
1458 .has_outbox = false,
1459 .out_is_imm = false,
1460 .encode_slave_id = false,
1461 .verify = NULL,
1462 .wrapper = mlx4_UPDATE_QP_wrapper
1463 },
1464 {
1465 .opcode = MLX4_CMD_GET_OP_REQ,
1466 .has_inbox = false,
1467 .has_outbox = false,
1468 .out_is_imm = false,
1469 .encode_slave_id = false,
1470 .verify = NULL,
1471 .wrapper = mlx4_CMD_EPERM_wrapper,
1472 },
1473 {
1474 .opcode = MLX4_CMD_ALLOCATE_VPP,
1475 .has_inbox = false,
1476 .has_outbox = true,
1477 .out_is_imm = false,
1478 .encode_slave_id = false,
1479 .verify = NULL,
1480 .wrapper = mlx4_CMD_EPERM_wrapper,
1481 },
1482 {
1483 .opcode = MLX4_CMD_SET_VPORT_QOS,
1484 .has_inbox = false,
1485 .has_outbox = true,
1486 .out_is_imm = false,
1487 .encode_slave_id = false,
1488 .verify = NULL,
1489 .wrapper = mlx4_CMD_EPERM_wrapper,
1490 },
1491 {
1492 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1493 .has_inbox = false,
1494 .has_outbox = false,
1495 .out_is_imm = false,
1496 .encode_slave_id = false,
1497 .verify = NULL, /* XXX verify: only demux can do this */
1498 .wrapper = NULL
1499 },
1500 {
1501 .opcode = MLX4_CMD_MAD_IFC,
1502 .has_inbox = true,
1503 .has_outbox = true,
1504 .out_is_imm = false,
1505 .encode_slave_id = false,
1506 .verify = NULL,
1507 .wrapper = mlx4_MAD_IFC_wrapper
1508 },
1509 {
1510 .opcode = MLX4_CMD_MAD_DEMUX,
1511 .has_inbox = false,
1512 .has_outbox = false,
1513 .out_is_imm = false,
1514 .encode_slave_id = false,
1515 .verify = NULL,
1516 .wrapper = mlx4_CMD_EPERM_wrapper
1517 },
1518 {
1519 .opcode = MLX4_CMD_QUERY_IF_STAT,
1520 .has_inbox = false,
1521 .has_outbox = true,
1522 .out_is_imm = false,
1523 .encode_slave_id = false,
1524 .verify = NULL,
1525 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1526 },
1527 {
1528 .opcode = MLX4_CMD_ACCESS_REG,
1529 .has_inbox = true,
1530 .has_outbox = true,
1531 .out_is_imm = false,
1532 .encode_slave_id = false,
1533 .verify = NULL,
1534 .wrapper = mlx4_ACCESS_REG_wrapper,
1535 },
1536 {
1537 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1538 .has_inbox = false,
1539 .has_outbox = false,
1540 .out_is_imm = false,
1541 .encode_slave_id = false,
1542 .verify = NULL,
1543 .wrapper = mlx4_CMD_EPERM_wrapper,
1544 },
1545 /* Native multicast commands are not available for guests */
1546 {
1547 .opcode = MLX4_CMD_QP_ATTACH,
1548 .has_inbox = true,
1549 .has_outbox = false,
1550 .out_is_imm = false,
1551 .encode_slave_id = false,
1552 .verify = NULL,
1553 .wrapper = mlx4_QP_ATTACH_wrapper
1554 },
1555 {
1556 .opcode = MLX4_CMD_PROMISC,
1557 .has_inbox = false,
1558 .has_outbox = false,
1559 .out_is_imm = false,
1560 .encode_slave_id = false,
1561 .verify = NULL,
1562 .wrapper = mlx4_PROMISC_wrapper
1563 },
1564 /* Ethernet specific commands */
1565 {
1566 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1567 .has_inbox = true,
1568 .has_outbox = false,
1569 .out_is_imm = false,
1570 .encode_slave_id = false,
1571 .verify = NULL,
1572 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1573 },
1574 {
1575 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1576 .has_inbox = false,
1577 .has_outbox = false,
1578 .out_is_imm = false,
1579 .encode_slave_id = false,
1580 .verify = NULL,
1581 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1582 },
1583 {
1584 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1585 .has_inbox = false,
1586 .has_outbox = true,
1587 .out_is_imm = false,
1588 .encode_slave_id = false,
1589 .verify = NULL,
1590 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1591 },
1592 {
1593 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1594 .has_inbox = false,
1595 .has_outbox = false,
1596 .out_is_imm = false,
1597 .encode_slave_id = false,
1598 .verify = NULL,
1599 .wrapper = NULL
1600 },
1601 /* flow steering commands */
1602 {
1603 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1604 .has_inbox = true,
1605 .has_outbox = false,
1606 .out_is_imm = true,
1607 .encode_slave_id = false,
1608 .verify = NULL,
1609 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1610 },
1611 {
1612 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1613 .has_inbox = false,
1614 .has_outbox = false,
1615 .out_is_imm = false,
1616 .encode_slave_id = false,
1617 .verify = NULL,
1618 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1619 },
1620 {
1621 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1622 .has_inbox = false,
1623 .has_outbox = false,
1624 .out_is_imm = false,
1625 .encode_slave_id = false,
1626 .verify = NULL,
1627 .wrapper = mlx4_CMD_EPERM_wrapper
1628 },
1629 {
1630 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1631 .has_inbox = false,
1632 .has_outbox = false,
1633 .out_is_imm = false,
1634 .encode_slave_id = false,
1635 .verify = NULL,
1636 .wrapper = mlx4_CMD_EPERM_wrapper
1637 },
1638 };
1639
1640 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1641 struct mlx4_vhcr_cmd *in_vhcr)
1642 {
1643 struct mlx4_priv *priv = mlx4_priv(dev);
1644 struct mlx4_cmd_info *cmd = NULL;
1645 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1646 struct mlx4_vhcr *vhcr;
1647 struct mlx4_cmd_mailbox *inbox = NULL;
1648 struct mlx4_cmd_mailbox *outbox = NULL;
1649 u64 in_param;
1650 u64 out_param;
1651 int ret = 0;
1652 int i;
1653 int err = 0;
1654
1655 /* Create sw representation of Virtual HCR */
1656 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1657 if (!vhcr)
1658 return -ENOMEM;
1659
1660 /* DMA in the vHCR */
1661 if (!in_vhcr) {
1662 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1663 priv->mfunc.master.slave_state[slave].vhcr_dma,
1664 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1665 MLX4_ACCESS_MEM_ALIGN), 1);
1666 if (ret) {
1667 if (!(dev->persist->state &
1668 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1669 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1670 __func__, ret);
1671 kfree(vhcr);
1672 return ret;
1673 }
1674 }
1675
1676 /* Fill SW VHCR fields */
1677 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1678 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1679 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1680 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1681 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1682 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1683 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1684
1685 /* Lookup command */
1686 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1687 if (vhcr->op == cmd_info[i].opcode) {
1688 cmd = &cmd_info[i];
1689 break;
1690 }
1691 }
1692 if (!cmd) {
1693 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1694 vhcr->op, slave);
1695 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1696 goto out_status;
1697 }
1698
1699 /* Read inbox */
1700 if (cmd->has_inbox) {
1701 vhcr->in_param &= INBOX_MASK;
1702 inbox = mlx4_alloc_cmd_mailbox(dev);
1703 if (IS_ERR(inbox)) {
1704 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1705 inbox = NULL;
1706 goto out_status;
1707 }
1708
1709 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1710 vhcr->in_param,
1711 MLX4_MAILBOX_SIZE, 1);
1712 if (ret) {
1713 if (!(dev->persist->state &
1714 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1715 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1716 __func__, cmd->opcode);
1717 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1718 goto out_status;
1719 }
1720 }
1721
1722 /* Apply permission and bound checks if applicable */
1723 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1724 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1725 vhcr->op, slave, vhcr->in_modifier);
1726 vhcr_cmd->status = CMD_STAT_BAD_OP;
1727 goto out_status;
1728 }
1729
1730 /* Allocate outbox */
1731 if (cmd->has_outbox) {
1732 outbox = mlx4_alloc_cmd_mailbox(dev);
1733 if (IS_ERR(outbox)) {
1734 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1735 outbox = NULL;
1736 goto out_status;
1737 }
1738 }
1739
1740 /* Execute the command! */
1741 if (cmd->wrapper) {
1742 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1743 cmd);
1744 if (cmd->out_is_imm)
1745 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1746 } else {
1747 in_param = cmd->has_inbox ? (u64) inbox->dma :
1748 vhcr->in_param;
1749 out_param = cmd->has_outbox ? (u64) outbox->dma :
1750 vhcr->out_param;
1751 err = __mlx4_cmd(dev, in_param, &out_param,
1752 cmd->out_is_imm, vhcr->in_modifier,
1753 vhcr->op_modifier, vhcr->op,
1754 MLX4_CMD_TIME_CLASS_A,
1755 MLX4_CMD_NATIVE);
1756
1757 if (cmd->out_is_imm) {
1758 vhcr->out_param = out_param;
1759 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1760 }
1761 }
1762
1763 if (err) {
1764 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1765 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1766 vhcr->op, slave, vhcr->errno, err);
1767 vhcr_cmd->status = mlx4_errno_to_status(err);
1768 goto out_status;
1769 }
1770
1771
1772 /* Write outbox if command completed successfully */
1773 if (cmd->has_outbox && !vhcr_cmd->status) {
1774 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1775 vhcr->out_param,
1776 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1777 if (ret) {
1778 /* If we failed to write back the outbox after the
1779 *command was successfully executed, we must fail this
1780 * slave, as it is now in undefined state */
1781 if (!(dev->persist->state &
1782 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1783 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1784 goto out;
1785 }
1786 }
1787
1788 out_status:
1789 /* DMA back vhcr result */
1790 if (!in_vhcr) {
1791 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1792 priv->mfunc.master.slave_state[slave].vhcr_dma,
1793 ALIGN(sizeof(struct mlx4_vhcr),
1794 MLX4_ACCESS_MEM_ALIGN),
1795 MLX4_CMD_WRAPPED);
1796 if (ret)
1797 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1798 __func__);
1799 else if (vhcr->e_bit &&
1800 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1801 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1802 slave);
1803 }
1804
1805 out:
1806 kfree(vhcr);
1807 mlx4_free_cmd_mailbox(dev, inbox);
1808 mlx4_free_cmd_mailbox(dev, outbox);
1809 return ret;
1810 }
1811
1812 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1813 int slave, int port)
1814 {
1815 struct mlx4_vport_oper_state *vp_oper;
1816 struct mlx4_vport_state *vp_admin;
1817 struct mlx4_vf_immed_vlan_work *work;
1818 struct mlx4_dev *dev = &(priv->dev);
1819 int err;
1820 int admin_vlan_ix = NO_INDX;
1821
1822 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1823 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1824
1825 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1826 vp_oper->state.default_qos == vp_admin->default_qos &&
1827 vp_oper->state.link_state == vp_admin->link_state &&
1828 vp_oper->state.qos_vport == vp_admin->qos_vport)
1829 return 0;
1830
1831 if (!(priv->mfunc.master.slave_state[slave].active &&
1832 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1833 /* even if the UPDATE_QP command isn't supported, we still want
1834 * to set this VF link according to the admin directive
1835 */
1836 vp_oper->state.link_state = vp_admin->link_state;
1837 return -1;
1838 }
1839
1840 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1841 slave, port);
1842 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1843 vp_admin->default_vlan, vp_admin->default_qos,
1844 vp_admin->link_state);
1845
1846 work = kzalloc(sizeof(*work), GFP_KERNEL);
1847 if (!work)
1848 return -ENOMEM;
1849
1850 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1851 if (MLX4_VGT != vp_admin->default_vlan) {
1852 err = __mlx4_register_vlan(&priv->dev, port,
1853 vp_admin->default_vlan,
1854 &admin_vlan_ix);
1855 if (err) {
1856 kfree(work);
1857 mlx4_warn(&priv->dev,
1858 "No vlan resources slave %d, port %d\n",
1859 slave, port);
1860 return err;
1861 }
1862 } else {
1863 admin_vlan_ix = NO_INDX;
1864 }
1865 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1866 mlx4_dbg(&priv->dev,
1867 "alloc vlan %d idx %d slave %d port %d\n",
1868 (int)(vp_admin->default_vlan),
1869 admin_vlan_ix, slave, port);
1870 }
1871
1872 /* save original vlan ix and vlan id */
1873 work->orig_vlan_id = vp_oper->state.default_vlan;
1874 work->orig_vlan_ix = vp_oper->vlan_idx;
1875
1876 /* handle new qos */
1877 if (vp_oper->state.default_qos != vp_admin->default_qos)
1878 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1879
1880 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1881 vp_oper->vlan_idx = admin_vlan_ix;
1882
1883 vp_oper->state.default_vlan = vp_admin->default_vlan;
1884 vp_oper->state.default_qos = vp_admin->default_qos;
1885 vp_oper->state.link_state = vp_admin->link_state;
1886 vp_oper->state.qos_vport = vp_admin->qos_vport;
1887
1888 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1889 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1890
1891 /* iterate over QPs owned by this slave, using UPDATE_QP */
1892 work->port = port;
1893 work->slave = slave;
1894 work->qos = vp_oper->state.default_qos;
1895 work->qos_vport = vp_oper->state.qos_vport;
1896 work->vlan_id = vp_oper->state.default_vlan;
1897 work->vlan_ix = vp_oper->vlan_idx;
1898 work->priv = priv;
1899 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1900 queue_work(priv->mfunc.master.comm_wq, &work->work);
1901
1902 return 0;
1903 }
1904
1905 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1906 {
1907 struct mlx4_qos_manager *port_qos_ctl;
1908 struct mlx4_priv *priv = mlx4_priv(dev);
1909
1910 port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1911 bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1912
1913 /* Enable only default prio at PF init routine */
1914 set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1915 }
1916
1917 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1918 {
1919 int i;
1920 int err;
1921 int num_vfs;
1922 u16 availible_vpp;
1923 u8 vpp_param[MLX4_NUM_UP];
1924 struct mlx4_qos_manager *port_qos;
1925 struct mlx4_priv *priv = mlx4_priv(dev);
1926
1927 err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1928 if (err) {
1929 mlx4_info(dev, "Failed query availible VPPs\n");
1930 return;
1931 }
1932
1933 port_qos = &priv->mfunc.master.qos_ctl[port];
1934 num_vfs = (availible_vpp /
1935 bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1936
1937 for (i = 0; i < MLX4_NUM_UP; i++) {
1938 if (test_bit(i, port_qos->priority_bm))
1939 vpp_param[i] = num_vfs;
1940 }
1941
1942 err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1943 if (err) {
1944 mlx4_info(dev, "Failed allocating VPPs\n");
1945 return;
1946 }
1947
1948 /* Query actual allocated VPP, just to make sure */
1949 err = mlx4_ALLOCATE_VPP_get(dev, port, &availible_vpp, vpp_param);
1950 if (err) {
1951 mlx4_info(dev, "Failed query availible VPPs\n");
1952 return;
1953 }
1954
1955 port_qos->num_of_qos_vfs = num_vfs;
1956 mlx4_dbg(dev, "Port %d Availible VPPs %d\n", port, availible_vpp);
1957
1958 for (i = 0; i < MLX4_NUM_UP; i++)
1959 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1960 vpp_param[i]);
1961 }
1962
1963 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1964 {
1965 int port, err;
1966 struct mlx4_vport_state *vp_admin;
1967 struct mlx4_vport_oper_state *vp_oper;
1968 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1969 &priv->dev, slave);
1970 int min_port = find_first_bit(actv_ports.ports,
1971 priv->dev.caps.num_ports) + 1;
1972 int max_port = min_port - 1 +
1973 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1974
1975 for (port = min_port; port <= max_port; port++) {
1976 if (!test_bit(port - 1, actv_ports.ports))
1977 continue;
1978 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1979 priv->mfunc.master.vf_admin[slave].enable_smi[port];
1980 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1981 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1982 vp_oper->state = *vp_admin;
1983 if (MLX4_VGT != vp_admin->default_vlan) {
1984 err = __mlx4_register_vlan(&priv->dev, port,
1985 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1986 if (err) {
1987 vp_oper->vlan_idx = NO_INDX;
1988 mlx4_warn(&priv->dev,
1989 "No vlan resources slave %d, port %d\n",
1990 slave, port);
1991 return err;
1992 }
1993 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
1994 (int)(vp_oper->state.default_vlan),
1995 vp_oper->vlan_idx, slave, port);
1996 }
1997 if (vp_admin->spoofchk) {
1998 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1999 port,
2000 vp_admin->mac);
2001 if (0 > vp_oper->mac_idx) {
2002 err = vp_oper->mac_idx;
2003 vp_oper->mac_idx = NO_INDX;
2004 mlx4_warn(&priv->dev,
2005 "No mac resources slave %d, port %d\n",
2006 slave, port);
2007 return err;
2008 }
2009 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
2010 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2011 }
2012 }
2013 return 0;
2014 }
2015
2016 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2017 {
2018 int port;
2019 struct mlx4_vport_oper_state *vp_oper;
2020 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2021 &priv->dev, slave);
2022 int min_port = find_first_bit(actv_ports.ports,
2023 priv->dev.caps.num_ports) + 1;
2024 int max_port = min_port - 1 +
2025 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2026
2027
2028 for (port = min_port; port <= max_port; port++) {
2029 if (!test_bit(port - 1, actv_ports.ports))
2030 continue;
2031 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2032 MLX4_VF_SMI_DISABLED;
2033 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2034 if (NO_INDX != vp_oper->vlan_idx) {
2035 __mlx4_unregister_vlan(&priv->dev,
2036 port, vp_oper->state.default_vlan);
2037 vp_oper->vlan_idx = NO_INDX;
2038 }
2039 if (NO_INDX != vp_oper->mac_idx) {
2040 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2041 vp_oper->mac_idx = NO_INDX;
2042 }
2043 }
2044 return;
2045 }
2046
2047 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2048 u16 param, u8 toggle)
2049 {
2050 struct mlx4_priv *priv = mlx4_priv(dev);
2051 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2052 u32 reply;
2053 u8 is_going_down = 0;
2054 int i;
2055 unsigned long flags;
2056
2057 slave_state[slave].comm_toggle ^= 1;
2058 reply = (u32) slave_state[slave].comm_toggle << 31;
2059 if (toggle != slave_state[slave].comm_toggle) {
2060 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2061 toggle, slave);
2062 goto reset_slave;
2063 }
2064 if (cmd == MLX4_COMM_CMD_RESET) {
2065 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2066 slave_state[slave].active = false;
2067 slave_state[slave].old_vlan_api = false;
2068 mlx4_master_deactivate_admin_state(priv, slave);
2069 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2070 slave_state[slave].event_eq[i].eqn = -1;
2071 slave_state[slave].event_eq[i].token = 0;
2072 }
2073 /*check if we are in the middle of FLR process,
2074 if so return "retry" status to the slave*/
2075 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2076 goto inform_slave_state;
2077
2078 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
2079
2080 /* write the version in the event field */
2081 reply |= mlx4_comm_get_version();
2082
2083 goto reset_slave;
2084 }
2085 /*command from slave in the middle of FLR*/
2086 if (cmd != MLX4_COMM_CMD_RESET &&
2087 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2088 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2089 slave, cmd);
2090 return;
2091 }
2092
2093 switch (cmd) {
2094 case MLX4_COMM_CMD_VHCR0:
2095 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2096 goto reset_slave;
2097 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2098 priv->mfunc.master.slave_state[slave].cookie = 0;
2099 break;
2100 case MLX4_COMM_CMD_VHCR1:
2101 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2102 goto reset_slave;
2103 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2104 break;
2105 case MLX4_COMM_CMD_VHCR2:
2106 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2107 goto reset_slave;
2108 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2109 break;
2110 case MLX4_COMM_CMD_VHCR_EN:
2111 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2112 goto reset_slave;
2113 slave_state[slave].vhcr_dma |= param;
2114 if (mlx4_master_activate_admin_state(priv, slave))
2115 goto reset_slave;
2116 slave_state[slave].active = true;
2117 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
2118 break;
2119 case MLX4_COMM_CMD_VHCR_POST:
2120 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2121 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2122 mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2123 slave, cmd, slave_state[slave].last_cmd);
2124 goto reset_slave;
2125 }
2126
2127 mutex_lock(&priv->cmd.slave_cmd_mutex);
2128 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2129 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2130 slave);
2131 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2132 goto reset_slave;
2133 }
2134 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2135 break;
2136 default:
2137 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2138 goto reset_slave;
2139 }
2140 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2141 if (!slave_state[slave].is_slave_going_down)
2142 slave_state[slave].last_cmd = cmd;
2143 else
2144 is_going_down = 1;
2145 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2146 if (is_going_down) {
2147 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2148 cmd, slave);
2149 return;
2150 }
2151 __raw_writel((__force u32) cpu_to_be32(reply),
2152 &priv->mfunc.comm[slave].slave_read);
2153 mmiowb();
2154
2155 return;
2156
2157 reset_slave:
2158 /* cleanup any slave resources */
2159 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2160 mlx4_delete_all_resources_for_slave(dev, slave);
2161
2162 if (cmd != MLX4_COMM_CMD_RESET) {
2163 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2164 slave, cmd);
2165 /* Turn on internal error letting slave reset itself immeditaly,
2166 * otherwise it might take till timeout on command is passed
2167 */
2168 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2169 }
2170
2171 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2172 if (!slave_state[slave].is_slave_going_down)
2173 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2174 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2175 /*with slave in the middle of flr, no need to clean resources again.*/
2176 inform_slave_state:
2177 memset(&slave_state[slave].event_eq, 0,
2178 sizeof(struct mlx4_slave_event_eq_info));
2179 __raw_writel((__force u32) cpu_to_be32(reply),
2180 &priv->mfunc.comm[slave].slave_read);
2181 wmb();
2182 }
2183
2184 /* master command processing */
2185 void mlx4_master_comm_channel(struct work_struct *work)
2186 {
2187 struct mlx4_mfunc_master_ctx *master =
2188 container_of(work,
2189 struct mlx4_mfunc_master_ctx,
2190 comm_work);
2191 struct mlx4_mfunc *mfunc =
2192 container_of(master, struct mlx4_mfunc, master);
2193 struct mlx4_priv *priv =
2194 container_of(mfunc, struct mlx4_priv, mfunc);
2195 struct mlx4_dev *dev = &priv->dev;
2196 __be32 *bit_vec;
2197 u32 comm_cmd;
2198 u32 vec;
2199 int i, j, slave;
2200 int toggle;
2201 int served = 0;
2202 int reported = 0;
2203 u32 slt;
2204
2205 bit_vec = master->comm_arm_bit_vector;
2206 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2207 vec = be32_to_cpu(bit_vec[i]);
2208 for (j = 0; j < 32; j++) {
2209 if (!(vec & (1 << j)))
2210 continue;
2211 ++reported;
2212 slave = (i * 32) + j;
2213 comm_cmd = swab32(readl(
2214 &mfunc->comm[slave].slave_write));
2215 slt = swab32(readl(&mfunc->comm[slave].slave_read))
2216 >> 31;
2217 toggle = comm_cmd >> 31;
2218 if (toggle != slt) {
2219 if (master->slave_state[slave].comm_toggle
2220 != slt) {
2221 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2222 slave, slt,
2223 master->slave_state[slave].comm_toggle);
2224 master->slave_state[slave].comm_toggle =
2225 slt;
2226 }
2227 mlx4_master_do_cmd(dev, slave,
2228 comm_cmd >> 16 & 0xff,
2229 comm_cmd & 0xffff, toggle);
2230 ++served;
2231 }
2232 }
2233 }
2234
2235 if (reported && reported != served)
2236 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2237 reported, served);
2238
2239 if (mlx4_ARM_COMM_CHANNEL(dev))
2240 mlx4_warn(dev, "Failed to arm comm channel events\n");
2241 }
2242
2243 static int sync_toggles(struct mlx4_dev *dev)
2244 {
2245 struct mlx4_priv *priv = mlx4_priv(dev);
2246 u32 wr_toggle;
2247 u32 rd_toggle;
2248 unsigned long end;
2249
2250 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2251 if (wr_toggle == 0xffffffff)
2252 end = jiffies + msecs_to_jiffies(30000);
2253 else
2254 end = jiffies + msecs_to_jiffies(5000);
2255
2256 while (time_before(jiffies, end)) {
2257 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2258 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2259 /* PCI might be offline */
2260 msleep(100);
2261 wr_toggle = swab32(readl(&priv->mfunc.comm->
2262 slave_write));
2263 continue;
2264 }
2265
2266 if (rd_toggle >> 31 == wr_toggle >> 31) {
2267 priv->cmd.comm_toggle = rd_toggle >> 31;
2268 return 0;
2269 }
2270
2271 cond_resched();
2272 }
2273
2274 /*
2275 * we could reach here if for example the previous VM using this
2276 * function misbehaved and left the channel with unsynced state. We
2277 * should fix this here and give this VM a chance to use a properly
2278 * synced channel
2279 */
2280 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2281 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2282 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2283 priv->cmd.comm_toggle = 0;
2284
2285 return 0;
2286 }
2287
2288 int mlx4_multi_func_init(struct mlx4_dev *dev)
2289 {
2290 struct mlx4_priv *priv = mlx4_priv(dev);
2291 struct mlx4_slave_state *s_state;
2292 int i, j, err, port;
2293
2294 if (mlx4_is_master(dev))
2295 priv->mfunc.comm =
2296 ioremap(pci_resource_start(dev->persist->pdev,
2297 priv->fw.comm_bar) +
2298 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2299 else
2300 priv->mfunc.comm =
2301 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2302 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2303 if (!priv->mfunc.comm) {
2304 mlx4_err(dev, "Couldn't map communication vector\n");
2305 goto err_vhcr;
2306 }
2307
2308 if (mlx4_is_master(dev)) {
2309 struct mlx4_vf_oper_state *vf_oper;
2310 struct mlx4_vf_admin_state *vf_admin;
2311
2312 priv->mfunc.master.slave_state =
2313 kzalloc(dev->num_slaves *
2314 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2315 if (!priv->mfunc.master.slave_state)
2316 goto err_comm;
2317
2318 priv->mfunc.master.vf_admin =
2319 kzalloc(dev->num_slaves *
2320 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2321 if (!priv->mfunc.master.vf_admin)
2322 goto err_comm_admin;
2323
2324 priv->mfunc.master.vf_oper =
2325 kzalloc(dev->num_slaves *
2326 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2327 if (!priv->mfunc.master.vf_oper)
2328 goto err_comm_oper;
2329
2330 for (i = 0; i < dev->num_slaves; ++i) {
2331 vf_admin = &priv->mfunc.master.vf_admin[i];
2332 vf_oper = &priv->mfunc.master.vf_oper[i];
2333 s_state = &priv->mfunc.master.slave_state[i];
2334 s_state->last_cmd = MLX4_COMM_CMD_RESET;
2335 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2336 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2337 s_state->event_eq[j].eqn = -1;
2338 __raw_writel((__force u32) 0,
2339 &priv->mfunc.comm[i].slave_write);
2340 __raw_writel((__force u32) 0,
2341 &priv->mfunc.comm[i].slave_read);
2342 mmiowb();
2343 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2344 struct mlx4_vport_state *admin_vport;
2345 struct mlx4_vport_state *oper_vport;
2346
2347 s_state->vlan_filter[port] =
2348 kzalloc(sizeof(struct mlx4_vlan_fltr),
2349 GFP_KERNEL);
2350 if (!s_state->vlan_filter[port]) {
2351 if (--port)
2352 kfree(s_state->vlan_filter[port]);
2353 goto err_slaves;
2354 }
2355
2356 admin_vport = &vf_admin->vport[port];
2357 oper_vport = &vf_oper->vport[port].state;
2358 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2359 admin_vport->default_vlan = MLX4_VGT;
2360 oper_vport->default_vlan = MLX4_VGT;
2361 admin_vport->qos_vport =
2362 MLX4_VPP_DEFAULT_VPORT;
2363 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2364 vf_oper->vport[port].vlan_idx = NO_INDX;
2365 vf_oper->vport[port].mac_idx = NO_INDX;
2366 mlx4_set_random_admin_guid(dev, i, port);
2367 }
2368 spin_lock_init(&s_state->lock);
2369 }
2370
2371 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2372 for (port = 1; port <= dev->caps.num_ports; port++) {
2373 if (mlx4_is_eth(dev, port)) {
2374 mlx4_set_default_port_qos(dev, port);
2375 mlx4_allocate_port_vpps(dev, port);
2376 }
2377 }
2378 }
2379
2380 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2381 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2382 INIT_WORK(&priv->mfunc.master.comm_work,
2383 mlx4_master_comm_channel);
2384 INIT_WORK(&priv->mfunc.master.slave_event_work,
2385 mlx4_gen_slave_eqe);
2386 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2387 mlx4_master_handle_slave_flr);
2388 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2389 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2390 priv->mfunc.master.comm_wq =
2391 create_singlethread_workqueue("mlx4_comm");
2392 if (!priv->mfunc.master.comm_wq)
2393 goto err_slaves;
2394
2395 if (mlx4_init_resource_tracker(dev))
2396 goto err_thread;
2397
2398 } else {
2399 err = sync_toggles(dev);
2400 if (err) {
2401 mlx4_err(dev, "Couldn't sync toggles\n");
2402 goto err_comm;
2403 }
2404 }
2405 return 0;
2406
2407 err_thread:
2408 flush_workqueue(priv->mfunc.master.comm_wq);
2409 destroy_workqueue(priv->mfunc.master.comm_wq);
2410 err_slaves:
2411 while (--i) {
2412 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2413 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2414 }
2415 kfree(priv->mfunc.master.vf_oper);
2416 err_comm_oper:
2417 kfree(priv->mfunc.master.vf_admin);
2418 err_comm_admin:
2419 kfree(priv->mfunc.master.slave_state);
2420 err_comm:
2421 iounmap(priv->mfunc.comm);
2422 err_vhcr:
2423 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2424 priv->mfunc.vhcr,
2425 priv->mfunc.vhcr_dma);
2426 priv->mfunc.vhcr = NULL;
2427 return -ENOMEM;
2428 }
2429
2430 int mlx4_cmd_init(struct mlx4_dev *dev)
2431 {
2432 struct mlx4_priv *priv = mlx4_priv(dev);
2433 int flags = 0;
2434
2435 if (!priv->cmd.initialized) {
2436 mutex_init(&priv->cmd.slave_cmd_mutex);
2437 sema_init(&priv->cmd.poll_sem, 1);
2438 priv->cmd.use_events = 0;
2439 priv->cmd.toggle = 1;
2440 priv->cmd.initialized = 1;
2441 flags |= MLX4_CMD_CLEANUP_STRUCT;
2442 }
2443
2444 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2445 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2446 0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2447 if (!priv->cmd.hcr) {
2448 mlx4_err(dev, "Couldn't map command register\n");
2449 goto err;
2450 }
2451 flags |= MLX4_CMD_CLEANUP_HCR;
2452 }
2453
2454 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2455 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2456 PAGE_SIZE,
2457 &priv->mfunc.vhcr_dma,
2458 GFP_KERNEL);
2459 if (!priv->mfunc.vhcr)
2460 goto err;
2461
2462 flags |= MLX4_CMD_CLEANUP_VHCR;
2463 }
2464
2465 if (!priv->cmd.pool) {
2466 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2467 dev->persist->pdev,
2468 MLX4_MAILBOX_SIZE,
2469 MLX4_MAILBOX_SIZE, 0);
2470 if (!priv->cmd.pool)
2471 goto err;
2472
2473 flags |= MLX4_CMD_CLEANUP_POOL;
2474 }
2475
2476 return 0;
2477
2478 err:
2479 mlx4_cmd_cleanup(dev, flags);
2480 return -ENOMEM;
2481 }
2482
2483 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2484 {
2485 struct mlx4_priv *priv = mlx4_priv(dev);
2486 int slave;
2487 u32 slave_read;
2488
2489 /* Report an internal error event to all
2490 * communication channels.
2491 */
2492 for (slave = 0; slave < dev->num_slaves; slave++) {
2493 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2494 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2495 __raw_writel((__force u32)cpu_to_be32(slave_read),
2496 &priv->mfunc.comm[slave].slave_read);
2497 /* Make sure that our comm channel write doesn't
2498 * get mixed in with writes from another CPU.
2499 */
2500 mmiowb();
2501 }
2502 }
2503
2504 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2505 {
2506 struct mlx4_priv *priv = mlx4_priv(dev);
2507 int i, port;
2508
2509 if (mlx4_is_master(dev)) {
2510 flush_workqueue(priv->mfunc.master.comm_wq);
2511 destroy_workqueue(priv->mfunc.master.comm_wq);
2512 for (i = 0; i < dev->num_slaves; i++) {
2513 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2514 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2515 }
2516 kfree(priv->mfunc.master.slave_state);
2517 kfree(priv->mfunc.master.vf_admin);
2518 kfree(priv->mfunc.master.vf_oper);
2519 dev->num_slaves = 0;
2520 }
2521
2522 iounmap(priv->mfunc.comm);
2523 }
2524
2525 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2526 {
2527 struct mlx4_priv *priv = mlx4_priv(dev);
2528
2529 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2530 pci_pool_destroy(priv->cmd.pool);
2531 priv->cmd.pool = NULL;
2532 }
2533
2534 if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2535 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2536 iounmap(priv->cmd.hcr);
2537 priv->cmd.hcr = NULL;
2538 }
2539 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2540 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2541 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2542 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2543 priv->mfunc.vhcr = NULL;
2544 }
2545 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2546 priv->cmd.initialized = 0;
2547 }
2548
2549 /*
2550 * Switch to using events to issue FW commands (can only be called
2551 * after event queue for command events has been initialized).
2552 */
2553 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2554 {
2555 struct mlx4_priv *priv = mlx4_priv(dev);
2556 int i;
2557 int err = 0;
2558
2559 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2560 sizeof (struct mlx4_cmd_context),
2561 GFP_KERNEL);
2562 if (!priv->cmd.context)
2563 return -ENOMEM;
2564
2565 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2566 priv->cmd.context[i].token = i;
2567 priv->cmd.context[i].next = i + 1;
2568 /* To support fatal error flow, initialize all
2569 * cmd contexts to allow simulating completions
2570 * with complete() at any time.
2571 */
2572 init_completion(&priv->cmd.context[i].done);
2573 }
2574
2575 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2576 priv->cmd.free_head = 0;
2577
2578 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2579 spin_lock_init(&priv->cmd.context_lock);
2580
2581 for (priv->cmd.token_mask = 1;
2582 priv->cmd.token_mask < priv->cmd.max_cmds;
2583 priv->cmd.token_mask <<= 1)
2584 ; /* nothing */
2585 --priv->cmd.token_mask;
2586
2587 down(&priv->cmd.poll_sem);
2588 priv->cmd.use_events = 1;
2589
2590 return err;
2591 }
2592
2593 /*
2594 * Switch back to polling (used when shutting down the device)
2595 */
2596 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2597 {
2598 struct mlx4_priv *priv = mlx4_priv(dev);
2599 int i;
2600
2601 priv->cmd.use_events = 0;
2602
2603 for (i = 0; i < priv->cmd.max_cmds; ++i)
2604 down(&priv->cmd.event_sem);
2605
2606 kfree(priv->cmd.context);
2607
2608 up(&priv->cmd.poll_sem);
2609 }
2610
2611 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2612 {
2613 struct mlx4_cmd_mailbox *mailbox;
2614
2615 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2616 if (!mailbox)
2617 return ERR_PTR(-ENOMEM);
2618
2619 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2620 &mailbox->dma);
2621 if (!mailbox->buf) {
2622 kfree(mailbox);
2623 return ERR_PTR(-ENOMEM);
2624 }
2625
2626 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2627
2628 return mailbox;
2629 }
2630 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2631
2632 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2633 struct mlx4_cmd_mailbox *mailbox)
2634 {
2635 if (!mailbox)
2636 return;
2637
2638 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2639 kfree(mailbox);
2640 }
2641 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2642
2643 u32 mlx4_comm_get_version(void)
2644 {
2645 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2646 }
2647
2648 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2649 {
2650 if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2651 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2652 vf, dev->persist->num_vfs);
2653 return -EINVAL;
2654 }
2655
2656 return vf+1;
2657 }
2658
2659 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2660 {
2661 if (slave < 1 || slave > dev->persist->num_vfs) {
2662 mlx4_err(dev,
2663 "Bad slave number:%d (number of activated slaves: %lu)\n",
2664 slave, dev->num_slaves);
2665 return -EINVAL;
2666 }
2667 return slave - 1;
2668 }
2669
2670 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2671 {
2672 struct mlx4_priv *priv = mlx4_priv(dev);
2673 struct mlx4_cmd_context *context;
2674 int i;
2675
2676 spin_lock(&priv->cmd.context_lock);
2677 if (priv->cmd.context) {
2678 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2679 context = &priv->cmd.context[i];
2680 context->fw_status = CMD_STAT_INTERNAL_ERR;
2681 context->result =
2682 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2683 complete(&context->done);
2684 }
2685 }
2686 spin_unlock(&priv->cmd.context_lock);
2687 }
2688
2689 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2690 {
2691 struct mlx4_active_ports actv_ports;
2692 int vf;
2693
2694 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2695
2696 if (slave == 0) {
2697 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2698 return actv_ports;
2699 }
2700
2701 vf = mlx4_get_vf_indx(dev, slave);
2702 if (vf < 0)
2703 return actv_ports;
2704
2705 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2706 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2707 dev->caps.num_ports));
2708
2709 return actv_ports;
2710 }
2711 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2712
2713 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2714 {
2715 unsigned n;
2716 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2717 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2718
2719 if (port <= 0 || port > m)
2720 return -EINVAL;
2721
2722 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2723 if (port <= n)
2724 port = n + 1;
2725
2726 return port;
2727 }
2728 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2729
2730 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2731 {
2732 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2733 if (test_bit(port - 1, actv_ports.ports))
2734 return port -
2735 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2736
2737 return -1;
2738 }
2739 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2740
2741 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2742 int port)
2743 {
2744 unsigned i;
2745 struct mlx4_slaves_pport slaves_pport;
2746
2747 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2748
2749 if (port <= 0 || port > dev->caps.num_ports)
2750 return slaves_pport;
2751
2752 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2753 struct mlx4_active_ports actv_ports =
2754 mlx4_get_active_ports(dev, i);
2755 if (test_bit(port - 1, actv_ports.ports))
2756 set_bit(i, slaves_pport.slaves);
2757 }
2758
2759 return slaves_pport;
2760 }
2761 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2762
2763 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2764 struct mlx4_dev *dev,
2765 const struct mlx4_active_ports *crit_ports)
2766 {
2767 unsigned i;
2768 struct mlx4_slaves_pport slaves_pport;
2769
2770 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2771
2772 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2773 struct mlx4_active_ports actv_ports =
2774 mlx4_get_active_ports(dev, i);
2775 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2776 dev->caps.num_ports))
2777 set_bit(i, slaves_pport.slaves);
2778 }
2779
2780 return slaves_pport;
2781 }
2782 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2783
2784 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2785 {
2786 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2787 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2788 + 1;
2789 int max_port = min_port +
2790 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2791
2792 if (port < min_port)
2793 port = min_port;
2794 else if (port >= max_port)
2795 port = max_port - 1;
2796
2797 return port;
2798 }
2799
2800 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2801 int max_tx_rate)
2802 {
2803 int i;
2804 int err;
2805 struct mlx4_qos_manager *port_qos;
2806 struct mlx4_dev *dev = &priv->dev;
2807 struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2808
2809 port_qos = &priv->mfunc.master.qos_ctl[port];
2810 memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2811
2812 if (slave > port_qos->num_of_qos_vfs) {
2813 mlx4_info(dev, "No availible VPP resources for this VF\n");
2814 return -EINVAL;
2815 }
2816
2817 /* Query for default QoS values from Vport 0 is needed */
2818 err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2819 if (err) {
2820 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2821 return err;
2822 }
2823
2824 for (i = 0; i < MLX4_NUM_UP; i++) {
2825 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2826 vpp_qos[i].max_avg_bw = max_tx_rate;
2827 vpp_qos[i].enable = 1;
2828 } else {
2829 /* if user supplied tx_rate == 0, meaning no rate limit
2830 * configuration is required. so we are leaving the
2831 * value of max_avg_bw as queried from Vport 0.
2832 */
2833 vpp_qos[i].enable = 0;
2834 }
2835 }
2836
2837 err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2838 if (err) {
2839 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2840 return err;
2841 }
2842
2843 return 0;
2844 }
2845
2846 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2847 struct mlx4_vport_state *vf_admin)
2848 {
2849 struct mlx4_qos_manager *info;
2850 struct mlx4_priv *priv = mlx4_priv(dev);
2851
2852 if (!mlx4_is_master(dev) ||
2853 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2854 return false;
2855
2856 info = &priv->mfunc.master.qos_ctl[port];
2857
2858 if (vf_admin->default_vlan != MLX4_VGT &&
2859 test_bit(vf_admin->default_qos, info->priority_bm))
2860 return true;
2861
2862 return false;
2863 }
2864
2865 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2866 struct mlx4_vport_state *vf_admin,
2867 int vlan, int qos)
2868 {
2869 struct mlx4_vport_state dummy_admin = {0};
2870
2871 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2872 !vf_admin->tx_rate)
2873 return true;
2874
2875 dummy_admin.default_qos = qos;
2876 dummy_admin.default_vlan = vlan;
2877
2878 /* VF wants to move to other VST state which is valid with current
2879 * rate limit. Either differnt default vlan in VST or other
2880 * supported QoS priority. Otherwise we don't allow this change when
2881 * the TX rate is still configured.
2882 */
2883 if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2884 return true;
2885
2886 mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2887 (vlan == MLX4_VGT) ? "VGT" : "VST");
2888
2889 if (vlan != MLX4_VGT)
2890 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2891
2892 mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2893
2894 return false;
2895 }
2896
2897 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2898 {
2899 struct mlx4_priv *priv = mlx4_priv(dev);
2900 struct mlx4_vport_state *s_info;
2901 int slave;
2902
2903 if (!mlx4_is_master(dev))
2904 return -EPROTONOSUPPORT;
2905
2906 slave = mlx4_get_slave_indx(dev, vf);
2907 if (slave < 0)
2908 return -EINVAL;
2909
2910 port = mlx4_slaves_closest_port(dev, slave, port);
2911 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2912 s_info->mac = mac;
2913 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2914 vf, port, s_info->mac);
2915 return 0;
2916 }
2917 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2918
2919
2920 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2921 {
2922 struct mlx4_priv *priv = mlx4_priv(dev);
2923 struct mlx4_vport_state *vf_admin;
2924 int slave;
2925
2926 if ((!mlx4_is_master(dev)) ||
2927 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2928 return -EPROTONOSUPPORT;
2929
2930 if ((vlan > 4095) || (qos > 7))
2931 return -EINVAL;
2932
2933 slave = mlx4_get_slave_indx(dev, vf);
2934 if (slave < 0)
2935 return -EINVAL;
2936
2937 port = mlx4_slaves_closest_port(dev, slave, port);
2938 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2939
2940 if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
2941 return -EPERM;
2942
2943 if ((0 == vlan) && (0 == qos))
2944 vf_admin->default_vlan = MLX4_VGT;
2945 else
2946 vf_admin->default_vlan = vlan;
2947 vf_admin->default_qos = qos;
2948
2949 /* If rate was configured prior to VST, we saved the configured rate
2950 * in vf_admin->rate and now, if priority supported we enforce the QoS
2951 */
2952 if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
2953 vf_admin->tx_rate)
2954 vf_admin->qos_vport = slave;
2955
2956 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2957 mlx4_info(dev,
2958 "updating vf %d port %d config will take effect on next VF restart\n",
2959 vf, port);
2960 return 0;
2961 }
2962 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2963
2964 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
2965 int max_tx_rate)
2966 {
2967 int err;
2968 int slave;
2969 struct mlx4_vport_state *vf_admin;
2970 struct mlx4_priv *priv = mlx4_priv(dev);
2971
2972 if (!mlx4_is_master(dev) ||
2973 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2974 return -EPROTONOSUPPORT;
2975
2976 if (min_tx_rate) {
2977 mlx4_info(dev, "Minimum BW share not supported\n");
2978 return -EPROTONOSUPPORT;
2979 }
2980
2981 slave = mlx4_get_slave_indx(dev, vf);
2982 if (slave < 0)
2983 return -EINVAL;
2984
2985 port = mlx4_slaves_closest_port(dev, slave, port);
2986 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2987
2988 err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
2989 if (err) {
2990 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
2991 max_tx_rate);
2992 return err;
2993 }
2994
2995 vf_admin->tx_rate = max_tx_rate;
2996 /* if VF is not in supported mode (VST with supported prio),
2997 * we do not change vport configuration for its QPs, but save
2998 * the rate, so it will be enforced when it moves to supported
2999 * mode next time.
3000 */
3001 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
3002 mlx4_info(dev,
3003 "rate set for VF %d when not in valid state\n", vf);
3004
3005 if (vf_admin->default_vlan != MLX4_VGT)
3006 mlx4_info(dev, "VST priority not supported by QoS\n");
3007 else
3008 mlx4_info(dev, "VF in VGT mode (needed VST)\n");
3009
3010 mlx4_info(dev,
3011 "rate %d take affect when VF moves to valid state\n",
3012 max_tx_rate);
3013 return 0;
3014 }
3015
3016 /* If user sets rate 0 assigning default vport for its QPs */
3017 vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3018
3019 if (priv->mfunc.master.slave_state[slave].active &&
3020 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3021 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3022
3023 return 0;
3024 }
3025 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3026
3027 /* mlx4_get_slave_default_vlan -
3028 * return true if VST ( default vlan)
3029 * if VST, will return vlan & qos (if not NULL)
3030 */
3031 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3032 u16 *vlan, u8 *qos)
3033 {
3034 struct mlx4_vport_oper_state *vp_oper;
3035 struct mlx4_priv *priv;
3036
3037 priv = mlx4_priv(dev);
3038 port = mlx4_slaves_closest_port(dev, slave, port);
3039 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3040
3041 if (MLX4_VGT != vp_oper->state.default_vlan) {
3042 if (vlan)
3043 *vlan = vp_oper->state.default_vlan;
3044 if (qos)
3045 *qos = vp_oper->state.default_qos;
3046 return true;
3047 }
3048 return false;
3049 }
3050 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3051
3052 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3053 {
3054 struct mlx4_priv *priv = mlx4_priv(dev);
3055 struct mlx4_vport_state *s_info;
3056 int slave;
3057
3058 if ((!mlx4_is_master(dev)) ||
3059 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3060 return -EPROTONOSUPPORT;
3061
3062 slave = mlx4_get_slave_indx(dev, vf);
3063 if (slave < 0)
3064 return -EINVAL;
3065
3066 port = mlx4_slaves_closest_port(dev, slave, port);
3067 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3068 s_info->spoofchk = setting;
3069
3070 return 0;
3071 }
3072 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3073
3074 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3075 {
3076 struct mlx4_priv *priv = mlx4_priv(dev);
3077 struct mlx4_vport_state *s_info;
3078 int slave;
3079
3080 if (!mlx4_is_master(dev))
3081 return -EPROTONOSUPPORT;
3082
3083 slave = mlx4_get_slave_indx(dev, vf);
3084 if (slave < 0)
3085 return -EINVAL;
3086
3087 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3088 ivf->vf = vf;
3089
3090 /* need to convert it to a func */
3091 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3092 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3093 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3094 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3095 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3096 ivf->mac[5] = ((s_info->mac) & 0xff);
3097
3098 ivf->vlan = s_info->default_vlan;
3099 ivf->qos = s_info->default_qos;
3100
3101 if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3102 ivf->max_tx_rate = s_info->tx_rate;
3103 else
3104 ivf->max_tx_rate = 0;
3105
3106 ivf->min_tx_rate = 0;
3107 ivf->spoofchk = s_info->spoofchk;
3108 ivf->linkstate = s_info->link_state;
3109
3110 return 0;
3111 }
3112 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3113
3114 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3115 {
3116 struct mlx4_priv *priv = mlx4_priv(dev);
3117 struct mlx4_vport_state *s_info;
3118 int slave;
3119 u8 link_stat_event;
3120
3121 slave = mlx4_get_slave_indx(dev, vf);
3122 if (slave < 0)
3123 return -EINVAL;
3124
3125 port = mlx4_slaves_closest_port(dev, slave, port);
3126 switch (link_state) {
3127 case IFLA_VF_LINK_STATE_AUTO:
3128 /* get current link state */
3129 if (!priv->sense.do_sense_port[port])
3130 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3131 else
3132 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3133 break;
3134
3135 case IFLA_VF_LINK_STATE_ENABLE:
3136 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3137 break;
3138
3139 case IFLA_VF_LINK_STATE_DISABLE:
3140 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3141 break;
3142
3143 default:
3144 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3145 link_state, slave, port);
3146 return -EINVAL;
3147 };
3148 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3149 s_info->link_state = link_state;
3150
3151 /* send event */
3152 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3153
3154 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3155 mlx4_dbg(dev,
3156 "updating vf %d port %d no link state HW enforcment\n",
3157 vf, port);
3158 return 0;
3159 }
3160 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3161
3162 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3163 {
3164 struct mlx4_priv *priv = mlx4_priv(dev);
3165
3166 if (slave < 1 || slave >= dev->num_slaves ||
3167 port < 1 || port > MLX4_MAX_PORTS)
3168 return 0;
3169
3170 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3171 MLX4_VF_SMI_ENABLED;
3172 }
3173 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3174
3175 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3176 {
3177 struct mlx4_priv *priv = mlx4_priv(dev);
3178
3179 if (slave == mlx4_master_func_num(dev))
3180 return 1;
3181
3182 if (slave < 1 || slave >= dev->num_slaves ||
3183 port < 1 || port > MLX4_MAX_PORTS)
3184 return 0;
3185
3186 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3187 MLX4_VF_SMI_ENABLED;
3188 }
3189 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3190
3191 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3192 int enabled)
3193 {
3194 struct mlx4_priv *priv = mlx4_priv(dev);
3195
3196 if (slave == mlx4_master_func_num(dev))
3197 return 0;
3198
3199 if (slave < 1 || slave >= dev->num_slaves ||
3200 port < 1 || port > MLX4_MAX_PORTS ||
3201 enabled < 0 || enabled > 1)
3202 return -EINVAL;
3203
3204 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3205 return 0;
3206 }
3207 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);
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