2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
45 #include <linux/delay.h>
46 #include <linux/etherdevice.h>
53 #include "mlx4_stats.h"
55 #define CMD_POLL_TOKEN 0xffff
56 #define INBOX_MASK 0xffffffffffffff00ULL
58 #define CMD_CHAN_VER 1
59 #define CMD_CHAN_IF_REV 1
62 /* command completed successfully: */
64 /* Internal error (such as a bus error) occurred while processing command: */
65 CMD_STAT_INTERNAL_ERR
= 0x01,
66 /* Operation/command not supported or opcode modifier not supported: */
67 CMD_STAT_BAD_OP
= 0x02,
68 /* Parameter not supported or parameter out of range: */
69 CMD_STAT_BAD_PARAM
= 0x03,
70 /* System not enabled or bad system state: */
71 CMD_STAT_BAD_SYS_STATE
= 0x04,
72 /* Attempt to access reserved or unallocaterd resource: */
73 CMD_STAT_BAD_RESOURCE
= 0x05,
74 /* Requested resource is currently executing a command, or is otherwise busy: */
75 CMD_STAT_RESOURCE_BUSY
= 0x06,
76 /* Required capability exceeds device limits: */
77 CMD_STAT_EXCEED_LIM
= 0x08,
78 /* Resource is not in the appropriate state or ownership: */
79 CMD_STAT_BAD_RES_STATE
= 0x09,
80 /* Index out of range: */
81 CMD_STAT_BAD_INDEX
= 0x0a,
82 /* FW image corrupted: */
83 CMD_STAT_BAD_NVMEM
= 0x0b,
84 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
85 CMD_STAT_ICM_ERROR
= 0x0c,
86 /* Attempt to modify a QP/EE which is not in the presumed state: */
87 CMD_STAT_BAD_QP_STATE
= 0x10,
88 /* Bad segment parameters (Address/Size): */
89 CMD_STAT_BAD_SEG_PARAM
= 0x20,
90 /* Memory Region has Memory Windows bound to: */
91 CMD_STAT_REG_BOUND
= 0x21,
92 /* HCA local attached memory not present: */
93 CMD_STAT_LAM_NOT_PRE
= 0x22,
94 /* Bad management packet (silently discarded): */
95 CMD_STAT_BAD_PKT
= 0x30,
96 /* More outstanding CQEs in CQ than new CQ size: */
97 CMD_STAT_BAD_SIZE
= 0x40,
98 /* Multi Function device support required: */
99 CMD_STAT_MULTI_FUNC_REQ
= 0x50,
103 HCR_IN_PARAM_OFFSET
= 0x00,
104 HCR_IN_MODIFIER_OFFSET
= 0x08,
105 HCR_OUT_PARAM_OFFSET
= 0x0c,
106 HCR_TOKEN_OFFSET
= 0x14,
107 HCR_STATUS_OFFSET
= 0x18,
109 HCR_OPMOD_SHIFT
= 12,
116 GO_BIT_TIMEOUT_MSECS
= 10000
119 enum mlx4_vlan_transition
{
120 MLX4_VLAN_TRANSITION_VST_VST
= 0,
121 MLX4_VLAN_TRANSITION_VST_VGT
= 1,
122 MLX4_VLAN_TRANSITION_VGT_VST
= 2,
123 MLX4_VLAN_TRANSITION_VGT_VGT
= 3,
127 struct mlx4_cmd_context
{
128 struct completion done
;
136 static int mlx4_master_process_vhcr(struct mlx4_dev
*dev
, int slave
,
137 struct mlx4_vhcr_cmd
*in_vhcr
);
139 static int mlx4_status_to_errno(u8 status
)
141 static const int trans_table
[] = {
142 [CMD_STAT_INTERNAL_ERR
] = -EIO
,
143 [CMD_STAT_BAD_OP
] = -EPERM
,
144 [CMD_STAT_BAD_PARAM
] = -EINVAL
,
145 [CMD_STAT_BAD_SYS_STATE
] = -ENXIO
,
146 [CMD_STAT_BAD_RESOURCE
] = -EBADF
,
147 [CMD_STAT_RESOURCE_BUSY
] = -EBUSY
,
148 [CMD_STAT_EXCEED_LIM
] = -ENOMEM
,
149 [CMD_STAT_BAD_RES_STATE
] = -EBADF
,
150 [CMD_STAT_BAD_INDEX
] = -EBADF
,
151 [CMD_STAT_BAD_NVMEM
] = -EFAULT
,
152 [CMD_STAT_ICM_ERROR
] = -ENFILE
,
153 [CMD_STAT_BAD_QP_STATE
] = -EINVAL
,
154 [CMD_STAT_BAD_SEG_PARAM
] = -EFAULT
,
155 [CMD_STAT_REG_BOUND
] = -EBUSY
,
156 [CMD_STAT_LAM_NOT_PRE
] = -EAGAIN
,
157 [CMD_STAT_BAD_PKT
] = -EINVAL
,
158 [CMD_STAT_BAD_SIZE
] = -ENOMEM
,
159 [CMD_STAT_MULTI_FUNC_REQ
] = -EACCES
,
162 if (status
>= ARRAY_SIZE(trans_table
) ||
163 (status
!= CMD_STAT_OK
&& trans_table
[status
] == 0))
166 return trans_table
[status
];
169 static u8
mlx4_errno_to_status(int errno
)
173 return CMD_STAT_BAD_OP
;
175 return CMD_STAT_BAD_PARAM
;
177 return CMD_STAT_BAD_SYS_STATE
;
179 return CMD_STAT_RESOURCE_BUSY
;
181 return CMD_STAT_EXCEED_LIM
;
183 return CMD_STAT_ICM_ERROR
;
185 return CMD_STAT_INTERNAL_ERR
;
189 static int mlx4_internal_err_ret_value(struct mlx4_dev
*dev
, u16 op
,
193 case MLX4_CMD_UNMAP_ICM
:
194 case MLX4_CMD_UNMAP_ICM_AUX
:
195 case MLX4_CMD_UNMAP_FA
:
196 case MLX4_CMD_2RST_QP
:
197 case MLX4_CMD_HW2SW_EQ
:
198 case MLX4_CMD_HW2SW_CQ
:
199 case MLX4_CMD_HW2SW_SRQ
:
200 case MLX4_CMD_HW2SW_MPT
:
201 case MLX4_CMD_CLOSE_HCA
:
202 case MLX4_QP_FLOW_STEERING_DETACH
:
203 case MLX4_CMD_FREE_RES
:
204 case MLX4_CMD_CLOSE_PORT
:
207 case MLX4_CMD_QP_ATTACH
:
208 /* On Detach case return success */
209 if (op_modifier
== 0)
211 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
214 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
218 static int mlx4_closing_cmd_fatal_error(u16 op
, u8 fw_status
)
220 /* Any error during the closing commands below is considered fatal */
221 if (op
== MLX4_CMD_CLOSE_HCA
||
222 op
== MLX4_CMD_HW2SW_EQ
||
223 op
== MLX4_CMD_HW2SW_CQ
||
224 op
== MLX4_CMD_2RST_QP
||
225 op
== MLX4_CMD_HW2SW_SRQ
||
226 op
== MLX4_CMD_SYNC_TPT
||
227 op
== MLX4_CMD_UNMAP_ICM
||
228 op
== MLX4_CMD_UNMAP_ICM_AUX
||
229 op
== MLX4_CMD_UNMAP_FA
)
231 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
232 * CMD_STAT_REG_BOUND.
233 * This status indicates that memory region has memory windows bound to it
234 * which may result from invalid user space usage and is not fatal.
236 if (op
== MLX4_CMD_HW2SW_MPT
&& fw_status
!= CMD_STAT_REG_BOUND
)
241 static int mlx4_cmd_reset_flow(struct mlx4_dev
*dev
, u16 op
, u8 op_modifier
,
244 /* Only if reset flow is really active return code is based on
245 * command, otherwise current error code is returned.
247 if (mlx4_internal_err_reset
) {
248 mlx4_enter_error_state(dev
->persist
);
249 err
= mlx4_internal_err_ret_value(dev
, op
, op_modifier
);
255 static int comm_pending(struct mlx4_dev
*dev
)
257 struct mlx4_priv
*priv
= mlx4_priv(dev
);
258 u32 status
= readl(&priv
->mfunc
.comm
->slave_read
);
260 return (swab32(status
) >> 31) != priv
->cmd
.comm_toggle
;
263 static int mlx4_comm_cmd_post(struct mlx4_dev
*dev
, u8 cmd
, u16 param
)
265 struct mlx4_priv
*priv
= mlx4_priv(dev
);
268 /* To avoid writing to unknown addresses after the device state was
269 * changed to internal error and the function was rest,
270 * check the INTERNAL_ERROR flag which is updated under
271 * device_state_mutex lock.
273 mutex_lock(&dev
->persist
->device_state_mutex
);
275 if (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
) {
276 mutex_unlock(&dev
->persist
->device_state_mutex
);
280 priv
->cmd
.comm_toggle
^= 1;
281 val
= param
| (cmd
<< 16) | (priv
->cmd
.comm_toggle
<< 31);
282 __raw_writel((__force u32
) cpu_to_be32(val
),
283 &priv
->mfunc
.comm
->slave_write
);
285 mutex_unlock(&dev
->persist
->device_state_mutex
);
289 static int mlx4_comm_cmd_poll(struct mlx4_dev
*dev
, u8 cmd
, u16 param
,
290 unsigned long timeout
)
292 struct mlx4_priv
*priv
= mlx4_priv(dev
);
295 int ret_from_pending
= 0;
297 /* First, verify that the master reports correct status */
298 if (comm_pending(dev
)) {
299 mlx4_warn(dev
, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
300 priv
->cmd
.comm_toggle
, cmd
);
305 down(&priv
->cmd
.poll_sem
);
306 if (mlx4_comm_cmd_post(dev
, cmd
, param
)) {
307 /* Only in case the device state is INTERNAL_ERROR,
308 * mlx4_comm_cmd_post returns with an error
310 err
= mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
314 end
= msecs_to_jiffies(timeout
) + jiffies
;
315 while (comm_pending(dev
) && time_before(jiffies
, end
))
317 ret_from_pending
= comm_pending(dev
);
318 if (ret_from_pending
) {
319 /* check if the slave is trying to boot in the middle of
320 * FLR process. The only non-zero result in the RESET command
321 * is MLX4_DELAY_RESET_SLAVE*/
322 if ((MLX4_COMM_CMD_RESET
== cmd
)) {
323 err
= MLX4_DELAY_RESET_SLAVE
;
326 mlx4_warn(dev
, "Communication channel command 0x%x timed out\n",
328 err
= mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
333 mlx4_enter_error_state(dev
->persist
);
335 up(&priv
->cmd
.poll_sem
);
339 static int mlx4_comm_cmd_wait(struct mlx4_dev
*dev
, u8 vhcr_cmd
,
340 u16 param
, u16 op
, unsigned long timeout
)
342 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
343 struct mlx4_cmd_context
*context
;
347 down(&cmd
->event_sem
);
349 spin_lock(&cmd
->context_lock
);
350 BUG_ON(cmd
->free_head
< 0);
351 context
= &cmd
->context
[cmd
->free_head
];
352 context
->token
+= cmd
->token_mask
+ 1;
353 cmd
->free_head
= context
->next
;
354 spin_unlock(&cmd
->context_lock
);
356 reinit_completion(&context
->done
);
358 if (mlx4_comm_cmd_post(dev
, vhcr_cmd
, param
)) {
359 /* Only in case the device state is INTERNAL_ERROR,
360 * mlx4_comm_cmd_post returns with an error
362 err
= mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
366 if (!wait_for_completion_timeout(&context
->done
,
367 msecs_to_jiffies(timeout
))) {
368 mlx4_warn(dev
, "communication channel command 0x%x (op=0x%x) timed out\n",
373 err
= context
->result
;
374 if (err
&& context
->fw_status
!= CMD_STAT_MULTI_FUNC_REQ
) {
375 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
376 vhcr_cmd
, context
->fw_status
);
377 if (mlx4_closing_cmd_fatal_error(op
, context
->fw_status
))
381 /* wait for comm channel ready
382 * this is necessary for prevention the race
383 * when switching between event to polling mode
384 * Skipping this section in case the device is in FATAL_ERROR state,
385 * In this state, no commands are sent via the comm channel until
386 * the device has returned from reset.
388 if (!(dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)) {
389 end
= msecs_to_jiffies(timeout
) + jiffies
;
390 while (comm_pending(dev
) && time_before(jiffies
, end
))
396 err
= mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
397 mlx4_enter_error_state(dev
->persist
);
399 spin_lock(&cmd
->context_lock
);
400 context
->next
= cmd
->free_head
;
401 cmd
->free_head
= context
- cmd
->context
;
402 spin_unlock(&cmd
->context_lock
);
408 int mlx4_comm_cmd(struct mlx4_dev
*dev
, u8 cmd
, u16 param
,
409 u16 op
, unsigned long timeout
)
411 if (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)
412 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
414 if (mlx4_priv(dev
)->cmd
.use_events
)
415 return mlx4_comm_cmd_wait(dev
, cmd
, param
, op
, timeout
);
416 return mlx4_comm_cmd_poll(dev
, cmd
, param
, timeout
);
419 static int cmd_pending(struct mlx4_dev
*dev
)
423 if (pci_channel_offline(dev
->persist
->pdev
))
426 status
= readl(mlx4_priv(dev
)->cmd
.hcr
+ HCR_STATUS_OFFSET
);
428 return (status
& swab32(1 << HCR_GO_BIT
)) ||
429 (mlx4_priv(dev
)->cmd
.toggle
==
430 !!(status
& swab32(1 << HCR_T_BIT
)));
433 static int mlx4_cmd_post(struct mlx4_dev
*dev
, u64 in_param
, u64 out_param
,
434 u32 in_modifier
, u8 op_modifier
, u16 op
, u16 token
,
437 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
438 u32 __iomem
*hcr
= cmd
->hcr
;
442 mutex_lock(&dev
->persist
->device_state_mutex
);
443 /* To avoid writing to unknown addresses after the device state was
444 * changed to internal error and the chip was reset,
445 * check the INTERNAL_ERROR flag which is updated under
446 * device_state_mutex lock.
448 if (pci_channel_offline(dev
->persist
->pdev
) ||
449 (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)) {
451 * Device is going through error recovery
452 * and cannot accept commands.
459 end
+= msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS
);
461 while (cmd_pending(dev
)) {
462 if (pci_channel_offline(dev
->persist
->pdev
)) {
464 * Device is going through error recovery
465 * and cannot accept commands.
470 if (time_after_eq(jiffies
, end
)) {
471 mlx4_err(dev
, "%s:cmd_pending failed\n", __func__
);
478 * We use writel (instead of something like memcpy_toio)
479 * because writes of less than 32 bits to the HCR don't work
480 * (and some architectures such as ia64 implement memcpy_toio
481 * in terms of writeb).
483 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), hcr
+ 0);
484 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), hcr
+ 1);
485 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), hcr
+ 2);
486 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), hcr
+ 3);
487 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), hcr
+ 4);
488 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), hcr
+ 5);
490 /* __raw_writel may not order writes. */
493 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
494 (cmd
->toggle
<< HCR_T_BIT
) |
495 (event
? (1 << HCR_E_BIT
) : 0) |
496 (op_modifier
<< HCR_OPMOD_SHIFT
) |
500 * Make sure that our HCR writes don't get mixed in with
501 * writes from another CPU starting a FW command.
505 cmd
->toggle
= cmd
->toggle
^ 1;
511 mlx4_warn(dev
, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
512 op
, ret
, in_param
, in_modifier
, op_modifier
);
513 mutex_unlock(&dev
->persist
->device_state_mutex
);
518 static int mlx4_slave_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
519 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
520 u16 op
, unsigned long timeout
)
522 struct mlx4_priv
*priv
= mlx4_priv(dev
);
523 struct mlx4_vhcr_cmd
*vhcr
= priv
->mfunc
.vhcr
;
526 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
528 vhcr
->in_param
= cpu_to_be64(in_param
);
529 vhcr
->out_param
= out_param
? cpu_to_be64(*out_param
) : 0;
530 vhcr
->in_modifier
= cpu_to_be32(in_modifier
);
531 vhcr
->opcode
= cpu_to_be16((((u16
) op_modifier
) << 12) | (op
& 0xfff));
532 vhcr
->token
= cpu_to_be16(CMD_POLL_TOKEN
);
534 vhcr
->flags
= !!(priv
->cmd
.use_events
) << 6;
536 if (mlx4_is_master(dev
)) {
537 ret
= mlx4_master_process_vhcr(dev
, dev
->caps
.function
, vhcr
);
542 be64_to_cpu(vhcr
->out_param
);
544 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
546 vhcr
->status
= CMD_STAT_BAD_PARAM
;
549 ret
= mlx4_status_to_errno(vhcr
->status
);
552 dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)
553 ret
= mlx4_internal_err_ret_value(dev
, op
, op_modifier
);
555 ret
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_POST
, 0, op
,
556 MLX4_COMM_TIME
+ timeout
);
561 be64_to_cpu(vhcr
->out_param
);
563 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
565 vhcr
->status
= CMD_STAT_BAD_PARAM
;
568 ret
= mlx4_status_to_errno(vhcr
->status
);
570 if (dev
->persist
->state
&
571 MLX4_DEVICE_STATE_INTERNAL_ERROR
)
572 ret
= mlx4_internal_err_ret_value(dev
, op
,
575 mlx4_err(dev
, "failed execution of VHCR_POST command opcode 0x%x\n", op
);
579 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
583 static int mlx4_cmd_poll(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
584 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
585 u16 op
, unsigned long timeout
)
587 struct mlx4_priv
*priv
= mlx4_priv(dev
);
588 void __iomem
*hcr
= priv
->cmd
.hcr
;
593 down(&priv
->cmd
.poll_sem
);
595 if (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
) {
597 * Device is going through error recovery
598 * and cannot accept commands.
600 err
= mlx4_internal_err_ret_value(dev
, op
, op_modifier
);
604 if (out_is_imm
&& !out_param
) {
605 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
611 err
= mlx4_cmd_post(dev
, in_param
, out_param
? *out_param
: 0,
612 in_modifier
, op_modifier
, op
, CMD_POLL_TOKEN
, 0);
616 end
= msecs_to_jiffies(timeout
) + jiffies
;
617 while (cmd_pending(dev
) && time_before(jiffies
, end
)) {
618 if (pci_channel_offline(dev
->persist
->pdev
)) {
620 * Device is going through error recovery
621 * and cannot accept commands.
627 if (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
) {
628 err
= mlx4_internal_err_ret_value(dev
, op
, op_modifier
);
635 if (cmd_pending(dev
)) {
636 mlx4_warn(dev
, "command 0x%x timed out (go bit not cleared)\n",
644 (u64
) be32_to_cpu((__force __be32
)
645 __raw_readl(hcr
+ HCR_OUT_PARAM_OFFSET
)) << 32 |
646 (u64
) be32_to_cpu((__force __be32
)
647 __raw_readl(hcr
+ HCR_OUT_PARAM_OFFSET
+ 4));
648 stat
= be32_to_cpu((__force __be32
)
649 __raw_readl(hcr
+ HCR_STATUS_OFFSET
)) >> 24;
650 err
= mlx4_status_to_errno(stat
);
652 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
654 if (mlx4_closing_cmd_fatal_error(op
, stat
))
661 err
= mlx4_cmd_reset_flow(dev
, op
, op_modifier
, err
);
663 up(&priv
->cmd
.poll_sem
);
667 void mlx4_cmd_event(struct mlx4_dev
*dev
, u16 token
, u8 status
, u64 out_param
)
669 struct mlx4_priv
*priv
= mlx4_priv(dev
);
670 struct mlx4_cmd_context
*context
=
671 &priv
->cmd
.context
[token
& priv
->cmd
.token_mask
];
673 /* previously timed out command completing at long last */
674 if (token
!= context
->token
)
677 context
->fw_status
= status
;
678 context
->result
= mlx4_status_to_errno(status
);
679 context
->out_param
= out_param
;
681 complete(&context
->done
);
684 static int mlx4_cmd_wait(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
685 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
686 u16 op
, unsigned long timeout
)
688 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
689 struct mlx4_cmd_context
*context
;
693 down(&cmd
->event_sem
);
695 spin_lock(&cmd
->context_lock
);
696 BUG_ON(cmd
->free_head
< 0);
697 context
= &cmd
->context
[cmd
->free_head
];
698 context
->token
+= cmd
->token_mask
+ 1;
699 cmd
->free_head
= context
->next
;
700 spin_unlock(&cmd
->context_lock
);
702 if (out_is_imm
&& !out_param
) {
703 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
709 reinit_completion(&context
->done
);
711 err
= mlx4_cmd_post(dev
, in_param
, out_param
? *out_param
: 0,
712 in_modifier
, op_modifier
, op
, context
->token
, 1);
716 if (op
== MLX4_CMD_SENSE_PORT
) {
718 wait_for_completion_interruptible_timeout(&context
->done
,
719 msecs_to_jiffies(timeout
));
721 context
->fw_status
= 0;
722 context
->out_param
= 0;
726 ret_wait
= (long)wait_for_completion_timeout(&context
->done
,
727 msecs_to_jiffies(timeout
));
730 mlx4_warn(dev
, "command 0x%x timed out (go bit not cleared)\n",
732 if (op
== MLX4_CMD_NOP
) {
741 err
= context
->result
;
743 /* Since we do not want to have this error message always
744 * displayed at driver start when there are ConnectX2 HCAs
745 * on the host, we deprecate the error message for this
746 * specific command/input_mod/opcode_mod/fw-status to be debug.
748 if (op
== MLX4_CMD_SET_PORT
&&
749 (in_modifier
== 1 || in_modifier
== 2) &&
750 op_modifier
== MLX4_SET_PORT_IB_OPCODE
&&
751 context
->fw_status
== CMD_STAT_BAD_SIZE
)
752 mlx4_dbg(dev
, "command 0x%x failed: fw status = 0x%x\n",
753 op
, context
->fw_status
);
755 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
756 op
, context
->fw_status
);
757 if (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)
758 err
= mlx4_internal_err_ret_value(dev
, op
, op_modifier
);
759 else if (mlx4_closing_cmd_fatal_error(op
, context
->fw_status
))
766 *out_param
= context
->out_param
;
770 err
= mlx4_cmd_reset_flow(dev
, op
, op_modifier
, err
);
772 spin_lock(&cmd
->context_lock
);
773 context
->next
= cmd
->free_head
;
774 cmd
->free_head
= context
- cmd
->context
;
775 spin_unlock(&cmd
->context_lock
);
781 int __mlx4_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
782 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
783 u16 op
, unsigned long timeout
, int native
)
785 if (pci_channel_offline(dev
->persist
->pdev
))
786 return mlx4_cmd_reset_flow(dev
, op
, op_modifier
, -EIO
);
788 if (!mlx4_is_mfunc(dev
) || (native
&& mlx4_is_master(dev
))) {
791 if (dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)
792 return mlx4_internal_err_ret_value(dev
, op
,
794 down_read(&mlx4_priv(dev
)->cmd
.switch_sem
);
795 if (mlx4_priv(dev
)->cmd
.use_events
)
796 ret
= mlx4_cmd_wait(dev
, in_param
, out_param
,
797 out_is_imm
, in_modifier
,
798 op_modifier
, op
, timeout
);
800 ret
= mlx4_cmd_poll(dev
, in_param
, out_param
,
801 out_is_imm
, in_modifier
,
802 op_modifier
, op
, timeout
);
804 up_read(&mlx4_priv(dev
)->cmd
.switch_sem
);
807 return mlx4_slave_cmd(dev
, in_param
, out_param
, out_is_imm
,
808 in_modifier
, op_modifier
, op
, timeout
);
810 EXPORT_SYMBOL_GPL(__mlx4_cmd
);
813 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev
*dev
)
815 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL
,
816 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
819 static int mlx4_ACCESS_MEM(struct mlx4_dev
*dev
, u64 master_addr
,
820 int slave
, u64 slave_addr
,
821 int size
, int is_read
)
826 if ((slave_addr
& 0xfff) | (master_addr
& 0xfff) |
827 (slave
& ~0x7f) | (size
& 0xff)) {
828 mlx4_err(dev
, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
829 slave_addr
, master_addr
, slave
, size
);
834 in_param
= (u64
) slave
| slave_addr
;
835 out_param
= (u64
) dev
->caps
.function
| master_addr
;
837 in_param
= (u64
) dev
->caps
.function
| master_addr
;
838 out_param
= (u64
) slave
| slave_addr
;
841 return mlx4_cmd_imm(dev
, in_param
, &out_param
, size
, 0,
843 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
846 static int query_pkey_block(struct mlx4_dev
*dev
, u8 port
, u16 index
, u16
*pkey
,
847 struct mlx4_cmd_mailbox
*inbox
,
848 struct mlx4_cmd_mailbox
*outbox
)
850 struct ib_smp
*in_mad
= (struct ib_smp
*)(inbox
->buf
);
851 struct ib_smp
*out_mad
= (struct ib_smp
*)(outbox
->buf
);
858 in_mad
->attr_mod
= cpu_to_be32(index
/ 32);
860 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
, port
, 3,
861 MLX4_CMD_MAD_IFC
, MLX4_CMD_TIME_CLASS_C
,
866 for (i
= 0; i
< 32; ++i
)
867 pkey
[i
] = be16_to_cpu(((__be16
*) out_mad
->data
)[i
]);
872 static int get_full_pkey_table(struct mlx4_dev
*dev
, u8 port
, u16
*table
,
873 struct mlx4_cmd_mailbox
*inbox
,
874 struct mlx4_cmd_mailbox
*outbox
)
879 for (i
= 0; i
< dev
->caps
.pkey_table_len
[port
]; i
+= 32) {
880 err
= query_pkey_block(dev
, port
, i
, table
+ i
, inbox
, outbox
);
887 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
888 #define PORT_STATE_OFFSET 32
890 static enum ib_port_state
vf_port_state(struct mlx4_dev
*dev
, int port
, int vf
)
892 if (mlx4_get_slave_port_state(dev
, vf
, port
) == SLAVE_PORT_UP
)
893 return IB_PORT_ACTIVE
;
898 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev
*dev
, int slave
,
899 struct mlx4_vhcr
*vhcr
,
900 struct mlx4_cmd_mailbox
*inbox
,
901 struct mlx4_cmd_mailbox
*outbox
,
902 struct mlx4_cmd_info
*cmd
)
904 struct ib_smp
*smp
= inbox
->buf
;
912 struct mlx4_priv
*priv
= mlx4_priv(dev
);
913 struct ib_smp
*outsmp
= outbox
->buf
;
914 __be16
*outtab
= (__be16
*)(outsmp
->data
);
915 __be32 slave_cap_mask
;
916 __be64 slave_node_guid
;
918 slave_port
= vhcr
->in_modifier
;
919 port
= mlx4_slave_convert_port(dev
, slave
, slave_port
);
921 /* network-view bit is for driver use only, and should not be passed to FW */
922 opcode_modifier
= vhcr
->op_modifier
& ~0x8; /* clear netw view bit */
923 network_view
= !!(vhcr
->op_modifier
& 0x8);
925 if (smp
->base_version
== 1 &&
926 smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_LID_ROUTED
&&
927 smp
->class_version
== 1) {
928 /* host view is paravirtualized */
929 if (!network_view
&& smp
->method
== IB_MGMT_METHOD_GET
) {
930 if (smp
->attr_id
== IB_SMP_ATTR_PKEY_TABLE
) {
931 index
= be32_to_cpu(smp
->attr_mod
);
932 if (port
< 1 || port
> dev
->caps
.num_ports
)
934 table
= kcalloc((dev
->caps
.pkey_table_len
[port
] / 32) + 1,
935 sizeof(*table
) * 32, GFP_KERNEL
);
939 /* need to get the full pkey table because the paravirtualized
940 * pkeys may be scattered among several pkey blocks.
942 err
= get_full_pkey_table(dev
, port
, table
, inbox
, outbox
);
944 for (vidx
= index
* 32; vidx
< (index
+ 1) * 32; ++vidx
) {
945 pidx
= priv
->virt2phys_pkey
[slave
][port
- 1][vidx
];
946 outtab
[vidx
% 32] = cpu_to_be16(table
[pidx
]);
952 if (smp
->attr_id
== IB_SMP_ATTR_PORT_INFO
) {
953 /*get the slave specific caps:*/
955 smp
->attr_mod
= cpu_to_be32(port
);
956 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
957 port
, opcode_modifier
,
958 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
959 /* modify the response for slaves */
960 if (!err
&& slave
!= mlx4_master_func_num(dev
)) {
961 u8
*state
= outsmp
->data
+ PORT_STATE_OFFSET
;
963 *state
= (*state
& 0xf0) | vf_port_state(dev
, port
, slave
);
964 slave_cap_mask
= priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
];
965 memcpy(outsmp
->data
+ PORT_CAPABILITY_LOCATION_IN_SMP
, &slave_cap_mask
, 4);
969 if (smp
->attr_id
== IB_SMP_ATTR_GUID_INFO
) {
970 __be64 guid
= mlx4_get_admin_guid(dev
, slave
,
973 /* set the PF admin guid to the FW/HW burned
974 * GUID, if it wasn't yet set
976 if (slave
== 0 && guid
== 0) {
978 err
= mlx4_cmd_box(dev
,
984 MLX4_CMD_TIME_CLASS_C
,
988 mlx4_set_admin_guid(dev
,
992 memcpy(outsmp
->data
, &guid
, 8);
995 /* clean all other gids */
996 memset(outsmp
->data
+ 8, 0, 56);
999 if (smp
->attr_id
== IB_SMP_ATTR_NODE_INFO
) {
1000 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
1001 port
, opcode_modifier
,
1002 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
1004 slave_node_guid
= mlx4_get_slave_node_guid(dev
, slave
);
1005 memcpy(outsmp
->data
+ 12, &slave_node_guid
, 8);
1012 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
1013 * These are the MADs used by ib verbs (such as ib_query_gids).
1015 if (slave
!= mlx4_master_func_num(dev
) &&
1016 !mlx4_vf_smi_enabled(dev
, slave
, port
)) {
1017 if (!(smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_LID_ROUTED
&&
1018 smp
->method
== IB_MGMT_METHOD_GET
) || network_view
) {
1019 mlx4_err(dev
, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
1020 slave
, smp
->mgmt_class
, smp
->method
,
1021 network_view
? "Network" : "Host",
1022 be16_to_cpu(smp
->attr_id
));
1027 return mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
1028 vhcr
->in_modifier
, opcode_modifier
,
1029 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
1032 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev
*dev
, int slave
,
1033 struct mlx4_vhcr
*vhcr
,
1034 struct mlx4_cmd_mailbox
*inbox
,
1035 struct mlx4_cmd_mailbox
*outbox
,
1036 struct mlx4_cmd_info
*cmd
)
1041 int mlx4_DMA_wrapper(struct mlx4_dev
*dev
, int slave
,
1042 struct mlx4_vhcr
*vhcr
,
1043 struct mlx4_cmd_mailbox
*inbox
,
1044 struct mlx4_cmd_mailbox
*outbox
,
1045 struct mlx4_cmd_info
*cmd
)
1051 in_param
= cmd
->has_inbox
? (u64
) inbox
->dma
: vhcr
->in_param
;
1052 out_param
= cmd
->has_outbox
? (u64
) outbox
->dma
: vhcr
->out_param
;
1053 if (cmd
->encode_slave_id
) {
1054 in_param
&= 0xffffffffffffff00ll
;
1058 err
= __mlx4_cmd(dev
, in_param
, &out_param
, cmd
->out_is_imm
,
1059 vhcr
->in_modifier
, vhcr
->op_modifier
, vhcr
->op
,
1060 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1062 if (cmd
->out_is_imm
)
1063 vhcr
->out_param
= out_param
;
1068 static struct mlx4_cmd_info cmd_info
[] = {
1070 .opcode
= MLX4_CMD_QUERY_FW
,
1073 .out_is_imm
= false,
1074 .encode_slave_id
= false,
1076 .wrapper
= mlx4_QUERY_FW_wrapper
1079 .opcode
= MLX4_CMD_QUERY_HCA
,
1082 .out_is_imm
= false,
1083 .encode_slave_id
= false,
1088 .opcode
= MLX4_CMD_QUERY_DEV_CAP
,
1091 .out_is_imm
= false,
1092 .encode_slave_id
= false,
1094 .wrapper
= mlx4_QUERY_DEV_CAP_wrapper
1097 .opcode
= MLX4_CMD_QUERY_FUNC_CAP
,
1100 .out_is_imm
= false,
1101 .encode_slave_id
= false,
1103 .wrapper
= mlx4_QUERY_FUNC_CAP_wrapper
1106 .opcode
= MLX4_CMD_QUERY_ADAPTER
,
1109 .out_is_imm
= false,
1110 .encode_slave_id
= false,
1115 .opcode
= MLX4_CMD_INIT_PORT
,
1117 .has_outbox
= false,
1118 .out_is_imm
= false,
1119 .encode_slave_id
= false,
1121 .wrapper
= mlx4_INIT_PORT_wrapper
1124 .opcode
= MLX4_CMD_CLOSE_PORT
,
1126 .has_outbox
= false,
1127 .out_is_imm
= false,
1128 .encode_slave_id
= false,
1130 .wrapper
= mlx4_CLOSE_PORT_wrapper
1133 .opcode
= MLX4_CMD_QUERY_PORT
,
1136 .out_is_imm
= false,
1137 .encode_slave_id
= false,
1139 .wrapper
= mlx4_QUERY_PORT_wrapper
1142 .opcode
= MLX4_CMD_SET_PORT
,
1144 .has_outbox
= false,
1145 .out_is_imm
= false,
1146 .encode_slave_id
= false,
1148 .wrapper
= mlx4_SET_PORT_wrapper
1151 .opcode
= MLX4_CMD_MAP_EQ
,
1153 .has_outbox
= false,
1154 .out_is_imm
= false,
1155 .encode_slave_id
= false,
1157 .wrapper
= mlx4_MAP_EQ_wrapper
1160 .opcode
= MLX4_CMD_SW2HW_EQ
,
1162 .has_outbox
= false,
1163 .out_is_imm
= false,
1164 .encode_slave_id
= true,
1166 .wrapper
= mlx4_SW2HW_EQ_wrapper
1169 .opcode
= MLX4_CMD_HW_HEALTH_CHECK
,
1171 .has_outbox
= false,
1172 .out_is_imm
= false,
1173 .encode_slave_id
= false,
1178 .opcode
= MLX4_CMD_NOP
,
1180 .has_outbox
= false,
1181 .out_is_imm
= false,
1182 .encode_slave_id
= false,
1187 .opcode
= MLX4_CMD_CONFIG_DEV
,
1190 .out_is_imm
= false,
1191 .encode_slave_id
= false,
1193 .wrapper
= mlx4_CONFIG_DEV_wrapper
1196 .opcode
= MLX4_CMD_ALLOC_RES
,
1198 .has_outbox
= false,
1200 .encode_slave_id
= false,
1202 .wrapper
= mlx4_ALLOC_RES_wrapper
1205 .opcode
= MLX4_CMD_FREE_RES
,
1207 .has_outbox
= false,
1208 .out_is_imm
= false,
1209 .encode_slave_id
= false,
1211 .wrapper
= mlx4_FREE_RES_wrapper
1214 .opcode
= MLX4_CMD_SW2HW_MPT
,
1216 .has_outbox
= false,
1217 .out_is_imm
= false,
1218 .encode_slave_id
= true,
1220 .wrapper
= mlx4_SW2HW_MPT_wrapper
1223 .opcode
= MLX4_CMD_QUERY_MPT
,
1226 .out_is_imm
= false,
1227 .encode_slave_id
= false,
1229 .wrapper
= mlx4_QUERY_MPT_wrapper
1232 .opcode
= MLX4_CMD_HW2SW_MPT
,
1234 .has_outbox
= false,
1235 .out_is_imm
= false,
1236 .encode_slave_id
= false,
1238 .wrapper
= mlx4_HW2SW_MPT_wrapper
1241 .opcode
= MLX4_CMD_READ_MTT
,
1244 .out_is_imm
= false,
1245 .encode_slave_id
= false,
1250 .opcode
= MLX4_CMD_WRITE_MTT
,
1252 .has_outbox
= false,
1253 .out_is_imm
= false,
1254 .encode_slave_id
= false,
1256 .wrapper
= mlx4_WRITE_MTT_wrapper
1259 .opcode
= MLX4_CMD_SYNC_TPT
,
1261 .has_outbox
= false,
1262 .out_is_imm
= false,
1263 .encode_slave_id
= false,
1268 .opcode
= MLX4_CMD_HW2SW_EQ
,
1270 .has_outbox
= false,
1271 .out_is_imm
= false,
1272 .encode_slave_id
= true,
1274 .wrapper
= mlx4_HW2SW_EQ_wrapper
1277 .opcode
= MLX4_CMD_QUERY_EQ
,
1280 .out_is_imm
= false,
1281 .encode_slave_id
= true,
1283 .wrapper
= mlx4_QUERY_EQ_wrapper
1286 .opcode
= MLX4_CMD_SW2HW_CQ
,
1288 .has_outbox
= false,
1289 .out_is_imm
= false,
1290 .encode_slave_id
= true,
1292 .wrapper
= mlx4_SW2HW_CQ_wrapper
1295 .opcode
= MLX4_CMD_HW2SW_CQ
,
1297 .has_outbox
= false,
1298 .out_is_imm
= false,
1299 .encode_slave_id
= false,
1301 .wrapper
= mlx4_HW2SW_CQ_wrapper
1304 .opcode
= MLX4_CMD_QUERY_CQ
,
1307 .out_is_imm
= false,
1308 .encode_slave_id
= false,
1310 .wrapper
= mlx4_QUERY_CQ_wrapper
1313 .opcode
= MLX4_CMD_MODIFY_CQ
,
1315 .has_outbox
= false,
1317 .encode_slave_id
= false,
1319 .wrapper
= mlx4_MODIFY_CQ_wrapper
1322 .opcode
= MLX4_CMD_SW2HW_SRQ
,
1324 .has_outbox
= false,
1325 .out_is_imm
= false,
1326 .encode_slave_id
= true,
1328 .wrapper
= mlx4_SW2HW_SRQ_wrapper
1331 .opcode
= MLX4_CMD_HW2SW_SRQ
,
1333 .has_outbox
= false,
1334 .out_is_imm
= false,
1335 .encode_slave_id
= false,
1337 .wrapper
= mlx4_HW2SW_SRQ_wrapper
1340 .opcode
= MLX4_CMD_QUERY_SRQ
,
1343 .out_is_imm
= false,
1344 .encode_slave_id
= false,
1346 .wrapper
= mlx4_QUERY_SRQ_wrapper
1349 .opcode
= MLX4_CMD_ARM_SRQ
,
1351 .has_outbox
= false,
1352 .out_is_imm
= false,
1353 .encode_slave_id
= false,
1355 .wrapper
= mlx4_ARM_SRQ_wrapper
1358 .opcode
= MLX4_CMD_RST2INIT_QP
,
1360 .has_outbox
= false,
1361 .out_is_imm
= false,
1362 .encode_slave_id
= true,
1364 .wrapper
= mlx4_RST2INIT_QP_wrapper
1367 .opcode
= MLX4_CMD_INIT2INIT_QP
,
1369 .has_outbox
= false,
1370 .out_is_imm
= false,
1371 .encode_slave_id
= false,
1373 .wrapper
= mlx4_INIT2INIT_QP_wrapper
1376 .opcode
= MLX4_CMD_INIT2RTR_QP
,
1378 .has_outbox
= false,
1379 .out_is_imm
= false,
1380 .encode_slave_id
= false,
1382 .wrapper
= mlx4_INIT2RTR_QP_wrapper
1385 .opcode
= MLX4_CMD_RTR2RTS_QP
,
1387 .has_outbox
= false,
1388 .out_is_imm
= false,
1389 .encode_slave_id
= false,
1391 .wrapper
= mlx4_RTR2RTS_QP_wrapper
1394 .opcode
= MLX4_CMD_RTS2RTS_QP
,
1396 .has_outbox
= false,
1397 .out_is_imm
= false,
1398 .encode_slave_id
= false,
1400 .wrapper
= mlx4_RTS2RTS_QP_wrapper
1403 .opcode
= MLX4_CMD_SQERR2RTS_QP
,
1405 .has_outbox
= false,
1406 .out_is_imm
= false,
1407 .encode_slave_id
= false,
1409 .wrapper
= mlx4_SQERR2RTS_QP_wrapper
1412 .opcode
= MLX4_CMD_2ERR_QP
,
1414 .has_outbox
= false,
1415 .out_is_imm
= false,
1416 .encode_slave_id
= false,
1418 .wrapper
= mlx4_GEN_QP_wrapper
1421 .opcode
= MLX4_CMD_RTS2SQD_QP
,
1423 .has_outbox
= false,
1424 .out_is_imm
= false,
1425 .encode_slave_id
= false,
1427 .wrapper
= mlx4_GEN_QP_wrapper
1430 .opcode
= MLX4_CMD_SQD2SQD_QP
,
1432 .has_outbox
= false,
1433 .out_is_imm
= false,
1434 .encode_slave_id
= false,
1436 .wrapper
= mlx4_SQD2SQD_QP_wrapper
1439 .opcode
= MLX4_CMD_SQD2RTS_QP
,
1441 .has_outbox
= false,
1442 .out_is_imm
= false,
1443 .encode_slave_id
= false,
1445 .wrapper
= mlx4_SQD2RTS_QP_wrapper
1448 .opcode
= MLX4_CMD_2RST_QP
,
1450 .has_outbox
= false,
1451 .out_is_imm
= false,
1452 .encode_slave_id
= false,
1454 .wrapper
= mlx4_2RST_QP_wrapper
1457 .opcode
= MLX4_CMD_QUERY_QP
,
1460 .out_is_imm
= false,
1461 .encode_slave_id
= false,
1463 .wrapper
= mlx4_GEN_QP_wrapper
1466 .opcode
= MLX4_CMD_SUSPEND_QP
,
1468 .has_outbox
= false,
1469 .out_is_imm
= false,
1470 .encode_slave_id
= false,
1472 .wrapper
= mlx4_GEN_QP_wrapper
1475 .opcode
= MLX4_CMD_UNSUSPEND_QP
,
1477 .has_outbox
= false,
1478 .out_is_imm
= false,
1479 .encode_slave_id
= false,
1481 .wrapper
= mlx4_GEN_QP_wrapper
1484 .opcode
= MLX4_CMD_UPDATE_QP
,
1486 .has_outbox
= false,
1487 .out_is_imm
= false,
1488 .encode_slave_id
= false,
1490 .wrapper
= mlx4_UPDATE_QP_wrapper
1493 .opcode
= MLX4_CMD_GET_OP_REQ
,
1495 .has_outbox
= false,
1496 .out_is_imm
= false,
1497 .encode_slave_id
= false,
1499 .wrapper
= mlx4_CMD_EPERM_wrapper
,
1502 .opcode
= MLX4_CMD_ALLOCATE_VPP
,
1505 .out_is_imm
= false,
1506 .encode_slave_id
= false,
1508 .wrapper
= mlx4_CMD_EPERM_wrapper
,
1511 .opcode
= MLX4_CMD_SET_VPORT_QOS
,
1514 .out_is_imm
= false,
1515 .encode_slave_id
= false,
1517 .wrapper
= mlx4_CMD_EPERM_wrapper
,
1520 .opcode
= MLX4_CMD_CONF_SPECIAL_QP
,
1522 .has_outbox
= false,
1523 .out_is_imm
= false,
1524 .encode_slave_id
= false,
1525 .verify
= NULL
, /* XXX verify: only demux can do this */
1529 .opcode
= MLX4_CMD_MAD_IFC
,
1532 .out_is_imm
= false,
1533 .encode_slave_id
= false,
1535 .wrapper
= mlx4_MAD_IFC_wrapper
1538 .opcode
= MLX4_CMD_MAD_DEMUX
,
1540 .has_outbox
= false,
1541 .out_is_imm
= false,
1542 .encode_slave_id
= false,
1544 .wrapper
= mlx4_CMD_EPERM_wrapper
1547 .opcode
= MLX4_CMD_QUERY_IF_STAT
,
1550 .out_is_imm
= false,
1551 .encode_slave_id
= false,
1553 .wrapper
= mlx4_QUERY_IF_STAT_wrapper
1556 .opcode
= MLX4_CMD_ACCESS_REG
,
1559 .out_is_imm
= false,
1560 .encode_slave_id
= false,
1562 .wrapper
= mlx4_ACCESS_REG_wrapper
,
1565 .opcode
= MLX4_CMD_CONGESTION_CTRL_OPCODE
,
1567 .has_outbox
= false,
1568 .out_is_imm
= false,
1569 .encode_slave_id
= false,
1571 .wrapper
= mlx4_CMD_EPERM_wrapper
,
1573 /* Native multicast commands are not available for guests */
1575 .opcode
= MLX4_CMD_QP_ATTACH
,
1577 .has_outbox
= false,
1578 .out_is_imm
= false,
1579 .encode_slave_id
= false,
1581 .wrapper
= mlx4_QP_ATTACH_wrapper
1584 .opcode
= MLX4_CMD_PROMISC
,
1586 .has_outbox
= false,
1587 .out_is_imm
= false,
1588 .encode_slave_id
= false,
1590 .wrapper
= mlx4_PROMISC_wrapper
1592 /* Ethernet specific commands */
1594 .opcode
= MLX4_CMD_SET_VLAN_FLTR
,
1596 .has_outbox
= false,
1597 .out_is_imm
= false,
1598 .encode_slave_id
= false,
1600 .wrapper
= mlx4_SET_VLAN_FLTR_wrapper
1603 .opcode
= MLX4_CMD_SET_MCAST_FLTR
,
1605 .has_outbox
= false,
1606 .out_is_imm
= false,
1607 .encode_slave_id
= false,
1609 .wrapper
= mlx4_SET_MCAST_FLTR_wrapper
1612 .opcode
= MLX4_CMD_DUMP_ETH_STATS
,
1615 .out_is_imm
= false,
1616 .encode_slave_id
= false,
1618 .wrapper
= mlx4_DUMP_ETH_STATS_wrapper
1621 .opcode
= MLX4_CMD_INFORM_FLR_DONE
,
1623 .has_outbox
= false,
1624 .out_is_imm
= false,
1625 .encode_slave_id
= false,
1629 /* flow steering commands */
1631 .opcode
= MLX4_QP_FLOW_STEERING_ATTACH
,
1633 .has_outbox
= false,
1635 .encode_slave_id
= false,
1637 .wrapper
= mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1640 .opcode
= MLX4_QP_FLOW_STEERING_DETACH
,
1642 .has_outbox
= false,
1643 .out_is_imm
= false,
1644 .encode_slave_id
= false,
1646 .wrapper
= mlx4_QP_FLOW_STEERING_DETACH_wrapper
1649 .opcode
= MLX4_FLOW_STEERING_IB_UC_QP_RANGE
,
1651 .has_outbox
= false,
1652 .out_is_imm
= false,
1653 .encode_slave_id
= false,
1655 .wrapper
= mlx4_CMD_EPERM_wrapper
1658 .opcode
= MLX4_CMD_VIRT_PORT_MAP
,
1660 .has_outbox
= false,
1661 .out_is_imm
= false,
1662 .encode_slave_id
= false,
1664 .wrapper
= mlx4_CMD_EPERM_wrapper
1668 static int mlx4_master_process_vhcr(struct mlx4_dev
*dev
, int slave
,
1669 struct mlx4_vhcr_cmd
*in_vhcr
)
1671 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1672 struct mlx4_cmd_info
*cmd
= NULL
;
1673 struct mlx4_vhcr_cmd
*vhcr_cmd
= in_vhcr
? in_vhcr
: priv
->mfunc
.vhcr
;
1674 struct mlx4_vhcr
*vhcr
;
1675 struct mlx4_cmd_mailbox
*inbox
= NULL
;
1676 struct mlx4_cmd_mailbox
*outbox
= NULL
;
1683 /* Create sw representation of Virtual HCR */
1684 vhcr
= kzalloc(sizeof(struct mlx4_vhcr
), GFP_KERNEL
);
1688 /* DMA in the vHCR */
1690 ret
= mlx4_ACCESS_MEM(dev
, priv
->mfunc
.vhcr_dma
, slave
,
1691 priv
->mfunc
.master
.slave_state
[slave
].vhcr_dma
,
1692 ALIGN(sizeof(struct mlx4_vhcr_cmd
),
1693 MLX4_ACCESS_MEM_ALIGN
), 1);
1695 if (!(dev
->persist
->state
&
1696 MLX4_DEVICE_STATE_INTERNAL_ERROR
))
1697 mlx4_err(dev
, "%s: Failed reading vhcr ret: 0x%x\n",
1704 /* Fill SW VHCR fields */
1705 vhcr
->in_param
= be64_to_cpu(vhcr_cmd
->in_param
);
1706 vhcr
->out_param
= be64_to_cpu(vhcr_cmd
->out_param
);
1707 vhcr
->in_modifier
= be32_to_cpu(vhcr_cmd
->in_modifier
);
1708 vhcr
->token
= be16_to_cpu(vhcr_cmd
->token
);
1709 vhcr
->op
= be16_to_cpu(vhcr_cmd
->opcode
) & 0xfff;
1710 vhcr
->op_modifier
= (u8
) (be16_to_cpu(vhcr_cmd
->opcode
) >> 12);
1711 vhcr
->e_bit
= vhcr_cmd
->flags
& (1 << 6);
1713 /* Lookup command */
1714 for (i
= 0; i
< ARRAY_SIZE(cmd_info
); ++i
) {
1715 if (vhcr
->op
== cmd_info
[i
].opcode
) {
1721 mlx4_err(dev
, "Unknown command:0x%x accepted from slave:%d\n",
1723 vhcr_cmd
->status
= CMD_STAT_BAD_PARAM
;
1728 if (cmd
->has_inbox
) {
1729 vhcr
->in_param
&= INBOX_MASK
;
1730 inbox
= mlx4_alloc_cmd_mailbox(dev
);
1731 if (IS_ERR(inbox
)) {
1732 vhcr_cmd
->status
= CMD_STAT_BAD_SIZE
;
1737 ret
= mlx4_ACCESS_MEM(dev
, inbox
->dma
, slave
,
1739 MLX4_MAILBOX_SIZE
, 1);
1741 if (!(dev
->persist
->state
&
1742 MLX4_DEVICE_STATE_INTERNAL_ERROR
))
1743 mlx4_err(dev
, "%s: Failed reading inbox (cmd:0x%x)\n",
1744 __func__
, cmd
->opcode
);
1745 vhcr_cmd
->status
= CMD_STAT_INTERNAL_ERR
;
1750 /* Apply permission and bound checks if applicable */
1751 if (cmd
->verify
&& cmd
->verify(dev
, slave
, vhcr
, inbox
)) {
1752 mlx4_warn(dev
, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1753 vhcr
->op
, slave
, vhcr
->in_modifier
);
1754 vhcr_cmd
->status
= CMD_STAT_BAD_OP
;
1758 /* Allocate outbox */
1759 if (cmd
->has_outbox
) {
1760 outbox
= mlx4_alloc_cmd_mailbox(dev
);
1761 if (IS_ERR(outbox
)) {
1762 vhcr_cmd
->status
= CMD_STAT_BAD_SIZE
;
1768 /* Execute the command! */
1770 err
= cmd
->wrapper(dev
, slave
, vhcr
, inbox
, outbox
,
1772 if (cmd
->out_is_imm
)
1773 vhcr_cmd
->out_param
= cpu_to_be64(vhcr
->out_param
);
1775 in_param
= cmd
->has_inbox
? (u64
) inbox
->dma
:
1777 out_param
= cmd
->has_outbox
? (u64
) outbox
->dma
:
1779 err
= __mlx4_cmd(dev
, in_param
, &out_param
,
1780 cmd
->out_is_imm
, vhcr
->in_modifier
,
1781 vhcr
->op_modifier
, vhcr
->op
,
1782 MLX4_CMD_TIME_CLASS_A
,
1785 if (cmd
->out_is_imm
) {
1786 vhcr
->out_param
= out_param
;
1787 vhcr_cmd
->out_param
= cpu_to_be64(vhcr
->out_param
);
1792 if (!(dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)) {
1793 if (vhcr
->op
== MLX4_CMD_ALLOC_RES
&&
1794 (vhcr
->in_modifier
& 0xff) == RES_COUNTER
&&
1797 "Unable to allocate counter for slave %d (%d)\n",
1800 mlx4_warn(dev
, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1801 vhcr
->op
, slave
, vhcr
->errno
, err
);
1803 vhcr_cmd
->status
= mlx4_errno_to_status(err
);
1808 /* Write outbox if command completed successfully */
1809 if (cmd
->has_outbox
&& !vhcr_cmd
->status
) {
1810 ret
= mlx4_ACCESS_MEM(dev
, outbox
->dma
, slave
,
1812 MLX4_MAILBOX_SIZE
, MLX4_CMD_WRAPPED
);
1814 /* If we failed to write back the outbox after the
1815 *command was successfully executed, we must fail this
1816 * slave, as it is now in undefined state */
1817 if (!(dev
->persist
->state
&
1818 MLX4_DEVICE_STATE_INTERNAL_ERROR
))
1819 mlx4_err(dev
, "%s:Failed writing outbox\n", __func__
);
1825 /* DMA back vhcr result */
1827 ret
= mlx4_ACCESS_MEM(dev
, priv
->mfunc
.vhcr_dma
, slave
,
1828 priv
->mfunc
.master
.slave_state
[slave
].vhcr_dma
,
1829 ALIGN(sizeof(struct mlx4_vhcr
),
1830 MLX4_ACCESS_MEM_ALIGN
),
1833 mlx4_err(dev
, "%s:Failed writing vhcr result\n",
1835 else if (vhcr
->e_bit
&&
1836 mlx4_GEN_EQE(dev
, slave
, &priv
->mfunc
.master
.cmd_eqe
))
1837 mlx4_warn(dev
, "Failed to generate command completion eqe for slave %d\n",
1843 mlx4_free_cmd_mailbox(dev
, inbox
);
1844 mlx4_free_cmd_mailbox(dev
, outbox
);
1848 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv
*priv
,
1849 int slave
, int port
)
1851 struct mlx4_vport_oper_state
*vp_oper
;
1852 struct mlx4_vport_state
*vp_admin
;
1853 struct mlx4_vf_immed_vlan_work
*work
;
1854 struct mlx4_dev
*dev
= &(priv
->dev
);
1856 int admin_vlan_ix
= NO_INDX
;
1858 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
1859 vp_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
1861 if (vp_oper
->state
.default_vlan
== vp_admin
->default_vlan
&&
1862 vp_oper
->state
.default_qos
== vp_admin
->default_qos
&&
1863 vp_oper
->state
.vlan_proto
== vp_admin
->vlan_proto
&&
1864 vp_oper
->state
.link_state
== vp_admin
->link_state
&&
1865 vp_oper
->state
.qos_vport
== vp_admin
->qos_vport
)
1868 if (!(priv
->mfunc
.master
.slave_state
[slave
].active
&&
1869 dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_UPDATE_QP
)) {
1870 /* even if the UPDATE_QP command isn't supported, we still want
1871 * to set this VF link according to the admin directive
1873 vp_oper
->state
.link_state
= vp_admin
->link_state
;
1877 mlx4_dbg(dev
, "updating immediately admin params slave %d port %d\n",
1879 mlx4_dbg(dev
, "vlan %d QoS %d link down %d\n",
1880 vp_admin
->default_vlan
, vp_admin
->default_qos
,
1881 vp_admin
->link_state
);
1883 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
1887 if (vp_oper
->state
.default_vlan
!= vp_admin
->default_vlan
) {
1888 if (MLX4_VGT
!= vp_admin
->default_vlan
) {
1889 err
= __mlx4_register_vlan(&priv
->dev
, port
,
1890 vp_admin
->default_vlan
,
1894 mlx4_warn(&priv
->dev
,
1895 "No vlan resources slave %d, port %d\n",
1900 admin_vlan_ix
= NO_INDX
;
1902 work
->flags
|= MLX4_VF_IMMED_VLAN_FLAG_VLAN
;
1903 mlx4_dbg(&priv
->dev
,
1904 "alloc vlan %d idx %d slave %d port %d\n",
1905 (int)(vp_admin
->default_vlan
),
1906 admin_vlan_ix
, slave
, port
);
1909 /* save original vlan ix and vlan id */
1910 work
->orig_vlan_id
= vp_oper
->state
.default_vlan
;
1911 work
->orig_vlan_ix
= vp_oper
->vlan_idx
;
1913 /* handle new qos */
1914 if (vp_oper
->state
.default_qos
!= vp_admin
->default_qos
)
1915 work
->flags
|= MLX4_VF_IMMED_VLAN_FLAG_QOS
;
1917 if (work
->flags
& MLX4_VF_IMMED_VLAN_FLAG_VLAN
)
1918 vp_oper
->vlan_idx
= admin_vlan_ix
;
1920 vp_oper
->state
.default_vlan
= vp_admin
->default_vlan
;
1921 vp_oper
->state
.default_qos
= vp_admin
->default_qos
;
1922 vp_oper
->state
.vlan_proto
= vp_admin
->vlan_proto
;
1923 vp_oper
->state
.link_state
= vp_admin
->link_state
;
1924 vp_oper
->state
.qos_vport
= vp_admin
->qos_vport
;
1926 if (vp_admin
->link_state
== IFLA_VF_LINK_STATE_DISABLE
)
1927 work
->flags
|= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE
;
1929 /* iterate over QPs owned by this slave, using UPDATE_QP */
1931 work
->slave
= slave
;
1932 work
->qos
= vp_oper
->state
.default_qos
;
1933 work
->qos_vport
= vp_oper
->state
.qos_vport
;
1934 work
->vlan_id
= vp_oper
->state
.default_vlan
;
1935 work
->vlan_ix
= vp_oper
->vlan_idx
;
1936 work
->vlan_proto
= vp_oper
->state
.vlan_proto
;
1938 INIT_WORK(&work
->work
, mlx4_vf_immed_vlan_work_handler
);
1939 queue_work(priv
->mfunc
.master
.comm_wq
, &work
->work
);
1944 static void mlx4_set_default_port_qos(struct mlx4_dev
*dev
, int port
)
1946 struct mlx4_qos_manager
*port_qos_ctl
;
1947 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1949 port_qos_ctl
= &priv
->mfunc
.master
.qos_ctl
[port
];
1950 bitmap_zero(port_qos_ctl
->priority_bm
, MLX4_NUM_UP
);
1952 /* Enable only default prio at PF init routine */
1953 set_bit(MLX4_DEFAULT_QOS_PRIO
, port_qos_ctl
->priority_bm
);
1956 static void mlx4_allocate_port_vpps(struct mlx4_dev
*dev
, int port
)
1962 u8 vpp_param
[MLX4_NUM_UP
];
1963 struct mlx4_qos_manager
*port_qos
;
1964 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1966 err
= mlx4_ALLOCATE_VPP_get(dev
, port
, &availible_vpp
, vpp_param
);
1968 mlx4_info(dev
, "Failed query availible VPPs\n");
1972 port_qos
= &priv
->mfunc
.master
.qos_ctl
[port
];
1973 num_vfs
= (availible_vpp
/
1974 bitmap_weight(port_qos
->priority_bm
, MLX4_NUM_UP
));
1976 for (i
= 0; i
< MLX4_NUM_UP
; i
++) {
1977 if (test_bit(i
, port_qos
->priority_bm
))
1978 vpp_param
[i
] = num_vfs
;
1981 err
= mlx4_ALLOCATE_VPP_set(dev
, port
, vpp_param
);
1983 mlx4_info(dev
, "Failed allocating VPPs\n");
1987 /* Query actual allocated VPP, just to make sure */
1988 err
= mlx4_ALLOCATE_VPP_get(dev
, port
, &availible_vpp
, vpp_param
);
1990 mlx4_info(dev
, "Failed query availible VPPs\n");
1994 port_qos
->num_of_qos_vfs
= num_vfs
;
1995 mlx4_dbg(dev
, "Port %d Availible VPPs %d\n", port
, availible_vpp
);
1997 for (i
= 0; i
< MLX4_NUM_UP
; i
++)
1998 mlx4_dbg(dev
, "Port %d UP %d Allocated %d VPPs\n", port
, i
,
2002 static int mlx4_master_activate_admin_state(struct mlx4_priv
*priv
, int slave
)
2005 struct mlx4_vport_state
*vp_admin
;
2006 struct mlx4_vport_oper_state
*vp_oper
;
2007 struct mlx4_slave_state
*slave_state
=
2008 &priv
->mfunc
.master
.slave_state
[slave
];
2009 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(
2011 int min_port
= find_first_bit(actv_ports
.ports
,
2012 priv
->dev
.caps
.num_ports
) + 1;
2013 int max_port
= min_port
- 1 +
2014 bitmap_weight(actv_ports
.ports
, priv
->dev
.caps
.num_ports
);
2016 for (port
= min_port
; port
<= max_port
; port
++) {
2017 if (!test_bit(port
- 1, actv_ports
.ports
))
2019 priv
->mfunc
.master
.vf_oper
[slave
].smi_enabled
[port
] =
2020 priv
->mfunc
.master
.vf_admin
[slave
].enable_smi
[port
];
2021 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
2022 vp_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2023 if (vp_admin
->vlan_proto
!= htons(ETH_P_8021AD
) ||
2024 slave_state
->vst_qinq_supported
) {
2025 vp_oper
->state
.vlan_proto
= vp_admin
->vlan_proto
;
2026 vp_oper
->state
.default_vlan
= vp_admin
->default_vlan
;
2027 vp_oper
->state
.default_qos
= vp_admin
->default_qos
;
2029 vp_oper
->state
.link_state
= vp_admin
->link_state
;
2030 vp_oper
->state
.mac
= vp_admin
->mac
;
2031 vp_oper
->state
.spoofchk
= vp_admin
->spoofchk
;
2032 vp_oper
->state
.tx_rate
= vp_admin
->tx_rate
;
2033 vp_oper
->state
.qos_vport
= vp_admin
->qos_vport
;
2034 vp_oper
->state
.guid
= vp_admin
->guid
;
2036 if (MLX4_VGT
!= vp_admin
->default_vlan
) {
2037 err
= __mlx4_register_vlan(&priv
->dev
, port
,
2038 vp_admin
->default_vlan
, &(vp_oper
->vlan_idx
));
2040 vp_oper
->vlan_idx
= NO_INDX
;
2041 vp_oper
->state
.default_vlan
= MLX4_VGT
;
2042 vp_oper
->state
.vlan_proto
= htons(ETH_P_8021Q
);
2043 mlx4_warn(&priv
->dev
,
2044 "No vlan resources slave %d, port %d\n",
2048 mlx4_dbg(&priv
->dev
, "alloc vlan %d idx %d slave %d port %d\n",
2049 (int)(vp_oper
->state
.default_vlan
),
2050 vp_oper
->vlan_idx
, slave
, port
);
2052 if (vp_admin
->spoofchk
) {
2053 vp_oper
->mac_idx
= __mlx4_register_mac(&priv
->dev
,
2056 if (0 > vp_oper
->mac_idx
) {
2057 err
= vp_oper
->mac_idx
;
2058 vp_oper
->mac_idx
= NO_INDX
;
2059 mlx4_warn(&priv
->dev
,
2060 "No mac resources slave %d, port %d\n",
2064 mlx4_dbg(&priv
->dev
, "alloc mac %llx idx %d slave %d port %d\n",
2065 vp_oper
->state
.mac
, vp_oper
->mac_idx
, slave
, port
);
2071 static void mlx4_master_deactivate_admin_state(struct mlx4_priv
*priv
, int slave
)
2074 struct mlx4_vport_oper_state
*vp_oper
;
2075 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(
2077 int min_port
= find_first_bit(actv_ports
.ports
,
2078 priv
->dev
.caps
.num_ports
) + 1;
2079 int max_port
= min_port
- 1 +
2080 bitmap_weight(actv_ports
.ports
, priv
->dev
.caps
.num_ports
);
2083 for (port
= min_port
; port
<= max_port
; port
++) {
2084 if (!test_bit(port
- 1, actv_ports
.ports
))
2086 priv
->mfunc
.master
.vf_oper
[slave
].smi_enabled
[port
] =
2087 MLX4_VF_SMI_DISABLED
;
2088 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
2089 if (NO_INDX
!= vp_oper
->vlan_idx
) {
2090 __mlx4_unregister_vlan(&priv
->dev
,
2091 port
, vp_oper
->state
.default_vlan
);
2092 vp_oper
->vlan_idx
= NO_INDX
;
2094 if (NO_INDX
!= vp_oper
->mac_idx
) {
2095 __mlx4_unregister_mac(&priv
->dev
, port
, vp_oper
->state
.mac
);
2096 vp_oper
->mac_idx
= NO_INDX
;
2102 static void mlx4_master_do_cmd(struct mlx4_dev
*dev
, int slave
, u8 cmd
,
2103 u16 param
, u8 toggle
)
2105 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2106 struct mlx4_slave_state
*slave_state
= priv
->mfunc
.master
.slave_state
;
2108 u8 is_going_down
= 0;
2110 unsigned long flags
;
2112 slave_state
[slave
].comm_toggle
^= 1;
2113 reply
= (u32
) slave_state
[slave
].comm_toggle
<< 31;
2114 if (toggle
!= slave_state
[slave
].comm_toggle
) {
2115 mlx4_warn(dev
, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2119 if (cmd
== MLX4_COMM_CMD_RESET
) {
2120 mlx4_warn(dev
, "Received reset from slave:%d\n", slave
);
2121 slave_state
[slave
].active
= false;
2122 slave_state
[slave
].old_vlan_api
= false;
2123 slave_state
[slave
].vst_qinq_supported
= false;
2124 mlx4_master_deactivate_admin_state(priv
, slave
);
2125 for (i
= 0; i
< MLX4_EVENT_TYPES_NUM
; ++i
) {
2126 slave_state
[slave
].event_eq
[i
].eqn
= -1;
2127 slave_state
[slave
].event_eq
[i
].token
= 0;
2129 /*check if we are in the middle of FLR process,
2130 if so return "retry" status to the slave*/
2131 if (MLX4_COMM_CMD_FLR
== slave_state
[slave
].last_cmd
)
2132 goto inform_slave_state
;
2134 mlx4_dispatch_event(dev
, MLX4_DEV_EVENT_SLAVE_SHUTDOWN
, slave
);
2136 /* write the version in the event field */
2137 reply
|= mlx4_comm_get_version();
2141 /*command from slave in the middle of FLR*/
2142 if (cmd
!= MLX4_COMM_CMD_RESET
&&
2143 MLX4_COMM_CMD_FLR
== slave_state
[slave
].last_cmd
) {
2144 mlx4_warn(dev
, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2150 case MLX4_COMM_CMD_VHCR0
:
2151 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_RESET
)
2153 slave_state
[slave
].vhcr_dma
= ((u64
) param
) << 48;
2154 priv
->mfunc
.master
.slave_state
[slave
].cookie
= 0;
2156 case MLX4_COMM_CMD_VHCR1
:
2157 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR0
)
2159 slave_state
[slave
].vhcr_dma
|= ((u64
) param
) << 32;
2161 case MLX4_COMM_CMD_VHCR2
:
2162 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR1
)
2164 slave_state
[slave
].vhcr_dma
|= ((u64
) param
) << 16;
2166 case MLX4_COMM_CMD_VHCR_EN
:
2167 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR2
)
2169 slave_state
[slave
].vhcr_dma
|= param
;
2170 if (mlx4_master_activate_admin_state(priv
, slave
))
2172 slave_state
[slave
].active
= true;
2173 mlx4_dispatch_event(dev
, MLX4_DEV_EVENT_SLAVE_INIT
, slave
);
2175 case MLX4_COMM_CMD_VHCR_POST
:
2176 if ((slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR_EN
) &&
2177 (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR_POST
)) {
2178 mlx4_warn(dev
, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2179 slave
, cmd
, slave_state
[slave
].last_cmd
);
2183 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
2184 if (mlx4_master_process_vhcr(dev
, slave
, NULL
)) {
2185 mlx4_err(dev
, "Failed processing vhcr for slave:%d, resetting slave\n",
2187 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
2190 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
2193 mlx4_warn(dev
, "Bad comm cmd:%d from slave:%d\n", cmd
, slave
);
2196 spin_lock_irqsave(&priv
->mfunc
.master
.slave_state_lock
, flags
);
2197 if (!slave_state
[slave
].is_slave_going_down
)
2198 slave_state
[slave
].last_cmd
= cmd
;
2201 spin_unlock_irqrestore(&priv
->mfunc
.master
.slave_state_lock
, flags
);
2202 if (is_going_down
) {
2203 mlx4_warn(dev
, "Slave is going down aborting command(%d) executing from slave:%d\n",
2207 __raw_writel((__force u32
) cpu_to_be32(reply
),
2208 &priv
->mfunc
.comm
[slave
].slave_read
);
2214 /* cleanup any slave resources */
2215 if (dev
->persist
->interface_state
& MLX4_INTERFACE_STATE_UP
)
2216 mlx4_delete_all_resources_for_slave(dev
, slave
);
2218 if (cmd
!= MLX4_COMM_CMD_RESET
) {
2219 mlx4_warn(dev
, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2221 /* Turn on internal error letting slave reset itself immeditaly,
2222 * otherwise it might take till timeout on command is passed
2224 reply
|= ((u32
)COMM_CHAN_EVENT_INTERNAL_ERR
);
2227 spin_lock_irqsave(&priv
->mfunc
.master
.slave_state_lock
, flags
);
2228 if (!slave_state
[slave
].is_slave_going_down
)
2229 slave_state
[slave
].last_cmd
= MLX4_COMM_CMD_RESET
;
2230 spin_unlock_irqrestore(&priv
->mfunc
.master
.slave_state_lock
, flags
);
2231 /*with slave in the middle of flr, no need to clean resources again.*/
2233 memset(&slave_state
[slave
].event_eq
, 0,
2234 sizeof(struct mlx4_slave_event_eq_info
));
2235 __raw_writel((__force u32
) cpu_to_be32(reply
),
2236 &priv
->mfunc
.comm
[slave
].slave_read
);
2240 /* master command processing */
2241 void mlx4_master_comm_channel(struct work_struct
*work
)
2243 struct mlx4_mfunc_master_ctx
*master
=
2245 struct mlx4_mfunc_master_ctx
,
2247 struct mlx4_mfunc
*mfunc
=
2248 container_of(master
, struct mlx4_mfunc
, master
);
2249 struct mlx4_priv
*priv
=
2250 container_of(mfunc
, struct mlx4_priv
, mfunc
);
2251 struct mlx4_dev
*dev
= &priv
->dev
;
2261 bit_vec
= master
->comm_arm_bit_vector
;
2262 for (i
= 0; i
< COMM_CHANNEL_BIT_ARRAY_SIZE
; i
++) {
2263 vec
= be32_to_cpu(bit_vec
[i
]);
2264 for (j
= 0; j
< 32; j
++) {
2265 if (!(vec
& (1 << j
)))
2268 slave
= (i
* 32) + j
;
2269 comm_cmd
= swab32(readl(
2270 &mfunc
->comm
[slave
].slave_write
));
2271 slt
= swab32(readl(&mfunc
->comm
[slave
].slave_read
))
2273 toggle
= comm_cmd
>> 31;
2274 if (toggle
!= slt
) {
2275 if (master
->slave_state
[slave
].comm_toggle
2277 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2279 master
->slave_state
[slave
].comm_toggle
);
2280 master
->slave_state
[slave
].comm_toggle
=
2283 mlx4_master_do_cmd(dev
, slave
,
2284 comm_cmd
>> 16 & 0xff,
2285 comm_cmd
& 0xffff, toggle
);
2291 if (reported
&& reported
!= served
)
2292 mlx4_warn(dev
, "Got command event with bitmask from %d slaves but %d were served\n",
2295 if (mlx4_ARM_COMM_CHANNEL(dev
))
2296 mlx4_warn(dev
, "Failed to arm comm channel events\n");
2299 static int sync_toggles(struct mlx4_dev
*dev
)
2301 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2306 wr_toggle
= swab32(readl(&priv
->mfunc
.comm
->slave_write
));
2307 if (wr_toggle
== 0xffffffff)
2308 end
= jiffies
+ msecs_to_jiffies(30000);
2310 end
= jiffies
+ msecs_to_jiffies(5000);
2312 while (time_before(jiffies
, end
)) {
2313 rd_toggle
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
2314 if (wr_toggle
== 0xffffffff || rd_toggle
== 0xffffffff) {
2315 /* PCI might be offline */
2317 /* If device removal has been requested,
2318 * do not continue retrying.
2320 if (dev
->persist
->interface_state
&
2321 MLX4_INTERFACE_STATE_NOWAIT
) {
2323 "communication channel is offline\n");
2328 wr_toggle
= swab32(readl(&priv
->mfunc
.comm
->
2333 if (rd_toggle
>> 31 == wr_toggle
>> 31) {
2334 priv
->cmd
.comm_toggle
= rd_toggle
>> 31;
2342 * we could reach here if for example the previous VM using this
2343 * function misbehaved and left the channel with unsynced state. We
2344 * should fix this here and give this VM a chance to use a properly
2347 mlx4_warn(dev
, "recovering from previously mis-behaved VM\n");
2348 __raw_writel((__force u32
) 0, &priv
->mfunc
.comm
->slave_read
);
2349 __raw_writel((__force u32
) 0, &priv
->mfunc
.comm
->slave_write
);
2350 priv
->cmd
.comm_toggle
= 0;
2355 int mlx4_multi_func_init(struct mlx4_dev
*dev
)
2357 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2358 struct mlx4_slave_state
*s_state
;
2359 int i
, j
, err
, port
;
2361 if (mlx4_is_master(dev
))
2363 ioremap(pci_resource_start(dev
->persist
->pdev
,
2364 priv
->fw
.comm_bar
) +
2365 priv
->fw
.comm_base
, MLX4_COMM_PAGESIZE
);
2368 ioremap(pci_resource_start(dev
->persist
->pdev
, 2) +
2369 MLX4_SLAVE_COMM_BASE
, MLX4_COMM_PAGESIZE
);
2370 if (!priv
->mfunc
.comm
) {
2371 mlx4_err(dev
, "Couldn't map communication vector\n");
2375 if (mlx4_is_master(dev
)) {
2376 struct mlx4_vf_oper_state
*vf_oper
;
2377 struct mlx4_vf_admin_state
*vf_admin
;
2379 priv
->mfunc
.master
.slave_state
=
2380 kzalloc(dev
->num_slaves
*
2381 sizeof(struct mlx4_slave_state
), GFP_KERNEL
);
2382 if (!priv
->mfunc
.master
.slave_state
)
2385 priv
->mfunc
.master
.vf_admin
=
2386 kzalloc(dev
->num_slaves
*
2387 sizeof(struct mlx4_vf_admin_state
), GFP_KERNEL
);
2388 if (!priv
->mfunc
.master
.vf_admin
)
2389 goto err_comm_admin
;
2391 priv
->mfunc
.master
.vf_oper
=
2392 kzalloc(dev
->num_slaves
*
2393 sizeof(struct mlx4_vf_oper_state
), GFP_KERNEL
);
2394 if (!priv
->mfunc
.master
.vf_oper
)
2397 for (i
= 0; i
< dev
->num_slaves
; ++i
) {
2398 vf_admin
= &priv
->mfunc
.master
.vf_admin
[i
];
2399 vf_oper
= &priv
->mfunc
.master
.vf_oper
[i
];
2400 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
2401 s_state
->last_cmd
= MLX4_COMM_CMD_RESET
;
2402 s_state
->vst_qinq_supported
= false;
2403 mutex_init(&priv
->mfunc
.master
.gen_eqe_mutex
[i
]);
2404 for (j
= 0; j
< MLX4_EVENT_TYPES_NUM
; ++j
)
2405 s_state
->event_eq
[j
].eqn
= -1;
2406 __raw_writel((__force u32
) 0,
2407 &priv
->mfunc
.comm
[i
].slave_write
);
2408 __raw_writel((__force u32
) 0,
2409 &priv
->mfunc
.comm
[i
].slave_read
);
2411 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++) {
2412 struct mlx4_vport_state
*admin_vport
;
2413 struct mlx4_vport_state
*oper_vport
;
2415 s_state
->vlan_filter
[port
] =
2416 kzalloc(sizeof(struct mlx4_vlan_fltr
),
2418 if (!s_state
->vlan_filter
[port
]) {
2420 kfree(s_state
->vlan_filter
[port
]);
2424 admin_vport
= &vf_admin
->vport
[port
];
2425 oper_vport
= &vf_oper
->vport
[port
].state
;
2426 INIT_LIST_HEAD(&s_state
->mcast_filters
[port
]);
2427 admin_vport
->default_vlan
= MLX4_VGT
;
2428 oper_vport
->default_vlan
= MLX4_VGT
;
2429 admin_vport
->qos_vport
=
2430 MLX4_VPP_DEFAULT_VPORT
;
2431 oper_vport
->qos_vport
= MLX4_VPP_DEFAULT_VPORT
;
2432 admin_vport
->vlan_proto
= htons(ETH_P_8021Q
);
2433 oper_vport
->vlan_proto
= htons(ETH_P_8021Q
);
2434 vf_oper
->vport
[port
].vlan_idx
= NO_INDX
;
2435 vf_oper
->vport
[port
].mac_idx
= NO_INDX
;
2436 mlx4_set_random_admin_guid(dev
, i
, port
);
2438 spin_lock_init(&s_state
->lock
);
2441 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_QOS_VPP
) {
2442 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2443 if (mlx4_is_eth(dev
, port
)) {
2444 mlx4_set_default_port_qos(dev
, port
);
2445 mlx4_allocate_port_vpps(dev
, port
);
2450 memset(&priv
->mfunc
.master
.cmd_eqe
, 0, sizeof(struct mlx4_eqe
));
2451 priv
->mfunc
.master
.cmd_eqe
.type
= MLX4_EVENT_TYPE_CMD
;
2452 INIT_WORK(&priv
->mfunc
.master
.comm_work
,
2453 mlx4_master_comm_channel
);
2454 INIT_WORK(&priv
->mfunc
.master
.slave_event_work
,
2455 mlx4_gen_slave_eqe
);
2456 INIT_WORK(&priv
->mfunc
.master
.slave_flr_event_work
,
2457 mlx4_master_handle_slave_flr
);
2458 spin_lock_init(&priv
->mfunc
.master
.slave_state_lock
);
2459 spin_lock_init(&priv
->mfunc
.master
.slave_eq
.event_lock
);
2460 priv
->mfunc
.master
.comm_wq
=
2461 create_singlethread_workqueue("mlx4_comm");
2462 if (!priv
->mfunc
.master
.comm_wq
)
2465 if (mlx4_init_resource_tracker(dev
))
2469 err
= sync_toggles(dev
);
2471 mlx4_err(dev
, "Couldn't sync toggles\n");
2478 flush_workqueue(priv
->mfunc
.master
.comm_wq
);
2479 destroy_workqueue(priv
->mfunc
.master
.comm_wq
);
2482 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++)
2483 kfree(priv
->mfunc
.master
.slave_state
[i
].vlan_filter
[port
]);
2485 kfree(priv
->mfunc
.master
.vf_oper
);
2487 kfree(priv
->mfunc
.master
.vf_admin
);
2489 kfree(priv
->mfunc
.master
.slave_state
);
2491 iounmap(priv
->mfunc
.comm
);
2492 priv
->mfunc
.comm
= NULL
;
2494 dma_free_coherent(&dev
->persist
->pdev
->dev
, PAGE_SIZE
,
2496 priv
->mfunc
.vhcr_dma
);
2497 priv
->mfunc
.vhcr
= NULL
;
2501 int mlx4_cmd_init(struct mlx4_dev
*dev
)
2503 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2506 if (!priv
->cmd
.initialized
) {
2507 init_rwsem(&priv
->cmd
.switch_sem
);
2508 mutex_init(&priv
->cmd
.slave_cmd_mutex
);
2509 sema_init(&priv
->cmd
.poll_sem
, 1);
2510 priv
->cmd
.use_events
= 0;
2511 priv
->cmd
.toggle
= 1;
2512 priv
->cmd
.initialized
= 1;
2513 flags
|= MLX4_CMD_CLEANUP_STRUCT
;
2516 if (!mlx4_is_slave(dev
) && !priv
->cmd
.hcr
) {
2517 priv
->cmd
.hcr
= ioremap(pci_resource_start(dev
->persist
->pdev
,
2518 0) + MLX4_HCR_BASE
, MLX4_HCR_SIZE
);
2519 if (!priv
->cmd
.hcr
) {
2520 mlx4_err(dev
, "Couldn't map command register\n");
2523 flags
|= MLX4_CMD_CLEANUP_HCR
;
2526 if (mlx4_is_mfunc(dev
) && !priv
->mfunc
.vhcr
) {
2527 priv
->mfunc
.vhcr
= dma_alloc_coherent(&dev
->persist
->pdev
->dev
,
2529 &priv
->mfunc
.vhcr_dma
,
2531 if (!priv
->mfunc
.vhcr
)
2534 flags
|= MLX4_CMD_CLEANUP_VHCR
;
2537 if (!priv
->cmd
.pool
) {
2538 priv
->cmd
.pool
= pci_pool_create("mlx4_cmd",
2541 MLX4_MAILBOX_SIZE
, 0);
2542 if (!priv
->cmd
.pool
)
2545 flags
|= MLX4_CMD_CLEANUP_POOL
;
2551 mlx4_cmd_cleanup(dev
, flags
);
2555 void mlx4_report_internal_err_comm_event(struct mlx4_dev
*dev
)
2557 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2561 /* If the comm channel has not yet been initialized,
2562 * skip reporting the internal error event to all
2563 * the communication channels.
2565 if (!priv
->mfunc
.comm
)
2568 /* Report an internal error event to all
2569 * communication channels.
2571 for (slave
= 0; slave
< dev
->num_slaves
; slave
++) {
2572 slave_read
= swab32(readl(&priv
->mfunc
.comm
[slave
].slave_read
));
2573 slave_read
|= (u32
)COMM_CHAN_EVENT_INTERNAL_ERR
;
2574 __raw_writel((__force u32
)cpu_to_be32(slave_read
),
2575 &priv
->mfunc
.comm
[slave
].slave_read
);
2576 /* Make sure that our comm channel write doesn't
2577 * get mixed in with writes from another CPU.
2583 void mlx4_multi_func_cleanup(struct mlx4_dev
*dev
)
2585 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2588 if (mlx4_is_master(dev
)) {
2589 flush_workqueue(priv
->mfunc
.master
.comm_wq
);
2590 destroy_workqueue(priv
->mfunc
.master
.comm_wq
);
2591 for (i
= 0; i
< dev
->num_slaves
; i
++) {
2592 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++)
2593 kfree(priv
->mfunc
.master
.slave_state
[i
].vlan_filter
[port
]);
2595 kfree(priv
->mfunc
.master
.slave_state
);
2596 kfree(priv
->mfunc
.master
.vf_admin
);
2597 kfree(priv
->mfunc
.master
.vf_oper
);
2598 dev
->num_slaves
= 0;
2601 iounmap(priv
->mfunc
.comm
);
2602 priv
->mfunc
.comm
= NULL
;
2605 void mlx4_cmd_cleanup(struct mlx4_dev
*dev
, int cleanup_mask
)
2607 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2609 if (priv
->cmd
.pool
&& (cleanup_mask
& MLX4_CMD_CLEANUP_POOL
)) {
2610 pci_pool_destroy(priv
->cmd
.pool
);
2611 priv
->cmd
.pool
= NULL
;
2614 if (!mlx4_is_slave(dev
) && priv
->cmd
.hcr
&&
2615 (cleanup_mask
& MLX4_CMD_CLEANUP_HCR
)) {
2616 iounmap(priv
->cmd
.hcr
);
2617 priv
->cmd
.hcr
= NULL
;
2619 if (mlx4_is_mfunc(dev
) && priv
->mfunc
.vhcr
&&
2620 (cleanup_mask
& MLX4_CMD_CLEANUP_VHCR
)) {
2621 dma_free_coherent(&dev
->persist
->pdev
->dev
, PAGE_SIZE
,
2622 priv
->mfunc
.vhcr
, priv
->mfunc
.vhcr_dma
);
2623 priv
->mfunc
.vhcr
= NULL
;
2625 if (priv
->cmd
.initialized
&& (cleanup_mask
& MLX4_CMD_CLEANUP_STRUCT
))
2626 priv
->cmd
.initialized
= 0;
2630 * Switch to using events to issue FW commands (can only be called
2631 * after event queue for command events has been initialized).
2633 int mlx4_cmd_use_events(struct mlx4_dev
*dev
)
2635 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2639 priv
->cmd
.context
= kmalloc(priv
->cmd
.max_cmds
*
2640 sizeof (struct mlx4_cmd_context
),
2642 if (!priv
->cmd
.context
)
2645 down_write(&priv
->cmd
.switch_sem
);
2646 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
) {
2647 priv
->cmd
.context
[i
].token
= i
;
2648 priv
->cmd
.context
[i
].next
= i
+ 1;
2649 /* To support fatal error flow, initialize all
2650 * cmd contexts to allow simulating completions
2651 * with complete() at any time.
2653 init_completion(&priv
->cmd
.context
[i
].done
);
2656 priv
->cmd
.context
[priv
->cmd
.max_cmds
- 1].next
= -1;
2657 priv
->cmd
.free_head
= 0;
2659 sema_init(&priv
->cmd
.event_sem
, priv
->cmd
.max_cmds
);
2661 for (priv
->cmd
.token_mask
= 1;
2662 priv
->cmd
.token_mask
< priv
->cmd
.max_cmds
;
2663 priv
->cmd
.token_mask
<<= 1)
2665 --priv
->cmd
.token_mask
;
2667 down(&priv
->cmd
.poll_sem
);
2668 priv
->cmd
.use_events
= 1;
2669 up_write(&priv
->cmd
.switch_sem
);
2675 * Switch back to polling (used when shutting down the device)
2677 void mlx4_cmd_use_polling(struct mlx4_dev
*dev
)
2679 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2682 down_write(&priv
->cmd
.switch_sem
);
2683 priv
->cmd
.use_events
= 0;
2685 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
)
2686 down(&priv
->cmd
.event_sem
);
2688 kfree(priv
->cmd
.context
);
2690 up(&priv
->cmd
.poll_sem
);
2691 up_write(&priv
->cmd
.switch_sem
);
2694 struct mlx4_cmd_mailbox
*mlx4_alloc_cmd_mailbox(struct mlx4_dev
*dev
)
2696 struct mlx4_cmd_mailbox
*mailbox
;
2698 mailbox
= kmalloc(sizeof *mailbox
, GFP_KERNEL
);
2700 return ERR_PTR(-ENOMEM
);
2702 mailbox
->buf
= pci_pool_zalloc(mlx4_priv(dev
)->cmd
.pool
, GFP_KERNEL
,
2704 if (!mailbox
->buf
) {
2706 return ERR_PTR(-ENOMEM
);
2711 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox
);
2713 void mlx4_free_cmd_mailbox(struct mlx4_dev
*dev
,
2714 struct mlx4_cmd_mailbox
*mailbox
)
2719 pci_pool_free(mlx4_priv(dev
)->cmd
.pool
, mailbox
->buf
, mailbox
->dma
);
2722 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox
);
2724 u32
mlx4_comm_get_version(void)
2726 return ((u32
) CMD_CHAN_IF_REV
<< 8) | (u32
) CMD_CHAN_VER
;
2729 static int mlx4_get_slave_indx(struct mlx4_dev
*dev
, int vf
)
2731 if ((vf
< 0) || (vf
>= dev
->persist
->num_vfs
)) {
2732 mlx4_err(dev
, "Bad vf number:%d (number of activated vf: %d)\n",
2733 vf
, dev
->persist
->num_vfs
);
2740 int mlx4_get_vf_indx(struct mlx4_dev
*dev
, int slave
)
2742 if (slave
< 1 || slave
> dev
->persist
->num_vfs
) {
2744 "Bad slave number:%d (number of activated slaves: %lu)\n",
2745 slave
, dev
->num_slaves
);
2751 void mlx4_cmd_wake_completions(struct mlx4_dev
*dev
)
2753 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2754 struct mlx4_cmd_context
*context
;
2757 spin_lock(&priv
->cmd
.context_lock
);
2758 if (priv
->cmd
.context
) {
2759 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
) {
2760 context
= &priv
->cmd
.context
[i
];
2761 context
->fw_status
= CMD_STAT_INTERNAL_ERR
;
2763 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR
);
2764 complete(&context
->done
);
2767 spin_unlock(&priv
->cmd
.context_lock
);
2770 struct mlx4_active_ports
mlx4_get_active_ports(struct mlx4_dev
*dev
, int slave
)
2772 struct mlx4_active_ports actv_ports
;
2775 bitmap_zero(actv_ports
.ports
, MLX4_MAX_PORTS
);
2778 bitmap_fill(actv_ports
.ports
, dev
->caps
.num_ports
);
2782 vf
= mlx4_get_vf_indx(dev
, slave
);
2786 bitmap_set(actv_ports
.ports
, dev
->dev_vfs
[vf
].min_port
- 1,
2787 min((int)dev
->dev_vfs
[mlx4_get_vf_indx(dev
, slave
)].n_ports
,
2788 dev
->caps
.num_ports
));
2792 EXPORT_SYMBOL_GPL(mlx4_get_active_ports
);
2794 int mlx4_slave_convert_port(struct mlx4_dev
*dev
, int slave
, int port
)
2797 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(dev
, slave
);
2798 unsigned m
= bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
);
2800 if (port
<= 0 || port
> m
)
2803 n
= find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
);
2809 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port
);
2811 int mlx4_phys_to_slave_port(struct mlx4_dev
*dev
, int slave
, int port
)
2813 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(dev
, slave
);
2814 if (test_bit(port
- 1, actv_ports
.ports
))
2816 find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
);
2820 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port
);
2822 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport(struct mlx4_dev
*dev
,
2826 struct mlx4_slaves_pport slaves_pport
;
2828 bitmap_zero(slaves_pport
.slaves
, MLX4_MFUNC_MAX
);
2830 if (port
<= 0 || port
> dev
->caps
.num_ports
)
2831 return slaves_pport
;
2833 for (i
= 0; i
< dev
->persist
->num_vfs
+ 1; i
++) {
2834 struct mlx4_active_ports actv_ports
=
2835 mlx4_get_active_ports(dev
, i
);
2836 if (test_bit(port
- 1, actv_ports
.ports
))
2837 set_bit(i
, slaves_pport
.slaves
);
2840 return slaves_pport
;
2842 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport
);
2844 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport_actv(
2845 struct mlx4_dev
*dev
,
2846 const struct mlx4_active_ports
*crit_ports
)
2849 struct mlx4_slaves_pport slaves_pport
;
2851 bitmap_zero(slaves_pport
.slaves
, MLX4_MFUNC_MAX
);
2853 for (i
= 0; i
< dev
->persist
->num_vfs
+ 1; i
++) {
2854 struct mlx4_active_ports actv_ports
=
2855 mlx4_get_active_ports(dev
, i
);
2856 if (bitmap_equal(crit_ports
->ports
, actv_ports
.ports
,
2857 dev
->caps
.num_ports
))
2858 set_bit(i
, slaves_pport
.slaves
);
2861 return slaves_pport
;
2863 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv
);
2865 static int mlx4_slaves_closest_port(struct mlx4_dev
*dev
, int slave
, int port
)
2867 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(dev
, slave
);
2868 int min_port
= find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
)
2870 int max_port
= min_port
+
2871 bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
);
2873 if (port
< min_port
)
2875 else if (port
>= max_port
)
2876 port
= max_port
- 1;
2881 static int mlx4_set_vport_qos(struct mlx4_priv
*priv
, int slave
, int port
,
2886 struct mlx4_qos_manager
*port_qos
;
2887 struct mlx4_dev
*dev
= &priv
->dev
;
2888 struct mlx4_vport_qos_param vpp_qos
[MLX4_NUM_UP
];
2890 port_qos
= &priv
->mfunc
.master
.qos_ctl
[port
];
2891 memset(vpp_qos
, 0, sizeof(struct mlx4_vport_qos_param
) * MLX4_NUM_UP
);
2893 if (slave
> port_qos
->num_of_qos_vfs
) {
2894 mlx4_info(dev
, "No availible VPP resources for this VF\n");
2898 /* Query for default QoS values from Vport 0 is needed */
2899 err
= mlx4_SET_VPORT_QOS_get(dev
, port
, 0, vpp_qos
);
2901 mlx4_info(dev
, "Failed to query Vport 0 QoS values\n");
2905 for (i
= 0; i
< MLX4_NUM_UP
; i
++) {
2906 if (test_bit(i
, port_qos
->priority_bm
) && max_tx_rate
) {
2907 vpp_qos
[i
].max_avg_bw
= max_tx_rate
;
2908 vpp_qos
[i
].enable
= 1;
2910 /* if user supplied tx_rate == 0, meaning no rate limit
2911 * configuration is required. so we are leaving the
2912 * value of max_avg_bw as queried from Vport 0.
2914 vpp_qos
[i
].enable
= 0;
2918 err
= mlx4_SET_VPORT_QOS_set(dev
, port
, slave
, vpp_qos
);
2920 mlx4_info(dev
, "Failed to set Vport %d QoS values\n", slave
);
2927 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev
*dev
, int port
,
2928 struct mlx4_vport_state
*vf_admin
)
2930 struct mlx4_qos_manager
*info
;
2931 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2933 if (!mlx4_is_master(dev
) ||
2934 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_QOS_VPP
))
2937 info
= &priv
->mfunc
.master
.qos_ctl
[port
];
2939 if (vf_admin
->default_vlan
!= MLX4_VGT
&&
2940 test_bit(vf_admin
->default_qos
, info
->priority_bm
))
2946 static bool mlx4_valid_vf_state_change(struct mlx4_dev
*dev
, int port
,
2947 struct mlx4_vport_state
*vf_admin
,
2950 struct mlx4_vport_state dummy_admin
= {0};
2952 if (!mlx4_is_vf_vst_and_prio_qos(dev
, port
, vf_admin
) ||
2956 dummy_admin
.default_qos
= qos
;
2957 dummy_admin
.default_vlan
= vlan
;
2959 /* VF wants to move to other VST state which is valid with current
2960 * rate limit. Either differnt default vlan in VST or other
2961 * supported QoS priority. Otherwise we don't allow this change when
2962 * the TX rate is still configured.
2964 if (mlx4_is_vf_vst_and_prio_qos(dev
, port
, &dummy_admin
))
2967 mlx4_info(dev
, "Cannot change VF state to %s while rate is set\n",
2968 (vlan
== MLX4_VGT
) ? "VGT" : "VST");
2970 if (vlan
!= MLX4_VGT
)
2971 mlx4_info(dev
, "VST priority %d not supported for QoS\n", qos
);
2973 mlx4_info(dev
, "Please set rate to 0 prior to this VF state change\n");
2978 int mlx4_set_vf_mac(struct mlx4_dev
*dev
, int port
, int vf
, u8
*mac
)
2980 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2981 struct mlx4_vport_state
*s_info
;
2984 if (!mlx4_is_master(dev
))
2985 return -EPROTONOSUPPORT
;
2987 if (is_multicast_ether_addr(mac
))
2990 slave
= mlx4_get_slave_indx(dev
, vf
);
2994 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
2995 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2997 if (s_info
->spoofchk
&& is_zero_ether_addr(mac
)) {
2998 mlx4_info(dev
, "MAC invalidation is not allowed when spoofchk is on\n");
3002 s_info
->mac
= mlx4_mac_to_u64(mac
);
3003 mlx4_info(dev
, "default mac on vf %d port %d to %llX will take effect only after vf restart\n",
3004 vf
, port
, s_info
->mac
);
3007 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac
);
3010 int mlx4_set_vf_vlan(struct mlx4_dev
*dev
, int port
, int vf
, u16 vlan
, u8 qos
,
3013 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3014 struct mlx4_vport_state
*vf_admin
;
3015 struct mlx4_slave_state
*slave_state
;
3016 struct mlx4_vport_oper_state
*vf_oper
;
3019 if ((!mlx4_is_master(dev
)) ||
3020 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
))
3021 return -EPROTONOSUPPORT
;
3023 if ((vlan
> 4095) || (qos
> 7))
3026 if (proto
== htons(ETH_P_8021AD
) &&
3027 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP
))
3028 return -EPROTONOSUPPORT
;
3030 if (proto
!= htons(ETH_P_8021Q
) &&
3031 proto
!= htons(ETH_P_8021AD
))
3034 if ((proto
== htons(ETH_P_8021AD
)) &&
3035 ((vlan
== 0) || (vlan
== MLX4_VGT
)))
3038 slave
= mlx4_get_slave_indx(dev
, vf
);
3042 slave_state
= &priv
->mfunc
.master
.slave_state
[slave
];
3043 if ((proto
== htons(ETH_P_8021AD
)) && (slave_state
->active
) &&
3044 (!slave_state
->vst_qinq_supported
)) {
3045 mlx4_err(dev
, "vf %d does not support VST QinQ mode\n", vf
);
3046 return -EPROTONOSUPPORT
;
3048 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
3049 vf_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
3050 vf_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
3052 if (!mlx4_valid_vf_state_change(dev
, port
, vf_admin
, vlan
, qos
))
3055 if ((0 == vlan
) && (0 == qos
))
3056 vf_admin
->default_vlan
= MLX4_VGT
;
3058 vf_admin
->default_vlan
= vlan
;
3059 vf_admin
->default_qos
= qos
;
3060 vf_admin
->vlan_proto
= proto
;
3062 /* If rate was configured prior to VST, we saved the configured rate
3063 * in vf_admin->rate and now, if priority supported we enforce the QoS
3065 if (mlx4_is_vf_vst_and_prio_qos(dev
, port
, vf_admin
) &&
3067 vf_admin
->qos_vport
= slave
;
3069 /* Try to activate new vf state without restart,
3070 * this option is not supported while moving to VST QinQ mode.
3072 if ((proto
== htons(ETH_P_8021AD
) &&
3073 vf_oper
->state
.vlan_proto
!= proto
) ||
3074 mlx4_master_immediate_activate_vlan_qos(priv
, slave
, port
))
3076 "updating vf %d port %d config will take effect on next VF restart\n",
3080 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan
);
3082 int mlx4_set_vf_rate(struct mlx4_dev
*dev
, int port
, int vf
, int min_tx_rate
,
3087 struct mlx4_vport_state
*vf_admin
;
3088 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3090 if (!mlx4_is_master(dev
) ||
3091 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_QOS_VPP
))
3092 return -EPROTONOSUPPORT
;
3095 mlx4_info(dev
, "Minimum BW share not supported\n");
3096 return -EPROTONOSUPPORT
;
3099 slave
= mlx4_get_slave_indx(dev
, vf
);
3103 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
3104 vf_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
3106 err
= mlx4_set_vport_qos(priv
, slave
, port
, max_tx_rate
);
3108 mlx4_info(dev
, "vf %d failed to set rate %d\n", vf
,
3113 vf_admin
->tx_rate
= max_tx_rate
;
3114 /* if VF is not in supported mode (VST with supported prio),
3115 * we do not change vport configuration for its QPs, but save
3116 * the rate, so it will be enforced when it moves to supported
3119 if (!mlx4_is_vf_vst_and_prio_qos(dev
, port
, vf_admin
)) {
3121 "rate set for VF %d when not in valid state\n", vf
);
3123 if (vf_admin
->default_vlan
!= MLX4_VGT
)
3124 mlx4_info(dev
, "VST priority not supported by QoS\n");
3126 mlx4_info(dev
, "VF in VGT mode (needed VST)\n");
3129 "rate %d take affect when VF moves to valid state\n",
3134 /* If user sets rate 0 assigning default vport for its QPs */
3135 vf_admin
->qos_vport
= max_tx_rate
? slave
: MLX4_VPP_DEFAULT_VPORT
;
3137 if (priv
->mfunc
.master
.slave_state
[slave
].active
&&
3138 dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_UPDATE_QP
)
3139 mlx4_master_immediate_activate_vlan_qos(priv
, slave
, port
);
3143 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate
);
3145 /* mlx4_get_slave_default_vlan -
3146 * return true if VST ( default vlan)
3147 * if VST, will return vlan & qos (if not NULL)
3149 bool mlx4_get_slave_default_vlan(struct mlx4_dev
*dev
, int port
, int slave
,
3152 struct mlx4_vport_oper_state
*vp_oper
;
3153 struct mlx4_priv
*priv
;
3155 priv
= mlx4_priv(dev
);
3156 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
3157 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
3159 if (MLX4_VGT
!= vp_oper
->state
.default_vlan
) {
3161 *vlan
= vp_oper
->state
.default_vlan
;
3163 *qos
= vp_oper
->state
.default_qos
;
3168 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan
);
3170 int mlx4_set_vf_spoofchk(struct mlx4_dev
*dev
, int port
, int vf
, bool setting
)
3172 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3173 struct mlx4_vport_state
*s_info
;
3177 if ((!mlx4_is_master(dev
)) ||
3178 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_FSM
))
3179 return -EPROTONOSUPPORT
;
3181 slave
= mlx4_get_slave_indx(dev
, vf
);
3185 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
3186 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
3188 mlx4_u64_to_mac(mac
, s_info
->mac
);
3189 if (setting
&& !is_valid_ether_addr(mac
)) {
3190 mlx4_info(dev
, "Illegal MAC with spoofchk\n");
3194 s_info
->spoofchk
= setting
;
3198 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk
);
3200 int mlx4_get_vf_config(struct mlx4_dev
*dev
, int port
, int vf
, struct ifla_vf_info
*ivf
)
3202 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3203 struct mlx4_vport_state
*s_info
;
3206 if (!mlx4_is_master(dev
))
3207 return -EPROTONOSUPPORT
;
3209 slave
= mlx4_get_slave_indx(dev
, vf
);
3213 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
3216 /* need to convert it to a func */
3217 ivf
->mac
[0] = ((s_info
->mac
>> (5*8)) & 0xff);
3218 ivf
->mac
[1] = ((s_info
->mac
>> (4*8)) & 0xff);
3219 ivf
->mac
[2] = ((s_info
->mac
>> (3*8)) & 0xff);
3220 ivf
->mac
[3] = ((s_info
->mac
>> (2*8)) & 0xff);
3221 ivf
->mac
[4] = ((s_info
->mac
>> (1*8)) & 0xff);
3222 ivf
->mac
[5] = ((s_info
->mac
) & 0xff);
3224 ivf
->vlan
= s_info
->default_vlan
;
3225 ivf
->qos
= s_info
->default_qos
;
3226 ivf
->vlan_proto
= s_info
->vlan_proto
;
3228 if (mlx4_is_vf_vst_and_prio_qos(dev
, port
, s_info
))
3229 ivf
->max_tx_rate
= s_info
->tx_rate
;
3231 ivf
->max_tx_rate
= 0;
3233 ivf
->min_tx_rate
= 0;
3234 ivf
->spoofchk
= s_info
->spoofchk
;
3235 ivf
->linkstate
= s_info
->link_state
;
3239 EXPORT_SYMBOL_GPL(mlx4_get_vf_config
);
3241 int mlx4_set_vf_link_state(struct mlx4_dev
*dev
, int port
, int vf
, int link_state
)
3243 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3244 struct mlx4_vport_state
*s_info
;
3248 slave
= mlx4_get_slave_indx(dev
, vf
);
3252 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
3253 switch (link_state
) {
3254 case IFLA_VF_LINK_STATE_AUTO
:
3255 /* get current link state */
3256 if (!priv
->sense
.do_sense_port
[port
])
3257 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
;
3259 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_DOWN
;
3262 case IFLA_VF_LINK_STATE_ENABLE
:
3263 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
;
3266 case IFLA_VF_LINK_STATE_DISABLE
:
3267 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_DOWN
;
3271 mlx4_warn(dev
, "unknown value for link_state %02x on slave %d port %d\n",
3272 link_state
, slave
, port
);
3275 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
3276 s_info
->link_state
= link_state
;
3279 mlx4_gen_port_state_change_eqe(dev
, slave
, port
, link_stat_event
);
3281 if (mlx4_master_immediate_activate_vlan_qos(priv
, slave
, port
))
3283 "updating vf %d port %d no link state HW enforcment\n",
3287 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state
);
3289 int mlx4_get_counter_stats(struct mlx4_dev
*dev
, int counter_index
,
3290 struct mlx4_counter
*counter_stats
, int reset
)
3292 struct mlx4_cmd_mailbox
*mailbox
= NULL
;
3293 struct mlx4_counter
*tmp_counter
;
3300 if (counter_index
== MLX4_SINK_COUNTER_INDEX(dev
))
3303 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
3304 if (IS_ERR(mailbox
))
3305 return PTR_ERR(mailbox
);
3307 memset(mailbox
->buf
, 0, sizeof(struct mlx4_counter
));
3308 if_stat_in_mod
= counter_index
;
3310 if_stat_in_mod
|= MLX4_QUERY_IF_STAT_RESET
;
3311 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
,
3313 MLX4_CMD_QUERY_IF_STAT
,
3314 MLX4_CMD_TIME_CLASS_C
,
3317 mlx4_dbg(dev
, "%s: failed to read statistics for counter index %d\n",
3318 __func__
, counter_index
);
3321 tmp_counter
= (struct mlx4_counter
*)mailbox
->buf
;
3322 counter_stats
->counter_mode
= tmp_counter
->counter_mode
;
3323 if (counter_stats
->counter_mode
== 0) {
3324 counter_stats
->rx_frames
=
3325 cpu_to_be64(be64_to_cpu(counter_stats
->rx_frames
) +
3326 be64_to_cpu(tmp_counter
->rx_frames
));
3327 counter_stats
->tx_frames
=
3328 cpu_to_be64(be64_to_cpu(counter_stats
->tx_frames
) +
3329 be64_to_cpu(tmp_counter
->tx_frames
));
3330 counter_stats
->rx_bytes
=
3331 cpu_to_be64(be64_to_cpu(counter_stats
->rx_bytes
) +
3332 be64_to_cpu(tmp_counter
->rx_bytes
));
3333 counter_stats
->tx_bytes
=
3334 cpu_to_be64(be64_to_cpu(counter_stats
->tx_bytes
) +
3335 be64_to_cpu(tmp_counter
->tx_bytes
));
3339 mlx4_free_cmd_mailbox(dev
, mailbox
);
3343 EXPORT_SYMBOL_GPL(mlx4_get_counter_stats
);
3345 int mlx4_get_vf_stats(struct mlx4_dev
*dev
, int port
, int vf_idx
,
3346 struct ifla_vf_stats
*vf_stats
)
3348 struct mlx4_counter tmp_vf_stats
;
3355 if (!mlx4_is_master(dev
))
3356 return -EPROTONOSUPPORT
;
3358 slave
= mlx4_get_slave_indx(dev
, vf_idx
);
3362 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
3363 err
= mlx4_calc_vf_counters(dev
, slave
, port
, &tmp_vf_stats
);
3364 if (!err
&& tmp_vf_stats
.counter_mode
== 0) {
3365 vf_stats
->rx_packets
= be64_to_cpu(tmp_vf_stats
.rx_frames
);
3366 vf_stats
->tx_packets
= be64_to_cpu(tmp_vf_stats
.tx_frames
);
3367 vf_stats
->rx_bytes
= be64_to_cpu(tmp_vf_stats
.rx_bytes
);
3368 vf_stats
->tx_bytes
= be64_to_cpu(tmp_vf_stats
.tx_bytes
);
3373 EXPORT_SYMBOL_GPL(mlx4_get_vf_stats
);
3375 int mlx4_vf_smi_enabled(struct mlx4_dev
*dev
, int slave
, int port
)
3377 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3379 if (slave
< 1 || slave
>= dev
->num_slaves
||
3380 port
< 1 || port
> MLX4_MAX_PORTS
)
3383 return priv
->mfunc
.master
.vf_oper
[slave
].smi_enabled
[port
] ==
3384 MLX4_VF_SMI_ENABLED
;
3386 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled
);
3388 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
)
3390 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3392 if (slave
== mlx4_master_func_num(dev
))
3395 if (slave
< 1 || slave
>= dev
->num_slaves
||
3396 port
< 1 || port
> MLX4_MAX_PORTS
)
3399 return priv
->mfunc
.master
.vf_admin
[slave
].enable_smi
[port
] ==
3400 MLX4_VF_SMI_ENABLED
;
3402 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin
);
3404 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
,
3407 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3408 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(
3410 int min_port
= find_first_bit(actv_ports
.ports
,
3411 priv
->dev
.caps
.num_ports
) + 1;
3412 int max_port
= min_port
- 1 +
3413 bitmap_weight(actv_ports
.ports
, priv
->dev
.caps
.num_ports
);
3415 if (slave
== mlx4_master_func_num(dev
))
3418 if (slave
< 1 || slave
>= dev
->num_slaves
||
3419 port
< 1 || port
> MLX4_MAX_PORTS
||
3420 enabled
< 0 || enabled
> 1)
3423 if (min_port
== max_port
&& dev
->caps
.num_ports
> 1) {
3424 mlx4_info(dev
, "SMI access disallowed for single ported VFs\n");
3425 return -EPROTONOSUPPORT
;
3428 priv
->mfunc
.master
.vf_admin
[slave
].enable_smi
[port
] = enabled
;
3431 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin
);