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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/ethernet/mellanox/mlx4/cq.c
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/hardirq.h>
38 #include <linux/export.h>
40 #include <linux/mlx4/cmd.h>
41 #include <linux/mlx4/cq.h>
46 #define MLX4_CQ_STATUS_OK ( 0 << 28)
47 #define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
48 #define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
49 #define MLX4_CQ_FLAG_CC ( 1 << 18)
50 #define MLX4_CQ_FLAG_OI ( 1 << 17)
51 #define MLX4_CQ_STATE_ARMED ( 9 << 8)
52 #define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
53 #define MLX4_EQ_STATE_FIRED (10 << 8)
55 #define TASKLET_MAX_TIME 2
56 #define TASKLET_MAX_TIME_JIFFIES msecs_to_jiffies(TASKLET_MAX_TIME)
58 void mlx4_cq_tasklet_cb(unsigned long data
)
61 unsigned long end
= jiffies
+ TASKLET_MAX_TIME_JIFFIES
;
62 struct mlx4_eq_tasklet
*ctx
= (struct mlx4_eq_tasklet
*)data
;
63 struct mlx4_cq
*mcq
, *temp
;
65 spin_lock_irqsave(&ctx
->lock
, flags
);
66 list_splice_tail_init(&ctx
->list
, &ctx
->process_list
);
67 spin_unlock_irqrestore(&ctx
->lock
, flags
);
69 list_for_each_entry_safe(mcq
, temp
, &ctx
->process_list
, tasklet_ctx
.list
) {
70 list_del_init(&mcq
->tasklet_ctx
.list
);
71 mcq
->tasklet_ctx
.comp(mcq
);
72 if (atomic_dec_and_test(&mcq
->refcount
))
74 if (time_after(jiffies
, end
))
78 if (!list_empty(&ctx
->process_list
))
79 tasklet_schedule(&ctx
->task
);
82 static void mlx4_add_cq_to_tasklet(struct mlx4_cq
*cq
)
85 struct mlx4_eq_tasklet
*tasklet_ctx
= cq
->tasklet_ctx
.priv
;
87 spin_lock_irqsave(&tasklet_ctx
->lock
, flags
);
88 /* When migrating CQs between EQs will be implemented, please note
89 * that you need to sync this point. It is possible that
90 * while migrating a CQ, completions on the old EQs could
93 if (list_empty_careful(&cq
->tasklet_ctx
.list
)) {
94 atomic_inc(&cq
->refcount
);
95 list_add_tail(&cq
->tasklet_ctx
.list
, &tasklet_ctx
->list
);
97 spin_unlock_irqrestore(&tasklet_ctx
->lock
, flags
);
100 void mlx4_cq_completion(struct mlx4_dev
*dev
, u32 cqn
)
104 cq
= radix_tree_lookup(&mlx4_priv(dev
)->cq_table
.tree
,
105 cqn
& (dev
->caps
.num_cqs
- 1));
107 mlx4_dbg(dev
, "Completion event for bogus CQ %08x\n", cqn
);
116 void mlx4_cq_event(struct mlx4_dev
*dev
, u32 cqn
, int event_type
)
118 struct mlx4_cq_table
*cq_table
= &mlx4_priv(dev
)->cq_table
;
121 spin_lock(&cq_table
->lock
);
123 cq
= radix_tree_lookup(&cq_table
->tree
, cqn
& (dev
->caps
.num_cqs
- 1));
125 atomic_inc(&cq
->refcount
);
127 spin_unlock(&cq_table
->lock
);
130 mlx4_warn(dev
, "Async event for bogus CQ %08x\n", cqn
);
134 cq
->event(cq
, event_type
);
136 if (atomic_dec_and_test(&cq
->refcount
))
140 static int mlx4_SW2HW_CQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
143 return mlx4_cmd(dev
, mailbox
->dma
, cq_num
, 0,
144 MLX4_CMD_SW2HW_CQ
, MLX4_CMD_TIME_CLASS_A
,
148 static int mlx4_MODIFY_CQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
149 int cq_num
, u32 opmod
)
151 return mlx4_cmd(dev
, mailbox
->dma
, cq_num
, opmod
, MLX4_CMD_MODIFY_CQ
,
152 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
155 static int mlx4_HW2SW_CQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
158 return mlx4_cmd_box(dev
, 0, mailbox
? mailbox
->dma
: 0,
159 cq_num
, mailbox
? 0 : 1, MLX4_CMD_HW2SW_CQ
,
160 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
163 int mlx4_cq_modify(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
,
164 u16 count
, u16 period
)
166 struct mlx4_cmd_mailbox
*mailbox
;
167 struct mlx4_cq_context
*cq_context
;
170 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
172 return PTR_ERR(mailbox
);
174 cq_context
= mailbox
->buf
;
175 cq_context
->cq_max_count
= cpu_to_be16(count
);
176 cq_context
->cq_period
= cpu_to_be16(period
);
178 err
= mlx4_MODIFY_CQ(dev
, mailbox
, cq
->cqn
, 1);
180 mlx4_free_cmd_mailbox(dev
, mailbox
);
183 EXPORT_SYMBOL_GPL(mlx4_cq_modify
);
185 int mlx4_cq_resize(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
,
186 int entries
, struct mlx4_mtt
*mtt
)
188 struct mlx4_cmd_mailbox
*mailbox
;
189 struct mlx4_cq_context
*cq_context
;
193 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
195 return PTR_ERR(mailbox
);
197 cq_context
= mailbox
->buf
;
198 cq_context
->logsize_usrpage
= cpu_to_be32(ilog2(entries
) << 24);
199 cq_context
->log_page_size
= mtt
->page_shift
- 12;
200 mtt_addr
= mlx4_mtt_addr(dev
, mtt
);
201 cq_context
->mtt_base_addr_h
= mtt_addr
>> 32;
202 cq_context
->mtt_base_addr_l
= cpu_to_be32(mtt_addr
& 0xffffffff);
204 err
= mlx4_MODIFY_CQ(dev
, mailbox
, cq
->cqn
, 0);
206 mlx4_free_cmd_mailbox(dev
, mailbox
);
209 EXPORT_SYMBOL_GPL(mlx4_cq_resize
);
211 int __mlx4_cq_alloc_icm(struct mlx4_dev
*dev
, int *cqn
)
213 struct mlx4_priv
*priv
= mlx4_priv(dev
);
214 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
217 *cqn
= mlx4_bitmap_alloc(&cq_table
->bitmap
);
221 err
= mlx4_table_get(dev
, &cq_table
->table
, *cqn
, GFP_KERNEL
);
225 err
= mlx4_table_get(dev
, &cq_table
->cmpt_table
, *cqn
, GFP_KERNEL
);
231 mlx4_table_put(dev
, &cq_table
->table
, *cqn
);
234 mlx4_bitmap_free(&cq_table
->bitmap
, *cqn
, MLX4_NO_RR
);
238 static int mlx4_cq_alloc_icm(struct mlx4_dev
*dev
, int *cqn
)
243 if (mlx4_is_mfunc(dev
)) {
244 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_CQ
,
245 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
246 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
250 *cqn
= get_param_l(&out_param
);
254 return __mlx4_cq_alloc_icm(dev
, cqn
);
257 void __mlx4_cq_free_icm(struct mlx4_dev
*dev
, int cqn
)
259 struct mlx4_priv
*priv
= mlx4_priv(dev
);
260 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
262 mlx4_table_put(dev
, &cq_table
->cmpt_table
, cqn
);
263 mlx4_table_put(dev
, &cq_table
->table
, cqn
);
264 mlx4_bitmap_free(&cq_table
->bitmap
, cqn
, MLX4_NO_RR
);
267 static void mlx4_cq_free_icm(struct mlx4_dev
*dev
, int cqn
)
272 if (mlx4_is_mfunc(dev
)) {
273 set_param_l(&in_param
, cqn
);
274 err
= mlx4_cmd(dev
, in_param
, RES_CQ
, RES_OP_RESERVE_AND_MAP
,
276 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
278 mlx4_warn(dev
, "Failed freeing cq:%d\n", cqn
);
280 __mlx4_cq_free_icm(dev
, cqn
);
283 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
,
284 struct mlx4_mtt
*mtt
, struct mlx4_uar
*uar
, u64 db_rec
,
285 struct mlx4_cq
*cq
, unsigned vector
, int collapsed
,
288 struct mlx4_priv
*priv
= mlx4_priv(dev
);
289 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
290 struct mlx4_cmd_mailbox
*mailbox
;
291 struct mlx4_cq_context
*cq_context
;
295 if (vector
>= dev
->caps
.num_comp_vectors
)
300 err
= mlx4_cq_alloc_icm(dev
, &cq
->cqn
);
304 spin_lock_irq(&cq_table
->lock
);
305 err
= radix_tree_insert(&cq_table
->tree
, cq
->cqn
, cq
);
306 spin_unlock_irq(&cq_table
->lock
);
310 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
311 if (IS_ERR(mailbox
)) {
312 err
= PTR_ERR(mailbox
);
316 cq_context
= mailbox
->buf
;
317 cq_context
->flags
= cpu_to_be32(!!collapsed
<< 18);
319 cq_context
->flags
|= cpu_to_be32(1 << 19);
321 cq_context
->logsize_usrpage
=
322 cpu_to_be32((ilog2(nent
) << 24) |
323 mlx4_to_hw_uar_index(dev
, uar
->index
));
324 cq_context
->comp_eqn
= priv
->eq_table
.eq
[MLX4_CQ_TO_EQ_VECTOR(vector
)].eqn
;
325 cq_context
->log_page_size
= mtt
->page_shift
- MLX4_ICM_PAGE_SHIFT
;
327 mtt_addr
= mlx4_mtt_addr(dev
, mtt
);
328 cq_context
->mtt_base_addr_h
= mtt_addr
>> 32;
329 cq_context
->mtt_base_addr_l
= cpu_to_be32(mtt_addr
& 0xffffffff);
330 cq_context
->db_rec_addr
= cpu_to_be64(db_rec
);
332 err
= mlx4_SW2HW_CQ(dev
, mailbox
, cq
->cqn
);
333 mlx4_free_cmd_mailbox(dev
, mailbox
);
340 atomic_set(&cq
->refcount
, 1);
341 init_completion(&cq
->free
);
342 cq
->comp
= mlx4_add_cq_to_tasklet
;
343 cq
->tasklet_ctx
.priv
=
344 &priv
->eq_table
.eq
[MLX4_CQ_TO_EQ_VECTOR(vector
)].tasklet_ctx
;
345 INIT_LIST_HEAD(&cq
->tasklet_ctx
.list
);
348 cq
->irq
= priv
->eq_table
.eq
[MLX4_CQ_TO_EQ_VECTOR(vector
)].irq
;
352 spin_lock_irq(&cq_table
->lock
);
353 radix_tree_delete(&cq_table
->tree
, cq
->cqn
);
354 spin_unlock_irq(&cq_table
->lock
);
357 mlx4_cq_free_icm(dev
, cq
->cqn
);
361 EXPORT_SYMBOL_GPL(mlx4_cq_alloc
);
363 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
)
365 struct mlx4_priv
*priv
= mlx4_priv(dev
);
366 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
369 err
= mlx4_HW2SW_CQ(dev
, NULL
, cq
->cqn
);
371 mlx4_warn(dev
, "HW2SW_CQ failed (%d) for CQN %06x\n", err
, cq
->cqn
);
373 synchronize_irq(priv
->eq_table
.eq
[MLX4_CQ_TO_EQ_VECTOR(cq
->vector
)].irq
);
374 if (priv
->eq_table
.eq
[MLX4_CQ_TO_EQ_VECTOR(cq
->vector
)].irq
!=
375 priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].irq
)
376 synchronize_irq(priv
->eq_table
.eq
[MLX4_EQ_ASYNC
].irq
);
378 spin_lock_irq(&cq_table
->lock
);
379 radix_tree_delete(&cq_table
->tree
, cq
->cqn
);
380 spin_unlock_irq(&cq_table
->lock
);
382 if (atomic_dec_and_test(&cq
->refcount
))
384 wait_for_completion(&cq
->free
);
386 mlx4_cq_free_icm(dev
, cq
->cqn
);
388 EXPORT_SYMBOL_GPL(mlx4_cq_free
);
390 int mlx4_init_cq_table(struct mlx4_dev
*dev
)
392 struct mlx4_cq_table
*cq_table
= &mlx4_priv(dev
)->cq_table
;
395 spin_lock_init(&cq_table
->lock
);
396 INIT_RADIX_TREE(&cq_table
->tree
, GFP_ATOMIC
);
397 if (mlx4_is_slave(dev
))
400 err
= mlx4_bitmap_init(&cq_table
->bitmap
, dev
->caps
.num_cqs
,
401 dev
->caps
.num_cqs
- 1, dev
->caps
.reserved_cqs
, 0);
408 void mlx4_cleanup_cq_table(struct mlx4_dev
*dev
)
410 if (mlx4_is_slave(dev
))
412 /* Nothing to do to clean up radix_tree */
413 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->cq_table
.bitmap
);