2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/vmalloc.h>
41 #include <linux/tcp.h>
43 #include <linux/moduleparam.h>
47 int mlx4_en_create_tx_ring(struct mlx4_en_priv
*priv
,
48 struct mlx4_en_tx_ring
**pring
, int qpn
, u32 size
,
49 u16 stride
, int node
, int queue_index
)
51 struct mlx4_en_dev
*mdev
= priv
->mdev
;
52 struct mlx4_en_tx_ring
*ring
;
56 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, node
);
58 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
60 en_err(priv
, "Failed allocating TX ring\n");
66 ring
->size_mask
= size
- 1;
67 ring
->stride
= stride
;
68 ring
->inline_thold
= priv
->prof
->inline_thold
;
70 tmp
= size
* sizeof(struct mlx4_en_tx_info
);
71 ring
->tx_info
= vmalloc_node(tmp
, node
);
73 ring
->tx_info
= vmalloc(tmp
);
80 en_dbg(DRV
, priv
, "Allocated tx_info ring at addr:%p size:%d\n",
83 ring
->bounce_buf
= kmalloc_node(MAX_DESC_SIZE
, GFP_KERNEL
, node
);
84 if (!ring
->bounce_buf
) {
85 ring
->bounce_buf
= kmalloc(MAX_DESC_SIZE
, GFP_KERNEL
);
86 if (!ring
->bounce_buf
) {
91 ring
->buf_size
= ALIGN(size
* ring
->stride
, MLX4_EN_PAGE_SIZE
);
93 /* Allocate HW buffers on provided NUMA node */
94 set_dev_node(&mdev
->dev
->pdev
->dev
, node
);
95 err
= mlx4_alloc_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
,
97 set_dev_node(&mdev
->dev
->pdev
->dev
, mdev
->dev
->numa_node
);
99 en_err(priv
, "Failed allocating hwq resources\n");
103 err
= mlx4_en_map_buffer(&ring
->wqres
.buf
);
105 en_err(priv
, "Failed to map TX buffer\n");
109 ring
->buf
= ring
->wqres
.buf
.direct
.buf
;
111 en_dbg(DRV
, priv
, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
112 ring
, ring
->buf
, ring
->size
, ring
->buf_size
,
113 (unsigned long long) ring
->wqres
.buf
.direct
.map
);
116 err
= mlx4_qp_alloc(mdev
->dev
, ring
->qpn
, &ring
->qp
, GFP_KERNEL
);
118 en_err(priv
, "Failed allocating qp %d\n", ring
->qpn
);
121 ring
->qp
.event
= mlx4_en_sqp_event
;
123 err
= mlx4_bf_alloc(mdev
->dev
, &ring
->bf
, node
);
125 en_dbg(DRV
, priv
, "working without blueflame (%d)\n", err
);
126 ring
->bf
.uar
= &mdev
->priv_uar
;
127 ring
->bf
.uar
->map
= mdev
->uar_map
;
128 ring
->bf_enabled
= false;
130 ring
->bf_enabled
= true;
132 ring
->hwtstamp_tx_type
= priv
->hwtstamp_config
.tx_type
;
133 ring
->queue_index
= queue_index
;
135 if (queue_index
< priv
->num_tx_rings_p_up
&& cpu_online(queue_index
))
136 cpumask_set_cpu(queue_index
, &ring
->affinity_mask
);
142 mlx4_en_unmap_buffer(&ring
->wqres
.buf
);
144 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
146 kfree(ring
->bounce_buf
);
147 ring
->bounce_buf
= NULL
;
149 vfree(ring
->tx_info
);
150 ring
->tx_info
= NULL
;
157 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv
*priv
,
158 struct mlx4_en_tx_ring
**pring
)
160 struct mlx4_en_dev
*mdev
= priv
->mdev
;
161 struct mlx4_en_tx_ring
*ring
= *pring
;
162 en_dbg(DRV
, priv
, "Destroying tx ring, qpn: %d\n", ring
->qpn
);
164 if (ring
->bf_enabled
)
165 mlx4_bf_free(mdev
->dev
, &ring
->bf
);
166 mlx4_qp_remove(mdev
->dev
, &ring
->qp
);
167 mlx4_qp_free(mdev
->dev
, &ring
->qp
);
168 mlx4_en_unmap_buffer(&ring
->wqres
.buf
);
169 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
170 kfree(ring
->bounce_buf
);
171 ring
->bounce_buf
= NULL
;
172 vfree(ring
->tx_info
);
173 ring
->tx_info
= NULL
;
178 int mlx4_en_activate_tx_ring(struct mlx4_en_priv
*priv
,
179 struct mlx4_en_tx_ring
*ring
,
180 int cq
, int user_prio
)
182 struct mlx4_en_dev
*mdev
= priv
->mdev
;
187 ring
->cons
= 0xffffffff;
188 ring
->last_nr_txbb
= 1;
190 memset(ring
->tx_info
, 0, ring
->size
* sizeof(struct mlx4_en_tx_info
));
191 memset(ring
->buf
, 0, ring
->buf_size
);
193 ring
->qp_state
= MLX4_QP_STATE_RST
;
194 ring
->doorbell_qpn
= ring
->qp
.qpn
<< 8;
196 mlx4_en_fill_qp_context(priv
, ring
->size
, ring
->stride
, 1, 0, ring
->qpn
,
197 ring
->cqn
, user_prio
, &ring
->context
);
198 if (ring
->bf_enabled
)
199 ring
->context
.usr_page
= cpu_to_be32(ring
->bf
.uar
->index
);
201 err
= mlx4_qp_to_ready(mdev
->dev
, &ring
->wqres
.mtt
, &ring
->context
,
202 &ring
->qp
, &ring
->qp_state
);
203 if (!user_prio
&& cpu_online(ring
->queue_index
))
204 netif_set_xps_queue(priv
->dev
, &ring
->affinity_mask
,
210 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv
*priv
,
211 struct mlx4_en_tx_ring
*ring
)
213 struct mlx4_en_dev
*mdev
= priv
->mdev
;
215 mlx4_qp_modify(mdev
->dev
, NULL
, ring
->qp_state
,
216 MLX4_QP_STATE_RST
, NULL
, 0, 0, &ring
->qp
);
219 static void mlx4_en_stamp_wqe(struct mlx4_en_priv
*priv
,
220 struct mlx4_en_tx_ring
*ring
, int index
,
223 __be32 stamp
= cpu_to_be32(STAMP_VAL
| (!!owner
<< STAMP_SHIFT
));
224 struct mlx4_en_tx_desc
*tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
225 struct mlx4_en_tx_info
*tx_info
= &ring
->tx_info
[index
];
226 void *end
= ring
->buf
+ ring
->buf_size
;
227 __be32
*ptr
= (__be32
*)tx_desc
;
230 /* Optimize the common case when there are no wraparounds */
231 if (likely((void *)tx_desc
+ tx_info
->nr_txbb
* TXBB_SIZE
<= end
)) {
232 /* Stamp the freed descriptor */
233 for (i
= 0; i
< tx_info
->nr_txbb
* TXBB_SIZE
;
239 /* Stamp the freed descriptor */
240 for (i
= 0; i
< tx_info
->nr_txbb
* TXBB_SIZE
;
244 if ((void *)ptr
>= end
) {
246 stamp
^= cpu_to_be32(0x80000000);
253 static u32
mlx4_en_free_tx_desc(struct mlx4_en_priv
*priv
,
254 struct mlx4_en_tx_ring
*ring
,
255 int index
, u8 owner
, u64 timestamp
)
257 struct mlx4_en_dev
*mdev
= priv
->mdev
;
258 struct mlx4_en_tx_info
*tx_info
= &ring
->tx_info
[index
];
259 struct mlx4_en_tx_desc
*tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
260 struct mlx4_wqe_data_seg
*data
= (void *) tx_desc
+ tx_info
->data_offset
;
261 struct sk_buff
*skb
= tx_info
->skb
;
262 struct skb_frag_struct
*frag
;
263 void *end
= ring
->buf
+ ring
->buf_size
;
264 int frags
= skb_shinfo(skb
)->nr_frags
;
266 struct skb_shared_hwtstamps hwts
;
269 mlx4_en_fill_hwtstamps(mdev
, &hwts
, timestamp
);
270 skb_tstamp_tx(skb
, &hwts
);
273 /* Optimize the common case when there are no wraparounds */
274 if (likely((void *) tx_desc
+ tx_info
->nr_txbb
* TXBB_SIZE
<= end
)) {
276 if (tx_info
->linear
) {
277 dma_unmap_single(priv
->ddev
,
278 (dma_addr_t
) be64_to_cpu(data
->addr
),
279 be32_to_cpu(data
->byte_count
),
284 for (i
= 0; i
< frags
; i
++) {
285 frag
= &skb_shinfo(skb
)->frags
[i
];
286 dma_unmap_page(priv
->ddev
,
287 (dma_addr_t
) be64_to_cpu(data
[i
].addr
),
288 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
293 if ((void *) data
>= end
) {
294 data
= ring
->buf
+ ((void *)data
- end
);
297 if (tx_info
->linear
) {
298 dma_unmap_single(priv
->ddev
,
299 (dma_addr_t
) be64_to_cpu(data
->addr
),
300 be32_to_cpu(data
->byte_count
),
305 for (i
= 0; i
< frags
; i
++) {
306 /* Check for wraparound before unmapping */
307 if ((void *) data
>= end
)
309 frag
= &skb_shinfo(skb
)->frags
[i
];
310 dma_unmap_page(priv
->ddev
,
311 (dma_addr_t
) be64_to_cpu(data
->addr
),
312 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
317 dev_kfree_skb_any(skb
);
318 return tx_info
->nr_txbb
;
322 int mlx4_en_free_tx_buf(struct net_device
*dev
, struct mlx4_en_tx_ring
*ring
)
324 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
327 /* Skip last polled descriptor */
328 ring
->cons
+= ring
->last_nr_txbb
;
329 en_dbg(DRV
, priv
, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
330 ring
->cons
, ring
->prod
);
332 if ((u32
) (ring
->prod
- ring
->cons
) > ring
->size
) {
333 if (netif_msg_tx_err(priv
))
334 en_warn(priv
, "Tx consumer passed producer!\n");
338 while (ring
->cons
!= ring
->prod
) {
339 ring
->last_nr_txbb
= mlx4_en_free_tx_desc(priv
, ring
,
340 ring
->cons
& ring
->size_mask
,
341 !!(ring
->cons
& ring
->size
), 0);
342 ring
->cons
+= ring
->last_nr_txbb
;
346 netdev_tx_reset_queue(ring
->tx_queue
);
349 en_dbg(DRV
, priv
, "Freed %d uncompleted tx descriptors\n", cnt
);
354 static int mlx4_en_process_tx_cq(struct net_device
*dev
,
355 struct mlx4_en_cq
*cq
,
358 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
359 struct mlx4_cq
*mcq
= &cq
->mcq
;
360 struct mlx4_en_tx_ring
*ring
= priv
->tx_ring
[cq
->ring
];
361 struct mlx4_cqe
*cqe
;
363 u16 new_index
, ring_index
, stamp_index
;
364 u32 txbbs_skipped
= 0;
366 u32 cons_index
= mcq
->cons_index
;
368 u32 size_mask
= ring
->size_mask
;
369 struct mlx4_cqe
*buf
= cq
->buf
;
372 int factor
= priv
->cqe_factor
;
379 index
= cons_index
& size_mask
;
380 cqe
= &buf
[(index
<< factor
) + factor
];
381 ring_index
= ring
->cons
& size_mask
;
382 stamp_index
= ring_index
;
384 /* Process all completed CQEs */
385 while (XNOR(cqe
->owner_sr_opcode
& MLX4_CQE_OWNER_MASK
,
386 cons_index
& size
) && (done
< budget
)) {
388 * make sure we read the CQE after we read the
393 if (unlikely((cqe
->owner_sr_opcode
& MLX4_CQE_OPCODE_MASK
) ==
394 MLX4_CQE_OPCODE_ERROR
)) {
395 struct mlx4_err_cqe
*cqe_err
= (struct mlx4_err_cqe
*)cqe
;
397 en_err(priv
, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
398 cqe_err
->vendor_err_syndrome
,
402 /* Skip over last polled CQE */
403 new_index
= be16_to_cpu(cqe
->wqe_index
) & size_mask
;
406 txbbs_skipped
+= ring
->last_nr_txbb
;
407 ring_index
= (ring_index
+ ring
->last_nr_txbb
) & size_mask
;
408 if (ring
->tx_info
[ring_index
].ts_requested
)
409 timestamp
= mlx4_en_get_cqe_ts(cqe
);
411 /* free next descriptor */
412 ring
->last_nr_txbb
= mlx4_en_free_tx_desc(
413 priv
, ring
, ring_index
,
414 !!((ring
->cons
+ txbbs_skipped
) &
415 ring
->size
), timestamp
);
417 mlx4_en_stamp_wqe(priv
, ring
, stamp_index
,
418 !!((ring
->cons
+ txbbs_stamp
) &
420 stamp_index
= ring_index
;
421 txbbs_stamp
= txbbs_skipped
;
423 bytes
+= ring
->tx_info
[ring_index
].nr_bytes
;
424 } while ((++done
< budget
) && (ring_index
!= new_index
));
427 index
= cons_index
& size_mask
;
428 cqe
= &buf
[(index
<< factor
) + factor
];
433 * To prevent CQ overflow we first update CQ consumer and only then
436 mcq
->cons_index
= cons_index
;
439 ring
->cons
+= txbbs_skipped
;
440 netdev_tx_completed_queue(ring
->tx_queue
, packets
, bytes
);
443 * Wakeup Tx queue if this stopped, and at least 1 packet
446 if (netif_tx_queue_stopped(ring
->tx_queue
) && txbbs_skipped
> 0) {
447 netif_tx_wake_queue(ring
->tx_queue
);
453 void mlx4_en_tx_irq(struct mlx4_cq
*mcq
)
455 struct mlx4_en_cq
*cq
= container_of(mcq
, struct mlx4_en_cq
, mcq
);
456 struct mlx4_en_priv
*priv
= netdev_priv(cq
->dev
);
459 napi_schedule(&cq
->napi
);
461 mlx4_en_arm_cq(priv
, cq
);
464 /* TX CQ polling - called by NAPI */
465 int mlx4_en_poll_tx_cq(struct napi_struct
*napi
, int budget
)
467 struct mlx4_en_cq
*cq
= container_of(napi
, struct mlx4_en_cq
, napi
);
468 struct net_device
*dev
= cq
->dev
;
469 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
472 done
= mlx4_en_process_tx_cq(dev
, cq
, budget
);
474 /* If we used up all the quota - we're probably not done yet... */
478 mlx4_en_arm_cq(priv
, cq
);
484 static struct mlx4_en_tx_desc
*mlx4_en_bounce_to_desc(struct mlx4_en_priv
*priv
,
485 struct mlx4_en_tx_ring
*ring
,
487 unsigned int desc_size
)
489 u32 copy
= (ring
->size
- index
) * TXBB_SIZE
;
492 for (i
= desc_size
- copy
- 4; i
>= 0; i
-= 4) {
493 if ((i
& (TXBB_SIZE
- 1)) == 0)
496 *((u32
*) (ring
->buf
+ i
)) =
497 *((u32
*) (ring
->bounce_buf
+ copy
+ i
));
500 for (i
= copy
- 4; i
>= 4 ; i
-= 4) {
501 if ((i
& (TXBB_SIZE
- 1)) == 0)
504 *((u32
*) (ring
->buf
+ index
* TXBB_SIZE
+ i
)) =
505 *((u32
*) (ring
->bounce_buf
+ i
));
508 /* Return real descriptor location */
509 return ring
->buf
+ index
* TXBB_SIZE
;
512 static int is_inline(int inline_thold
, struct sk_buff
*skb
, void **pfrag
)
516 if (inline_thold
&& !skb_is_gso(skb
) && skb
->len
<= inline_thold
) {
517 if (skb_shinfo(skb
)->nr_frags
== 1) {
518 ptr
= skb_frag_address_safe(&skb_shinfo(skb
)->frags
[0]);
526 } else if (unlikely(skb_shinfo(skb
)->nr_frags
))
535 static int inline_size(struct sk_buff
*skb
)
537 if (skb
->len
+ CTRL_SIZE
+ sizeof(struct mlx4_wqe_inline_seg
)
538 <= MLX4_INLINE_ALIGN
)
539 return ALIGN(skb
->len
+ CTRL_SIZE
+
540 sizeof(struct mlx4_wqe_inline_seg
), 16);
542 return ALIGN(skb
->len
+ CTRL_SIZE
+ 2 *
543 sizeof(struct mlx4_wqe_inline_seg
), 16);
546 static int get_real_size(struct sk_buff
*skb
, struct net_device
*dev
,
547 int *lso_header_size
)
549 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
552 if (skb_is_gso(skb
)) {
553 if (skb
->encapsulation
)
554 *lso_header_size
= (skb_inner_transport_header(skb
) - skb
->data
) + inner_tcp_hdrlen(skb
);
556 *lso_header_size
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
557 real_size
= CTRL_SIZE
+ skb_shinfo(skb
)->nr_frags
* DS_SIZE
+
558 ALIGN(*lso_header_size
+ 4, DS_SIZE
);
559 if (unlikely(*lso_header_size
!= skb_headlen(skb
))) {
560 /* We add a segment for the skb linear buffer only if
561 * it contains data */
562 if (*lso_header_size
< skb_headlen(skb
))
563 real_size
+= DS_SIZE
;
565 if (netif_msg_tx_err(priv
))
566 en_warn(priv
, "Non-linear headers\n");
571 *lso_header_size
= 0;
572 if (!is_inline(priv
->prof
->inline_thold
, skb
, NULL
))
573 real_size
= CTRL_SIZE
+ (skb_shinfo(skb
)->nr_frags
+ 1) * DS_SIZE
;
575 real_size
= inline_size(skb
);
581 static void build_inline_wqe(struct mlx4_en_tx_desc
*tx_desc
, struct sk_buff
*skb
,
582 int real_size
, u16
*vlan_tag
, int tx_ind
, void *fragptr
)
584 struct mlx4_wqe_inline_seg
*inl
= &tx_desc
->inl
;
585 int spc
= MLX4_INLINE_ALIGN
- CTRL_SIZE
- sizeof *inl
;
587 if (skb
->len
<= spc
) {
588 if (likely(skb
->len
>= MIN_PKT_LEN
)) {
589 inl
->byte_count
= cpu_to_be32(1 << 31 | skb
->len
);
591 inl
->byte_count
= cpu_to_be32(1 << 31 | MIN_PKT_LEN
);
592 memset(((void *)(inl
+ 1)) + skb
->len
, 0,
593 MIN_PKT_LEN
- skb
->len
);
595 skb_copy_from_linear_data(skb
, inl
+ 1, skb_headlen(skb
));
596 if (skb_shinfo(skb
)->nr_frags
)
597 memcpy(((void *)(inl
+ 1)) + skb_headlen(skb
), fragptr
,
598 skb_frag_size(&skb_shinfo(skb
)->frags
[0]));
601 inl
->byte_count
= cpu_to_be32(1 << 31 | spc
);
602 if (skb_headlen(skb
) <= spc
) {
603 skb_copy_from_linear_data(skb
, inl
+ 1, skb_headlen(skb
));
604 if (skb_headlen(skb
) < spc
) {
605 memcpy(((void *)(inl
+ 1)) + skb_headlen(skb
),
606 fragptr
, spc
- skb_headlen(skb
));
607 fragptr
+= spc
- skb_headlen(skb
);
609 inl
= (void *) (inl
+ 1) + spc
;
610 memcpy(((void *)(inl
+ 1)), fragptr
, skb
->len
- spc
);
612 skb_copy_from_linear_data(skb
, inl
+ 1, spc
);
613 inl
= (void *) (inl
+ 1) + spc
;
614 skb_copy_from_linear_data_offset(skb
, spc
, inl
+ 1,
615 skb_headlen(skb
) - spc
);
616 if (skb_shinfo(skb
)->nr_frags
)
617 memcpy(((void *)(inl
+ 1)) + skb_headlen(skb
) - spc
,
618 fragptr
, skb_frag_size(&skb_shinfo(skb
)->frags
[0]));
622 inl
->byte_count
= cpu_to_be32(1 << 31 | (skb
->len
- spc
));
626 u16
mlx4_en_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
627 void *accel_priv
, select_queue_fallback_t fallback
)
629 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
630 u16 rings_p_up
= priv
->num_tx_rings_p_up
;
634 return skb_tx_hash(dev
, skb
);
636 if (vlan_tx_tag_present(skb
))
637 up
= vlan_tx_tag_get(skb
) >> VLAN_PRIO_SHIFT
;
639 return fallback(dev
, skb
) % rings_p_up
+ up
* rings_p_up
;
642 static void mlx4_bf_copy(void __iomem
*dst
, unsigned long *src
, unsigned bytecnt
)
644 __iowrite64_copy(dst
, src
, bytecnt
/ 8);
647 netdev_tx_t
mlx4_en_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
649 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
650 struct mlx4_en_dev
*mdev
= priv
->mdev
;
651 struct device
*ddev
= priv
->ddev
;
652 struct mlx4_en_tx_ring
*ring
;
653 struct mlx4_en_tx_desc
*tx_desc
;
654 struct mlx4_wqe_data_seg
*data
;
655 struct mlx4_en_tx_info
*tx_info
;
671 real_size
= get_real_size(skb
, dev
, &lso_header_size
);
672 if (unlikely(!real_size
))
675 /* Align descriptor to TXBB size */
676 desc_size
= ALIGN(real_size
, TXBB_SIZE
);
677 nr_txbb
= desc_size
/ TXBB_SIZE
;
678 if (unlikely(nr_txbb
> MAX_DESC_TXBBS
)) {
679 if (netif_msg_tx_err(priv
))
680 en_warn(priv
, "Oversized header or SG list\n");
684 tx_ind
= skb
->queue_mapping
;
685 ring
= priv
->tx_ring
[tx_ind
];
686 if (vlan_tx_tag_present(skb
))
687 vlan_tag
= vlan_tx_tag_get(skb
);
689 /* Check available TXBBs And 2K spare for prefetch */
690 if (unlikely(((int)(ring
->prod
- ring
->cons
)) >
691 ring
->size
- HEADROOM
- MAX_DESC_TXBBS
)) {
692 /* every full Tx ring stops queue */
693 netif_tx_stop_queue(ring
->tx_queue
);
694 ring
->queue_stopped
++;
696 /* If queue was emptied after the if, and before the
697 * stop_queue - need to wake the queue, or else it will remain
699 * Need a memory barrier to make sure ring->cons was not
700 * updated before queue was stopped.
704 if (unlikely(((int)(ring
->prod
- ring
->cons
)) <=
705 ring
->size
- HEADROOM
- MAX_DESC_TXBBS
)) {
706 netif_tx_wake_queue(ring
->tx_queue
);
709 return NETDEV_TX_BUSY
;
713 /* Track current inflight packets for performance analysis */
714 AVG_PERF_COUNTER(priv
->pstats
.inflight_avg
,
715 (u32
) (ring
->prod
- ring
->cons
- 1));
717 /* Packet is good - grab an index and transmit it */
718 index
= ring
->prod
& ring
->size_mask
;
719 bf_index
= ring
->prod
;
721 /* See if we have enough space for whole descriptor TXBB for setting
722 * SW ownership on next descriptor; if not, use a bounce buffer. */
723 if (likely(index
+ nr_txbb
<= ring
->size
))
724 tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
726 tx_desc
= (struct mlx4_en_tx_desc
*) ring
->bounce_buf
;
730 /* Save skb in tx_info ring */
731 tx_info
= &ring
->tx_info
[index
];
733 tx_info
->nr_txbb
= nr_txbb
;
736 data
= ((void *)&tx_desc
->lso
+ ALIGN(lso_header_size
+ 4,
739 data
= &tx_desc
->data
;
741 /* valid only for none inline segments */
742 tx_info
->data_offset
= (void *)data
- (void *)tx_desc
;
744 tx_info
->linear
= (lso_header_size
< skb_headlen(skb
) &&
745 !is_inline(ring
->inline_thold
, skb
, NULL
)) ? 1 : 0;
747 data
+= skb_shinfo(skb
)->nr_frags
+ tx_info
->linear
- 1;
749 if (is_inline(ring
->inline_thold
, skb
, &fragptr
)) {
753 for (i
= skb_shinfo(skb
)->nr_frags
- 1; i
>= 0; i
--) {
754 struct skb_frag_struct
*frag
;
757 frag
= &skb_shinfo(skb
)->frags
[i
];
758 dma
= skb_frag_dma_map(ddev
, frag
,
759 0, skb_frag_size(frag
),
761 if (dma_mapping_error(ddev
, dma
))
764 data
->addr
= cpu_to_be64(dma
);
765 data
->lkey
= cpu_to_be32(mdev
->mr
.key
);
767 data
->byte_count
= cpu_to_be32(skb_frag_size(frag
));
771 /* Map linear part */
772 if (tx_info
->linear
) {
773 u32 byte_count
= skb_headlen(skb
) - lso_header_size
;
776 dma
= dma_map_single(ddev
, skb
->data
+
777 lso_header_size
, byte_count
,
779 if (dma_mapping_error(ddev
, dma
))
782 data
->addr
= cpu_to_be64(dma
);
783 data
->lkey
= cpu_to_be32(mdev
->mr
.key
);
785 data
->byte_count
= cpu_to_be32(byte_count
);
791 * For timestamping add flag to skb_shinfo and
792 * set flag for further reference
794 if (ring
->hwtstamp_tx_type
== HWTSTAMP_TX_ON
&&
795 skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) {
796 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
797 tx_info
->ts_requested
= 1;
800 /* Prepare ctrl segement apart opcode+ownership, which depends on
801 * whether LSO is used */
802 tx_desc
->ctrl
.vlan_tag
= cpu_to_be16(vlan_tag
);
803 tx_desc
->ctrl
.ins_vlan
= MLX4_WQE_CTRL_INS_VLAN
*
804 !!vlan_tx_tag_present(skb
);
805 tx_desc
->ctrl
.fence_size
= (real_size
/ 16) & 0x3f;
806 tx_desc
->ctrl
.srcrb_flags
= priv
->ctrl_flags
;
807 if (likely(skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
808 tx_desc
->ctrl
.srcrb_flags
|= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
|
809 MLX4_WQE_CTRL_TCP_UDP_CSUM
);
813 if (priv
->flags
& MLX4_EN_FLAG_ENABLE_HW_LOOPBACK
) {
816 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
817 * so that VFs and PF can communicate with each other
819 ethh
= (struct ethhdr
*)skb
->data
;
820 tx_desc
->ctrl
.srcrb_flags16
[0] = get_unaligned((__be16
*)ethh
->h_dest
);
821 tx_desc
->ctrl
.imm
= get_unaligned((__be32
*)(ethh
->h_dest
+ 2));
824 /* Handle LSO (TSO) packets */
825 if (lso_header_size
) {
826 /* Mark opcode as LSO */
827 op_own
= cpu_to_be32(MLX4_OPCODE_LSO
| (1 << 6)) |
828 ((ring
->prod
& ring
->size
) ?
829 cpu_to_be32(MLX4_EN_BIT_DESC_OWN
) : 0);
831 /* Fill in the LSO prefix */
832 tx_desc
->lso
.mss_hdr_size
= cpu_to_be32(
833 skb_shinfo(skb
)->gso_size
<< 16 | lso_header_size
);
836 * note that we already verified that it is linear */
837 memcpy(tx_desc
->lso
.header
, skb
->data
, lso_header_size
);
839 priv
->port_stats
.tso_packets
++;
840 i
= ((skb
->len
- lso_header_size
) / skb_shinfo(skb
)->gso_size
) +
841 !!((skb
->len
- lso_header_size
) % skb_shinfo(skb
)->gso_size
);
842 tx_info
->nr_bytes
= skb
->len
+ (i
- 1) * lso_header_size
;
845 /* Normal (Non LSO) packet */
846 op_own
= cpu_to_be32(MLX4_OPCODE_SEND
) |
847 ((ring
->prod
& ring
->size
) ?
848 cpu_to_be32(MLX4_EN_BIT_DESC_OWN
) : 0);
849 tx_info
->nr_bytes
= max_t(unsigned int, skb
->len
, ETH_ZLEN
);
853 ring
->bytes
+= tx_info
->nr_bytes
;
854 netdev_tx_sent_queue(ring
->tx_queue
, tx_info
->nr_bytes
);
855 AVG_PERF_COUNTER(priv
->pstats
.tx_pktsz_avg
, skb
->len
);
858 build_inline_wqe(tx_desc
, skb
, real_size
, &vlan_tag
, tx_ind
, fragptr
);
862 if (skb
->encapsulation
) {
863 struct iphdr
*ipv4
= (struct iphdr
*)skb_inner_network_header(skb
);
864 if (ipv4
->protocol
== IPPROTO_TCP
|| ipv4
->protocol
== IPPROTO_UDP
)
865 op_own
|= cpu_to_be32(MLX4_WQE_CTRL_IIP
| MLX4_WQE_CTRL_ILP
);
867 op_own
|= cpu_to_be32(MLX4_WQE_CTRL_IIP
);
870 ring
->prod
+= nr_txbb
;
872 /* If we used a bounce buffer then copy descriptor back into place */
874 tx_desc
= mlx4_en_bounce_to_desc(priv
, ring
, index
, desc_size
);
876 skb_tx_timestamp(skb
);
878 if (ring
->bf_enabled
&& desc_size
<= MAX_BF
&& !bounce
&& !vlan_tx_tag_present(skb
)) {
879 tx_desc
->ctrl
.bf_qpn
|= cpu_to_be32(ring
->doorbell_qpn
);
881 op_own
|= htonl((bf_index
& 0xffff) << 8);
882 /* Ensure new descirptor hits memory
883 * before setting ownership of this descriptor to HW */
885 tx_desc
->ctrl
.owner_opcode
= op_own
;
889 mlx4_bf_copy(ring
->bf
.reg
+ ring
->bf
.offset
, (unsigned long *) &tx_desc
->ctrl
,
894 ring
->bf
.offset
^= ring
->bf
.buf_size
;
896 /* Ensure new descirptor hits memory
897 * before setting ownership of this descriptor to HW */
899 tx_desc
->ctrl
.owner_opcode
= op_own
;
901 iowrite32be(ring
->doorbell_qpn
, ring
->bf
.uar
->map
+ MLX4_SEND_DOORBELL
);
907 en_err(priv
, "DMA mapping error\n");
909 for (i
++; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
911 dma_unmap_page(ddev
, (dma_addr_t
) be64_to_cpu(data
->addr
),
912 be32_to_cpu(data
->byte_count
),
917 dev_kfree_skb_any(skb
);
918 priv
->stats
.tx_dropped
++;