]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/net/ethernet/mellanox/mlx4/eq.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / eq.c
1 /*
2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/mm.h>
39 #include <linux/dma-mapping.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/cpu_rmap.h>
43
44 #include "mlx4.h"
45 #include "fw.h"
46
47 enum {
48 MLX4_IRQNAME_SIZE = 32
49 };
50
51 enum {
52 MLX4_NUM_ASYNC_EQE = 0x100,
53 MLX4_NUM_SPARE_EQE = 0x80,
54 MLX4_EQ_ENTRY_SIZE = 0x20
55 };
56
57 #define MLX4_EQ_STATUS_OK ( 0 << 28)
58 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
59 #define MLX4_EQ_OWNER_SW ( 0 << 24)
60 #define MLX4_EQ_OWNER_HW ( 1 << 24)
61 #define MLX4_EQ_FLAG_EC ( 1 << 18)
62 #define MLX4_EQ_FLAG_OI ( 1 << 17)
63 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
64 #define MLX4_EQ_STATE_FIRED (10 << 8)
65 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66
67 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
76 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
81 (1ull << MLX4_EVENT_TYPE_CMD) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
85
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
87 {
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
91
92 return async_ev_mask;
93 }
94
95 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
96 {
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
98 req_not << 31),
99 eq->doorbell);
100 /* We still want ordering, just not swabbing, so add a barrier */
101 mb();
102 }
103
104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
105 {
106 unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
107 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
108 }
109
110 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
111 {
112 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
113 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
114 }
115
116 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
117 {
118 struct mlx4_eqe *eqe =
119 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
120 return (!!(eqe->owner & 0x80) ^
121 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
122 eqe : NULL;
123 }
124
125 void mlx4_gen_slave_eqe(struct work_struct *work)
126 {
127 struct mlx4_mfunc_master_ctx *master =
128 container_of(work, struct mlx4_mfunc_master_ctx,
129 slave_event_work);
130 struct mlx4_mfunc *mfunc =
131 container_of(master, struct mlx4_mfunc, master);
132 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
133 struct mlx4_dev *dev = &priv->dev;
134 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
135 struct mlx4_eqe *eqe;
136 u8 slave;
137 int i;
138
139 for (eqe = next_slave_event_eqe(slave_eq); eqe;
140 eqe = next_slave_event_eqe(slave_eq)) {
141 slave = eqe->slave_id;
142
143 /* All active slaves need to receive the event */
144 if (slave == ALL_SLAVES) {
145 for (i = 0; i < dev->num_slaves; i++) {
146 if (i != dev->caps.function &&
147 master->slave_state[i].active)
148 if (mlx4_GEN_EQE(dev, i, eqe))
149 mlx4_warn(dev, "Failed to "
150 " generate event "
151 "for slave %d\n", i);
152 }
153 } else {
154 if (mlx4_GEN_EQE(dev, slave, eqe))
155 mlx4_warn(dev, "Failed to generate event "
156 "for slave %d\n", slave);
157 }
158 ++slave_eq->cons;
159 }
160 }
161
162
163 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
164 {
165 struct mlx4_priv *priv = mlx4_priv(dev);
166 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
167 struct mlx4_eqe *s_eqe;
168 unsigned long flags;
169
170 spin_lock_irqsave(&slave_eq->event_lock, flags);
171 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
172 if ((!!(s_eqe->owner & 0x80)) ^
173 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
174 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
175 "No free EQE on slave events queue\n", slave);
176 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
177 return;
178 }
179
180 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1);
181 s_eqe->slave_id = slave;
182 /* ensure all information is written before setting the ownersip bit */
183 wmb();
184 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
185 ++slave_eq->prod;
186
187 queue_work(priv->mfunc.master.comm_wq,
188 &priv->mfunc.master.slave_event_work);
189 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
190 }
191
192 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
193 struct mlx4_eqe *eqe)
194 {
195 struct mlx4_priv *priv = mlx4_priv(dev);
196 struct mlx4_slave_state *s_slave =
197 &priv->mfunc.master.slave_state[slave];
198
199 if (!s_slave->active) {
200 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
201 return;
202 }
203
204 slave_event(dev, slave, eqe);
205 }
206
207 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
208 {
209 struct mlx4_eqe eqe;
210
211 struct mlx4_priv *priv = mlx4_priv(dev);
212 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
213
214 if (!s_slave->active)
215 return 0;
216
217 memset(&eqe, 0, sizeof eqe);
218
219 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
220 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
221 eqe.event.port_mgmt_change.port = port;
222
223 return mlx4_GEN_EQE(dev, slave, &eqe);
224 }
225 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
226
227 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
228 {
229 struct mlx4_eqe eqe;
230
231 /*don't send if we don't have the that slave */
232 if (dev->num_vfs < slave)
233 return 0;
234 memset(&eqe, 0, sizeof eqe);
235
236 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
237 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
238 eqe.event.port_mgmt_change.port = port;
239
240 return mlx4_GEN_EQE(dev, slave, &eqe);
241 }
242 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
243
244 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
245 u8 port_subtype_change)
246 {
247 struct mlx4_eqe eqe;
248
249 /*don't send if we don't have the that slave */
250 if (dev->num_vfs < slave)
251 return 0;
252 memset(&eqe, 0, sizeof eqe);
253
254 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
255 eqe.subtype = port_subtype_change;
256 eqe.event.port_change.port = cpu_to_be32(port << 28);
257
258 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
259 port_subtype_change, slave, port);
260 return mlx4_GEN_EQE(dev, slave, &eqe);
261 }
262 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
263
264 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
265 {
266 struct mlx4_priv *priv = mlx4_priv(dev);
267 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
268 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) {
269 pr_err("%s: Error: asking for slave:%d, port:%d\n",
270 __func__, slave, port);
271 return SLAVE_PORT_DOWN;
272 }
273 return s_state[slave].port_state[port];
274 }
275 EXPORT_SYMBOL(mlx4_get_slave_port_state);
276
277 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
278 enum slave_port_state state)
279 {
280 struct mlx4_priv *priv = mlx4_priv(dev);
281 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
282
283 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
284 pr_err("%s: Error: asking for slave:%d, port:%d\n",
285 __func__, slave, port);
286 return -1;
287 }
288 s_state[slave].port_state[port] = state;
289
290 return 0;
291 }
292
293 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
294 {
295 int i;
296 enum slave_port_gen_event gen_event;
297
298 for (i = 0; i < dev->num_slaves; i++)
299 set_and_calc_slave_port_state(dev, i, port, event, &gen_event);
300 }
301 /**************************************************************************
302 The function get as input the new event to that port,
303 and according to the prev state change the slave's port state.
304 The events are:
305 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
306 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
307 MLX4_PORT_STATE_IB_EVENT_GID_VALID
308 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
309 ***************************************************************************/
310 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
311 u8 port, int event,
312 enum slave_port_gen_event *gen_event)
313 {
314 struct mlx4_priv *priv = mlx4_priv(dev);
315 struct mlx4_slave_state *ctx = NULL;
316 unsigned long flags;
317 int ret = -1;
318 enum slave_port_state cur_state =
319 mlx4_get_slave_port_state(dev, slave, port);
320
321 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
322
323 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
324 pr_err("%s: Error: asking for slave:%d, port:%d\n",
325 __func__, slave, port);
326 return ret;
327 }
328
329 ctx = &priv->mfunc.master.slave_state[slave];
330 spin_lock_irqsave(&ctx->lock, flags);
331
332 mlx4_dbg(dev, "%s: slave: %d, current state: %d new event :%d\n",
333 __func__, slave, cur_state, event);
334
335 switch (cur_state) {
336 case SLAVE_PORT_DOWN:
337 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
338 mlx4_set_slave_port_state(dev, slave, port,
339 SLAVE_PENDING_UP);
340 break;
341 case SLAVE_PENDING_UP:
342 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
343 mlx4_set_slave_port_state(dev, slave, port,
344 SLAVE_PORT_DOWN);
345 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
346 mlx4_set_slave_port_state(dev, slave, port,
347 SLAVE_PORT_UP);
348 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
349 }
350 break;
351 case SLAVE_PORT_UP:
352 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
353 mlx4_set_slave_port_state(dev, slave, port,
354 SLAVE_PORT_DOWN);
355 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
356 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
357 event) {
358 mlx4_set_slave_port_state(dev, slave, port,
359 SLAVE_PENDING_UP);
360 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
361 }
362 break;
363 default:
364 pr_err("%s: BUG!!! UNKNOWN state: "
365 "slave:%d, port:%d\n", __func__, slave, port);
366 goto out;
367 }
368 ret = mlx4_get_slave_port_state(dev, slave, port);
369 mlx4_dbg(dev, "%s: slave: %d, current state: %d new event"
370 " :%d gen_event: %d\n",
371 __func__, slave, cur_state, event, *gen_event);
372
373 out:
374 spin_unlock_irqrestore(&ctx->lock, flags);
375 return ret;
376 }
377
378 EXPORT_SYMBOL(set_and_calc_slave_port_state);
379
380 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
381 {
382 struct mlx4_eqe eqe;
383
384 memset(&eqe, 0, sizeof eqe);
385
386 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
387 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
388 eqe.event.port_mgmt_change.port = port;
389 eqe.event.port_mgmt_change.params.port_info.changed_attr =
390 cpu_to_be32((u32) attr);
391
392 slave_event(dev, ALL_SLAVES, &eqe);
393 return 0;
394 }
395 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
396
397 void mlx4_master_handle_slave_flr(struct work_struct *work)
398 {
399 struct mlx4_mfunc_master_ctx *master =
400 container_of(work, struct mlx4_mfunc_master_ctx,
401 slave_flr_event_work);
402 struct mlx4_mfunc *mfunc =
403 container_of(master, struct mlx4_mfunc, master);
404 struct mlx4_priv *priv =
405 container_of(mfunc, struct mlx4_priv, mfunc);
406 struct mlx4_dev *dev = &priv->dev;
407 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
408 int i;
409 int err;
410
411 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
412
413 for (i = 0 ; i < dev->num_slaves; i++) {
414
415 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
416 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
417 "clean slave: %d\n", i);
418
419 mlx4_delete_all_resources_for_slave(dev, i);
420 /*return the slave to running mode*/
421 spin_lock(&priv->mfunc.master.slave_state_lock);
422 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
423 slave_state[i].is_slave_going_down = 0;
424 spin_unlock(&priv->mfunc.master.slave_state_lock);
425 /*notify the FW:*/
426 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
427 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
428 if (err)
429 mlx4_warn(dev, "Failed to notify FW on "
430 "FLR done (slave:%d)\n", i);
431 }
432 }
433 }
434
435 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
436 {
437 struct mlx4_priv *priv = mlx4_priv(dev);
438 struct mlx4_eqe *eqe;
439 int cqn;
440 int eqes_found = 0;
441 int set_ci = 0;
442 int port;
443 int slave = 0;
444 int ret;
445 u32 flr_slave;
446 u8 update_slave_state;
447 int i;
448 enum slave_port_gen_event gen_event;
449
450 while ((eqe = next_eqe_sw(eq))) {
451 /*
452 * Make sure we read EQ entry contents after we've
453 * checked the ownership bit.
454 */
455 rmb();
456
457 switch (eqe->type) {
458 case MLX4_EVENT_TYPE_COMP:
459 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
460 mlx4_cq_completion(dev, cqn);
461 break;
462
463 case MLX4_EVENT_TYPE_PATH_MIG:
464 case MLX4_EVENT_TYPE_COMM_EST:
465 case MLX4_EVENT_TYPE_SQ_DRAINED:
466 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
467 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
468 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
469 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
470 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
471 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
472 if (mlx4_is_master(dev)) {
473 /* forward only to slave owning the QP */
474 ret = mlx4_get_slave_from_resource_id(dev,
475 RES_QP,
476 be32_to_cpu(eqe->event.qp.qpn)
477 & 0xffffff, &slave);
478 if (ret && ret != -ENOENT) {
479 mlx4_dbg(dev, "QP event %02x(%02x) on "
480 "EQ %d at index %u: could "
481 "not get slave id (%d)\n",
482 eqe->type, eqe->subtype,
483 eq->eqn, eq->cons_index, ret);
484 break;
485 }
486
487 if (!ret && slave != dev->caps.function) {
488 mlx4_slave_event(dev, slave, eqe);
489 break;
490 }
491
492 }
493 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
494 0xffffff, eqe->type);
495 break;
496
497 case MLX4_EVENT_TYPE_SRQ_LIMIT:
498 mlx4_warn(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
499 __func__);
500 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
501 if (mlx4_is_master(dev)) {
502 /* forward only to slave owning the SRQ */
503 ret = mlx4_get_slave_from_resource_id(dev,
504 RES_SRQ,
505 be32_to_cpu(eqe->event.srq.srqn)
506 & 0xffffff,
507 &slave);
508 if (ret && ret != -ENOENT) {
509 mlx4_warn(dev, "SRQ event %02x(%02x) "
510 "on EQ %d at index %u: could"
511 " not get slave id (%d)\n",
512 eqe->type, eqe->subtype,
513 eq->eqn, eq->cons_index, ret);
514 break;
515 }
516 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
517 " event: %02x(%02x)\n", __func__,
518 slave,
519 be32_to_cpu(eqe->event.srq.srqn),
520 eqe->type, eqe->subtype);
521
522 if (!ret && slave != dev->caps.function) {
523 mlx4_warn(dev, "%s: sending event "
524 "%02x(%02x) to slave:%d\n",
525 __func__, eqe->type,
526 eqe->subtype, slave);
527 mlx4_slave_event(dev, slave, eqe);
528 break;
529 }
530 }
531 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
532 0xffffff, eqe->type);
533 break;
534
535 case MLX4_EVENT_TYPE_CMD:
536 mlx4_cmd_event(dev,
537 be16_to_cpu(eqe->event.cmd.token),
538 eqe->event.cmd.status,
539 be64_to_cpu(eqe->event.cmd.out_param));
540 break;
541
542 case MLX4_EVENT_TYPE_PORT_CHANGE:
543 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
544 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
545 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
546 port);
547 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
548 if (!mlx4_is_master(dev))
549 break;
550 for (i = 0; i < dev->num_slaves; i++) {
551 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
552 if (i == mlx4_master_func_num(dev))
553 continue;
554 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
555 " to slave: %d, port:%d\n",
556 __func__, i, port);
557 mlx4_slave_event(dev, i, eqe);
558 } else { /* IB port */
559 set_and_calc_slave_port_state(dev, i, port,
560 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
561 &gen_event);
562 /*we can be in pending state, then do not send port_down event*/
563 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
564 if (i == mlx4_master_func_num(dev))
565 continue;
566 mlx4_slave_event(dev, i, eqe);
567 }
568 }
569 }
570 } else {
571 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
572
573 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
574
575 if (!mlx4_is_master(dev))
576 break;
577 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
578 for (i = 0; i < dev->num_slaves; i++) {
579 if (i == mlx4_master_func_num(dev))
580 continue;
581 mlx4_slave_event(dev, i, eqe);
582 }
583 else /* IB port */
584 /* port-up event will be sent to a slave when the
585 * slave's alias-guid is set. This is done in alias_GUID.c
586 */
587 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
588 }
589 break;
590
591 case MLX4_EVENT_TYPE_CQ_ERROR:
592 mlx4_warn(dev, "CQ %s on CQN %06x\n",
593 eqe->event.cq_err.syndrome == 1 ?
594 "overrun" : "access violation",
595 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
596 if (mlx4_is_master(dev)) {
597 ret = mlx4_get_slave_from_resource_id(dev,
598 RES_CQ,
599 be32_to_cpu(eqe->event.cq_err.cqn)
600 & 0xffffff, &slave);
601 if (ret && ret != -ENOENT) {
602 mlx4_dbg(dev, "CQ event %02x(%02x) on "
603 "EQ %d at index %u: could "
604 "not get slave id (%d)\n",
605 eqe->type, eqe->subtype,
606 eq->eqn, eq->cons_index, ret);
607 break;
608 }
609
610 if (!ret && slave != dev->caps.function) {
611 mlx4_slave_event(dev, slave, eqe);
612 break;
613 }
614 }
615 mlx4_cq_event(dev,
616 be32_to_cpu(eqe->event.cq_err.cqn)
617 & 0xffffff,
618 eqe->type);
619 break;
620
621 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
622 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
623 break;
624
625 case MLX4_EVENT_TYPE_COMM_CHANNEL:
626 if (!mlx4_is_master(dev)) {
627 mlx4_warn(dev, "Received comm channel event "
628 "for non master device\n");
629 break;
630 }
631 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
632 eqe->event.comm_channel_arm.bit_vec,
633 sizeof eqe->event.comm_channel_arm.bit_vec);
634 queue_work(priv->mfunc.master.comm_wq,
635 &priv->mfunc.master.comm_work);
636 break;
637
638 case MLX4_EVENT_TYPE_FLR_EVENT:
639 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
640 if (!mlx4_is_master(dev)) {
641 mlx4_warn(dev, "Non-master function received"
642 "FLR event\n");
643 break;
644 }
645
646 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
647
648 if (flr_slave >= dev->num_slaves) {
649 mlx4_warn(dev,
650 "Got FLR for unknown function: %d\n",
651 flr_slave);
652 update_slave_state = 0;
653 } else
654 update_slave_state = 1;
655
656 spin_lock(&priv->mfunc.master.slave_state_lock);
657 if (update_slave_state) {
658 priv->mfunc.master.slave_state[flr_slave].active = false;
659 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
660 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
661 }
662 spin_unlock(&priv->mfunc.master.slave_state_lock);
663 queue_work(priv->mfunc.master.comm_wq,
664 &priv->mfunc.master.slave_flr_event_work);
665 break;
666
667 case MLX4_EVENT_TYPE_FATAL_WARNING:
668 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
669 if (mlx4_is_master(dev))
670 for (i = 0; i < dev->num_slaves; i++) {
671 mlx4_dbg(dev, "%s: Sending "
672 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
673 " to slave: %d\n", __func__, i);
674 if (i == dev->caps.function)
675 continue;
676 mlx4_slave_event(dev, i, eqe);
677 }
678 mlx4_err(dev, "Temperature Threshold was reached! "
679 "Threshold: %d celsius degrees; "
680 "Current Temperature: %d\n",
681 be16_to_cpu(eqe->event.warming.warning_threshold),
682 be16_to_cpu(eqe->event.warming.current_temperature));
683 } else
684 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
685 "subtype %02x on EQ %d at index %u. owner=%x, "
686 "nent=0x%x, slave=%x, ownership=%s\n",
687 eqe->type, eqe->subtype, eq->eqn,
688 eq->cons_index, eqe->owner, eq->nent,
689 eqe->slave_id,
690 !!(eqe->owner & 0x80) ^
691 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
692
693 break;
694
695 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
696 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
697 (unsigned long) eqe);
698 break;
699
700 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
701 case MLX4_EVENT_TYPE_ECC_DETECT:
702 default:
703 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
704 "index %u. owner=%x, nent=0x%x, slave=%x, "
705 "ownership=%s\n",
706 eqe->type, eqe->subtype, eq->eqn,
707 eq->cons_index, eqe->owner, eq->nent,
708 eqe->slave_id,
709 !!(eqe->owner & 0x80) ^
710 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
711 break;
712 };
713
714 ++eq->cons_index;
715 eqes_found = 1;
716 ++set_ci;
717
718 /*
719 * The HCA will think the queue has overflowed if we
720 * don't tell it we've been processing events. We
721 * create our EQs with MLX4_NUM_SPARE_EQE extra
722 * entries, so we must update our consumer index at
723 * least that often.
724 */
725 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
726 eq_set_ci(eq, 0);
727 set_ci = 0;
728 }
729 }
730
731 eq_set_ci(eq, 1);
732
733 return eqes_found;
734 }
735
736 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
737 {
738 struct mlx4_dev *dev = dev_ptr;
739 struct mlx4_priv *priv = mlx4_priv(dev);
740 int work = 0;
741 int i;
742
743 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
744
745 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
746 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
747
748 return IRQ_RETVAL(work);
749 }
750
751 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
752 {
753 struct mlx4_eq *eq = eq_ptr;
754 struct mlx4_dev *dev = eq->dev;
755
756 mlx4_eq_int(dev, eq);
757
758 /* MSI-X vectors always belong to us */
759 return IRQ_HANDLED;
760 }
761
762 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
763 struct mlx4_vhcr *vhcr,
764 struct mlx4_cmd_mailbox *inbox,
765 struct mlx4_cmd_mailbox *outbox,
766 struct mlx4_cmd_info *cmd)
767 {
768 struct mlx4_priv *priv = mlx4_priv(dev);
769 struct mlx4_slave_event_eq_info *event_eq =
770 priv->mfunc.master.slave_state[slave].event_eq;
771 u32 in_modifier = vhcr->in_modifier;
772 u32 eqn = in_modifier & 0x1FF;
773 u64 in_param = vhcr->in_param;
774 int err = 0;
775 int i;
776
777 if (slave == dev->caps.function)
778 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
779 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
780 MLX4_CMD_NATIVE);
781 if (!err)
782 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
783 if (in_param & (1LL << i))
784 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
785
786 return err;
787 }
788
789 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
790 int eq_num)
791 {
792 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
793 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
794 MLX4_CMD_WRAPPED);
795 }
796
797 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
798 int eq_num)
799 {
800 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
801 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
802 MLX4_CMD_WRAPPED);
803 }
804
805 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
806 int eq_num)
807 {
808 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
809 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
810 MLX4_CMD_WRAPPED);
811 }
812
813 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
814 {
815 /*
816 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
817 * we need to map, take the difference of highest index and
818 * the lowest index we'll use and add 1.
819 */
820 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
821 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
822 }
823
824 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
825 {
826 struct mlx4_priv *priv = mlx4_priv(dev);
827 int index;
828
829 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
830
831 if (!priv->eq_table.uar_map[index]) {
832 priv->eq_table.uar_map[index] =
833 ioremap(pci_resource_start(dev->pdev, 2) +
834 ((eq->eqn / 4) << PAGE_SHIFT),
835 PAGE_SIZE);
836 if (!priv->eq_table.uar_map[index]) {
837 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
838 eq->eqn);
839 return NULL;
840 }
841 }
842
843 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
844 }
845
846 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
847 u8 intr, struct mlx4_eq *eq)
848 {
849 struct mlx4_priv *priv = mlx4_priv(dev);
850 struct mlx4_cmd_mailbox *mailbox;
851 struct mlx4_eq_context *eq_context;
852 int npages;
853 u64 *dma_list = NULL;
854 dma_addr_t t;
855 u64 mtt_addr;
856 int err = -ENOMEM;
857 int i;
858
859 eq->dev = dev;
860 eq->nent = roundup_pow_of_two(max(nent, 2));
861 npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
862
863 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
864 GFP_KERNEL);
865 if (!eq->page_list)
866 goto err_out;
867
868 for (i = 0; i < npages; ++i)
869 eq->page_list[i].buf = NULL;
870
871 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
872 if (!dma_list)
873 goto err_out_free;
874
875 mailbox = mlx4_alloc_cmd_mailbox(dev);
876 if (IS_ERR(mailbox))
877 goto err_out_free;
878 eq_context = mailbox->buf;
879
880 for (i = 0; i < npages; ++i) {
881 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
882 PAGE_SIZE, &t, GFP_KERNEL);
883 if (!eq->page_list[i].buf)
884 goto err_out_free_pages;
885
886 dma_list[i] = t;
887 eq->page_list[i].map = t;
888
889 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
890 }
891
892 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
893 if (eq->eqn == -1)
894 goto err_out_free_pages;
895
896 eq->doorbell = mlx4_get_eq_uar(dev, eq);
897 if (!eq->doorbell) {
898 err = -ENOMEM;
899 goto err_out_free_eq;
900 }
901
902 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
903 if (err)
904 goto err_out_free_eq;
905
906 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
907 if (err)
908 goto err_out_free_mtt;
909
910 memset(eq_context, 0, sizeof *eq_context);
911 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
912 MLX4_EQ_STATE_ARMED);
913 eq_context->log_eq_size = ilog2(eq->nent);
914 eq_context->intr = intr;
915 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
916
917 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
918 eq_context->mtt_base_addr_h = mtt_addr >> 32;
919 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
920
921 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
922 if (err) {
923 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
924 goto err_out_free_mtt;
925 }
926
927 kfree(dma_list);
928 mlx4_free_cmd_mailbox(dev, mailbox);
929
930 eq->cons_index = 0;
931
932 return err;
933
934 err_out_free_mtt:
935 mlx4_mtt_cleanup(dev, &eq->mtt);
936
937 err_out_free_eq:
938 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
939
940 err_out_free_pages:
941 for (i = 0; i < npages; ++i)
942 if (eq->page_list[i].buf)
943 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
944 eq->page_list[i].buf,
945 eq->page_list[i].map);
946
947 mlx4_free_cmd_mailbox(dev, mailbox);
948
949 err_out_free:
950 kfree(eq->page_list);
951 kfree(dma_list);
952
953 err_out:
954 return err;
955 }
956
957 static void mlx4_free_eq(struct mlx4_dev *dev,
958 struct mlx4_eq *eq)
959 {
960 struct mlx4_priv *priv = mlx4_priv(dev);
961 struct mlx4_cmd_mailbox *mailbox;
962 int err;
963 int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
964 int i;
965
966 mailbox = mlx4_alloc_cmd_mailbox(dev);
967 if (IS_ERR(mailbox))
968 return;
969
970 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
971 if (err)
972 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
973
974 if (0) {
975 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
976 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
977 if (i % 4 == 0)
978 pr_cont("[%02x] ", i * 4);
979 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
980 if ((i + 1) % 4 == 0)
981 pr_cont("\n");
982 }
983 }
984
985 mlx4_mtt_cleanup(dev, &eq->mtt);
986 for (i = 0; i < npages; ++i)
987 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
988 eq->page_list[i].buf,
989 eq->page_list[i].map);
990
991 kfree(eq->page_list);
992 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
993 mlx4_free_cmd_mailbox(dev, mailbox);
994 }
995
996 static void mlx4_free_irqs(struct mlx4_dev *dev)
997 {
998 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
999 struct mlx4_priv *priv = mlx4_priv(dev);
1000 int i, vec;
1001
1002 if (eq_table->have_irq)
1003 free_irq(dev->pdev->irq, dev);
1004
1005 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1006 if (eq_table->eq[i].have_irq) {
1007 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1008 eq_table->eq[i].have_irq = 0;
1009 }
1010
1011 for (i = 0; i < dev->caps.comp_pool; i++) {
1012 /*
1013 * Freeing the assigned irq's
1014 * all bits should be 0, but we need to validate
1015 */
1016 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1017 /* NO need protecting*/
1018 vec = dev->caps.num_comp_vectors + 1 + i;
1019 free_irq(priv->eq_table.eq[vec].irq,
1020 &priv->eq_table.eq[vec]);
1021 }
1022 }
1023
1024
1025 kfree(eq_table->irq_names);
1026 }
1027
1028 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1029 {
1030 struct mlx4_priv *priv = mlx4_priv(dev);
1031
1032 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1033 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1034 if (!priv->clr_base) {
1035 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1036 return -ENOMEM;
1037 }
1038
1039 return 0;
1040 }
1041
1042 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1043 {
1044 struct mlx4_priv *priv = mlx4_priv(dev);
1045
1046 iounmap(priv->clr_base);
1047 }
1048
1049 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1050 {
1051 struct mlx4_priv *priv = mlx4_priv(dev);
1052
1053 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1054 sizeof *priv->eq_table.eq, GFP_KERNEL);
1055 if (!priv->eq_table.eq)
1056 return -ENOMEM;
1057
1058 return 0;
1059 }
1060
1061 void mlx4_free_eq_table(struct mlx4_dev *dev)
1062 {
1063 kfree(mlx4_priv(dev)->eq_table.eq);
1064 }
1065
1066 int mlx4_init_eq_table(struct mlx4_dev *dev)
1067 {
1068 struct mlx4_priv *priv = mlx4_priv(dev);
1069 int err;
1070 int i;
1071
1072 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1073 sizeof *priv->eq_table.uar_map,
1074 GFP_KERNEL);
1075 if (!priv->eq_table.uar_map) {
1076 err = -ENOMEM;
1077 goto err_out_free;
1078 }
1079
1080 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
1081 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
1082 if (err)
1083 goto err_out_free;
1084
1085 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1086 priv->eq_table.uar_map[i] = NULL;
1087
1088 if (!mlx4_is_slave(dev)) {
1089 err = mlx4_map_clr_int(dev);
1090 if (err)
1091 goto err_out_bitmap;
1092
1093 priv->eq_table.clr_mask =
1094 swab32(1 << (priv->eq_table.inta_pin & 31));
1095 priv->eq_table.clr_int = priv->clr_base +
1096 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1097 }
1098
1099 priv->eq_table.irq_names =
1100 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1101 dev->caps.comp_pool),
1102 GFP_KERNEL);
1103 if (!priv->eq_table.irq_names) {
1104 err = -ENOMEM;
1105 goto err_out_bitmap;
1106 }
1107
1108 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1109 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1110 dev->caps.reserved_cqs +
1111 MLX4_NUM_SPARE_EQE,
1112 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1113 &priv->eq_table.eq[i]);
1114 if (err) {
1115 --i;
1116 goto err_out_unmap;
1117 }
1118 }
1119
1120 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1121 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1122 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1123 if (err)
1124 goto err_out_comp;
1125
1126 /*if additional completion vectors poolsize is 0 this loop will not run*/
1127 for (i = dev->caps.num_comp_vectors + 1;
1128 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1129
1130 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1131 dev->caps.reserved_cqs +
1132 MLX4_NUM_SPARE_EQE,
1133 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1134 &priv->eq_table.eq[i]);
1135 if (err) {
1136 --i;
1137 goto err_out_unmap;
1138 }
1139 }
1140
1141
1142 if (dev->flags & MLX4_FLAG_MSI_X) {
1143 const char *eq_name;
1144
1145 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1146 if (i < dev->caps.num_comp_vectors) {
1147 snprintf(priv->eq_table.irq_names +
1148 i * MLX4_IRQNAME_SIZE,
1149 MLX4_IRQNAME_SIZE,
1150 "mlx4-comp-%d@pci:%s", i,
1151 pci_name(dev->pdev));
1152 } else {
1153 snprintf(priv->eq_table.irq_names +
1154 i * MLX4_IRQNAME_SIZE,
1155 MLX4_IRQNAME_SIZE,
1156 "mlx4-async@pci:%s",
1157 pci_name(dev->pdev));
1158 }
1159
1160 eq_name = priv->eq_table.irq_names +
1161 i * MLX4_IRQNAME_SIZE;
1162 err = request_irq(priv->eq_table.eq[i].irq,
1163 mlx4_msi_x_interrupt, 0, eq_name,
1164 priv->eq_table.eq + i);
1165 if (err)
1166 goto err_out_async;
1167
1168 priv->eq_table.eq[i].have_irq = 1;
1169 }
1170 } else {
1171 snprintf(priv->eq_table.irq_names,
1172 MLX4_IRQNAME_SIZE,
1173 DRV_NAME "@pci:%s",
1174 pci_name(dev->pdev));
1175 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1176 IRQF_SHARED, priv->eq_table.irq_names, dev);
1177 if (err)
1178 goto err_out_async;
1179
1180 priv->eq_table.have_irq = 1;
1181 }
1182
1183 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1184 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1185 if (err)
1186 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1187 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1188
1189 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1190 eq_set_ci(&priv->eq_table.eq[i], 1);
1191
1192 return 0;
1193
1194 err_out_async:
1195 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1196
1197 err_out_comp:
1198 i = dev->caps.num_comp_vectors - 1;
1199
1200 err_out_unmap:
1201 while (i >= 0) {
1202 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1203 --i;
1204 }
1205 if (!mlx4_is_slave(dev))
1206 mlx4_unmap_clr_int(dev);
1207 mlx4_free_irqs(dev);
1208
1209 err_out_bitmap:
1210 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1211
1212 err_out_free:
1213 kfree(priv->eq_table.uar_map);
1214
1215 return err;
1216 }
1217
1218 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1219 {
1220 struct mlx4_priv *priv = mlx4_priv(dev);
1221 int i;
1222
1223 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1224 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1225
1226 mlx4_free_irqs(dev);
1227
1228 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1229 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1230
1231 if (!mlx4_is_slave(dev))
1232 mlx4_unmap_clr_int(dev);
1233
1234 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1235 if (priv->eq_table.uar_map[i])
1236 iounmap(priv->eq_table.uar_map[i]);
1237
1238 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1239
1240 kfree(priv->eq_table.uar_map);
1241 }
1242
1243 /* A test that verifies that we can accept interrupts on all
1244 * the irq vectors of the device.
1245 * Interrupts are checked using the NOP command.
1246 */
1247 int mlx4_test_interrupts(struct mlx4_dev *dev)
1248 {
1249 struct mlx4_priv *priv = mlx4_priv(dev);
1250 int i;
1251 int err;
1252
1253 err = mlx4_NOP(dev);
1254 /* When not in MSI_X, there is only one irq to check */
1255 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1256 return err;
1257
1258 /* A loop over all completion vectors, for each vector we will check
1259 * whether it works by mapping command completions to that vector
1260 * and performing a NOP command
1261 */
1262 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1263 /* Temporary use polling for command completions */
1264 mlx4_cmd_use_polling(dev);
1265
1266 /* Map the new eq to handle all asyncronous events */
1267 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1268 priv->eq_table.eq[i].eqn);
1269 if (err) {
1270 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1271 mlx4_cmd_use_events(dev);
1272 break;
1273 }
1274
1275 /* Go back to using events */
1276 mlx4_cmd_use_events(dev);
1277 err = mlx4_NOP(dev);
1278 }
1279
1280 /* Return to default */
1281 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1282 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1283 return err;
1284 }
1285 EXPORT_SYMBOL(mlx4_test_interrupts);
1286
1287 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1288 int *vector)
1289 {
1290
1291 struct mlx4_priv *priv = mlx4_priv(dev);
1292 int vec = 0, err = 0, i;
1293
1294 mutex_lock(&priv->msix_ctl.pool_lock);
1295 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1296 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1297 priv->msix_ctl.pool_bm |= 1ULL << i;
1298 vec = dev->caps.num_comp_vectors + 1 + i;
1299 snprintf(priv->eq_table.irq_names +
1300 vec * MLX4_IRQNAME_SIZE,
1301 MLX4_IRQNAME_SIZE, "%s", name);
1302 #ifdef CONFIG_RFS_ACCEL
1303 if (rmap) {
1304 err = irq_cpu_rmap_add(rmap,
1305 priv->eq_table.eq[vec].irq);
1306 if (err)
1307 mlx4_warn(dev, "Failed adding irq rmap\n");
1308 }
1309 #endif
1310 err = request_irq(priv->eq_table.eq[vec].irq,
1311 mlx4_msi_x_interrupt, 0,
1312 &priv->eq_table.irq_names[vec<<5],
1313 priv->eq_table.eq + vec);
1314 if (err) {
1315 /*zero out bit by fliping it*/
1316 priv->msix_ctl.pool_bm ^= 1 << i;
1317 vec = 0;
1318 continue;
1319 /*we dont want to break here*/
1320 }
1321 eq_set_ci(&priv->eq_table.eq[vec], 1);
1322 }
1323 }
1324 mutex_unlock(&priv->msix_ctl.pool_lock);
1325
1326 if (vec) {
1327 *vector = vec;
1328 } else {
1329 *vector = 0;
1330 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1331 }
1332 return err;
1333 }
1334 EXPORT_SYMBOL(mlx4_assign_eq);
1335
1336 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1337 {
1338 struct mlx4_priv *priv = mlx4_priv(dev);
1339 /*bm index*/
1340 int i = vec - dev->caps.num_comp_vectors - 1;
1341
1342 if (likely(i >= 0)) {
1343 /*sanity check , making sure were not trying to free irq's
1344 Belonging to a legacy EQ*/
1345 mutex_lock(&priv->msix_ctl.pool_lock);
1346 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1347 free_irq(priv->eq_table.eq[vec].irq,
1348 &priv->eq_table.eq[vec]);
1349 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1350 }
1351 mutex_unlock(&priv->msix_ctl.pool_lock);
1352 }
1353
1354 }
1355 EXPORT_SYMBOL(mlx4_release_eq);
1356
ubuntu-zesty-kernel mirror