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mlx4_core: Add proxy and tunnel QPs to the reserved QP area
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "DPDP",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [59] = "Port management change event support",
113 };
114 int i;
115
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
118 if (fname[i] && (flags & (1LL << i)))
119 mlx4_dbg(dev, " %s\n", fname[i]);
120 }
121
122 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
123 {
124 static const char * const fname[] = {
125 [0] = "RSS support",
126 [1] = "RSS Toeplitz Hash Function support",
127 [2] = "RSS XOR Hash Function support",
128 [3] = "Device manage flow steering support"
129 };
130 int i;
131
132 for (i = 0; i < ARRAY_SIZE(fname); ++i)
133 if (fname[i] && (flags & (1LL << i)))
134 mlx4_dbg(dev, " %s\n", fname[i]);
135 }
136
137 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
138 {
139 struct mlx4_cmd_mailbox *mailbox;
140 u32 *inbox;
141 int err = 0;
142
143 #define MOD_STAT_CFG_IN_SIZE 0x100
144
145 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
146 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
147
148 mailbox = mlx4_alloc_cmd_mailbox(dev);
149 if (IS_ERR(mailbox))
150 return PTR_ERR(mailbox);
151 inbox = mailbox->buf;
152
153 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
154
155 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
156 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
157
158 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
159 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
160
161 mlx4_free_cmd_mailbox(dev, mailbox);
162 return err;
163 }
164
165 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
166 struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox,
168 struct mlx4_cmd_mailbox *outbox,
169 struct mlx4_cmd_info *cmd)
170 {
171 u8 field;
172 u32 size;
173 int err = 0;
174
175 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
176 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
177 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
178 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
179 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
180 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
181 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
182 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
183 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
184 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
185 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
186 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
187 #define QUERY_FUNC_CAP_BASE_TUNNEL_QPN_OFFSET 0x44
188 #define QUERY_FUNC_CAP_BASE_PROXY_QPN_OFFSET 0x48
189
190 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
191 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
192 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
193
194 /* when opcode modifier = 1 */
195 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
196 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
197 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
198
199 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
200 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
201
202 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
203
204 if (vhcr->op_modifier == 1) {
205 field = vhcr->in_modifier;
206 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
207
208 field = 0;
209 /* ensure force vlan and force mac bits are not set */
210 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
211 /* ensure that phy_wqe_gid bit is not set */
212 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
213
214 } else if (vhcr->op_modifier == 0) {
215 /* enable rdma and ethernet interfaces */
216 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
217 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
218
219 field = dev->caps.num_ports;
220 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
221
222 size = 0; /* no PF behaviour is set for now */
223 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
224
225 field = 0; /* protected FMR support not available as yet */
226 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
227
228 size = dev->caps.num_qps;
229 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
230
231 size = dev->caps.num_srqs;
232 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
233
234 size = dev->caps.num_cqs;
235 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
236
237 size = dev->caps.num_eqs;
238 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
239
240 size = dev->caps.reserved_eqs;
241 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
242
243 size = dev->caps.num_mpts;
244 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
245
246 size = dev->caps.num_mtts;
247 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
248
249 size = dev->caps.num_mgms + dev->caps.num_amgms;
250 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
251
252 size = dev->caps.base_tunnel_sqpn + 8 * slave;
253 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_BASE_TUNNEL_QPN_OFFSET);
254
255 size = dev->caps.sqp_start + 8 * slave;
256 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_BASE_PROXY_QPN_OFFSET);
257
258 } else
259 err = -EINVAL;
260
261 return err;
262 }
263
264 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
265 {
266 struct mlx4_cmd_mailbox *mailbox;
267 u32 *outbox;
268 u8 field;
269 u32 size;
270 int i;
271 int err = 0;
272
273
274 mailbox = mlx4_alloc_cmd_mailbox(dev);
275 if (IS_ERR(mailbox))
276 return PTR_ERR(mailbox);
277
278 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
279 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
280 if (err)
281 goto out;
282
283 outbox = mailbox->buf;
284
285 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
286 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
287 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
288 err = -EPROTONOSUPPORT;
289 goto out;
290 }
291 func_cap->flags = field;
292
293 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
294 func_cap->num_ports = field;
295
296 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
297 func_cap->pf_context_behaviour = size;
298
299 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
300 func_cap->qp_quota = size & 0xFFFFFF;
301
302 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
303 func_cap->srq_quota = size & 0xFFFFFF;
304
305 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
306 func_cap->cq_quota = size & 0xFFFFFF;
307
308 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
309 func_cap->max_eq = size & 0xFFFFFF;
310
311 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
312 func_cap->reserved_eq = size & 0xFFFFFF;
313
314 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
315 func_cap->mpt_quota = size & 0xFFFFFF;
316
317 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
318 func_cap->mtt_quota = size & 0xFFFFFF;
319
320 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
321 func_cap->mcg_quota = size & 0xFFFFFF;
322
323 MLX4_GET(size, outbox, QUERY_FUNC_CAP_BASE_TUNNEL_QPN_OFFSET);
324 func_cap->base_tunnel_qpn = size & 0xFFFFFF;
325
326 MLX4_GET(size, outbox, QUERY_FUNC_CAP_BASE_PROXY_QPN_OFFSET);
327 func_cap->base_proxy_qpn = size & 0xFFFFFF;
328
329 for (i = 1; i <= func_cap->num_ports; ++i) {
330 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
331 MLX4_CMD_QUERY_FUNC_CAP,
332 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
333 if (err)
334 goto out;
335
336 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
337 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
338 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
339 mlx4_err(dev, "VLAN is enforced on this port\n");
340 err = -EPROTONOSUPPORT;
341 goto out;
342 }
343
344 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
345 mlx4_err(dev, "Force mac is enabled on this port\n");
346 err = -EPROTONOSUPPORT;
347 goto out;
348 }
349 } else if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB) {
350 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
351 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
352 mlx4_err(dev, "phy_wqe_gid is "
353 "enforced on this ib port\n");
354 err = -EPROTONOSUPPORT;
355 goto out;
356 }
357 }
358
359 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
360 func_cap->physical_port[i] = field;
361 }
362
363 /* All other resources are allocated by the master, but we still report
364 * 'num' and 'reserved' capabilities as follows:
365 * - num remains the maximum resource index
366 * - 'num - reserved' is the total available objects of a resource, but
367 * resource indices may be less than 'reserved'
368 * TODO: set per-resource quotas */
369
370 out:
371 mlx4_free_cmd_mailbox(dev, mailbox);
372
373 return err;
374 }
375
376 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
377 {
378 struct mlx4_cmd_mailbox *mailbox;
379 u32 *outbox;
380 u8 field;
381 u32 field32, flags, ext_flags;
382 u16 size;
383 u16 stat_rate;
384 int err;
385 int i;
386
387 #define QUERY_DEV_CAP_OUT_SIZE 0x100
388 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
389 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
390 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
391 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
392 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
393 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
394 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
395 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
396 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
397 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
398 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
399 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
400 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
401 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
402 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
403 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
404 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
405 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
406 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
407 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
408 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
409 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
410 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
411 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
412 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
413 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
414 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
415 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
416 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
417 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
418 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
419 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
420 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
421 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
422 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
423 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
424 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
425 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
426 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
427 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
428 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
429 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
430 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
431 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
432 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
433 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
434 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
435 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
436 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
437 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
438 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
439 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
440 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
441 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
442 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
443 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
444 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
445 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
446 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
447 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
448 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
449 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
450 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
451 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
452 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
453 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
454 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
455 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
456
457 dev_cap->flags2 = 0;
458 mailbox = mlx4_alloc_cmd_mailbox(dev);
459 if (IS_ERR(mailbox))
460 return PTR_ERR(mailbox);
461 outbox = mailbox->buf;
462
463 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
464 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
465 if (err)
466 goto out;
467
468 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
469 dev_cap->reserved_qps = 1 << (field & 0xf);
470 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
471 dev_cap->max_qps = 1 << (field & 0x1f);
472 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
473 dev_cap->reserved_srqs = 1 << (field >> 4);
474 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
475 dev_cap->max_srqs = 1 << (field & 0x1f);
476 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
477 dev_cap->max_cq_sz = 1 << field;
478 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
479 dev_cap->reserved_cqs = 1 << (field & 0xf);
480 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
481 dev_cap->max_cqs = 1 << (field & 0x1f);
482 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
483 dev_cap->max_mpts = 1 << (field & 0x3f);
484 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
485 dev_cap->reserved_eqs = field & 0xf;
486 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
487 dev_cap->max_eqs = 1 << (field & 0xf);
488 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
489 dev_cap->reserved_mtts = 1 << (field >> 4);
490 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
491 dev_cap->max_mrw_sz = 1 << field;
492 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
493 dev_cap->reserved_mrws = 1 << (field & 0xf);
494 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
495 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
496 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
497 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
498 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
499 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
500 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
501 field &= 0x1f;
502 if (!field)
503 dev_cap->max_gso_sz = 0;
504 else
505 dev_cap->max_gso_sz = 1 << field;
506
507 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
508 if (field & 0x20)
509 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
510 if (field & 0x10)
511 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
512 field &= 0xf;
513 if (field) {
514 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
515 dev_cap->max_rss_tbl_sz = 1 << field;
516 } else
517 dev_cap->max_rss_tbl_sz = 0;
518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
519 dev_cap->max_rdma_global = 1 << (field & 0x3f);
520 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
521 dev_cap->local_ca_ack_delay = field & 0x1f;
522 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
523 dev_cap->num_ports = field & 0xf;
524 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
525 dev_cap->max_msg_sz = 1 << (field & 0x1f);
526 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
527 if (field & 0x80)
528 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
529 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
530 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
531 dev_cap->fs_max_num_qp_per_entry = field;
532 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
533 dev_cap->stat_rate_support = stat_rate;
534 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
535 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
536 dev_cap->flags = flags | (u64)ext_flags << 32;
537 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
538 dev_cap->reserved_uars = field >> 4;
539 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
540 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
541 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
542 dev_cap->min_page_sz = 1 << field;
543
544 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
545 if (field & 0x80) {
546 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
547 dev_cap->bf_reg_size = 1 << (field & 0x1f);
548 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
549 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
550 field = 3;
551 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
552 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
553 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
554 } else {
555 dev_cap->bf_reg_size = 0;
556 mlx4_dbg(dev, "BlueFlame not available\n");
557 }
558
559 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
560 dev_cap->max_sq_sg = field;
561 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
562 dev_cap->max_sq_desc_sz = size;
563
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
565 dev_cap->max_qp_per_mcg = 1 << field;
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
567 dev_cap->reserved_mgms = field & 0xf;
568 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
569 dev_cap->max_mcgs = 1 << field;
570 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
571 dev_cap->reserved_pds = field >> 4;
572 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
573 dev_cap->max_pds = 1 << (field & 0x3f);
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
575 dev_cap->reserved_xrcds = field >> 4;
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
577 dev_cap->max_xrcds = 1 << (field & 0x1f);
578
579 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
580 dev_cap->rdmarc_entry_sz = size;
581 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
582 dev_cap->qpc_entry_sz = size;
583 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
584 dev_cap->aux_entry_sz = size;
585 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
586 dev_cap->altc_entry_sz = size;
587 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
588 dev_cap->eqc_entry_sz = size;
589 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
590 dev_cap->cqc_entry_sz = size;
591 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
592 dev_cap->srq_entry_sz = size;
593 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
594 dev_cap->cmpt_entry_sz = size;
595 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
596 dev_cap->mtt_entry_sz = size;
597 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
598 dev_cap->dmpt_entry_sz = size;
599
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
601 dev_cap->max_srq_sz = 1 << field;
602 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
603 dev_cap->max_qp_sz = 1 << field;
604 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
605 dev_cap->resize_srq = field & 1;
606 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
607 dev_cap->max_rq_sg = field;
608 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
609 dev_cap->max_rq_desc_sz = size;
610
611 MLX4_GET(dev_cap->bmme_flags, outbox,
612 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
613 MLX4_GET(dev_cap->reserved_lkey, outbox,
614 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
615 MLX4_GET(dev_cap->max_icm_sz, outbox,
616 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
617 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
618 MLX4_GET(dev_cap->max_counters, outbox,
619 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
620
621 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
622 for (i = 1; i <= dev_cap->num_ports; ++i) {
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
624 dev_cap->max_vl[i] = field >> 4;
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
626 dev_cap->ib_mtu[i] = field >> 4;
627 dev_cap->max_port_width[i] = field & 0xf;
628 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
629 dev_cap->max_gids[i] = 1 << (field & 0xf);
630 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
631 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
632 }
633 } else {
634 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
635 #define QUERY_PORT_MTU_OFFSET 0x01
636 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
637 #define QUERY_PORT_WIDTH_OFFSET 0x06
638 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
639 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
640 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
641 #define QUERY_PORT_MAC_OFFSET 0x10
642 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
643 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
644 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
645
646 for (i = 1; i <= dev_cap->num_ports; ++i) {
647 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
648 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
649 if (err)
650 goto out;
651
652 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
653 dev_cap->supported_port_types[i] = field & 3;
654 dev_cap->suggested_type[i] = (field >> 3) & 1;
655 dev_cap->default_sense[i] = (field >> 4) & 1;
656 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
657 dev_cap->ib_mtu[i] = field & 0xf;
658 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
659 dev_cap->max_port_width[i] = field & 0xf;
660 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
661 dev_cap->max_gids[i] = 1 << (field >> 4);
662 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
663 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
664 dev_cap->max_vl[i] = field & 0xf;
665 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
666 dev_cap->log_max_macs[i] = field & 0xf;
667 dev_cap->log_max_vlans[i] = field >> 4;
668 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
669 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
670 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
671 dev_cap->trans_type[i] = field32 >> 24;
672 dev_cap->vendor_oui[i] = field32 & 0xffffff;
673 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
674 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
675 }
676 }
677
678 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
679 dev_cap->bmme_flags, dev_cap->reserved_lkey);
680
681 /*
682 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
683 * we can't use any EQs whose doorbell falls on that page,
684 * even if the EQ itself isn't reserved.
685 */
686 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
687 dev_cap->reserved_eqs);
688
689 mlx4_dbg(dev, "Max ICM size %lld MB\n",
690 (unsigned long long) dev_cap->max_icm_sz >> 20);
691 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
692 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
693 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
694 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
695 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
696 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
697 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
698 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
699 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
700 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
701 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
702 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
703 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
704 dev_cap->max_pds, dev_cap->reserved_mgms);
705 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
706 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
707 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
708 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
709 dev_cap->max_port_width[1]);
710 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
711 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
712 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
713 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
714 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
715 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
716 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
717
718 dump_dev_cap_flags(dev, dev_cap->flags);
719 dump_dev_cap_flags2(dev, dev_cap->flags2);
720
721 out:
722 mlx4_free_cmd_mailbox(dev, mailbox);
723 return err;
724 }
725
726 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
727 struct mlx4_vhcr *vhcr,
728 struct mlx4_cmd_mailbox *inbox,
729 struct mlx4_cmd_mailbox *outbox,
730 struct mlx4_cmd_info *cmd)
731 {
732 int err = 0;
733 u8 field;
734
735 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
736 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
737 if (err)
738 return err;
739
740 /* For guests, report Blueflame disabled */
741 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
742 field &= 0x7f;
743 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
744
745 return 0;
746 }
747
748 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
749 struct mlx4_vhcr *vhcr,
750 struct mlx4_cmd_mailbox *inbox,
751 struct mlx4_cmd_mailbox *outbox,
752 struct mlx4_cmd_info *cmd)
753 {
754 u64 def_mac;
755 u8 port_type;
756 u16 short_field;
757 int err;
758
759 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
760 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
761 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
762
763 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
764 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
765 MLX4_CMD_NATIVE);
766
767 if (!err && dev->caps.function != slave) {
768 /* set slave default_mac address */
769 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
770 def_mac += slave << 8;
771 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
772
773 /* get port type - currently only eth is enabled */
774 MLX4_GET(port_type, outbox->buf,
775 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
776
777 /* No link sensing allowed */
778 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
779 /* set port type to currently operating port type */
780 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
781
782 MLX4_PUT(outbox->buf, port_type,
783 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
784
785 short_field = 1; /* slave max gids */
786 MLX4_PUT(outbox->buf, short_field,
787 QUERY_PORT_CUR_MAX_GID_OFFSET);
788
789 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
790 MLX4_PUT(outbox->buf, short_field,
791 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
792 }
793
794 return err;
795 }
796
797 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
798 int *gid_tbl_len, int *pkey_tbl_len)
799 {
800 struct mlx4_cmd_mailbox *mailbox;
801 u32 *outbox;
802 u16 field;
803 int err;
804
805 mailbox = mlx4_alloc_cmd_mailbox(dev);
806 if (IS_ERR(mailbox))
807 return PTR_ERR(mailbox);
808
809 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
810 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
811 MLX4_CMD_WRAPPED);
812 if (err)
813 goto out;
814
815 outbox = mailbox->buf;
816
817 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
818 *gid_tbl_len = field;
819
820 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
821 *pkey_tbl_len = field;
822
823 out:
824 mlx4_free_cmd_mailbox(dev, mailbox);
825 return err;
826 }
827 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
828
829 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
830 {
831 struct mlx4_cmd_mailbox *mailbox;
832 struct mlx4_icm_iter iter;
833 __be64 *pages;
834 int lg;
835 int nent = 0;
836 int i;
837 int err = 0;
838 int ts = 0, tc = 0;
839
840 mailbox = mlx4_alloc_cmd_mailbox(dev);
841 if (IS_ERR(mailbox))
842 return PTR_ERR(mailbox);
843 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
844 pages = mailbox->buf;
845
846 for (mlx4_icm_first(icm, &iter);
847 !mlx4_icm_last(&iter);
848 mlx4_icm_next(&iter)) {
849 /*
850 * We have to pass pages that are aligned to their
851 * size, so find the least significant 1 in the
852 * address or size and use that as our log2 size.
853 */
854 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
855 if (lg < MLX4_ICM_PAGE_SHIFT) {
856 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
857 MLX4_ICM_PAGE_SIZE,
858 (unsigned long long) mlx4_icm_addr(&iter),
859 mlx4_icm_size(&iter));
860 err = -EINVAL;
861 goto out;
862 }
863
864 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
865 if (virt != -1) {
866 pages[nent * 2] = cpu_to_be64(virt);
867 virt += 1 << lg;
868 }
869
870 pages[nent * 2 + 1] =
871 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
872 (lg - MLX4_ICM_PAGE_SHIFT));
873 ts += 1 << (lg - 10);
874 ++tc;
875
876 if (++nent == MLX4_MAILBOX_SIZE / 16) {
877 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
878 MLX4_CMD_TIME_CLASS_B,
879 MLX4_CMD_NATIVE);
880 if (err)
881 goto out;
882 nent = 0;
883 }
884 }
885 }
886
887 if (nent)
888 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
889 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
890 if (err)
891 goto out;
892
893 switch (op) {
894 case MLX4_CMD_MAP_FA:
895 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
896 break;
897 case MLX4_CMD_MAP_ICM_AUX:
898 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
899 break;
900 case MLX4_CMD_MAP_ICM:
901 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
902 tc, ts, (unsigned long long) virt - (ts << 10));
903 break;
904 }
905
906 out:
907 mlx4_free_cmd_mailbox(dev, mailbox);
908 return err;
909 }
910
911 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
912 {
913 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
914 }
915
916 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
917 {
918 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
919 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
920 }
921
922
923 int mlx4_RUN_FW(struct mlx4_dev *dev)
924 {
925 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
926 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
927 }
928
929 int mlx4_QUERY_FW(struct mlx4_dev *dev)
930 {
931 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
932 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
933 struct mlx4_cmd_mailbox *mailbox;
934 u32 *outbox;
935 int err = 0;
936 u64 fw_ver;
937 u16 cmd_if_rev;
938 u8 lg;
939
940 #define QUERY_FW_OUT_SIZE 0x100
941 #define QUERY_FW_VER_OFFSET 0x00
942 #define QUERY_FW_PPF_ID 0x09
943 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
944 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
945 #define QUERY_FW_ERR_START_OFFSET 0x30
946 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
947 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
948
949 #define QUERY_FW_SIZE_OFFSET 0x00
950 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
951 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
952
953 #define QUERY_FW_COMM_BASE_OFFSET 0x40
954 #define QUERY_FW_COMM_BAR_OFFSET 0x48
955
956 mailbox = mlx4_alloc_cmd_mailbox(dev);
957 if (IS_ERR(mailbox))
958 return PTR_ERR(mailbox);
959 outbox = mailbox->buf;
960
961 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
962 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
963 if (err)
964 goto out;
965
966 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
967 /*
968 * FW subminor version is at more significant bits than minor
969 * version, so swap here.
970 */
971 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
972 ((fw_ver & 0xffff0000ull) >> 16) |
973 ((fw_ver & 0x0000ffffull) << 16);
974
975 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
976 dev->caps.function = lg;
977
978 if (mlx4_is_slave(dev))
979 goto out;
980
981
982 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
983 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
984 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
985 mlx4_err(dev, "Installed FW has unsupported "
986 "command interface revision %d.\n",
987 cmd_if_rev);
988 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
989 (int) (dev->caps.fw_ver >> 32),
990 (int) (dev->caps.fw_ver >> 16) & 0xffff,
991 (int) dev->caps.fw_ver & 0xffff);
992 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
993 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
994 err = -ENODEV;
995 goto out;
996 }
997
998 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
999 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1000
1001 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1002 cmd->max_cmds = 1 << lg;
1003
1004 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1005 (int) (dev->caps.fw_ver >> 32),
1006 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1007 (int) dev->caps.fw_ver & 0xffff,
1008 cmd_if_rev, cmd->max_cmds);
1009
1010 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1011 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1012 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1013 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1014
1015 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1016 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1017
1018 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1019 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1020 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1021 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1022
1023 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1024 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1025 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1026 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1027 fw->comm_bar, fw->comm_base);
1028 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1029
1030 /*
1031 * Round up number of system pages needed in case
1032 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1033 */
1034 fw->fw_pages =
1035 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1036 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1037
1038 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1039 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1040
1041 out:
1042 mlx4_free_cmd_mailbox(dev, mailbox);
1043 return err;
1044 }
1045
1046 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1047 struct mlx4_vhcr *vhcr,
1048 struct mlx4_cmd_mailbox *inbox,
1049 struct mlx4_cmd_mailbox *outbox,
1050 struct mlx4_cmd_info *cmd)
1051 {
1052 u8 *outbuf;
1053 int err;
1054
1055 outbuf = outbox->buf;
1056 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1057 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1058 if (err)
1059 return err;
1060
1061 /* for slaves, set pci PPF ID to invalid and zero out everything
1062 * else except FW version */
1063 outbuf[0] = outbuf[1] = 0;
1064 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1065 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1066
1067 return 0;
1068 }
1069
1070 static void get_board_id(void *vsd, char *board_id)
1071 {
1072 int i;
1073
1074 #define VSD_OFFSET_SIG1 0x00
1075 #define VSD_OFFSET_SIG2 0xde
1076 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1077 #define VSD_OFFSET_TS_BOARD_ID 0x20
1078
1079 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1080
1081 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1082
1083 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1084 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1085 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1086 } else {
1087 /*
1088 * The board ID is a string but the firmware byte
1089 * swaps each 4-byte word before passing it back to
1090 * us. Therefore we need to swab it before printing.
1091 */
1092 for (i = 0; i < 4; ++i)
1093 ((u32 *) board_id)[i] =
1094 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1095 }
1096 }
1097
1098 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1099 {
1100 struct mlx4_cmd_mailbox *mailbox;
1101 u32 *outbox;
1102 int err;
1103
1104 #define QUERY_ADAPTER_OUT_SIZE 0x100
1105 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1106 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1107
1108 mailbox = mlx4_alloc_cmd_mailbox(dev);
1109 if (IS_ERR(mailbox))
1110 return PTR_ERR(mailbox);
1111 outbox = mailbox->buf;
1112
1113 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1114 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1115 if (err)
1116 goto out;
1117
1118 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1119
1120 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1121 adapter->board_id);
1122
1123 out:
1124 mlx4_free_cmd_mailbox(dev, mailbox);
1125 return err;
1126 }
1127
1128 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1129 {
1130 struct mlx4_cmd_mailbox *mailbox;
1131 __be32 *inbox;
1132 int err;
1133
1134 #define INIT_HCA_IN_SIZE 0x200
1135 #define INIT_HCA_VERSION_OFFSET 0x000
1136 #define INIT_HCA_VERSION 2
1137 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1138 #define INIT_HCA_FLAGS_OFFSET 0x014
1139 #define INIT_HCA_QPC_OFFSET 0x020
1140 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1141 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1142 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1143 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1144 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1145 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1146 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1147 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1148 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1149 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1150 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1151 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1152 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1153 #define INIT_HCA_MCAST_OFFSET 0x0c0
1154 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1155 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1156 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1157 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1158 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1159 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1160 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1161 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1162 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1163 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1164 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1165 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1166 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1167 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1168 #define INIT_HCA_TPT_OFFSET 0x0f0
1169 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1170 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1171 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1172 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1173 #define INIT_HCA_UAR_OFFSET 0x120
1174 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1175 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1176
1177 mailbox = mlx4_alloc_cmd_mailbox(dev);
1178 if (IS_ERR(mailbox))
1179 return PTR_ERR(mailbox);
1180 inbox = mailbox->buf;
1181
1182 memset(inbox, 0, INIT_HCA_IN_SIZE);
1183
1184 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1185
1186 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1187 (ilog2(cache_line_size()) - 4) << 5;
1188
1189 #if defined(__LITTLE_ENDIAN)
1190 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1191 #elif defined(__BIG_ENDIAN)
1192 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1193 #else
1194 #error Host endianness not defined
1195 #endif
1196 /* Check port for UD address vector: */
1197 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1198
1199 /* Enable IPoIB checksumming if we can: */
1200 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1201 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1202
1203 /* Enable QoS support if module parameter set */
1204 if (enable_qos)
1205 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1206
1207 /* enable counters */
1208 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1209 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1210
1211 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1212
1213 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1214 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1215 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1216 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1217 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1218 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1219 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1220 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1221 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1222 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1223 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1224 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1225
1226 /* steering attributes */
1227 if (dev->caps.steering_mode ==
1228 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1229 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1230 cpu_to_be32(1 <<
1231 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1232
1233 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1234 MLX4_PUT(inbox, param->log_mc_entry_sz,
1235 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1236 MLX4_PUT(inbox, param->log_mc_table_sz,
1237 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1238 /* Enable Ethernet flow steering
1239 * with udp unicast and tcp unicast
1240 */
1241 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1242 INIT_HCA_FS_ETH_BITS_OFFSET);
1243 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1244 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1245 /* Enable IPoIB flow steering
1246 * with udp unicast and tcp unicast
1247 */
1248 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1249 INIT_HCA_FS_IB_BITS_OFFSET);
1250 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1251 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1252 } else {
1253 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1254 MLX4_PUT(inbox, param->log_mc_entry_sz,
1255 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1256 MLX4_PUT(inbox, param->log_mc_hash_sz,
1257 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1258 MLX4_PUT(inbox, param->log_mc_table_sz,
1259 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1260 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1261 MLX4_PUT(inbox, (u8) (1 << 3),
1262 INIT_HCA_UC_STEERING_OFFSET);
1263 }
1264
1265 /* TPT attributes */
1266
1267 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1268 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1269 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1270 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1271
1272 /* UAR attributes */
1273
1274 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1275 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1276
1277 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1278 MLX4_CMD_NATIVE);
1279
1280 if (err)
1281 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1282
1283 mlx4_free_cmd_mailbox(dev, mailbox);
1284 return err;
1285 }
1286
1287 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1288 struct mlx4_init_hca_param *param)
1289 {
1290 struct mlx4_cmd_mailbox *mailbox;
1291 __be32 *outbox;
1292 int err;
1293
1294 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1295
1296 mailbox = mlx4_alloc_cmd_mailbox(dev);
1297 if (IS_ERR(mailbox))
1298 return PTR_ERR(mailbox);
1299 outbox = mailbox->buf;
1300
1301 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1302 MLX4_CMD_QUERY_HCA,
1303 MLX4_CMD_TIME_CLASS_B,
1304 !mlx4_is_slave(dev));
1305 if (err)
1306 goto out;
1307
1308 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1309
1310 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1311
1312 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1313 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1314 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1315 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1316 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1317 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1318 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1319 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1320 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1321 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1322 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1323 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1324
1325 /* steering attributes */
1326 if (dev->caps.steering_mode ==
1327 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1328
1329 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1330 MLX4_GET(param->log_mc_entry_sz, outbox,
1331 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1332 MLX4_GET(param->log_mc_table_sz, outbox,
1333 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1334 } else {
1335 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1336 MLX4_GET(param->log_mc_entry_sz, outbox,
1337 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1338 MLX4_GET(param->log_mc_hash_sz, outbox,
1339 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1340 MLX4_GET(param->log_mc_table_sz, outbox,
1341 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1342 }
1343
1344 /* TPT attributes */
1345
1346 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1347 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1348 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1349 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1350
1351 /* UAR attributes */
1352
1353 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1354 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1355
1356 out:
1357 mlx4_free_cmd_mailbox(dev, mailbox);
1358
1359 return err;
1360 }
1361
1362 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1363 struct mlx4_vhcr *vhcr,
1364 struct mlx4_cmd_mailbox *inbox,
1365 struct mlx4_cmd_mailbox *outbox,
1366 struct mlx4_cmd_info *cmd)
1367 {
1368 struct mlx4_priv *priv = mlx4_priv(dev);
1369 int port = vhcr->in_modifier;
1370 int err;
1371
1372 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1373 return 0;
1374
1375 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1376 return -ENODEV;
1377
1378 /* Enable port only if it was previously disabled */
1379 if (!priv->mfunc.master.init_port_ref[port]) {
1380 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1381 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1382 if (err)
1383 return err;
1384 }
1385 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1386 ++priv->mfunc.master.init_port_ref[port];
1387 return 0;
1388 }
1389
1390 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1391 {
1392 struct mlx4_cmd_mailbox *mailbox;
1393 u32 *inbox;
1394 int err;
1395 u32 flags;
1396 u16 field;
1397
1398 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1399 #define INIT_PORT_IN_SIZE 256
1400 #define INIT_PORT_FLAGS_OFFSET 0x00
1401 #define INIT_PORT_FLAG_SIG (1 << 18)
1402 #define INIT_PORT_FLAG_NG (1 << 17)
1403 #define INIT_PORT_FLAG_G0 (1 << 16)
1404 #define INIT_PORT_VL_SHIFT 4
1405 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1406 #define INIT_PORT_MTU_OFFSET 0x04
1407 #define INIT_PORT_MAX_GID_OFFSET 0x06
1408 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1409 #define INIT_PORT_GUID0_OFFSET 0x10
1410 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1411 #define INIT_PORT_SI_GUID_OFFSET 0x20
1412
1413 mailbox = mlx4_alloc_cmd_mailbox(dev);
1414 if (IS_ERR(mailbox))
1415 return PTR_ERR(mailbox);
1416 inbox = mailbox->buf;
1417
1418 memset(inbox, 0, INIT_PORT_IN_SIZE);
1419
1420 flags = 0;
1421 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1422 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1423 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1424
1425 field = 128 << dev->caps.ib_mtu_cap[port];
1426 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1427 field = dev->caps.gid_table_len[port];
1428 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1429 field = dev->caps.pkey_table_len[port];
1430 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1431
1432 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1433 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1434
1435 mlx4_free_cmd_mailbox(dev, mailbox);
1436 } else
1437 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1438 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1439
1440 return err;
1441 }
1442 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1443
1444 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1445 struct mlx4_vhcr *vhcr,
1446 struct mlx4_cmd_mailbox *inbox,
1447 struct mlx4_cmd_mailbox *outbox,
1448 struct mlx4_cmd_info *cmd)
1449 {
1450 struct mlx4_priv *priv = mlx4_priv(dev);
1451 int port = vhcr->in_modifier;
1452 int err;
1453
1454 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1455 (1 << port)))
1456 return 0;
1457
1458 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1459 return -ENODEV;
1460 if (priv->mfunc.master.init_port_ref[port] == 1) {
1461 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1462 MLX4_CMD_NATIVE);
1463 if (err)
1464 return err;
1465 }
1466 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1467 --priv->mfunc.master.init_port_ref[port];
1468 return 0;
1469 }
1470
1471 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1472 {
1473 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1474 MLX4_CMD_WRAPPED);
1475 }
1476 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1477
1478 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1479 {
1480 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1481 MLX4_CMD_NATIVE);
1482 }
1483
1484 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1485 {
1486 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1487 MLX4_CMD_SET_ICM_SIZE,
1488 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1489 if (ret)
1490 return ret;
1491
1492 /*
1493 * Round up number of system pages needed in case
1494 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1495 */
1496 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1497 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1498
1499 return 0;
1500 }
1501
1502 int mlx4_NOP(struct mlx4_dev *dev)
1503 {
1504 /* Input modifier of 0x1f means "finish as soon as possible." */
1505 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1506 }
1507
1508 #define MLX4_WOL_SETUP_MODE (5 << 28)
1509 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1510 {
1511 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1512
1513 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1514 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1515 MLX4_CMD_NATIVE);
1516 }
1517 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1518
1519 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1520 {
1521 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1522
1523 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1524 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1525 }
1526 EXPORT_SYMBOL_GPL(mlx4_wol_write);
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