2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION
);
58 struct workqueue_struct
*mlx4_wq
;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level
= 0;
63 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
64 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x
, int, 0444);
72 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs
[3] = {0, 0, 0};
81 static int num_vfs_argc
= 3;
82 module_param_array(num_vfs
, byte
, &num_vfs_argc
, 0444);
83 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf
[3] = {0, 0, 0};
87 static int probe_vfs_argc
= 3;
88 module_param_array(probe_vf
, byte
, &probe_vfs_argc
, 0444);
89 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
93 module_param_named(log_num_mgm_entry_size
,
94 mlx4_log_num_mgm_entry_size
, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe
= true;
103 module_param(enable_64b_cqe_eqe
, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
109 static char mlx4_version
[] =
110 DRV_NAME
": Mellanox ConnectX core driver v"
111 DRV_VERSION
" (" DRV_RELDATE
")\n";
113 static struct mlx4_profile default_profile
= {
116 .rdmarc_per_qp
= 1 << 4,
120 .num_mtt
= 1 << 20, /* It is really num mtt segements */
123 static int log_num_mac
= 7;
124 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
125 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
127 static int log_num_vlan
;
128 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
129 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
130 /* Log2 max number of VLANs per ETH port (0-7) */
131 #define MLX4_LOG_NUM_VLANS 7
133 static bool use_prio
;
134 module_param_named(use_prio
, use_prio
, bool, 0444);
135 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports (deprecated)");
137 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
138 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
139 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
141 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
142 static int arr_argc
= 2;
143 module_param_array(port_type_array
, int, &arr_argc
, 0444);
144 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
145 "1 for IB, 2 for Ethernet");
147 struct mlx4_port_config
{
148 struct list_head list
;
149 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
150 struct pci_dev
*pdev
;
153 static atomic_t pf_loading
= ATOMIC_INIT(0);
155 int mlx4_check_port_params(struct mlx4_dev
*dev
,
156 enum mlx4_port_type
*port_type
)
160 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
161 if (port_type
[i
] != port_type
[i
+ 1]) {
162 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
163 mlx4_err(dev
, "Only same port types supported on this HCA, aborting\n");
169 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
170 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
171 mlx4_err(dev
, "Requested port type for port %d is not supported on this HCA\n",
179 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
183 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
184 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
187 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
192 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
194 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
198 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
199 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
200 dev_cap
->min_page_sz
, PAGE_SIZE
);
203 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
204 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
205 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
209 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
210 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
212 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
216 dev
->caps
.num_ports
= dev_cap
->num_ports
;
217 dev
->phys_caps
.num_phys_eqs
= MLX4_MAX_EQ_NUM
;
218 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
219 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
220 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
221 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
222 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
223 /* set gid and pkey table operating lengths by default
224 * to non-sriov values */
225 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
226 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
227 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
228 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
229 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
230 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
231 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
232 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
233 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
234 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
235 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
236 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
239 dev
->caps
.uar_page_size
= PAGE_SIZE
;
240 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
241 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
242 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
243 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
244 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
245 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
246 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
247 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
248 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
249 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
250 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
251 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
252 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
254 * Subtract 1 from the limit because we need to allocate a
255 * spare CQE so the HCA HW can tell the difference between an
256 * empty CQ and a full CQ.
258 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
259 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
260 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
261 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
262 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
264 /* The first 128 UARs are used for EQ doorbells */
265 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
266 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
267 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
268 dev_cap
->reserved_xrcds
: 0;
269 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
270 dev_cap
->max_xrcds
: 0;
271 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
273 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
274 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
275 dev
->caps
.flags
= dev_cap
->flags
;
276 dev
->caps
.flags2
= dev_cap
->flags2
;
277 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
278 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
279 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
280 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
281 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
283 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
284 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
285 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
286 /* Don't do sense port on multifunction devices (for now at least) */
287 if (mlx4_is_mfunc(dev
))
288 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
290 dev
->caps
.log_num_macs
= log_num_mac
;
291 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
293 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
294 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
295 if (dev
->caps
.supported_type
[i
]) {
296 /* if only ETH is supported - assign ETH */
297 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
298 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
299 /* if only IB is supported, assign IB */
300 else if (dev
->caps
.supported_type
[i
] ==
302 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
304 /* if IB and ETH are supported, we set the port
305 * type according to user selection of port type;
306 * if user selected none, take the FW hint */
307 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
308 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
309 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
311 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
315 * Link sensing is allowed on the port if 3 conditions are true:
316 * 1. Both protocols are supported on the port.
317 * 2. Different types are supported on the port
318 * 3. FW declared that it supports link sensing
320 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
321 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
322 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
323 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
326 * If "default_sense" bit is set, we move the port to "AUTO" mode
327 * and perform sense_port FW command to try and set the correct
328 * port type from beginning
330 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
331 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
332 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
333 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
334 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
335 dev
->caps
.port_type
[i
] = sensed_port
;
337 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
340 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
341 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
342 mlx4_warn(dev
, "Requested number of MACs is too much for port %d, reducing to %d\n",
343 i
, 1 << dev
->caps
.log_num_macs
);
345 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
346 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
347 mlx4_warn(dev
, "Requested number of VLANs is too much for port %d, reducing to %d\n",
348 i
, 1 << dev
->caps
.log_num_vlans
);
352 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
354 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
355 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
356 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
357 (1 << dev
->caps
.log_num_macs
) *
358 (1 << dev
->caps
.log_num_vlans
) *
360 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
362 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
363 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
364 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
365 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
367 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
369 if (!enable_64b_cqe_eqe
&& !mlx4_is_slave(dev
)) {
371 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
372 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
373 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
374 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
378 if ((dev
->caps
.flags
&
379 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
381 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
386 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev
*dev
,
387 enum pci_bus_speed
*speed
,
388 enum pcie_link_width
*width
)
390 u32 lnkcap1
, lnkcap2
;
393 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
395 *speed
= PCI_SPEED_UNKNOWN
;
396 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
398 err1
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP
, &lnkcap1
);
399 err2
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
400 if (!err2
&& lnkcap2
) { /* PCIe r3.0-compliant */
401 if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_8_0GB
)
402 *speed
= PCIE_SPEED_8_0GT
;
403 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_5_0GB
)
404 *speed
= PCIE_SPEED_5_0GT
;
405 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_2_5GB
)
406 *speed
= PCIE_SPEED_2_5GT
;
409 *width
= (lnkcap1
& PCI_EXP_LNKCAP_MLW
) >> PCIE_MLW_CAP_SHIFT
;
410 if (!lnkcap2
) { /* pre-r3.0 */
411 if (lnkcap1
& PCI_EXP_LNKCAP_SLS_5_0GB
)
412 *speed
= PCIE_SPEED_5_0GT
;
413 else if (lnkcap1
& PCI_EXP_LNKCAP_SLS_2_5GB
)
414 *speed
= PCIE_SPEED_2_5GT
;
418 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
) {
420 err2
? err2
: -EINVAL
;
425 static void mlx4_check_pcie_caps(struct mlx4_dev
*dev
)
427 enum pcie_link_width width
, width_cap
;
428 enum pci_bus_speed speed
, speed_cap
;
431 #define PCIE_SPEED_STR(speed) \
432 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
433 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
434 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
437 err
= mlx4_get_pcie_dev_link_caps(dev
, &speed_cap
, &width_cap
);
440 "Unable to determine PCIe device BW capabilities\n");
444 err
= pcie_get_minimum_link(dev
->pdev
, &speed
, &width
);
445 if (err
|| speed
== PCI_SPEED_UNKNOWN
||
446 width
== PCIE_LNK_WIDTH_UNKNOWN
) {
448 "Unable to determine PCI device chain minimum BW\n");
452 if (width
!= width_cap
|| speed
!= speed_cap
)
454 "PCIe BW is different than device's capability\n");
456 mlx4_info(dev
, "PCIe link speed is %s, device supports %s\n",
457 PCIE_SPEED_STR(speed
), PCIE_SPEED_STR(speed_cap
));
458 mlx4_info(dev
, "PCIe link width is x%d, device supports x%d\n",
463 /*The function checks if there are live vf, return the num of them*/
464 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
466 struct mlx4_priv
*priv
= mlx4_priv(dev
);
467 struct mlx4_slave_state
*s_state
;
471 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
472 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
473 if (s_state
->active
&& s_state
->last_cmd
!=
474 MLX4_COMM_CMD_RESET
) {
475 mlx4_warn(dev
, "%s: slave: %d is still active\n",
483 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
485 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
487 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
488 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
491 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
493 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
495 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
499 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
501 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
503 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
505 if (!mlx4_is_master(dev
))
508 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
510 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
512 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
514 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
516 if (!mlx4_is_master(dev
))
519 priv
->slave_node_guids
[slave
] = guid
;
521 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
523 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
525 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
527 if (!mlx4_is_master(dev
))
530 return priv
->slave_node_guids
[slave
];
532 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
534 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
536 struct mlx4_priv
*priv
= mlx4_priv(dev
);
537 struct mlx4_slave_state
*s_slave
;
539 if (!mlx4_is_master(dev
))
542 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
543 return !!s_slave
->active
;
545 EXPORT_SYMBOL(mlx4_is_slave_active
);
547 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
548 struct mlx4_dev_cap
*dev_cap
,
549 struct mlx4_init_hca_param
*hca_param
)
551 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
552 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
553 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
554 dev
->caps
.fs_log_max_ucast_qp_range_size
=
555 dev_cap
->fs_log_max_ucast_qp_range_size
;
557 dev
->caps
.num_qp_per_mgm
=
558 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
560 mlx4_dbg(dev
, "Steering mode is: %s\n",
561 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
564 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
568 struct mlx4_dev_cap dev_cap
;
569 struct mlx4_func_cap func_cap
;
570 struct mlx4_init_hca_param hca_param
;
573 memset(&hca_param
, 0, sizeof(hca_param
));
574 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
576 mlx4_err(dev
, "QUERY_HCA command failed, aborting\n");
580 /* fail if the hca has an unknown global capability
581 * at this time global_caps should be always zeroed
583 if (hca_param
.global_caps
) {
584 mlx4_err(dev
, "Unknown hca global capabilities\n");
588 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
590 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
592 memset(&dev_cap
, 0, sizeof(dev_cap
));
593 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
594 err
= mlx4_dev_cap(dev
, &dev_cap
);
596 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
600 err
= mlx4_QUERY_FW(dev
);
602 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version\n");
604 page_size
= ~dev
->caps
.page_size_cap
+ 1;
605 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
606 if (page_size
> PAGE_SIZE
) {
607 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
608 page_size
, PAGE_SIZE
);
612 /* slave gets uar page size from QUERY_HCA fw command */
613 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
615 /* TODO: relax this assumption */
616 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
617 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
618 dev
->caps
.uar_page_size
, PAGE_SIZE
);
622 memset(&func_cap
, 0, sizeof(func_cap
));
623 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
625 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
630 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
631 PF_CONTEXT_BEHAVIOUR_MASK
) {
632 mlx4_err(dev
, "Unknown pf context behaviour\n");
636 dev
->caps
.num_ports
= func_cap
.num_ports
;
637 dev
->quotas
.qp
= func_cap
.qp_quota
;
638 dev
->quotas
.srq
= func_cap
.srq_quota
;
639 dev
->quotas
.cq
= func_cap
.cq_quota
;
640 dev
->quotas
.mpt
= func_cap
.mpt_quota
;
641 dev
->quotas
.mtt
= func_cap
.mtt_quota
;
642 dev
->caps
.num_qps
= 1 << hca_param
.log_num_qps
;
643 dev
->caps
.num_srqs
= 1 << hca_param
.log_num_srqs
;
644 dev
->caps
.num_cqs
= 1 << hca_param
.log_num_cqs
;
645 dev
->caps
.num_mpts
= 1 << hca_param
.log_mpt_sz
;
646 dev
->caps
.num_eqs
= func_cap
.max_eq
;
647 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
648 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
649 dev
->caps
.num_mgms
= 0;
650 dev
->caps
.num_amgms
= 0;
652 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
653 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
654 dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
658 dev
->caps
.qp0_qkey
= kcalloc(dev
->caps
.num_ports
, sizeof(u32
), GFP_KERNEL
);
659 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
660 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
661 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
662 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
664 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
665 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
||
666 !dev
->caps
.qp0_qkey
) {
671 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
672 err
= mlx4_QUERY_FUNC_CAP(dev
, (u32
) i
, &func_cap
);
674 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
678 dev
->caps
.qp0_qkey
[i
- 1] = func_cap
.qp0_qkey
;
679 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
680 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
681 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
682 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
683 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
684 dev
->caps
.phys_port_id
[i
] = func_cap
.phys_port_id
;
685 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
686 &dev
->caps
.gid_table_len
[i
],
687 &dev
->caps
.pkey_table_len
[i
]))
691 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
692 dev
->caps
.reserved_uars
) >
693 pci_resource_len(dev
->pdev
, 2)) {
694 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
695 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
696 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
700 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
701 dev
->caps
.eqe_size
= 64;
702 dev
->caps
.eqe_factor
= 1;
704 dev
->caps
.eqe_size
= 32;
705 dev
->caps
.eqe_factor
= 0;
708 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
709 dev
->caps
.cqe_size
= 64;
710 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_64B_CQE
;
712 dev
->caps
.cqe_size
= 32;
715 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
716 mlx4_warn(dev
, "Timestamping is not supported in slave mode\n");
718 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
723 kfree(dev
->caps
.qp0_qkey
);
724 kfree(dev
->caps
.qp0_tunnel
);
725 kfree(dev
->caps
.qp0_proxy
);
726 kfree(dev
->caps
.qp1_tunnel
);
727 kfree(dev
->caps
.qp1_proxy
);
728 dev
->caps
.qp0_qkey
= NULL
;
729 dev
->caps
.qp0_tunnel
= NULL
;
730 dev
->caps
.qp0_proxy
= NULL
;
731 dev
->caps
.qp1_tunnel
= NULL
;
732 dev
->caps
.qp1_proxy
= NULL
;
737 static void mlx4_request_modules(struct mlx4_dev
*dev
)
740 int has_ib_port
= false;
741 int has_eth_port
= false;
742 #define EN_DRV_NAME "mlx4_en"
743 #define IB_DRV_NAME "mlx4_ib"
745 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
746 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
)
748 else if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
753 request_module_nowait(EN_DRV_NAME
);
754 if (has_ib_port
|| (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IBOE
))
755 request_module_nowait(IB_DRV_NAME
);
759 * Change the port configuration of the device.
760 * Every user of this function must hold the port mutex.
762 int mlx4_change_port_types(struct mlx4_dev
*dev
,
763 enum mlx4_port_type
*port_types
)
769 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
770 /* Change the port type only if the new type is different
771 * from the current, and not set to Auto */
772 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
776 mlx4_unregister_device(dev
);
777 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
778 mlx4_CLOSE_PORT(dev
, port
);
779 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
780 err
= mlx4_SET_PORT(dev
, port
, -1);
782 mlx4_err(dev
, "Failed to set port %d, aborting\n",
787 mlx4_set_port_mask(dev
);
788 err
= mlx4_register_device(dev
);
790 mlx4_err(dev
, "Failed to register device\n");
793 mlx4_request_modules(dev
);
800 static ssize_t
show_port_type(struct device
*dev
,
801 struct device_attribute
*attr
,
804 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
806 struct mlx4_dev
*mdev
= info
->dev
;
810 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
812 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
813 sprintf(buf
, "auto (%s)\n", type
);
815 sprintf(buf
, "%s\n", type
);
820 static ssize_t
set_port_type(struct device
*dev
,
821 struct device_attribute
*attr
,
822 const char *buf
, size_t count
)
824 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
826 struct mlx4_dev
*mdev
= info
->dev
;
827 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
828 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
829 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
833 if (!strcmp(buf
, "ib\n"))
834 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
835 else if (!strcmp(buf
, "eth\n"))
836 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
837 else if (!strcmp(buf
, "auto\n"))
838 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
840 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
844 mlx4_stop_sense(mdev
);
845 mutex_lock(&priv
->port_mutex
);
846 /* Possible type is always the one that was delivered */
847 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
849 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
850 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
851 mdev
->caps
.possible_type
[i
+1];
852 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
853 types
[i
] = mdev
->caps
.port_type
[i
+1];
856 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
857 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
858 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
859 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
860 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
866 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
870 mlx4_do_sense_ports(mdev
, new_types
, types
);
872 err
= mlx4_check_port_params(mdev
, new_types
);
876 /* We are about to apply the changes after the configuration
877 * was verified, no need to remember the temporary types
879 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
880 priv
->port
[i
+ 1].tmp_type
= 0;
882 err
= mlx4_change_port_types(mdev
, new_types
);
885 mlx4_start_sense(mdev
);
886 mutex_unlock(&priv
->port_mutex
);
887 return err
? err
: count
;
898 static inline int int_to_ibta_mtu(int mtu
)
901 case 256: return IB_MTU_256
;
902 case 512: return IB_MTU_512
;
903 case 1024: return IB_MTU_1024
;
904 case 2048: return IB_MTU_2048
;
905 case 4096: return IB_MTU_4096
;
910 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
913 case IB_MTU_256
: return 256;
914 case IB_MTU_512
: return 512;
915 case IB_MTU_1024
: return 1024;
916 case IB_MTU_2048
: return 2048;
917 case IB_MTU_4096
: return 4096;
922 static ssize_t
show_port_ib_mtu(struct device
*dev
,
923 struct device_attribute
*attr
,
926 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
928 struct mlx4_dev
*mdev
= info
->dev
;
930 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
931 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
934 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
938 static ssize_t
set_port_ib_mtu(struct device
*dev
,
939 struct device_attribute
*attr
,
940 const char *buf
, size_t count
)
942 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
944 struct mlx4_dev
*mdev
= info
->dev
;
945 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
946 int err
, port
, mtu
, ibta_mtu
= -1;
948 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
949 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
953 err
= kstrtoint(buf
, 0, &mtu
);
955 ibta_mtu
= int_to_ibta_mtu(mtu
);
957 if (err
|| ibta_mtu
< 0) {
958 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
962 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
964 mlx4_stop_sense(mdev
);
965 mutex_lock(&priv
->port_mutex
);
966 mlx4_unregister_device(mdev
);
967 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
968 mlx4_CLOSE_PORT(mdev
, port
);
969 err
= mlx4_SET_PORT(mdev
, port
, -1);
971 mlx4_err(mdev
, "Failed to set port %d, aborting\n",
976 err
= mlx4_register_device(mdev
);
978 mutex_unlock(&priv
->port_mutex
);
979 mlx4_start_sense(mdev
);
980 return err
? err
: count
;
983 static int mlx4_load_fw(struct mlx4_dev
*dev
)
985 struct mlx4_priv
*priv
= mlx4_priv(dev
);
988 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
989 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
990 if (!priv
->fw
.fw_icm
) {
991 mlx4_err(dev
, "Couldn't allocate FW area, aborting\n");
995 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
997 mlx4_err(dev
, "MAP_FA command failed, aborting\n");
1001 err
= mlx4_RUN_FW(dev
);
1003 mlx4_err(dev
, "RUN_FW command failed, aborting\n");
1013 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1017 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
1020 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1024 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
1026 ((u64
) (MLX4_CMPT_TYPE_QP
*
1027 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1028 cmpt_entry_sz
, dev
->caps
.num_qps
,
1029 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1034 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
1036 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
1037 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1038 cmpt_entry_sz
, dev
->caps
.num_srqs
,
1039 dev
->caps
.reserved_srqs
, 0, 0);
1043 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
1045 ((u64
) (MLX4_CMPT_TYPE_CQ
*
1046 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1047 cmpt_entry_sz
, dev
->caps
.num_cqs
,
1048 dev
->caps
.reserved_cqs
, 0, 0);
1052 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1054 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
1056 ((u64
) (MLX4_CMPT_TYPE_EQ
*
1057 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1058 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
1065 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1068 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1071 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1077 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
1078 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
1080 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1085 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
1087 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting\n");
1091 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory\n",
1092 (unsigned long long) icm_size
>> 10,
1093 (unsigned long long) aux_pages
<< 2);
1095 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
1096 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1097 if (!priv
->fw
.aux_icm
) {
1098 mlx4_err(dev
, "Couldn't allocate aux memory, aborting\n");
1102 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
1104 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting\n");
1108 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
1110 mlx4_err(dev
, "Failed to map cMPT context memory, aborting\n");
1115 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1117 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1118 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1119 num_eqs
, num_eqs
, 0, 0);
1121 mlx4_err(dev
, "Failed to map EQ context memory, aborting\n");
1122 goto err_unmap_cmpt
;
1126 * Reserved MTT entries must be aligned up to a cacheline
1127 * boundary, since the FW will write to them, while the driver
1128 * writes to all other MTT entries. (The variable
1129 * dev->caps.mtt_entry_sz below is really the MTT segment
1130 * size, not the raw entry size)
1132 dev
->caps
.reserved_mtts
=
1133 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1134 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1136 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1138 dev
->caps
.mtt_entry_sz
,
1140 dev
->caps
.reserved_mtts
, 1, 0);
1142 mlx4_err(dev
, "Failed to map MTT context memory, aborting\n");
1146 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1147 init_hca
->dmpt_base
,
1148 dev_cap
->dmpt_entry_sz
,
1150 dev
->caps
.reserved_mrws
, 1, 1);
1152 mlx4_err(dev
, "Failed to map dMPT context memory, aborting\n");
1156 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1158 dev_cap
->qpc_entry_sz
,
1160 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1163 mlx4_err(dev
, "Failed to map QP context memory, aborting\n");
1164 goto err_unmap_dmpt
;
1167 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1168 init_hca
->auxc_base
,
1169 dev_cap
->aux_entry_sz
,
1171 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1174 mlx4_err(dev
, "Failed to map AUXC context memory, aborting\n");
1178 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1179 init_hca
->altc_base
,
1180 dev_cap
->altc_entry_sz
,
1182 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1185 mlx4_err(dev
, "Failed to map ALTC context memory, aborting\n");
1186 goto err_unmap_auxc
;
1189 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1190 init_hca
->rdmarc_base
,
1191 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1193 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1196 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1197 goto err_unmap_altc
;
1200 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1202 dev_cap
->cqc_entry_sz
,
1204 dev
->caps
.reserved_cqs
, 0, 0);
1206 mlx4_err(dev
, "Failed to map CQ context memory, aborting\n");
1207 goto err_unmap_rdmarc
;
1210 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1211 init_hca
->srqc_base
,
1212 dev_cap
->srq_entry_sz
,
1214 dev
->caps
.reserved_srqs
, 0, 0);
1216 mlx4_err(dev
, "Failed to map SRQ context memory, aborting\n");
1221 * For flow steering device managed mode it is required to use
1222 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1223 * required, but for simplicity just map the whole multicast
1224 * group table now. The table isn't very big and it's a lot
1225 * easier than trying to track ref counts.
1227 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1229 mlx4_get_mgm_entry_size(dev
),
1230 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1231 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1234 mlx4_err(dev
, "Failed to map MCG context memory, aborting\n");
1241 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1244 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1247 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1250 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1253 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1256 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1259 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1262 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1265 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1268 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1269 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1270 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1271 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1274 mlx4_UNMAP_ICM_AUX(dev
);
1277 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1282 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1284 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1286 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1287 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1288 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1289 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1290 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1291 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1292 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1293 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1294 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1295 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1296 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1297 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1298 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1299 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1301 mlx4_UNMAP_ICM_AUX(dev
);
1302 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1305 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1307 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1309 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1310 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1311 mlx4_warn(dev
, "Failed to close slave function\n");
1312 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1315 static int map_bf_area(struct mlx4_dev
*dev
)
1317 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1318 resource_size_t bf_start
;
1319 resource_size_t bf_len
;
1322 if (!dev
->caps
.bf_reg_size
)
1325 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1326 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1327 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1328 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1329 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1330 if (!priv
->bf_mapping
)
1336 static void unmap_bf_area(struct mlx4_dev
*dev
)
1338 if (mlx4_priv(dev
)->bf_mapping
)
1339 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1342 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1344 u32 clockhi
, clocklo
, clockhi1
;
1347 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1349 for (i
= 0; i
< 10; i
++) {
1350 clockhi
= swab32(readl(priv
->clock_mapping
));
1351 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1352 clockhi1
= swab32(readl(priv
->clock_mapping
));
1353 if (clockhi
== clockhi1
)
1357 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1361 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1364 static int map_internal_clock(struct mlx4_dev
*dev
)
1366 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1368 priv
->clock_mapping
=
1369 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1370 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1372 if (!priv
->clock_mapping
)
1378 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1380 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1382 if (priv
->clock_mapping
)
1383 iounmap(priv
->clock_mapping
);
1386 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1388 unmap_internal_clock(dev
);
1390 if (mlx4_is_slave(dev
))
1391 mlx4_slave_exit(dev
);
1393 mlx4_CLOSE_HCA(dev
, 0);
1394 mlx4_free_icms(dev
);
1396 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1400 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1402 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1403 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1404 int ret_from_reset
= 0;
1406 u32 cmd_channel_ver
;
1408 if (atomic_read(&pf_loading
)) {
1409 mlx4_warn(dev
, "PF is not ready - Deferring probe\n");
1410 return -EPROBE_DEFER
;
1413 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1414 priv
->cmd
.max_cmds
= 1;
1415 mlx4_warn(dev
, "Sending reset\n");
1416 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1418 /* if we are in the middle of flr the slave will try
1419 * NUM_OF_RESET_RETRIES times before leaving.*/
1420 if (ret_from_reset
) {
1421 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1422 mlx4_warn(dev
, "slave is currently in the middle of FLR - Deferring probe\n");
1423 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1424 return -EPROBE_DEFER
;
1429 /* check the driver version - the slave I/F revision
1430 * must match the master's */
1431 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1432 cmd_channel_ver
= mlx4_comm_get_version();
1434 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1435 MLX4_COMM_GET_IF_REV(slave_read
)) {
1436 mlx4_err(dev
, "slave driver version is not supported by the master\n");
1440 mlx4_warn(dev
, "Sending vhcr0\n");
1441 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1444 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1447 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1450 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1453 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1457 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1458 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1462 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1466 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1467 if (dev
->caps
.port_type
[i
] == MLX4_PORT_TYPE_ETH
)
1468 dev
->caps
.gid_table_len
[i
] =
1469 mlx4_get_slave_num_gids(dev
, 0, i
);
1471 dev
->caps
.gid_table_len
[i
] = 1;
1472 dev
->caps
.pkey_table_len
[i
] =
1473 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1477 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1479 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1481 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1483 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1487 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1490 static void choose_steering_mode(struct mlx4_dev
*dev
,
1491 struct mlx4_dev_cap
*dev_cap
)
1493 if (mlx4_log_num_mgm_entry_size
== -1 &&
1494 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1495 (!mlx4_is_mfunc(dev
) ||
1496 (dev_cap
->fs_max_num_qp_per_entry
>= (dev
->num_vfs
+ 1))) &&
1497 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1498 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1499 dev
->oper_log_mgm_entry_size
=
1500 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1501 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1502 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1503 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1504 dev_cap
->fs_log_max_ucast_qp_range_size
;
1506 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1507 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1508 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1510 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1512 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1513 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1514 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1516 dev
->oper_log_mgm_entry_size
=
1517 mlx4_log_num_mgm_entry_size
> 0 ?
1518 mlx4_log_num_mgm_entry_size
:
1519 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1520 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1522 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1523 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1524 dev
->oper_log_mgm_entry_size
,
1525 mlx4_log_num_mgm_entry_size
);
1528 static void choose_tunnel_offload_mode(struct mlx4_dev
*dev
,
1529 struct mlx4_dev_cap
*dev_cap
)
1531 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
&&
1532 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
)
1533 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
;
1535 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_NONE
;
1537 mlx4_dbg(dev
, "Tunneling offload mode is: %s\n", (dev
->caps
.tunnel_offload_mode
1538 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) ? "vxlan" : "none");
1541 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1543 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1544 struct mlx4_adapter adapter
;
1545 struct mlx4_dev_cap dev_cap
;
1546 struct mlx4_mod_stat_cfg mlx4_cfg
;
1547 struct mlx4_profile profile
;
1548 struct mlx4_init_hca_param init_hca
;
1552 if (!mlx4_is_slave(dev
)) {
1553 err
= mlx4_QUERY_FW(dev
);
1556 mlx4_info(dev
, "non-primary physical function, skipping\n");
1558 mlx4_err(dev
, "QUERY_FW command failed, aborting\n");
1562 err
= mlx4_load_fw(dev
);
1564 mlx4_err(dev
, "Failed to start FW, aborting\n");
1568 mlx4_cfg
.log_pg_sz_m
= 1;
1569 mlx4_cfg
.log_pg_sz
= 0;
1570 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1572 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1574 err
= mlx4_dev_cap(dev
, &dev_cap
);
1576 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
1580 choose_steering_mode(dev
, &dev_cap
);
1581 choose_tunnel_offload_mode(dev
, &dev_cap
);
1583 err
= mlx4_get_phys_port_id(dev
);
1585 mlx4_err(dev
, "Fail to get physical port id\n");
1587 if (mlx4_is_master(dev
))
1588 mlx4_parav_master_pf_caps(dev
);
1590 profile
= default_profile
;
1591 if (dev
->caps
.steering_mode
==
1592 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1593 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1595 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1597 if ((long long) icm_size
< 0) {
1602 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1604 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1605 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1606 init_hca
.mw_enabled
= 0;
1607 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1608 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1609 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1611 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1615 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1617 mlx4_err(dev
, "INIT_HCA command failed, aborting\n");
1621 * If TS is supported by FW
1622 * read HCA frequency by QUERY_HCA command
1624 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1625 memset(&init_hca
, 0, sizeof(init_hca
));
1626 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1628 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp\n");
1629 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1631 dev
->caps
.hca_core_clock
=
1632 init_hca
.hca_core_clock
;
1635 /* In case we got HCA frequency 0 - disable timestamping
1636 * to avoid dividing by zero
1638 if (!dev
->caps
.hca_core_clock
) {
1639 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1641 "HCA frequency is 0 - timestamping is not supported\n");
1642 } else if (map_internal_clock(dev
)) {
1644 * Map internal clock,
1645 * in case of failure disable timestamping
1647 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1648 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported\n");
1652 err
= mlx4_init_slave(dev
);
1654 if (err
!= -EPROBE_DEFER
)
1655 mlx4_err(dev
, "Failed to initialize slave\n");
1659 err
= mlx4_slave_cap(dev
);
1661 mlx4_err(dev
, "Failed to obtain slave caps\n");
1666 if (map_bf_area(dev
))
1667 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1669 /*Only the master set the ports, all the rest got it from it.*/
1670 if (!mlx4_is_slave(dev
))
1671 mlx4_set_port_mask(dev
);
1673 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1675 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting\n");
1679 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1680 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1685 unmap_internal_clock(dev
);
1688 if (mlx4_is_slave(dev
)) {
1689 kfree(dev
->caps
.qp0_qkey
);
1690 kfree(dev
->caps
.qp0_tunnel
);
1691 kfree(dev
->caps
.qp0_proxy
);
1692 kfree(dev
->caps
.qp1_tunnel
);
1693 kfree(dev
->caps
.qp1_proxy
);
1697 if (mlx4_is_slave(dev
))
1698 mlx4_slave_exit(dev
);
1700 mlx4_CLOSE_HCA(dev
, 0);
1703 if (!mlx4_is_slave(dev
))
1704 mlx4_free_icms(dev
);
1707 if (!mlx4_is_slave(dev
)) {
1709 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1714 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1716 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1719 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1722 nent
= dev
->caps
.max_counters
;
1723 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1726 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1728 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1731 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1733 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1735 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1738 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1745 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1750 if (mlx4_is_mfunc(dev
)) {
1751 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1752 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1753 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1755 *idx
= get_param_l(&out_param
);
1759 return __mlx4_counter_alloc(dev
, idx
);
1761 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1763 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1765 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
, MLX4_USE_RR
);
1769 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1773 if (mlx4_is_mfunc(dev
)) {
1774 set_param_l(&in_param
, idx
);
1775 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1776 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1780 __mlx4_counter_free(dev
, idx
);
1782 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1784 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1786 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1789 __be32 ib_port_default_caps
;
1791 err
= mlx4_init_uar_table(dev
);
1793 mlx4_err(dev
, "Failed to initialize user access region table, aborting\n");
1797 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1799 mlx4_err(dev
, "Failed to allocate driver access region, aborting\n");
1800 goto err_uar_table_free
;
1803 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1805 mlx4_err(dev
, "Couldn't map kernel access region, aborting\n");
1810 err
= mlx4_init_pd_table(dev
);
1812 mlx4_err(dev
, "Failed to initialize protection domain table, aborting\n");
1816 err
= mlx4_init_xrcd_table(dev
);
1818 mlx4_err(dev
, "Failed to initialize reliable connection domain table, aborting\n");
1819 goto err_pd_table_free
;
1822 err
= mlx4_init_mr_table(dev
);
1824 mlx4_err(dev
, "Failed to initialize memory region table, aborting\n");
1825 goto err_xrcd_table_free
;
1828 if (!mlx4_is_slave(dev
)) {
1829 err
= mlx4_init_mcg_table(dev
);
1831 mlx4_err(dev
, "Failed to initialize multicast group table, aborting\n");
1832 goto err_mr_table_free
;
1834 err
= mlx4_config_mad_demux(dev
);
1836 mlx4_err(dev
, "Failed in config_mad_demux, aborting\n");
1837 goto err_mcg_table_free
;
1841 err
= mlx4_init_eq_table(dev
);
1843 mlx4_err(dev
, "Failed to initialize event queue table, aborting\n");
1844 goto err_mcg_table_free
;
1847 err
= mlx4_cmd_use_events(dev
);
1849 mlx4_err(dev
, "Failed to switch to event-driven firmware commands, aborting\n");
1850 goto err_eq_table_free
;
1853 err
= mlx4_NOP(dev
);
1855 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
1856 mlx4_warn(dev
, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
1857 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1858 mlx4_warn(dev
, "Trying again without MSI-X\n");
1860 mlx4_err(dev
, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
1861 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1862 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
1868 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
1870 err
= mlx4_init_cq_table(dev
);
1872 mlx4_err(dev
, "Failed to initialize completion queue table, aborting\n");
1876 err
= mlx4_init_srq_table(dev
);
1878 mlx4_err(dev
, "Failed to initialize shared receive queue table, aborting\n");
1879 goto err_cq_table_free
;
1882 err
= mlx4_init_qp_table(dev
);
1884 mlx4_err(dev
, "Failed to initialize queue pair table, aborting\n");
1885 goto err_srq_table_free
;
1888 err
= mlx4_init_counters_table(dev
);
1889 if (err
&& err
!= -ENOENT
) {
1890 mlx4_err(dev
, "Failed to initialize counters table, aborting\n");
1891 goto err_qp_table_free
;
1894 if (!mlx4_is_slave(dev
)) {
1895 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
1896 ib_port_default_caps
= 0;
1897 err
= mlx4_get_port_ib_caps(dev
, port
,
1898 &ib_port_default_caps
);
1900 mlx4_warn(dev
, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
1902 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
1904 /* initialize per-slave default ib port capabilities */
1905 if (mlx4_is_master(dev
)) {
1907 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1908 if (i
== mlx4_master_func_num(dev
))
1910 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
1911 ib_port_default_caps
;
1915 if (mlx4_is_mfunc(dev
))
1916 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
1918 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
1920 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
1921 dev
->caps
.pkey_table_len
[port
] : -1);
1923 mlx4_err(dev
, "Failed to set port %d, aborting\n",
1925 goto err_counters_table_free
;
1932 err_counters_table_free
:
1933 mlx4_cleanup_counters_table(dev
);
1936 mlx4_cleanup_qp_table(dev
);
1939 mlx4_cleanup_srq_table(dev
);
1942 mlx4_cleanup_cq_table(dev
);
1945 mlx4_cmd_use_polling(dev
);
1948 mlx4_cleanup_eq_table(dev
);
1951 if (!mlx4_is_slave(dev
))
1952 mlx4_cleanup_mcg_table(dev
);
1955 mlx4_cleanup_mr_table(dev
);
1957 err_xrcd_table_free
:
1958 mlx4_cleanup_xrcd_table(dev
);
1961 mlx4_cleanup_pd_table(dev
);
1967 mlx4_uar_free(dev
, &priv
->driver_uar
);
1970 mlx4_cleanup_uar_table(dev
);
1974 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
1976 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1977 struct msix_entry
*entries
;
1978 int nreq
= min_t(int, dev
->caps
.num_ports
*
1979 min_t(int, num_online_cpus() + 1,
1980 MAX_MSIX_P_PORT
) + MSIX_LEGACY_SZ
, MAX_MSIX
);
1984 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
1987 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
1991 for (i
= 0; i
< nreq
; ++i
)
1992 entries
[i
].entry
= i
;
1994 nreq
= pci_enable_msix_range(dev
->pdev
, entries
, 2, nreq
);
1999 } else if (nreq
< MSIX_LEGACY_SZ
+
2000 dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
2001 /*Working in legacy mode , all EQ's shared*/
2002 dev
->caps
.comp_pool
= 0;
2003 dev
->caps
.num_comp_vectors
= nreq
- 1;
2005 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
2006 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
2008 for (i
= 0; i
< nreq
; ++i
)
2009 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
2011 dev
->flags
|= MLX4_FLAG_MSI_X
;
2018 dev
->caps
.num_comp_vectors
= 1;
2019 dev
->caps
.comp_pool
= 0;
2021 for (i
= 0; i
< 2; ++i
)
2022 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
2025 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
2027 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
2032 if (!mlx4_is_slave(dev
)) {
2033 mlx4_init_mac_table(dev
, &info
->mac_table
);
2034 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
2035 mlx4_init_roce_gid_table(dev
, &info
->gid_table
);
2036 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
2039 sprintf(info
->dev_name
, "mlx4_port%d", port
);
2040 info
->port_attr
.attr
.name
= info
->dev_name
;
2041 if (mlx4_is_mfunc(dev
))
2042 info
->port_attr
.attr
.mode
= S_IRUGO
;
2044 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2045 info
->port_attr
.store
= set_port_type
;
2047 info
->port_attr
.show
= show_port_type
;
2048 sysfs_attr_init(&info
->port_attr
.attr
);
2050 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
2052 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
2056 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
2057 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
2058 if (mlx4_is_mfunc(dev
))
2059 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
2061 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2062 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
2064 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
2065 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
2067 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
2069 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
2070 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2077 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
2082 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2083 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
2086 static int mlx4_init_steering(struct mlx4_dev
*dev
)
2088 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2089 int num_entries
= dev
->caps
.num_ports
;
2092 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
2096 for (i
= 0; i
< num_entries
; i
++)
2097 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2098 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
2099 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
2104 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
2106 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2107 struct mlx4_steer_index
*entry
, *tmp_entry
;
2108 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
2109 int num_entries
= dev
->caps
.num_ports
;
2112 for (i
= 0; i
< num_entries
; i
++) {
2113 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2114 list_for_each_entry_safe(pqp
, tmp_pqp
,
2115 &priv
->steer
[i
].promisc_qps
[j
],
2117 list_del(&pqp
->list
);
2120 list_for_each_entry_safe(entry
, tmp_entry
,
2121 &priv
->steer
[i
].steer_entries
[j
],
2123 list_del(&entry
->list
);
2124 list_for_each_entry_safe(pqp
, tmp_pqp
,
2127 list_del(&pqp
->list
);
2137 static int extended_func_num(struct pci_dev
*pdev
)
2139 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2142 #define MLX4_OWNER_BASE 0x8069c
2143 #define MLX4_OWNER_SIZE 4
2145 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2147 void __iomem
*owner
;
2150 if (pci_channel_offline(dev
->pdev
))
2153 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2156 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2165 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2167 void __iomem
*owner
;
2169 if (pci_channel_offline(dev
->pdev
))
2172 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2175 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2183 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
)
2185 struct mlx4_priv
*priv
;
2186 struct mlx4_dev
*dev
;
2189 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2190 int prb_vf
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2191 const int param_map
[MLX4_MAX_PORTS
+ 1][MLX4_MAX_PORTS
+ 1] = {
2192 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2193 unsigned total_vfs
= 0;
2194 int sriov_initialized
= 0;
2197 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2199 err
= pci_enable_device(pdev
);
2201 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
2205 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2206 * per port, we must limit the number of VFs to 63 (since their are
2209 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) && i
< num_vfs_argc
;
2210 total_vfs
+= nvfs
[param_map
[num_vfs_argc
- 1][i
]], i
++) {
2211 nvfs
[param_map
[num_vfs_argc
- 1][i
]] = num_vfs
[i
];
2213 dev_err(&pdev
->dev
, "num_vfs module parameter cannot be negative\n");
2217 for (i
= 0; i
< sizeof(prb_vf
)/sizeof(prb_vf
[0]) && i
< probe_vfs_argc
;
2219 prb_vf
[param_map
[probe_vfs_argc
- 1][i
]] = probe_vf
[i
];
2220 if (prb_vf
[i
] < 0 || prb_vf
[i
] > nvfs
[i
]) {
2221 dev_err(&pdev
->dev
, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2225 if (total_vfs
>= MLX4_MAX_NUM_VF
) {
2227 "Requested more VF's (%d) than allowed (%d)\n",
2228 total_vfs
, MLX4_MAX_NUM_VF
- 1);
2232 for (i
= 0; i
< MLX4_MAX_PORTS
; i
++) {
2233 if (nvfs
[i
] + nvfs
[2] >= MLX4_MAX_NUM_VF_P_PORT
) {
2235 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2236 nvfs
[i
] + nvfs
[2], i
+ 1,
2237 MLX4_MAX_NUM_VF_P_PORT
- 1);
2246 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2247 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2248 dev_err(&pdev
->dev
, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2249 pci_dev_data
, pci_resource_flags(pdev
, 0));
2251 goto err_disable_pdev
;
2253 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2254 dev_err(&pdev
->dev
, "Missing UAR, aborting\n");
2256 goto err_disable_pdev
;
2259 err
= pci_request_regions(pdev
, DRV_NAME
);
2261 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2262 goto err_disable_pdev
;
2265 pci_set_master(pdev
);
2267 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2269 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
2270 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2272 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
2273 goto err_release_regions
;
2276 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2278 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2279 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2281 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, aborting\n");
2282 goto err_release_regions
;
2286 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2287 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2289 dev
= pci_get_drvdata(pdev
);
2290 priv
= mlx4_priv(dev
);
2292 INIT_LIST_HEAD(&priv
->ctx_list
);
2293 spin_lock_init(&priv
->ctx_lock
);
2295 mutex_init(&priv
->port_mutex
);
2297 INIT_LIST_HEAD(&priv
->pgdir_list
);
2298 mutex_init(&priv
->pgdir_mutex
);
2300 INIT_LIST_HEAD(&priv
->bf_list
);
2301 mutex_init(&priv
->bf_mutex
);
2303 dev
->rev_id
= pdev
->revision
;
2304 dev
->numa_node
= dev_to_node(&pdev
->dev
);
2305 /* Detect if this device is a virtual function */
2306 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2307 /* When acting as pf, we normally skip vfs unless explicitly
2308 * requested to probe them. */
2310 unsigned vfs_offset
= 0;
2311 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) &&
2312 vfs_offset
+ nvfs
[i
] < extended_func_num(pdev
);
2313 vfs_offset
+= nvfs
[i
], i
++)
2315 if (i
== sizeof(nvfs
)/sizeof(nvfs
[0])) {
2319 if ((extended_func_num(pdev
) - vfs_offset
)
2321 mlx4_warn(dev
, "Skipping virtual function:%d\n",
2322 extended_func_num(pdev
));
2327 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2328 dev
->flags
|= MLX4_FLAG_SLAVE
;
2330 /* We reset the device and enable SRIOV only for physical
2331 * devices. Try to claim ownership on the device;
2332 * if already taken, skip -- do not allow multiple PFs */
2333 err
= mlx4_get_ownership(dev
);
2338 mlx4_warn(dev
, "Multiple PFs not yet supported - Skipping PF\n");
2345 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n",
2347 dev
->dev_vfs
= kzalloc(
2348 total_vfs
* sizeof(*dev
->dev_vfs
),
2350 if (NULL
== dev
->dev_vfs
) {
2351 mlx4_err(dev
, "Failed to allocate memory for VFs\n");
2354 atomic_inc(&pf_loading
);
2355 err
= pci_enable_sriov(pdev
, total_vfs
);
2357 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2359 atomic_dec(&pf_loading
);
2362 mlx4_warn(dev
, "Running in master mode\n");
2363 dev
->flags
|= MLX4_FLAG_SRIOV
|
2365 dev
->num_vfs
= total_vfs
;
2366 sriov_initialized
= 1;
2371 atomic_set(&priv
->opreq_count
, 0);
2372 INIT_WORK(&priv
->opreq_task
, mlx4_opreq_action
);
2375 * Now reset the HCA before we touch the PCI capabilities or
2376 * attempt a firmware command, since a boot ROM may have left
2377 * the HCA in an undefined state.
2379 err
= mlx4_reset(dev
);
2381 mlx4_err(dev
, "Failed to reset HCA, aborting\n");
2387 err
= mlx4_cmd_init(dev
);
2389 mlx4_err(dev
, "Failed to init command interface, aborting\n");
2393 /* In slave functions, the communication channel must be initialized
2394 * before posting commands. Also, init num_slaves before calling
2396 if (mlx4_is_mfunc(dev
)) {
2397 if (mlx4_is_master(dev
))
2398 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2400 dev
->num_slaves
= 0;
2401 err
= mlx4_multi_func_init(dev
);
2403 mlx4_err(dev
, "Failed to init slave mfunc interface, aborting\n");
2409 err
= mlx4_init_hca(dev
);
2411 if (err
== -EACCES
) {
2412 /* Not primary Physical function
2413 * Running in slave mode */
2414 mlx4_cmd_cleanup(dev
);
2415 dev
->flags
|= MLX4_FLAG_SLAVE
;
2416 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2422 /* check if the device is functioning at its maximum possible speed.
2423 * No return code for this call, just warn the user in case of PCI
2424 * express device capabilities are under-satisfied by the bus.
2426 if (!mlx4_is_slave(dev
))
2427 mlx4_check_pcie_caps(dev
);
2429 /* In master functions, the communication channel must be initialized
2430 * after obtaining its address from fw */
2431 if (mlx4_is_master(dev
)) {
2433 err
= mlx4_multi_func_init(dev
);
2435 mlx4_err(dev
, "Failed to init master mfunc interface, aborting\n");
2438 if (sriov_initialized
) {
2440 mlx4_foreach_port(i
, dev
, MLX4_PORT_TYPE_IB
)
2444 (num_vfs_argc
> 1 || probe_vfs_argc
> 1)) {
2446 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2448 goto err_master_mfunc
;
2450 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]); i
++) {
2452 for (j
= 0; j
< nvfs
[i
]; ++sum
, ++j
) {
2453 dev
->dev_vfs
[sum
].min_port
=
2455 dev
->dev_vfs
[sum
].n_ports
= i
< 2 ? 1 :
2456 dev
->caps
.num_ports
;
2462 err
= mlx4_alloc_eq_table(dev
);
2464 goto err_master_mfunc
;
2466 priv
->msix_ctl
.pool_bm
= 0;
2467 mutex_init(&priv
->msix_ctl
.pool_lock
);
2469 mlx4_enable_msi_x(dev
);
2470 if ((mlx4_is_mfunc(dev
)) &&
2471 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2473 mlx4_err(dev
, "INTx is not supported in multi-function mode, aborting\n");
2477 if (!mlx4_is_slave(dev
)) {
2478 err
= mlx4_init_steering(dev
);
2483 err
= mlx4_setup_hca(dev
);
2484 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2485 !mlx4_is_mfunc(dev
)) {
2486 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2487 dev
->caps
.num_comp_vectors
= 1;
2488 dev
->caps
.comp_pool
= 0;
2489 pci_disable_msix(pdev
);
2490 err
= mlx4_setup_hca(dev
);
2496 mlx4_init_quotas(dev
);
2498 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2499 err
= mlx4_init_port_info(dev
, port
);
2504 err
= mlx4_register_device(dev
);
2508 mlx4_request_modules(dev
);
2510 mlx4_sense_init(dev
);
2511 mlx4_start_sense(dev
);
2515 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2516 atomic_dec(&pf_loading
);
2521 for (--port
; port
>= 1; --port
)
2522 mlx4_cleanup_port_info(&priv
->port
[port
]);
2524 mlx4_cleanup_counters_table(dev
);
2525 mlx4_cleanup_qp_table(dev
);
2526 mlx4_cleanup_srq_table(dev
);
2527 mlx4_cleanup_cq_table(dev
);
2528 mlx4_cmd_use_polling(dev
);
2529 mlx4_cleanup_eq_table(dev
);
2530 mlx4_cleanup_mcg_table(dev
);
2531 mlx4_cleanup_mr_table(dev
);
2532 mlx4_cleanup_xrcd_table(dev
);
2533 mlx4_cleanup_pd_table(dev
);
2534 mlx4_cleanup_uar_table(dev
);
2537 if (!mlx4_is_slave(dev
))
2538 mlx4_clear_steering(dev
);
2541 mlx4_free_eq_table(dev
);
2544 if (mlx4_is_master(dev
))
2545 mlx4_multi_func_cleanup(dev
);
2547 if (mlx4_is_slave(dev
)) {
2548 kfree(dev
->caps
.qp0_qkey
);
2549 kfree(dev
->caps
.qp0_tunnel
);
2550 kfree(dev
->caps
.qp0_proxy
);
2551 kfree(dev
->caps
.qp1_tunnel
);
2552 kfree(dev
->caps
.qp1_proxy
);
2556 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2557 pci_disable_msix(pdev
);
2559 mlx4_close_hca(dev
);
2562 if (mlx4_is_slave(dev
))
2563 mlx4_multi_func_cleanup(dev
);
2566 mlx4_cmd_cleanup(dev
);
2569 if (dev
->flags
& MLX4_FLAG_SRIOV
)
2570 pci_disable_sriov(pdev
);
2573 if (!mlx4_is_slave(dev
))
2574 mlx4_free_ownership(dev
);
2576 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2577 atomic_dec(&pf_loading
);
2579 kfree(priv
->dev
.dev_vfs
);
2584 err_release_regions
:
2585 pci_release_regions(pdev
);
2588 pci_disable_device(pdev
);
2589 pci_set_drvdata(pdev
, NULL
);
2593 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2595 struct mlx4_priv
*priv
;
2596 struct mlx4_dev
*dev
;
2598 printk_once(KERN_INFO
"%s", mlx4_version
);
2600 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2605 pci_set_drvdata(pdev
, dev
);
2606 priv
->pci_dev_data
= id
->driver_data
;
2608 return __mlx4_init_one(pdev
, id
->driver_data
);
2611 static void __mlx4_remove_one(struct pci_dev
*pdev
)
2613 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2614 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2621 pci_dev_data
= priv
->pci_dev_data
;
2623 /* in SRIOV it is not allowed to unload the pf's
2624 * driver while there are alive vf's */
2625 if (mlx4_is_master(dev
) && mlx4_how_many_lives_vf(dev
))
2626 pr_warn("Removing PF when there are assigned VF's !!!\n");
2627 mlx4_stop_sense(dev
);
2628 mlx4_unregister_device(dev
);
2630 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2631 mlx4_cleanup_port_info(&priv
->port
[p
]);
2632 mlx4_CLOSE_PORT(dev
, p
);
2635 if (mlx4_is_master(dev
))
2636 mlx4_free_resource_tracker(dev
,
2637 RES_TR_FREE_SLAVES_ONLY
);
2639 mlx4_cleanup_counters_table(dev
);
2640 mlx4_cleanup_qp_table(dev
);
2641 mlx4_cleanup_srq_table(dev
);
2642 mlx4_cleanup_cq_table(dev
);
2643 mlx4_cmd_use_polling(dev
);
2644 mlx4_cleanup_eq_table(dev
);
2645 mlx4_cleanup_mcg_table(dev
);
2646 mlx4_cleanup_mr_table(dev
);
2647 mlx4_cleanup_xrcd_table(dev
);
2648 mlx4_cleanup_pd_table(dev
);
2650 if (mlx4_is_master(dev
))
2651 mlx4_free_resource_tracker(dev
,
2652 RES_TR_FREE_STRUCTS_ONLY
);
2655 mlx4_uar_free(dev
, &priv
->driver_uar
);
2656 mlx4_cleanup_uar_table(dev
);
2657 if (!mlx4_is_slave(dev
))
2658 mlx4_clear_steering(dev
);
2659 mlx4_free_eq_table(dev
);
2660 if (mlx4_is_master(dev
))
2661 mlx4_multi_func_cleanup(dev
);
2662 mlx4_close_hca(dev
);
2663 if (mlx4_is_slave(dev
))
2664 mlx4_multi_func_cleanup(dev
);
2665 mlx4_cmd_cleanup(dev
);
2667 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2668 pci_disable_msix(pdev
);
2669 if (dev
->flags
& MLX4_FLAG_SRIOV
) {
2670 mlx4_warn(dev
, "Disabling SR-IOV\n");
2671 pci_disable_sriov(pdev
);
2675 if (!mlx4_is_slave(dev
))
2676 mlx4_free_ownership(dev
);
2678 kfree(dev
->caps
.qp0_qkey
);
2679 kfree(dev
->caps
.qp0_tunnel
);
2680 kfree(dev
->caps
.qp0_proxy
);
2681 kfree(dev
->caps
.qp1_tunnel
);
2682 kfree(dev
->caps
.qp1_proxy
);
2683 kfree(dev
->dev_vfs
);
2685 pci_release_regions(pdev
);
2686 pci_disable_device(pdev
);
2687 memset(priv
, 0, sizeof(*priv
));
2688 priv
->pci_dev_data
= pci_dev_data
;
2692 static void mlx4_remove_one(struct pci_dev
*pdev
)
2694 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2695 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2697 __mlx4_remove_one(pdev
);
2699 pci_set_drvdata(pdev
, NULL
);
2702 int mlx4_restart_one(struct pci_dev
*pdev
)
2704 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2705 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2708 pci_dev_data
= priv
->pci_dev_data
;
2709 __mlx4_remove_one(pdev
);
2710 return __mlx4_init_one(pdev
, pci_dev_data
);
2713 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table
) = {
2714 /* MT25408 "Hermon" SDR */
2715 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2716 /* MT25408 "Hermon" DDR */
2717 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2718 /* MT25408 "Hermon" QDR */
2719 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2720 /* MT25408 "Hermon" DDR PCIe gen2 */
2721 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2722 /* MT25408 "Hermon" QDR PCIe gen2 */
2723 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2724 /* MT25408 "Hermon" EN 10GigE */
2725 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2726 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2727 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2728 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2729 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2730 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2731 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2732 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2733 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2734 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2735 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2736 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2737 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2738 /* MT25400 Family [ConnectX-2 Virtual Function] */
2739 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
2740 /* MT27500 Family [ConnectX-3] */
2741 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
2742 /* MT27500 Family [ConnectX-3 Virtual Function] */
2743 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
2744 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
2745 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
2746 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
2747 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
2748 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
2749 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
2750 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
2751 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
2752 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
2753 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
2754 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
2755 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
2759 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
2761 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
2762 pci_channel_state_t state
)
2764 __mlx4_remove_one(pdev
);
2766 return state
== pci_channel_io_perm_failure
?
2767 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
2770 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
2772 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2773 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2776 ret
= __mlx4_init_one(pdev
, priv
->pci_dev_data
);
2778 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
2781 static const struct pci_error_handlers mlx4_err_handler
= {
2782 .error_detected
= mlx4_pci_err_detected
,
2783 .slot_reset
= mlx4_pci_slot_reset
,
2786 static struct pci_driver mlx4_driver
= {
2788 .id_table
= mlx4_pci_table
,
2789 .probe
= mlx4_init_one
,
2790 .shutdown
= __mlx4_remove_one
,
2791 .remove
= mlx4_remove_one
,
2792 .err_handler
= &mlx4_err_handler
,
2795 static int __init
mlx4_verify_params(void)
2797 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
2798 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac
);
2802 if (log_num_vlan
!= 0)
2803 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2804 MLX4_LOG_NUM_VLANS
);
2807 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
2809 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
2810 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
2815 /* Check if module param for ports type has legal combination */
2816 if (port_type_array
[0] == false && port_type_array
[1] == true) {
2817 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2818 port_type_array
[0] = true;
2821 if (mlx4_log_num_mgm_entry_size
!= -1 &&
2822 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
2823 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
2824 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
2825 mlx4_log_num_mgm_entry_size
,
2826 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
2827 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
2834 static int __init
mlx4_init(void)
2838 if (mlx4_verify_params())
2843 mlx4_wq
= create_singlethread_workqueue("mlx4");
2847 ret
= pci_register_driver(&mlx4_driver
);
2849 destroy_workqueue(mlx4_wq
);
2850 return ret
< 0 ? ret
: 0;
2853 static void __exit
mlx4_cleanup(void)
2855 pci_unregister_driver(&mlx4_driver
);
2856 destroy_workqueue(mlx4_wq
);
2859 module_init(mlx4_init
);
2860 module_exit(mlx4_cleanup
);