drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/spinlock.h>
  48 #include <net/devlink.h>
  49 #include <linux/rwsem.h>
  50
  51 #include <linux/mlx4/device.h>
  52 #include <linux/mlx4/driver.h>
  53 #include <linux/mlx4/doorbell.h>
  54 #include <linux/mlx4/cmd.h>
  55 #include "fw_qos.h"
  56
  57 #define DRV_NAME        "mlx4_core"
  58 #define PFX             DRV_NAME ": "
  59 #define DRV_VERSION     "2.2-1"
  60 #define DRV_RELDATE     "Feb, 2014"
  61
  62 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  63 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  64 #define MLX4_FS_NUM_OF_L2_ADDR          8
  65 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  66 #define MLX4_FS_NUM_MCG                 (1 << 17)
  67
  68 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
  69
  70 #define MLX4_QUERY_IF_STAT_RESET        BIT(31)
  71
  72 enum {
  73         MLX4_HCR_BASE           = 0x80680,
  74         MLX4_HCR_SIZE           = 0x0001c,
  75         MLX4_CLR_INT_SIZE       = 0x00008,
  76         MLX4_SLAVE_COMM_BASE    = 0x0,
  77         MLX4_COMM_PAGESIZE      = 0x1000,
  78         MLX4_CLOCK_SIZE         = 0x00008,
  79         MLX4_COMM_CHAN_CAPS     = 0x8,
  80         MLX4_COMM_CHAN_FLAGS    = 0xc
  81 };
  82
  83 enum {
  84         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
  85         MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
  86         MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
  87         MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
  88         MLX4_MTT_ENTRY_PER_SEG  = 8,
  89 };
  90
  91 enum {
  92         MLX4_NUM_PDS            = 1 << 15
  93 };
  94
  95 enum {
  96         MLX4_CMPT_TYPE_QP       = 0,
  97         MLX4_CMPT_TYPE_SRQ      = 1,
  98         MLX4_CMPT_TYPE_CQ       = 2,
  99         MLX4_CMPT_TYPE_EQ       = 3,
 100         MLX4_CMPT_NUM_TYPE
 101 };
 102
 103 enum {
 104         MLX4_CMPT_SHIFT         = 24,
 105         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 106 };
 107
 108 enum mlx4_mpt_state {
 109         MLX4_MPT_DISABLED = 0,
 110         MLX4_MPT_EN_HW,
 111         MLX4_MPT_EN_SW
 112 };
 113
 114 #define MLX4_COMM_TIME          10000
 115 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
 116 #define MLX4_COMM_CMD_NA_OP    0x0
 117
 118
 119 enum {
 120         MLX4_COMM_CMD_RESET,
 121         MLX4_COMM_CMD_VHCR0,
 122         MLX4_COMM_CMD_VHCR1,
 123         MLX4_COMM_CMD_VHCR2,
 124         MLX4_COMM_CMD_VHCR_EN,
 125         MLX4_COMM_CMD_VHCR_POST,
 126         MLX4_COMM_CMD_FLR = 254
 127 };
 128
 129 enum {
 130         MLX4_VF_SMI_DISABLED,
 131         MLX4_VF_SMI_ENABLED
 132 };
 133
 134 /*The flag indicates that the slave should delay the RESET cmd*/
 135 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 136 /*indicates how many retries will be done if we are in the middle of FLR*/
 137 #define NUM_OF_RESET_RETRIES    10
 138 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 139 enum mlx4_resource {
 140         RES_QP,
 141         RES_CQ,
 142         RES_SRQ,
 143         RES_XRCD,
 144         RES_MPT,
 145         RES_MTT,
 146         RES_MAC,
 147         RES_VLAN,
 148         RES_NPORT_ID,
 149         RES_COUNTER,
 150         RES_FS_RULE,
 151         RES_EQ,
 152         MLX4_NUM_OF_RESOURCE_TYPE
 153 };
 154
 155 enum mlx4_alloc_mode {
 156         RES_OP_RESERVE,
 157         RES_OP_RESERVE_AND_MAP,
 158         RES_OP_MAP_ICM,
 159 };
 160
 161 enum mlx4_res_tracker_free_type {
 162         RES_TR_FREE_ALL,
 163         RES_TR_FREE_SLAVES_ONLY,
 164         RES_TR_FREE_STRUCTS_ONLY,
 165 };
 166
 167 /*
 168  *Virtual HCR structures.
 169  * mlx4_vhcr is the sw representation, in machine endianness
 170  *
 171  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 172  * to FW to go through communication channel.
 173  * It is big endian, and has the same structure as the physical HCR
 174  * used by command interface
 175  */
 176 struct mlx4_vhcr {
 177         u64     in_param;
 178         u64     out_param;
 179         u32     in_modifier;
 180         u32     errno;
 181         u16     op;
 182         u16     token;
 183         u8      op_modifier;
 184         u8      e_bit;
 185 };
 186
 187 struct mlx4_vhcr_cmd {
 188         __be64 in_param;
 189         __be32 in_modifier;
 190         u32 reserved1;
 191         __be64 out_param;
 192         __be16 token;
 193         u16 reserved;
 194         u8 status;
 195         u8 flags;
 196         __be16 opcode;
 197 };
 198
 199 struct mlx4_cmd_info {
 200         u16 opcode;
 201         bool has_inbox;
 202         bool has_outbox;
 203         bool out_is_imm;
 204         bool encode_slave_id;
 205         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 206                       struct mlx4_cmd_mailbox *inbox);
 207         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 208                        struct mlx4_cmd_mailbox *inbox,
 209                        struct mlx4_cmd_mailbox *outbox,
 210                        struct mlx4_cmd_info *cmd);
 211 };
 212
 213 #ifdef CONFIG_MLX4_DEBUG
 214 extern int mlx4_debug_level;
 215 #else /* CONFIG_MLX4_DEBUG */
 216 #define mlx4_debug_level        (0)
 217 #endif /* CONFIG_MLX4_DEBUG */
 218
 219 #define mlx4_dbg(mdev, format, ...)                                     \
 220 do {                                                                    \
 221         if (mlx4_debug_level)                                           \
 222                 dev_printk(KERN_DEBUG,                                  \
 223                            &(mdev)->persist->pdev->dev, format,         \
 224                            ##__VA_ARGS__);                              \
 225 } while (0)
 226
 227 #define mlx4_err(mdev, format, ...)                                     \
 228         dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 229 #define mlx4_info(mdev, format, ...)                                    \
 230         dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 231 #define mlx4_warn(mdev, format, ...)                                    \
 232         dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 233
 234 extern int mlx4_log_num_mgm_entry_size;
 235 extern int log_mtts_per_seg;
 236 extern int mlx4_internal_err_reset;
 237
 238 #define MLX4_MAX_NUM_SLAVES     (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
 239                                      MLX4_MFUNC_MAX))
 240 #define ALL_SLAVES 0xff
 241
 242 struct mlx4_bitmap {
 243         u32                     last;
 244         u32                     top;
 245         u32                     max;
 246         u32                     reserved_top;
 247         u32                     mask;
 248         u32                     avail;
 249         u32                     effective_len;
 250         spinlock_t              lock;
 251         unsigned long          *table;
 252 };
 253
 254 struct mlx4_buddy {
 255         unsigned long         **bits;
 256         unsigned int           *num_free;
 257         u32                     max_order;
 258         spinlock_t              lock;
 259 };
 260
 261 struct mlx4_icm;
 262
 263 struct mlx4_icm_table {
 264         u64                     virt;
 265         int                     num_icm;
 266         u32                     num_obj;
 267         int                     obj_size;
 268         int                     lowmem;
 269         int                     coherent;
 270         struct mutex            mutex;
 271         struct mlx4_icm       **icm;
 272 };
 273
 274 #define MLX4_MPT_FLAG_SW_OWNS       (0xfUL << 28)
 275 #define MLX4_MPT_FLAG_FREE          (0x3UL << 28)
 276 #define MLX4_MPT_FLAG_MIO           (1 << 17)
 277 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
 278 #define MLX4_MPT_FLAG_PHYSICAL      (1 <<  9)
 279 #define MLX4_MPT_FLAG_REGION        (1 <<  8)
 280
 281 #define MLX4_MPT_PD_MASK            (0x1FFFFUL)
 282 #define MLX4_MPT_PD_VF_MASK         (0xFE0000UL)
 283 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
 284 #define MLX4_MPT_PD_FLAG_RAE        (1 << 28)
 285 #define MLX4_MPT_PD_FLAG_EN_INV     (3 << 24)
 286
 287 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
 288
 289 #define MLX4_MPT_STATUS_SW              0xF0
 290 #define MLX4_MPT_STATUS_HW              0x00
 291
 292 #define MLX4_CQE_SIZE_MASK_STRIDE       0x3
 293 #define MLX4_EQE_SIZE_MASK_STRIDE       0x30
 294
 295 #define MLX4_EQ_ASYNC                   0
 296 #define MLX4_EQ_TO_CQ_VECTOR(vector)    ((vector) - \
 297                                          !!((int)(vector) >= MLX4_EQ_ASYNC))
 298 #define MLX4_CQ_TO_EQ_VECTOR(vector)    ((vector) + \
 299                                          !!((int)(vector) >= MLX4_EQ_ASYNC))
 300
 301 /*
 302  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 303  */
 304 struct mlx4_mpt_entry {
 305         __be32 flags;
 306         __be32 qpn;
 307         __be32 key;
 308         __be32 pd_flags;
 309         __be64 start;
 310         __be64 length;
 311         __be32 lkey;
 312         __be32 win_cnt;
 313         u8      reserved1[3];
 314         u8      mtt_rep;
 315         __be64 mtt_addr;
 316         __be32 mtt_sz;
 317         __be32 entity_size;
 318         __be32 first_byte_offset;
 319 } __packed;
 320
 321 /*
 322  * Must be packed because start is 64 bits but only aligned to 32 bits.
 323  */
 324 struct mlx4_eq_context {
 325         __be32                  flags;
 326         u16                     reserved1[3];
 327         __be16                  page_offset;
 328         u8                      log_eq_size;
 329         u8                      reserved2[4];
 330         u8                      eq_period;
 331         u8                      reserved3;
 332         u8                      eq_max_count;
 333         u8                      reserved4[3];
 334         u8                      intr;
 335         u8                      log_page_size;
 336         u8                      reserved5[2];
 337         u8                      mtt_base_addr_h;
 338         __be32                  mtt_base_addr_l;
 339         u32                     reserved6[2];
 340         __be32                  consumer_index;
 341         __be32                  producer_index;
 342         u32                     reserved7[4];
 343 };
 344
 345 struct mlx4_cq_context {
 346         __be32                  flags;
 347         u16                     reserved1[3];
 348         __be16                  page_offset;
 349         __be32                  logsize_usrpage;
 350         __be16                  cq_period;
 351         __be16                  cq_max_count;
 352         u8                      reserved2[3];
 353         u8                      comp_eqn;
 354         u8                      log_page_size;
 355         u8                      reserved3[2];
 356         u8                      mtt_base_addr_h;
 357         __be32                  mtt_base_addr_l;
 358         __be32                  last_notified_index;
 359         __be32                  solicit_producer_index;
 360         __be32                  consumer_index;
 361         __be32                  producer_index;
 362         u32                     reserved4[2];
 363         __be64                  db_rec_addr;
 364 };
 365
 366 struct mlx4_srq_context {
 367         __be32                  state_logsize_srqn;
 368         u8                      logstride;
 369         u8                      reserved1;
 370         __be16                  xrcd;
 371         __be32                  pg_offset_cqn;
 372         u32                     reserved2;
 373         u8                      log_page_size;
 374         u8                      reserved3[2];
 375         u8                      mtt_base_addr_h;
 376         __be32                  mtt_base_addr_l;
 377         __be32                  pd;
 378         __be16                  limit_watermark;
 379         __be16                  wqe_cnt;
 380         u16                     reserved4;
 381         __be16                  wqe_counter;
 382         u32                     reserved5;
 383         __be64                  db_rec_addr;
 384 };
 385
 386 struct mlx4_eq_tasklet {
 387         struct list_head list;
 388         struct list_head process_list;
 389         struct tasklet_struct task;
 390         /* lock on completion tasklet list */
 391         spinlock_t lock;
 392 };
 393
 394 struct mlx4_eq {
 395         struct mlx4_dev        *dev;
 396         void __iomem           *doorbell;
 397         int                     eqn;
 398         u32                     cons_index;
 399         u16                     irq;
 400         u16                     have_irq;
 401         int                     nent;
 402         struct mlx4_buf_list   *page_list;
 403         struct mlx4_mtt         mtt;
 404         struct mlx4_eq_tasklet  tasklet_ctx;
 405         struct mlx4_active_ports actv_ports;
 406         u32                     ref_count;
 407         cpumask_var_t           affinity_mask;
 408 };
 409
 410 struct mlx4_slave_eqe {
 411         u8 type;
 412         u8 port;
 413         u32 param;
 414 };
 415
 416 struct mlx4_slave_event_eq_info {
 417         int eqn;
 418         u16 token;
 419 };
 420
 421 struct mlx4_profile {
 422         int                     num_qp;
 423         int                     rdmarc_per_qp;
 424         int                     num_srq;
 425         int                     num_cq;
 426         int                     num_mcg;
 427         int                     num_mpt;
 428         unsigned                num_mtt;
 429 };
 430
 431 struct mlx4_fw {
 432         u64                     clr_int_base;
 433         u64                     catas_offset;
 434         u64                     comm_base;
 435         u64                     clock_offset;
 436         struct mlx4_icm        *fw_icm;
 437         struct mlx4_icm        *aux_icm;
 438         u32                     catas_size;
 439         u16                     fw_pages;
 440         u8                      clr_int_bar;
 441         u8                      catas_bar;
 442         u8                      comm_bar;
 443         u8                      clock_bar;
 444 };
 445
 446 struct mlx4_comm {
 447         u32                     slave_write;
 448         u32                     slave_read;
 449 };
 450
 451 enum {
 452         MLX4_MCAST_CONFIG       = 0,
 453         MLX4_MCAST_DISABLE      = 1,
 454         MLX4_MCAST_ENABLE       = 2,
 455 };
 456
 457 #define VLAN_FLTR_SIZE  128
 458
 459 struct mlx4_vlan_fltr {
 460         __be32 entry[VLAN_FLTR_SIZE];
 461 };
 462
 463 struct mlx4_mcast_entry {
 464         struct list_head list;
 465         u64 addr;
 466 };
 467
 468 struct mlx4_promisc_qp {
 469         struct list_head list;
 470         u32 qpn;
 471 };
 472
 473 struct mlx4_steer_index {
 474         struct list_head list;
 475         unsigned int index;
 476         struct list_head duplicates;
 477 };
 478
 479 #define MLX4_EVENT_TYPES_NUM 64
 480
 481 struct mlx4_slave_state {
 482         u8 comm_toggle;
 483         u8 last_cmd;
 484         u8 init_port_mask;
 485         bool active;
 486         bool old_vlan_api;
 487         bool vst_qinq_supported;
 488         u8 function;
 489         dma_addr_t vhcr_dma;
 490         u16 mtu[MLX4_MAX_PORTS + 1];
 491         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 492         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 493         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 494         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 495         /* event type to eq number lookup */
 496         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 497         u16 eq_pi;
 498         u16 eq_ci;
 499         spinlock_t lock;
 500         /*initialized via the kzalloc*/
 501         u8 is_slave_going_down;
 502         u32 cookie;
 503         enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
 504 };
 505
 506 #define MLX4_VGT 4095
 507 #define NO_INDX  (-1)
 508
 509 struct mlx4_vport_state {
 510         u64 mac;
 511         u16 default_vlan;
 512         u8  default_qos;
 513         __be16 vlan_proto;
 514         u32 tx_rate;
 515         bool spoofchk;
 516         u32 link_state;
 517         u8 qos_vport;
 518         __be64 guid;
 519 };
 520
 521 struct mlx4_vf_admin_state {
 522         struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
 523         u8 enable_smi[MLX4_MAX_PORTS + 1];
 524 };
 525
 526 struct mlx4_vport_oper_state {
 527         struct mlx4_vport_state state;
 528         int mac_idx;
 529         int vlan_idx;
 530 };
 531
 532 struct mlx4_vf_oper_state {
 533         struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
 534         u8 smi_enabled[MLX4_MAX_PORTS + 1];
 535 };
 536
 537 struct slave_list {
 538         struct mutex mutex;
 539         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 540 };
 541
 542 struct resource_allocator {
 543         spinlock_t alloc_lock; /* protect quotas */
 544         union {
 545                 int res_reserved;
 546                 int res_port_rsvd[MLX4_MAX_PORTS];
 547         };
 548         union {
 549                 int res_free;
 550                 int res_port_free[MLX4_MAX_PORTS];
 551         };
 552         int *quota;
 553         int *allocated;
 554         int *guaranteed;
 555 };
 556
 557 struct mlx4_resource_tracker {
 558         spinlock_t lock;
 559         /* tree for each resources */
 560         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 561         /* num_of_slave's lists, one per slave */
 562         struct slave_list *slave_list;
 563         struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
 564 };
 565
 566 #define SLAVE_EVENT_EQ_SIZE     128
 567 struct mlx4_slave_event_eq {
 568         u32 eqn;
 569         u32 cons;
 570         u32 prod;
 571         spinlock_t event_lock;
 572         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 573 };
 574
 575 struct mlx4_qos_manager {
 576         int num_of_qos_vfs;
 577         DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
 578 };
 579
 580 struct mlx4_master_qp0_state {
 581         int proxy_qp0_active;
 582         int qp0_active;
 583         int port_active;
 584 };
 585
 586 struct mlx4_mfunc_master_ctx {
 587         struct mlx4_slave_state *slave_state;
 588         struct mlx4_vf_admin_state *vf_admin;
 589         struct mlx4_vf_oper_state *vf_oper;
 590         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 591         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 592         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 593         u8                      pptx;
 594         u8                      pprx;
 595         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 596         struct mlx4_resource_tracker res_tracker;
 597         struct workqueue_struct *comm_wq;
 598         struct work_struct      comm_work;
 599         struct work_struct      slave_event_work;
 600         struct work_struct      slave_flr_event_work;
 601         spinlock_t              slave_state_lock;
 602         __be32                  comm_arm_bit_vector[4];
 603         struct mlx4_eqe         cmd_eqe;
 604         struct mlx4_slave_event_eq slave_eq;
 605         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 606         struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
 607 };
 608
 609 struct mlx4_mfunc {
 610         struct mlx4_comm __iomem       *comm;
 611         struct mlx4_vhcr_cmd           *vhcr;
 612         dma_addr_t                      vhcr_dma;
 613
 614         struct mlx4_mfunc_master_ctx    master;
 615 };
 616
 617 #define MGM_QPN_MASK       0x00FFFFFF
 618 #define MGM_BLCK_LB_BIT    30
 619
 620 struct mlx4_mgm {
 621         __be32                  next_gid_index;
 622         __be32                  members_count;
 623         u32                     reserved[2];
 624         u8                      gid[16];
 625         __be32                  qp[MLX4_MAX_QP_PER_MGM];
 626 };
 627
 628 struct mlx4_cmd {
 629         struct pci_pool        *pool;
 630         void __iomem           *hcr;
 631         struct mutex            slave_cmd_mutex;
 632         struct semaphore        poll_sem;
 633         struct semaphore        event_sem;
 634         struct rw_semaphore     switch_sem;
 635         int                     max_cmds;
 636         spinlock_t              context_lock;
 637         int                     free_head;
 638         struct mlx4_cmd_context *context;
 639         u16                     token_mask;
 640         u8                      use_events;
 641         u8                      toggle;
 642         u8                      comm_toggle;
 643         u8                      initialized;
 644 };
 645
 646 enum {
 647         MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
 648         MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
 649         MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
 650 };
 651 struct mlx4_vf_immed_vlan_work {
 652         struct work_struct      work;
 653         struct mlx4_priv        *priv;
 654         int                     flags;
 655         int                     slave;
 656         int                     vlan_ix;
 657         int                     orig_vlan_ix;
 658         u8                      port;
 659         u8                      qos;
 660         u8                      qos_vport;
 661         u16                     vlan_id;
 662         u16                     orig_vlan_id;
 663         __be16                  vlan_proto;
 664 };
 665
 666
 667 struct mlx4_uar_table {
 668         struct mlx4_bitmap      bitmap;
 669 };
 670
 671 struct mlx4_mr_table {
 672         struct mlx4_bitmap      mpt_bitmap;
 673         struct mlx4_buddy       mtt_buddy;
 674         u64                     mtt_base;
 675         u64                     mpt_base;
 676         struct mlx4_icm_table   mtt_table;
 677         struct mlx4_icm_table   dmpt_table;
 678 };
 679
 680 struct mlx4_cq_table {
 681         struct mlx4_bitmap      bitmap;
 682         spinlock_t              lock;
 683         struct radix_tree_root  tree;
 684         struct mlx4_icm_table   table;
 685         struct mlx4_icm_table   cmpt_table;
 686 };
 687
 688 struct mlx4_eq_table {
 689         struct mlx4_bitmap      bitmap;
 690         char                   *irq_names;
 691         void __iomem           *clr_int;
 692         void __iomem          **uar_map;
 693         u32                     clr_mask;
 694         struct mlx4_eq         *eq;
 695         struct mlx4_icm_table   table;
 696         struct mlx4_icm_table   cmpt_table;
 697         int                     have_irq;
 698         u8                      inta_pin;
 699 };
 700
 701 struct mlx4_srq_table {
 702         struct mlx4_bitmap      bitmap;
 703         spinlock_t              lock;
 704         struct radix_tree_root  tree;
 705         struct mlx4_icm_table   table;
 706         struct mlx4_icm_table   cmpt_table;
 707 };
 708
 709 enum mlx4_qp_table_zones {
 710         MLX4_QP_TABLE_ZONE_GENERAL,
 711         MLX4_QP_TABLE_ZONE_RSS,
 712         MLX4_QP_TABLE_ZONE_RAW_ETH,
 713         MLX4_QP_TABLE_ZONE_NUM
 714 };
 715
 716 struct mlx4_qp_table {
 717         struct mlx4_bitmap      *bitmap_gen;
 718         struct mlx4_zone_allocator *zones;
 719         u32                     zones_uids[MLX4_QP_TABLE_ZONE_NUM];
 720         u32                     rdmarc_base;
 721         int                     rdmarc_shift;
 722         spinlock_t              lock;
 723         struct mlx4_icm_table   qp_table;
 724         struct mlx4_icm_table   auxc_table;
 725         struct mlx4_icm_table   altc_table;
 726         struct mlx4_icm_table   rdmarc_table;
 727         struct mlx4_icm_table   cmpt_table;
 728 };
 729
 730 struct mlx4_mcg_table {
 731         struct mutex            mutex;
 732         struct mlx4_bitmap      bitmap;
 733         struct mlx4_icm_table   table;
 734 };
 735
 736 struct mlx4_catas_err {
 737         u32 __iomem            *map;
 738         struct timer_list       timer;
 739         struct list_head        list;
 740 };
 741
 742 #define MLX4_MAX_MAC_NUM        128
 743 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 744
 745 struct mlx4_mac_table {
 746         __be64                  entries[MLX4_MAX_MAC_NUM];
 747         int                     refs[MLX4_MAX_MAC_NUM];
 748         bool                    is_dup[MLX4_MAX_MAC_NUM];
 749         struct mutex            mutex;
 750         int                     total;
 751         int                     max;
 752 };
 753
 754 #define MLX4_ROCE_GID_ENTRY_SIZE        16
 755
 756 struct mlx4_roce_gid_entry {
 757         u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
 758 };
 759
 760 struct mlx4_roce_gid_table {
 761         struct mlx4_roce_gid_entry      roce_gids[MLX4_ROCE_MAX_GIDS];
 762         struct mutex                    mutex;
 763 };
 764
 765 #define MLX4_MAX_VLAN_NUM       128
 766 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 767
 768 struct mlx4_vlan_table {
 769         __be32                  entries[MLX4_MAX_VLAN_NUM];
 770         int                     refs[MLX4_MAX_VLAN_NUM];
 771         int                     is_dup[MLX4_MAX_VLAN_NUM];
 772         struct mutex            mutex;
 773         int                     total;
 774         int                     max;
 775 };
 776
 777 #define SET_PORT_GEN_ALL_VALID          0x7
 778 #define SET_PORT_PROMISC_SHIFT          31
 779 #define SET_PORT_MC_PROMISC_SHIFT       30
 780
 781 enum {
 782         MCAST_DIRECT_ONLY       = 0,
 783         MCAST_DIRECT            = 1,
 784         MCAST_DEFAULT           = 2
 785 };
 786
 787
 788 struct mlx4_set_port_general_context {
 789         u16 reserved1;
 790         u8 v_ignore_fcs;
 791         u8 flags;
 792         union {
 793                 u8 ignore_fcs;
 794                 u8 roce_mode;
 795         };
 796         u8 reserved2;
 797         __be16 mtu;
 798         u8 pptx;
 799         u8 pfctx;
 800         u16 reserved3;
 801         u8 pprx;
 802         u8 pfcrx;
 803         u16 reserved4;
 804         u32 reserved5;
 805         u8 phv_en;
 806         u8 reserved6[3];
 807 };
 808
 809 struct mlx4_set_port_rqp_calc_context {
 810         __be32 base_qpn;
 811         u8 rererved;
 812         u8 n_mac;
 813         u8 n_vlan;
 814         u8 n_prio;
 815         u8 reserved2[3];
 816         u8 mac_miss;
 817         u8 intra_no_vlan;
 818         u8 no_vlan;
 819         u8 intra_vlan_miss;
 820         u8 vlan_miss;
 821         u8 reserved3[3];
 822         u8 no_vlan_prio;
 823         __be32 promisc;
 824         __be32 mcast;
 825 };
 826
 827 struct mlx4_port_info {
 828         struct mlx4_dev        *dev;
 829         int                     port;
 830         char                    dev_name[16];
 831         struct device_attribute port_attr;
 832         enum mlx4_port_type     tmp_type;
 833         char                    dev_mtu_name[16];
 834         struct device_attribute port_mtu_attr;
 835         struct mlx4_mac_table   mac_table;
 836         struct mlx4_vlan_table  vlan_table;
 837         struct mlx4_roce_gid_table gid_table;
 838         int                     base_qpn;
 839         struct cpu_rmap         *rmap;
 840         struct devlink_port     devlink_port;
 841 };
 842
 843 struct mlx4_sense {
 844         struct mlx4_dev         *dev;
 845         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 846         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 847         struct delayed_work     sense_poll;
 848 };
 849
 850 struct mlx4_msix_ctl {
 851         DECLARE_BITMAP(pool_bm, MAX_MSIX);
 852         struct mutex    pool_lock;
 853 };
 854
 855 struct mlx4_steer {
 856         struct list_head promisc_qps[MLX4_NUM_STEERS];
 857         struct list_head steer_entries[MLX4_NUM_STEERS];
 858 };
 859
 860 enum {
 861         MLX4_PCI_DEV_IS_VF              = 1 << 0,
 862         MLX4_PCI_DEV_FORCE_SENSE_PORT   = 1 << 1,
 863 };
 864
 865 enum {
 866         MLX4_NO_RR      = 0,
 867         MLX4_USE_RR     = 1,
 868 };
 869
 870 struct mlx4_priv {
 871         struct mlx4_dev         dev;
 872
 873         struct list_head        dev_list;
 874         struct list_head        ctx_list;
 875         spinlock_t              ctx_lock;
 876
 877         int                     pci_dev_data;
 878         int                     removed;
 879
 880         struct list_head        pgdir_list;
 881         struct mutex            pgdir_mutex;
 882
 883         struct mlx4_fw          fw;
 884         struct mlx4_cmd         cmd;
 885         struct mlx4_mfunc       mfunc;
 886
 887         struct mlx4_bitmap      pd_bitmap;
 888         struct mlx4_bitmap      xrcd_bitmap;
 889         struct mlx4_uar_table   uar_table;
 890         struct mlx4_mr_table    mr_table;
 891         struct mlx4_cq_table    cq_table;
 892         struct mlx4_eq_table    eq_table;
 893         struct mlx4_srq_table   srq_table;
 894         struct mlx4_qp_table    qp_table;
 895         struct mlx4_mcg_table   mcg_table;
 896         struct mlx4_bitmap      counters_bitmap;
 897         int                     def_counter[MLX4_MAX_PORTS];
 898
 899         struct mlx4_catas_err   catas_err;
 900
 901         void __iomem           *clr_base;
 902
 903         struct mlx4_uar         driver_uar;
 904         void __iomem           *kar;
 905         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 906         struct mlx4_sense       sense;
 907         struct mutex            port_mutex;
 908         struct mlx4_msix_ctl    msix_ctl;
 909         struct mlx4_steer       *steer;
 910         struct list_head        bf_list;
 911         struct mutex            bf_mutex;
 912         struct io_mapping       *bf_mapping;
 913         void __iomem            *clock_mapping;
 914         int                     reserved_mtts;
 915         int                     fs_hash_mode;
 916         u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
 917         struct mlx4_port_map    v2p; /* cached port mapping configuration */
 918         struct mutex            bond_mutex; /* for bond mode */
 919         __be64                  slave_node_guids[MLX4_MFUNC_MAX];
 920
 921         atomic_t                opreq_count;
 922         struct work_struct      opreq_task;
 923 };
 924
 925 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 926 {
 927         return container_of(dev, struct mlx4_priv, dev);
 928 }
 929
 930 #define MLX4_SENSE_RANGE        (HZ * 3)
 931
 932 extern struct workqueue_struct *mlx4_wq;
 933
 934 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 935 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
 936 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
 937                             int align, u32 skip_mask);
 938 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
 939                             int use_rr);
 940 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 941 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 942                      u32 reserved_bot, u32 resetrved_top);
 943 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 944
 945 int mlx4_reset(struct mlx4_dev *dev);
 946
 947 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 948 void mlx4_free_eq_table(struct mlx4_dev *dev);
 949
 950 int mlx4_init_pd_table(struct mlx4_dev *dev);
 951 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 952 int mlx4_init_uar_table(struct mlx4_dev *dev);
 953 int mlx4_init_mr_table(struct mlx4_dev *dev);
 954 int mlx4_init_eq_table(struct mlx4_dev *dev);
 955 int mlx4_init_cq_table(struct mlx4_dev *dev);
 956 int mlx4_init_qp_table(struct mlx4_dev *dev);
 957 int mlx4_init_srq_table(struct mlx4_dev *dev);
 958 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 959
 960 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 961 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 962 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 963 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 964 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 965 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 966 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 967 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 968 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 969 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
 970 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 971 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 972 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 973 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 974 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 975 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
 976 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
 977 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
 978 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
 979 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 980 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 981
 982 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 983                            struct mlx4_vhcr *vhcr,
 984                            struct mlx4_cmd_mailbox *inbox,
 985                            struct mlx4_cmd_mailbox *outbox,
 986                            struct mlx4_cmd_info *cmd);
 987 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 988                            struct mlx4_vhcr *vhcr,
 989                            struct mlx4_cmd_mailbox *inbox,
 990                            struct mlx4_cmd_mailbox *outbox,
 991                            struct mlx4_cmd_info *cmd);
 992 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 993                            struct mlx4_vhcr *vhcr,
 994                            struct mlx4_cmd_mailbox *inbox,
 995                            struct mlx4_cmd_mailbox *outbox,
 996                            struct mlx4_cmd_info *cmd);
 997 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 998                            struct mlx4_vhcr *vhcr,
 999                            struct mlx4_cmd_mailbox *inbox,
1000                            struct mlx4_cmd_mailbox *outbox,
1001                            struct mlx4_cmd_info *cmd);
1002 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
1003                            struct mlx4_vhcr *vhcr,
1004                            struct mlx4_cmd_mailbox *inbox,
1005                            struct mlx4_cmd_mailbox *outbox,
1006                            struct mlx4_cmd_info *cmd);
1007 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1008                           struct mlx4_vhcr *vhcr,
1009                           struct mlx4_cmd_mailbox *inbox,
1010                           struct mlx4_cmd_mailbox *outbox,
1011                           struct mlx4_cmd_info *cmd);
1012 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
1013                             struct mlx4_vhcr *vhcr,
1014                             struct mlx4_cmd_mailbox *inbox,
1015                             struct mlx4_cmd_mailbox *outbox,
1016                             struct mlx4_cmd_info *cmd);
1017 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1018                      struct mlx4_vhcr *vhcr,
1019                      struct mlx4_cmd_mailbox *inbox,
1020                      struct mlx4_cmd_mailbox *outbox,
1021                      struct mlx4_cmd_info *cmd);
1022 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1023                             int *base, u8 flags);
1024 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1025 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1026 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1027 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1028                      int start_index, int npages, u64 *page_list);
1029 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1030 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1031 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1032                           struct mlx4_counter *data);
1033 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1034 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1035
1036 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1037 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1038 int mlx4_catas_init(struct mlx4_dev *dev);
1039 void mlx4_catas_end(struct mlx4_dev *dev);
1040 int mlx4_restart_one(struct pci_dev *pdev);
1041 int mlx4_register_device(struct mlx4_dev *dev);
1042 void mlx4_unregister_device(struct mlx4_dev *dev);
1043 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1044                          unsigned long param);
1045
1046 struct mlx4_dev_cap;
1047 struct mlx4_init_hca_param;
1048
1049 u64 mlx4_make_profile(struct mlx4_dev *dev,
1050                       struct mlx4_profile *request,
1051                       struct mlx4_dev_cap *dev_cap,
1052                       struct mlx4_init_hca_param *init_hca);
1053 void mlx4_master_comm_channel(struct work_struct *work);
1054 void mlx4_gen_slave_eqe(struct work_struct *work);
1055 void mlx4_master_handle_slave_flr(struct work_struct *work);
1056
1057 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1058                            struct mlx4_vhcr *vhcr,
1059                            struct mlx4_cmd_mailbox *inbox,
1060                            struct mlx4_cmd_mailbox *outbox,
1061                            struct mlx4_cmd_info *cmd);
1062 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1063                           struct mlx4_vhcr *vhcr,
1064                           struct mlx4_cmd_mailbox *inbox,
1065                           struct mlx4_cmd_mailbox *outbox,
1066                           struct mlx4_cmd_info *cmd);
1067 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1068                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1069                         struct mlx4_cmd_mailbox *outbox,
1070                         struct mlx4_cmd_info *cmd);
1071 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1072                           struct mlx4_vhcr *vhcr,
1073                           struct mlx4_cmd_mailbox *inbox,
1074                           struct mlx4_cmd_mailbox *outbox,
1075                           struct mlx4_cmd_info *cmd);
1076 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1077                             struct mlx4_vhcr *vhcr,
1078                             struct mlx4_cmd_mailbox *inbox,
1079                             struct mlx4_cmd_mailbox *outbox,
1080                           struct mlx4_cmd_info *cmd);
1081 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1082                           struct mlx4_vhcr *vhcr,
1083                           struct mlx4_cmd_mailbox *inbox,
1084                           struct mlx4_cmd_mailbox *outbox,
1085                           struct mlx4_cmd_info *cmd);
1086 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1087                           struct mlx4_vhcr *vhcr,
1088                           struct mlx4_cmd_mailbox *inbox,
1089                           struct mlx4_cmd_mailbox *outbox,
1090                           struct mlx4_cmd_info *cmd);
1091 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1092                           struct mlx4_vhcr *vhcr,
1093                           struct mlx4_cmd_mailbox *inbox,
1094                           struct mlx4_cmd_mailbox *outbox,
1095                           struct mlx4_cmd_info *cmd);
1096 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1097                           struct mlx4_vhcr *vhcr,
1098                           struct mlx4_cmd_mailbox *inbox,
1099                           struct mlx4_cmd_mailbox *outbox,
1100                           struct mlx4_cmd_info *cmd);
1101 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1102                           struct mlx4_vhcr *vhcr,
1103                           struct mlx4_cmd_mailbox *inbox,
1104                           struct mlx4_cmd_mailbox *outbox,
1105                            struct mlx4_cmd_info *cmd);
1106 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1107                            struct mlx4_vhcr *vhcr,
1108                            struct mlx4_cmd_mailbox *inbox,
1109                            struct mlx4_cmd_mailbox *outbox,
1110                            struct mlx4_cmd_info *cmd);
1111 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1112                            struct mlx4_vhcr *vhcr,
1113                            struct mlx4_cmd_mailbox *inbox,
1114                            struct mlx4_cmd_mailbox *outbox,
1115                            struct mlx4_cmd_info *cmd);
1116 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1117                            struct mlx4_vhcr *vhcr,
1118                            struct mlx4_cmd_mailbox *inbox,
1119                            struct mlx4_cmd_mailbox *outbox,
1120                            struct mlx4_cmd_info *cmd);
1121 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1122                          struct mlx4_vhcr *vhcr,
1123                          struct mlx4_cmd_mailbox *inbox,
1124                          struct mlx4_cmd_mailbox *outbox,
1125                          struct mlx4_cmd_info *cmd);
1126 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1127                         struct mlx4_vhcr *vhcr,
1128                         struct mlx4_cmd_mailbox *inbox,
1129                         struct mlx4_cmd_mailbox *outbox,
1130                         struct mlx4_cmd_info *cmd);
1131 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1132                              struct mlx4_vhcr *vhcr,
1133                              struct mlx4_cmd_mailbox *inbox,
1134                              struct mlx4_cmd_mailbox *outbox,
1135                              struct mlx4_cmd_info *cmd);
1136 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1137                               struct mlx4_vhcr *vhcr,
1138                               struct mlx4_cmd_mailbox *inbox,
1139                               struct mlx4_cmd_mailbox *outbox,
1140                               struct mlx4_cmd_info *cmd);
1141 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1142                              struct mlx4_vhcr *vhcr,
1143                              struct mlx4_cmd_mailbox *inbox,
1144                              struct mlx4_cmd_mailbox *outbox,
1145                              struct mlx4_cmd_info *cmd);
1146 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1147                             struct mlx4_vhcr *vhcr,
1148                             struct mlx4_cmd_mailbox *inbox,
1149                             struct mlx4_cmd_mailbox *outbox,
1150                             struct mlx4_cmd_info *cmd);
1151 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1152                             struct mlx4_vhcr *vhcr,
1153                             struct mlx4_cmd_mailbox *inbox,
1154                             struct mlx4_cmd_mailbox *outbox,
1155                             struct mlx4_cmd_info *cmd);
1156 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1157                               struct mlx4_vhcr *vhcr,
1158                               struct mlx4_cmd_mailbox *inbox,
1159                               struct mlx4_cmd_mailbox *outbox,
1160                               struct mlx4_cmd_info *cmd);
1161 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1162                          struct mlx4_vhcr *vhcr,
1163                          struct mlx4_cmd_mailbox *inbox,
1164                          struct mlx4_cmd_mailbox *outbox,
1165                          struct mlx4_cmd_info *cmd);
1166 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1167                             struct mlx4_vhcr *vhcr,
1168                             struct mlx4_cmd_mailbox *inbox,
1169                             struct mlx4_cmd_mailbox *outbox,
1170                             struct mlx4_cmd_info *cmd);
1171 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1172                             struct mlx4_vhcr *vhcr,
1173                             struct mlx4_cmd_mailbox *inbox,
1174                             struct mlx4_cmd_mailbox *outbox,
1175                             struct mlx4_cmd_info *cmd);
1176 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1177                             struct mlx4_vhcr *vhcr,
1178                             struct mlx4_cmd_mailbox *inbox,
1179                             struct mlx4_cmd_mailbox *outbox,
1180                             struct mlx4_cmd_info *cmd);
1181 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1182                          struct mlx4_vhcr *vhcr,
1183                          struct mlx4_cmd_mailbox *inbox,
1184                          struct mlx4_cmd_mailbox *outbox,
1185                          struct mlx4_cmd_info *cmd);
1186 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1187                           struct mlx4_vhcr *vhcr,
1188                           struct mlx4_cmd_mailbox *inbox,
1189                           struct mlx4_cmd_mailbox *outbox,
1190                           struct mlx4_cmd_info *cmd);
1191
1192 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1193
1194 enum {
1195         MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1196         MLX4_CMD_CLEANUP_POOL   = 1UL << 1,
1197         MLX4_CMD_CLEANUP_HCR    = 1UL << 2,
1198         MLX4_CMD_CLEANUP_VHCR   = 1UL << 3,
1199         MLX4_CMD_CLEANUP_ALL    = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1200 };
1201
1202 int mlx4_cmd_init(struct mlx4_dev *dev);
1203 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1204 int mlx4_multi_func_init(struct mlx4_dev *dev);
1205 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1206 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1207 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1208 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1209 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1210
1211 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1212                   u16 op, unsigned long timeout);
1213
1214 void mlx4_cq_tasklet_cb(unsigned long data);
1215 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1216 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1217
1218 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1219
1220 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1221
1222 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1223
1224 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1225                     enum mlx4_port_type *type);
1226 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1227                          enum mlx4_port_type *stype,
1228                          enum mlx4_port_type *defaults);
1229 void mlx4_start_sense(struct mlx4_dev *dev);
1230 void mlx4_stop_sense(struct mlx4_dev *dev);
1231 void mlx4_sense_init(struct mlx4_dev *dev);
1232 int mlx4_check_port_params(struct mlx4_dev *dev,
1233                            enum mlx4_port_type *port_type);
1234 int mlx4_change_port_types(struct mlx4_dev *dev,
1235                            enum mlx4_port_type *port_types);
1236
1237 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1238 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1239 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1240                               struct mlx4_roce_gid_table *table);
1241 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1242 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1243 int mlx4_bond_vlan_table(struct mlx4_dev *dev);
1244 int mlx4_unbond_vlan_table(struct mlx4_dev *dev);
1245 int mlx4_bond_mac_table(struct mlx4_dev *dev);
1246 int mlx4_unbond_mac_table(struct mlx4_dev *dev);
1247
1248 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1249 /* resource tracker functions*/
1250 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1251                                     enum mlx4_resource resource_type,
1252                                     u64 resource_id, int *slave);
1253 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1254 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1255 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1256
1257 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1258                                 enum mlx4_res_tracker_free_type type);
1259
1260 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1261                           struct mlx4_vhcr *vhcr,
1262                           struct mlx4_cmd_mailbox *inbox,
1263                           struct mlx4_cmd_mailbox *outbox,
1264                           struct mlx4_cmd_info *cmd);
1265 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1266                           struct mlx4_vhcr *vhcr,
1267                           struct mlx4_cmd_mailbox *inbox,
1268                           struct mlx4_cmd_mailbox *outbox,
1269                           struct mlx4_cmd_info *cmd);
1270 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1271                            struct mlx4_vhcr *vhcr,
1272                            struct mlx4_cmd_mailbox *inbox,
1273                            struct mlx4_cmd_mailbox *outbox,
1274                            struct mlx4_cmd_info *cmd);
1275 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1276                             struct mlx4_vhcr *vhcr,
1277                             struct mlx4_cmd_mailbox *inbox,
1278                             struct mlx4_cmd_mailbox *outbox,
1279                             struct mlx4_cmd_info *cmd);
1280 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1281                                struct mlx4_vhcr *vhcr,
1282                                struct mlx4_cmd_mailbox *inbox,
1283                                struct mlx4_cmd_mailbox *outbox,
1284                                struct mlx4_cmd_info *cmd);
1285 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1286                             struct mlx4_vhcr *vhcr,
1287                             struct mlx4_cmd_mailbox *inbox,
1288                             struct mlx4_cmd_mailbox *outbox,
1289                             struct mlx4_cmd_info *cmd);
1290 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1291
1292 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1293                                     int *gid_tbl_len, int *pkey_tbl_len);
1294
1295 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1296                            struct mlx4_vhcr *vhcr,
1297                            struct mlx4_cmd_mailbox *inbox,
1298                            struct mlx4_cmd_mailbox *outbox,
1299                            struct mlx4_cmd_info *cmd);
1300
1301 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1302                            struct mlx4_vhcr *vhcr,
1303                            struct mlx4_cmd_mailbox *inbox,
1304                            struct mlx4_cmd_mailbox *outbox,
1305                            struct mlx4_cmd_info *cmd);
1306
1307 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1308                          struct mlx4_vhcr *vhcr,
1309                          struct mlx4_cmd_mailbox *inbox,
1310                          struct mlx4_cmd_mailbox *outbox,
1311                          struct mlx4_cmd_info *cmd);
1312 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1313                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1314 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1315                           int block_mcast_loopback, enum mlx4_protocol prot,
1316                           enum mlx4_steer_type steer);
1317 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1318                               u8 gid[16], u8 port,
1319                               int block_mcast_loopback,
1320                               enum mlx4_protocol prot, u64 *reg_id);
1321 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1322                                 struct mlx4_vhcr *vhcr,
1323                                 struct mlx4_cmd_mailbox *inbox,
1324                                 struct mlx4_cmd_mailbox *outbox,
1325                                 struct mlx4_cmd_info *cmd);
1326 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1327                                struct mlx4_vhcr *vhcr,
1328                                struct mlx4_cmd_mailbox *inbox,
1329                                struct mlx4_cmd_mailbox *outbox,
1330                                struct mlx4_cmd_info *cmd);
1331 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1332                                      int port, void *buf);
1333 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1334                                    struct mlx4_vhcr *vhcr,
1335                                    struct mlx4_cmd_mailbox *inbox,
1336                                    struct mlx4_cmd_mailbox *outbox,
1337                                 struct mlx4_cmd_info *cmd);
1338 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1339                             struct mlx4_vhcr *vhcr,
1340                             struct mlx4_cmd_mailbox *inbox,
1341                             struct mlx4_cmd_mailbox *outbox,
1342                             struct mlx4_cmd_info *cmd);
1343 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1344                                struct mlx4_vhcr *vhcr,
1345                                struct mlx4_cmd_mailbox *inbox,
1346                                struct mlx4_cmd_mailbox *outbox,
1347                                struct mlx4_cmd_info *cmd);
1348 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1349                                          struct mlx4_vhcr *vhcr,
1350                                          struct mlx4_cmd_mailbox *inbox,
1351                                          struct mlx4_cmd_mailbox *outbox,
1352                                          struct mlx4_cmd_info *cmd);
1353 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1354                                          struct mlx4_vhcr *vhcr,
1355                                          struct mlx4_cmd_mailbox *inbox,
1356                                          struct mlx4_cmd_mailbox *outbox,
1357                                          struct mlx4_cmd_info *cmd);
1358 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1359                             struct mlx4_vhcr *vhcr,
1360                             struct mlx4_cmd_mailbox *inbox,
1361                             struct mlx4_cmd_mailbox *outbox,
1362                             struct mlx4_cmd_info *cmd);
1363
1364 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1365 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1366
1367 static inline void set_param_l(u64 *arg, u32 val)
1368 {
1369         *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1370 }
1371
1372 static inline void set_param_h(u64 *arg, u32 val)
1373 {
1374         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1375 }
1376
1377 static inline u32 get_param_l(u64 *arg)
1378 {
1379         return (u32) (*arg & 0xffffffff);
1380 }
1381
1382 static inline u32 get_param_h(u64 *arg)
1383 {
1384         return (u32)(*arg >> 32);
1385 }
1386
1387 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1388 {
1389         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1390 }
1391
1392 #define NOT_MASKED_PD_BITS 17
1393
1394 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1395
1396 void mlx4_init_quotas(struct mlx4_dev *dev);
1397
1398 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */
1399 void mlx4_replace_zero_macs(struct mlx4_dev *dev);
1400 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1401 /* Returns the VF index of slave */
1402 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1403 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1404 int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1405 int mlx4_bond_fs_rules(struct mlx4_dev *dev);
1406 int mlx4_unbond_fs_rules(struct mlx4_dev *dev);
1407
1408 enum mlx4_zone_flags {
1409         MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO   = 1UL << 0,
1410         MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO      = 1UL << 1,
1411         MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO       = 1UL << 2,
1412         MLX4_ZONE_USE_RR                        = 1UL << 3,
1413 };
1414
1415 enum mlx4_zone_alloc_flags {
1416         /* No two objects could overlap between zones. UID
1417          * could be left unused. If this flag is given and
1418          * two overlapped zones are used, an object will be free'd
1419          * from the smallest possible matching zone.
1420          */
1421         MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP        = 1UL << 0,
1422 };
1423
1424 struct mlx4_zone_allocator;
1425
1426 /* Create a new zone allocator */
1427 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1428
1429 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1430  * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1431  * Similarly, when searching for an object to free, this offset it taken into
1432  * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1433  * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1434  * When an allocation fails, <zone_alloc> tries to allocate from other zones
1435  * according to the policy set by <flags>. <puid> is the unique identifier
1436  * received to this zone.
1437  */
1438 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1439                       struct mlx4_bitmap *bitmap,
1440                       u32 flags,
1441                       int priority,
1442                       int offset,
1443                       u32 *puid);
1444
1445 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1446 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1447
1448 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1449  * the attached bitmaps.
1450  */
1451 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1452
1453 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1454  * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1455  * allocated from is returned in <puid>. If the allocation fails, a negative
1456  * number is returned. Otherwise, the offset of the first object is returned.
1457  */
1458 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1459                             int align, u32 skip_mask, u32 *puid);
1460
1461 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1462  * <zones>.
1463  */
1464 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1465                            u32 uid, u32 obj, u32 count);
1466
1467 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1468  * specifying the uid when freeing an object, zone allocator could figure it by
1469  * itself. Other parameters are similar to mlx4_zone_free.
1470  */
1471 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1472
1473 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1474 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1475
1476 #endif /* MLX4_H */