drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58 #include "mlx4_stats.h"
  59
  60 #define DRV_NAME        "mlx4_en"
  61 #define DRV_VERSION     "4.0-0"
  62
  63 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  64
  65 /*
  66  * Device constants
  67  */
  68
  69
  70 #define MLX4_EN_PAGE_SHIFT      12
  71 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  72 #define DEF_RX_RINGS            16
  73 #define MAX_RX_RINGS            128
  74 #define MIN_RX_RINGS            4
  75 #define LOG_TXBB_SIZE           6
  76 #define TXBB_SIZE               BIT(LOG_TXBB_SIZE)
  77 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  78 #define STAMP_STRIDE            64
  79 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  80 #define STAMP_SHIFT             31
  81 #define STAMP_VAL               0x7fffffff
  82 #define STATS_DELAY             (HZ / 4)
  83 #define SERVICE_TASK_DELAY      (HZ / 4)
  84 #define MAX_NUM_OF_FS_RULES     256
  85
  86 #define MLX4_EN_FILTER_HASH_SHIFT 4
  87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  88
  89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  90 #define MAX_DESC_SIZE           512
  91 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  92
  93 /*
  94  * OS related constants and tunables
  95  */
  96
  97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
  98 #define MLX4_EN_PRIV_FLAGS_PHV       2
  99
 100 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 101
 102 /* Use the maximum between 16384 and a single page */
 103 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 104
 105 #define MLX4_EN_MAX_RX_FRAGS    4
 106
 107 /* Maximum ring sizes */
 108 #define MLX4_EN_MAX_TX_SIZE     8192
 109 #define MLX4_EN_MAX_RX_SIZE     8192
 110
 111 /* Minimum ring size for our page-allocation scheme to work */
 112 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 113 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 114
 115 #define MLX4_EN_SMALL_PKT_SIZE          64
 116 #define MLX4_EN_MIN_TX_RING_P_UP        1
 117 #define MLX4_EN_MAX_TX_RING_P_UP        32
 118 #define MLX4_EN_NUM_UP_LOW              1
 119 #define MLX4_EN_NUM_UP_HIGH             8
 120 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 121 #define MLX4_EN_DEF_TX_RING_SIZE        MLX4_EN_DEF_RX_RING_SIZE
 122 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 123                                          MLX4_EN_NUM_UP_HIGH)
 124
 125 #define MLX4_EN_DEFAULT_TX_WORK         256
 126
 127 /* Target number of packets to coalesce with interrupt moderation */
 128 #define MLX4_EN_RX_COAL_TARGET  44
 129 #define MLX4_EN_RX_COAL_TIME    0x10
 130
 131 #define MLX4_EN_TX_COAL_PKTS    16
 132 #define MLX4_EN_TX_COAL_TIME    0x10
 133
 134 #define MLX4_EN_RX_RATE_LOW             400000
 135 #define MLX4_EN_RX_COAL_TIME_LOW        0
 136 #define MLX4_EN_RX_RATE_HIGH            450000
 137 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 138 #define MLX4_EN_RX_SIZE_THRESH          1024
 139 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 140 #define MLX4_EN_SAMPLE_INTERVAL         0
 141 #define MLX4_EN_AVG_PKT_SMALL           256
 142
 143 #define MLX4_EN_AUTO_CONF       0xffff
 144
 145 #define MLX4_EN_DEF_RX_PAUSE    1
 146 #define MLX4_EN_DEF_TX_PAUSE    1
 147
 148 /* Interval between successive polls in the Tx routine when polling is used
 149    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 150 #define MLX4_EN_TX_POLL_MODER   16
 151 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 152
 153 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 154 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 155 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 156
 157 #define MLX4_EN_MIN_MTU         46
 158 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
 159  * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
 160  */
 161 #define MLX4_EN_EFF_MTU(mtu)    ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
 162 #define ETH_BCAST               0xffffffffffffULL
 163
 164 #define MLX4_EN_LOOPBACK_RETRIES        5
 165 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 166
 167 #ifdef MLX4_EN_PERF_STAT
 168 /* Number of samples to 'average' */
 169 #define AVG_SIZE                        128
 170 #define AVG_FACTOR                      1024
 171
 172 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 173 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 174 #define AVG_PERF_COUNTER(cnt, sample) \
 175         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 176 #define GET_PERF_COUNTER(cnt)           (cnt)
 177 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 178
 179 #else
 180
 181 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 182 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 183 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 184 #define GET_PERF_COUNTER(cnt)           (0)
 185 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 186 #endif /* MLX4_EN_PERF_STAT */
 187
 188 /* Constants for TX flow */
 189 enum {
 190         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 191         MAX_BF = 256,
 192         MIN_PKT_LEN = 17,
 193 };
 194
 195 /*
 196  * Configurables
 197  */
 198
 199 enum cq_type {
 200         /* keep tx types first */
 201         TX,
 202         TX_XDP,
 203 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
 204         RX,
 205 };
 206
 207
 208 /*
 209  * Useful macros
 210  */
 211 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 212 #define XNOR(x, y)              (!(x) == !(y))
 213
 214
 215 struct mlx4_en_tx_info {
 216         union {
 217                 struct sk_buff *skb;
 218                 struct page *page;
 219         };
 220         dma_addr_t      map0_dma;
 221         u32             map0_byte_count;
 222         u32             nr_txbb;
 223         u32             nr_bytes;
 224         u8              linear;
 225         u8              data_offset;
 226         u8              inl;
 227         u8              ts_requested;
 228         u8              nr_maps;
 229 } ____cacheline_aligned_in_smp;
 230
 231
 232 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 233 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 234 #define MLX4_EN_MEMTYPE_PAD     0x100
 235 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 236
 237
 238 struct mlx4_en_tx_desc {
 239         struct mlx4_wqe_ctrl_seg ctrl;
 240         union {
 241                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 242                 struct mlx4_wqe_lso_seg lso;
 243                 struct mlx4_wqe_inline_seg inl;
 244         };
 245 };
 246
 247 #define MLX4_EN_USE_SRQ         0x01000000
 248
 249 #define MLX4_EN_CX3_LOW_ID      0x1000
 250 #define MLX4_EN_CX3_HIGH_ID     0x1005
 251
 252 struct mlx4_en_rx_alloc {
 253         struct page     *page;
 254         dma_addr_t      dma;
 255         u32             page_offset;
 256 };
 257
 258 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
 259
 260 struct mlx4_en_page_cache {
 261         u32 index;
 262         struct {
 263                 struct page     *page;
 264                 dma_addr_t      dma;
 265         } buf[MLX4_EN_CACHE_SIZE];
 266 };
 267
 268 struct mlx4_en_priv;
 269
 270 struct mlx4_en_tx_ring {
 271         /* cache line used and dirtied in tx completion
 272          * (mlx4_en_free_tx_buf())
 273          */
 274         u32                     last_nr_txbb;
 275         u32                     cons;
 276         unsigned long           wake_queue;
 277         struct netdev_queue     *tx_queue;
 278         u32                     (*free_tx_desc)(struct mlx4_en_priv *priv,
 279                                                 struct mlx4_en_tx_ring *ring,
 280                                                 int index,
 281                                                 u64 timestamp, int napi_mode);
 282         struct mlx4_en_rx_ring  *recycle_ring;
 283
 284         /* cache line used and dirtied in mlx4_en_xmit() */
 285         u32                     prod ____cacheline_aligned_in_smp;
 286         unsigned int            tx_dropped;
 287         unsigned long           bytes;
 288         unsigned long           packets;
 289         unsigned long           tx_csum;
 290         unsigned long           tso_packets;
 291         unsigned long           xmit_more;
 292         struct mlx4_bf          bf;
 293
 294         /* Following part should be mostly read */
 295         __be32                  doorbell_qpn;
 296         __be32                  mr_key;
 297         u32                     size; /* number of TXBBs */
 298         u32                     size_mask;
 299         u32                     full_size;
 300         u32                     buf_size;
 301         void                    *buf;
 302         struct mlx4_en_tx_info  *tx_info;
 303         int                     qpn;
 304         u8                      queue_index;
 305         bool                    bf_enabled;
 306         bool                    bf_alloced;
 307         u8                      hwtstamp_tx_type;
 308         u8                      *bounce_buf;
 309
 310         /* Not used in fast path
 311          * Only queue_stopped might be used if BQL is not properly working.
 312          */
 313         unsigned long           queue_stopped;
 314         struct mlx4_hwq_resources sp_wqres;
 315         struct mlx4_qp          sp_qp;
 316         struct mlx4_qp_context  sp_context;
 317         cpumask_t               sp_affinity_mask;
 318         enum mlx4_qp_state      sp_qp_state;
 319         u16                     sp_stride;
 320         u16                     sp_cqn; /* index of port CQ associated with this ring */
 321 } ____cacheline_aligned_in_smp;
 322
 323 struct mlx4_en_rx_desc {
 324         /* actual number of entries depends on rx ring stride */
 325         struct mlx4_wqe_data_seg data[0];
 326 };
 327
 328 struct mlx4_en_rx_ring {
 329         struct mlx4_hwq_resources wqres;
 330         u32 size ;      /* number of Rx descs*/
 331         u32 actual_size;
 332         u32 size_mask;
 333         u16 stride;
 334         u16 log_stride;
 335         u16 cqn;        /* index of port CQ associated with this ring */
 336         u32 prod;
 337         u32 cons;
 338         u32 buf_size;
 339         u8  fcs_del;
 340         void *buf;
 341         void *rx_info;
 342         struct bpf_prog __rcu *xdp_prog;
 343         struct mlx4_en_page_cache page_cache;
 344         unsigned long bytes;
 345         unsigned long packets;
 346         unsigned long csum_ok;
 347         unsigned long csum_none;
 348         unsigned long csum_complete;
 349         unsigned long rx_alloc_pages;
 350         unsigned long xdp_drop;
 351         unsigned long xdp_tx;
 352         unsigned long xdp_tx_full;
 353         unsigned long dropped;
 354         int hwtstamp_rx_filter;
 355         cpumask_var_t affinity_mask;
 356 };
 357
 358 struct mlx4_en_cq {
 359         struct mlx4_cq          mcq;
 360         struct mlx4_hwq_resources wqres;
 361         int                     ring;
 362         struct net_device      *dev;
 363         union {
 364                 struct napi_struct napi;
 365                 bool               xdp_busy;
 366         };
 367         int size;
 368         int buf_size;
 369         int vector;
 370         enum cq_type type;
 371         u16 moder_time;
 372         u16 moder_cnt;
 373         struct mlx4_cqe *buf;
 374 #define MLX4_EN_OPCODE_ERROR    0x1e
 375
 376         struct irq_desc *irq_desc;
 377 };
 378
 379 struct mlx4_en_port_profile {
 380         u32 flags;
 381         u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
 382         u32 rx_ring_num;
 383         u32 tx_ring_size;
 384         u32 rx_ring_size;
 385         u8 num_tx_rings_p_up;
 386         u8 rx_pause;
 387         u8 rx_ppp;
 388         u8 tx_pause;
 389         u8 tx_ppp;
 390         u8 num_up;
 391         int rss_rings;
 392         int inline_thold;
 393         struct hwtstamp_config hwtstamp_config;
 394 };
 395
 396 struct mlx4_en_profile {
 397         int udp_rss;
 398         u8 rss_mask;
 399         u32 active_ports;
 400         u32 small_pkt_int;
 401         u8 no_reset;
 402         u8 max_num_tx_rings_p_up;
 403         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 404 };
 405
 406 struct mlx4_en_dev {
 407         struct mlx4_dev         *dev;
 408         struct pci_dev          *pdev;
 409         struct mutex            state_lock;
 410         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 411         struct net_device       *upper[MLX4_MAX_PORTS + 1];
 412         u32                     port_cnt;
 413         bool                    device_up;
 414         struct mlx4_en_profile  profile;
 415         u32                     LSO_support;
 416         struct workqueue_struct *workqueue;
 417         struct device           *dma_device;
 418         void __iomem            *uar_map;
 419         struct mlx4_uar         priv_uar;
 420         struct mlx4_mr          mr;
 421         u32                     priv_pdn;
 422         spinlock_t              uar_lock;
 423         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 424         u32                     nominal_c_mult;
 425         struct cyclecounter     cycles;
 426         seqlock_t               clock_lock;
 427         struct timecounter      clock;
 428         unsigned long           last_overflow_check;
 429         struct ptp_clock        *ptp_clock;
 430         struct ptp_clock_info   ptp_clock_info;
 431         struct notifier_block   nb;
 432 };
 433
 434
 435 struct mlx4_en_rss_map {
 436         int base_qpn;
 437         struct mlx4_qp qps[MAX_RX_RINGS];
 438         enum mlx4_qp_state state[MAX_RX_RINGS];
 439         struct mlx4_qp *indir_qp;
 440         enum mlx4_qp_state indir_state;
 441 };
 442
 443 enum mlx4_en_port_flag {
 444         MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
 445         MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
 446 };
 447
 448 struct mlx4_en_port_state {
 449         int link_state;
 450         int link_speed;
 451         int transceiver;
 452         u32 flags;
 453 };
 454
 455 enum mlx4_en_mclist_act {
 456         MCLIST_NONE,
 457         MCLIST_REM,
 458         MCLIST_ADD,
 459 };
 460
 461 struct mlx4_en_mc_list {
 462         struct list_head        list;
 463         enum mlx4_en_mclist_act action;
 464         u8                      addr[ETH_ALEN];
 465         u64                     reg_id;
 466         u64                     tunnel_reg_id;
 467 };
 468
 469 struct mlx4_en_frag_info {
 470         u16 frag_size;
 471         u32 frag_stride;
 472 };
 473
 474 #ifdef CONFIG_MLX4_EN_DCB
 475 /* Minimal TC BW - setting to 0 will block traffic */
 476 #define MLX4_EN_BW_MIN 1
 477 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 478
 479 #define MLX4_EN_TC_ETS 7
 480
 481 enum dcb_pfc_type {
 482         pfc_disabled = 0,
 483         pfc_enabled_full,
 484         pfc_enabled_tx,
 485         pfc_enabled_rx
 486 };
 487
 488 struct mlx4_en_cee_config {
 489         bool    pfc_state;
 490         enum    dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
 491 };
 492 #endif
 493
 494 struct ethtool_flow_id {
 495         struct list_head list;
 496         struct ethtool_rx_flow_spec flow_spec;
 497         u64 id;
 498 };
 499
 500 enum {
 501         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 502         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 503         /* whether we need to enable hardware loopback by putting dmac
 504          * in Tx WQE
 505          */
 506         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 507         /* whether we need to drop packets that hardware loopback-ed */
 508         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 509         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4),
 510         MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP        = (1 << 5),
 511 #ifdef CONFIG_MLX4_EN_DCB
 512         MLX4_EN_FLAG_DCB_ENABLED        = (1 << 6),
 513 #endif
 514 };
 515
 516 #define PORT_BEACON_MAX_LIMIT (65535)
 517 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 518 #define MLX4_EN_MAC_HASH_IDX 5
 519
 520 struct mlx4_en_stats_bitmap {
 521         DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
 522         struct mutex mutex; /* for mutual access to stats bitmap */
 523 };
 524
 525 struct mlx4_en_priv {
 526         struct mlx4_en_dev *mdev;
 527         struct mlx4_en_port_profile *prof;
 528         struct net_device *dev;
 529         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 530         struct mlx4_en_port_state port_state;
 531         spinlock_t stats_lock;
 532         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 533         /* To allow rules removal while port is going down */
 534         struct list_head ethtool_list;
 535
 536         unsigned long last_moder_packets[MAX_RX_RINGS];
 537         unsigned long last_moder_tx_packets;
 538         unsigned long last_moder_bytes[MAX_RX_RINGS];
 539         unsigned long last_moder_jiffies;
 540         int last_moder_time[MAX_RX_RINGS];
 541         u16 rx_usecs;
 542         u16 rx_frames;
 543         u16 tx_usecs;
 544         u16 tx_frames;
 545         u32 pkt_rate_low;
 546         u16 rx_usecs_low;
 547         u32 pkt_rate_high;
 548         u16 rx_usecs_high;
 549         u16 sample_interval;
 550         u16 adaptive_rx_coal;
 551         u32 msg_enable;
 552         u32 loopback_ok;
 553         u32 validate_loopback;
 554
 555         struct mlx4_hwq_resources res;
 556         int link_state;
 557         int last_link_state;
 558         bool port_up;
 559         int port;
 560         int registered;
 561         int allocated;
 562         int stride;
 563         unsigned char current_mac[ETH_ALEN + 2];
 564         int mac_index;
 565         unsigned max_mtu;
 566         int base_qpn;
 567         int cqe_factor;
 568         int cqe_size;
 569
 570         struct mlx4_en_rss_map rss_map;
 571         __be32 ctrl_flags;
 572         u32 flags;
 573         u8 num_tx_rings_p_up;
 574         u32 tx_work_limit;
 575         u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
 576         u32 rx_ring_num;
 577         u32 rx_skb_size;
 578         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 579         u8 num_frags;
 580         u8 log_rx_info;
 581         u8 dma_dir;
 582         u16 rx_headroom;
 583
 584         struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
 585         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 586         struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
 587         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 588         struct mlx4_qp drop_qp;
 589         struct work_struct rx_mode_task;
 590         struct work_struct watchdog_task;
 591         struct work_struct linkstate_task;
 592         struct delayed_work stats_task;
 593         struct delayed_work service_task;
 594         struct work_struct vxlan_add_task;
 595         struct work_struct vxlan_del_task;
 596         struct mlx4_en_perf_stats pstats;
 597         struct mlx4_en_pkt_stats pkstats;
 598         struct mlx4_en_counter_stats pf_stats;
 599         struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
 600         struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
 601         struct mlx4_en_flow_stats_rx rx_flowstats;
 602         struct mlx4_en_flow_stats_tx tx_flowstats;
 603         struct mlx4_en_port_stats port_stats;
 604         struct mlx4_en_xdp_stats xdp_stats;
 605         struct mlx4_en_stats_bitmap stats_bitmap;
 606         struct list_head mc_list;
 607         struct list_head curr_list;
 608         u64 broadcast_id;
 609         struct mlx4_en_stat_out_mbox hw_stats;
 610         int vids[128];
 611         bool wol;
 612         struct device *ddev;
 613         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 614         struct hwtstamp_config hwtstamp_config;
 615         u32 counter_index;
 616
 617 #ifdef CONFIG_MLX4_EN_DCB
 618 #define MLX4_EN_DCB_ENABLED     0x3
 619         struct ieee_ets ets;
 620         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 621         enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
 622         struct mlx4_en_cee_config cee_config;
 623         u8 dcbx_cap;
 624 #endif
 625 #ifdef CONFIG_RFS_ACCEL
 626         spinlock_t filters_lock;
 627         int last_filter_id;
 628         struct list_head filters;
 629         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 630 #endif
 631         u64 tunnel_reg_id;
 632         __be16 vxlan_port;
 633
 634         u32 pflags;
 635         u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
 636         u8 rss_hash_fn;
 637 };
 638
 639 enum mlx4_en_wol {
 640         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 641         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 642 };
 643
 644 struct mlx4_mac_entry {
 645         struct hlist_node hlist;
 646         unsigned char mac[ETH_ALEN + 2];
 647         u64 reg_id;
 648         struct rcu_head rcu;
 649 };
 650
 651 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
 652 {
 653         return buf + idx * cqe_sz;
 654 }
 655
 656 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 657
 658 void mlx4_en_init_ptys2ethtool_map(void);
 659 void mlx4_en_update_loopback_state(struct net_device *dev,
 660                                    netdev_features_t features);
 661
 662 void mlx4_en_destroy_netdev(struct net_device *dev);
 663 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 664                         struct mlx4_en_port_profile *prof);
 665
 666 int mlx4_en_start_port(struct net_device *dev);
 667 void mlx4_en_stop_port(struct net_device *dev, int detach);
 668
 669 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
 670                               struct mlx4_en_stats_bitmap *stats_bitmap,
 671                               u8 rx_ppp, u8 rx_pause,
 672                               u8 tx_ppp, u8 tx_pause);
 673
 674 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
 675                                 struct mlx4_en_priv *tmp,
 676                                 struct mlx4_en_port_profile *prof,
 677                                 bool carry_xdp_prog);
 678 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
 679                                     struct mlx4_en_priv *tmp);
 680
 681 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 682                       int entries, int ring, enum cq_type mode, int node);
 683 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 684 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 685                         int cq_idx);
 686 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 687 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 688 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 689
 690 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 691 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 692                          void *accel_priv, select_queue_fallback_t fallback);
 693 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 694 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
 695                                struct mlx4_en_rx_alloc *frame,
 696                                struct mlx4_en_priv *priv, unsigned int length,
 697                                int tx_ind, bool *doorbell_pending);
 698 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
 699 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 700                         struct mlx4_en_rx_alloc *frame);
 701
 702 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 703                            struct mlx4_en_tx_ring **pring,
 704                            u32 size, u16 stride,
 705                            int node, int queue_index);
 706 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 707                              struct mlx4_en_tx_ring **pring);
 708 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
 709                                     struct mlx4_en_tx_ring *ring);
 710 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 711                              struct mlx4_en_tx_ring *ring,
 712                              int cq, int user_prio);
 713 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 714                                 struct mlx4_en_tx_ring *ring);
 715 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 716 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
 717 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 718                            struct mlx4_en_rx_ring **pring,
 719                            u32 size, u16 stride, int node);
 720 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 721                              struct mlx4_en_rx_ring **pring,
 722                              u32 size, u16 stride);
 723 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 724 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 725                                 struct mlx4_en_rx_ring *ring);
 726 int mlx4_en_process_rx_cq(struct net_device *dev,
 727                           struct mlx4_en_cq *cq,
 728                           int budget);
 729 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 730 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 731 bool mlx4_en_process_tx_cq(struct net_device *dev,
 732                            struct mlx4_en_cq *cq, int napi_budget);
 733 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 734                          struct mlx4_en_tx_ring *ring,
 735                          int index, u64 timestamp,
 736                          int napi_mode);
 737 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 738                             struct mlx4_en_tx_ring *ring,
 739                             int index, u64 timestamp,
 740                             int napi_mode);
 741 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 742                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 743                 struct mlx4_qp_context *context);
 744 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 745 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
 746                             int loopback);
 747 void mlx4_en_calc_rx_buf(struct net_device *dev);
 748 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 749 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 750 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 751 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 752 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 753 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 754
 755 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 756 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 757
 758 void mlx4_en_fold_software_stats(struct net_device *dev);
 759 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 760 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 761
 762 #ifdef CONFIG_MLX4_EN_DCB
 763 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 764 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 765 #endif
 766
 767 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 768 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
 769
 770 #ifdef CONFIG_RFS_ACCEL
 771 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 772 #endif
 773
 774 #define MLX4_EN_NUM_SELF_TEST   5
 775 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 776 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 777
 778 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
 779         ((dev->features & feature) ^ (new_features & feature))
 780
 781 int mlx4_en_reset_config(struct net_device *dev,
 782                          struct hwtstamp_config ts_config,
 783                          netdev_features_t new_features);
 784 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
 785                                      struct mlx4_en_stats_bitmap *stats_bitmap,
 786                                      u8 rx_ppp, u8 rx_pause,
 787                                      u8 tx_ppp, u8 tx_pause);
 788 int mlx4_en_netdev_event(struct notifier_block *this,
 789                          unsigned long event, void *ptr);
 790
 791 /*
 792  * Functions for time stamping
 793  */
 794 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 795 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 796                             struct skb_shared_hwtstamps *hwts,
 797                             u64 timestamp);
 798 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 799 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 800
 801 /* Globals
 802  */
 803 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 804
 805
 806
 807 /*
 808  * printk / logging functions
 809  */
 810
 811 __printf(3, 4)
 812 void en_print(const char *level, const struct mlx4_en_priv *priv,
 813               const char *format, ...);
 814
 815 #define en_dbg(mlevel, priv, format, ...)                               \
 816 do {                                                                    \
 817         if (NETIF_MSG_##mlevel & (priv)->msg_enable)                    \
 818                 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);      \
 819 } while (0)
 820 #define en_warn(priv, format, ...)                                      \
 821         en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
 822 #define en_err(priv, format, ...)                                       \
 823         en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
 824 #define en_info(priv, format, ...)                                      \
 825         en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
 826
 827 #define mlx4_err(mdev, format, ...)                                     \
 828         pr_err(DRV_NAME " %s: " format,                                 \
 829                dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 830 #define mlx4_info(mdev, format, ...)                                    \
 831         pr_info(DRV_NAME " %s: " format,                                \
 832                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 833 #define mlx4_warn(mdev, format, ...)                                    \
 834         pr_warn(DRV_NAME " %s: " format,                                \
 835                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 836
 837 #endif