drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58 #include "mlx4_stats.h"
  59
  60 #define DRV_NAME        "mlx4_en"
  61 #define DRV_VERSION     "2.2-1"
  62 #define DRV_RELDATE     "Feb 2014"
  63
  64 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  65
  66 /*
  67  * Device constants
  68  */
  69
  70
  71 #define MLX4_EN_PAGE_SHIFT      12
  72 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  73 #define DEF_RX_RINGS            16
  74 #define MAX_RX_RINGS            128
  75 #define MIN_RX_RINGS            4
  76 #define TXBB_SIZE               64
  77 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  78 #define STAMP_STRIDE            64
  79 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  80 #define STAMP_SHIFT             31
  81 #define STAMP_VAL               0x7fffffff
  82 #define STATS_DELAY             (HZ / 4)
  83 #define SERVICE_TASK_DELAY      (HZ / 4)
  84 #define MAX_NUM_OF_FS_RULES     256
  85
  86 #define MLX4_EN_FILTER_HASH_SHIFT 4
  87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  88
  89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  90 #define MAX_DESC_SIZE           512
  91 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  92
  93 /*
  94  * OS related constants and tunables
  95  */
  96
  97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
  98 #define MLX4_EN_PRIV_FLAGS_PHV       2
  99
 100 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 101
 102 /* Use the maximum between 16384 and a single page */
 103 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 104
 105 #define MLX4_EN_ALLOC_PREFER_ORDER      PAGE_ALLOC_COSTLY_ORDER
 106
 107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
 108  * and 4K allocations) */
 109 enum {
 110         FRAG_SZ0 = 1536 - NET_IP_ALIGN,
 111         FRAG_SZ1 = 4096,
 112         FRAG_SZ2 = 4096,
 113         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 114 };
 115 #define MLX4_EN_MAX_RX_FRAGS    4
 116
 117 /* Maximum ring sizes */
 118 #define MLX4_EN_MAX_TX_SIZE     8192
 119 #define MLX4_EN_MAX_RX_SIZE     8192
 120
 121 /* Minimum ring size for our page-allocation scheme to work */
 122 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 123 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 124
 125 #define MLX4_EN_SMALL_PKT_SIZE          64
 126 #define MLX4_EN_MIN_TX_RING_P_UP        1
 127 #define MLX4_EN_MAX_TX_RING_P_UP        32
 128 #define MLX4_EN_NUM_UP                  8
 129 #define MLX4_EN_DEF_TX_RING_SIZE        512
 130 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 131 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 132                                          MLX4_EN_NUM_UP)
 133
 134 #define MLX4_EN_DEFAULT_TX_WORK         256
 135
 136 /* Target number of packets to coalesce with interrupt moderation */
 137 #define MLX4_EN_RX_COAL_TARGET  44
 138 #define MLX4_EN_RX_COAL_TIME    0x10
 139
 140 #define MLX4_EN_TX_COAL_PKTS    16
 141 #define MLX4_EN_TX_COAL_TIME    0x10
 142
 143 #define MLX4_EN_RX_RATE_LOW             400000
 144 #define MLX4_EN_RX_COAL_TIME_LOW        0
 145 #define MLX4_EN_RX_RATE_HIGH            450000
 146 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 147 #define MLX4_EN_RX_SIZE_THRESH          1024
 148 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 149 #define MLX4_EN_SAMPLE_INTERVAL         0
 150 #define MLX4_EN_AVG_PKT_SMALL           256
 151
 152 #define MLX4_EN_AUTO_CONF       0xffff
 153
 154 #define MLX4_EN_DEF_RX_PAUSE    1
 155 #define MLX4_EN_DEF_TX_PAUSE    1
 156
 157 /* Interval between successive polls in the Tx routine when polling is used
 158    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 159 #define MLX4_EN_TX_POLL_MODER   16
 160 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 161
 162 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 163 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 164 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 165
 166 #define MLX4_EN_MIN_MTU         46
 167 #define ETH_BCAST               0xffffffffffffULL
 168
 169 #define MLX4_EN_LOOPBACK_RETRIES        5
 170 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 171
 172 #ifdef MLX4_EN_PERF_STAT
 173 /* Number of samples to 'average' */
 174 #define AVG_SIZE                        128
 175 #define AVG_FACTOR                      1024
 176
 177 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 178 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 179 #define AVG_PERF_COUNTER(cnt, sample) \
 180         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 181 #define GET_PERF_COUNTER(cnt)           (cnt)
 182 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 183
 184 #else
 185
 186 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 187 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 188 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 189 #define GET_PERF_COUNTER(cnt)           (0)
 190 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 191 #endif /* MLX4_EN_PERF_STAT */
 192
 193 /* Constants for TX flow */
 194 enum {
 195         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 196         MAX_BF = 256,
 197         MIN_PKT_LEN = 17,
 198 };
 199
 200 /*
 201  * Configurables
 202  */
 203
 204 enum cq_type {
 205         RX = 0,
 206         TX = 1,
 207 };
 208
 209
 210 /*
 211  * Useful macros
 212  */
 213 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 214 #define XNOR(x, y)              (!(x) == !(y))
 215
 216
 217 struct mlx4_en_tx_info {
 218         struct sk_buff *skb;
 219         dma_addr_t      map0_dma;
 220         u32             map0_byte_count;
 221         u32             nr_txbb;
 222         u32             nr_bytes;
 223         u8              linear;
 224         u8              data_offset;
 225         u8              inl;
 226         u8              ts_requested;
 227         u8              nr_maps;
 228 } ____cacheline_aligned_in_smp;
 229
 230
 231 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 232 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 233 #define MLX4_EN_MEMTYPE_PAD     0x100
 234 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 235
 236
 237 struct mlx4_en_tx_desc {
 238         struct mlx4_wqe_ctrl_seg ctrl;
 239         union {
 240                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 241                 struct mlx4_wqe_lso_seg lso;
 242                 struct mlx4_wqe_inline_seg inl;
 243         };
 244 };
 245
 246 #define MLX4_EN_USE_SRQ         0x01000000
 247
 248 #define MLX4_EN_CX3_LOW_ID      0x1000
 249 #define MLX4_EN_CX3_HIGH_ID     0x1005
 250
 251 struct mlx4_en_rx_alloc {
 252         struct page     *page;
 253         dma_addr_t      dma;
 254         u32             page_offset;
 255         u32             page_size;
 256 };
 257
 258 struct mlx4_en_tx_ring {
 259         /* cache line used and dirtied in tx completion
 260          * (mlx4_en_free_tx_buf())
 261          */
 262         u32                     last_nr_txbb;
 263         u32                     cons;
 264         unsigned long           wake_queue;
 265
 266         /* cache line used and dirtied in mlx4_en_xmit() */
 267         u32                     prod ____cacheline_aligned_in_smp;
 268         unsigned long           bytes;
 269         unsigned long           packets;
 270         unsigned long           tx_csum;
 271         unsigned long           tso_packets;
 272         unsigned long           xmit_more;
 273         struct mlx4_bf          bf;
 274         unsigned long           queue_stopped;
 275
 276         /* Following part should be mostly read */
 277         cpumask_t               affinity_mask;
 278         struct mlx4_qp          qp;
 279         struct mlx4_hwq_resources wqres;
 280         u32                     size; /* number of TXBBs */
 281         u32                     size_mask;
 282         u16                     stride;
 283         u32                     full_size;
 284         u16                     cqn;    /* index of port CQ associated with this ring */
 285         u32                     buf_size;
 286         __be32                  doorbell_qpn;
 287         __be32                  mr_key;
 288         void                    *buf;
 289         struct mlx4_en_tx_info  *tx_info;
 290         u8                      *bounce_buf;
 291         struct mlx4_qp_context  context;
 292         int                     qpn;
 293         enum mlx4_qp_state      qp_state;
 294         u8                      queue_index;
 295         bool                    bf_enabled;
 296         bool                    bf_alloced;
 297         struct netdev_queue     *tx_queue;
 298         int                     hwtstamp_tx_type;
 299 } ____cacheline_aligned_in_smp;
 300
 301 struct mlx4_en_rx_desc {
 302         /* actual number of entries depends on rx ring stride */
 303         struct mlx4_wqe_data_seg data[0];
 304 };
 305
 306 struct mlx4_en_rx_ring {
 307         struct mlx4_hwq_resources wqres;
 308         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 309         u32 size ;      /* number of Rx descs*/
 310         u32 actual_size;
 311         u32 size_mask;
 312         u16 stride;
 313         u16 log_stride;
 314         u16 cqn;        /* index of port CQ associated with this ring */
 315         u32 prod;
 316         u32 cons;
 317         u32 buf_size;
 318         u8  fcs_del;
 319         void *buf;
 320         void *rx_info;
 321         unsigned long bytes;
 322         unsigned long packets;
 323 #ifdef CONFIG_NET_RX_BUSY_POLL
 324         unsigned long yields;
 325         unsigned long misses;
 326         unsigned long cleaned;
 327 #endif
 328         unsigned long csum_ok;
 329         unsigned long csum_none;
 330         unsigned long csum_complete;
 331         int hwtstamp_rx_filter;
 332         cpumask_var_t affinity_mask;
 333 };
 334
 335 struct mlx4_en_cq {
 336         struct mlx4_cq          mcq;
 337         struct mlx4_hwq_resources wqres;
 338         int                     ring;
 339         struct net_device      *dev;
 340         struct napi_struct      napi;
 341         int size;
 342         int buf_size;
 343         int vector;
 344         enum cq_type is_tx;
 345         u16 moder_time;
 346         u16 moder_cnt;
 347         struct mlx4_cqe *buf;
 348 #define MLX4_EN_OPCODE_ERROR    0x1e
 349
 350 #ifdef CONFIG_NET_RX_BUSY_POLL
 351         unsigned int state;
 352 #define MLX4_EN_CQ_STATE_IDLE        0
 353 #define MLX4_EN_CQ_STATE_NAPI     1    /* NAPI owns this CQ */
 354 #define MLX4_EN_CQ_STATE_POLL     2    /* poll owns this CQ */
 355 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
 356 #define MLX4_EN_CQ_STATE_NAPI_YIELD  4    /* NAPI yielded this CQ */
 357 #define MLX4_EN_CQ_STATE_POLL_YIELD  8    /* poll yielded this CQ */
 358 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
 359 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
 360         spinlock_t poll_lock; /* protects from LLS/napi conflicts */
 361 #endif  /* CONFIG_NET_RX_BUSY_POLL */
 362         struct irq_desc *irq_desc;
 363 };
 364
 365 struct mlx4_en_port_profile {
 366         u32 flags;
 367         u32 tx_ring_num;
 368         u32 rx_ring_num;
 369         u32 tx_ring_size;
 370         u32 rx_ring_size;
 371         u8 rx_pause;
 372         u8 rx_ppp;
 373         u8 tx_pause;
 374         u8 tx_ppp;
 375         int rss_rings;
 376         int inline_thold;
 377 };
 378
 379 struct mlx4_en_profile {
 380         int udp_rss;
 381         u8 rss_mask;
 382         u32 active_ports;
 383         u32 small_pkt_int;
 384         u8 no_reset;
 385         u8 num_tx_rings_p_up;
 386         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 387 };
 388
 389 struct mlx4_en_dev {
 390         struct mlx4_dev         *dev;
 391         struct pci_dev          *pdev;
 392         struct mutex            state_lock;
 393         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 394         struct net_device       *upper[MLX4_MAX_PORTS + 1];
 395         u32                     port_cnt;
 396         bool                    device_up;
 397         struct mlx4_en_profile  profile;
 398         u32                     LSO_support;
 399         struct workqueue_struct *workqueue;
 400         struct device           *dma_device;
 401         void __iomem            *uar_map;
 402         struct mlx4_uar         priv_uar;
 403         struct mlx4_mr          mr;
 404         u32                     priv_pdn;
 405         spinlock_t              uar_lock;
 406         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 407         rwlock_t                clock_lock;
 408         u32                     nominal_c_mult;
 409         struct cyclecounter     cycles;
 410         struct timecounter      clock;
 411         unsigned long           last_overflow_check;
 412         unsigned long           overflow_period;
 413         struct ptp_clock        *ptp_clock;
 414         struct ptp_clock_info   ptp_clock_info;
 415         struct notifier_block   nb;
 416 };
 417
 418
 419 struct mlx4_en_rss_map {
 420         int base_qpn;
 421         struct mlx4_qp qps[MAX_RX_RINGS];
 422         enum mlx4_qp_state state[MAX_RX_RINGS];
 423         struct mlx4_qp indir_qp;
 424         enum mlx4_qp_state indir_state;
 425 };
 426
 427 enum mlx4_en_port_flag {
 428         MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
 429         MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
 430 };
 431
 432 struct mlx4_en_port_state {
 433         int link_state;
 434         int link_speed;
 435         int transceiver;
 436         u32 flags;
 437 };
 438
 439 enum mlx4_en_mclist_act {
 440         MCLIST_NONE,
 441         MCLIST_REM,
 442         MCLIST_ADD,
 443 };
 444
 445 struct mlx4_en_mc_list {
 446         struct list_head        list;
 447         enum mlx4_en_mclist_act action;
 448         u8                      addr[ETH_ALEN];
 449         u64                     reg_id;
 450         u64                     tunnel_reg_id;
 451 };
 452
 453 struct mlx4_en_frag_info {
 454         u16 frag_size;
 455         u16 frag_prefix_size;
 456         u16 frag_stride;
 457 };
 458
 459 #ifdef CONFIG_MLX4_EN_DCB
 460 /* Minimal TC BW - setting to 0 will block traffic */
 461 #define MLX4_EN_BW_MIN 1
 462 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 463
 464 #define MLX4_EN_TC_ETS 7
 465
 466 #endif
 467
 468 struct ethtool_flow_id {
 469         struct list_head list;
 470         struct ethtool_rx_flow_spec flow_spec;
 471         u64 id;
 472 };
 473
 474 enum {
 475         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 476         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 477         /* whether we need to enable hardware loopback by putting dmac
 478          * in Tx WQE
 479          */
 480         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 481         /* whether we need to drop packets that hardware loopback-ed */
 482         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 483         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4),
 484         MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP        = (1 << 5),
 485 };
 486
 487 #define PORT_BEACON_MAX_LIMIT (65535)
 488 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 489 #define MLX4_EN_MAC_HASH_IDX 5
 490
 491 struct mlx4_en_stats_bitmap {
 492         DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
 493         struct mutex mutex; /* for mutual access to stats bitmap */
 494 };
 495
 496 struct mlx4_en_priv {
 497         struct mlx4_en_dev *mdev;
 498         struct mlx4_en_port_profile *prof;
 499         struct net_device *dev;
 500         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 501         struct net_device_stats stats;
 502         struct net_device_stats ret_stats;
 503         struct mlx4_en_port_state port_state;
 504         spinlock_t stats_lock;
 505         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 506         /* To allow rules removal while port is going down */
 507         struct list_head ethtool_list;
 508
 509         unsigned long last_moder_packets[MAX_RX_RINGS];
 510         unsigned long last_moder_tx_packets;
 511         unsigned long last_moder_bytes[MAX_RX_RINGS];
 512         unsigned long last_moder_jiffies;
 513         int last_moder_time[MAX_RX_RINGS];
 514         u16 rx_usecs;
 515         u16 rx_frames;
 516         u16 tx_usecs;
 517         u16 tx_frames;
 518         u32 pkt_rate_low;
 519         u16 rx_usecs_low;
 520         u32 pkt_rate_high;
 521         u16 rx_usecs_high;
 522         u16 sample_interval;
 523         u16 adaptive_rx_coal;
 524         u32 msg_enable;
 525         u32 loopback_ok;
 526         u32 validate_loopback;
 527
 528         struct mlx4_hwq_resources res;
 529         int link_state;
 530         int last_link_state;
 531         bool port_up;
 532         int port;
 533         int registered;
 534         int allocated;
 535         int stride;
 536         unsigned char current_mac[ETH_ALEN + 2];
 537         int mac_index;
 538         unsigned max_mtu;
 539         int base_qpn;
 540         int cqe_factor;
 541         int cqe_size;
 542
 543         struct mlx4_en_rss_map rss_map;
 544         __be32 ctrl_flags;
 545         u32 flags;
 546         u8 num_tx_rings_p_up;
 547         u32 tx_work_limit;
 548         u32 tx_ring_num;
 549         u32 rx_ring_num;
 550         u32 rx_skb_size;
 551         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 552         u16 num_frags;
 553         u16 log_rx_info;
 554
 555         struct mlx4_en_tx_ring **tx_ring;
 556         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 557         struct mlx4_en_cq **tx_cq;
 558         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 559         struct mlx4_qp drop_qp;
 560         struct work_struct rx_mode_task;
 561         struct work_struct watchdog_task;
 562         struct work_struct linkstate_task;
 563         struct delayed_work stats_task;
 564         struct delayed_work service_task;
 565 #ifdef CONFIG_MLX4_EN_VXLAN
 566         struct work_struct vxlan_add_task;
 567         struct work_struct vxlan_del_task;
 568 #endif
 569         struct mlx4_en_perf_stats pstats;
 570         struct mlx4_en_pkt_stats pkstats;
 571         struct mlx4_en_counter_stats pf_stats;
 572         struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
 573         struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
 574         struct mlx4_en_flow_stats_rx rx_flowstats;
 575         struct mlx4_en_flow_stats_tx tx_flowstats;
 576         struct mlx4_en_port_stats port_stats;
 577         struct mlx4_en_stats_bitmap stats_bitmap;
 578         struct list_head mc_list;
 579         struct list_head curr_list;
 580         u64 broadcast_id;
 581         struct mlx4_en_stat_out_mbox hw_stats;
 582         int vids[128];
 583         bool wol;
 584         struct device *ddev;
 585         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 586         struct hwtstamp_config hwtstamp_config;
 587         u32 counter_index;
 588
 589 #ifdef CONFIG_MLX4_EN_DCB
 590         struct ieee_ets ets;
 591         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 592         enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
 593 #endif
 594 #ifdef CONFIG_RFS_ACCEL
 595         spinlock_t filters_lock;
 596         int last_filter_id;
 597         struct list_head filters;
 598         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 599 #endif
 600         u64 tunnel_reg_id;
 601         __be16 vxlan_port;
 602
 603         u32 pflags;
 604         u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
 605         u8 rss_hash_fn;
 606 };
 607
 608 enum mlx4_en_wol {
 609         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 610         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 611 };
 612
 613 struct mlx4_mac_entry {
 614         struct hlist_node hlist;
 615         unsigned char mac[ETH_ALEN + 2];
 616         u64 reg_id;
 617         struct rcu_head rcu;
 618 };
 619
 620 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
 621 {
 622         return buf + idx * cqe_sz;
 623 }
 624
 625 #ifdef CONFIG_NET_RX_BUSY_POLL
 626 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 627 {
 628         spin_lock_init(&cq->poll_lock);
 629         cq->state = MLX4_EN_CQ_STATE_IDLE;
 630 }
 631
 632 /* called from the device poll rutine to get ownership of a cq */
 633 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 634 {
 635         int rc = true;
 636         spin_lock(&cq->poll_lock);
 637         if (cq->state & MLX4_CQ_LOCKED) {
 638                 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
 639                 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
 640                 rc = false;
 641         } else
 642                 /* we don't care if someone yielded */
 643                 cq->state = MLX4_EN_CQ_STATE_NAPI;
 644         spin_unlock(&cq->poll_lock);
 645         return rc;
 646 }
 647
 648 /* returns true is someone tried to get the cq while napi had it */
 649 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 650 {
 651         int rc = false;
 652         spin_lock(&cq->poll_lock);
 653         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
 654                                MLX4_EN_CQ_STATE_NAPI_YIELD));
 655
 656         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 657                 rc = true;
 658         cq->state = MLX4_EN_CQ_STATE_IDLE;
 659         spin_unlock(&cq->poll_lock);
 660         return rc;
 661 }
 662
 663 /* called from mlx4_en_low_latency_poll() */
 664 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 665 {
 666         int rc = true;
 667         spin_lock_bh(&cq->poll_lock);
 668         if ((cq->state & MLX4_CQ_LOCKED)) {
 669                 struct net_device *dev = cq->dev;
 670                 struct mlx4_en_priv *priv = netdev_priv(dev);
 671                 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
 672
 673                 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
 674                 rc = false;
 675                 rx_ring->yields++;
 676         } else
 677                 /* preserve yield marks */
 678                 cq->state |= MLX4_EN_CQ_STATE_POLL;
 679         spin_unlock_bh(&cq->poll_lock);
 680         return rc;
 681 }
 682
 683 /* returns true if someone tried to get the cq while it was locked */
 684 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 685 {
 686         int rc = false;
 687         spin_lock_bh(&cq->poll_lock);
 688         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
 689
 690         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 691                 rc = true;
 692         cq->state = MLX4_EN_CQ_STATE_IDLE;
 693         spin_unlock_bh(&cq->poll_lock);
 694         return rc;
 695 }
 696
 697 /* true if a socket is polling, even if it did not get the lock */
 698 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 699 {
 700         WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
 701         return cq->state & CQ_USER_PEND;
 702 }
 703 #else
 704 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 705 {
 706 }
 707
 708 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 709 {
 710         return true;
 711 }
 712
 713 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 714 {
 715         return false;
 716 }
 717
 718 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 719 {
 720         return false;
 721 }
 722
 723 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 724 {
 725         return false;
 726 }
 727
 728 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 729 {
 730         return false;
 731 }
 732 #endif /* CONFIG_NET_RX_BUSY_POLL */
 733
 734 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 735
 736 void mlx4_en_update_loopback_state(struct net_device *dev,
 737                                    netdev_features_t features);
 738
 739 void mlx4_en_destroy_netdev(struct net_device *dev);
 740 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 741                         struct mlx4_en_port_profile *prof);
 742
 743 int mlx4_en_start_port(struct net_device *dev);
 744 void mlx4_en_stop_port(struct net_device *dev, int detach);
 745
 746 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
 747                               struct mlx4_en_stats_bitmap *stats_bitmap,
 748                               u8 rx_ppp, u8 rx_pause,
 749                               u8 tx_ppp, u8 tx_pause);
 750
 751 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 752 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 753
 754 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 755                       int entries, int ring, enum cq_type mode, int node);
 756 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 757 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 758                         int cq_idx);
 759 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 760 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 761 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 762
 763 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 764 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 765                          void *accel_priv, select_queue_fallback_t fallback);
 766 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 767
 768 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 769                            struct mlx4_en_tx_ring **pring,
 770                            u32 size, u16 stride,
 771                            int node, int queue_index);
 772 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 773                              struct mlx4_en_tx_ring **pring);
 774 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 775                              struct mlx4_en_tx_ring *ring,
 776                              int cq, int user_prio);
 777 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 778                                 struct mlx4_en_tx_ring *ring);
 779 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 780 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
 781 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 782                            struct mlx4_en_rx_ring **pring,
 783                            u32 size, u16 stride, int node);
 784 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 785                              struct mlx4_en_rx_ring **pring,
 786                              u32 size, u16 stride);
 787 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 788 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 789                                 struct mlx4_en_rx_ring *ring);
 790 int mlx4_en_process_rx_cq(struct net_device *dev,
 791                           struct mlx4_en_cq *cq,
 792                           int budget);
 793 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 794 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 795 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 796                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 797                 struct mlx4_qp_context *context);
 798 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 799 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 800 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 801
 802 void mlx4_en_calc_rx_buf(struct net_device *dev);
 803 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 804 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 805 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 806 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 807 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 808 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 809
 810 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 811 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 812
 813 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 814 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 815
 816 #ifdef CONFIG_MLX4_EN_DCB
 817 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 818 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 819 #endif
 820
 821 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 822
 823 #ifdef CONFIG_RFS_ACCEL
 824 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 825 #endif
 826
 827 #define MLX4_EN_NUM_SELF_TEST   5
 828 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 829 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 830
 831 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
 832         ((dev->features & feature) ^ (new_features & feature))
 833
 834 int mlx4_en_reset_config(struct net_device *dev,
 835                          struct hwtstamp_config ts_config,
 836                          netdev_features_t new_features);
 837 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
 838                                      struct mlx4_en_stats_bitmap *stats_bitmap,
 839                                      u8 rx_ppp, u8 rx_pause,
 840                                      u8 tx_ppp, u8 tx_pause);
 841 int mlx4_en_netdev_event(struct notifier_block *this,
 842                          unsigned long event, void *ptr);
 843
 844 /*
 845  * Functions for time stamping
 846  */
 847 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 848 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 849                             struct skb_shared_hwtstamps *hwts,
 850                             u64 timestamp);
 851 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 852 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 853
 854 /* Globals
 855  */
 856 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 857
 858
 859
 860 /*
 861  * printk / logging functions
 862  */
 863
 864 __printf(3, 4)
 865 void en_print(const char *level, const struct mlx4_en_priv *priv,
 866               const char *format, ...);
 867
 868 #define en_dbg(mlevel, priv, format, ...)                               \
 869 do {                                                                    \
 870         if (NETIF_MSG_##mlevel & (priv)->msg_enable)                    \
 871                 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);      \
 872 } while (0)
 873 #define en_warn(priv, format, ...)                                      \
 874         en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
 875 #define en_err(priv, format, ...)                                       \
 876         en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
 877 #define en_info(priv, format, ...)                                      \
 878         en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
 879
 880 #define mlx4_err(mdev, format, ...)                                     \
 881         pr_err(DRV_NAME " %s: " format,                                 \
 882                dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 883 #define mlx4_info(mdev, format, ...)                                    \
 884         pr_info(DRV_NAME " %s: " format,                                \
 885                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 886 #define mlx4_warn(mdev, format, ...)                                    \
 887         pr_warn(DRV_NAME " %s: " format,                                \
 888                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 889
 890 #endif