2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/if_vlan.h>
36 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
42 #define MLX4_MAC_VALID (1ull << 63)
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev
*dev
, struct mlx4_mac_table
*table
)
56 mutex_init(&table
->mutex
);
57 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
58 table
->entries
[i
] = 0;
61 table
->max
= 1 << dev
->caps
.log_num_macs
;
65 void mlx4_init_vlan_table(struct mlx4_dev
*dev
, struct mlx4_vlan_table
*table
)
69 mutex_init(&table
->mutex
);
70 for (i
= 0; i
< MLX4_MAX_VLAN_NUM
; i
++) {
71 table
->entries
[i
] = 0;
74 table
->max
= (1 << dev
->caps
.log_num_vlans
) - MLX4_VLAN_REGULAR
;
78 static int validate_index(struct mlx4_dev
*dev
,
79 struct mlx4_mac_table
*table
, int index
)
83 if (index
< 0 || index
>= table
->max
|| !table
->entries
[index
]) {
84 mlx4_warn(dev
, "No valid Mac entry for the given index\n");
90 static int find_index(struct mlx4_dev
*dev
,
91 struct mlx4_mac_table
*table
, u64 mac
)
95 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
96 if ((mac
& MLX4_MAC_MASK
) ==
97 (MLX4_MAC_MASK
& be64_to_cpu(table
->entries
[i
])))
104 static int mlx4_set_port_mac_table(struct mlx4_dev
*dev
, u8 port
,
107 struct mlx4_cmd_mailbox
*mailbox
;
111 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
113 return PTR_ERR(mailbox
);
115 memcpy(mailbox
->buf
, entries
, MLX4_MAC_TABLE_SIZE
);
117 in_mod
= MLX4_SET_PORT_MAC_TABLE
<< 8 | port
;
119 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
120 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
122 mlx4_free_cmd_mailbox(dev
, mailbox
);
126 int mlx4_find_cached_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *idx
)
128 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
129 struct mlx4_mac_table
*table
= &info
->mac_table
;
132 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
136 if (mac
== (MLX4_MAC_MASK
& be64_to_cpu(table
->entries
[i
]))) {
144 EXPORT_SYMBOL_GPL(mlx4_find_cached_mac
);
146 int __mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
148 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
149 struct mlx4_mac_table
*table
= &info
->mac_table
;
153 mlx4_dbg(dev
, "Registering MAC: 0x%llx for port %d\n",
154 (unsigned long long) mac
, port
);
156 mutex_lock(&table
->mutex
);
157 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
158 if (free
< 0 && !table
->entries
[i
]) {
163 if (mac
== (MLX4_MAC_MASK
& be64_to_cpu(table
->entries
[i
]))) {
164 /* MAC already registered, increment ref count */
171 mlx4_dbg(dev
, "Free MAC index is %d\n", free
);
173 if (table
->total
== table
->max
) {
174 /* No free mac entries */
179 /* Register new MAC */
180 table
->entries
[free
] = cpu_to_be64(mac
| MLX4_MAC_VALID
);
182 err
= mlx4_set_port_mac_table(dev
, port
, table
->entries
);
184 mlx4_err(dev
, "Failed adding MAC: 0x%llx\n",
185 (unsigned long long) mac
);
186 table
->entries
[free
] = 0;
189 table
->refs
[free
] = 1;
193 mutex_unlock(&table
->mutex
);
196 EXPORT_SYMBOL_GPL(__mlx4_register_mac
);
198 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
203 if (mlx4_is_mfunc(dev
)) {
204 if (!(dev
->flags
& MLX4_FLAG_OLD_REG_MAC
)) {
205 err
= mlx4_cmd_imm(dev
, mac
, &out_param
,
206 ((u32
) port
) << 8 | (u32
) RES_MAC
,
207 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
208 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
210 if (err
&& err
== -EINVAL
&& mlx4_is_slave(dev
)) {
211 /* retry using old REG_MAC format */
212 set_param_l(&out_param
, port
);
213 err
= mlx4_cmd_imm(dev
, mac
, &out_param
, RES_MAC
,
214 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
215 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
217 dev
->flags
|= MLX4_FLAG_OLD_REG_MAC
;
222 return get_param_l(&out_param
);
224 return __mlx4_register_mac(dev
, port
, mac
);
226 EXPORT_SYMBOL_GPL(mlx4_register_mac
);
228 int mlx4_get_base_qpn(struct mlx4_dev
*dev
, u8 port
)
230 return dev
->caps
.reserved_qps_base
[MLX4_QP_REGION_ETH_ADDR
] +
231 (port
- 1) * (1 << dev
->caps
.log_num_macs
);
233 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn
);
235 void __mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
237 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
238 struct mlx4_mac_table
*table
= &info
->mac_table
;
241 mutex_lock(&table
->mutex
);
242 index
= find_index(dev
, table
, mac
);
244 if (validate_index(dev
, table
, index
))
246 if (--table
->refs
[index
]) {
247 mlx4_dbg(dev
, "Have more references for index %d,"
248 "no need to modify mac table\n", index
);
252 table
->entries
[index
] = 0;
253 mlx4_set_port_mac_table(dev
, port
, table
->entries
);
256 mutex_unlock(&table
->mutex
);
258 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac
);
260 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
264 if (mlx4_is_mfunc(dev
)) {
265 if (!(dev
->flags
& MLX4_FLAG_OLD_REG_MAC
)) {
266 (void) mlx4_cmd_imm(dev
, mac
, &out_param
,
267 ((u32
) port
) << 8 | (u32
) RES_MAC
,
268 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_FREE_RES
,
269 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
271 /* use old unregister mac format */
272 set_param_l(&out_param
, port
);
273 (void) mlx4_cmd_imm(dev
, mac
, &out_param
, RES_MAC
,
274 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_FREE_RES
,
275 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
279 __mlx4_unregister_mac(dev
, port
, mac
);
282 EXPORT_SYMBOL_GPL(mlx4_unregister_mac
);
284 int __mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
)
286 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
287 struct mlx4_mac_table
*table
= &info
->mac_table
;
288 int index
= qpn
- info
->base_qpn
;
291 /* CX1 doesn't support multi-functions */
292 mutex_lock(&table
->mutex
);
294 err
= validate_index(dev
, table
, index
);
298 table
->entries
[index
] = cpu_to_be64(new_mac
| MLX4_MAC_VALID
);
300 err
= mlx4_set_port_mac_table(dev
, port
, table
->entries
);
302 mlx4_err(dev
, "Failed adding MAC: 0x%llx\n",
303 (unsigned long long) new_mac
);
304 table
->entries
[index
] = 0;
307 mutex_unlock(&table
->mutex
);
310 EXPORT_SYMBOL_GPL(__mlx4_replace_mac
);
312 static int mlx4_set_port_vlan_table(struct mlx4_dev
*dev
, u8 port
,
315 struct mlx4_cmd_mailbox
*mailbox
;
319 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
321 return PTR_ERR(mailbox
);
323 memcpy(mailbox
->buf
, entries
, MLX4_VLAN_TABLE_SIZE
);
324 in_mod
= MLX4_SET_PORT_VLAN_TABLE
<< 8 | port
;
325 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
326 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
328 mlx4_free_cmd_mailbox(dev
, mailbox
);
333 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
)
335 struct mlx4_vlan_table
*table
= &mlx4_priv(dev
)->port
[port
].vlan_table
;
338 for (i
= 0; i
< MLX4_MAX_VLAN_NUM
; ++i
) {
339 if (table
->refs
[i
] &&
340 (vid
== (MLX4_VLAN_MASK
&
341 be32_to_cpu(table
->entries
[i
])))) {
342 /* VLAN already registered, increase reference count */
350 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan
);
352 int __mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
,
355 struct mlx4_vlan_table
*table
= &mlx4_priv(dev
)->port
[port
].vlan_table
;
359 mutex_lock(&table
->mutex
);
361 if (table
->total
== table
->max
) {
362 /* No free vlan entries */
367 for (i
= MLX4_VLAN_REGULAR
; i
< MLX4_MAX_VLAN_NUM
; i
++) {
368 if (free
< 0 && (table
->refs
[i
] == 0)) {
373 if (table
->refs
[i
] &&
374 (vlan
== (MLX4_VLAN_MASK
&
375 be32_to_cpu(table
->entries
[i
])))) {
376 /* Vlan already registered, increase references count */
388 /* Register new VLAN */
389 table
->refs
[free
] = 1;
390 table
->entries
[free
] = cpu_to_be32(vlan
| MLX4_VLAN_VALID
);
392 err
= mlx4_set_port_vlan_table(dev
, port
, table
->entries
);
394 mlx4_warn(dev
, "Failed adding vlan: %u\n", vlan
);
395 table
->refs
[free
] = 0;
396 table
->entries
[free
] = 0;
403 mutex_unlock(&table
->mutex
);
407 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
)
415 if (mlx4_is_mfunc(dev
)) {
416 err
= mlx4_cmd_imm(dev
, vlan
, &out_param
,
417 ((u32
) port
) << 8 | (u32
) RES_VLAN
,
418 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
419 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
421 *index
= get_param_l(&out_param
);
425 return __mlx4_register_vlan(dev
, port
, vlan
, index
);
427 EXPORT_SYMBOL_GPL(mlx4_register_vlan
);
429 void __mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
)
431 struct mlx4_vlan_table
*table
= &mlx4_priv(dev
)->port
[port
].vlan_table
;
434 mutex_lock(&table
->mutex
);
435 if (mlx4_find_cached_vlan(dev
, port
, vlan
, &index
)) {
436 mlx4_warn(dev
, "vlan 0x%x is not in the vlan table\n", vlan
);
440 if (index
< MLX4_VLAN_REGULAR
) {
441 mlx4_warn(dev
, "Trying to free special vlan index %d\n", index
);
445 if (--table
->refs
[index
]) {
446 mlx4_dbg(dev
, "Have %d more references for index %d,"
447 "no need to modify vlan table\n", table
->refs
[index
],
451 table
->entries
[index
] = 0;
452 mlx4_set_port_vlan_table(dev
, port
, table
->entries
);
455 mutex_unlock(&table
->mutex
);
458 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
)
462 if (mlx4_is_mfunc(dev
)) {
463 (void) mlx4_cmd_imm(dev
, vlan
, &out_param
,
464 ((u32
) port
) << 8 | (u32
) RES_VLAN
,
465 RES_OP_RESERVE_AND_MAP
,
466 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
470 __mlx4_unregister_vlan(dev
, port
, vlan
);
472 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan
);
474 int mlx4_get_port_ib_caps(struct mlx4_dev
*dev
, u8 port
, __be32
*caps
)
476 struct mlx4_cmd_mailbox
*inmailbox
, *outmailbox
;
480 inmailbox
= mlx4_alloc_cmd_mailbox(dev
);
481 if (IS_ERR(inmailbox
))
482 return PTR_ERR(inmailbox
);
484 outmailbox
= mlx4_alloc_cmd_mailbox(dev
);
485 if (IS_ERR(outmailbox
)) {
486 mlx4_free_cmd_mailbox(dev
, inmailbox
);
487 return PTR_ERR(outmailbox
);
490 inbuf
= inmailbox
->buf
;
491 outbuf
= outmailbox
->buf
;
496 *(__be16
*) (&inbuf
[16]) = cpu_to_be16(0x0015);
497 *(__be32
*) (&inbuf
[20]) = cpu_to_be32(port
);
499 err
= mlx4_cmd_box(dev
, inmailbox
->dma
, outmailbox
->dma
, port
, 3,
500 MLX4_CMD_MAD_IFC
, MLX4_CMD_TIME_CLASS_C
,
503 *caps
= *(__be32
*) (outbuf
+ 84);
504 mlx4_free_cmd_mailbox(dev
, inmailbox
);
505 mlx4_free_cmd_mailbox(dev
, outmailbox
);
509 static int mlx4_common_set_port(struct mlx4_dev
*dev
, int slave
, u32 in_mod
,
510 u8 op_mod
, struct mlx4_cmd_mailbox
*inbox
)
512 struct mlx4_priv
*priv
= mlx4_priv(dev
);
513 struct mlx4_port_info
*port_info
;
514 struct mlx4_mfunc_master_ctx
*master
= &priv
->mfunc
.master
;
515 struct mlx4_slave_state
*slave_st
= &master
->slave_state
[slave
];
516 struct mlx4_set_port_rqp_calc_context
*qpn_context
;
517 struct mlx4_set_port_general_context
*gen_context
;
518 int reset_qkey_viols
;
527 __be32 slave_cap_mask
;
530 port
= in_mod
& 0xff;
531 in_modifier
= in_mod
>> 8;
533 port_info
= &priv
->port
[port
];
535 /* Slaves cannot perform SET_PORT operations except changing MTU */
537 if (slave
!= dev
->caps
.function
&&
538 in_modifier
!= MLX4_SET_PORT_GENERAL
) {
539 mlx4_warn(dev
, "denying SET_PORT for slave:%d\n",
543 switch (in_modifier
) {
544 case MLX4_SET_PORT_RQP_CALC
:
545 qpn_context
= inbox
->buf
;
546 qpn_context
->base_qpn
=
547 cpu_to_be32(port_info
->base_qpn
);
548 qpn_context
->n_mac
= 0x7;
549 promisc
= be32_to_cpu(qpn_context
->promisc
) >>
550 SET_PORT_PROMISC_SHIFT
;
551 qpn_context
->promisc
= cpu_to_be32(
552 promisc
<< SET_PORT_PROMISC_SHIFT
|
553 port_info
->base_qpn
);
554 promisc
= be32_to_cpu(qpn_context
->mcast
) >>
555 SET_PORT_MC_PROMISC_SHIFT
;
556 qpn_context
->mcast
= cpu_to_be32(
557 promisc
<< SET_PORT_MC_PROMISC_SHIFT
|
558 port_info
->base_qpn
);
560 case MLX4_SET_PORT_GENERAL
:
561 gen_context
= inbox
->buf
;
562 /* Mtu is configured as the max MTU among all the
563 * the functions on the port. */
564 mtu
= be16_to_cpu(gen_context
->mtu
);
565 mtu
= min_t(int, mtu
, dev
->caps
.eth_mtu_cap
[port
] +
566 ETH_HLEN
+ VLAN_HLEN
+ ETH_FCS_LEN
);
567 prev_mtu
= slave_st
->mtu
[port
];
568 slave_st
->mtu
[port
] = mtu
;
569 if (mtu
> master
->max_mtu
[port
])
570 master
->max_mtu
[port
] = mtu
;
571 if (mtu
< prev_mtu
&& prev_mtu
==
572 master
->max_mtu
[port
]) {
573 slave_st
->mtu
[port
] = mtu
;
574 master
->max_mtu
[port
] = mtu
;
575 for (i
= 0; i
< dev
->num_slaves
; i
++) {
576 master
->max_mtu
[port
] =
577 max(master
->max_mtu
[port
],
578 master
->slave_state
[i
].mtu
[port
]);
582 gen_context
->mtu
= cpu_to_be16(master
->max_mtu
[port
]);
585 return mlx4_cmd(dev
, inbox
->dma
, in_mod
, op_mod
,
586 MLX4_CMD_SET_PORT
, MLX4_CMD_TIME_CLASS_B
,
590 /* For IB, we only consider:
591 * - The capability mask, which is set to the aggregate of all
592 * slave function capabilities
593 * - The QKey violatin counter - reset according to each request.
596 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
597 reset_qkey_viols
= (*(u8
*) inbox
->buf
) & 0x40;
598 new_cap_mask
= ((__be32
*) inbox
->buf
)[2];
600 reset_qkey_viols
= ((u8
*) inbox
->buf
)[3] & 0x1;
601 new_cap_mask
= ((__be32
*) inbox
->buf
)[1];
604 /* slave may not set the IS_SM capability for the port */
605 if (slave
!= mlx4_master_func_num(dev
) &&
606 (be32_to_cpu(new_cap_mask
) & MLX4_PORT_CAP_IS_SM
))
609 /* No DEV_MGMT in multifunc mode */
610 if (mlx4_is_mfunc(dev
) &&
611 (be32_to_cpu(new_cap_mask
) & MLX4_PORT_CAP_DEV_MGMT_SUP
))
616 priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
];
617 priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
] = new_cap_mask
;
618 for (i
= 0; i
< dev
->num_slaves
; i
++)
620 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
];
622 /* only clear mailbox for guests. Master may be setting
623 * MTU or PKEY table size
625 if (slave
!= dev
->caps
.function
)
626 memset(inbox
->buf
, 0, 256);
627 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
628 *(u8
*) inbox
->buf
|= !!reset_qkey_viols
<< 6;
629 ((__be32
*) inbox
->buf
)[2] = agg_cap_mask
;
631 ((u8
*) inbox
->buf
)[3] |= !!reset_qkey_viols
;
632 ((__be32
*) inbox
->buf
)[1] = agg_cap_mask
;
635 err
= mlx4_cmd(dev
, inbox
->dma
, port
, is_eth
, MLX4_CMD_SET_PORT
,
636 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
638 priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
] =
643 int mlx4_SET_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
644 struct mlx4_vhcr
*vhcr
,
645 struct mlx4_cmd_mailbox
*inbox
,
646 struct mlx4_cmd_mailbox
*outbox
,
647 struct mlx4_cmd_info
*cmd
)
649 return mlx4_common_set_port(dev
, slave
, vhcr
->in_modifier
,
650 vhcr
->op_modifier
, inbox
);
653 /* bit locations for set port command with zero op modifier */
655 MLX4_SET_PORT_VL_CAP
= 4, /* bits 7:4 */
656 MLX4_SET_PORT_MTU_CAP
= 12, /* bits 15:12 */
657 MLX4_CHANGE_PORT_PKEY_TBL_SZ
= 20,
658 MLX4_CHANGE_PORT_VL_CAP
= 21,
659 MLX4_CHANGE_PORT_MTU_CAP
= 22,
662 int mlx4_SET_PORT(struct mlx4_dev
*dev
, u8 port
, int pkey_tbl_sz
)
664 struct mlx4_cmd_mailbox
*mailbox
;
665 int err
, vl_cap
, pkey_tbl_flag
= 0;
667 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
670 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
672 return PTR_ERR(mailbox
);
674 ((__be32
*) mailbox
->buf
)[1] = dev
->caps
.ib_port_def_cap
[port
];
676 if (pkey_tbl_sz
>= 0 && mlx4_is_master(dev
)) {
678 ((__be16
*) mailbox
->buf
)[20] = cpu_to_be16(pkey_tbl_sz
);
681 /* IB VL CAP enum isn't used by the firmware, just numerical values */
682 for (vl_cap
= 8; vl_cap
>= 1; vl_cap
>>= 1) {
683 ((__be32
*) mailbox
->buf
)[0] = cpu_to_be32(
684 (1 << MLX4_CHANGE_PORT_MTU_CAP
) |
685 (1 << MLX4_CHANGE_PORT_VL_CAP
) |
686 (pkey_tbl_flag
<< MLX4_CHANGE_PORT_PKEY_TBL_SZ
) |
687 (dev
->caps
.port_ib_mtu
[port
] << MLX4_SET_PORT_MTU_CAP
) |
688 (vl_cap
<< MLX4_SET_PORT_VL_CAP
));
689 err
= mlx4_cmd(dev
, mailbox
->dma
, port
, 0, MLX4_CMD_SET_PORT
,
690 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
695 mlx4_free_cmd_mailbox(dev
, mailbox
);
699 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
700 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
)
702 struct mlx4_cmd_mailbox
*mailbox
;
703 struct mlx4_set_port_general_context
*context
;
707 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
709 return PTR_ERR(mailbox
);
710 context
= mailbox
->buf
;
711 context
->flags
= SET_PORT_GEN_ALL_VALID
;
712 context
->mtu
= cpu_to_be16(mtu
);
713 context
->pptx
= (pptx
* (!pfctx
)) << 7;
714 context
->pfctx
= pfctx
;
715 context
->pprx
= (pprx
* (!pfcrx
)) << 7;
716 context
->pfcrx
= pfcrx
;
718 in_mod
= MLX4_SET_PORT_GENERAL
<< 8 | port
;
719 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
720 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
722 mlx4_free_cmd_mailbox(dev
, mailbox
);
725 EXPORT_SYMBOL(mlx4_SET_PORT_general
);
727 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
730 struct mlx4_cmd_mailbox
*mailbox
;
731 struct mlx4_set_port_rqp_calc_context
*context
;
734 u32 m_promisc
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
) ?
735 MCAST_DIRECT
: MCAST_DEFAULT
;
737 if (dev
->caps
.steering_mode
!= MLX4_STEERING_MODE_A0
)
740 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
742 return PTR_ERR(mailbox
);
743 context
= mailbox
->buf
;
744 context
->base_qpn
= cpu_to_be32(base_qpn
);
745 context
->n_mac
= dev
->caps
.log_num_macs
;
746 context
->promisc
= cpu_to_be32(promisc
<< SET_PORT_PROMISC_SHIFT
|
748 context
->mcast
= cpu_to_be32(m_promisc
<< SET_PORT_MC_PROMISC_SHIFT
|
750 context
->intra_no_vlan
= 0;
751 context
->no_vlan
= MLX4_NO_VLAN_IDX
;
752 context
->intra_vlan_miss
= 0;
753 context
->vlan_miss
= MLX4_VLAN_MISS_IDX
;
755 in_mod
= MLX4_SET_PORT_RQP_CALC
<< 8 | port
;
756 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
757 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
759 mlx4_free_cmd_mailbox(dev
, mailbox
);
762 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc
);
764 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
)
766 struct mlx4_cmd_mailbox
*mailbox
;
767 struct mlx4_set_port_prio2tc_context
*context
;
772 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
774 return PTR_ERR(mailbox
);
775 context
= mailbox
->buf
;
776 for (i
= 0; i
< MLX4_NUM_UP
; i
+= 2)
777 context
->prio2tc
[i
>> 1] = prio2tc
[i
] << 4 | prio2tc
[i
+ 1];
779 in_mod
= MLX4_SET_PORT_PRIO2TC
<< 8 | port
;
780 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
781 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
783 mlx4_free_cmd_mailbox(dev
, mailbox
);
786 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC
);
788 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
789 u8
*pg
, u16
*ratelimit
)
791 struct mlx4_cmd_mailbox
*mailbox
;
792 struct mlx4_set_port_scheduler_context
*context
;
797 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
799 return PTR_ERR(mailbox
);
800 context
= mailbox
->buf
;
802 for (i
= 0; i
< MLX4_NUM_TC
; i
++) {
803 struct mlx4_port_scheduler_tc_cfg_be
*tc
= &context
->tc
[i
];
804 u16 r
= ratelimit
&& ratelimit
[i
] ? ratelimit
[i
] :
805 MLX4_RATELIMIT_DEFAULT
;
807 tc
->pg
= htons(pg
[i
]);
808 tc
->bw_precentage
= htons(tc_tx_bw
[i
]);
810 tc
->max_bw_units
= htons(MLX4_RATELIMIT_UNITS
);
811 tc
->max_bw_value
= htons(r
);
814 in_mod
= MLX4_SET_PORT_SCHEDULER
<< 8 | port
;
815 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
816 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
818 mlx4_free_cmd_mailbox(dev
, mailbox
);
821 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER
);
823 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev
*dev
, int slave
,
824 struct mlx4_vhcr
*vhcr
,
825 struct mlx4_cmd_mailbox
*inbox
,
826 struct mlx4_cmd_mailbox
*outbox
,
827 struct mlx4_cmd_info
*cmd
)
834 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
,
835 u64 mac
, u64 clear
, u8 mode
)
837 return mlx4_cmd(dev
, (mac
| (clear
<< 63)), port
, mode
,
838 MLX4_CMD_SET_MCAST_FLTR
, MLX4_CMD_TIME_CLASS_B
,
841 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR
);
843 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev
*dev
, int slave
,
844 struct mlx4_vhcr
*vhcr
,
845 struct mlx4_cmd_mailbox
*inbox
,
846 struct mlx4_cmd_mailbox
*outbox
,
847 struct mlx4_cmd_info
*cmd
)
854 int mlx4_common_dump_eth_stats(struct mlx4_dev
*dev
, int slave
,
855 u32 in_mod
, struct mlx4_cmd_mailbox
*outbox
)
857 return mlx4_cmd_box(dev
, 0, outbox
->dma
, in_mod
, 0,
858 MLX4_CMD_DUMP_ETH_STATS
, MLX4_CMD_TIME_CLASS_B
,
862 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev
*dev
, int slave
,
863 struct mlx4_vhcr
*vhcr
,
864 struct mlx4_cmd_mailbox
*inbox
,
865 struct mlx4_cmd_mailbox
*outbox
,
866 struct mlx4_cmd_info
*cmd
)
868 if (slave
!= dev
->caps
.function
)
870 return mlx4_common_dump_eth_stats(dev
, slave
,
871 vhcr
->in_modifier
, outbox
);
874 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
)
876 if (!mlx4_is_mfunc(dev
)) {
881 *stats_bitmap
= (MLX4_STATS_TRAFFIC_COUNTERS_MASK
|
882 MLX4_STATS_TRAFFIC_DROPS_MASK
|
883 MLX4_STATS_PORT_COUNTERS_MASK
);
885 if (mlx4_is_master(dev
))
886 *stats_bitmap
|= MLX4_STATS_ERROR_COUNTERS_MASK
;
888 EXPORT_SYMBOL(mlx4_set_stats_bitmap
);