drivers/net/ethernet/mellanox/mlx4/srq.c

   1 /*
   2  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/init.h>
  35
  36 #include <linux/mlx4/cmd.h>
  37 #include <linux/export.h>
  38 #include <linux/gfp.h>
  39
  40 #include "mlx4.h"
  41 #include "icm.h"
  42
  43 struct mlx4_srq_context {
  44         __be32                  state_logsize_srqn;
  45         u8                      logstride;
  46         u8                      reserved1;
  47         __be16                  xrcd;
  48         __be32                  pg_offset_cqn;
  49         u32                     reserved2;
  50         u8                      log_page_size;
  51         u8                      reserved3[2];
  52         u8                      mtt_base_addr_h;
  53         __be32                  mtt_base_addr_l;
  54         __be32                  pd;
  55         __be16                  limit_watermark;
  56         __be16                  wqe_cnt;
  57         u16                     reserved4;
  58         __be16                  wqe_counter;
  59         u32                     reserved5;
  60         __be64                  db_rec_addr;
  61 };
  62
  63 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type)
  64 {
  65         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  66         struct mlx4_srq *srq;
  67
  68         spin_lock(&srq_table->lock);
  69
  70         srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1));
  71         if (srq)
  72                 atomic_inc(&srq->refcount);
  73
  74         spin_unlock(&srq_table->lock);
  75
  76         if (!srq) {
  77                 mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  78                 return;
  79         }
  80
  81         srq->event(srq, event_type);
  82
  83         if (atomic_dec_and_test(&srq->refcount))
  84                 complete(&srq->free);
  85 }
  86
  87 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  88                           int srq_num)
  89 {
  90         return mlx4_cmd(dev, mailbox->dma | dev->caps.function, srq_num, 0,
  91                         MLX4_CMD_SW2HW_SRQ, MLX4_CMD_TIME_CLASS_A,
  92                         MLX4_CMD_WRAPPED);
  93 }
  94
  95 static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  96                           int srq_num)
  97 {
  98         return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
  99                             mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ,
 100                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 101 }
 102
 103 static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark)
 104 {
 105         return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
 106                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
 107 }
 108
 109 static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 110                           int srq_num)
 111 {
 112         return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ,
 113                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 114 }
 115
 116 static int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
 117 {
 118         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 119         int err;
 120
 121
 122         *srqn = mlx4_bitmap_alloc(&srq_table->bitmap);
 123         if (*srqn == -1)
 124                 return -ENOMEM;
 125
 126         err = mlx4_table_get(dev, &srq_table->table, *srqn);
 127         if (err)
 128                 goto err_out;
 129
 130         err = mlx4_table_get(dev, &srq_table->cmpt_table, *srqn);
 131         if (err)
 132                 goto err_put;
 133         return 0;
 134
 135 err_put:
 136         mlx4_table_put(dev, &srq_table->table, *srqn);
 137
 138 err_out:
 139         mlx4_bitmap_free(&srq_table->bitmap, *srqn);
 140         return err;
 141 }
 142
 143 static int mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
 144 {
 145         u64 out_param;
 146         int err;
 147
 148         if (mlx4_is_mfunc(dev)) {
 149                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_SRQ,
 150                                    RES_OP_RESERVE_AND_MAP,
 151                                    MLX4_CMD_ALLOC_RES,
 152                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 153                 if (!err)
 154                         *srqn = get_param_l(&out_param);
 155
 156                 return err;
 157         }
 158         return __mlx4_srq_alloc_icm(dev, srqn);
 159 }
 160
 161 static void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
 162 {
 163         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 164
 165         mlx4_table_put(dev, &srq_table->cmpt_table, srqn);
 166         mlx4_table_put(dev, &srq_table->table, srqn);
 167         mlx4_bitmap_free(&srq_table->bitmap, srqn);
 168 }
 169
 170 static void mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
 171 {
 172         u64 in_param;
 173
 174         if (mlx4_is_mfunc(dev)) {
 175                 set_param_l(&in_param, srqn);
 176                 if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
 177                              MLX4_CMD_FREE_RES,
 178                              MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
 179                         mlx4_warn(dev, "Failed freeing cq:%d\n", srqn);
 180                 return;
 181         }
 182         __mlx4_srq_free_icm(dev, srqn);
 183 }
 184
 185 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd,
 186                    struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq)
 187 {
 188         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 189         struct mlx4_cmd_mailbox *mailbox;
 190         struct mlx4_srq_context *srq_context;
 191         u64 mtt_addr;
 192         int err;
 193
 194         err = mlx4_srq_alloc_icm(dev, &srq->srqn);
 195         if (err)
 196                 return err;
 197
 198         spin_lock_irq(&srq_table->lock);
 199         err = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
 200         spin_unlock_irq(&srq_table->lock);
 201         if (err)
 202                 goto err_icm;
 203
 204         mailbox = mlx4_alloc_cmd_mailbox(dev);
 205         if (IS_ERR(mailbox)) {
 206                 err = PTR_ERR(mailbox);
 207                 goto err_radix;
 208         }
 209
 210         srq_context = mailbox->buf;
 211         memset(srq_context, 0, sizeof *srq_context);
 212
 213         srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) |
 214                                                       srq->srqn);
 215         srq_context->logstride          = srq->wqe_shift - 4;
 216         srq_context->xrcd               = cpu_to_be16(xrcd);
 217         srq_context->pg_offset_cqn      = cpu_to_be32(cqn & 0xffffff);
 218         srq_context->log_page_size      = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 219
 220         mtt_addr = mlx4_mtt_addr(dev, mtt);
 221         srq_context->mtt_base_addr_h    = mtt_addr >> 32;
 222         srq_context->mtt_base_addr_l    = cpu_to_be32(mtt_addr & 0xffffffff);
 223         srq_context->pd                 = cpu_to_be32(pdn);
 224         srq_context->db_rec_addr        = cpu_to_be64(db_rec);
 225
 226         err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn);
 227         mlx4_free_cmd_mailbox(dev, mailbox);
 228         if (err)
 229                 goto err_radix;
 230
 231         atomic_set(&srq->refcount, 1);
 232         init_completion(&srq->free);
 233
 234         return 0;
 235
 236 err_radix:
 237         spin_lock_irq(&srq_table->lock);
 238         radix_tree_delete(&srq_table->tree, srq->srqn);
 239         spin_unlock_irq(&srq_table->lock);
 240
 241 err_icm:
 242         mlx4_srq_free_icm(dev, srq->srqn);
 243         return err;
 244 }
 245 EXPORT_SYMBOL_GPL(mlx4_srq_alloc);
 246
 247 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq)
 248 {
 249         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 250         int err;
 251
 252         err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn);
 253         if (err)
 254                 mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn);
 255
 256         spin_lock_irq(&srq_table->lock);
 257         radix_tree_delete(&srq_table->tree, srq->srqn);
 258         spin_unlock_irq(&srq_table->lock);
 259
 260         if (atomic_dec_and_test(&srq->refcount))
 261                 complete(&srq->free);
 262         wait_for_completion(&srq->free);
 263
 264         mlx4_srq_free_icm(dev, srq->srqn);
 265 }
 266 EXPORT_SYMBOL_GPL(mlx4_srq_free);
 267
 268 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark)
 269 {
 270         return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark);
 271 }
 272 EXPORT_SYMBOL_GPL(mlx4_srq_arm);
 273
 274 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark)
 275 {
 276         struct mlx4_cmd_mailbox *mailbox;
 277         struct mlx4_srq_context *srq_context;
 278         int err;
 279
 280         mailbox = mlx4_alloc_cmd_mailbox(dev);
 281         if (IS_ERR(mailbox))
 282                 return PTR_ERR(mailbox);
 283
 284         srq_context = mailbox->buf;
 285
 286         err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn);
 287         if (err)
 288                 goto err_out;
 289         *limit_watermark = be16_to_cpu(srq_context->limit_watermark);
 290
 291 err_out:
 292         mlx4_free_cmd_mailbox(dev, mailbox);
 293         return err;
 294 }
 295 EXPORT_SYMBOL_GPL(mlx4_srq_query);
 296
 297 int mlx4_init_srq_table(struct mlx4_dev *dev)
 298 {
 299         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 300         int err;
 301
 302         spin_lock_init(&srq_table->lock);
 303         INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC);
 304         if (mlx4_is_slave(dev))
 305                 return 0;
 306
 307         err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs,
 308                                dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0);
 309         if (err)
 310                 return err;
 311
 312         return 0;
 313 }
 314
 315 void mlx4_cleanup_srq_table(struct mlx4_dev *dev)
 316 {
 317         if (mlx4_is_slave(dev))
 318                 return;
 319         mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap);
 320 }