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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
44
45 #include "mlx5_core.h"
46
47 enum {
48 CMD_IF_REV = 5,
49 };
50
51 enum {
52 CMD_MODE_POLLING,
53 CMD_MODE_EVENTS
54 };
55
56 enum {
57 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
58 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
59 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
60 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
61 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
62 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
63 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
64 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
65 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
66 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
67 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
68 };
69
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71 struct mlx5_cmd_msg *in,
72 struct mlx5_cmd_msg *out,
73 void *uout, int uout_size,
74 mlx5_cmd_cbk_t cbk,
75 void *context, int page_queue)
76 {
77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78 struct mlx5_cmd_work_ent *ent;
79
80 ent = kzalloc(sizeof(*ent), alloc_flags);
81 if (!ent)
82 return ERR_PTR(-ENOMEM);
83
84 ent->in = in;
85 ent->out = out;
86 ent->uout = uout;
87 ent->uout_size = uout_size;
88 ent->callback = cbk;
89 ent->context = context;
90 ent->cmd = cmd;
91 ent->page_queue = page_queue;
92
93 return ent;
94 }
95
96 static u8 alloc_token(struct mlx5_cmd *cmd)
97 {
98 u8 token;
99
100 spin_lock(&cmd->token_lock);
101 cmd->token++;
102 if (cmd->token == 0)
103 cmd->token++;
104 token = cmd->token;
105 spin_unlock(&cmd->token_lock);
106
107 return token;
108 }
109
110 static int alloc_ent(struct mlx5_cmd *cmd)
111 {
112 unsigned long flags;
113 int ret;
114
115 spin_lock_irqsave(&cmd->alloc_lock, flags);
116 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117 if (ret < cmd->max_reg_cmds)
118 clear_bit(ret, &cmd->bitmask);
119 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
120
121 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
122 }
123
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
125 {
126 unsigned long flags;
127
128 spin_lock_irqsave(&cmd->alloc_lock, flags);
129 set_bit(idx, &cmd->bitmask);
130 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
131 }
132
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
134 {
135 return cmd->cmd_buf + (idx << cmd->log_stride);
136 }
137
138 static u8 xor8_buf(void *buf, size_t offset, int len)
139 {
140 u8 *ptr = buf;
141 u8 sum = 0;
142 int i;
143 int end = len + offset;
144
145 for (i = offset; i < end; i++)
146 sum ^= ptr[i];
147
148 return sum;
149 }
150
151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
152 {
153 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
154 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
155
156 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
157 return -EINVAL;
158
159 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
160 return -EINVAL;
161
162 return 0;
163 }
164
165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
166 {
167 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
168 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
169
170 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
171 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
172 }
173
174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
175 {
176 struct mlx5_cmd_mailbox *next = msg->next;
177 int size = msg->len;
178 int blen = size - min_t(int, sizeof(msg->first.data), size);
179 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
180 / MLX5_CMD_DATA_BLOCK_SIZE;
181 int i = 0;
182
183 for (i = 0; i < n && next; i++) {
184 calc_block_sig(next->buf);
185 next = next->next;
186 }
187 }
188
189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
190 {
191 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
192 if (csum) {
193 calc_chain_sig(ent->in);
194 calc_chain_sig(ent->out);
195 }
196 }
197
198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
199 {
200 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
201 u8 own;
202
203 do {
204 own = ent->lay->status_own;
205 if (!(own & CMD_OWNER_HW)) {
206 ent->ret = 0;
207 return;
208 }
209 usleep_range(5000, 10000);
210 } while (time_before(jiffies, poll_end));
211
212 ent->ret = -ETIMEDOUT;
213 }
214
215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
216 {
217 kfree(ent);
218 }
219
220
221 static int verify_signature(struct mlx5_cmd_work_ent *ent)
222 {
223 struct mlx5_cmd_mailbox *next = ent->out->next;
224 int err;
225 u8 sig;
226 int size = ent->out->len;
227 int blen = size - min_t(int, sizeof(ent->out->first.data), size);
228 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
229 / MLX5_CMD_DATA_BLOCK_SIZE;
230 int i = 0;
231
232 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
233 if (sig != 0xff)
234 return -EINVAL;
235
236 for (i = 0; i < n && next; i++) {
237 err = verify_block_sig(next->buf);
238 if (err)
239 return err;
240
241 next = next->next;
242 }
243
244 return 0;
245 }
246
247 static void dump_buf(void *buf, int size, int data_only, int offset)
248 {
249 __be32 *p = buf;
250 int i;
251
252 for (i = 0; i < size; i += 16) {
253 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
254 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
255 be32_to_cpu(p[3]));
256 p += 4;
257 offset += 16;
258 }
259 if (!data_only)
260 pr_debug("\n");
261 }
262
263 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
264 u32 *synd, u8 *status)
265 {
266 *synd = 0;
267 *status = 0;
268
269 switch (op) {
270 case MLX5_CMD_OP_TEARDOWN_HCA:
271 case MLX5_CMD_OP_DISABLE_HCA:
272 case MLX5_CMD_OP_MANAGE_PAGES:
273 case MLX5_CMD_OP_DESTROY_MKEY:
274 case MLX5_CMD_OP_DESTROY_EQ:
275 case MLX5_CMD_OP_DESTROY_CQ:
276 case MLX5_CMD_OP_DESTROY_QP:
277 case MLX5_CMD_OP_DESTROY_PSV:
278 case MLX5_CMD_OP_DESTROY_SRQ:
279 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
280 case MLX5_CMD_OP_DESTROY_DCT:
281 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
282 case MLX5_CMD_OP_DEALLOC_PD:
283 case MLX5_CMD_OP_DEALLOC_UAR:
284 case MLX5_CMD_OP_DETACH_FROM_MCG:
285 case MLX5_CMD_OP_DEALLOC_XRCD:
286 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
287 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
288 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
289 case MLX5_CMD_OP_DESTROY_LAG:
290 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
291 case MLX5_CMD_OP_DESTROY_TIR:
292 case MLX5_CMD_OP_DESTROY_SQ:
293 case MLX5_CMD_OP_DESTROY_RQ:
294 case MLX5_CMD_OP_DESTROY_RMP:
295 case MLX5_CMD_OP_DESTROY_TIS:
296 case MLX5_CMD_OP_DESTROY_RQT:
297 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
298 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
299 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
300 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
301 case MLX5_CMD_OP_2ERR_QP:
302 case MLX5_CMD_OP_2RST_QP:
303 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
304 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
305 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
306 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
307 case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
308 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
309 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
310 return MLX5_CMD_STAT_OK;
311
312 case MLX5_CMD_OP_QUERY_HCA_CAP:
313 case MLX5_CMD_OP_QUERY_ADAPTER:
314 case MLX5_CMD_OP_INIT_HCA:
315 case MLX5_CMD_OP_ENABLE_HCA:
316 case MLX5_CMD_OP_QUERY_PAGES:
317 case MLX5_CMD_OP_SET_HCA_CAP:
318 case MLX5_CMD_OP_QUERY_ISSI:
319 case MLX5_CMD_OP_SET_ISSI:
320 case MLX5_CMD_OP_CREATE_MKEY:
321 case MLX5_CMD_OP_QUERY_MKEY:
322 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
323 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
324 case MLX5_CMD_OP_CREATE_EQ:
325 case MLX5_CMD_OP_QUERY_EQ:
326 case MLX5_CMD_OP_GEN_EQE:
327 case MLX5_CMD_OP_CREATE_CQ:
328 case MLX5_CMD_OP_QUERY_CQ:
329 case MLX5_CMD_OP_MODIFY_CQ:
330 case MLX5_CMD_OP_CREATE_QP:
331 case MLX5_CMD_OP_RST2INIT_QP:
332 case MLX5_CMD_OP_INIT2RTR_QP:
333 case MLX5_CMD_OP_RTR2RTS_QP:
334 case MLX5_CMD_OP_RTS2RTS_QP:
335 case MLX5_CMD_OP_SQERR2RTS_QP:
336 case MLX5_CMD_OP_QUERY_QP:
337 case MLX5_CMD_OP_SQD_RTS_QP:
338 case MLX5_CMD_OP_INIT2INIT_QP:
339 case MLX5_CMD_OP_CREATE_PSV:
340 case MLX5_CMD_OP_CREATE_SRQ:
341 case MLX5_CMD_OP_QUERY_SRQ:
342 case MLX5_CMD_OP_ARM_RQ:
343 case MLX5_CMD_OP_CREATE_XRC_SRQ:
344 case MLX5_CMD_OP_QUERY_XRC_SRQ:
345 case MLX5_CMD_OP_ARM_XRC_SRQ:
346 case MLX5_CMD_OP_CREATE_DCT:
347 case MLX5_CMD_OP_DRAIN_DCT:
348 case MLX5_CMD_OP_QUERY_DCT:
349 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
350 case MLX5_CMD_OP_QUERY_VPORT_STATE:
351 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
352 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
353 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
354 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
355 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
356 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
357 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
358 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
359 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
360 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
361 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
362 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
363 case MLX5_CMD_OP_QUERY_Q_COUNTER:
364 case MLX5_CMD_OP_ALLOC_PD:
365 case MLX5_CMD_OP_ALLOC_UAR:
366 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
367 case MLX5_CMD_OP_ACCESS_REG:
368 case MLX5_CMD_OP_ATTACH_TO_MCG:
369 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
370 case MLX5_CMD_OP_MAD_IFC:
371 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
372 case MLX5_CMD_OP_SET_MAD_DEMUX:
373 case MLX5_CMD_OP_NOP:
374 case MLX5_CMD_OP_ALLOC_XRCD:
375 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
376 case MLX5_CMD_OP_QUERY_CONG_STATUS:
377 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
378 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
379 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
380 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
381 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
382 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
383 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
384 case MLX5_CMD_OP_CREATE_LAG:
385 case MLX5_CMD_OP_MODIFY_LAG:
386 case MLX5_CMD_OP_QUERY_LAG:
387 case MLX5_CMD_OP_CREATE_VPORT_LAG:
388 case MLX5_CMD_OP_CREATE_TIR:
389 case MLX5_CMD_OP_MODIFY_TIR:
390 case MLX5_CMD_OP_QUERY_TIR:
391 case MLX5_CMD_OP_CREATE_SQ:
392 case MLX5_CMD_OP_MODIFY_SQ:
393 case MLX5_CMD_OP_QUERY_SQ:
394 case MLX5_CMD_OP_CREATE_RQ:
395 case MLX5_CMD_OP_MODIFY_RQ:
396 case MLX5_CMD_OP_QUERY_RQ:
397 case MLX5_CMD_OP_CREATE_RMP:
398 case MLX5_CMD_OP_MODIFY_RMP:
399 case MLX5_CMD_OP_QUERY_RMP:
400 case MLX5_CMD_OP_CREATE_TIS:
401 case MLX5_CMD_OP_MODIFY_TIS:
402 case MLX5_CMD_OP_QUERY_TIS:
403 case MLX5_CMD_OP_CREATE_RQT:
404 case MLX5_CMD_OP_MODIFY_RQT:
405 case MLX5_CMD_OP_QUERY_RQT:
406
407 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
408 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
409 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
410 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
411 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
412 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
413 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
414 case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
415 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
416 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
417 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
418 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
419 *status = MLX5_DRIVER_STATUS_ABORTED;
420 *synd = MLX5_DRIVER_SYND;
421 return -EIO;
422 default:
423 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
424 return -EINVAL;
425 }
426 }
427
428 const char *mlx5_command_str(int command)
429 {
430 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
431
432 switch (command) {
433 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
434 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
435 MLX5_COMMAND_STR_CASE(INIT_HCA);
436 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
437 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
438 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
439 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
440 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
441 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
442 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
443 MLX5_COMMAND_STR_CASE(SET_ISSI);
444 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
445 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
446 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
447 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
448 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
449 MLX5_COMMAND_STR_CASE(CREATE_EQ);
450 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
451 MLX5_COMMAND_STR_CASE(QUERY_EQ);
452 MLX5_COMMAND_STR_CASE(GEN_EQE);
453 MLX5_COMMAND_STR_CASE(CREATE_CQ);
454 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
455 MLX5_COMMAND_STR_CASE(QUERY_CQ);
456 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
457 MLX5_COMMAND_STR_CASE(CREATE_QP);
458 MLX5_COMMAND_STR_CASE(DESTROY_QP);
459 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
460 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
461 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
462 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
463 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
464 MLX5_COMMAND_STR_CASE(2ERR_QP);
465 MLX5_COMMAND_STR_CASE(2RST_QP);
466 MLX5_COMMAND_STR_CASE(QUERY_QP);
467 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
468 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
469 MLX5_COMMAND_STR_CASE(CREATE_PSV);
470 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
471 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
472 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
473 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
474 MLX5_COMMAND_STR_CASE(ARM_RQ);
475 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
476 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
477 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
478 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
479 MLX5_COMMAND_STR_CASE(CREATE_DCT);
480 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
481 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
482 MLX5_COMMAND_STR_CASE(QUERY_DCT);
483 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
484 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
485 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
486 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
487 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
488 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
489 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
490 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
491 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
492 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
493 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
494 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
495 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
496 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
497 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
498 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
499 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
500 MLX5_COMMAND_STR_CASE(ALLOC_PD);
501 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
502 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
503 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
504 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
505 MLX5_COMMAND_STR_CASE(ACCESS_REG);
506 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
507 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
508 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
509 MLX5_COMMAND_STR_CASE(MAD_IFC);
510 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
511 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
512 MLX5_COMMAND_STR_CASE(NOP);
513 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
514 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
515 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
516 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
517 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
518 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
519 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
520 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
521 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
522 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
523 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
524 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
525 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
526 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
527 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
528 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
529 MLX5_COMMAND_STR_CASE(CREATE_LAG);
530 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
531 MLX5_COMMAND_STR_CASE(QUERY_LAG);
532 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
533 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
534 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
535 MLX5_COMMAND_STR_CASE(CREATE_TIR);
536 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
537 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
538 MLX5_COMMAND_STR_CASE(QUERY_TIR);
539 MLX5_COMMAND_STR_CASE(CREATE_SQ);
540 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
541 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
542 MLX5_COMMAND_STR_CASE(QUERY_SQ);
543 MLX5_COMMAND_STR_CASE(CREATE_RQ);
544 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
545 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
546 MLX5_COMMAND_STR_CASE(QUERY_RQ);
547 MLX5_COMMAND_STR_CASE(CREATE_RMP);
548 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
549 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
550 MLX5_COMMAND_STR_CASE(QUERY_RMP);
551 MLX5_COMMAND_STR_CASE(CREATE_TIS);
552 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
553 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
554 MLX5_COMMAND_STR_CASE(QUERY_TIS);
555 MLX5_COMMAND_STR_CASE(CREATE_RQT);
556 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
557 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
558 MLX5_COMMAND_STR_CASE(QUERY_RQT);
559 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
560 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
561 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
562 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
563 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
564 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
565 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
566 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
567 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
568 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
569 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
570 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
571 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
572 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
573 MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
574 MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
575 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
576 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
577 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
578 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
579 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
580 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
581 default: return "unknown command opcode";
582 }
583 }
584
585 static const char *cmd_status_str(u8 status)
586 {
587 switch (status) {
588 case MLX5_CMD_STAT_OK:
589 return "OK";
590 case MLX5_CMD_STAT_INT_ERR:
591 return "internal error";
592 case MLX5_CMD_STAT_BAD_OP_ERR:
593 return "bad operation";
594 case MLX5_CMD_STAT_BAD_PARAM_ERR:
595 return "bad parameter";
596 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
597 return "bad system state";
598 case MLX5_CMD_STAT_BAD_RES_ERR:
599 return "bad resource";
600 case MLX5_CMD_STAT_RES_BUSY:
601 return "resource busy";
602 case MLX5_CMD_STAT_LIM_ERR:
603 return "limits exceeded";
604 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
605 return "bad resource state";
606 case MLX5_CMD_STAT_IX_ERR:
607 return "bad index";
608 case MLX5_CMD_STAT_NO_RES_ERR:
609 return "no resources";
610 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
611 return "bad input length";
612 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
613 return "bad output length";
614 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
615 return "bad QP state";
616 case MLX5_CMD_STAT_BAD_PKT_ERR:
617 return "bad packet (discarded)";
618 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
619 return "bad size too many outstanding CQEs";
620 default:
621 return "unknown status";
622 }
623 }
624
625 static int cmd_status_to_err(u8 status)
626 {
627 switch (status) {
628 case MLX5_CMD_STAT_OK: return 0;
629 case MLX5_CMD_STAT_INT_ERR: return -EIO;
630 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
631 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
632 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
633 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
634 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
635 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
636 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
637 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
638 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
639 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
640 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
641 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
642 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
643 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
644 default: return -EIO;
645 }
646 }
647
648 struct mlx5_ifc_mbox_out_bits {
649 u8 status[0x8];
650 u8 reserved_at_8[0x18];
651
652 u8 syndrome[0x20];
653
654 u8 reserved_at_40[0x40];
655 };
656
657 struct mlx5_ifc_mbox_in_bits {
658 u8 opcode[0x10];
659 u8 reserved_at_10[0x10];
660
661 u8 reserved_at_20[0x10];
662 u8 op_mod[0x10];
663
664 u8 reserved_at_40[0x40];
665 };
666
667 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
668 {
669 *status = MLX5_GET(mbox_out, out, status);
670 *syndrome = MLX5_GET(mbox_out, out, syndrome);
671 }
672
673 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
674 {
675 u32 syndrome;
676 u8 status;
677 u16 opcode;
678 u16 op_mod;
679
680 mlx5_cmd_mbox_status(out, &status, &syndrome);
681 if (!status)
682 return 0;
683
684 opcode = MLX5_GET(mbox_in, in, opcode);
685 op_mod = MLX5_GET(mbox_in, in, op_mod);
686
687 mlx5_core_err(dev,
688 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
689 mlx5_command_str(opcode),
690 opcode, op_mod,
691 cmd_status_str(status),
692 status,
693 syndrome);
694
695 return cmd_status_to_err(status);
696 }
697
698 static void dump_command(struct mlx5_core_dev *dev,
699 struct mlx5_cmd_work_ent *ent, int input)
700 {
701 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
702 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
703 struct mlx5_cmd_mailbox *next = msg->next;
704 int data_only;
705 u32 offset = 0;
706 int dump_len;
707
708 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
709
710 if (data_only)
711 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
712 "dump command data %s(0x%x) %s\n",
713 mlx5_command_str(op), op,
714 input ? "INPUT" : "OUTPUT");
715 else
716 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
717 mlx5_command_str(op), op,
718 input ? "INPUT" : "OUTPUT");
719
720 if (data_only) {
721 if (input) {
722 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
723 offset += sizeof(ent->lay->in);
724 } else {
725 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
726 offset += sizeof(ent->lay->out);
727 }
728 } else {
729 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
730 offset += sizeof(*ent->lay);
731 }
732
733 while (next && offset < msg->len) {
734 if (data_only) {
735 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
736 dump_buf(next->buf, dump_len, 1, offset);
737 offset += MLX5_CMD_DATA_BLOCK_SIZE;
738 } else {
739 mlx5_core_dbg(dev, "command block:\n");
740 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
741 offset += sizeof(struct mlx5_cmd_prot_block);
742 }
743 next = next->next;
744 }
745
746 if (data_only)
747 pr_debug("\n");
748 }
749
750 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
751 {
752 return MLX5_GET(mbox_in, in->first.data, opcode);
753 }
754
755 static void cb_timeout_handler(struct work_struct *work)
756 {
757 struct delayed_work *dwork = container_of(work, struct delayed_work,
758 work);
759 struct mlx5_cmd_work_ent *ent = container_of(dwork,
760 struct mlx5_cmd_work_ent,
761 cb_timeout_work);
762 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
763 cmd);
764
765 ent->ret = -ETIMEDOUT;
766 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
767 mlx5_command_str(msg_to_opcode(ent->in)),
768 msg_to_opcode(ent->in));
769 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
770 }
771
772 static void cmd_work_handler(struct work_struct *work)
773 {
774 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
775 struct mlx5_cmd *cmd = ent->cmd;
776 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
777 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
778 struct mlx5_cmd_layout *lay;
779 struct semaphore *sem;
780 unsigned long flags;
781
782 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
783 down(sem);
784 if (!ent->page_queue) {
785 ent->idx = alloc_ent(cmd);
786 if (ent->idx < 0) {
787 mlx5_core_err(dev, "failed to allocate command entry\n");
788 up(sem);
789 return;
790 }
791 } else {
792 ent->idx = cmd->max_reg_cmds;
793 spin_lock_irqsave(&cmd->alloc_lock, flags);
794 clear_bit(ent->idx, &cmd->bitmask);
795 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
796 }
797
798 cmd->ent_arr[ent->idx] = ent;
799 lay = get_inst(cmd, ent->idx);
800 ent->lay = lay;
801 memset(lay, 0, sizeof(*lay));
802 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
803 ent->op = be32_to_cpu(lay->in[0]) >> 16;
804 if (ent->in->next)
805 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
806 lay->inlen = cpu_to_be32(ent->in->len);
807 if (ent->out->next)
808 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
809 lay->outlen = cpu_to_be32(ent->out->len);
810 lay->type = MLX5_PCI_CMD_XPORT;
811 lay->token = ent->token;
812 lay->status_own = CMD_OWNER_HW;
813 set_signature(ent, !cmd->checksum_disabled);
814 dump_command(dev, ent, 1);
815 ent->ts1 = ktime_get_ns();
816
817 if (ent->callback)
818 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
819
820 /* ring doorbell after the descriptor is valid */
821 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
822 wmb();
823 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
824 mmiowb();
825 /* if not in polling don't use ent after this point */
826 if (cmd->mode == CMD_MODE_POLLING) {
827 poll_timeout(ent);
828 /* make sure we read the descriptor after ownership is SW */
829 rmb();
830 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
831 }
832 }
833
834 static const char *deliv_status_to_str(u8 status)
835 {
836 switch (status) {
837 case MLX5_CMD_DELIVERY_STAT_OK:
838 return "no errors";
839 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
840 return "signature error";
841 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
842 return "token error";
843 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
844 return "bad block number";
845 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
846 return "output pointer not aligned to block size";
847 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
848 return "input pointer not aligned to block size";
849 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
850 return "firmware internal error";
851 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
852 return "command input length error";
853 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
854 return "command ouput length error";
855 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
856 return "reserved fields not cleared";
857 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
858 return "bad command descriptor type";
859 default:
860 return "unknown status code";
861 }
862 }
863
864 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
865 {
866 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
867 struct mlx5_cmd *cmd = &dev->cmd;
868 int err;
869
870 if (cmd->mode == CMD_MODE_POLLING) {
871 wait_for_completion(&ent->done);
872 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
873 ent->ret = -ETIMEDOUT;
874 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
875 }
876
877 err = ent->ret;
878
879 if (err == -ETIMEDOUT) {
880 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
881 mlx5_command_str(msg_to_opcode(ent->in)),
882 msg_to_opcode(ent->in));
883 }
884 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
885 err, deliv_status_to_str(ent->status), ent->status);
886
887 return err;
888 }
889
890 /* Notes:
891 * 1. Callback functions may not sleep
892 * 2. page queue commands do not support asynchrous completion
893 */
894 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
895 struct mlx5_cmd_msg *out, void *uout, int uout_size,
896 mlx5_cmd_cbk_t callback,
897 void *context, int page_queue, u8 *status,
898 u8 token)
899 {
900 struct mlx5_cmd *cmd = &dev->cmd;
901 struct mlx5_cmd_work_ent *ent;
902 struct mlx5_cmd_stats *stats;
903 int err = 0;
904 s64 ds;
905 u16 op;
906
907 if (callback && page_queue)
908 return -EINVAL;
909
910 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
911 page_queue);
912 if (IS_ERR(ent))
913 return PTR_ERR(ent);
914
915 ent->token = token;
916
917 if (!callback)
918 init_completion(&ent->done);
919
920 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
921 INIT_WORK(&ent->work, cmd_work_handler);
922 if (page_queue) {
923 cmd_work_handler(&ent->work);
924 } else if (!queue_work(cmd->wq, &ent->work)) {
925 mlx5_core_warn(dev, "failed to queue work\n");
926 err = -ENOMEM;
927 goto out_free;
928 }
929
930 if (callback)
931 goto out;
932
933 err = wait_func(dev, ent);
934 if (err == -ETIMEDOUT)
935 goto out_free;
936
937 ds = ent->ts2 - ent->ts1;
938 op = MLX5_GET(mbox_in, in->first.data, opcode);
939 if (op < ARRAY_SIZE(cmd->stats)) {
940 stats = &cmd->stats[op];
941 spin_lock_irq(&stats->lock);
942 stats->sum += ds;
943 ++stats->n;
944 spin_unlock_irq(&stats->lock);
945 }
946 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
947 "fw exec time for %s is %lld nsec\n",
948 mlx5_command_str(op), ds);
949 *status = ent->status;
950
951 out_free:
952 free_cmd(ent);
953 out:
954 return err;
955 }
956
957 static ssize_t dbg_write(struct file *filp, const char __user *buf,
958 size_t count, loff_t *pos)
959 {
960 struct mlx5_core_dev *dev = filp->private_data;
961 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
962 char lbuf[3];
963 int err;
964
965 if (!dbg->in_msg || !dbg->out_msg)
966 return -ENOMEM;
967
968 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
969 return -EFAULT;
970
971 lbuf[sizeof(lbuf) - 1] = 0;
972
973 if (strcmp(lbuf, "go"))
974 return -EINVAL;
975
976 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
977
978 return err ? err : count;
979 }
980
981
982 static const struct file_operations fops = {
983 .owner = THIS_MODULE,
984 .open = simple_open,
985 .write = dbg_write,
986 };
987
988 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
989 u8 token)
990 {
991 struct mlx5_cmd_prot_block *block;
992 struct mlx5_cmd_mailbox *next;
993 int copy;
994
995 if (!to || !from)
996 return -ENOMEM;
997
998 copy = min_t(int, size, sizeof(to->first.data));
999 memcpy(to->first.data, from, copy);
1000 size -= copy;
1001 from += copy;
1002
1003 next = to->next;
1004 while (size) {
1005 if (!next) {
1006 /* this is a BUG */
1007 return -ENOMEM;
1008 }
1009
1010 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1011 block = next->buf;
1012 memcpy(block->data, from, copy);
1013 from += copy;
1014 size -= copy;
1015 block->token = token;
1016 next = next->next;
1017 }
1018
1019 return 0;
1020 }
1021
1022 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1023 {
1024 struct mlx5_cmd_prot_block *block;
1025 struct mlx5_cmd_mailbox *next;
1026 int copy;
1027
1028 if (!to || !from)
1029 return -ENOMEM;
1030
1031 copy = min_t(int, size, sizeof(from->first.data));
1032 memcpy(to, from->first.data, copy);
1033 size -= copy;
1034 to += copy;
1035
1036 next = from->next;
1037 while (size) {
1038 if (!next) {
1039 /* this is a BUG */
1040 return -ENOMEM;
1041 }
1042
1043 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1044 block = next->buf;
1045
1046 memcpy(to, block->data, copy);
1047 to += copy;
1048 size -= copy;
1049 next = next->next;
1050 }
1051
1052 return 0;
1053 }
1054
1055 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1056 gfp_t flags)
1057 {
1058 struct mlx5_cmd_mailbox *mailbox;
1059
1060 mailbox = kmalloc(sizeof(*mailbox), flags);
1061 if (!mailbox)
1062 return ERR_PTR(-ENOMEM);
1063
1064 mailbox->buf = pci_pool_zalloc(dev->cmd.pool, flags,
1065 &mailbox->dma);
1066 if (!mailbox->buf) {
1067 mlx5_core_dbg(dev, "failed allocation\n");
1068 kfree(mailbox);
1069 return ERR_PTR(-ENOMEM);
1070 }
1071 mailbox->next = NULL;
1072
1073 return mailbox;
1074 }
1075
1076 static void free_cmd_box(struct mlx5_core_dev *dev,
1077 struct mlx5_cmd_mailbox *mailbox)
1078 {
1079 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1080 kfree(mailbox);
1081 }
1082
1083 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1084 gfp_t flags, int size,
1085 u8 token)
1086 {
1087 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1088 struct mlx5_cmd_prot_block *block;
1089 struct mlx5_cmd_msg *msg;
1090 int blen;
1091 int err;
1092 int n;
1093 int i;
1094
1095 msg = kzalloc(sizeof(*msg), flags);
1096 if (!msg)
1097 return ERR_PTR(-ENOMEM);
1098
1099 blen = size - min_t(int, sizeof(msg->first.data), size);
1100 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1101
1102 for (i = 0; i < n; i++) {
1103 tmp = alloc_cmd_box(dev, flags);
1104 if (IS_ERR(tmp)) {
1105 mlx5_core_warn(dev, "failed allocating block\n");
1106 err = PTR_ERR(tmp);
1107 goto err_alloc;
1108 }
1109
1110 block = tmp->buf;
1111 tmp->next = head;
1112 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1113 block->block_num = cpu_to_be32(n - i - 1);
1114 block->token = token;
1115 head = tmp;
1116 }
1117 msg->next = head;
1118 msg->len = size;
1119 return msg;
1120
1121 err_alloc:
1122 while (head) {
1123 tmp = head->next;
1124 free_cmd_box(dev, head);
1125 head = tmp;
1126 }
1127 kfree(msg);
1128
1129 return ERR_PTR(err);
1130 }
1131
1132 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1133 struct mlx5_cmd_msg *msg)
1134 {
1135 struct mlx5_cmd_mailbox *head = msg->next;
1136 struct mlx5_cmd_mailbox *next;
1137
1138 while (head) {
1139 next = head->next;
1140 free_cmd_box(dev, head);
1141 head = next;
1142 }
1143 kfree(msg);
1144 }
1145
1146 static ssize_t data_write(struct file *filp, const char __user *buf,
1147 size_t count, loff_t *pos)
1148 {
1149 struct mlx5_core_dev *dev = filp->private_data;
1150 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1151 void *ptr;
1152
1153 if (*pos != 0)
1154 return -EINVAL;
1155
1156 kfree(dbg->in_msg);
1157 dbg->in_msg = NULL;
1158 dbg->inlen = 0;
1159 ptr = memdup_user(buf, count);
1160 if (IS_ERR(ptr))
1161 return PTR_ERR(ptr);
1162 dbg->in_msg = ptr;
1163 dbg->inlen = count;
1164
1165 *pos = count;
1166
1167 return count;
1168 }
1169
1170 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1171 loff_t *pos)
1172 {
1173 struct mlx5_core_dev *dev = filp->private_data;
1174 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1175 int copy;
1176
1177 if (*pos)
1178 return 0;
1179
1180 if (!dbg->out_msg)
1181 return -ENOMEM;
1182
1183 copy = min_t(int, count, dbg->outlen);
1184 if (copy_to_user(buf, dbg->out_msg, copy))
1185 return -EFAULT;
1186
1187 *pos += copy;
1188
1189 return copy;
1190 }
1191
1192 static const struct file_operations dfops = {
1193 .owner = THIS_MODULE,
1194 .open = simple_open,
1195 .write = data_write,
1196 .read = data_read,
1197 };
1198
1199 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1200 loff_t *pos)
1201 {
1202 struct mlx5_core_dev *dev = filp->private_data;
1203 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1204 char outlen[8];
1205 int err;
1206
1207 if (*pos)
1208 return 0;
1209
1210 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1211 if (err < 0)
1212 return err;
1213
1214 if (copy_to_user(buf, &outlen, err))
1215 return -EFAULT;
1216
1217 *pos += err;
1218
1219 return err;
1220 }
1221
1222 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1223 size_t count, loff_t *pos)
1224 {
1225 struct mlx5_core_dev *dev = filp->private_data;
1226 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1227 char outlen_str[8];
1228 int outlen;
1229 void *ptr;
1230 int err;
1231
1232 if (*pos != 0 || count > 6)
1233 return -EINVAL;
1234
1235 kfree(dbg->out_msg);
1236 dbg->out_msg = NULL;
1237 dbg->outlen = 0;
1238
1239 if (copy_from_user(outlen_str, buf, count))
1240 return -EFAULT;
1241
1242 outlen_str[7] = 0;
1243
1244 err = sscanf(outlen_str, "%d", &outlen);
1245 if (err < 0)
1246 return err;
1247
1248 ptr = kzalloc(outlen, GFP_KERNEL);
1249 if (!ptr)
1250 return -ENOMEM;
1251
1252 dbg->out_msg = ptr;
1253 dbg->outlen = outlen;
1254
1255 *pos = count;
1256
1257 return count;
1258 }
1259
1260 static const struct file_operations olfops = {
1261 .owner = THIS_MODULE,
1262 .open = simple_open,
1263 .write = outlen_write,
1264 .read = outlen_read,
1265 };
1266
1267 static void set_wqname(struct mlx5_core_dev *dev)
1268 {
1269 struct mlx5_cmd *cmd = &dev->cmd;
1270
1271 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1272 dev_name(&dev->pdev->dev));
1273 }
1274
1275 static void clean_debug_files(struct mlx5_core_dev *dev)
1276 {
1277 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1278
1279 if (!mlx5_debugfs_root)
1280 return;
1281
1282 mlx5_cmdif_debugfs_cleanup(dev);
1283 debugfs_remove_recursive(dbg->dbg_root);
1284 }
1285
1286 static int create_debugfs_files(struct mlx5_core_dev *dev)
1287 {
1288 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1289 int err = -ENOMEM;
1290
1291 if (!mlx5_debugfs_root)
1292 return 0;
1293
1294 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1295 if (!dbg->dbg_root)
1296 return err;
1297
1298 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1299 dev, &dfops);
1300 if (!dbg->dbg_in)
1301 goto err_dbg;
1302
1303 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1304 dev, &dfops);
1305 if (!dbg->dbg_out)
1306 goto err_dbg;
1307
1308 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1309 dev, &olfops);
1310 if (!dbg->dbg_outlen)
1311 goto err_dbg;
1312
1313 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1314 &dbg->status);
1315 if (!dbg->dbg_status)
1316 goto err_dbg;
1317
1318 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1319 if (!dbg->dbg_run)
1320 goto err_dbg;
1321
1322 mlx5_cmdif_debugfs_init(dev);
1323
1324 return 0;
1325
1326 err_dbg:
1327 clean_debug_files(dev);
1328 return err;
1329 }
1330
1331 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1332 {
1333 struct mlx5_cmd *cmd = &dev->cmd;
1334 int i;
1335
1336 for (i = 0; i < cmd->max_reg_cmds; i++)
1337 down(&cmd->sem);
1338 down(&cmd->pages_sem);
1339
1340 cmd->mode = mode;
1341
1342 up(&cmd->pages_sem);
1343 for (i = 0; i < cmd->max_reg_cmds; i++)
1344 up(&cmd->sem);
1345 }
1346
1347 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1348 {
1349 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1350 }
1351
1352 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1353 {
1354 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1355 }
1356
1357 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1358 {
1359 unsigned long flags;
1360
1361 if (msg->parent) {
1362 spin_lock_irqsave(&msg->parent->lock, flags);
1363 list_add_tail(&msg->list, &msg->parent->head);
1364 spin_unlock_irqrestore(&msg->parent->lock, flags);
1365 } else {
1366 mlx5_free_cmd_msg(dev, msg);
1367 }
1368 }
1369
1370 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1371 {
1372 struct mlx5_cmd *cmd = &dev->cmd;
1373 struct mlx5_cmd_work_ent *ent;
1374 mlx5_cmd_cbk_t callback;
1375 void *context;
1376 int err;
1377 int i;
1378 s64 ds;
1379 struct mlx5_cmd_stats *stats;
1380 unsigned long flags;
1381 unsigned long vector;
1382
1383 /* there can be at most 32 command queues */
1384 vector = vec & 0xffffffff;
1385 for (i = 0; i < (1 << cmd->log_sz); i++) {
1386 if (test_bit(i, &vector)) {
1387 struct semaphore *sem;
1388
1389 ent = cmd->ent_arr[i];
1390 if (ent->callback)
1391 cancel_delayed_work(&ent->cb_timeout_work);
1392 if (ent->page_queue)
1393 sem = &cmd->pages_sem;
1394 else
1395 sem = &cmd->sem;
1396 ent->ts2 = ktime_get_ns();
1397 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1398 dump_command(dev, ent, 0);
1399 if (!ent->ret) {
1400 if (!cmd->checksum_disabled)
1401 ent->ret = verify_signature(ent);
1402 else
1403 ent->ret = 0;
1404 if (vec & MLX5_TRIGGERED_CMD_COMP)
1405 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1406 else
1407 ent->status = ent->lay->status_own >> 1;
1408
1409 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1410 ent->ret, deliv_status_to_str(ent->status), ent->status);
1411 }
1412 free_ent(cmd, ent->idx);
1413
1414 if (ent->callback) {
1415 ds = ent->ts2 - ent->ts1;
1416 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1417 stats = &cmd->stats[ent->op];
1418 spin_lock_irqsave(&stats->lock, flags);
1419 stats->sum += ds;
1420 ++stats->n;
1421 spin_unlock_irqrestore(&stats->lock, flags);
1422 }
1423
1424 callback = ent->callback;
1425 context = ent->context;
1426 err = ent->ret;
1427 if (!err) {
1428 err = mlx5_copy_from_msg(ent->uout,
1429 ent->out,
1430 ent->uout_size);
1431
1432 err = err ? err : mlx5_cmd_check(dev,
1433 ent->in->first.data,
1434 ent->uout);
1435 }
1436
1437 mlx5_free_cmd_msg(dev, ent->out);
1438 free_msg(dev, ent->in);
1439
1440 err = err ? err : ent->status;
1441 free_cmd(ent);
1442 callback(err, context);
1443 } else {
1444 complete(&ent->done);
1445 }
1446 up(sem);
1447 }
1448 }
1449 }
1450 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1451
1452 static int status_to_err(u8 status)
1453 {
1454 return status ? -1 : 0; /* TBD more meaningful codes */
1455 }
1456
1457 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1458 gfp_t gfp)
1459 {
1460 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1461 struct cmd_msg_cache *ch = NULL;
1462 struct mlx5_cmd *cmd = &dev->cmd;
1463 int i;
1464
1465 if (in_size <= 16)
1466 goto cache_miss;
1467
1468 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1469 ch = &cmd->cache[i];
1470 if (in_size > ch->max_inbox_size)
1471 continue;
1472 spin_lock_irq(&ch->lock);
1473 if (list_empty(&ch->head)) {
1474 spin_unlock_irq(&ch->lock);
1475 continue;
1476 }
1477 msg = list_entry(ch->head.next, typeof(*msg), list);
1478 /* For cached lists, we must explicitly state what is
1479 * the real size
1480 */
1481 msg->len = in_size;
1482 list_del(&msg->list);
1483 spin_unlock_irq(&ch->lock);
1484 break;
1485 }
1486
1487 if (!IS_ERR(msg))
1488 return msg;
1489
1490 cache_miss:
1491 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1492 return msg;
1493 }
1494
1495 static int is_manage_pages(void *in)
1496 {
1497 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1498 }
1499
1500 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1501 int out_size, mlx5_cmd_cbk_t callback, void *context)
1502 {
1503 struct mlx5_cmd_msg *inb;
1504 struct mlx5_cmd_msg *outb;
1505 int pages_queue;
1506 gfp_t gfp;
1507 int err;
1508 u8 status = 0;
1509 u32 drv_synd;
1510 u8 token;
1511
1512 if (pci_channel_offline(dev->pdev) ||
1513 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1514 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1515
1516 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1517 MLX5_SET(mbox_out, out, status, status);
1518 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1519 return err;
1520 }
1521
1522 pages_queue = is_manage_pages(in);
1523 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1524
1525 inb = alloc_msg(dev, in_size, gfp);
1526 if (IS_ERR(inb)) {
1527 err = PTR_ERR(inb);
1528 return err;
1529 }
1530
1531 token = alloc_token(&dev->cmd);
1532
1533 err = mlx5_copy_to_msg(inb, in, in_size, token);
1534 if (err) {
1535 mlx5_core_warn(dev, "err %d\n", err);
1536 goto out_in;
1537 }
1538
1539 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1540 if (IS_ERR(outb)) {
1541 err = PTR_ERR(outb);
1542 goto out_in;
1543 }
1544
1545 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1546 pages_queue, &status, token);
1547 if (err)
1548 goto out_out;
1549
1550 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1551 if (status) {
1552 err = status_to_err(status);
1553 goto out_out;
1554 }
1555
1556 if (!callback)
1557 err = mlx5_copy_from_msg(out, outb, out_size);
1558
1559 out_out:
1560 if (!callback)
1561 mlx5_free_cmd_msg(dev, outb);
1562
1563 out_in:
1564 if (!callback)
1565 free_msg(dev, inb);
1566 return err;
1567 }
1568
1569 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1570 int out_size)
1571 {
1572 int err;
1573
1574 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1575 return err ? : mlx5_cmd_check(dev, in, out);
1576 }
1577 EXPORT_SYMBOL(mlx5_cmd_exec);
1578
1579 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1580 void *out, int out_size, mlx5_cmd_cbk_t callback,
1581 void *context)
1582 {
1583 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1584 }
1585 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1586
1587 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1588 {
1589 struct cmd_msg_cache *ch;
1590 struct mlx5_cmd_msg *msg;
1591 struct mlx5_cmd_msg *n;
1592 int i;
1593
1594 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1595 ch = &dev->cmd.cache[i];
1596 list_for_each_entry_safe(msg, n, &ch->head, list) {
1597 list_del(&msg->list);
1598 mlx5_free_cmd_msg(dev, msg);
1599 }
1600 }
1601 }
1602
1603 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1604 512, 32, 16, 8, 2
1605 };
1606
1607 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1608 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1609 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1610 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1611 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1612 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1613 };
1614
1615 static void create_msg_cache(struct mlx5_core_dev *dev)
1616 {
1617 struct mlx5_cmd *cmd = &dev->cmd;
1618 struct cmd_msg_cache *ch;
1619 struct mlx5_cmd_msg *msg;
1620 int i;
1621 int k;
1622
1623 /* Initialize and fill the caches with initial entries */
1624 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1625 ch = &cmd->cache[k];
1626 spin_lock_init(&ch->lock);
1627 INIT_LIST_HEAD(&ch->head);
1628 ch->num_ent = cmd_cache_num_ent[k];
1629 ch->max_inbox_size = cmd_cache_ent_size[k];
1630 for (i = 0; i < ch->num_ent; i++) {
1631 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1632 ch->max_inbox_size, 0);
1633 if (IS_ERR(msg))
1634 break;
1635 msg->parent = ch;
1636 list_add_tail(&msg->list, &ch->head);
1637 }
1638 }
1639 }
1640
1641 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1642 {
1643 struct device *ddev = &dev->pdev->dev;
1644
1645 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1646 &cmd->alloc_dma, GFP_KERNEL);
1647 if (!cmd->cmd_alloc_buf)
1648 return -ENOMEM;
1649
1650 /* make sure it is aligned to 4K */
1651 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1652 cmd->cmd_buf = cmd->cmd_alloc_buf;
1653 cmd->dma = cmd->alloc_dma;
1654 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1655 return 0;
1656 }
1657
1658 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1659 cmd->alloc_dma);
1660 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1661 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1662 &cmd->alloc_dma, GFP_KERNEL);
1663 if (!cmd->cmd_alloc_buf)
1664 return -ENOMEM;
1665
1666 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1667 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1668 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1669 return 0;
1670 }
1671
1672 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1673 {
1674 struct device *ddev = &dev->pdev->dev;
1675
1676 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1677 cmd->alloc_dma);
1678 }
1679
1680 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1681 {
1682 int size = sizeof(struct mlx5_cmd_prot_block);
1683 int align = roundup_pow_of_two(size);
1684 struct mlx5_cmd *cmd = &dev->cmd;
1685 u32 cmd_h, cmd_l;
1686 u16 cmd_if_rev;
1687 int err;
1688 int i;
1689
1690 memset(cmd, 0, sizeof(*cmd));
1691 cmd_if_rev = cmdif_rev(dev);
1692 if (cmd_if_rev != CMD_IF_REV) {
1693 dev_err(&dev->pdev->dev,
1694 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1695 CMD_IF_REV, cmd_if_rev);
1696 return -EINVAL;
1697 }
1698
1699 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1700 if (!cmd->pool)
1701 return -ENOMEM;
1702
1703 err = alloc_cmd_page(dev, cmd);
1704 if (err)
1705 goto err_free_pool;
1706
1707 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1708 cmd->log_sz = cmd_l >> 4 & 0xf;
1709 cmd->log_stride = cmd_l & 0xf;
1710 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1711 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1712 1 << cmd->log_sz);
1713 err = -EINVAL;
1714 goto err_free_page;
1715 }
1716
1717 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1718 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1719 err = -EINVAL;
1720 goto err_free_page;
1721 }
1722
1723 cmd->checksum_disabled = 1;
1724 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1725 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1726
1727 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1728 if (cmd->cmdif_rev > CMD_IF_REV) {
1729 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1730 CMD_IF_REV, cmd->cmdif_rev);
1731 err = -EOPNOTSUPP;
1732 goto err_free_page;
1733 }
1734
1735 spin_lock_init(&cmd->alloc_lock);
1736 spin_lock_init(&cmd->token_lock);
1737 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1738 spin_lock_init(&cmd->stats[i].lock);
1739
1740 sema_init(&cmd->sem, cmd->max_reg_cmds);
1741 sema_init(&cmd->pages_sem, 1);
1742
1743 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1744 cmd_l = (u32)(cmd->dma);
1745 if (cmd_l & 0xfff) {
1746 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1747 err = -ENOMEM;
1748 goto err_free_page;
1749 }
1750
1751 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1752 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1753
1754 /* Make sure firmware sees the complete address before we proceed */
1755 wmb();
1756
1757 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1758
1759 cmd->mode = CMD_MODE_POLLING;
1760
1761 create_msg_cache(dev);
1762
1763 set_wqname(dev);
1764 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1765 if (!cmd->wq) {
1766 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1767 err = -ENOMEM;
1768 goto err_cache;
1769 }
1770
1771 err = create_debugfs_files(dev);
1772 if (err) {
1773 err = -ENOMEM;
1774 goto err_wq;
1775 }
1776
1777 return 0;
1778
1779 err_wq:
1780 destroy_workqueue(cmd->wq);
1781
1782 err_cache:
1783 destroy_msg_cache(dev);
1784
1785 err_free_page:
1786 free_cmd_page(dev, cmd);
1787
1788 err_free_pool:
1789 pci_pool_destroy(cmd->pool);
1790
1791 return err;
1792 }
1793 EXPORT_SYMBOL(mlx5_cmd_init);
1794
1795 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1796 {
1797 struct mlx5_cmd *cmd = &dev->cmd;
1798
1799 clean_debug_files(dev);
1800 destroy_workqueue(cmd->wq);
1801 destroy_msg_cache(dev);
1802 free_cmd_page(dev, cmd);
1803 pci_pool_destroy(cmd->pool);
1804 }
1805 EXPORT_SYMBOL(mlx5_cmd_cleanup);
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