1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
4 #ifndef __MLX5_EN_TC_INT_PORT_H__
5 #define __MLX5_EN_TC_INT_PORT_H__
9 struct mlx5e_tc_int_port
;
10 struct mlx5e_tc_int_port_priv
;
12 enum mlx5e_tc_int_port_type
{
13 MLX5E_TC_INT_PORT_INGRESS
,
14 MLX5E_TC_INT_PORT_EGRESS
,
17 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
18 bool mlx5e_tc_int_port_supported(const struct mlx5_eswitch
*esw
);
20 struct mlx5e_tc_int_port_priv
*
21 mlx5e_tc_int_port_init(struct mlx5e_priv
*priv
);
23 mlx5e_tc_int_port_cleanup(struct mlx5e_tc_int_port_priv
*priv
);
25 void mlx5e_tc_int_port_init_rep_rx(struct mlx5e_priv
*priv
);
26 void mlx5e_tc_int_port_cleanup_rep_rx(struct mlx5e_priv
*priv
);
29 mlx5e_tc_int_port_dev_fwd(struct mlx5e_tc_int_port_priv
*priv
,
30 struct sk_buff
*skb
, u32 int_vport_metadata
,
32 struct mlx5e_tc_int_port
*
33 mlx5e_tc_int_port_get(struct mlx5e_tc_int_port_priv
*priv
,
35 enum mlx5e_tc_int_port_type type
);
37 mlx5e_tc_int_port_put(struct mlx5e_tc_int_port_priv
*priv
,
38 struct mlx5e_tc_int_port
*int_port
);
40 u32
mlx5e_tc_int_port_get_metadata(struct mlx5e_tc_int_port
*int_port
);
41 u32
mlx5e_tc_int_port_get_metadata_for_match(struct mlx5e_tc_int_port
*int_port
);
42 int mlx5e_tc_int_port_get_flow_source(struct mlx5e_tc_int_port
*int_port
);
43 #else /* CONFIG_MLX5_CLS_ACT */
45 mlx5e_tc_int_port_get_metadata_for_match(struct mlx5e_tc_int_port
*int_port
)
51 mlx5e_tc_int_port_get_flow_source(struct mlx5e_tc_int_port
*int_port
)
56 static inline bool mlx5e_tc_int_port_supported(const struct mlx5_eswitch
*esw
)
61 static inline void mlx5e_tc_int_port_init_rep_rx(struct mlx5e_priv
*priv
) {}
62 static inline void mlx5e_tc_int_port_cleanup_rep_rx(struct mlx5e_priv
*priv
) {}
64 #endif /* CONFIG_MLX5_CLS_ACT */
65 #endif /* __MLX5_EN_TC_INT_PORT_H__ */