2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
57 #include "lib/hv_vhca.h"
59 extern const struct net_device_ops mlx5e_netdev_ops
;
62 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
63 #define MLX5E_METADATA_ETHER_LEN 8
65 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
67 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
69 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
70 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
72 #define MLX5E_MAX_PRIORITY 8
73 #define MLX5E_MAX_DSCP 64
74 #define MLX5E_MAX_NUM_TC 8
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80 #define MLX5E_RX_MAX_HEAD (256)
82 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
83 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
84 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
85 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
86 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
87 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
97 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
98 #define MLX5E_MAX_RQ_NUM_MTTS \
99 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
100 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
101 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
102 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
103 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
104 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
105 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
107 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
108 #define MLX5E_LOG_MAX_RX_WQE_BULK \
109 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
111 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
112 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
113 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
115 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
116 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
117 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
118 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_TX_XSK_POLL_BUDGET 64
142 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
144 #define MLX5E_UMR_WQE_INLINE_SZ \
145 (sizeof(struct mlx5e_umr_wqe) + \
146 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
147 MLX5_UMR_MTT_ALIGNMENT))
148 #define MLX5E_UMR_WQEBBS \
149 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
151 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
153 #define mlx5e_dbg(mlevel, priv, format, ...) \
155 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
156 netdev_warn(priv->netdev, format, \
160 enum mlx5e_rq_group
{
161 MLX5E_RQ_GROUP_REGULAR
,
163 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
166 static inline u8
mlx5e_get_num_lag_ports(struct mlx5_core_dev
*mdev
)
168 if (mlx5_lag_is_lacp_owner(mdev
))
171 return clamp_t(u8
, MLX5_CAP_GEN(mdev
, num_lag_ports
), 1, MLX5_MAX_PORTS
);
174 static inline u16
mlx5_min_rx_wqes(int wq_type
, u32 wq_size
)
177 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
178 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW
,
181 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
,
186 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
187 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
189 return is_kdump_kernel() ?
190 MLX5E_MIN_NUM_CHANNELS
:
191 min_t(int, mlx5_comp_vectors_count(mdev
), MLX5E_MAX_NUM_CHANNELS
);
194 struct mlx5e_tx_wqe
{
195 struct mlx5_wqe_ctrl_seg ctrl
;
198 struct mlx5_wqe_eth_seg eth
;
199 struct mlx5_wqe_data_seg data
[0];
201 u8 tls_progress_params_ctx
[0];
205 struct mlx5e_rx_wqe_ll
{
206 struct mlx5_wqe_srq_next_seg next
;
207 struct mlx5_wqe_data_seg data
[];
210 struct mlx5e_rx_wqe_cyc
{
211 struct mlx5_wqe_data_seg data
[0];
214 struct mlx5e_umr_wqe
{
215 struct mlx5_wqe_ctrl_seg ctrl
;
216 struct mlx5_wqe_umr_ctrl_seg uctrl
;
217 struct mlx5_mkey_seg mkc
;
219 struct mlx5_mtt inline_mtts
[0];
220 u8 tls_static_params_ctx
[0];
224 extern const char mlx5e_self_tests
[][ETH_GSTRING_LEN
];
226 enum mlx5e_priv_flag
{
227 MLX5E_PFLAG_RX_CQE_BASED_MODER
,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER
,
229 MLX5E_PFLAG_RX_CQE_COMPRESS
,
230 MLX5E_PFLAG_RX_STRIDING_RQ
,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE
,
232 MLX5E_PFLAG_XDP_TX_MPWQE
,
233 MLX5E_NUM_PFLAGS
, /* Keep last */
236 #define MLX5E_SET_PFLAG(params, pflag, enable) \
239 (params)->pflags |= BIT(pflag); \
241 (params)->pflags &= ~(BIT(pflag)); \
244 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
246 #ifdef CONFIG_MLX5_CORE_EN_DCB
247 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
250 struct mlx5e_params
{
253 u8 log_rq_mtu_frames
;
256 bool rx_cqe_compress_def
;
257 bool tunneled_offload_en
;
258 struct dim_cq_moder rx_cq_moderation
;
259 struct dim_cq_moder tx_cq_moderation
;
261 u8 tx_min_inline_mode
;
262 bool vlan_strip_disable
;
268 struct bpf_prog
*xdp_prog
;
269 struct mlx5e_xsk
*xsk
;
274 #ifdef CONFIG_MLX5_CORE_EN_DCB
275 struct mlx5e_cee_config
{
276 /* bw pct for priority group */
277 u8 pg_bw_pct
[CEE_DCBX_MAX_PGS
];
278 u8 prio_to_pg_map
[CEE_DCBX_MAX_PRIO
];
279 bool pfc_setting
[CEE_DCBX_MAX_PRIO
];
286 MLX5_DCB_CHG_NO_RESET
,
290 enum mlx5_dcbx_oper_mode mode
;
291 struct mlx5e_cee_config cee_cfg
; /* pending configuration */
294 /* The only setting that cannot be read from FW */
295 u8 tc_tsa
[IEEE_8021QAZ_MAX_TCS
];
298 /* Buffer configuration */
304 struct mlx5e_dcbx_dp
{
305 u8 dscp2prio
[MLX5E_MAX_DSCP
];
311 MLX5E_RQ_STATE_ENABLED
,
312 MLX5E_RQ_STATE_RECOVERING
,
314 MLX5E_RQ_STATE_NO_CSUM_COMPLETE
,
315 MLX5E_RQ_STATE_CSUM_FULL
, /* cqe_csum_full hw bit is set */
319 /* data path - accessed per cqe */
322 /* data path - accessed per napi poll */
324 struct napi_struct
*napi
;
325 struct mlx5_core_cq mcq
;
326 struct mlx5e_channel
*channel
;
329 struct mlx5_core_dev
*mdev
;
330 struct mlx5_wq_ctrl wq_ctrl
;
331 } ____cacheline_aligned_in_smp
;
333 struct mlx5e_cq_decomp
{
334 /* cqe decompression */
335 struct mlx5_cqe64 title
;
336 struct mlx5_mini_cqe8 mini_arr
[MLX5_MINI_CQE_ARRAY_SIZE
];
340 } ____cacheline_aligned_in_smp
;
342 struct mlx5e_tx_wqe_info
{
347 #ifdef CONFIG_MLX5_EN_TLS
348 struct page
*resync_dump_frag_page
;
352 enum mlx5e_dma_map_type
{
353 MLX5E_DMA_MAP_SINGLE
,
357 struct mlx5e_sq_dma
{
360 enum mlx5e_dma_map_type type
;
364 MLX5E_SQ_STATE_ENABLED
,
365 MLX5E_SQ_STATE_RECOVERING
,
366 MLX5E_SQ_STATE_IPSEC
,
369 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE
,
372 struct mlx5e_sq_wqe_info
{
376 /* Auxiliary data for different opcodes. */
387 /* dirtied @completion */
390 struct dim dim
; /* Adaptive Moderation */
393 u16 pc ____cacheline_aligned_in_smp
;
399 struct mlx5_wq_cyc wq
;
401 struct mlx5e_sq_stats
*stats
;
403 struct mlx5e_sq_dma
*dma_fifo
;
404 struct mlx5e_tx_wqe_info
*wqe_info
;
406 void __iomem
*uar_map
;
407 struct netdev_queue
*txq
;
415 struct hwtstamp_config
*tstamp
;
416 struct mlx5_clock
*clock
;
419 struct mlx5_wq_ctrl wq_ctrl
;
420 struct mlx5e_channel
*channel
;
424 struct work_struct recover_work
;
425 } ____cacheline_aligned_in_smp
;
427 struct mlx5e_dma_info
{
438 /* XDP packets can be transmitted in different ways. On completion, we need to
439 * distinguish between them to clean up things in a proper way.
441 enum mlx5e_xdp_xmit_mode
{
442 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
443 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
446 MLX5E_XDP_XMIT_MODE_FRAME
,
448 /* The xdp_frame was created in place as a result of XDP_TX from a
449 * regular RQ. No DMA remapping happened, and the page belongs to us.
451 MLX5E_XDP_XMIT_MODE_PAGE
,
453 /* No xdp_frame was created at all, the transmit happened from a UMEM
454 * page. The UMEM Completion Ring producer pointer has to be increased.
456 MLX5E_XDP_XMIT_MODE_XSK
,
459 struct mlx5e_xdp_info
{
460 enum mlx5e_xdp_xmit_mode mode
;
463 struct xdp_frame
*xdpf
;
468 struct mlx5e_dma_info di
;
473 struct mlx5e_xdp_xmit_data
{
479 struct mlx5e_xdp_info_fifo
{
480 struct mlx5e_xdp_info
*xi
;
486 struct mlx5e_xdp_wqe_info
{
491 struct mlx5e_xdp_mpwqe
{
492 /* Current MPWQE session */
493 struct mlx5e_tx_wqe
*wqe
;
500 typedef int (*mlx5e_fp_xmit_xdp_frame_check
)(struct mlx5e_xdpsq
*);
501 typedef bool (*mlx5e_fp_xmit_xdp_frame
)(struct mlx5e_xdpsq
*,
502 struct mlx5e_xdp_xmit_data
*,
503 struct mlx5e_xdp_info
*,
509 /* dirtied @completion */
514 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp
;
516 struct mlx5_wqe_ctrl_seg
*doorbell_cseg
;
517 struct mlx5e_xdp_mpwqe mpwqe
;
522 struct xdp_umem
*umem
;
523 struct mlx5_wq_cyc wq
;
524 struct mlx5e_xdpsq_stats
*stats
;
525 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check
;
526 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame
;
528 struct mlx5e_xdp_wqe_info
*wqe_info
;
529 struct mlx5e_xdp_info_fifo xdpi_fifo
;
531 void __iomem
*uar_map
;
540 struct mlx5_wq_ctrl wq_ctrl
;
541 struct mlx5e_channel
*channel
;
542 } ____cacheline_aligned_in_smp
;
549 struct mlx5_wqe_ctrl_seg
*doorbell_cseg
;
552 /* write@xmit, read@completion */
554 struct mlx5e_sq_wqe_info
*ico_wqe
;
558 struct mlx5_wq_cyc wq
;
559 void __iomem
*uar_map
;
564 struct mlx5_wq_ctrl wq_ctrl
;
565 struct mlx5e_channel
*channel
;
567 struct work_struct recover_work
;
568 } ____cacheline_aligned_in_smp
;
570 struct mlx5e_wqe_frag_info
{
571 struct mlx5e_dma_info
*di
;
576 struct mlx5e_umr_dma_info
{
577 struct mlx5e_dma_info dma_info
[MLX5_MPWRQ_PAGES_PER_WQE
];
580 struct mlx5e_mpw_info
{
581 struct mlx5e_umr_dma_info umr
;
582 u16 consumed_strides
;
583 DECLARE_BITMAP(xdp_xmit_bitmap
, MLX5_MPWRQ_PAGES_PER_WQE
);
586 #define MLX5E_MAX_RX_FRAGS 4
588 /* a single cache unit is capable to serve one napi call (for non-striding rq)
589 * or a MPWQE (for striding rq).
591 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
592 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
593 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
594 struct mlx5e_page_cache
{
597 struct mlx5e_dma_info page_cache
[MLX5E_CACHE_SIZE
];
601 typedef void (*mlx5e_fp_handle_rx_cqe
)(struct mlx5e_rq
*, struct mlx5_cqe64
*);
602 typedef struct sk_buff
*
603 (*mlx5e_fp_skb_from_cqe_mpwrq
)(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
,
604 u16 cqe_bcnt
, u32 head_offset
, u32 page_idx
);
605 typedef struct sk_buff
*
606 (*mlx5e_fp_skb_from_cqe
)(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
607 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
);
608 typedef bool (*mlx5e_fp_post_rx_wqes
)(struct mlx5e_rq
*rq
);
609 typedef void (*mlx5e_fp_dealloc_wqe
)(struct mlx5e_rq
*, u16
);
612 MLX5E_RQ_FLAG_XDP_XMIT
,
613 MLX5E_RQ_FLAG_XDP_REDIRECT
,
616 struct mlx5e_rq_frag_info
{
621 struct mlx5e_rq_frags_info
{
622 struct mlx5e_rq_frag_info arr
[MLX5E_MAX_RX_FRAGS
];
632 struct mlx5_wq_cyc wq
;
633 struct mlx5e_wqe_frag_info
*frags
;
634 struct mlx5e_dma_info
*di
;
635 struct mlx5e_rq_frags_info info
;
636 mlx5e_fp_skb_from_cqe skb_from_cqe
;
639 struct mlx5_wq_ll wq
;
640 struct mlx5e_umr_wqe umr_wqe
;
641 struct mlx5e_mpw_info
*info
;
642 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq
;
654 u8 map_dir
; /* dma map direction */
657 struct mlx5e_channel
*channel
;
659 struct net_device
*netdev
;
660 struct mlx5e_rq_stats
*stats
;
662 struct mlx5e_cq_decomp cqd
;
663 struct mlx5e_page_cache page_cache
;
664 struct hwtstamp_config
*tstamp
;
665 struct mlx5_clock
*clock
;
667 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
668 mlx5e_fp_post_rx_wqes post_wqes
;
669 mlx5e_fp_dealloc_wqe dealloc_wqe
;
675 struct dim dim
; /* Dynamic Interrupt Moderation */
678 struct bpf_prog
*xdp_prog
;
679 struct mlx5e_xdpsq
*xdpsq
;
680 DECLARE_BITMAP(flags
, 8);
681 struct page_pool
*page_pool
;
683 /* AF_XDP zero-copy */
684 struct zero_copy_allocator zca
;
685 struct xdp_umem
*umem
;
687 struct work_struct recover_work
;
690 struct mlx5_wq_ctrl wq_ctrl
;
694 struct mlx5_core_dev
*mdev
;
695 struct mlx5_core_mkey umr_mkey
;
697 /* XDP read-mostly */
698 struct xdp_rxq_info xdp_rxq
;
699 } ____cacheline_aligned_in_smp
;
701 enum mlx5e_channel_state
{
702 MLX5E_CHANNEL_STATE_XSK
,
703 MLX5E_CHANNEL_NUM_STATES
706 struct mlx5e_channel
{
709 struct mlx5e_xdpsq rq_xdpsq
;
710 struct mlx5e_txqsq sq
[MLX5E_MAX_NUM_TC
];
711 struct mlx5e_icosq icosq
; /* internal control operations */
713 struct napi_struct napi
;
715 struct net_device
*netdev
;
721 struct mlx5e_xdpsq xdpsq
;
723 /* AF_XDP zero-copy */
724 struct mlx5e_rq xskrq
;
725 struct mlx5e_xdpsq xsksq
;
726 struct mlx5e_icosq xskicosq
;
727 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
728 spinlock_t xskicosq_lock
;
730 /* data path - accessed per napi poll */
731 struct irq_desc
*irq_desc
;
732 struct mlx5e_ch_stats
*stats
;
735 struct mlx5e_priv
*priv
;
736 struct mlx5_core_dev
*mdev
;
737 struct hwtstamp_config
*tstamp
;
738 DECLARE_BITMAP(state
, MLX5E_CHANNEL_NUM_STATES
);
743 struct mlx5e_channels
{
744 struct mlx5e_channel
**c
;
746 struct mlx5e_params params
;
749 struct mlx5e_channel_stats
{
750 struct mlx5e_ch_stats ch
;
751 struct mlx5e_sq_stats sq
[MLX5E_MAX_NUM_TC
];
752 struct mlx5e_rq_stats rq
;
753 struct mlx5e_rq_stats xskrq
;
754 struct mlx5e_xdpsq_stats rq_xdpsq
;
755 struct mlx5e_xdpsq_stats xdpsq
;
756 struct mlx5e_xdpsq_stats xsksq
;
757 } ____cacheline_aligned_in_smp
;
761 MLX5E_STATE_DESTROYING
,
762 MLX5E_STATE_XDP_TX_ENABLED
,
763 MLX5E_STATE_XDP_ACTIVE
,
773 struct mlx5e_rqt rqt
;
774 struct list_head list
;
782 struct mlx5e_rss_params
{
783 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
784 u32 rx_hash_fields
[MLX5E_NUM_INDIR_TIRS
];
785 u8 toeplitz_hash_key
[40];
789 struct mlx5e_modify_sq_param
{
796 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
797 struct mlx5e_hv_vhca_stats_agent
{
798 struct mlx5_hv_vhca_agent
*agent
;
799 struct delayed_work work
;
806 /* UMEMs are stored separately from channels, because we don't want to
807 * lose them when channels are recreated. The kernel also stores UMEMs,
808 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
809 * so rely on our mechanism.
811 struct xdp_umem
**umems
;
816 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
817 * initialized, and used where we can't allocate them because that functions
818 * must not fail. Use with care and make sure the same variable is not used
819 * simultaneously by multiple users.
821 struct mlx5e_scratchpad
{
822 cpumask_var_t cpumask
;
826 /* priv data path fields - start */
827 struct mlx5e_txqsq
*txq2sq
[MLX5E_MAX_NUM_CHANNELS
* MLX5E_MAX_NUM_TC
];
828 int channel_tc2realtxq
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
829 #ifdef CONFIG_MLX5_CORE_EN_DCB
830 struct mlx5e_dcbx_dp dcbx_dp
;
832 /* priv data path fields - end */
836 struct mutex state_lock
; /* Protects Interface state */
837 struct mlx5e_rq drop_rq
;
839 struct mlx5e_channels channels
;
840 u32 tisn
[MLX5_MAX_PORTS
][MLX5E_MAX_NUM_TC
];
841 struct mlx5e_rqt indir_rqt
;
842 struct mlx5e_tir indir_tir
[MLX5E_NUM_INDIR_TIRS
];
843 struct mlx5e_tir inner_indir_tir
[MLX5E_NUM_INDIR_TIRS
];
844 struct mlx5e_tir direct_tir
[MLX5E_MAX_NUM_CHANNELS
];
845 struct mlx5e_tir xsk_tir
[MLX5E_MAX_NUM_CHANNELS
];
846 struct mlx5e_rss_params rss_params
;
847 u32 tx_rates
[MLX5E_MAX_NUM_SQS
];
849 struct mlx5e_flow_steering fs
;
851 struct workqueue_struct
*wq
;
852 struct work_struct update_carrier_work
;
853 struct work_struct set_rx_mode_work
;
854 struct work_struct tx_timeout_work
;
855 struct work_struct update_stats_work
;
856 struct work_struct monitor_counters_work
;
857 struct mlx5_nb monitor_counters_nb
;
859 struct mlx5_core_dev
*mdev
;
860 struct net_device
*netdev
;
861 struct mlx5e_stats stats
;
862 struct mlx5e_channel_stats channel_stats
[MLX5E_MAX_NUM_CHANNELS
];
865 struct hwtstamp_config tstamp
;
867 u16 drop_rq_q_counter
;
868 struct notifier_block events_nb
;
870 #ifdef CONFIG_MLX5_CORE_EN_DCB
871 struct mlx5e_dcbx dcbx
;
874 const struct mlx5e_profile
*profile
;
876 #ifdef CONFIG_MLX5_EN_IPSEC
877 struct mlx5e_ipsec
*ipsec
;
879 #ifdef CONFIG_MLX5_EN_TLS
880 struct mlx5e_tls
*tls
;
882 struct devlink_health_reporter
*tx_reporter
;
883 struct devlink_health_reporter
*rx_reporter
;
884 struct devlink_port dl_port
;
885 struct mlx5e_xsk xsk
;
886 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
887 struct mlx5e_hv_vhca_stats_agent stats_agent
;
889 struct mlx5e_scratchpad scratchpad
;
892 struct mlx5e_profile
{
893 int (*init
)(struct mlx5_core_dev
*mdev
,
894 struct net_device
*netdev
,
895 const struct mlx5e_profile
*profile
, void *ppriv
);
896 void (*cleanup
)(struct mlx5e_priv
*priv
);
897 int (*init_rx
)(struct mlx5e_priv
*priv
);
898 void (*cleanup_rx
)(struct mlx5e_priv
*priv
);
899 int (*init_tx
)(struct mlx5e_priv
*priv
);
900 void (*cleanup_tx
)(struct mlx5e_priv
*priv
);
901 void (*enable
)(struct mlx5e_priv
*priv
);
902 void (*disable
)(struct mlx5e_priv
*priv
);
903 int (*update_rx
)(struct mlx5e_priv
*priv
);
904 void (*update_stats
)(struct mlx5e_priv
*priv
);
905 void (*update_carrier
)(struct mlx5e_priv
*priv
);
906 unsigned int (*stats_grps_num
)(struct mlx5e_priv
*priv
);
907 mlx5e_stats_grp_t
*stats_grps
;
909 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
910 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe
;
916 void mlx5e_build_ptys2ethtool_map(void);
918 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
919 struct net_device
*sb_dev
);
920 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
921 netdev_tx_t
mlx5e_sq_xmit(struct mlx5e_txqsq
*sq
, struct sk_buff
*skb
,
922 struct mlx5e_tx_wqe
*wqe
, u16 pi
, bool xmit_more
);
924 void mlx5e_trigger_irq(struct mlx5e_icosq
*sq
);
925 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
, struct mlx5_eqe
*eqe
);
926 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
927 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
928 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
, int napi_budget
);
929 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
930 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq
*sq
);
932 static inline u32
mlx5e_rqwq_get_size(struct mlx5e_rq
*rq
)
934 switch (rq
->wq_type
) {
935 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
936 return mlx5_wq_ll_get_size(&rq
->mpwqe
.wq
);
938 return mlx5_wq_cyc_get_size(&rq
->wqe
.wq
);
942 static inline u32
mlx5e_rqwq_get_cur_sz(struct mlx5e_rq
*rq
)
944 switch (rq
->wq_type
) {
945 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
946 return rq
->mpwqe
.wq
.cur_sz
;
948 return rq
->wqe
.wq
.cur_sz
;
952 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
);
953 bool mlx5e_striding_rq_possible(struct mlx5_core_dev
*mdev
,
954 struct mlx5e_params
*params
);
956 void mlx5e_page_dma_unmap(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
);
957 void mlx5e_page_release_dynamic(struct mlx5e_rq
*rq
,
958 struct mlx5e_dma_info
*dma_info
,
960 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
961 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
962 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
963 void mlx5e_poll_ico_cq(struct mlx5e_cq
*cq
);
964 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq
*rq
);
965 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
);
966 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
);
968 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
,
969 u16 cqe_bcnt
, u32 head_offset
, u32 page_idx
);
971 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
,
972 u16 cqe_bcnt
, u32 head_offset
, u32 page_idx
);
974 mlx5e_skb_from_cqe_linear(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
975 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
);
977 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
978 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
);
980 void mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
);
981 void mlx5e_fold_sw_stats64(struct mlx5e_priv
*priv
, struct rtnl_link_stats64
*s
);
983 void mlx5e_init_l2_addr(struct mlx5e_priv
*priv
);
984 int mlx5e_self_test_num(struct mlx5e_priv
*priv
);
985 void mlx5e_self_test(struct net_device
*ndev
, struct ethtool_test
*etest
,
987 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
989 int mlx5e_hwstamp_set(struct mlx5e_priv
*priv
, struct ifreq
*ifr
);
990 int mlx5e_hwstamp_get(struct mlx5e_priv
*priv
, struct ifreq
*ifr
);
991 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv
*priv
, bool val
);
993 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
995 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
997 void mlx5e_timestamp_init(struct mlx5e_priv
*priv
);
999 struct mlx5e_redirect_rqt_param
{
1002 u32 rqn
; /* Direct RQN (Non-RSS) */
1005 struct mlx5e_channels
*channels
;
1006 } rss
; /* RSS data */
1010 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
,
1011 struct mlx5e_redirect_rqt_param rrp
);
1012 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params
*rss_params
,
1013 const struct mlx5e_tirc_config
*ttconfig
,
1014 void *tirc
, bool inner
);
1015 void mlx5e_modify_tirs_hash(struct mlx5e_priv
*priv
, void *in
);
1016 struct mlx5e_tirc_config
mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt
);
1018 struct mlx5e_xsk_param
;
1020 struct mlx5e_rq_param
;
1021 int mlx5e_open_rq(struct mlx5e_channel
*c
, struct mlx5e_params
*params
,
1022 struct mlx5e_rq_param
*param
, struct mlx5e_xsk_param
*xsk
,
1023 struct xdp_umem
*umem
, struct mlx5e_rq
*rq
);
1024 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
, int wait_time
);
1025 void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
);
1026 void mlx5e_close_rq(struct mlx5e_rq
*rq
);
1028 struct mlx5e_sq_param
;
1029 int mlx5e_open_icosq(struct mlx5e_channel
*c
, struct mlx5e_params
*params
,
1030 struct mlx5e_sq_param
*param
, struct mlx5e_icosq
*sq
);
1031 void mlx5e_close_icosq(struct mlx5e_icosq
*sq
);
1032 int mlx5e_open_xdpsq(struct mlx5e_channel
*c
, struct mlx5e_params
*params
,
1033 struct mlx5e_sq_param
*param
, struct xdp_umem
*umem
,
1034 struct mlx5e_xdpsq
*sq
, bool is_redirect
);
1035 void mlx5e_close_xdpsq(struct mlx5e_xdpsq
*sq
);
1037 struct mlx5e_cq_param
;
1038 int mlx5e_open_cq(struct mlx5e_channel
*c
, struct dim_cq_moder moder
,
1039 struct mlx5e_cq_param
*param
, struct mlx5e_cq
*cq
);
1040 void mlx5e_close_cq(struct mlx5e_cq
*cq
);
1042 int mlx5e_open_locked(struct net_device
*netdev
);
1043 int mlx5e_close_locked(struct net_device
*netdev
);
1045 int mlx5e_open_channels(struct mlx5e_priv
*priv
,
1046 struct mlx5e_channels
*chs
);
1047 void mlx5e_close_channels(struct mlx5e_channels
*chs
);
1049 /* Function pointer to be used to modify HW or kernel settings while
1050 * switching channels
1052 typedef int (*mlx5e_fp_preactivate
)(struct mlx5e_priv
*priv
, void *context
);
1053 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1054 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1058 int mlx5e_safe_reopen_channels(struct mlx5e_priv
*priv
);
1059 int mlx5e_safe_switch_channels(struct mlx5e_priv
*priv
,
1060 struct mlx5e_channels
*new_chs
,
1061 mlx5e_fp_preactivate preactivate
,
1063 int mlx5e_num_channels_changed(struct mlx5e_priv
*priv
);
1064 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv
*priv
, void *context
);
1065 void mlx5e_activate_priv_channels(struct mlx5e_priv
*priv
);
1066 void mlx5e_deactivate_priv_channels(struct mlx5e_priv
*priv
);
1068 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
1070 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params
*params
,
1072 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
,
1074 void mlx5e_set_rq_type(struct mlx5_core_dev
*mdev
, struct mlx5e_params
*params
);
1075 void mlx5e_init_rq_type_params(struct mlx5_core_dev
*mdev
,
1076 struct mlx5e_params
*params
);
1077 int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
, int next_state
);
1078 void mlx5e_activate_rq(struct mlx5e_rq
*rq
);
1079 void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
);
1080 void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
);
1081 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq
*rq
);
1082 void mlx5e_activate_icosq(struct mlx5e_icosq
*icosq
);
1083 void mlx5e_deactivate_icosq(struct mlx5e_icosq
*icosq
);
1085 int mlx5e_modify_sq(struct mlx5_core_dev
*mdev
, u32 sqn
,
1086 struct mlx5e_modify_sq_param
*p
);
1087 void mlx5e_activate_txqsq(struct mlx5e_txqsq
*sq
);
1088 void mlx5e_tx_disable_queue(struct netdev_queue
*txq
);
1090 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev
*mdev
)
1092 return MLX5_CAP_ETH(mdev
, swp
) &&
1093 MLX5_CAP_ETH(mdev
, swp_csum
) && MLX5_CAP_ETH(mdev
, swp_lso
);
1096 extern const struct ethtool_ops mlx5e_ethtool_ops
;
1097 #ifdef CONFIG_MLX5_CORE_EN_DCB
1098 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops
;
1099 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv
*priv
, struct ieee_ets
*ets
);
1100 void mlx5e_dcbnl_initialize(struct mlx5e_priv
*priv
);
1101 void mlx5e_dcbnl_init_app(struct mlx5e_priv
*priv
);
1102 void mlx5e_dcbnl_delete_app(struct mlx5e_priv
*priv
);
1105 int mlx5e_create_tir(struct mlx5_core_dev
*mdev
, struct mlx5e_tir
*tir
,
1107 void mlx5e_destroy_tir(struct mlx5_core_dev
*mdev
,
1108 struct mlx5e_tir
*tir
);
1109 int mlx5e_create_mdev_resources(struct mlx5_core_dev
*mdev
);
1110 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev
*mdev
);
1111 int mlx5e_refresh_tirs(struct mlx5e_priv
*priv
, bool enable_uc_lb
);
1113 /* common netdev helpers */
1114 void mlx5e_create_q_counters(struct mlx5e_priv
*priv
);
1115 void mlx5e_destroy_q_counters(struct mlx5e_priv
*priv
);
1116 int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
,
1117 struct mlx5e_rq
*drop_rq
);
1118 void mlx5e_close_drop_rq(struct mlx5e_rq
*drop_rq
);
1120 int mlx5e_create_indirect_rqt(struct mlx5e_priv
*priv
);
1122 int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
, bool inner_ttc
);
1123 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
, bool inner_ttc
);
1125 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1126 void mlx5e_destroy_direct_rqts(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1127 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1128 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
, struct mlx5e_tir
*tirs
);
1129 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
);
1131 int mlx5e_create_tis(struct mlx5_core_dev
*mdev
, void *in
, u32
*tisn
);
1132 void mlx5e_destroy_tis(struct mlx5_core_dev
*mdev
, u32 tisn
);
1134 int mlx5e_create_tises(struct mlx5e_priv
*priv
);
1135 void mlx5e_destroy_tises(struct mlx5e_priv
*priv
);
1136 int mlx5e_update_nic_rx(struct mlx5e_priv
*priv
);
1137 void mlx5e_update_carrier(struct mlx5e_priv
*priv
);
1138 int mlx5e_close(struct net_device
*netdev
);
1139 int mlx5e_open(struct net_device
*netdev
);
1140 void mlx5e_update_ndo_stats(struct mlx5e_priv
*priv
);
1142 void mlx5e_queue_update_stats(struct mlx5e_priv
*priv
);
1143 int mlx5e_bits_invert(unsigned long a
, int size
);
1145 int mlx5e_set_dev_port_mtu(struct mlx5e_priv
*priv
);
1146 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv
*priv
, void *context
);
1147 int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
,
1148 mlx5e_fp_preactivate preactivate
);
1150 /* ethtool helpers */
1151 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv
*priv
,
1152 struct ethtool_drvinfo
*drvinfo
);
1153 void mlx5e_ethtool_get_strings(struct mlx5e_priv
*priv
,
1154 uint32_t stringset
, uint8_t *data
);
1155 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv
*priv
, int sset
);
1156 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv
*priv
,
1157 struct ethtool_stats
*stats
, u64
*data
);
1158 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv
*priv
,
1159 struct ethtool_ringparam
*param
);
1160 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv
*priv
,
1161 struct ethtool_ringparam
*param
);
1162 void mlx5e_ethtool_get_channels(struct mlx5e_priv
*priv
,
1163 struct ethtool_channels
*ch
);
1164 int mlx5e_ethtool_set_channels(struct mlx5e_priv
*priv
,
1165 struct ethtool_channels
*ch
);
1166 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv
*priv
,
1167 struct ethtool_coalesce
*coal
);
1168 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv
*priv
,
1169 struct ethtool_coalesce
*coal
);
1170 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv
*priv
,
1171 struct ethtool_link_ksettings
*link_ksettings
);
1172 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv
*priv
,
1173 const struct ethtool_link_ksettings
*link_ksettings
);
1174 int mlx5e_get_rxfh(struct net_device
*netdev
, u32
*indir
, u8
*key
, u8
*hfunc
);
1175 int mlx5e_set_rxfh(struct net_device
*dev
, const u32
*indir
, const u8
*key
,
1177 int mlx5e_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
1179 int mlx5e_set_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
);
1180 u32
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv
*priv
);
1181 u32
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv
*priv
);
1182 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv
*priv
,
1183 struct ethtool_ts_info
*info
);
1184 int mlx5e_ethtool_flash_device(struct mlx5e_priv
*priv
,
1185 struct ethtool_flash
*flash
);
1186 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv
*priv
,
1187 struct ethtool_pauseparam
*pauseparam
);
1188 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv
*priv
,
1189 struct ethtool_pauseparam
*pauseparam
);
1191 /* mlx5e generic netdev management API */
1192 int mlx5e_netdev_init(struct net_device
*netdev
,
1193 struct mlx5e_priv
*priv
,
1194 struct mlx5_core_dev
*mdev
,
1195 const struct mlx5e_profile
*profile
,
1197 void mlx5e_netdev_cleanup(struct net_device
*netdev
, struct mlx5e_priv
*priv
);
1199 mlx5e_create_netdev(struct mlx5_core_dev
*mdev
, const struct mlx5e_profile
*profile
,
1200 int nch
, void *ppriv
);
1201 int mlx5e_attach_netdev(struct mlx5e_priv
*priv
);
1202 void mlx5e_detach_netdev(struct mlx5e_priv
*priv
);
1203 void mlx5e_destroy_netdev(struct mlx5e_priv
*priv
);
1204 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv
*priv
);
1205 void mlx5e_build_nic_params(struct mlx5e_priv
*priv
,
1206 struct mlx5e_xsk
*xsk
,
1207 struct mlx5e_rss_params
*rss_params
,
1208 struct mlx5e_params
*params
,
1210 void mlx5e_build_rq_params(struct mlx5_core_dev
*mdev
,
1211 struct mlx5e_params
*params
);
1212 void mlx5e_build_rss_params(struct mlx5e_rss_params
*rss_params
,
1214 void mlx5e_rx_dim_work(struct work_struct
*work
);
1215 void mlx5e_tx_dim_work(struct work_struct
*work
);
1217 void mlx5e_add_vxlan_port(struct net_device
*netdev
, struct udp_tunnel_info
*ti
);
1218 void mlx5e_del_vxlan_port(struct net_device
*netdev
, struct udp_tunnel_info
*ti
);
1219 netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
1220 struct net_device
*netdev
,
1221 netdev_features_t features
);
1222 int mlx5e_set_features(struct net_device
*netdev
, netdev_features_t features
);
1223 #ifdef CONFIG_MLX5_ESWITCH
1224 int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
);
1225 int mlx5e_set_vf_rate(struct net_device
*dev
, int vf
, int min_tx_rate
, int max_tx_rate
);
1226 int mlx5e_get_vf_config(struct net_device
*dev
, int vf
, struct ifla_vf_info
*ivi
);
1227 int mlx5e_get_vf_stats(struct net_device
*dev
, int vf
, struct ifla_vf_stats
*vf_stats
);
1229 #endif /* __MLX5_EN_H__ */