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1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include <net/switchdev.h>
48 #include "wq.h"
49 #include "mlx5_core.h"
50 #include "en_stats.h"
51
52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
53
54 #define MLX5E_MAX_NUM_TC 8
55
56 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
57 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
59
60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
63
64 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
65 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
66 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
67
68 #define MLX5_RX_HEADROOM NET_SKB_PAD
69
70 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
71 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
72 #define MLX5_MPWRQ_LOG_WQE_SZ 18
73 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
74 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
75 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
77 MLX5_MPWRQ_WQE_PAGE_ORDER)
78
79 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
80 #define MLX5E_REQUIRED_MTTS(rqs, wqes)\
81 (rqs * wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
82 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) <= U16_MAX)
83
84 #define MLX5_UMR_ALIGN (2048)
85 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
86
87 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
88 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
89 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
90 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
91 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
92 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
93 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
94 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
95
96 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
97 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
98 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
99 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
100 #define MLX5E_TX_CQ_POLL_BUDGET 128
101 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
102 #define MLX5E_SQ_BF_BUDGET 16
103
104 #define MLX5E_ICOSQ_MAX_WQEBBS \
105 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
106
107 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
108 #define MLX5E_XDP_IHS_DS_COUNT \
109 DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
110 #define MLX5E_XDP_TX_DS_COUNT \
111 (MLX5E_XDP_IHS_DS_COUNT + \
112 (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
113 #define MLX5E_XDP_TX_WQEBBS \
114 DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
115
116 #define MLX5E_NUM_MAIN_GROUPS 9
117
118 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
119 {
120 switch (wq_type) {
121 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
122 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
123 wq_size / 2);
124 default:
125 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
126 wq_size / 2);
127 }
128 }
129
130 static inline int mlx5_min_log_rq_size(int wq_type)
131 {
132 switch (wq_type) {
133 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
134 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
135 default:
136 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
137 }
138 }
139
140 static inline int mlx5_max_log_rq_size(int wq_type)
141 {
142 switch (wq_type) {
143 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
144 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
145 default:
146 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
147 }
148 }
149
150 enum {
151 MLX5E_INLINE_MODE_L2,
152 MLX5E_INLINE_MODE_VPORT_CONTEXT,
153 MLX5_INLINE_MODE_NOT_REQUIRED,
154 };
155
156 struct mlx5e_tx_wqe {
157 struct mlx5_wqe_ctrl_seg ctrl;
158 struct mlx5_wqe_eth_seg eth;
159 };
160
161 struct mlx5e_rx_wqe {
162 struct mlx5_wqe_srq_next_seg next;
163 struct mlx5_wqe_data_seg data;
164 };
165
166 struct mlx5e_umr_wqe {
167 struct mlx5_wqe_ctrl_seg ctrl;
168 struct mlx5_wqe_umr_ctrl_seg uctrl;
169 struct mlx5_mkey_seg mkc;
170 struct mlx5_wqe_data_seg data;
171 };
172
173 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
174 "rx_cqe_moder",
175 };
176
177 enum mlx5e_priv_flag {
178 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
179 };
180
181 #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
182 do { \
183 if (enable) \
184 priv->pflags |= pflag; \
185 else \
186 priv->pflags &= ~pflag; \
187 } while (0)
188
189 #ifdef CONFIG_MLX5_CORE_EN_DCB
190 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
191 #endif
192
193 struct mlx5e_cq_moder {
194 u16 usec;
195 u16 pkts;
196 };
197
198 struct mlx5e_params {
199 u8 log_sq_size;
200 u8 rq_wq_type;
201 u8 mpwqe_log_stride_sz;
202 u8 mpwqe_log_num_strides;
203 u8 log_rq_size;
204 u16 num_channels;
205 u8 num_tc;
206 u8 rx_cq_period_mode;
207 bool rx_cqe_compress_admin;
208 bool rx_cqe_compress;
209 struct mlx5e_cq_moder rx_cq_moderation;
210 struct mlx5e_cq_moder tx_cq_moderation;
211 u16 min_rx_wqes;
212 bool lro_en;
213 u32 lro_wqe_sz;
214 u16 tx_max_inline;
215 u8 tx_min_inline_mode;
216 u8 rss_hfunc;
217 u8 toeplitz_hash_key[40];
218 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
219 bool vlan_strip_disable;
220 #ifdef CONFIG_MLX5_CORE_EN_DCB
221 struct ieee_ets ets;
222 #endif
223 bool rx_am_enabled;
224 };
225
226 struct mlx5e_tstamp {
227 rwlock_t lock;
228 struct cyclecounter cycles;
229 struct timecounter clock;
230 struct hwtstamp_config hwtstamp_config;
231 u32 nominal_c_mult;
232 unsigned long overflow_period;
233 struct delayed_work overflow_work;
234 struct mlx5_core_dev *mdev;
235 struct ptp_clock *ptp;
236 struct ptp_clock_info ptp_info;
237 };
238
239 enum {
240 MLX5E_RQ_STATE_FLUSH,
241 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
242 MLX5E_RQ_STATE_AM,
243 };
244
245 struct mlx5e_cq {
246 /* data path - accessed per cqe */
247 struct mlx5_cqwq wq;
248
249 /* data path - accessed per napi poll */
250 u16 event_ctr;
251 struct napi_struct *napi;
252 struct mlx5_core_cq mcq;
253 struct mlx5e_channel *channel;
254 struct mlx5e_priv *priv;
255
256 /* cqe decompression */
257 struct mlx5_cqe64 title;
258 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
259 u8 mini_arr_idx;
260 u16 decmprs_left;
261 u16 decmprs_wqe_counter;
262
263 /* control */
264 struct mlx5_wq_ctrl wq_ctrl;
265 } ____cacheline_aligned_in_smp;
266
267 struct mlx5e_rq;
268 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
269 struct mlx5_cqe64 *cqe);
270 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
271 u16 ix);
272
273 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
274
275 struct mlx5e_dma_info {
276 struct page *page;
277 dma_addr_t addr;
278 };
279
280 struct mlx5e_rx_am_stats {
281 int ppms; /* packets per msec */
282 int epms; /* events per msec */
283 };
284
285 struct mlx5e_rx_am_sample {
286 ktime_t time;
287 unsigned int pkt_ctr;
288 u16 event_ctr;
289 };
290
291 struct mlx5e_rx_am { /* Adaptive Moderation */
292 u8 state;
293 struct mlx5e_rx_am_stats prev_stats;
294 struct mlx5e_rx_am_sample start_sample;
295 struct work_struct work;
296 u8 profile_ix;
297 u8 mode;
298 u8 tune_state;
299 u8 steps_right;
300 u8 steps_left;
301 u8 tired;
302 };
303
304 /* a single cache unit is capable to serve one napi call (for non-striding rq)
305 * or a MPWQE (for striding rq).
306 */
307 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
308 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
309 #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
310 struct mlx5e_page_cache {
311 u32 head;
312 u32 tail;
313 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
314 };
315
316 struct mlx5e_rq {
317 /* data path */
318 struct mlx5_wq_ll wq;
319
320 union {
321 struct mlx5e_dma_info *dma_info;
322 struct {
323 struct mlx5e_mpw_info *info;
324 void *mtt_no_align;
325 u32 mtt_offset;
326 } mpwqe;
327 };
328 struct {
329 u8 page_order;
330 u32 wqe_sz; /* wqe data buffer size */
331 u8 map_dir; /* dma map direction */
332 } buff;
333 __be32 mkey_be;
334
335 struct device *pdev;
336 struct net_device *netdev;
337 struct mlx5e_tstamp *tstamp;
338 struct mlx5e_rq_stats stats;
339 struct mlx5e_cq cq;
340 struct mlx5e_page_cache page_cache;
341
342 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
343 mlx5e_fp_alloc_wqe alloc_wqe;
344 mlx5e_fp_dealloc_wqe dealloc_wqe;
345
346 unsigned long state;
347 int ix;
348
349 struct mlx5e_rx_am am; /* Adaptive Moderation */
350 struct bpf_prog *xdp_prog;
351
352 /* control */
353 struct mlx5_wq_ctrl wq_ctrl;
354 u8 wq_type;
355 u32 mpwqe_stride_sz;
356 u32 mpwqe_num_strides;
357 u32 rqn;
358 struct mlx5e_channel *channel;
359 struct mlx5e_priv *priv;
360 } ____cacheline_aligned_in_smp;
361
362 struct mlx5e_umr_dma_info {
363 __be64 *mtt;
364 dma_addr_t mtt_addr;
365 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
366 struct mlx5e_umr_wqe wqe;
367 };
368
369 struct mlx5e_mpw_info {
370 struct mlx5e_umr_dma_info umr;
371 u16 consumed_strides;
372 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
373 };
374
375 struct mlx5e_tx_wqe_info {
376 u32 num_bytes;
377 u8 num_wqebbs;
378 u8 num_dma;
379 };
380
381 enum mlx5e_dma_map_type {
382 MLX5E_DMA_MAP_SINGLE,
383 MLX5E_DMA_MAP_PAGE
384 };
385
386 struct mlx5e_sq_dma {
387 dma_addr_t addr;
388 u32 size;
389 enum mlx5e_dma_map_type type;
390 };
391
392 enum {
393 MLX5E_SQ_STATE_FLUSH,
394 MLX5E_SQ_STATE_BF_ENABLE,
395 };
396
397 struct mlx5e_sq_wqe_info {
398 u8 opcode;
399 u8 num_wqebbs;
400 };
401
402 enum mlx5e_sq_type {
403 MLX5E_SQ_TXQ,
404 MLX5E_SQ_ICO,
405 MLX5E_SQ_XDP
406 };
407
408 struct mlx5e_sq {
409 /* data path */
410
411 /* dirtied @completion */
412 u16 cc;
413 u32 dma_fifo_cc;
414
415 /* dirtied @xmit */
416 u16 pc ____cacheline_aligned_in_smp;
417 u32 dma_fifo_pc;
418 u16 bf_offset;
419 u16 prev_cc;
420 u8 bf_budget;
421 struct mlx5e_sq_stats stats;
422
423 struct mlx5e_cq cq;
424
425 /* pointers to per tx element info: write@xmit, read@completion */
426 union {
427 struct {
428 struct sk_buff **skb;
429 struct mlx5e_sq_dma *dma_fifo;
430 struct mlx5e_tx_wqe_info *wqe_info;
431 } txq;
432 struct mlx5e_sq_wqe_info *ico_wqe;
433 struct {
434 struct mlx5e_sq_wqe_info *wqe_info;
435 struct mlx5e_dma_info *di;
436 bool doorbell;
437 } xdp;
438 } db;
439
440 /* read only */
441 struct mlx5_wq_cyc wq;
442 u32 dma_fifo_mask;
443 void __iomem *uar_map;
444 struct netdev_queue *txq;
445 u32 sqn;
446 u16 bf_buf_size;
447 u16 max_inline;
448 u8 min_inline_mode;
449 u16 edge;
450 struct device *pdev;
451 struct mlx5e_tstamp *tstamp;
452 __be32 mkey_be;
453 unsigned long state;
454
455 /* control path */
456 struct mlx5_wq_ctrl wq_ctrl;
457 struct mlx5_uar uar;
458 struct mlx5e_channel *channel;
459 int tc;
460 u32 rate_limit;
461 u8 type;
462 } ____cacheline_aligned_in_smp;
463
464 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
465 {
466 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
467 (sq->cc == sq->pc));
468 }
469
470 enum channel_flags {
471 MLX5E_CHANNEL_NAPI_SCHED = 1,
472 };
473
474 struct mlx5e_channel {
475 /* data path */
476 struct mlx5e_rq rq;
477 struct mlx5e_sq xdp_sq;
478 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
479 struct mlx5e_sq icosq; /* internal control operations */
480 bool xdp;
481 struct napi_struct napi;
482 struct device *pdev;
483 struct net_device *netdev;
484 __be32 mkey_be;
485 u8 num_tc;
486 unsigned long flags;
487
488 /* control */
489 struct mlx5e_priv *priv;
490 int ix;
491 int cpu;
492 };
493
494 enum mlx5e_traffic_types {
495 MLX5E_TT_IPV4_TCP,
496 MLX5E_TT_IPV6_TCP,
497 MLX5E_TT_IPV4_UDP,
498 MLX5E_TT_IPV6_UDP,
499 MLX5E_TT_IPV4_IPSEC_AH,
500 MLX5E_TT_IPV6_IPSEC_AH,
501 MLX5E_TT_IPV4_IPSEC_ESP,
502 MLX5E_TT_IPV6_IPSEC_ESP,
503 MLX5E_TT_IPV4,
504 MLX5E_TT_IPV6,
505 MLX5E_TT_ANY,
506 MLX5E_NUM_TT,
507 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
508 };
509
510 enum {
511 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
512 MLX5E_STATE_OPENED,
513 MLX5E_STATE_DESTROYING,
514 };
515
516 struct mlx5e_vxlan_db {
517 spinlock_t lock; /* protect vxlan table */
518 struct radix_tree_root tree;
519 };
520
521 struct mlx5e_l2_rule {
522 u8 addr[ETH_ALEN + 2];
523 struct mlx5_flow_rule *rule;
524 };
525
526 struct mlx5e_flow_table {
527 int num_groups;
528 struct mlx5_flow_table *t;
529 struct mlx5_flow_group **g;
530 };
531
532 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
533
534 struct mlx5e_tc_table {
535 struct mlx5_flow_table *t;
536
537 struct rhashtable_params ht_params;
538 struct rhashtable ht;
539 };
540
541 struct mlx5e_vlan_table {
542 struct mlx5e_flow_table ft;
543 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
544 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
545 struct mlx5_flow_rule *untagged_rule;
546 struct mlx5_flow_rule *any_vlan_rule;
547 bool filter_disabled;
548 };
549
550 struct mlx5e_l2_table {
551 struct mlx5e_flow_table ft;
552 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
553 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
554 struct mlx5e_l2_rule broadcast;
555 struct mlx5e_l2_rule allmulti;
556 struct mlx5e_l2_rule promisc;
557 bool broadcast_enabled;
558 bool allmulti_enabled;
559 bool promisc_enabled;
560 };
561
562 /* L3/L4 traffic type classifier */
563 struct mlx5e_ttc_table {
564 struct mlx5e_flow_table ft;
565 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
566 };
567
568 #define ARFS_HASH_SHIFT BITS_PER_BYTE
569 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
570 struct arfs_table {
571 struct mlx5e_flow_table ft;
572 struct mlx5_flow_rule *default_rule;
573 struct hlist_head rules_hash[ARFS_HASH_SIZE];
574 };
575
576 enum arfs_type {
577 ARFS_IPV4_TCP,
578 ARFS_IPV6_TCP,
579 ARFS_IPV4_UDP,
580 ARFS_IPV6_UDP,
581 ARFS_NUM_TYPES,
582 };
583
584 struct mlx5e_arfs_tables {
585 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
586 /* Protect aRFS rules list */
587 spinlock_t arfs_lock;
588 struct list_head rules;
589 int last_filter_id;
590 struct workqueue_struct *wq;
591 };
592
593 /* NIC prio FTS */
594 enum {
595 MLX5E_VLAN_FT_LEVEL = 0,
596 MLX5E_L2_FT_LEVEL,
597 MLX5E_TTC_FT_LEVEL,
598 MLX5E_ARFS_FT_LEVEL
599 };
600
601 struct mlx5e_ethtool_table {
602 struct mlx5_flow_table *ft;
603 int num_rules;
604 };
605
606 #define ETHTOOL_NUM_L3_L4_FTS 7
607 #define ETHTOOL_NUM_L2_FTS 4
608
609 struct mlx5e_ethtool_steering {
610 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
611 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
612 struct list_head rules;
613 int tot_num_rules;
614 };
615
616 struct mlx5e_flow_steering {
617 struct mlx5_flow_namespace *ns;
618 struct mlx5e_ethtool_steering ethtool;
619 struct mlx5e_tc_table tc;
620 struct mlx5e_vlan_table vlan;
621 struct mlx5e_l2_table l2;
622 struct mlx5e_ttc_table ttc;
623 struct mlx5e_arfs_tables arfs;
624 };
625
626 struct mlx5e_rqt {
627 u32 rqtn;
628 bool enabled;
629 };
630
631 struct mlx5e_tir {
632 u32 tirn;
633 struct mlx5e_rqt rqt;
634 struct list_head list;
635 };
636
637 enum {
638 MLX5E_TC_PRIO = 0,
639 MLX5E_NIC_PRIO
640 };
641
642 struct mlx5e_profile {
643 void (*init)(struct mlx5_core_dev *mdev,
644 struct net_device *netdev,
645 const struct mlx5e_profile *profile, void *ppriv);
646 void (*cleanup)(struct mlx5e_priv *priv);
647 int (*init_rx)(struct mlx5e_priv *priv);
648 void (*cleanup_rx)(struct mlx5e_priv *priv);
649 int (*init_tx)(struct mlx5e_priv *priv);
650 void (*cleanup_tx)(struct mlx5e_priv *priv);
651 void (*enable)(struct mlx5e_priv *priv);
652 void (*disable)(struct mlx5e_priv *priv);
653 void (*update_stats)(struct mlx5e_priv *priv);
654 int (*max_nch)(struct mlx5_core_dev *mdev);
655 int max_tc;
656 };
657
658 struct mlx5e_priv {
659 /* priv data path fields - start */
660 struct mlx5e_sq **txq_to_sq_map;
661 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
662 struct bpf_prog *xdp_prog;
663 /* priv data path fields - end */
664
665 unsigned long state;
666 struct mutex state_lock; /* Protects Interface state */
667 struct mlx5_core_mkey umr_mkey;
668 struct mlx5e_rq drop_rq;
669
670 struct mlx5e_channel **channel;
671 u32 tisn[MLX5E_MAX_NUM_TC];
672 struct mlx5e_rqt indir_rqt;
673 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
674 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
675 u32 tx_rates[MLX5E_MAX_NUM_SQS];
676
677 struct mlx5e_flow_steering fs;
678 struct mlx5e_vxlan_db vxlan;
679
680 struct mlx5e_params params;
681 struct workqueue_struct *wq;
682 struct work_struct update_carrier_work;
683 struct work_struct set_rx_mode_work;
684 struct work_struct tx_timeout_work;
685 struct delayed_work update_stats_work;
686
687 u32 pflags;
688 struct mlx5_core_dev *mdev;
689 struct net_device *netdev;
690 struct mlx5e_stats stats;
691 struct mlx5e_tstamp tstamp;
692 u16 q_counter;
693 const struct mlx5e_profile *profile;
694 void *ppriv;
695 };
696
697 void mlx5e_build_ptys2ethtool_map(void);
698
699 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
700 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
701 void *accel_priv, select_queue_fallback_t fallback);
702 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
703
704 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
705 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
706 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
707 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
708 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
709 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
710
711 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
712 bool recycle);
713 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
714 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
715 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
716 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
717 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
718 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
719 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
720 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
721 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
722 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
723
724 void mlx5e_rx_am(struct mlx5e_rq *rq);
725 void mlx5e_rx_am_work(struct work_struct *work);
726 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
727
728 void mlx5e_update_stats(struct mlx5e_priv *priv);
729
730 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
731 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
732 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
733 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
734 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
735 int location);
736 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
737 struct ethtool_rxnfc *info, u32 *rule_locs);
738 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
739 struct ethtool_rx_flow_spec *fs);
740 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
741 int location);
742 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
743 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
744 void mlx5e_set_rx_mode_work(struct work_struct *work);
745
746 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
747 struct skb_shared_hwtstamps *hwts);
748 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
749 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
750 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
751 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
752 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
753
754 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
755 u16 vid);
756 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
757 u16 vid);
758 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
759 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
760
761 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
762
763 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
764 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
765
766 int mlx5e_open_locked(struct net_device *netdev);
767 int mlx5e_close_locked(struct net_device *netdev);
768 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
769 u32 *indirection_rqt, int len,
770 int num_channels);
771 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
772
773 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
774 u8 cq_period_mode);
775
776 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
777 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
778 {
779 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
780
781 /* ensure wqe is visible to device before updating doorbell record */
782 dma_wmb();
783
784 *sq->wq.db = cpu_to_be32(sq->pc);
785
786 /* ensure doorbell record is visible to device before ringing the
787 * doorbell
788 */
789 wmb();
790 if (bf_sz)
791 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
792 else
793 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
794 /* flush the write-combining mapped buffer */
795 wmb();
796
797 sq->bf_offset ^= sq->bf_buf_size;
798 }
799
800 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
801 {
802 struct mlx5_core_cq *mcq;
803
804 mcq = &cq->mcq;
805 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
806 }
807
808 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
809 {
810 return rq->mpwqe.mtt_offset +
811 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
812 }
813
814 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
815 {
816 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
817 MLX5E_MAX_NUM_CHANNELS);
818 }
819
820 extern const struct ethtool_ops mlx5e_ethtool_ops;
821 #ifdef CONFIG_MLX5_CORE_EN_DCB
822 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
823 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
824 #endif
825
826 #ifndef CONFIG_RFS_ACCEL
827 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
828 {
829 return 0;
830 }
831
832 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
833
834 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
835 {
836 return -ENOTSUPP;
837 }
838
839 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
840 {
841 return -ENOTSUPP;
842 }
843 #else
844 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
845 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
846 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
847 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
848 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
849 u16 rxq_index, u32 flow_id);
850 #endif
851
852 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
853 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
854 struct mlx5e_tir *tir, u32 *in, int inlen);
855 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
856 struct mlx5e_tir *tir);
857 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
858 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
859 int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev);
860
861 struct mlx5_eswitch_rep;
862 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
863 struct mlx5_eswitch_rep *rep);
864 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
865 struct mlx5_eswitch_rep *rep);
866 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
867 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
868 struct mlx5_eswitch_rep *rep);
869 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
870 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
871 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
872
873 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
874 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
875 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
876 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
877 int mlx5e_create_tises(struct mlx5e_priv *priv);
878 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
879 int mlx5e_close(struct net_device *netdev);
880 int mlx5e_open(struct net_device *netdev);
881 void mlx5e_update_stats_work(struct work_struct *work);
882 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
883 const struct mlx5e_profile *profile,
884 void *ppriv);
885 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
886 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
887 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
888 struct rtnl_link_stats64 *
889 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
890
891 #endif /* __MLX5_EN_H__ */
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