drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include <net/switchdev.h>
  48 #include "wq.h"
  49 #include "mlx5_core.h"
  50 #include "en_stats.h"
  51
  52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  53
  54 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  55 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  56
  57 #define MLX5E_MAX_NUM_TC        8
  58
  59 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  60 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  61 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  62
  63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  66
  67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  70
  71 #define MLX5_RX_HEADROOM NET_SKB_PAD
  72
  73 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
  74         (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
  75 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
  76         max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
  77 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)       MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
  78 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
  79
  80 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  81 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  82                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  83 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  84 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  85                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  86
  87 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  88 #define MLX5E_REQUIRED_MTTS(wqes)               \
  89         (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  90 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
  91
  92 #define MLX5_UMR_ALIGN                          (2048)
  93 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (128)
  94
  95 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  96 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
  97 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
  98
  99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
 100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
 101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
 102 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
 103 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
 104 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
 105 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
 106
 107 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 108 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 109 #define MLX5E_MIN_NUM_CHANNELS         0x1
 110 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 111 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 112 #define MLX5E_TX_CQ_POLL_BUDGET        128
 113 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 114
 115 #define MLX5E_ICOSQ_MAX_WQEBBS \
 116         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 117
 118 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 119 #define MLX5E_XDP_TX_DS_COUNT \
 120         ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 121
 122 #define MLX5E_NUM_MAIN_GROUPS 9
 123
 124 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 125 {
 126         switch (wq_type) {
 127         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 128                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 129                              wq_size / 2);
 130         default:
 131                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 132                              wq_size / 2);
 133         }
 134 }
 135
 136 static inline int mlx5_min_log_rq_size(int wq_type)
 137 {
 138         switch (wq_type) {
 139         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 140                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 141         default:
 142                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 143         }
 144 }
 145
 146 static inline int mlx5_max_log_rq_size(int wq_type)
 147 {
 148         switch (wq_type) {
 149         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 150                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 151         default:
 152                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 153         }
 154 }
 155
 156 struct mlx5e_tx_wqe {
 157         struct mlx5_wqe_ctrl_seg ctrl;
 158         struct mlx5_wqe_eth_seg  eth;
 159 };
 160
 161 struct mlx5e_rx_wqe {
 162         struct mlx5_wqe_srq_next_seg  next;
 163         struct mlx5_wqe_data_seg      data;
 164 };
 165
 166 struct mlx5e_umr_wqe {
 167         struct mlx5_wqe_ctrl_seg       ctrl;
 168         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 169         struct mlx5_mkey_seg           mkc;
 170         struct mlx5_wqe_data_seg       data;
 171 };
 172
 173 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
 174
 175 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 176         "rx_cqe_moder",
 177         "rx_cqe_compress",
 178 };
 179
 180 enum mlx5e_priv_flag {
 181         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 182         MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
 183 };
 184
 185 #define MLX5E_SET_PFLAG(priv, pflag, enable)                    \
 186         do {                                                    \
 187                 if (enable)                                     \
 188                         (priv)->params.pflags |= (pflag);       \
 189                 else                                            \
 190                         (priv)->params.pflags &= ~(pflag);      \
 191         } while (0)
 192
 193 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
 194
 195 #ifdef CONFIG_MLX5_CORE_EN_DCB
 196 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 197 #endif
 198
 199 struct mlx5e_cq_moder {
 200         u16 usec;
 201         u16 pkts;
 202 };
 203
 204 struct mlx5e_params {
 205         u8  log_sq_size;
 206         u8  rq_wq_type;
 207         u8  mpwqe_log_stride_sz;
 208         u8  mpwqe_log_num_strides;
 209         u8  log_rq_size;
 210         u16 num_channels;
 211         u8  num_tc;
 212         u8  rx_cq_period_mode;
 213         bool rx_cqe_compress_def;
 214         struct mlx5e_cq_moder rx_cq_moderation;
 215         struct mlx5e_cq_moder tx_cq_moderation;
 216         u16 min_rx_wqes;
 217         bool lro_en;
 218         u32 lro_wqe_sz;
 219         u16 tx_max_inline;
 220         u8  tx_min_inline_mode;
 221         u8  rss_hfunc;
 222         u8  toeplitz_hash_key[40];
 223         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 224         bool vlan_strip_disable;
 225         bool rx_am_enabled;
 226         u32 lro_timeout;
 227         u32 pflags;
 228 };
 229
 230 #ifdef CONFIG_MLX5_CORE_EN_DCB
 231 struct mlx5e_cee_config {
 232         /* bw pct for priority group */
 233         u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];
 234         u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];
 235         bool                       pfc_setting[CEE_DCBX_MAX_PRIO];
 236         bool                       pfc_enable;
 237 };
 238
 239 enum {
 240         MLX5_DCB_CHG_RESET,
 241         MLX5_DCB_NO_CHG,
 242         MLX5_DCB_CHG_NO_RESET,
 243 };
 244
 245 struct mlx5e_dcbx {
 246         enum mlx5_dcbx_oper_mode   mode;
 247         struct mlx5e_cee_config    cee_cfg; /* pending configuration */
 248
 249         /* The only setting that cannot be read from FW */
 250         u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];
 251 };
 252 #endif
 253
 254 struct mlx5e_tstamp {
 255         rwlock_t                   lock;
 256         struct cyclecounter        cycles;
 257         struct timecounter         clock;
 258         struct hwtstamp_config     hwtstamp_config;
 259         u32                        nominal_c_mult;
 260         unsigned long              overflow_period;
 261         struct delayed_work        overflow_work;
 262         struct mlx5_core_dev      *mdev;
 263         struct ptp_clock          *ptp;
 264         struct ptp_clock_info      ptp_info;
 265         u8                        *pps_pin_caps;
 266 };
 267
 268 enum {
 269         MLX5E_RQ_STATE_ENABLED,
 270         MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
 271         MLX5E_RQ_STATE_AM,
 272 };
 273
 274 struct mlx5e_cq {
 275         /* data path - accessed per cqe */
 276         struct mlx5_cqwq           wq;
 277
 278         /* data path - accessed per napi poll */
 279         u16                        event_ctr;
 280         struct napi_struct        *napi;
 281         struct mlx5_core_cq        mcq;
 282         struct mlx5e_channel      *channel;
 283         struct mlx5e_priv         *priv;
 284
 285         /* cqe decompression */
 286         struct mlx5_cqe64          title;
 287         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 288         u8                         mini_arr_idx;
 289         u16                        decmprs_left;
 290         u16                        decmprs_wqe_counter;
 291
 292         /* control */
 293         struct mlx5_frag_wq_ctrl   wq_ctrl;
 294 } ____cacheline_aligned_in_smp;
 295
 296 struct mlx5e_tx_wqe_info {
 297         u32 num_bytes;
 298         u8  num_wqebbs;
 299         u8  num_dma;
 300 };
 301
 302 enum mlx5e_dma_map_type {
 303         MLX5E_DMA_MAP_SINGLE,
 304         MLX5E_DMA_MAP_PAGE
 305 };
 306
 307 struct mlx5e_sq_dma {
 308         dma_addr_t              addr;
 309         u32                     size;
 310         enum mlx5e_dma_map_type type;
 311 };
 312
 313 enum {
 314         MLX5E_SQ_STATE_ENABLED,
 315 };
 316
 317 struct mlx5e_sq_wqe_info {
 318         u8  opcode;
 319         u8  num_wqebbs;
 320 };
 321
 322 struct mlx5e_txqsq {
 323         /* data path */
 324
 325         /* dirtied @completion */
 326         u16                        cc;
 327         u32                        dma_fifo_cc;
 328
 329         /* dirtied @xmit */
 330         u16                        pc ____cacheline_aligned_in_smp;
 331         u32                        dma_fifo_pc;
 332         struct mlx5e_sq_stats      stats;
 333
 334         struct mlx5e_cq            cq;
 335
 336         /* write@xmit, read@completion */
 337         struct {
 338                 struct sk_buff           **skb;
 339                 struct mlx5e_sq_dma       *dma_fifo;
 340                 struct mlx5e_tx_wqe_info  *wqe_info;
 341         } db;
 342
 343         /* read only */
 344         struct mlx5_wq_cyc         wq;
 345         u32                        dma_fifo_mask;
 346         void __iomem              *uar_map;
 347         struct netdev_queue       *txq;
 348         u32                        sqn;
 349         u16                        max_inline;
 350         u8                         min_inline_mode;
 351         u16                        edge;
 352         struct device             *pdev;
 353         struct mlx5e_tstamp       *tstamp;
 354         __be32                     mkey_be;
 355         unsigned long              state;
 356
 357         /* control path */
 358         struct mlx5_wq_ctrl        wq_ctrl;
 359         struct mlx5e_channel      *channel;
 360         int                        tc;
 361         u32                        rate_limit;
 362 } ____cacheline_aligned_in_smp;
 363
 364 struct mlx5e_xdpsq {
 365         /* data path */
 366
 367         /* dirtied @rx completion */
 368         u16                        cc;
 369         u16                        pc;
 370
 371         struct mlx5e_cq            cq;
 372
 373         /* write@xmit, read@completion */
 374         struct {
 375                 struct mlx5e_dma_info     *di;
 376                 bool                       doorbell;
 377         } db;
 378
 379         /* read only */
 380         struct mlx5_wq_cyc         wq;
 381         void __iomem              *uar_map;
 382         u32                        sqn;
 383         struct device             *pdev;
 384         __be32                     mkey_be;
 385         u8                         min_inline_mode;
 386         unsigned long              state;
 387
 388         /* control path */
 389         struct mlx5_wq_ctrl        wq_ctrl;
 390         struct mlx5e_channel      *channel;
 391 } ____cacheline_aligned_in_smp;
 392
 393 struct mlx5e_icosq {
 394         /* data path */
 395
 396         /* dirtied @completion */
 397         u16                        cc;
 398
 399         /* dirtied @xmit */
 400         u16                        pc ____cacheline_aligned_in_smp;
 401         u32                        dma_fifo_pc;
 402         u16                        prev_cc;
 403
 404         struct mlx5e_cq            cq;
 405
 406         /* write@xmit, read@completion */
 407         struct {
 408                 struct mlx5e_sq_wqe_info *ico_wqe;
 409         } db;
 410
 411         /* read only */
 412         struct mlx5_wq_cyc         wq;
 413         void __iomem              *uar_map;
 414         u32                        sqn;
 415         u16                        edge;
 416         struct device             *pdev;
 417         __be32                     mkey_be;
 418         unsigned long              state;
 419
 420         /* control path */
 421         struct mlx5_wq_ctrl        wq_ctrl;
 422         struct mlx5e_channel      *channel;
 423 } ____cacheline_aligned_in_smp;
 424
 425 static inline bool
 426 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
 427 {
 428         return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
 429 }
 430
 431 struct mlx5e_dma_info {
 432         struct page     *page;
 433         dma_addr_t      addr;
 434 };
 435
 436 struct mlx5e_umr_dma_info {
 437         __be64                *mtt;
 438         dma_addr_t             mtt_addr;
 439         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 440         struct mlx5e_umr_wqe   wqe;
 441 };
 442
 443 struct mlx5e_mpw_info {
 444         struct mlx5e_umr_dma_info umr;
 445         u16 consumed_strides;
 446         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 447 };
 448
 449 struct mlx5e_rx_am_stats {
 450         int ppms; /* packets per msec */
 451         int epms; /* events per msec */
 452 };
 453
 454 struct mlx5e_rx_am_sample {
 455         ktime_t         time;
 456         unsigned int    pkt_ctr;
 457         u16             event_ctr;
 458 };
 459
 460 struct mlx5e_rx_am { /* Adaptive Moderation */
 461         u8                                      state;
 462         struct mlx5e_rx_am_stats                prev_stats;
 463         struct mlx5e_rx_am_sample               start_sample;
 464         struct work_struct                      work;
 465         u8                                      profile_ix;
 466         u8                                      mode;
 467         u8                                      tune_state;
 468         u8                                      steps_right;
 469         u8                                      steps_left;
 470         u8                                      tired;
 471 };
 472
 473 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 474  * or a MPWQE (for striding rq).
 475  */
 476 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 477                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 478 #define MLX5E_CACHE_SIZE        (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 479 struct mlx5e_page_cache {
 480         u32 head;
 481         u32 tail;
 482         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 483 };
 484
 485 struct mlx5e_rq;
 486 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
 487 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16);
 488 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
 489
 490 struct mlx5e_rq {
 491         /* data path */
 492         struct mlx5_wq_ll      wq;
 493
 494         union {
 495                 struct mlx5e_dma_info *dma_info;
 496                 struct {
 497                         struct mlx5e_mpw_info *info;
 498                         void                  *mtt_no_align;
 499                 } mpwqe;
 500         };
 501         struct {
 502                 u8             page_order;
 503                 u32            wqe_sz;    /* wqe data buffer size */
 504                 u8             map_dir;   /* dma map direction */
 505         } buff;
 506         __be32                 mkey_be;
 507
 508         struct device         *pdev;
 509         struct net_device     *netdev;
 510         struct mlx5e_tstamp   *tstamp;
 511         struct mlx5e_rq_stats  stats;
 512         struct mlx5e_cq        cq;
 513         struct mlx5e_page_cache page_cache;
 514
 515         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 516         mlx5e_fp_alloc_wqe     alloc_wqe;
 517         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 518
 519         unsigned long          state;
 520         int                    ix;
 521         u16                    rx_headroom;
 522
 523         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 524
 525         /* XDP */
 526         struct bpf_prog       *xdp_prog;
 527         struct mlx5e_xdpsq     xdpsq;
 528
 529         /* control */
 530         struct mlx5_wq_ctrl    wq_ctrl;
 531         u8                     wq_type;
 532         u32                    mpwqe_stride_sz;
 533         u32                    mpwqe_num_strides;
 534         u32                    rqn;
 535         struct mlx5e_channel  *channel;
 536         struct mlx5e_priv     *priv;
 537         struct mlx5_core_mkey  umr_mkey;
 538 } ____cacheline_aligned_in_smp;
 539
 540 enum channel_flags {
 541         MLX5E_CHANNEL_NAPI_SCHED = 1,
 542 };
 543
 544 struct mlx5e_channel {
 545         /* data path */
 546         struct mlx5e_rq            rq;
 547         struct mlx5e_txqsq         sq[MLX5E_MAX_NUM_TC];
 548         struct mlx5e_icosq         icosq;   /* internal control operations */
 549         bool                       xdp;
 550         struct napi_struct         napi;
 551         struct device             *pdev;
 552         struct net_device         *netdev;
 553         __be32                     mkey_be;
 554         u8                         num_tc;
 555         unsigned long              flags;
 556
 557         /* control */
 558         struct mlx5e_priv         *priv;
 559         int                        ix;
 560         int                        cpu;
 561 };
 562
 563 struct mlx5e_channels {
 564         struct mlx5e_channel **c;
 565         unsigned int           num;
 566 };
 567
 568 enum mlx5e_traffic_types {
 569         MLX5E_TT_IPV4_TCP,
 570         MLX5E_TT_IPV6_TCP,
 571         MLX5E_TT_IPV4_UDP,
 572         MLX5E_TT_IPV6_UDP,
 573         MLX5E_TT_IPV4_IPSEC_AH,
 574         MLX5E_TT_IPV6_IPSEC_AH,
 575         MLX5E_TT_IPV4_IPSEC_ESP,
 576         MLX5E_TT_IPV6_IPSEC_ESP,
 577         MLX5E_TT_IPV4,
 578         MLX5E_TT_IPV6,
 579         MLX5E_TT_ANY,
 580         MLX5E_NUM_TT,
 581         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 582 };
 583
 584 enum {
 585         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 586         MLX5E_STATE_OPENED,
 587         MLX5E_STATE_DESTROYING,
 588 };
 589
 590 struct mlx5e_vxlan_db {
 591         spinlock_t                      lock; /* protect vxlan table */
 592         struct radix_tree_root          tree;
 593 };
 594
 595 struct mlx5e_l2_rule {
 596         u8  addr[ETH_ALEN + 2];
 597         struct mlx5_flow_handle *rule;
 598 };
 599
 600 struct mlx5e_flow_table {
 601         int num_groups;
 602         struct mlx5_flow_table *t;
 603         struct mlx5_flow_group **g;
 604 };
 605
 606 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 607
 608 struct mlx5e_tc_table {
 609         struct mlx5_flow_table          *t;
 610
 611         struct rhashtable_params        ht_params;
 612         struct rhashtable               ht;
 613 };
 614
 615 struct mlx5e_vlan_table {
 616         struct mlx5e_flow_table         ft;
 617         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 618         struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
 619         struct mlx5_flow_handle *untagged_rule;
 620         struct mlx5_flow_handle *any_cvlan_rule;
 621         struct mlx5_flow_handle *any_svlan_rule;
 622         bool                    filter_disabled;
 623 };
 624
 625 struct mlx5e_l2_table {
 626         struct mlx5e_flow_table    ft;
 627         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 628         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 629         struct mlx5e_l2_rule       broadcast;
 630         struct mlx5e_l2_rule       allmulti;
 631         struct mlx5e_l2_rule       promisc;
 632         bool                       broadcast_enabled;
 633         bool                       allmulti_enabled;
 634         bool                       promisc_enabled;
 635 };
 636
 637 /* L3/L4 traffic type classifier */
 638 struct mlx5e_ttc_table {
 639         struct mlx5e_flow_table  ft;
 640         struct mlx5_flow_handle  *rules[MLX5E_NUM_TT];
 641 };
 642
 643 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 644 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 645 struct arfs_table {
 646         struct mlx5e_flow_table  ft;
 647         struct mlx5_flow_handle  *default_rule;
 648         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 649 };
 650
 651 enum  arfs_type {
 652         ARFS_IPV4_TCP,
 653         ARFS_IPV6_TCP,
 654         ARFS_IPV4_UDP,
 655         ARFS_IPV6_UDP,
 656         ARFS_NUM_TYPES,
 657 };
 658
 659 struct mlx5e_arfs_tables {
 660         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 661         /* Protect aRFS rules list */
 662         spinlock_t                     arfs_lock;
 663         struct list_head               rules;
 664         int                            last_filter_id;
 665         struct workqueue_struct        *wq;
 666 };
 667
 668 /* NIC prio FTS */
 669 enum {
 670         MLX5E_VLAN_FT_LEVEL = 0,
 671         MLX5E_L2_FT_LEVEL,
 672         MLX5E_TTC_FT_LEVEL,
 673         MLX5E_ARFS_FT_LEVEL
 674 };
 675
 676 struct mlx5e_ethtool_table {
 677         struct mlx5_flow_table *ft;
 678         int                    num_rules;
 679 };
 680
 681 #define ETHTOOL_NUM_L3_L4_FTS 7
 682 #define ETHTOOL_NUM_L2_FTS 4
 683
 684 struct mlx5e_ethtool_steering {
 685         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 686         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 687         struct list_head                rules;
 688         int                             tot_num_rules;
 689 };
 690
 691 struct mlx5e_flow_steering {
 692         struct mlx5_flow_namespace      *ns;
 693         struct mlx5e_ethtool_steering   ethtool;
 694         struct mlx5e_tc_table           tc;
 695         struct mlx5e_vlan_table         vlan;
 696         struct mlx5e_l2_table           l2;
 697         struct mlx5e_ttc_table          ttc;
 698         struct mlx5e_arfs_tables        arfs;
 699 };
 700
 701 struct mlx5e_rqt {
 702         u32              rqtn;
 703         bool             enabled;
 704 };
 705
 706 struct mlx5e_tir {
 707         u32               tirn;
 708         struct mlx5e_rqt  rqt;
 709         struct list_head  list;
 710 };
 711
 712 enum {
 713         MLX5E_TC_PRIO = 0,
 714         MLX5E_NIC_PRIO
 715 };
 716
 717 struct mlx5e_profile {
 718         void    (*init)(struct mlx5_core_dev *mdev,
 719                         struct net_device *netdev,
 720                         const struct mlx5e_profile *profile, void *ppriv);
 721         void    (*cleanup)(struct mlx5e_priv *priv);
 722         int     (*init_rx)(struct mlx5e_priv *priv);
 723         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 724         int     (*init_tx)(struct mlx5e_priv *priv);
 725         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 726         void    (*enable)(struct mlx5e_priv *priv);
 727         void    (*disable)(struct mlx5e_priv *priv);
 728         void    (*update_stats)(struct mlx5e_priv *priv);
 729         int     (*max_nch)(struct mlx5_core_dev *mdev);
 730         int     max_tc;
 731 };
 732
 733 struct mlx5e_priv {
 734         /* priv data path fields - start */
 735         struct mlx5e_txqsq         **txq_to_sq_map;
 736         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 737         struct bpf_prog *xdp_prog;
 738         /* priv data path fields - end */
 739
 740         unsigned long              state;
 741         struct mutex               state_lock; /* Protects Interface state */
 742         struct mlx5e_rq            drop_rq;
 743
 744         struct mlx5e_channels      channels;
 745         u32                        tisn[MLX5E_MAX_NUM_TC];
 746         struct mlx5e_rqt           indir_rqt;
 747         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 748         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 749         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 750
 751         struct mlx5e_flow_steering fs;
 752         struct mlx5e_vxlan_db      vxlan;
 753
 754         struct mlx5e_params        params;
 755         struct workqueue_struct    *wq;
 756         struct work_struct         update_carrier_work;
 757         struct work_struct         set_rx_mode_work;
 758         struct work_struct         tx_timeout_work;
 759         struct delayed_work        update_stats_work;
 760
 761         struct mlx5_core_dev      *mdev;
 762         struct net_device         *netdev;
 763         struct mlx5e_stats         stats;
 764         struct mlx5e_tstamp        tstamp;
 765         u16 q_counter;
 766 #ifdef CONFIG_MLX5_CORE_EN_DCB
 767         struct mlx5e_dcbx          dcbx;
 768 #endif
 769
 770         const struct mlx5e_profile *profile;
 771         void                      *ppriv;
 772 };
 773
 774 void mlx5e_build_ptys2ethtool_map(void);
 775
 776 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 777                        void *accel_priv, select_queue_fallback_t fallback);
 778 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 779
 780 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 781 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 782 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 783 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 784 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 785 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
 786 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
 787 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
 788
 789 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 790                         bool recycle);
 791 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 792 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 793 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 794 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 795 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 796 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 797 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 798 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 799 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 800 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 801
 802 void mlx5e_rx_am(struct mlx5e_rq *rq);
 803 void mlx5e_rx_am_work(struct work_struct *work);
 804 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 805
 806 void mlx5e_update_stats(struct mlx5e_priv *priv);
 807
 808 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 809 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 810 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 811 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 812 int mlx5e_self_test_num(struct mlx5e_priv *priv);
 813 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
 814                      u64 *buf);
 815 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 816                            int location);
 817 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 818                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 819 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 820                                struct ethtool_rx_flow_spec *fs);
 821 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 822                               int location);
 823 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 824 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 825 void mlx5e_set_rx_mode_work(struct work_struct *work);
 826
 827 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 828                         struct skb_shared_hwtstamps *hwts);
 829 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 830 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 831 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
 832                              struct ptp_clock_event *event);
 833 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 834 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 835 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
 836
 837 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 838                           u16 vid);
 839 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 840                            u16 vid);
 841 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 842 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 843
 844 int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd);
 845
 846 struct mlx5e_redirect_rqt_param {
 847         bool is_rss;
 848         union {
 849                 u32 rqn; /* Direct RQN (Non-RSS) */
 850                 struct {
 851                         u8 hfunc;
 852                         struct mlx5e_channels *channels;
 853                 } rss; /* RSS data */
 854         };
 855 };
 856
 857 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
 858                        struct mlx5e_redirect_rqt_param rrp);
 859 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
 860                                     enum mlx5e_traffic_types tt);
 861
 862 int mlx5e_open_locked(struct net_device *netdev);
 863 int mlx5e_close_locked(struct net_device *netdev);
 864 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 865                                    u32 *indirection_rqt, int len,
 866                                    int num_channels);
 867 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 868
 869 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 870                                  u8 cq_period_mode);
 871 void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type);
 872
 873 static inline
 874 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
 875 {
 876         u16                         pi   = *pc & wq->sz_m1;
 877         struct mlx5e_tx_wqe        *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 878         struct mlx5_wqe_ctrl_seg   *cseg = &wqe->ctrl;
 879
 880         memset(cseg, 0, sizeof(*cseg));
 881
 882         cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
 883         cseg->qpn_ds           = cpu_to_be32((sqn << 8) | 0x01);
 884
 885         (*pc)++;
 886
 887         return wqe;
 888 }
 889
 890 static inline
 891 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
 892                      void __iomem *uar_map,
 893                      struct mlx5_wqe_ctrl_seg *ctrl)
 894 {
 895         ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
 896         /* ensure wqe is visible to device before updating doorbell record */
 897         dma_wmb();
 898
 899         *wq->db = cpu_to_be32(pc);
 900
 901         /* ensure doorbell record is visible to device before ringing the
 902          * doorbell
 903          */
 904         wmb();
 905
 906         mlx5_write64((__be32 *)ctrl, uar_map, NULL);
 907 }
 908
 909 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 910 {
 911         struct mlx5_core_cq *mcq;
 912
 913         mcq = &cq->mcq;
 914         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 915 }
 916
 917 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 918 {
 919         return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 920 }
 921
 922 extern const struct ethtool_ops mlx5e_ethtool_ops;
 923 #ifdef CONFIG_MLX5_CORE_EN_DCB
 924 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 925 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 926 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
 927 #endif
 928
 929 #ifndef CONFIG_RFS_ACCEL
 930 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
 931 {
 932         return 0;
 933 }
 934
 935 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
 936
 937 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
 938 {
 939         return -EOPNOTSUPP;
 940 }
 941
 942 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
 943 {
 944         return -EOPNOTSUPP;
 945 }
 946 #else
 947 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
 948 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
 949 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
 950 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
 951 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
 952                         u16 rxq_index, u32 flow_id);
 953 #endif
 954
 955 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 956 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
 957                      struct mlx5e_tir *tir, u32 *in, int inlen);
 958 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
 959                        struct mlx5e_tir *tir);
 960 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
 961 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
 962 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
 963                                      bool enable_uc_lb);
 964
 965 struct mlx5_eswitch_rep;
 966 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
 967                          struct mlx5_eswitch_rep *rep);
 968 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
 969                             struct mlx5_eswitch_rep *rep);
 970 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
 971 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
 972                           struct mlx5_eswitch_rep *rep);
 973 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
 974 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
 975 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
 976 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 977 void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv);
 978
 979 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
 980 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
 981 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
 982 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
 983 int mlx5e_create_tises(struct mlx5e_priv *priv);
 984 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
 985 int mlx5e_close(struct net_device *netdev);
 986 int mlx5e_open(struct net_device *netdev);
 987 void mlx5e_update_stats_work(struct work_struct *work);
 988 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
 989                                        const struct mlx5e_profile *profile,
 990                                        void *ppriv);
 991 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
 992 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 993 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 994 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
 995
 996 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
 997                             void *sp);
 998 bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id);
 999
1000 bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv);
1001 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv);
1002 #endif /* __MLX5_EN_H__ */