drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/crash_dump.h>
  41 #include <linux/mlx5/driver.h>
  42 #include <linux/mlx5/qp.h>
  43 #include <linux/mlx5/cq.h>
  44 #include <linux/mlx5/port.h>
  45 #include <linux/mlx5/vport.h>
  46 #include <linux/mlx5/transobj.h>
  47 #include <linux/rhashtable.h>
  48 #include <net/switchdev.h>
  49 #include "wq.h"
  50 #include "mlx5_core.h"
  51 #include "en_stats.h"
  52
  53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  54
  55 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
  56
  57 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
  58 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
  59
  60 #define MLX5E_MAX_DSCP          64
  61 #define MLX5E_MAX_NUM_TC        8
  62
  63 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  64 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  65 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  66
  67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  70
  71 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x2
  72 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  73 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  74
  75 #define MLX5_RX_HEADROOM NET_SKB_PAD
  76 #define MLX5_SKB_FRAG_SZ(len)   (SKB_DATA_ALIGN(len) +  \
  77                                  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
  78
  79 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
  80         (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
  81 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
  82         max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
  83 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)       MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
  84 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
  85 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
  86         (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
  87         MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
  88
  89 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  90 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  91                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  92 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  93 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  94                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  95
  96 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  97 #define MLX5E_REQUIRED_MTTS(wqes)               \
  98         (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  99 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
 100
 101 #define MLX5_UMR_ALIGN                          (2048)
 102 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (256)
 103
 104 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
 105 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
 106 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
 107
 108 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
 109 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
 110 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
 111 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
 112 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
 113 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
 114 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
 115 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
 116
 117 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 118 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 119 #define MLX5E_MIN_NUM_CHANNELS         0x1
 120 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 121 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 122 #define MLX5E_TX_CQ_POLL_BUDGET        128
 123 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 124
 125 #define MLX5E_ICOSQ_MAX_WQEBBS \
 126         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 127
 128 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 129 #define MLX5E_XDP_TX_DS_COUNT \
 130         ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 131
 132 #define MLX5E_NUM_MAIN_GROUPS 9
 133
 134 #define MLX5E_MSG_LEVEL                 NETIF_MSG_LINK
 135
 136 #define mlx5e_dbg(mlevel, priv, format, ...)                    \
 137 do {                                                            \
 138         if (NETIF_MSG_##mlevel & (priv)->msglevel)              \
 139                 netdev_warn(priv->netdev, format,               \
 140                             ##__VA_ARGS__);                     \
 141 } while (0)
 142
 143
 144 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 145 {
 146         switch (wq_type) {
 147         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 148                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 149                              wq_size / 2);
 150         default:
 151                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 152                              wq_size / 2);
 153         }
 154 }
 155
 156 static inline int mlx5_min_log_rq_size(int wq_type)
 157 {
 158         switch (wq_type) {
 159         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 160                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 161         default:
 162                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 163         }
 164 }
 165
 166 static inline int mlx5_max_log_rq_size(int wq_type)
 167 {
 168         switch (wq_type) {
 169         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 170                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 171         default:
 172                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 173         }
 174 }
 175
 176 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 177 {
 178         return is_kdump_kernel() ?
 179                 MLX5E_MIN_NUM_CHANNELS :
 180                 min_t(int, mdev->priv.eq_table.num_comp_vectors,
 181                       MLX5E_MAX_NUM_CHANNELS);
 182 }
 183
 184 struct mlx5e_tx_wqe {
 185         struct mlx5_wqe_ctrl_seg ctrl;
 186         struct mlx5_wqe_eth_seg  eth;
 187 };
 188
 189 struct mlx5e_rx_wqe {
 190         struct mlx5_wqe_srq_next_seg  next;
 191         struct mlx5_wqe_data_seg      data;
 192 };
 193
 194 struct mlx5e_umr_wqe {
 195         struct mlx5_wqe_ctrl_seg       ctrl;
 196         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 197         struct mlx5_mkey_seg           mkc;
 198         struct mlx5_wqe_data_seg       data;
 199 };
 200
 201 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
 202
 203 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 204         "rx_cqe_moder",
 205         "tx_cqe_moder",
 206         "rx_cqe_compress",
 207 };
 208
 209 enum mlx5e_priv_flag {
 210         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 211         MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1),
 212         MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2),
 213 };
 214
 215 #define MLX5E_SET_PFLAG(params, pflag, enable)                  \
 216         do {                                                    \
 217                 if (enable)                                     \
 218                         (params)->pflags |= (pflag);            \
 219                 else                                            \
 220                         (params)->pflags &= ~(pflag);           \
 221         } while (0)
 222
 223 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
 224
 225 #ifdef CONFIG_MLX5_CORE_EN_DCB
 226 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 227 #endif
 228
 229 struct mlx5e_cq_moder {
 230         u16 usec;
 231         u16 pkts;
 232         u8 cq_period_mode;
 233 };
 234
 235 struct mlx5e_params {
 236         u8  log_sq_size;
 237         u8  rq_wq_type;
 238         u16 rq_headroom;
 239         u8  mpwqe_log_stride_sz;
 240         u8  mpwqe_log_num_strides;
 241         u8  log_rq_size;
 242         u16 num_channels;
 243         u8  num_tc;
 244         bool rx_cqe_compress_def;
 245         struct mlx5e_cq_moder rx_cq_moderation;
 246         struct mlx5e_cq_moder tx_cq_moderation;
 247         bool lro_en;
 248         u32 lro_wqe_sz;
 249         u16 tx_max_inline;
 250         u8  tx_min_inline_mode;
 251         u8  rss_hfunc;
 252         u8  toeplitz_hash_key[40];
 253         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 254         bool vlan_strip_disable;
 255         bool scatter_fcs_en;
 256         bool rx_am_enabled;
 257         u32 lro_timeout;
 258         u32 pflags;
 259         struct bpf_prog *xdp_prog;
 260 };
 261
 262 #ifdef CONFIG_MLX5_CORE_EN_DCB
 263 struct mlx5e_cee_config {
 264         /* bw pct for priority group */
 265         u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];
 266         u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];
 267         bool                       pfc_setting[CEE_DCBX_MAX_PRIO];
 268         bool                       pfc_enable;
 269 };
 270
 271 enum {
 272         MLX5_DCB_CHG_RESET,
 273         MLX5_DCB_NO_CHG,
 274         MLX5_DCB_CHG_NO_RESET,
 275 };
 276
 277 struct mlx5e_dcbx {
 278         enum mlx5_dcbx_oper_mode   mode;
 279         struct mlx5e_cee_config    cee_cfg; /* pending configuration */
 280         u8                         dscp_app_cnt;
 281
 282         /* The only setting that cannot be read from FW */
 283         u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];
 284         u8                         cap;
 285 };
 286
 287 struct mlx5e_dcbx_dp {
 288         u8                         dscp2prio[MLX5E_MAX_DSCP];
 289         u8                         trust_state;
 290 };
 291 #endif
 292
 293 enum {
 294         MLX5E_RQ_STATE_ENABLED,
 295         MLX5E_RQ_STATE_AM,
 296 };
 297
 298 #define MLX5E_TEST_BIT(state, nr) (state & BIT(nr))
 299
 300 struct mlx5e_cq {
 301         /* data path - accessed per cqe */
 302         struct mlx5_cqwq           wq;
 303
 304         /* data path - accessed per napi poll */
 305         u16                        event_ctr;
 306         struct napi_struct        *napi;
 307         struct mlx5_core_cq        mcq;
 308         struct mlx5e_channel      *channel;
 309
 310         /* cqe decompression */
 311         struct mlx5_cqe64          title;
 312         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 313         u8                         mini_arr_idx;
 314         u16                        decmprs_left;
 315         u16                        decmprs_wqe_counter;
 316
 317         /* control */
 318         struct mlx5_core_dev      *mdev;
 319         struct mlx5_frag_wq_ctrl   wq_ctrl;
 320 } ____cacheline_aligned_in_smp;
 321
 322 struct mlx5e_tx_wqe_info {
 323         struct sk_buff *skb;
 324         u32 num_bytes;
 325         u8  num_wqebbs;
 326         u8  num_dma;
 327 };
 328
 329 enum mlx5e_dma_map_type {
 330         MLX5E_DMA_MAP_SINGLE,
 331         MLX5E_DMA_MAP_PAGE
 332 };
 333
 334 struct mlx5e_sq_dma {
 335         dma_addr_t              addr;
 336         u32                     size;
 337         enum mlx5e_dma_map_type type;
 338 };
 339
 340 enum {
 341         MLX5E_SQ_STATE_ENABLED,
 342         MLX5E_SQ_STATE_IPSEC,
 343 };
 344
 345 struct mlx5e_sq_wqe_info {
 346         u8  opcode;
 347 };
 348
 349 struct mlx5e_txqsq {
 350         /* data path */
 351
 352         /* dirtied @completion */
 353         u16                        cc;
 354         u32                        dma_fifo_cc;
 355
 356         /* dirtied @xmit */
 357         u16                        pc ____cacheline_aligned_in_smp;
 358         u32                        dma_fifo_pc;
 359         struct mlx5e_sq_stats      stats;
 360
 361         struct mlx5e_cq            cq;
 362
 363         /* write@xmit, read@completion */
 364         struct {
 365                 struct mlx5e_sq_dma       *dma_fifo;
 366                 struct mlx5e_tx_wqe_info  *wqe_info;
 367         } db;
 368
 369         /* read only */
 370         struct mlx5_wq_cyc         wq;
 371         u32                        dma_fifo_mask;
 372         void __iomem              *uar_map;
 373         struct netdev_queue       *txq;
 374         u32                        sqn;
 375         u16                        max_inline;
 376         u8                         min_inline_mode;
 377         u16                        edge;
 378         struct device             *pdev;
 379         __be32                     mkey_be;
 380         unsigned long              state;
 381         struct hwtstamp_config    *tstamp;
 382         struct mlx5_clock         *clock;
 383
 384         /* control path */
 385         struct mlx5_wq_ctrl        wq_ctrl;
 386         struct mlx5e_channel      *channel;
 387         int                        txq_ix;
 388         u32                        rate_limit;
 389 } ____cacheline_aligned_in_smp;
 390
 391 struct mlx5e_xdpsq {
 392         /* data path */
 393
 394         /* dirtied @rx completion */
 395         u16                        cc;
 396         u16                        pc;
 397
 398         struct mlx5e_cq            cq;
 399
 400         /* write@xmit, read@completion */
 401         struct {
 402                 struct mlx5e_dma_info     *di;
 403                 bool                       doorbell;
 404         } db;
 405
 406         /* read only */
 407         struct mlx5_wq_cyc         wq;
 408         void __iomem              *uar_map;
 409         u32                        sqn;
 410         struct device             *pdev;
 411         __be32                     mkey_be;
 412         u8                         min_inline_mode;
 413         unsigned long              state;
 414
 415         /* control path */
 416         struct mlx5_wq_ctrl        wq_ctrl;
 417         struct mlx5e_channel      *channel;
 418 } ____cacheline_aligned_in_smp;
 419
 420 struct mlx5e_icosq {
 421         /* data path */
 422
 423         /* dirtied @xmit */
 424         u16                        pc ____cacheline_aligned_in_smp;
 425
 426         struct mlx5e_cq            cq;
 427
 428         /* write@xmit, read@completion */
 429         struct {
 430                 struct mlx5e_sq_wqe_info *ico_wqe;
 431         } db;
 432
 433         /* read only */
 434         struct mlx5_wq_cyc         wq;
 435         void __iomem              *uar_map;
 436         u32                        sqn;
 437         u16                        edge;
 438         __be32                     mkey_be;
 439         unsigned long              state;
 440
 441         /* control path */
 442         struct mlx5_wq_ctrl        wq_ctrl;
 443         struct mlx5e_channel      *channel;
 444 } ____cacheline_aligned_in_smp;
 445
 446 static inline bool
 447 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
 448 {
 449         return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
 450 }
 451
 452 struct mlx5e_dma_info {
 453         struct page     *page;
 454         dma_addr_t      addr;
 455 };
 456
 457 struct mlx5e_wqe_frag_info {
 458         struct mlx5e_dma_info di;
 459         u32 offset;
 460 };
 461
 462 struct mlx5e_umr_dma_info {
 463         __be64                *mtt;
 464         dma_addr_t             mtt_addr;
 465         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 466         struct mlx5e_umr_wqe   wqe;
 467 };
 468
 469 struct mlx5e_mpw_info {
 470         struct mlx5e_umr_dma_info umr;
 471         u16 consumed_strides;
 472         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 473 };
 474
 475 struct mlx5e_rx_am_stats {
 476         int ppms; /* packets per msec */
 477         int bpms; /* bytes per msec */
 478         int epms; /* events per msec */
 479 };
 480
 481 struct mlx5e_rx_am_sample {
 482         ktime_t time;
 483         u32     pkt_ctr;
 484         u32     byte_ctr;
 485         u16     event_ctr;
 486 };
 487
 488 struct mlx5e_rx_am { /* Adaptive Moderation */
 489         u8                                      state;
 490         struct mlx5e_rx_am_stats                prev_stats;
 491         struct mlx5e_rx_am_sample               start_sample;
 492         struct work_struct                      work;
 493         u8                                      profile_ix;
 494         u8                                      mode;
 495         u8                                      tune_state;
 496         u8                                      steps_right;
 497         u8                                      steps_left;
 498         u8                                      tired;
 499 };
 500
 501 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 502  * or a MPWQE (for striding rq).
 503  */
 504 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 505                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 506 #define MLX5E_CACHE_SIZE        (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 507 struct mlx5e_page_cache {
 508         u32 head;
 509         u32 tail;
 510         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 511 };
 512
 513 struct mlx5e_rq;
 514 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
 515 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
 516 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
 517
 518 struct mlx5e_rq {
 519         /* data path */
 520         struct mlx5_wq_ll      wq;
 521
 522         union {
 523                 struct {
 524                         struct mlx5e_wqe_frag_info *frag_info;
 525                         u32 frag_sz;    /* max possible skb frag_sz */
 526                         union {
 527                                 bool page_reuse;
 528                                 bool xdp_xmit;
 529                         };
 530                 } wqe;
 531                 struct {
 532                         struct mlx5e_mpw_info *info;
 533                         void                  *mtt_no_align;
 534                         u16                    num_strides;
 535                         u8                     log_stride_sz;
 536                         bool                   umr_in_progress;
 537                 } mpwqe;
 538         };
 539         struct {
 540                 u16            headroom;
 541                 u8             page_order;
 542                 u8             map_dir;   /* dma map direction */
 543         } buff;
 544
 545         struct mlx5e_channel  *channel;
 546         struct device         *pdev;
 547         struct net_device     *netdev;
 548         struct mlx5e_rq_stats  stats;
 549         struct mlx5e_cq        cq;
 550         struct mlx5e_page_cache page_cache;
 551         struct hwtstamp_config *tstamp;
 552         struct mlx5_clock      *clock;
 553
 554         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 555         mlx5e_fp_post_rx_wqes  post_wqes;
 556         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 557
 558         unsigned long          state;
 559         int                    ix;
 560
 561         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 562
 563         /* XDP */
 564         struct bpf_prog       *xdp_prog;
 565         struct mlx5e_xdpsq     xdpsq;
 566
 567         /* control */
 568         struct mlx5_wq_ctrl    wq_ctrl;
 569         __be32                 mkey_be;
 570         u8                     wq_type;
 571         u32                    rqn;
 572         struct mlx5_core_dev  *mdev;
 573         struct mlx5_core_mkey  umr_mkey;
 574 } ____cacheline_aligned_in_smp;
 575
 576 struct mlx5e_channel {
 577         /* data path */
 578         struct mlx5e_rq            rq;
 579         struct mlx5e_txqsq         sq[MLX5E_MAX_NUM_TC];
 580         struct mlx5e_icosq         icosq;   /* internal control operations */
 581         bool                       xdp;
 582         struct napi_struct         napi;
 583         struct device             *pdev;
 584         struct net_device         *netdev;
 585         __be32                     mkey_be;
 586         u8                         num_tc;
 587
 588         /* data path - accessed per napi poll */
 589         struct irq_desc *irq_desc;
 590
 591         /* control */
 592         struct mlx5e_priv         *priv;
 593         struct mlx5_core_dev      *mdev;
 594         struct hwtstamp_config    *tstamp;
 595         int                        ix;
 596         int                        cpu;
 597 };
 598
 599 struct mlx5e_channels {
 600         struct mlx5e_channel **c;
 601         unsigned int           num;
 602         struct mlx5e_params    params;
 603 };
 604
 605 enum mlx5e_traffic_types {
 606         MLX5E_TT_IPV4_TCP,
 607         MLX5E_TT_IPV6_TCP,
 608         MLX5E_TT_IPV4_UDP,
 609         MLX5E_TT_IPV6_UDP,
 610         MLX5E_TT_IPV4_IPSEC_AH,
 611         MLX5E_TT_IPV6_IPSEC_AH,
 612         MLX5E_TT_IPV4_IPSEC_ESP,
 613         MLX5E_TT_IPV6_IPSEC_ESP,
 614         MLX5E_TT_IPV4,
 615         MLX5E_TT_IPV6,
 616         MLX5E_TT_ANY,
 617         MLX5E_NUM_TT,
 618         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 619 };
 620
 621 enum mlx5e_tunnel_types {
 622         MLX5E_TT_IPV4_GRE,
 623         MLX5E_TT_IPV6_GRE,
 624         MLX5E_NUM_TUNNEL_TT,
 625 };
 626
 627 enum {
 628         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 629         MLX5E_STATE_OPENED,
 630         MLX5E_STATE_DESTROYING,
 631 };
 632
 633 struct mlx5e_vxlan_db {
 634         spinlock_t                      lock; /* protect vxlan table */
 635         struct radix_tree_root          tree;
 636 };
 637
 638 struct mlx5e_l2_rule {
 639         u8  addr[ETH_ALEN + 2];
 640         struct mlx5_flow_handle *rule;
 641 };
 642
 643 struct mlx5e_flow_table {
 644         int num_groups;
 645         struct mlx5_flow_table *t;
 646         struct mlx5_flow_group **g;
 647 };
 648
 649 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 650
 651 struct mlx5e_tc_table {
 652         struct mlx5_flow_table          *t;
 653
 654         struct rhashtable_params        ht_params;
 655         struct rhashtable               ht;
 656
 657         DECLARE_HASHTABLE(mod_hdr_tbl, 8);
 658 };
 659
 660 struct mlx5e_vlan_table {
 661         struct mlx5e_flow_table         ft;
 662         DECLARE_BITMAP(active_cvlans, VLAN_N_VID);
 663         DECLARE_BITMAP(active_svlans, VLAN_N_VID);
 664         struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID];
 665         struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID];
 666         struct mlx5_flow_handle *untagged_rule;
 667         struct mlx5_flow_handle *any_cvlan_rule;
 668         struct mlx5_flow_handle *any_svlan_rule;
 669         bool                    cvlan_filter_disabled;
 670 };
 671
 672 struct mlx5e_l2_table {
 673         struct mlx5e_flow_table    ft;
 674         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 675         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 676         struct mlx5e_l2_rule       broadcast;
 677         struct mlx5e_l2_rule       allmulti;
 678         struct mlx5e_l2_rule       promisc;
 679         bool                       broadcast_enabled;
 680         bool                       allmulti_enabled;
 681         bool                       promisc_enabled;
 682 };
 683
 684 /* L3/L4 traffic type classifier */
 685 struct mlx5e_ttc_table {
 686         struct mlx5e_flow_table  ft;
 687         struct mlx5_flow_handle  *rules[MLX5E_NUM_TT];
 688         struct mlx5_flow_handle  *tunnel_rules[MLX5E_NUM_TUNNEL_TT];
 689 };
 690
 691 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 692 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 693 struct arfs_table {
 694         struct mlx5e_flow_table  ft;
 695         struct mlx5_flow_handle  *default_rule;
 696         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 697 };
 698
 699 enum  arfs_type {
 700         ARFS_IPV4_TCP,
 701         ARFS_IPV6_TCP,
 702         ARFS_IPV4_UDP,
 703         ARFS_IPV6_UDP,
 704         ARFS_NUM_TYPES,
 705 };
 706
 707 struct mlx5e_arfs_tables {
 708         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 709         /* Protect aRFS rules list */
 710         spinlock_t                     arfs_lock;
 711         struct list_head               rules;
 712         int                            last_filter_id;
 713         struct workqueue_struct        *wq;
 714 };
 715
 716 /* NIC prio FTS */
 717 enum {
 718         MLX5E_VLAN_FT_LEVEL = 0,
 719         MLX5E_L2_FT_LEVEL,
 720         MLX5E_TTC_FT_LEVEL,
 721         MLX5E_INNER_TTC_FT_LEVEL,
 722         MLX5E_ARFS_FT_LEVEL
 723 };
 724
 725 struct mlx5e_ethtool_table {
 726         struct mlx5_flow_table *ft;
 727         int                    num_rules;
 728 };
 729
 730 #define ETHTOOL_NUM_L3_L4_FTS 7
 731 #define ETHTOOL_NUM_L2_FTS 4
 732
 733 struct mlx5e_ethtool_steering {
 734         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 735         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 736         struct list_head                rules;
 737         int                             tot_num_rules;
 738 };
 739
 740 struct mlx5e_flow_steering {
 741         struct mlx5_flow_namespace      *ns;
 742         struct mlx5e_ethtool_steering   ethtool;
 743         struct mlx5e_tc_table           tc;
 744         struct mlx5e_vlan_table         vlan;
 745         struct mlx5e_l2_table           l2;
 746         struct mlx5e_ttc_table          ttc;
 747         struct mlx5e_ttc_table          inner_ttc;
 748         struct mlx5e_arfs_tables        arfs;
 749 };
 750
 751 struct mlx5e_rqt {
 752         u32              rqtn;
 753         bool             enabled;
 754 };
 755
 756 struct mlx5e_tir {
 757         u32               tirn;
 758         struct mlx5e_rqt  rqt;
 759         struct list_head  list;
 760 };
 761
 762 enum {
 763         MLX5E_TC_PRIO = 0,
 764         MLX5E_NIC_PRIO
 765 };
 766
 767 struct mlx5e_priv {
 768         /* priv data path fields - start */
 769         struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
 770         int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 771 #ifdef CONFIG_MLX5_CORE_EN_DCB
 772         struct mlx5e_dcbx_dp       dcbx_dp;
 773 #endif
 774         /* priv data path fields - end */
 775
 776         u32                        msglevel;
 777         unsigned long              state;
 778         struct mutex               state_lock; /* Protects Interface state */
 779         struct mlx5e_rq            drop_rq;
 780
 781         struct mlx5e_channels      channels;
 782         u32                        tisn[MLX5E_MAX_NUM_TC];
 783         struct mlx5e_rqt           indir_rqt;
 784         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 785         struct mlx5e_tir           inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
 786         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 787         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 788         int                        hard_mtu;
 789
 790         struct mlx5e_flow_steering fs;
 791         struct mlx5e_vxlan_db      vxlan;
 792
 793         struct workqueue_struct    *wq;
 794         struct work_struct         update_carrier_work;
 795         struct work_struct         set_rx_mode_work;
 796         struct work_struct         tx_timeout_work;
 797         struct delayed_work        update_stats_work;
 798
 799         struct mlx5_core_dev      *mdev;
 800         struct net_device         *netdev;
 801         struct mlx5e_stats         stats;
 802         struct hwtstamp_config     tstamp;
 803         u16 q_counter;
 804 #ifdef CONFIG_MLX5_CORE_EN_DCB
 805         struct mlx5e_dcbx          dcbx;
 806 #endif
 807
 808         const struct mlx5e_profile *profile;
 809         void                      *ppriv;
 810 #ifdef CONFIG_MLX5_EN_IPSEC
 811         struct mlx5e_ipsec        *ipsec;
 812 #endif
 813 };
 814
 815 struct mlx5e_profile {
 816         void    (*init)(struct mlx5_core_dev *mdev,
 817                         struct net_device *netdev,
 818                         const struct mlx5e_profile *profile, void *ppriv);
 819         void    (*cleanup)(struct mlx5e_priv *priv);
 820         int     (*init_rx)(struct mlx5e_priv *priv);
 821         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 822         int     (*init_tx)(struct mlx5e_priv *priv);
 823         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 824         void    (*enable)(struct mlx5e_priv *priv);
 825         void    (*disable)(struct mlx5e_priv *priv);
 826         void    (*update_stats)(struct mlx5e_priv *priv);
 827         void    (*update_carrier)(struct mlx5e_priv *priv);
 828         int     (*max_nch)(struct mlx5_core_dev *mdev);
 829         struct {
 830                 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 831                 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
 832         } rx_handlers;
 833         void    (*netdev_registered_init)(struct mlx5e_priv *priv);
 834         void    (*netdev_registered_remove)(struct mlx5e_priv *priv);
 835         int     max_tc;
 836 };
 837
 838 void mlx5e_build_ptys2ethtool_map(void);
 839
 840 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 841                        void *accel_priv, select_queue_fallback_t fallback);
 842 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 843
 844 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 845 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 846 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 847 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 848 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 849 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
 850 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
 851 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
 852
 853 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 854                         bool recycle);
 855 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 856 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 857 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 858 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
 859 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 860 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 861 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 862
 863 void mlx5e_rx_am(struct mlx5e_rq *rq);
 864 void mlx5e_rx_am_work(struct work_struct *work);
 865 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 866
 867 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full);
 868
 869 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 870 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 871 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 872 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 873 int mlx5e_self_test_num(struct mlx5e_priv *priv);
 874 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
 875                      u64 *buf);
 876 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 877                            int location);
 878 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 879                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 880 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 881                                struct ethtool_rx_flow_spec *fs);
 882 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 883                               int location);
 884 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 885 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 886 void mlx5e_set_rx_mode_work(struct work_struct *work);
 887
 888 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
 889 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
 890 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
 891
 892 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 893                           u16 vid);
 894 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 895                            u16 vid);
 896 void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv);
 897 void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv);
 898 void mlx5e_timestamp_set(struct mlx5e_priv *priv);
 899
 900 struct mlx5e_redirect_rqt_param {
 901         bool is_rss;
 902         union {
 903                 u32 rqn; /* Direct RQN (Non-RSS) */
 904                 struct {
 905                         u8 hfunc;
 906                         struct mlx5e_channels *channels;
 907                 } rss; /* RSS data */
 908         };
 909 };
 910
 911 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
 912                        struct mlx5e_redirect_rqt_param rrp);
 913 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
 914                                     enum mlx5e_traffic_types tt,
 915                                     void *tirc, bool inner);
 916
 917 int mlx5e_open_locked(struct net_device *netdev);
 918 int mlx5e_close_locked(struct net_device *netdev);
 919
 920 int mlx5e_open_channels(struct mlx5e_priv *priv,
 921                         struct mlx5e_channels *chs);
 922 void mlx5e_close_channels(struct mlx5e_channels *chs);
 923
 924 /* Function pointer to be used to modify WH settings while
 925  * switching channels
 926  */
 927 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
 928 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
 929                                 struct mlx5e_channels *new_chs,
 930                                 mlx5e_fp_hw_modify hw_modify);
 931 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
 932 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
 933
 934 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
 935                                    int num_channels);
 936 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 937
 938 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
 939                                  u8 cq_period_mode);
 940 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 941                                  u8 cq_period_mode);
 942 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 943                                struct mlx5e_params *params,
 944                                u8 rq_type);
 945
 946 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
 947 {
 948         return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
 949                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
 950 }
 951
 952 static inline
 953 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
 954 {
 955         u16                         pi   = *pc & wq->sz_m1;
 956         struct mlx5e_tx_wqe        *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 957         struct mlx5_wqe_ctrl_seg   *cseg = &wqe->ctrl;
 958
 959         memset(cseg, 0, sizeof(*cseg));
 960
 961         cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
 962         cseg->qpn_ds           = cpu_to_be32((sqn << 8) | 0x01);
 963
 964         (*pc)++;
 965
 966         return wqe;
 967 }
 968
 969 static inline
 970 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
 971                      void __iomem *uar_map,
 972                      struct mlx5_wqe_ctrl_seg *ctrl)
 973 {
 974         ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
 975         /* ensure wqe is visible to device before updating doorbell record */
 976         dma_wmb();
 977
 978         *wq->db = cpu_to_be32(pc);
 979
 980         /* ensure doorbell record is visible to device before ringing the
 981          * doorbell
 982          */
 983         wmb();
 984
 985         mlx5_write64((__be32 *)ctrl, uar_map, NULL);
 986 }
 987
 988 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 989 {
 990         struct mlx5_core_cq *mcq;
 991
 992         mcq = &cq->mcq;
 993         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 994 }
 995
 996 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 997 {
 998         return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 999 }
1000
1001 extern const struct ethtool_ops mlx5e_ethtool_ops;
1002 #ifdef CONFIG_MLX5_CORE_EN_DCB
1003 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1004 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1005 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1006 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1007 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1008 #endif
1009
1010 #ifndef CONFIG_RFS_ACCEL
1011 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
1012 {
1013         return 0;
1014 }
1015
1016 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
1017
1018 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
1019 {
1020         return -EOPNOTSUPP;
1021 }
1022
1023 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
1024 {
1025         return -EOPNOTSUPP;
1026 }
1027 #else
1028 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
1029 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
1030 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
1031 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
1032 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1033                         u16 rxq_index, u32 flow_id);
1034 #endif
1035
1036 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1037 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1038                      struct mlx5e_tir *tir, u32 *in, int inlen);
1039 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1040                        struct mlx5e_tir *tir);
1041 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1042 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1043 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1044
1045 /* common netdev helpers */
1046 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1047
1048 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
1049 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1050
1051 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1052 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1053 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1054 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1055 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1056
1057 int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
1058 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
1059
1060 int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv);
1061 void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv);
1062
1063 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1064                      u32 underlay_qpn, u32 *tisn);
1065 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1066
1067 int mlx5e_create_tises(struct mlx5e_priv *priv);
1068 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1069 int mlx5e_close(struct net_device *netdev);
1070 int mlx5e_open(struct net_device *netdev);
1071 void mlx5e_update_stats_work(struct work_struct *work);
1072 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
1073
1074 /* ethtool helpers */
1075 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1076                                struct ethtool_drvinfo *drvinfo);
1077 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1078                                uint32_t stringset, uint8_t *data);
1079 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1080 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1081                                      struct ethtool_stats *stats, u64 *data);
1082 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1083                                  struct ethtool_ringparam *param);
1084 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1085                                 struct ethtool_ringparam *param);
1086 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1087                                 struct ethtool_channels *ch);
1088 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1089                                struct ethtool_channels *ch);
1090 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1091                                struct ethtool_coalesce *coal);
1092 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1093                                struct ethtool_coalesce *coal);
1094 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1095                               struct ethtool_ts_info *info);
1096 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1097                                struct ethtool_flash *flash);
1098
1099 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1100                             void *cb_priv);
1101
1102 /* mlx5e generic netdev management API */
1103 struct net_device*
1104 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1105                     void *ppriv);
1106 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1107 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1108 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1109 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1110                             struct mlx5e_params *params,
1111                             u16 max_channels);
1112 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1113 #endif /* __MLX5_EN_H__ */