drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include <net/switchdev.h>
  48 #include "wq.h"
  49 #include "mlx5_core.h"
  50 #include "en_stats.h"
  51
  52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  53
  54 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  55 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  56
  57 #define MLX5E_MAX_NUM_TC        8
  58
  59 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  60 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  61 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  62
  63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  66
  67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  70
  71 #define MLX5_RX_HEADROOM NET_SKB_PAD
  72
  73 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
  74         (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
  75 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
  76         max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
  77 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)       MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
  78 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
  79
  80 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  81 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  82                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  83 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  84 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  85                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  86
  87 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  88 #define MLX5E_REQUIRED_MTTS(wqes)               \
  89         (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  90 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
  91
  92 #define MLX5_UMR_ALIGN                          (2048)
  93 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (128)
  94
  95 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  96 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
  97 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
  98
  99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
 100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
 101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
 102 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
 103 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
 104 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
 105 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
 106
 107 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 108 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 109 #define MLX5E_MIN_NUM_CHANNELS         0x1
 110 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 111 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 112 #define MLX5E_TX_CQ_POLL_BUDGET        128
 113 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 114 #define MLX5E_SQ_BF_BUDGET             16
 115
 116 #define MLX5E_ICOSQ_MAX_WQEBBS \
 117         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 118
 119 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 120 #define MLX5E_XDP_IHS_DS_COUNT \
 121         DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
 122 #define MLX5E_XDP_TX_DS_COUNT \
 123         ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 124 #define MLX5E_XDP_TX_WQEBBS \
 125         DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
 126
 127 #define MLX5E_NUM_MAIN_GROUPS 9
 128
 129 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 130 {
 131         switch (wq_type) {
 132         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 133                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 134                              wq_size / 2);
 135         default:
 136                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 137                              wq_size / 2);
 138         }
 139 }
 140
 141 static inline int mlx5_min_log_rq_size(int wq_type)
 142 {
 143         switch (wq_type) {
 144         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 145                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 146         default:
 147                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 148         }
 149 }
 150
 151 static inline int mlx5_max_log_rq_size(int wq_type)
 152 {
 153         switch (wq_type) {
 154         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 155                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 156         default:
 157                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 158         }
 159 }
 160
 161 struct mlx5e_tx_wqe {
 162         struct mlx5_wqe_ctrl_seg ctrl;
 163         struct mlx5_wqe_eth_seg  eth;
 164 };
 165
 166 struct mlx5e_rx_wqe {
 167         struct mlx5_wqe_srq_next_seg  next;
 168         struct mlx5_wqe_data_seg      data;
 169 };
 170
 171 struct mlx5e_umr_wqe {
 172         struct mlx5_wqe_ctrl_seg       ctrl;
 173         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 174         struct mlx5_mkey_seg           mkc;
 175         struct mlx5_wqe_data_seg       data;
 176 };
 177
 178 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
 179
 180 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 181         "rx_cqe_moder",
 182         "rx_cqe_compress",
 183 };
 184
 185 enum mlx5e_priv_flag {
 186         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 187         MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
 188 };
 189
 190 #define MLX5E_SET_PFLAG(priv, pflag, enable)                    \
 191         do {                                                    \
 192                 if (enable)                                     \
 193                         (priv)->params.pflags |= (pflag);       \
 194                 else                                            \
 195                         (priv)->params.pflags &= ~(pflag);      \
 196         } while (0)
 197
 198 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
 199
 200 #ifdef CONFIG_MLX5_CORE_EN_DCB
 201 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 202 #endif
 203
 204 struct mlx5e_cq_moder {
 205         u16 usec;
 206         u16 pkts;
 207 };
 208
 209 struct mlx5e_params {
 210         u8  log_sq_size;
 211         u8  rq_wq_type;
 212         u8  mpwqe_log_stride_sz;
 213         u8  mpwqe_log_num_strides;
 214         u8  log_rq_size;
 215         u16 num_channels;
 216         u8  num_tc;
 217         u8  rx_cq_period_mode;
 218         bool rx_cqe_compress_def;
 219         struct mlx5e_cq_moder rx_cq_moderation;
 220         struct mlx5e_cq_moder tx_cq_moderation;
 221         u16 min_rx_wqes;
 222         bool lro_en;
 223         u32 lro_wqe_sz;
 224         u16 tx_max_inline;
 225         u8  tx_min_inline_mode;
 226         u8  rss_hfunc;
 227         u8  toeplitz_hash_key[40];
 228         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 229         bool vlan_strip_disable;
 230         bool rx_am_enabled;
 231         u32 lro_timeout;
 232         u32 pflags;
 233 };
 234
 235 #ifdef CONFIG_MLX5_CORE_EN_DCB
 236 struct mlx5e_cee_config {
 237         /* bw pct for priority group */
 238         u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];
 239         u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];
 240         bool                       pfc_setting[CEE_DCBX_MAX_PRIO];
 241         bool                       pfc_enable;
 242 };
 243
 244 enum {
 245         MLX5_DCB_CHG_RESET,
 246         MLX5_DCB_NO_CHG,
 247         MLX5_DCB_CHG_NO_RESET,
 248 };
 249
 250 struct mlx5e_dcbx {
 251         enum mlx5_dcbx_oper_mode   mode;
 252         struct mlx5e_cee_config    cee_cfg; /* pending configuration */
 253
 254         /* The only setting that cannot be read from FW */
 255         u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];
 256 };
 257 #endif
 258
 259 struct mlx5e_tstamp {
 260         rwlock_t                   lock;
 261         struct cyclecounter        cycles;
 262         struct timecounter         clock;
 263         struct hwtstamp_config     hwtstamp_config;
 264         u32                        nominal_c_mult;
 265         unsigned long              overflow_period;
 266         struct delayed_work        overflow_work;
 267         struct mlx5_core_dev      *mdev;
 268         struct ptp_clock          *ptp;
 269         struct ptp_clock_info      ptp_info;
 270         u8                        *pps_pin_caps;
 271 };
 272
 273 enum {
 274         MLX5E_RQ_STATE_ENABLED,
 275         MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
 276         MLX5E_RQ_STATE_AM,
 277 };
 278
 279 struct mlx5e_cq {
 280         /* data path - accessed per cqe */
 281         struct mlx5_cqwq           wq;
 282
 283         /* data path - accessed per napi poll */
 284         u16                        event_ctr;
 285         struct napi_struct        *napi;
 286         struct mlx5_core_cq        mcq;
 287         struct mlx5e_channel      *channel;
 288         struct mlx5e_priv         *priv;
 289
 290         /* cqe decompression */
 291         struct mlx5_cqe64          title;
 292         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 293         u8                         mini_arr_idx;
 294         u16                        decmprs_left;
 295         u16                        decmprs_wqe_counter;
 296
 297         /* control */
 298         struct mlx5_frag_wq_ctrl   wq_ctrl;
 299 } ____cacheline_aligned_in_smp;
 300
 301 struct mlx5e_rq;
 302 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
 303                                        struct mlx5_cqe64 *cqe);
 304 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
 305                                   u16 ix);
 306
 307 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
 308
 309 struct mlx5e_dma_info {
 310         struct page     *page;
 311         dma_addr_t      addr;
 312 };
 313
 314 struct mlx5e_rx_am_stats {
 315         int ppms; /* packets per msec */
 316         int epms; /* events per msec */
 317 };
 318
 319 struct mlx5e_rx_am_sample {
 320         ktime_t         time;
 321         unsigned int    pkt_ctr;
 322         u16             event_ctr;
 323 };
 324
 325 struct mlx5e_rx_am { /* Adaptive Moderation */
 326         u8                                      state;
 327         struct mlx5e_rx_am_stats                prev_stats;
 328         struct mlx5e_rx_am_sample               start_sample;
 329         struct work_struct                      work;
 330         u8                                      profile_ix;
 331         u8                                      mode;
 332         u8                                      tune_state;
 333         u8                                      steps_right;
 334         u8                                      steps_left;
 335         u8                                      tired;
 336 };
 337
 338 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 339  * or a MPWQE (for striding rq).
 340  */
 341 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 342                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 343 #define MLX5E_CACHE_SIZE        (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 344 struct mlx5e_page_cache {
 345         u32 head;
 346         u32 tail;
 347         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 348 };
 349
 350 struct mlx5e_rq {
 351         /* data path */
 352         struct mlx5_wq_ll      wq;
 353
 354         union {
 355                 struct mlx5e_dma_info *dma_info;
 356                 struct {
 357                         struct mlx5e_mpw_info *info;
 358                         void                  *mtt_no_align;
 359                 } mpwqe;
 360         };
 361         struct {
 362                 u8             page_order;
 363                 u32            wqe_sz;    /* wqe data buffer size */
 364                 u8             map_dir;   /* dma map direction */
 365         } buff;
 366         __be32                 mkey_be;
 367
 368         struct device         *pdev;
 369         struct net_device     *netdev;
 370         struct mlx5e_tstamp   *tstamp;
 371         struct mlx5e_rq_stats  stats;
 372         struct mlx5e_cq        cq;
 373         struct mlx5e_page_cache page_cache;
 374
 375         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 376         mlx5e_fp_alloc_wqe     alloc_wqe;
 377         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 378
 379         unsigned long          state;
 380         int                    ix;
 381         u16                    rx_headroom;
 382
 383         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 384         struct bpf_prog       *xdp_prog;
 385
 386         /* control */
 387         struct mlx5_wq_ctrl    wq_ctrl;
 388         u8                     wq_type;
 389         u32                    mpwqe_stride_sz;
 390         u32                    mpwqe_num_strides;
 391         u32                    rqn;
 392         struct mlx5e_channel  *channel;
 393         struct mlx5e_priv     *priv;
 394         struct mlx5_core_mkey  umr_mkey;
 395 } ____cacheline_aligned_in_smp;
 396
 397 struct mlx5e_umr_dma_info {
 398         __be64                *mtt;
 399         dma_addr_t             mtt_addr;
 400         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 401         struct mlx5e_umr_wqe   wqe;
 402 };
 403
 404 struct mlx5e_mpw_info {
 405         struct mlx5e_umr_dma_info umr;
 406         u16 consumed_strides;
 407         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 408 };
 409
 410 struct mlx5e_tx_wqe_info {
 411         u32 num_bytes;
 412         u8  num_wqebbs;
 413         u8  num_dma;
 414 };
 415
 416 enum mlx5e_dma_map_type {
 417         MLX5E_DMA_MAP_SINGLE,
 418         MLX5E_DMA_MAP_PAGE
 419 };
 420
 421 struct mlx5e_sq_dma {
 422         dma_addr_t              addr;
 423         u32                     size;
 424         enum mlx5e_dma_map_type type;
 425 };
 426
 427 enum {
 428         MLX5E_SQ_STATE_ENABLED,
 429         MLX5E_SQ_STATE_BF_ENABLE,
 430 };
 431
 432 struct mlx5e_sq_wqe_info {
 433         u8  opcode;
 434         u8  num_wqebbs;
 435 };
 436
 437 enum mlx5e_sq_type {
 438         MLX5E_SQ_TXQ,
 439         MLX5E_SQ_ICO,
 440         MLX5E_SQ_XDP
 441 };
 442
 443 struct mlx5e_sq {
 444         /* data path */
 445
 446         /* dirtied @completion */
 447         u16                        cc;
 448         u32                        dma_fifo_cc;
 449
 450         /* dirtied @xmit */
 451         u16                        pc ____cacheline_aligned_in_smp;
 452         u32                        dma_fifo_pc;
 453         u16                        bf_offset;
 454         u16                        prev_cc;
 455         u8                         bf_budget;
 456         struct mlx5e_sq_stats      stats;
 457
 458         struct mlx5e_cq            cq;
 459
 460         /* pointers to per tx element info: write@xmit, read@completion */
 461         union {
 462                 struct {
 463                         struct sk_buff           **skb;
 464                         struct mlx5e_sq_dma       *dma_fifo;
 465                         struct mlx5e_tx_wqe_info  *wqe_info;
 466                 } txq;
 467                 struct mlx5e_sq_wqe_info *ico_wqe;
 468                 struct {
 469                         struct mlx5e_sq_wqe_info  *wqe_info;
 470                         struct mlx5e_dma_info     *di;
 471                         bool                       doorbell;
 472                 } xdp;
 473         } db;
 474
 475         /* read only */
 476         struct mlx5_wq_cyc         wq;
 477         u32                        dma_fifo_mask;
 478         void __iomem              *uar_map;
 479         struct netdev_queue       *txq;
 480         u32                        sqn;
 481         u16                        bf_buf_size;
 482         u16                        max_inline;
 483         u8                         min_inline_mode;
 484         u16                        edge;
 485         struct device             *pdev;
 486         struct mlx5e_tstamp       *tstamp;
 487         __be32                     mkey_be;
 488         unsigned long              state;
 489
 490         /* control path */
 491         struct mlx5_wq_ctrl        wq_ctrl;
 492         struct mlx5_sq_bfreg       bfreg;
 493         struct mlx5e_channel      *channel;
 494         int                        tc;
 495         u32                        rate_limit;
 496         u8                         type;
 497 } ____cacheline_aligned_in_smp;
 498
 499 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 500 {
 501         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 502                 (sq->cc  == sq->pc));
 503 }
 504
 505 enum channel_flags {
 506         MLX5E_CHANNEL_NAPI_SCHED = 1,
 507 };
 508
 509 struct mlx5e_channel {
 510         /* data path */
 511         struct mlx5e_rq            rq;
 512         struct mlx5e_sq            xdp_sq;
 513         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 514         struct mlx5e_sq            icosq;   /* internal control operations */
 515         bool                       xdp;
 516         struct napi_struct         napi;
 517         struct device             *pdev;
 518         struct net_device         *netdev;
 519         __be32                     mkey_be;
 520         u8                         num_tc;
 521         unsigned long              flags;
 522
 523         /* control */
 524         struct mlx5e_priv         *priv;
 525         int                        ix;
 526         int                        cpu;
 527 };
 528
 529 enum mlx5e_traffic_types {
 530         MLX5E_TT_IPV4_TCP,
 531         MLX5E_TT_IPV6_TCP,
 532         MLX5E_TT_IPV4_UDP,
 533         MLX5E_TT_IPV6_UDP,
 534         MLX5E_TT_IPV4_IPSEC_AH,
 535         MLX5E_TT_IPV6_IPSEC_AH,
 536         MLX5E_TT_IPV4_IPSEC_ESP,
 537         MLX5E_TT_IPV6_IPSEC_ESP,
 538         MLX5E_TT_IPV4,
 539         MLX5E_TT_IPV6,
 540         MLX5E_TT_ANY,
 541         MLX5E_NUM_TT,
 542         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 543 };
 544
 545 enum {
 546         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 547         MLX5E_STATE_OPENED,
 548         MLX5E_STATE_DESTROYING,
 549 };
 550
 551 struct mlx5e_vxlan_db {
 552         spinlock_t                      lock; /* protect vxlan table */
 553         struct radix_tree_root          tree;
 554 };
 555
 556 struct mlx5e_l2_rule {
 557         u8  addr[ETH_ALEN + 2];
 558         struct mlx5_flow_handle *rule;
 559 };
 560
 561 struct mlx5e_flow_table {
 562         int num_groups;
 563         struct mlx5_flow_table *t;
 564         struct mlx5_flow_group **g;
 565 };
 566
 567 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 568
 569 struct mlx5e_tc_table {
 570         struct mlx5_flow_table          *t;
 571
 572         struct rhashtable_params        ht_params;
 573         struct rhashtable               ht;
 574 };
 575
 576 struct mlx5e_vlan_table {
 577         struct mlx5e_flow_table         ft;
 578         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 579         struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
 580         struct mlx5_flow_handle *untagged_rule;
 581         struct mlx5_flow_handle *any_cvlan_rule;
 582         struct mlx5_flow_handle *any_svlan_rule;
 583         bool                    filter_disabled;
 584 };
 585
 586 struct mlx5e_l2_table {
 587         struct mlx5e_flow_table    ft;
 588         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 589         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 590         struct mlx5e_l2_rule       broadcast;
 591         struct mlx5e_l2_rule       allmulti;
 592         struct mlx5e_l2_rule       promisc;
 593         bool                       broadcast_enabled;
 594         bool                       allmulti_enabled;
 595         bool                       promisc_enabled;
 596 };
 597
 598 /* L3/L4 traffic type classifier */
 599 struct mlx5e_ttc_table {
 600         struct mlx5e_flow_table  ft;
 601         struct mlx5_flow_handle  *rules[MLX5E_NUM_TT];
 602 };
 603
 604 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 605 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 606 struct arfs_table {
 607         struct mlx5e_flow_table  ft;
 608         struct mlx5_flow_handle  *default_rule;
 609         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 610 };
 611
 612 enum  arfs_type {
 613         ARFS_IPV4_TCP,
 614         ARFS_IPV6_TCP,
 615         ARFS_IPV4_UDP,
 616         ARFS_IPV6_UDP,
 617         ARFS_NUM_TYPES,
 618 };
 619
 620 struct mlx5e_arfs_tables {
 621         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 622         /* Protect aRFS rules list */
 623         spinlock_t                     arfs_lock;
 624         struct list_head               rules;
 625         int                            last_filter_id;
 626         struct workqueue_struct        *wq;
 627 };
 628
 629 /* NIC prio FTS */
 630 enum {
 631         MLX5E_VLAN_FT_LEVEL = 0,
 632         MLX5E_L2_FT_LEVEL,
 633         MLX5E_TTC_FT_LEVEL,
 634         MLX5E_ARFS_FT_LEVEL
 635 };
 636
 637 struct mlx5e_ethtool_table {
 638         struct mlx5_flow_table *ft;
 639         int                    num_rules;
 640 };
 641
 642 #define ETHTOOL_NUM_L3_L4_FTS 7
 643 #define ETHTOOL_NUM_L2_FTS 4
 644
 645 struct mlx5e_ethtool_steering {
 646         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 647         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 648         struct list_head                rules;
 649         int                             tot_num_rules;
 650 };
 651
 652 struct mlx5e_flow_steering {
 653         struct mlx5_flow_namespace      *ns;
 654         struct mlx5e_ethtool_steering   ethtool;
 655         struct mlx5e_tc_table           tc;
 656         struct mlx5e_vlan_table         vlan;
 657         struct mlx5e_l2_table           l2;
 658         struct mlx5e_ttc_table          ttc;
 659         struct mlx5e_arfs_tables        arfs;
 660 };
 661
 662 struct mlx5e_rqt {
 663         u32              rqtn;
 664         bool             enabled;
 665 };
 666
 667 struct mlx5e_tir {
 668         u32               tirn;
 669         struct mlx5e_rqt  rqt;
 670         struct list_head  list;
 671 };
 672
 673 enum {
 674         MLX5E_TC_PRIO = 0,
 675         MLX5E_NIC_PRIO
 676 };
 677
 678 struct mlx5e_profile {
 679         void    (*init)(struct mlx5_core_dev *mdev,
 680                         struct net_device *netdev,
 681                         const struct mlx5e_profile *profile, void *ppriv);
 682         void    (*cleanup)(struct mlx5e_priv *priv);
 683         int     (*init_rx)(struct mlx5e_priv *priv);
 684         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 685         int     (*init_tx)(struct mlx5e_priv *priv);
 686         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 687         void    (*enable)(struct mlx5e_priv *priv);
 688         void    (*disable)(struct mlx5e_priv *priv);
 689         void    (*update_stats)(struct mlx5e_priv *priv);
 690         int     (*max_nch)(struct mlx5_core_dev *mdev);
 691         int     max_tc;
 692 };
 693
 694 struct mlx5e_priv {
 695         /* priv data path fields - start */
 696         struct mlx5e_sq            **txq_to_sq_map;
 697         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 698         struct bpf_prog *xdp_prog;
 699         /* priv data path fields - end */
 700
 701         unsigned long              state;
 702         struct mutex               state_lock; /* Protects Interface state */
 703         struct mlx5e_rq            drop_rq;
 704
 705         struct mlx5e_channel     **channel;
 706         u32                        tisn[MLX5E_MAX_NUM_TC];
 707         struct mlx5e_rqt           indir_rqt;
 708         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 709         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 710         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 711
 712         struct mlx5e_flow_steering fs;
 713         struct mlx5e_vxlan_db      vxlan;
 714
 715         struct mlx5e_params        params;
 716         struct workqueue_struct    *wq;
 717         struct work_struct         update_carrier_work;
 718         struct work_struct         set_rx_mode_work;
 719         struct work_struct         tx_timeout_work;
 720         struct delayed_work        update_stats_work;
 721
 722         struct mlx5_core_dev      *mdev;
 723         struct net_device         *netdev;
 724         struct mlx5e_stats         stats;
 725         struct mlx5e_tstamp        tstamp;
 726         u16 q_counter;
 727 #ifdef CONFIG_MLX5_CORE_EN_DCB
 728         struct mlx5e_dcbx          dcbx;
 729 #endif
 730
 731         const struct mlx5e_profile *profile;
 732         void                      *ppriv;
 733 };
 734
 735 void mlx5e_build_ptys2ethtool_map(void);
 736
 737 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 738 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 739                        void *accel_priv, select_queue_fallback_t fallback);
 740 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 741
 742 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 743 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 744 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 745 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 746 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 747 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
 748
 749 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 750                         bool recycle);
 751 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 752 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 753 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 754 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 755 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 756 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 757 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 758 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 759 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 760 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 761
 762 void mlx5e_rx_am(struct mlx5e_rq *rq);
 763 void mlx5e_rx_am_work(struct work_struct *work);
 764 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 765
 766 void mlx5e_update_stats(struct mlx5e_priv *priv);
 767
 768 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 769 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 770 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 771 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 772 int mlx5e_self_test_num(struct mlx5e_priv *priv);
 773 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
 774                      u64 *buf);
 775 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 776                            int location);
 777 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 778                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 779 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 780                                struct ethtool_rx_flow_spec *fs);
 781 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 782                               int location);
 783 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 784 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 785 void mlx5e_set_rx_mode_work(struct work_struct *work);
 786
 787 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 788                         struct skb_shared_hwtstamps *hwts);
 789 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 790 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 791 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
 792                              struct ptp_clock_event *event);
 793 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 794 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 795 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
 796
 797 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 798                           u16 vid);
 799 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 800                            u16 vid);
 801 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 802 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 803
 804 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
 805
 806 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
 807 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
 808                                     enum mlx5e_traffic_types tt);
 809
 810 int mlx5e_open_locked(struct net_device *netdev);
 811 int mlx5e_close_locked(struct net_device *netdev);
 812 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 813                                    u32 *indirection_rqt, int len,
 814                                    int num_channels);
 815 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 816
 817 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 818                                  u8 cq_period_mode);
 819
 820 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
 821                                       struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
 822 {
 823         u16 ofst = sq->bf_offset;
 824
 825         /* ensure wqe is visible to device before updating doorbell record */
 826         dma_wmb();
 827
 828         *sq->wq.db = cpu_to_be32(sq->pc);
 829
 830         /* ensure doorbell record is visible to device before ringing the
 831          * doorbell
 832          */
 833         wmb();
 834         if (bf_sz)
 835                 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
 836         else
 837                 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
 838         /* flush the write-combining mapped buffer */
 839         wmb();
 840
 841         sq->bf_offset ^= sq->bf_buf_size;
 842 }
 843
 844 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 845 {
 846         struct mlx5_core_cq *mcq;
 847
 848         mcq = &cq->mcq;
 849         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 850 }
 851
 852 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 853 {
 854         return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 855 }
 856
 857 extern const struct ethtool_ops mlx5e_ethtool_ops;
 858 #ifdef CONFIG_MLX5_CORE_EN_DCB
 859 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 860 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 861 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
 862 #endif
 863
 864 #ifndef CONFIG_RFS_ACCEL
 865 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
 866 {
 867         return 0;
 868 }
 869
 870 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
 871
 872 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
 873 {
 874         return -EOPNOTSUPP;
 875 }
 876
 877 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
 878 {
 879         return -EOPNOTSUPP;
 880 }
 881 #else
 882 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
 883 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
 884 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
 885 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
 886 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
 887                         u16 rxq_index, u32 flow_id);
 888 #endif
 889
 890 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 891 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
 892                      struct mlx5e_tir *tir, u32 *in, int inlen);
 893 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
 894                        struct mlx5e_tir *tir);
 895 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
 896 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
 897 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
 898                                      bool enable_uc_lb);
 899
 900 struct mlx5_eswitch_rep;
 901 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
 902                          struct mlx5_eswitch_rep *rep);
 903 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
 904                             struct mlx5_eswitch_rep *rep);
 905 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
 906 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
 907                           struct mlx5_eswitch_rep *rep);
 908 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
 909 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
 910 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
 911 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 912 void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv);
 913
 914 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
 915 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
 916 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
 917 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
 918 int mlx5e_create_tises(struct mlx5e_priv *priv);
 919 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
 920 int mlx5e_close(struct net_device *netdev);
 921 int mlx5e_open(struct net_device *netdev);
 922 void mlx5e_update_stats_work(struct work_struct *work);
 923 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
 924                                        const struct mlx5e_profile *profile,
 925                                        void *ppriv);
 926 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
 927 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 928 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 929 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
 930 void mlx5e_add_vxlan_port(struct net_device *netdev,
 931                           struct udp_tunnel_info *ti);
 932 void mlx5e_del_vxlan_port(struct net_device *netdev,
 933                           struct udp_tunnel_info *ti);
 934
 935 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
 936                             void *sp);
 937 bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id);
 938
 939 bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv);
 940 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv);
 941 #endif /* __MLX5_EN_H__ */