drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/if_vlan.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/timecounter.h>
  36 #include <linux/net_tstamp.h>
  37 #include <linux/ptp_clock_kernel.h>
  38 #include <linux/mlx5/driver.h>
  39 #include <linux/mlx5/qp.h>
  40 #include <linux/mlx5/cq.h>
  41 #include <linux/mlx5/vport.h>
  42 #include <linux/mlx5/transobj.h>
  43 #include "wq.h"
  44 #include "mlx5_core.h"
  45
  46 #define MLX5E_MAX_NUM_TC        8
  47
  48 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  49 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  50 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  51
  52 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  53 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  54 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  55
  56 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  57 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
  58 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
  59 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
  60 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
  61 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
  62
  63 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
  64 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
  65 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
  66 #define MLX5E_TX_CQ_POLL_BUDGET        128
  67 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
  68 #define MLX5E_SQ_BF_BUDGET             16
  69
  70 #define MLX5E_NUM_MAIN_GROUPS 9
  71
  72 static const char vport_strings[][ETH_GSTRING_LEN] = {
  73         /* vport statistics */
  74         "rx_packets",
  75         "rx_bytes",
  76         "tx_packets",
  77         "tx_bytes",
  78         "rx_error_packets",
  79         "rx_error_bytes",
  80         "tx_error_packets",
  81         "tx_error_bytes",
  82         "rx_unicast_packets",
  83         "rx_unicast_bytes",
  84         "tx_unicast_packets",
  85         "tx_unicast_bytes",
  86         "rx_multicast_packets",
  87         "rx_multicast_bytes",
  88         "tx_multicast_packets",
  89         "tx_multicast_bytes",
  90         "rx_broadcast_packets",
  91         "rx_broadcast_bytes",
  92         "tx_broadcast_packets",
  93         "tx_broadcast_bytes",
  94
  95         /* SW counters */
  96         "tso_packets",
  97         "tso_bytes",
  98         "lro_packets",
  99         "lro_bytes",
 100         "rx_csum_good",
 101         "rx_csum_none",
 102         "rx_csum_sw",
 103         "tx_csum_offload",
 104         "tx_queue_stopped",
 105         "tx_queue_wake",
 106         "tx_queue_dropped",
 107         "rx_wqe_err",
 108 };
 109
 110 struct mlx5e_vport_stats {
 111         /* HW counters */
 112         u64 rx_packets;
 113         u64 rx_bytes;
 114         u64 tx_packets;
 115         u64 tx_bytes;
 116         u64 rx_error_packets;
 117         u64 rx_error_bytes;
 118         u64 tx_error_packets;
 119         u64 tx_error_bytes;
 120         u64 rx_unicast_packets;
 121         u64 rx_unicast_bytes;
 122         u64 tx_unicast_packets;
 123         u64 tx_unicast_bytes;
 124         u64 rx_multicast_packets;
 125         u64 rx_multicast_bytes;
 126         u64 tx_multicast_packets;
 127         u64 tx_multicast_bytes;
 128         u64 rx_broadcast_packets;
 129         u64 rx_broadcast_bytes;
 130         u64 tx_broadcast_packets;
 131         u64 tx_broadcast_bytes;
 132
 133         /* SW counters */
 134         u64 tso_packets;
 135         u64 tso_bytes;
 136         u64 lro_packets;
 137         u64 lro_bytes;
 138         u64 rx_csum_good;
 139         u64 rx_csum_none;
 140         u64 rx_csum_sw;
 141         u64 tx_csum_offload;
 142         u64 tx_queue_stopped;
 143         u64 tx_queue_wake;
 144         u64 tx_queue_dropped;
 145         u64 rx_wqe_err;
 146
 147 #define NUM_VPORT_COUNTERS     32
 148 };
 149
 150 static const char pport_strings[][ETH_GSTRING_LEN] = {
 151         /* IEEE802.3 counters */
 152         "frames_tx",
 153         "frames_rx",
 154         "check_seq_err",
 155         "alignment_err",
 156         "octets_tx",
 157         "octets_received",
 158         "multicast_xmitted",
 159         "broadcast_xmitted",
 160         "multicast_rx",
 161         "broadcast_rx",
 162         "in_range_len_errors",
 163         "out_of_range_len",
 164         "too_long_errors",
 165         "symbol_err",
 166         "mac_control_tx",
 167         "mac_control_rx",
 168         "unsupported_op_rx",
 169         "pause_ctrl_rx",
 170         "pause_ctrl_tx",
 171
 172         /* RFC2863 counters */
 173         "in_octets",
 174         "in_ucast_pkts",
 175         "in_discards",
 176         "in_errors",
 177         "in_unknown_protos",
 178         "out_octets",
 179         "out_ucast_pkts",
 180         "out_discards",
 181         "out_errors",
 182         "in_multicast_pkts",
 183         "in_broadcast_pkts",
 184         "out_multicast_pkts",
 185         "out_broadcast_pkts",
 186
 187         /* RFC2819 counters */
 188         "drop_events",
 189         "octets",
 190         "pkts",
 191         "broadcast_pkts",
 192         "multicast_pkts",
 193         "crc_align_errors",
 194         "undersize_pkts",
 195         "oversize_pkts",
 196         "fragments",
 197         "jabbers",
 198         "collisions",
 199         "p64octets",
 200         "p65to127octets",
 201         "p128to255octets",
 202         "p256to511octets",
 203         "p512to1023octets",
 204         "p1024to1518octets",
 205         "p1519to2047octets",
 206         "p2048to4095octets",
 207         "p4096to8191octets",
 208         "p8192to10239octets",
 209 };
 210
 211 #define NUM_IEEE_802_3_COUNTERS         19
 212 #define NUM_RFC_2863_COUNTERS           13
 213 #define NUM_RFC_2819_COUNTERS           21
 214 #define NUM_PPORT_COUNTERS              (NUM_IEEE_802_3_COUNTERS + \
 215                                          NUM_RFC_2863_COUNTERS + \
 216                                          NUM_RFC_2819_COUNTERS)
 217
 218 struct mlx5e_pport_stats {
 219         __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
 220         __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
 221         __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
 222 };
 223
 224 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
 225         "packets",
 226         "csum_none",
 227         "csum_sw",
 228         "lro_packets",
 229         "lro_bytes",
 230         "wqe_err"
 231 };
 232
 233 struct mlx5e_rq_stats {
 234         u64 packets;
 235         u64 csum_none;
 236         u64 csum_sw;
 237         u64 lro_packets;
 238         u64 lro_bytes;
 239         u64 wqe_err;
 240 #define NUM_RQ_STATS 6
 241 };
 242
 243 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
 244         "packets",
 245         "tso_packets",
 246         "tso_bytes",
 247         "csum_offload_none",
 248         "stopped",
 249         "wake",
 250         "dropped",
 251         "nop"
 252 };
 253
 254 struct mlx5e_sq_stats {
 255         u64 packets;
 256         u64 tso_packets;
 257         u64 tso_bytes;
 258         u64 csum_offload_none;
 259         u64 stopped;
 260         u64 wake;
 261         u64 dropped;
 262         u64 nop;
 263 #define NUM_SQ_STATS 8
 264 };
 265
 266 struct mlx5e_stats {
 267         struct mlx5e_vport_stats   vport;
 268         struct mlx5e_pport_stats   pport;
 269 };
 270
 271 struct mlx5e_params {
 272         u8  log_sq_size;
 273         u8  log_rq_size;
 274         u16 num_channels;
 275         u8  default_vlan_prio;
 276         u8  num_tc;
 277         u16 rx_cq_moderation_usec;
 278         u16 rx_cq_moderation_pkts;
 279         u16 tx_cq_moderation_usec;
 280         u16 tx_cq_moderation_pkts;
 281         u16 min_rx_wqes;
 282         bool lro_en;
 283         u32 lro_wqe_sz;
 284         u16 tx_max_inline;
 285         u8  rss_hfunc;
 286         u8  toeplitz_hash_key[40];
 287         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 288 };
 289
 290 struct mlx5e_tstamp {
 291         rwlock_t                   lock;
 292         struct cyclecounter        cycles;
 293         struct timecounter         clock;
 294         struct hwtstamp_config     hwtstamp_config;
 295         u32                        nominal_c_mult;
 296         unsigned long              overflow_period;
 297         struct delayed_work        overflow_work;
 298         struct mlx5_core_dev      *mdev;
 299         struct ptp_clock          *ptp;
 300         struct ptp_clock_info      ptp_info;
 301 };
 302
 303 enum {
 304         MLX5E_RQ_STATE_POST_WQES_ENABLE,
 305 };
 306
 307 struct mlx5e_cq {
 308         /* data path - accessed per cqe */
 309         struct mlx5_cqwq           wq;
 310
 311         /* data path - accessed per napi poll */
 312         struct napi_struct        *napi;
 313         struct mlx5_core_cq        mcq;
 314         struct mlx5e_channel      *channel;
 315         struct mlx5e_priv         *priv;
 316
 317         /* control */
 318         struct mlx5_wq_ctrl        wq_ctrl;
 319 } ____cacheline_aligned_in_smp;
 320
 321 struct mlx5e_rq {
 322         /* data path */
 323         struct mlx5_wq_ll      wq;
 324         u32                    wqe_sz;
 325         struct sk_buff       **skb;
 326
 327         struct device         *pdev;
 328         struct net_device     *netdev;
 329         struct mlx5e_tstamp   *tstamp;
 330         struct mlx5e_rq_stats  stats;
 331         struct mlx5e_cq        cq;
 332
 333         unsigned long          state;
 334         int                    ix;
 335
 336         /* control */
 337         struct mlx5_wq_ctrl    wq_ctrl;
 338         u32                    rqn;
 339         struct mlx5e_channel  *channel;
 340         struct mlx5e_priv     *priv;
 341 } ____cacheline_aligned_in_smp;
 342
 343 struct mlx5e_tx_wqe_info {
 344         u32 num_bytes;
 345         u8  num_wqebbs;
 346         u8  num_dma;
 347 };
 348
 349 enum mlx5e_dma_map_type {
 350         MLX5E_DMA_MAP_SINGLE,
 351         MLX5E_DMA_MAP_PAGE
 352 };
 353
 354 struct mlx5e_sq_dma {
 355         dma_addr_t              addr;
 356         u32                     size;
 357         enum mlx5e_dma_map_type type;
 358 };
 359
 360 enum {
 361         MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
 362 };
 363
 364 struct mlx5e_sq {
 365         /* data path */
 366
 367         /* dirtied @completion */
 368         u16                        cc;
 369         u32                        dma_fifo_cc;
 370
 371         /* dirtied @xmit */
 372         u16                        pc ____cacheline_aligned_in_smp;
 373         u32                        dma_fifo_pc;
 374         u16                        bf_offset;
 375         u16                        prev_cc;
 376         u8                         bf_budget;
 377         struct mlx5e_sq_stats      stats;
 378
 379         struct mlx5e_cq            cq;
 380
 381         /* pointers to per packet info: write@xmit, read@completion */
 382         struct sk_buff           **skb;
 383         struct mlx5e_sq_dma       *dma_fifo;
 384         struct mlx5e_tx_wqe_info  *wqe_info;
 385
 386         /* read only */
 387         struct mlx5_wq_cyc         wq;
 388         u32                        dma_fifo_mask;
 389         void __iomem              *uar_map;
 390         void __iomem              *uar_bf_map;
 391         struct netdev_queue       *txq;
 392         u32                        sqn;
 393         u16                        bf_buf_size;
 394         u16                        max_inline;
 395         u16                        edge;
 396         struct device             *pdev;
 397         struct mlx5e_tstamp       *tstamp;
 398         __be32                     mkey_be;
 399         unsigned long              state;
 400
 401         /* control path */
 402         struct mlx5_wq_ctrl        wq_ctrl;
 403         struct mlx5_uar            uar;
 404         struct mlx5e_channel      *channel;
 405         int                        tc;
 406 } ____cacheline_aligned_in_smp;
 407
 408 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 409 {
 410         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 411                 (sq->cc  == sq->pc));
 412 }
 413
 414 enum channel_flags {
 415         MLX5E_CHANNEL_NAPI_SCHED = 1,
 416 };
 417
 418 struct mlx5e_channel {
 419         /* data path */
 420         struct mlx5e_rq            rq;
 421         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 422         struct napi_struct         napi;
 423         struct device             *pdev;
 424         struct net_device         *netdev;
 425         __be32                     mkey_be;
 426         u8                         num_tc;
 427         unsigned long              flags;
 428
 429         /* control */
 430         struct mlx5e_priv         *priv;
 431         int                        ix;
 432         int                        cpu;
 433 };
 434
 435 enum mlx5e_traffic_types {
 436         MLX5E_TT_IPV4_TCP,
 437         MLX5E_TT_IPV6_TCP,
 438         MLX5E_TT_IPV4_UDP,
 439         MLX5E_TT_IPV6_UDP,
 440         MLX5E_TT_IPV4_IPSEC_AH,
 441         MLX5E_TT_IPV6_IPSEC_AH,
 442         MLX5E_TT_IPV4_IPSEC_ESP,
 443         MLX5E_TT_IPV6_IPSEC_ESP,
 444         MLX5E_TT_IPV4,
 445         MLX5E_TT_IPV6,
 446         MLX5E_TT_ANY,
 447         MLX5E_NUM_TT,
 448 };
 449
 450 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
 451
 452 enum mlx5e_rqt_ix {
 453         MLX5E_INDIRECTION_RQT,
 454         MLX5E_SINGLE_RQ_RQT,
 455         MLX5E_NUM_RQT,
 456 };
 457
 458 struct mlx5e_eth_addr_info {
 459         u8  addr[ETH_ALEN + 2];
 460         u32 tt_vec;
 461         struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
 462 };
 463
 464 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
 465
 466 struct mlx5e_eth_addr_db {
 467         struct hlist_head          netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
 468         struct hlist_head          netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
 469         struct mlx5e_eth_addr_info broadcast;
 470         struct mlx5e_eth_addr_info allmulti;
 471         struct mlx5e_eth_addr_info promisc;
 472         bool                       broadcast_enabled;
 473         bool                       allmulti_enabled;
 474         bool                       promisc_enabled;
 475 };
 476
 477 enum {
 478         MLX5E_STATE_ASYNC_EVENTS_ENABLE,
 479         MLX5E_STATE_OPENED,
 480         MLX5E_STATE_DESTROYING,
 481 };
 482
 483 struct mlx5e_vlan_db {
 484         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 485         struct mlx5_flow_rule   *active_vlans_rule[VLAN_N_VID];
 486         struct mlx5_flow_rule   *untagged_rule;
 487         struct mlx5_flow_rule   *any_vlan_rule;
 488         bool          filter_disabled;
 489 };
 490
 491 struct mlx5e_flow_table {
 492         int num_groups;
 493         struct mlx5_flow_table          *t;
 494         struct mlx5_flow_group          **g;
 495 };
 496
 497 struct mlx5e_flow_tables {
 498         struct mlx5_flow_namespace      *ns;
 499         struct mlx5e_flow_table         vlan;
 500         struct mlx5e_flow_table         main;
 501 };
 502
 503 struct mlx5e_priv {
 504         /* priv data path fields - start */
 505         int                        default_vlan_prio;
 506         struct mlx5e_sq            **txq_to_sq_map;
 507         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 508         /* priv data path fields - end */
 509
 510         unsigned long              state;
 511         struct mutex               state_lock; /* Protects Interface state */
 512         struct mlx5_uar            cq_uar;
 513         u32                        pdn;
 514         u32                        tdn;
 515         struct mlx5_core_mr        mr;
 516         struct mlx5e_rq            drop_rq;
 517
 518         struct mlx5e_channel     **channel;
 519         u32                        tisn[MLX5E_MAX_NUM_TC];
 520         u32                        rqtn[MLX5E_NUM_RQT];
 521         u32                        tirn[MLX5E_NUM_TT];
 522
 523         struct mlx5e_flow_tables   fts;
 524         struct mlx5e_eth_addr_db   eth_addr;
 525         struct mlx5e_vlan_db       vlan;
 526
 527         struct mlx5e_params        params;
 528         spinlock_t                 async_events_spinlock; /* sync hw events */
 529         struct work_struct         update_carrier_work;
 530         struct work_struct         set_rx_mode_work;
 531         struct delayed_work        update_stats_work;
 532
 533         struct mlx5_core_dev      *mdev;
 534         struct net_device         *netdev;
 535         struct mlx5e_stats         stats;
 536         struct mlx5e_tstamp        tstamp;
 537 };
 538
 539 #define MLX5E_NET_IP_ALIGN 2
 540
 541 struct mlx5e_tx_wqe {
 542         struct mlx5_wqe_ctrl_seg ctrl;
 543         struct mlx5_wqe_eth_seg  eth;
 544 };
 545
 546 struct mlx5e_rx_wqe {
 547         struct mlx5_wqe_srq_next_seg  next;
 548         struct mlx5_wqe_data_seg      data;
 549 };
 550
 551 enum mlx5e_link_mode {
 552         MLX5E_1000BASE_CX_SGMII  = 0,
 553         MLX5E_1000BASE_KX        = 1,
 554         MLX5E_10GBASE_CX4        = 2,
 555         MLX5E_10GBASE_KX4        = 3,
 556         MLX5E_10GBASE_KR         = 4,
 557         MLX5E_20GBASE_KR2        = 5,
 558         MLX5E_40GBASE_CR4        = 6,
 559         MLX5E_40GBASE_KR4        = 7,
 560         MLX5E_56GBASE_R4         = 8,
 561         MLX5E_10GBASE_CR         = 12,
 562         MLX5E_10GBASE_SR         = 13,
 563         MLX5E_10GBASE_ER         = 14,
 564         MLX5E_40GBASE_SR4        = 15,
 565         MLX5E_40GBASE_LR4        = 16,
 566         MLX5E_100GBASE_CR4       = 20,
 567         MLX5E_100GBASE_SR4       = 21,
 568         MLX5E_100GBASE_KR4       = 22,
 569         MLX5E_100GBASE_LR4       = 23,
 570         MLX5E_100BASE_TX         = 24,
 571         MLX5E_100BASE_T          = 25,
 572         MLX5E_10GBASE_T          = 26,
 573         MLX5E_25GBASE_CR         = 27,
 574         MLX5E_25GBASE_KR         = 28,
 575         MLX5E_25GBASE_SR         = 29,
 576         MLX5E_50GBASE_CR2        = 30,
 577         MLX5E_50GBASE_KR2        = 31,
 578         MLX5E_LINK_MODES_NUMBER,
 579 };
 580
 581 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
 582
 583 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 584 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 585                        void *accel_priv, select_queue_fallback_t fallback);
 586 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 587
 588 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 589 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 590 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 591 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
 592 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 593 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 594 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 595
 596 void mlx5e_update_stats(struct mlx5e_priv *priv);
 597
 598 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
 599 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
 600 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
 601 void mlx5e_set_rx_mode_work(struct work_struct *work);
 602
 603 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 604                         struct skb_shared_hwtstamps *hwts);
 605 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 606 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 607 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 608 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 609
 610 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 611                           u16 vid);
 612 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 613                            u16 vid);
 614 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 615 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 616
 617 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
 618 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
 619
 620 int mlx5e_open_locked(struct net_device *netdev);
 621 int mlx5e_close_locked(struct net_device *netdev);
 622
 623 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
 624                                       struct mlx5e_tx_wqe *wqe, int bf_sz)
 625 {
 626         u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
 627
 628         /* ensure wqe is visible to device before updating doorbell record */
 629         dma_wmb();
 630
 631         *sq->wq.db = cpu_to_be32(sq->pc);
 632
 633         /* ensure doorbell record is visible to device before ringing the
 634          * doorbell
 635          */
 636         wmb();
 637
 638         if (bf_sz) {
 639                 __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);
 640
 641                 /* flush the write-combining mapped buffer */
 642                 wmb();
 643
 644         } else {
 645                 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
 646         }
 647
 648         sq->bf_offset ^= sq->bf_buf_size;
 649 }
 650
 651 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 652 {
 653         struct mlx5_core_cq *mcq;
 654
 655         mcq = &cq->mcq;
 656         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
 657 }
 658
 659 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 660 {
 661         return min_t(int, mdev->priv.eq_table.num_comp_vectors,
 662                      MLX5E_MAX_NUM_CHANNELS);
 663 }
 664
 665 extern const struct ethtool_ops mlx5e_ethtool_ops;
 666 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);