drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include "wq.h"
  48 #include "mlx5_core.h"
  49
  50 #define MLX5E_MAX_NUM_TC        8
  51
  52 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  53 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  54 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  55
  56 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  57 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  58 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  59
  60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x4
  62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  63
  64 #define MLX5_MPWRQ_LOG_NUM_STRIDES              11 /* >= 9, HW restriction */
  65 #define MLX5_MPWRQ_LOG_STRIDE_SIZE              6  /* >= 6, HW restriction */
  66 #define MLX5_MPWRQ_NUM_STRIDES                  BIT(MLX5_MPWRQ_LOG_NUM_STRIDES)
  67 #define MLX5_MPWRQ_STRIDE_SIZE                  BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE)
  68 #define MLX5_MPWRQ_LOG_WQE_SZ                   (MLX5_MPWRQ_LOG_NUM_STRIDES +\
  69                                                  MLX5_MPWRQ_LOG_STRIDE_SIZE)
  70 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  71                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  72 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  73 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  74                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  75 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (128)
  76
  77 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  78 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
  79 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
  80 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
  81 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
  82 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
  83 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
  84
  85 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
  86 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
  87 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
  88 #define MLX5E_TX_CQ_POLL_BUDGET        128
  89 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
  90 #define MLX5E_SQ_BF_BUDGET             16
  91
  92 #define MLX5E_NUM_MAIN_GROUPS 9
  93 #define MLX5E_NET_IP_ALIGN 2
  94
  95 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
  96 {
  97         switch (wq_type) {
  98         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  99                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 100                              wq_size / 2);
 101         default:
 102                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 103                              wq_size / 2);
 104         }
 105 }
 106
 107 static inline int mlx5_min_log_rq_size(int wq_type)
 108 {
 109         switch (wq_type) {
 110         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 111                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 112         default:
 113                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 114         }
 115 }
 116
 117 static inline int mlx5_max_log_rq_size(int wq_type)
 118 {
 119         switch (wq_type) {
 120         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 121                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 122         default:
 123                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 124         }
 125 }
 126
 127 struct mlx5e_tx_wqe {
 128         struct mlx5_wqe_ctrl_seg ctrl;
 129         struct mlx5_wqe_eth_seg  eth;
 130 };
 131
 132 struct mlx5e_rx_wqe {
 133         struct mlx5_wqe_srq_next_seg  next;
 134         struct mlx5_wqe_data_seg      data;
 135 };
 136
 137 #ifdef CONFIG_MLX5_CORE_EN_DCB
 138 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 139 #define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */
 140 #endif
 141
 142 static const char vport_strings[][ETH_GSTRING_LEN] = {
 143         /* vport statistics */
 144         "rx_packets",
 145         "rx_bytes",
 146         "tx_packets",
 147         "tx_bytes",
 148         "rx_error_packets",
 149         "rx_error_bytes",
 150         "tx_error_packets",
 151         "tx_error_bytes",
 152         "rx_unicast_packets",
 153         "rx_unicast_bytes",
 154         "tx_unicast_packets",
 155         "tx_unicast_bytes",
 156         "rx_multicast_packets",
 157         "rx_multicast_bytes",
 158         "tx_multicast_packets",
 159         "tx_multicast_bytes",
 160         "rx_broadcast_packets",
 161         "rx_broadcast_bytes",
 162         "tx_broadcast_packets",
 163         "tx_broadcast_bytes",
 164
 165         /* SW counters */
 166         "tso_packets",
 167         "tso_bytes",
 168         "tso_inner_packets",
 169         "tso_inner_bytes",
 170         "lro_packets",
 171         "lro_bytes",
 172         "rx_csum_good",
 173         "rx_csum_none",
 174         "rx_csum_sw",
 175         "tx_csum_offload",
 176         "tx_csum_inner",
 177         "tx_queue_stopped",
 178         "tx_queue_wake",
 179         "tx_queue_dropped",
 180         "rx_wqe_err",
 181         "rx_mpwqe_filler",
 182 };
 183
 184 struct mlx5e_vport_stats {
 185         /* HW counters */
 186         u64 rx_packets;
 187         u64 rx_bytes;
 188         u64 tx_packets;
 189         u64 tx_bytes;
 190         u64 rx_error_packets;
 191         u64 rx_error_bytes;
 192         u64 tx_error_packets;
 193         u64 tx_error_bytes;
 194         u64 rx_unicast_packets;
 195         u64 rx_unicast_bytes;
 196         u64 tx_unicast_packets;
 197         u64 tx_unicast_bytes;
 198         u64 rx_multicast_packets;
 199         u64 rx_multicast_bytes;
 200         u64 tx_multicast_packets;
 201         u64 tx_multicast_bytes;
 202         u64 rx_broadcast_packets;
 203         u64 rx_broadcast_bytes;
 204         u64 tx_broadcast_packets;
 205         u64 tx_broadcast_bytes;
 206
 207         /* SW counters */
 208         u64 tso_packets;
 209         u64 tso_bytes;
 210         u64 tso_inner_packets;
 211         u64 tso_inner_bytes;
 212         u64 lro_packets;
 213         u64 lro_bytes;
 214         u64 rx_csum_good;
 215         u64 rx_csum_none;
 216         u64 rx_csum_sw;
 217         u64 tx_csum_offload;
 218         u64 tx_csum_inner;
 219         u64 tx_queue_stopped;
 220         u64 tx_queue_wake;
 221         u64 tx_queue_dropped;
 222         u64 rx_wqe_err;
 223         u64 rx_mpwqe_filler;
 224
 225 #define NUM_VPORT_COUNTERS     36
 226 };
 227
 228 static const char pport_strings[][ETH_GSTRING_LEN] = {
 229         /* IEEE802.3 counters */
 230         "frames_tx",
 231         "frames_rx",
 232         "check_seq_err",
 233         "alignment_err",
 234         "octets_tx",
 235         "octets_received",
 236         "multicast_xmitted",
 237         "broadcast_xmitted",
 238         "multicast_rx",
 239         "broadcast_rx",
 240         "in_range_len_errors",
 241         "out_of_range_len",
 242         "too_long_errors",
 243         "symbol_err",
 244         "mac_control_tx",
 245         "mac_control_rx",
 246         "unsupported_op_rx",
 247         "pause_ctrl_rx",
 248         "pause_ctrl_tx",
 249
 250         /* RFC2863 counters */
 251         "in_octets",
 252         "in_ucast_pkts",
 253         "in_discards",
 254         "in_errors",
 255         "in_unknown_protos",
 256         "out_octets",
 257         "out_ucast_pkts",
 258         "out_discards",
 259         "out_errors",
 260         "in_multicast_pkts",
 261         "in_broadcast_pkts",
 262         "out_multicast_pkts",
 263         "out_broadcast_pkts",
 264
 265         /* RFC2819 counters */
 266         "drop_events",
 267         "octets",
 268         "pkts",
 269         "broadcast_pkts",
 270         "multicast_pkts",
 271         "crc_align_errors",
 272         "undersize_pkts",
 273         "oversize_pkts",
 274         "fragments",
 275         "jabbers",
 276         "collisions",
 277         "p64octets",
 278         "p65to127octets",
 279         "p128to255octets",
 280         "p256to511octets",
 281         "p512to1023octets",
 282         "p1024to1518octets",
 283         "p1519to2047octets",
 284         "p2048to4095octets",
 285         "p4096to8191octets",
 286         "p8192to10239octets",
 287 };
 288
 289 #define NUM_IEEE_802_3_COUNTERS         19
 290 #define NUM_RFC_2863_COUNTERS           13
 291 #define NUM_RFC_2819_COUNTERS           21
 292 #define NUM_PPORT_COUNTERS              (NUM_IEEE_802_3_COUNTERS + \
 293                                          NUM_RFC_2863_COUNTERS + \
 294                                          NUM_RFC_2819_COUNTERS)
 295
 296 struct mlx5e_pport_stats {
 297         __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
 298         __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
 299         __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
 300 };
 301
 302 static const char qcounter_stats_strings[][ETH_GSTRING_LEN] = {
 303         "rx_out_of_buffer",
 304 };
 305
 306 struct mlx5e_qcounter_stats {
 307         u32 rx_out_of_buffer;
 308 #define NUM_Q_COUNTERS 1
 309 };
 310
 311 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
 312         "packets",
 313         "bytes",
 314         "csum_none",
 315         "csum_sw",
 316         "lro_packets",
 317         "lro_bytes",
 318         "wqe_err",
 319         "mpwqe_filler",
 320 };
 321
 322 struct mlx5e_rq_stats {
 323         u64 packets;
 324         u64 bytes;
 325         u64 csum_none;
 326         u64 csum_sw;
 327         u64 lro_packets;
 328         u64 lro_bytes;
 329         u64 wqe_err;
 330         u64 mpwqe_filler;
 331 #define NUM_RQ_STATS 8
 332 };
 333
 334 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
 335         "packets",
 336         "bytes",
 337         "tso_packets",
 338         "tso_bytes",
 339         "tso_inner_packets",
 340         "tso_inner_bytes",
 341         "csum_offload_inner",
 342         "nop",
 343         "csum_offload_none",
 344         "stopped",
 345         "wake",
 346         "dropped",
 347 };
 348
 349 struct mlx5e_sq_stats {
 350         /* commonly accessed in data path */
 351         u64 packets;
 352         u64 bytes;
 353         u64 tso_packets;
 354         u64 tso_bytes;
 355         u64 tso_inner_packets;
 356         u64 tso_inner_bytes;
 357         u64 csum_offload_inner;
 358         u64 nop;
 359         /* less likely accessed in data path */
 360         u64 csum_offload_none;
 361         u64 stopped;
 362         u64 wake;
 363         u64 dropped;
 364 #define NUM_SQ_STATS 12
 365 };
 366
 367 struct mlx5e_stats {
 368         struct mlx5e_vport_stats   vport;
 369         struct mlx5e_pport_stats   pport;
 370         struct mlx5e_qcounter_stats qcnt;
 371 };
 372
 373 struct mlx5e_params {
 374         u8  log_sq_size;
 375         u8  rq_wq_type;
 376         u8  log_rq_size;
 377         u16 num_channels;
 378         u8  num_tc;
 379         u16 rx_cq_moderation_usec;
 380         u16 rx_cq_moderation_pkts;
 381         u16 tx_cq_moderation_usec;
 382         u16 tx_cq_moderation_pkts;
 383         u16 min_rx_wqes;
 384         bool lro_en;
 385         u32 lro_wqe_sz;
 386         u16 tx_max_inline;
 387         u8  rss_hfunc;
 388         u8  toeplitz_hash_key[40];
 389         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 390 #ifdef CONFIG_MLX5_CORE_EN_DCB
 391         struct ieee_ets ets;
 392 #endif
 393 };
 394
 395 struct mlx5e_tstamp {
 396         rwlock_t                   lock;
 397         struct cyclecounter        cycles;
 398         struct timecounter         clock;
 399         struct hwtstamp_config     hwtstamp_config;
 400         u32                        nominal_c_mult;
 401         unsigned long              overflow_period;
 402         struct delayed_work        overflow_work;
 403         struct mlx5_core_dev      *mdev;
 404         struct ptp_clock          *ptp;
 405         struct ptp_clock_info      ptp_info;
 406 };
 407
 408 enum {
 409         MLX5E_RQ_STATE_POST_WQES_ENABLE,
 410 };
 411
 412 struct mlx5e_cq {
 413         /* data path - accessed per cqe */
 414         struct mlx5_cqwq           wq;
 415
 416         /* data path - accessed per napi poll */
 417         struct napi_struct        *napi;
 418         struct mlx5_core_cq        mcq;
 419         struct mlx5e_channel      *channel;
 420         struct mlx5e_priv         *priv;
 421
 422         /* control */
 423         struct mlx5_wq_ctrl        wq_ctrl;
 424 } ____cacheline_aligned_in_smp;
 425
 426 struct mlx5e_rq;
 427 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
 428                                        struct mlx5_cqe64 *cqe);
 429 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
 430                                   u16 ix);
 431
 432 struct mlx5e_dma_info {
 433         struct page     *page;
 434         dma_addr_t      addr;
 435 };
 436
 437 struct mlx5e_mpw_info {
 438         struct mlx5e_dma_info dma_info;
 439         u16 consumed_strides;
 440         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 441 };
 442
 443 struct mlx5e_rq {
 444         /* data path */
 445         struct mlx5_wq_ll      wq;
 446         u32                    wqe_sz;
 447         struct sk_buff       **skb;
 448         struct mlx5e_mpw_info *wqe_info;
 449
 450         struct device         *pdev;
 451         struct net_device     *netdev;
 452         struct mlx5e_tstamp   *tstamp;
 453         struct mlx5e_rq_stats  stats;
 454         struct mlx5e_cq        cq;
 455         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 456         mlx5e_fp_alloc_wqe     alloc_wqe;
 457
 458         unsigned long          state;
 459         int                    ix;
 460
 461         /* control */
 462         struct mlx5_wq_ctrl    wq_ctrl;
 463         u8                     wq_type;
 464         u32                    rqn;
 465         struct mlx5e_channel  *channel;
 466         struct mlx5e_priv     *priv;
 467 } ____cacheline_aligned_in_smp;
 468
 469 struct mlx5e_tx_wqe_info {
 470         u32 num_bytes;
 471         u8  num_wqebbs;
 472         u8  num_dma;
 473 };
 474
 475 enum mlx5e_dma_map_type {
 476         MLX5E_DMA_MAP_SINGLE,
 477         MLX5E_DMA_MAP_PAGE
 478 };
 479
 480 struct mlx5e_sq_dma {
 481         dma_addr_t              addr;
 482         u32                     size;
 483         enum mlx5e_dma_map_type type;
 484 };
 485
 486 enum {
 487         MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
 488         MLX5E_SQ_STATE_BF_ENABLE,
 489 };
 490
 491 struct mlx5e_ico_wqe_info {
 492         u8  opcode;
 493         u8  num_wqebbs;
 494 };
 495
 496 struct mlx5e_sq {
 497         /* data path */
 498
 499         /* dirtied @completion */
 500         u16                        cc;
 501         u32                        dma_fifo_cc;
 502
 503         /* dirtied @xmit */
 504         u16                        pc ____cacheline_aligned_in_smp;
 505         u32                        dma_fifo_pc;
 506         u16                        bf_offset;
 507         u16                        prev_cc;
 508         u8                         bf_budget;
 509         struct mlx5e_sq_stats      stats;
 510
 511         struct mlx5e_cq            cq;
 512
 513         /* pointers to per packet info: write@xmit, read@completion */
 514         struct sk_buff           **skb;
 515         struct mlx5e_sq_dma       *dma_fifo;
 516         struct mlx5e_tx_wqe_info  *wqe_info;
 517
 518         /* read only */
 519         struct mlx5_wq_cyc         wq;
 520         u32                        dma_fifo_mask;
 521         void __iomem              *uar_map;
 522         struct netdev_queue       *txq;
 523         u32                        sqn;
 524         u16                        bf_buf_size;
 525         u16                        max_inline;
 526         u16                        edge;
 527         struct device             *pdev;
 528         struct mlx5e_tstamp       *tstamp;
 529         __be32                     mkey_be;
 530         unsigned long              state;
 531
 532         /* control path */
 533         struct mlx5_wq_ctrl        wq_ctrl;
 534         struct mlx5_uar            uar;
 535         struct mlx5e_channel      *channel;
 536         int                        tc;
 537         struct mlx5e_ico_wqe_info *ico_wqe_info;
 538 } ____cacheline_aligned_in_smp;
 539
 540 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 541 {
 542         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 543                 (sq->cc  == sq->pc));
 544 }
 545
 546 enum channel_flags {
 547         MLX5E_CHANNEL_NAPI_SCHED = 1,
 548 };
 549
 550 struct mlx5e_channel {
 551         /* data path */
 552         struct mlx5e_rq            rq;
 553         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 554         struct mlx5e_sq            icosq;   /* internal control operations */
 555         struct napi_struct         napi;
 556         struct device             *pdev;
 557         struct net_device         *netdev;
 558         __be32                     mkey_be;
 559         u8                         num_tc;
 560         unsigned long              flags;
 561
 562         /* control */
 563         struct mlx5e_priv         *priv;
 564         int                        ix;
 565         int                        cpu;
 566 };
 567
 568 enum mlx5e_traffic_types {
 569         MLX5E_TT_IPV4_TCP,
 570         MLX5E_TT_IPV6_TCP,
 571         MLX5E_TT_IPV4_UDP,
 572         MLX5E_TT_IPV6_UDP,
 573         MLX5E_TT_IPV4_IPSEC_AH,
 574         MLX5E_TT_IPV6_IPSEC_AH,
 575         MLX5E_TT_IPV4_IPSEC_ESP,
 576         MLX5E_TT_IPV6_IPSEC_ESP,
 577         MLX5E_TT_IPV4,
 578         MLX5E_TT_IPV6,
 579         MLX5E_TT_ANY,
 580         MLX5E_NUM_TT,
 581 };
 582
 583 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
 584
 585 enum mlx5e_rqt_ix {
 586         MLX5E_INDIRECTION_RQT,
 587         MLX5E_SINGLE_RQ_RQT,
 588         MLX5E_NUM_RQT,
 589 };
 590
 591 struct mlx5e_eth_addr_info {
 592         u8  addr[ETH_ALEN + 2];
 593         u32 tt_vec;
 594         struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
 595 };
 596
 597 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
 598
 599 struct mlx5e_eth_addr_db {
 600         struct hlist_head          netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
 601         struct hlist_head          netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
 602         struct mlx5e_eth_addr_info broadcast;
 603         struct mlx5e_eth_addr_info allmulti;
 604         struct mlx5e_eth_addr_info promisc;
 605         bool                       broadcast_enabled;
 606         bool                       allmulti_enabled;
 607         bool                       promisc_enabled;
 608 };
 609
 610 enum {
 611         MLX5E_STATE_ASYNC_EVENTS_ENABLE,
 612         MLX5E_STATE_OPENED,
 613         MLX5E_STATE_DESTROYING,
 614 };
 615
 616 struct mlx5e_vlan_db {
 617         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 618         struct mlx5_flow_rule   *active_vlans_rule[VLAN_N_VID];
 619         struct mlx5_flow_rule   *untagged_rule;
 620         struct mlx5_flow_rule   *any_vlan_rule;
 621         bool          filter_disabled;
 622 };
 623
 624 struct mlx5e_vxlan_db {
 625         spinlock_t                      lock; /* protect vxlan table */
 626         struct radix_tree_root          tree;
 627 };
 628
 629 struct mlx5e_flow_table {
 630         int num_groups;
 631         struct mlx5_flow_table          *t;
 632         struct mlx5_flow_group          **g;
 633 };
 634
 635 struct mlx5e_tc_flow_table {
 636         struct mlx5_flow_table          *t;
 637
 638         struct rhashtable_params        ht_params;
 639         struct rhashtable               ht;
 640 };
 641
 642 struct mlx5e_flow_tables {
 643         struct mlx5_flow_namespace      *ns;
 644         struct mlx5e_tc_flow_table      tc;
 645         struct mlx5e_flow_table         vlan;
 646         struct mlx5e_flow_table         main;
 647 };
 648
 649 struct mlx5e_priv {
 650         /* priv data path fields - start */
 651         struct mlx5e_sq            **txq_to_sq_map;
 652         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 653         /* priv data path fields - end */
 654
 655         unsigned long              state;
 656         struct mutex               state_lock; /* Protects Interface state */
 657         struct mlx5_uar            cq_uar;
 658         u32                        pdn;
 659         u32                        tdn;
 660         struct mlx5_core_mkey      mkey;
 661         struct mlx5e_rq            drop_rq;
 662
 663         struct mlx5e_channel     **channel;
 664         u32                        tisn[MLX5E_MAX_NUM_TC];
 665         u32                        rqtn[MLX5E_NUM_RQT];
 666         u32                        tirn[MLX5E_NUM_TT];
 667
 668         struct mlx5e_flow_tables   fts;
 669         struct mlx5e_eth_addr_db   eth_addr;
 670         struct mlx5e_vlan_db       vlan;
 671         struct mlx5e_vxlan_db      vxlan;
 672
 673         struct mlx5e_params        params;
 674         struct work_struct         update_carrier_work;
 675         struct work_struct         set_rx_mode_work;
 676         struct delayed_work        update_stats_work;
 677
 678         struct mlx5_core_dev      *mdev;
 679         struct net_device         *netdev;
 680         struct mlx5e_stats         stats;
 681         struct mlx5e_tstamp        tstamp;
 682         u16 q_counter;
 683 };
 684
 685 enum mlx5e_link_mode {
 686         MLX5E_1000BASE_CX_SGMII  = 0,
 687         MLX5E_1000BASE_KX        = 1,
 688         MLX5E_10GBASE_CX4        = 2,
 689         MLX5E_10GBASE_KX4        = 3,
 690         MLX5E_10GBASE_KR         = 4,
 691         MLX5E_20GBASE_KR2        = 5,
 692         MLX5E_40GBASE_CR4        = 6,
 693         MLX5E_40GBASE_KR4        = 7,
 694         MLX5E_56GBASE_R4         = 8,
 695         MLX5E_10GBASE_CR         = 12,
 696         MLX5E_10GBASE_SR         = 13,
 697         MLX5E_10GBASE_ER         = 14,
 698         MLX5E_40GBASE_SR4        = 15,
 699         MLX5E_40GBASE_LR4        = 16,
 700         MLX5E_100GBASE_CR4       = 20,
 701         MLX5E_100GBASE_SR4       = 21,
 702         MLX5E_100GBASE_KR4       = 22,
 703         MLX5E_100GBASE_LR4       = 23,
 704         MLX5E_100BASE_TX         = 24,
 705         MLX5E_100BASE_T          = 25,
 706         MLX5E_10GBASE_T          = 26,
 707         MLX5E_25GBASE_CR         = 27,
 708         MLX5E_25GBASE_KR         = 28,
 709         MLX5E_25GBASE_SR         = 29,
 710         MLX5E_50GBASE_CR2        = 30,
 711         MLX5E_50GBASE_KR2        = 31,
 712         MLX5E_LINK_MODES_NUMBER,
 713 };
 714
 715 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
 716
 717 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 718 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 719                        void *accel_priv, select_queue_fallback_t fallback);
 720 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 721
 722 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 723 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 724 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 725 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 726 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 727
 728 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 729 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 730 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 731 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 732 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 733 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 734
 735 void mlx5e_update_stats(struct mlx5e_priv *priv);
 736
 737 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
 738 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
 739 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
 740 void mlx5e_set_rx_mode_work(struct work_struct *work);
 741
 742 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 743                         struct skb_shared_hwtstamps *hwts);
 744 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 745 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 746 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 747 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 748
 749 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 750                           u16 vid);
 751 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 752                            u16 vid);
 753 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 754 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 755
 756 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
 757 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
 758
 759 int mlx5e_open_locked(struct net_device *netdev);
 760 int mlx5e_close_locked(struct net_device *netdev);
 761 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 762                                    u32 *indirection_rqt, int len,
 763                                    int num_channels);
 764
 765 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
 766                                       struct mlx5e_tx_wqe *wqe, int bf_sz)
 767 {
 768         u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
 769
 770         /* ensure wqe is visible to device before updating doorbell record */
 771         dma_wmb();
 772
 773         *sq->wq.db = cpu_to_be32(sq->pc);
 774
 775         /* ensure doorbell record is visible to device before ringing the
 776          * doorbell
 777          */
 778         wmb();
 779         if (bf_sz)
 780                 __iowrite64_copy(sq->uar_map + ofst, &wqe->ctrl, bf_sz);
 781         else
 782                 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
 783         /* flush the write-combining mapped buffer */
 784         wmb();
 785
 786         sq->bf_offset ^= sq->bf_buf_size;
 787 }
 788
 789 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 790 {
 791         struct mlx5_core_cq *mcq;
 792
 793         mcq = &cq->mcq;
 794         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
 795 }
 796
 797 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 798 {
 799         return min_t(int, mdev->priv.eq_table.num_comp_vectors,
 800                      MLX5E_MAX_NUM_CHANNELS);
 801 }
 802
 803 extern const struct ethtool_ops mlx5e_ethtool_ops;
 804 #ifdef CONFIG_MLX5_CORE_EN_DCB
 805 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 806 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 807 #endif
 808
 809 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 810
 811 #endif /* __MLX5_EN_H__ */