2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/rhashtable.h>
48 #include <net/switchdev.h>
50 #include "mlx5_core.h"
53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
55 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
57 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
58 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
60 #define MLX5E_MAX_DSCP 64
61 #define MLX5E_MAX_NUM_TC 8
63 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
64 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
65 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
71 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
72 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
73 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
80 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
81 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
82 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
83 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
84 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
86 #define MLX5_MPWRQ_LOG_WQE_SZ 18
87 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
88 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
89 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
90 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
91 MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
94 #define MLX5E_REQUIRED_MTTS(wqes) \
95 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
98 #define MLX5_UMR_ALIGN (2048)
99 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
101 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
102 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
103 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
105 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
106 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
107 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
108 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
109 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
110 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
111 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
112 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
114 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
115 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
116 #define MLX5E_MIN_NUM_CHANNELS 0x1
117 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
118 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
119 #define MLX5E_TX_CQ_POLL_BUDGET 128
120 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
122 #define MLX5E_ICOSQ_MAX_WQEBBS \
123 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
125 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
126 #define MLX5E_XDP_TX_DS_COUNT \
127 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
129 #define MLX5E_NUM_MAIN_GROUPS 9
131 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
133 #define mlx5e_dbg(mlevel, priv, format, ...) \
135 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
136 netdev_warn(priv->netdev, format, \
141 static inline u16
mlx5_min_rx_wqes(int wq_type
, u32 wq_size
)
144 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
145 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW
,
148 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
,
153 static inline int mlx5_min_log_rq_size(int wq_type
)
156 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
157 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
;
159 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
;
163 static inline int mlx5_max_log_rq_size(int wq_type
)
166 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
167 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW
;
169 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE
;
173 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
175 return is_kdump_kernel() ?
176 MLX5E_MIN_NUM_CHANNELS
:
177 min_t(int, mdev
->priv
.eq_table
.num_comp_vectors
,
178 MLX5E_MAX_NUM_CHANNELS
);
181 struct mlx5e_tx_wqe
{
182 struct mlx5_wqe_ctrl_seg ctrl
;
183 struct mlx5_wqe_eth_seg eth
;
186 struct mlx5e_rx_wqe
{
187 struct mlx5_wqe_srq_next_seg next
;
188 struct mlx5_wqe_data_seg data
;
191 struct mlx5e_umr_wqe
{
192 struct mlx5_wqe_ctrl_seg ctrl
;
193 struct mlx5_wqe_umr_ctrl_seg uctrl
;
194 struct mlx5_mkey_seg mkc
;
195 struct mlx5_wqe_data_seg data
;
198 extern const char mlx5e_self_tests
[][ETH_GSTRING_LEN
];
200 static const char mlx5e_priv_flags
[][ETH_GSTRING_LEN
] = {
206 enum mlx5e_priv_flag
{
207 MLX5E_PFLAG_RX_CQE_BASED_MODER
= (1 << 0),
208 MLX5E_PFLAG_TX_CQE_BASED_MODER
= (1 << 1),
209 MLX5E_PFLAG_RX_CQE_COMPRESS
= (1 << 2),
212 #define MLX5E_SET_PFLAG(params, pflag, enable) \
215 (params)->pflags |= (pflag); \
217 (params)->pflags &= ~(pflag); \
220 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
222 #ifdef CONFIG_MLX5_CORE_EN_DCB
223 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
226 struct mlx5e_cq_moder
{
232 struct mlx5e_params
{
236 u8 mpwqe_log_stride_sz
;
237 u8 mpwqe_log_num_strides
;
241 bool rx_cqe_compress_def
;
242 struct mlx5e_cq_moder rx_cq_moderation
;
243 struct mlx5e_cq_moder tx_cq_moderation
;
247 u8 tx_min_inline_mode
;
249 u8 toeplitz_hash_key
[40];
250 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
251 bool vlan_strip_disable
;
256 struct bpf_prog
*xdp_prog
;
259 #ifdef CONFIG_MLX5_CORE_EN_DCB
260 struct mlx5e_cee_config
{
261 /* bw pct for priority group */
262 u8 pg_bw_pct
[CEE_DCBX_MAX_PGS
];
263 u8 prio_to_pg_map
[CEE_DCBX_MAX_PRIO
];
264 bool pfc_setting
[CEE_DCBX_MAX_PRIO
];
271 MLX5_DCB_CHG_NO_RESET
,
275 enum mlx5_dcbx_oper_mode mode
;
276 struct mlx5e_cee_config cee_cfg
; /* pending configuration */
279 /* The only setting that cannot be read from FW */
280 u8 tc_tsa
[IEEE_8021QAZ_MAX_TCS
];
284 struct mlx5e_dcbx_dp
{
285 u8 dscp2prio
[MLX5E_MAX_DSCP
];
291 MLX5E_RQ_STATE_ENABLED
,
295 #define MLX5E_TEST_BIT(state, nr) (state & BIT(nr))
298 /* data path - accessed per cqe */
301 /* data path - accessed per napi poll */
303 struct napi_struct
*napi
;
304 struct mlx5_core_cq mcq
;
305 struct mlx5e_channel
*channel
;
307 /* cqe decompression */
308 struct mlx5_cqe64 title
;
309 struct mlx5_mini_cqe8 mini_arr
[MLX5_MINI_CQE_ARRAY_SIZE
];
312 u16 decmprs_wqe_counter
;
315 struct mlx5_core_dev
*mdev
;
316 struct mlx5_frag_wq_ctrl wq_ctrl
;
317 } ____cacheline_aligned_in_smp
;
319 struct mlx5e_tx_wqe_info
{
326 enum mlx5e_dma_map_type
{
327 MLX5E_DMA_MAP_SINGLE
,
331 struct mlx5e_sq_dma
{
334 enum mlx5e_dma_map_type type
;
338 MLX5E_SQ_STATE_ENABLED
,
339 MLX5E_SQ_STATE_IPSEC
,
342 struct mlx5e_sq_wqe_info
{
349 /* dirtied @completion */
354 u16 pc ____cacheline_aligned_in_smp
;
356 struct mlx5e_sq_stats stats
;
360 /* write@xmit, read@completion */
362 struct mlx5e_sq_dma
*dma_fifo
;
363 struct mlx5e_tx_wqe_info
*wqe_info
;
367 struct mlx5_wq_cyc wq
;
369 void __iomem
*uar_map
;
370 struct netdev_queue
*txq
;
378 struct hwtstamp_config
*tstamp
;
379 struct mlx5_clock
*clock
;
382 struct mlx5_wq_ctrl wq_ctrl
;
383 struct mlx5e_channel
*channel
;
386 } ____cacheline_aligned_in_smp
;
391 /* dirtied @rx completion */
397 /* write@xmit, read@completion */
399 struct mlx5e_dma_info
*di
;
404 struct mlx5_wq_cyc wq
;
405 void __iomem
*uar_map
;
413 struct mlx5_wq_ctrl wq_ctrl
;
414 struct mlx5e_channel
*channel
;
415 } ____cacheline_aligned_in_smp
;
421 u16 pc ____cacheline_aligned_in_smp
;
425 /* write@xmit, read@completion */
427 struct mlx5e_sq_wqe_info
*ico_wqe
;
431 struct mlx5_wq_cyc wq
;
432 void __iomem
*uar_map
;
439 struct mlx5_wq_ctrl wq_ctrl
;
440 struct mlx5e_channel
*channel
;
441 } ____cacheline_aligned_in_smp
;
444 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc
*wq
, u16 cc
, u16 pc
, u16 n
)
446 return (((wq
->sz_m1
& (cc
- pc
)) >= n
) || (cc
== pc
));
449 struct mlx5e_dma_info
{
454 struct mlx5e_wqe_frag_info
{
455 struct mlx5e_dma_info di
;
459 struct mlx5e_umr_dma_info
{
462 struct mlx5e_dma_info dma_info
[MLX5_MPWRQ_PAGES_PER_WQE
];
463 struct mlx5e_umr_wqe wqe
;
466 struct mlx5e_mpw_info
{
467 struct mlx5e_umr_dma_info umr
;
468 u16 consumed_strides
;
469 u16 skbs_frags
[MLX5_MPWRQ_PAGES_PER_WQE
];
472 struct mlx5e_rx_am_stats
{
473 int ppms
; /* packets per msec */
474 int bpms
; /* bytes per msec */
475 int epms
; /* events per msec */
478 struct mlx5e_rx_am_sample
{
485 struct mlx5e_rx_am
{ /* Adaptive Moderation */
487 struct mlx5e_rx_am_stats prev_stats
;
488 struct mlx5e_rx_am_sample start_sample
;
489 struct work_struct work
;
498 /* a single cache unit is capable to serve one napi call (for non-striding rq)
499 * or a MPWQE (for striding rq).
501 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
502 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
503 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
504 struct mlx5e_page_cache
{
507 struct mlx5e_dma_info page_cache
[MLX5E_CACHE_SIZE
];
511 typedef void (*mlx5e_fp_handle_rx_cqe
)(struct mlx5e_rq
*, struct mlx5_cqe64
*);
512 typedef bool (*mlx5e_fp_post_rx_wqes
)(struct mlx5e_rq
*rq
);
513 typedef void (*mlx5e_fp_dealloc_wqe
)(struct mlx5e_rq
*, u16
);
517 struct mlx5_wq_ll wq
;
521 struct mlx5e_wqe_frag_info
*frag_info
;
522 u32 frag_sz
; /* max possible skb frag_sz */
529 struct mlx5e_mpw_info
*info
;
533 bool umr_in_progress
;
539 u8 map_dir
; /* dma map direction */
542 struct mlx5e_channel
*channel
;
544 struct net_device
*netdev
;
545 struct mlx5e_rq_stats stats
;
547 struct mlx5e_page_cache page_cache
;
548 struct hwtstamp_config
*tstamp
;
549 struct mlx5_clock
*clock
;
551 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
552 mlx5e_fp_post_rx_wqes post_wqes
;
553 mlx5e_fp_dealloc_wqe dealloc_wqe
;
558 struct mlx5e_rx_am am
; /* Adaptive Moderation */
561 struct bpf_prog
*xdp_prog
;
562 struct mlx5e_xdpsq xdpsq
;
565 struct mlx5_wq_ctrl wq_ctrl
;
569 struct mlx5_core_dev
*mdev
;
570 struct mlx5_core_mkey umr_mkey
;
571 } ____cacheline_aligned_in_smp
;
573 struct mlx5e_channel
{
576 struct mlx5e_txqsq sq
[MLX5E_MAX_NUM_TC
];
577 struct mlx5e_icosq icosq
; /* internal control operations */
579 struct napi_struct napi
;
581 struct net_device
*netdev
;
585 /* data path - accessed per napi poll */
586 struct irq_desc
*irq_desc
;
589 struct mlx5e_priv
*priv
;
590 struct mlx5_core_dev
*mdev
;
591 struct hwtstamp_config
*tstamp
;
595 struct mlx5e_channels
{
596 struct mlx5e_channel
**c
;
598 struct mlx5e_params params
;
601 enum mlx5e_traffic_types
{
606 MLX5E_TT_IPV4_IPSEC_AH
,
607 MLX5E_TT_IPV6_IPSEC_AH
,
608 MLX5E_TT_IPV4_IPSEC_ESP
,
609 MLX5E_TT_IPV6_IPSEC_ESP
,
614 MLX5E_NUM_INDIR_TIRS
= MLX5E_TT_ANY
,
617 enum mlx5e_tunnel_types
{
624 MLX5E_STATE_ASYNC_EVENTS_ENABLED
,
626 MLX5E_STATE_DESTROYING
,
629 struct mlx5e_vxlan_db
{
630 spinlock_t lock
; /* protect vxlan table */
631 struct radix_tree_root tree
;
634 struct mlx5e_l2_rule
{
635 u8 addr
[ETH_ALEN
+ 2];
636 struct mlx5_flow_handle
*rule
;
639 struct mlx5e_flow_table
{
641 struct mlx5_flow_table
*t
;
642 struct mlx5_flow_group
**g
;
645 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
647 struct mlx5e_tc_table
{
648 struct mlx5_flow_table
*t
;
650 struct rhashtable_params ht_params
;
651 struct rhashtable ht
;
653 DECLARE_HASHTABLE(mod_hdr_tbl
, 8);
656 struct mlx5e_vlan_table
{
657 struct mlx5e_flow_table ft
;
658 DECLARE_BITMAP(active_cvlans
, VLAN_N_VID
);
659 DECLARE_BITMAP(active_svlans
, VLAN_N_VID
);
660 struct mlx5_flow_handle
*active_cvlans_rule
[VLAN_N_VID
];
661 struct mlx5_flow_handle
*active_svlans_rule
[VLAN_N_VID
];
662 struct mlx5_flow_handle
*untagged_rule
;
663 struct mlx5_flow_handle
*any_cvlan_rule
;
664 struct mlx5_flow_handle
*any_svlan_rule
;
665 bool cvlan_filter_disabled
;
668 struct mlx5e_l2_table
{
669 struct mlx5e_flow_table ft
;
670 struct hlist_head netdev_uc
[MLX5E_L2_ADDR_HASH_SIZE
];
671 struct hlist_head netdev_mc
[MLX5E_L2_ADDR_HASH_SIZE
];
672 struct mlx5e_l2_rule broadcast
;
673 struct mlx5e_l2_rule allmulti
;
674 struct mlx5e_l2_rule promisc
;
675 bool broadcast_enabled
;
676 bool allmulti_enabled
;
677 bool promisc_enabled
;
680 /* L3/L4 traffic type classifier */
681 struct mlx5e_ttc_table
{
682 struct mlx5e_flow_table ft
;
683 struct mlx5_flow_handle
*rules
[MLX5E_NUM_TT
];
684 struct mlx5_flow_handle
*tunnel_rules
[MLX5E_NUM_TUNNEL_TT
];
687 #define ARFS_HASH_SHIFT BITS_PER_BYTE
688 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
690 struct mlx5e_flow_table ft
;
691 struct mlx5_flow_handle
*default_rule
;
692 struct hlist_head rules_hash
[ARFS_HASH_SIZE
];
703 struct mlx5e_arfs_tables
{
704 struct arfs_table arfs_tables
[ARFS_NUM_TYPES
];
705 /* Protect aRFS rules list */
706 spinlock_t arfs_lock
;
707 struct list_head rules
;
709 struct workqueue_struct
*wq
;
714 MLX5E_VLAN_FT_LEVEL
= 0,
717 MLX5E_INNER_TTC_FT_LEVEL
,
721 struct mlx5e_ethtool_table
{
722 struct mlx5_flow_table
*ft
;
726 #define ETHTOOL_NUM_L3_L4_FTS 7
727 #define ETHTOOL_NUM_L2_FTS 4
729 struct mlx5e_ethtool_steering
{
730 struct mlx5e_ethtool_table l3_l4_ft
[ETHTOOL_NUM_L3_L4_FTS
];
731 struct mlx5e_ethtool_table l2_ft
[ETHTOOL_NUM_L2_FTS
];
732 struct list_head rules
;
736 struct mlx5e_flow_steering
{
737 struct mlx5_flow_namespace
*ns
;
738 struct mlx5e_ethtool_steering ethtool
;
739 struct mlx5e_tc_table tc
;
740 struct mlx5e_vlan_table vlan
;
741 struct mlx5e_l2_table l2
;
742 struct mlx5e_ttc_table ttc
;
743 struct mlx5e_ttc_table inner_ttc
;
744 struct mlx5e_arfs_tables arfs
;
754 struct mlx5e_rqt rqt
;
755 struct list_head list
;
764 /* priv data path fields - start */
765 struct mlx5e_txqsq
*txq2sq
[MLX5E_MAX_NUM_CHANNELS
* MLX5E_MAX_NUM_TC
];
766 int channel_tc2txq
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
767 #ifdef CONFIG_MLX5_CORE_EN_DCB
768 struct mlx5e_dcbx_dp dcbx_dp
;
770 /* priv data path fields - end */
774 struct mutex state_lock
; /* Protects Interface state */
775 struct mlx5e_rq drop_rq
;
777 struct mlx5e_channels channels
;
778 u32 tisn
[MLX5E_MAX_NUM_TC
];
779 struct mlx5e_rqt indir_rqt
;
780 struct mlx5e_tir indir_tir
[MLX5E_NUM_INDIR_TIRS
];
781 struct mlx5e_tir inner_indir_tir
[MLX5E_NUM_INDIR_TIRS
];
782 struct mlx5e_tir direct_tir
[MLX5E_MAX_NUM_CHANNELS
];
783 u32 tx_rates
[MLX5E_MAX_NUM_SQS
];
786 struct mlx5e_flow_steering fs
;
787 struct mlx5e_vxlan_db vxlan
;
789 struct workqueue_struct
*wq
;
790 struct work_struct update_carrier_work
;
791 struct work_struct set_rx_mode_work
;
792 struct work_struct tx_timeout_work
;
793 struct delayed_work update_stats_work
;
795 struct mlx5_core_dev
*mdev
;
796 struct net_device
*netdev
;
797 struct mlx5e_stats stats
;
798 struct hwtstamp_config tstamp
;
800 #ifdef CONFIG_MLX5_CORE_EN_DCB
801 struct mlx5e_dcbx dcbx
;
804 const struct mlx5e_profile
*profile
;
806 #ifdef CONFIG_MLX5_EN_IPSEC
807 struct mlx5e_ipsec
*ipsec
;
811 struct mlx5e_profile
{
812 void (*init
)(struct mlx5_core_dev
*mdev
,
813 struct net_device
*netdev
,
814 const struct mlx5e_profile
*profile
, void *ppriv
);
815 void (*cleanup
)(struct mlx5e_priv
*priv
);
816 int (*init_rx
)(struct mlx5e_priv
*priv
);
817 void (*cleanup_rx
)(struct mlx5e_priv
*priv
);
818 int (*init_tx
)(struct mlx5e_priv
*priv
);
819 void (*cleanup_tx
)(struct mlx5e_priv
*priv
);
820 void (*enable
)(struct mlx5e_priv
*priv
);
821 void (*disable
)(struct mlx5e_priv
*priv
);
822 void (*update_stats
)(struct mlx5e_priv
*priv
);
823 void (*update_carrier
)(struct mlx5e_priv
*priv
);
824 int (*max_nch
)(struct mlx5_core_dev
*mdev
);
826 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
827 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe
;
829 void (*netdev_registered_init
)(struct mlx5e_priv
*priv
);
830 void (*netdev_registered_remove
)(struct mlx5e_priv
*priv
);
834 void mlx5e_build_ptys2ethtool_map(void);
836 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
837 void *accel_priv
, select_queue_fallback_t fallback
);
838 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
840 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
);
841 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
842 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
843 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
, int napi_budget
);
844 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
845 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq
*cq
);
846 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq
*sq
);
847 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq
*sq
);
849 void mlx5e_page_release(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
,
851 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
852 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
853 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
854 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq
*rq
);
855 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
);
856 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
);
857 void mlx5e_free_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
);
859 void mlx5e_rx_am(struct mlx5e_rq
*rq
);
860 void mlx5e_rx_am_work(struct work_struct
*work
);
861 struct mlx5e_cq_moder
mlx5e_am_get_def_profile(u8 rx_cq_period_mode
);
863 void mlx5e_update_stats(struct mlx5e_priv
*priv
, bool full
);
865 int mlx5e_create_flow_steering(struct mlx5e_priv
*priv
);
866 void mlx5e_destroy_flow_steering(struct mlx5e_priv
*priv
);
867 void mlx5e_init_l2_addr(struct mlx5e_priv
*priv
);
868 void mlx5e_destroy_flow_table(struct mlx5e_flow_table
*ft
);
869 int mlx5e_self_test_num(struct mlx5e_priv
*priv
);
870 void mlx5e_self_test(struct net_device
*ndev
, struct ethtool_test
*etest
,
872 int mlx5e_ethtool_get_flow(struct mlx5e_priv
*priv
, struct ethtool_rxnfc
*info
,
874 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv
*priv
,
875 struct ethtool_rxnfc
*info
, u32
*rule_locs
);
876 int mlx5e_ethtool_flow_replace(struct mlx5e_priv
*priv
,
877 struct ethtool_rx_flow_spec
*fs
);
878 int mlx5e_ethtool_flow_remove(struct mlx5e_priv
*priv
,
880 void mlx5e_ethtool_init_steering(struct mlx5e_priv
*priv
);
881 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv
*priv
);
882 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
884 int mlx5e_hwstamp_set(struct mlx5e_priv
*priv
, struct ifreq
*ifr
);
885 int mlx5e_hwstamp_get(struct mlx5e_priv
*priv
, struct ifreq
*ifr
);
886 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv
*priv
, bool val
);
888 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
890 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
892 void mlx5e_enable_cvlan_filter(struct mlx5e_priv
*priv
);
893 void mlx5e_disable_cvlan_filter(struct mlx5e_priv
*priv
);
894 void mlx5e_timestamp_set(struct mlx5e_priv
*priv
);
896 struct mlx5e_redirect_rqt_param
{
899 u32 rqn
; /* Direct RQN (Non-RSS) */
902 struct mlx5e_channels
*channels
;
903 } rss
; /* RSS data */
907 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
,
908 struct mlx5e_redirect_rqt_param rrp
);
909 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params
*params
,
910 enum mlx5e_traffic_types tt
,
911 void *tirc
, bool inner
);
913 int mlx5e_open_locked(struct net_device
*netdev
);
914 int mlx5e_close_locked(struct net_device
*netdev
);
916 int mlx5e_open_channels(struct mlx5e_priv
*priv
,
917 struct mlx5e_channels
*chs
);
918 void mlx5e_close_channels(struct mlx5e_channels
*chs
);
920 /* Function pointer to be used to modify WH settings while
923 typedef int (*mlx5e_fp_hw_modify
)(struct mlx5e_priv
*priv
);
924 void mlx5e_switch_priv_channels(struct mlx5e_priv
*priv
,
925 struct mlx5e_channels
*new_chs
,
926 mlx5e_fp_hw_modify hw_modify
);
927 void mlx5e_activate_priv_channels(struct mlx5e_priv
*priv
);
928 void mlx5e_deactivate_priv_channels(struct mlx5e_priv
*priv
);
930 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
932 int mlx5e_get_max_linkspeed(struct mlx5_core_dev
*mdev
, u32
*speed
);
934 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params
*params
,
936 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
,
938 void mlx5e_set_rq_type_params(struct mlx5_core_dev
*mdev
,
939 struct mlx5e_params
*params
, u8 rq_type
);
941 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev
*mdev
)
943 return (MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
) &&
944 MLX5_CAP_FLOWTABLE_NIC_RX(mdev
, ft_field_support
.inner_ip_version
));
948 struct mlx5e_tx_wqe
*mlx5e_post_nop(struct mlx5_wq_cyc
*wq
, u32 sqn
, u16
*pc
)
950 u16 pi
= *pc
& wq
->sz_m1
;
951 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
952 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
954 memset(cseg
, 0, sizeof(*cseg
));
956 cseg
->opmod_idx_opcode
= cpu_to_be32((*pc
<< 8) | MLX5_OPCODE_NOP
);
957 cseg
->qpn_ds
= cpu_to_be32((sqn
<< 8) | 0x01);
965 void mlx5e_notify_hw(struct mlx5_wq_cyc
*wq
, u16 pc
,
966 void __iomem
*uar_map
,
967 struct mlx5_wqe_ctrl_seg
*ctrl
)
969 ctrl
->fm_ce_se
= MLX5_WQE_CTRL_CQ_UPDATE
;
970 /* ensure wqe is visible to device before updating doorbell record */
973 *wq
->db
= cpu_to_be32(pc
);
975 /* ensure doorbell record is visible to device before ringing the
980 mlx5_write64((__be32
*)ctrl
, uar_map
, NULL
);
983 static inline void mlx5e_cq_arm(struct mlx5e_cq
*cq
)
985 struct mlx5_core_cq
*mcq
;
988 mlx5_cq_arm(mcq
, MLX5_CQ_DB_REQ_NOT
, mcq
->uar
->map
, cq
->wq
.cc
);
991 static inline u32
mlx5e_get_wqe_mtt_offset(struct mlx5e_rq
*rq
, u16 wqe_ix
)
993 return wqe_ix
* ALIGN(MLX5_MPWRQ_PAGES_PER_WQE
, 8);
996 extern const struct ethtool_ops mlx5e_ethtool_ops
;
997 #ifdef CONFIG_MLX5_CORE_EN_DCB
998 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops
;
999 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv
*priv
, struct ieee_ets
*ets
);
1000 void mlx5e_dcbnl_initialize(struct mlx5e_priv
*priv
);
1001 void mlx5e_dcbnl_init_app(struct mlx5e_priv
*priv
);
1002 void mlx5e_dcbnl_delete_app(struct mlx5e_priv
*priv
);
1005 #ifndef CONFIG_RFS_ACCEL
1006 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv
*priv
)
1011 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv
*priv
) {}
1013 static inline int mlx5e_arfs_enable(struct mlx5e_priv
*priv
)
1018 static inline int mlx5e_arfs_disable(struct mlx5e_priv
*priv
)
1023 int mlx5e_arfs_create_tables(struct mlx5e_priv
*priv
);
1024 void mlx5e_arfs_destroy_tables(struct mlx5e_priv
*priv
);
1025 int mlx5e_arfs_enable(struct mlx5e_priv
*priv
);
1026 int mlx5e_arfs_disable(struct mlx5e_priv
*priv
);
1027 int mlx5e_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
1028 u16 rxq_index
, u32 flow_id
);
1031 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
);
1032 int mlx5e_create_tir(struct mlx5_core_dev
*mdev
,
1033 struct mlx5e_tir
*tir
, u32
*in
, int inlen
);
1034 void mlx5e_destroy_tir(struct mlx5_core_dev
*mdev
,
1035 struct mlx5e_tir
*tir
);
1036 int mlx5e_create_mdev_resources(struct mlx5_core_dev
*mdev
);
1037 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev
*mdev
);
1038 int mlx5e_refresh_tirs(struct mlx5e_priv
*priv
, bool enable_uc_lb
);
1040 /* common netdev helpers */
1041 int mlx5e_create_indirect_rqt(struct mlx5e_priv
*priv
);
1043 int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
);
1044 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
);
1046 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
);
1047 void mlx5e_destroy_direct_rqts(struct mlx5e_priv
*priv
);
1048 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
);
1049 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
);
1050 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
);
1052 int mlx5e_create_ttc_table(struct mlx5e_priv
*priv
);
1053 void mlx5e_destroy_ttc_table(struct mlx5e_priv
*priv
);
1055 int mlx5e_create_inner_ttc_table(struct mlx5e_priv
*priv
);
1056 void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv
*priv
);
1058 int mlx5e_create_tis(struct mlx5_core_dev
*mdev
, int tc
,
1059 u32 underlay_qpn
, u32
*tisn
);
1060 void mlx5e_destroy_tis(struct mlx5_core_dev
*mdev
, u32 tisn
);
1062 int mlx5e_create_tises(struct mlx5e_priv
*priv
);
1063 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
);
1064 int mlx5e_close(struct net_device
*netdev
);
1065 int mlx5e_open(struct net_device
*netdev
);
1066 void mlx5e_update_stats_work(struct work_struct
*work
);
1067 u32
mlx5e_choose_lro_timeout(struct mlx5_core_dev
*mdev
, u32 wanted_timeout
);
1069 /* ethtool helpers */
1070 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv
*priv
,
1071 struct ethtool_drvinfo
*drvinfo
);
1072 void mlx5e_ethtool_get_strings(struct mlx5e_priv
*priv
,
1073 uint32_t stringset
, uint8_t *data
);
1074 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv
*priv
, int sset
);
1075 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv
*priv
,
1076 struct ethtool_stats
*stats
, u64
*data
);
1077 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv
*priv
,
1078 struct ethtool_ringparam
*param
);
1079 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv
*priv
,
1080 struct ethtool_ringparam
*param
);
1081 void mlx5e_ethtool_get_channels(struct mlx5e_priv
*priv
,
1082 struct ethtool_channels
*ch
);
1083 int mlx5e_ethtool_set_channels(struct mlx5e_priv
*priv
,
1084 struct ethtool_channels
*ch
);
1085 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv
*priv
,
1086 struct ethtool_coalesce
*coal
);
1087 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv
*priv
,
1088 struct ethtool_coalesce
*coal
);
1089 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv
*priv
,
1090 struct ethtool_ts_info
*info
);
1091 int mlx5e_ethtool_flash_device(struct mlx5e_priv
*priv
,
1092 struct ethtool_flash
*flash
);
1094 int mlx5e_setup_tc_block_cb(enum tc_setup_type type
, void *type_data
,
1097 /* mlx5e generic netdev management API */
1099 mlx5e_create_netdev(struct mlx5_core_dev
*mdev
, const struct mlx5e_profile
*profile
,
1101 int mlx5e_attach_netdev(struct mlx5e_priv
*priv
);
1102 void mlx5e_detach_netdev(struct mlx5e_priv
*priv
);
1103 void mlx5e_destroy_netdev(struct mlx5e_priv
*priv
);
1104 void mlx5e_build_nic_params(struct mlx5_core_dev
*mdev
,
1105 struct mlx5e_params
*params
,
1107 u8
mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev
*mdev
);
1108 #endif /* __MLX5_EN_H__ */