drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/crash_dump.h>
  41 #include <linux/mlx5/driver.h>
  42 #include <linux/mlx5/qp.h>
  43 #include <linux/mlx5/cq.h>
  44 #include <linux/mlx5/port.h>
  45 #include <linux/mlx5/vport.h>
  46 #include <linux/mlx5/transobj.h>
  47 #include <linux/rhashtable.h>
  48 #include <net/switchdev.h>
  49 #include "wq.h"
  50 #include "mlx5_core.h"
  51 #include "en_stats.h"
  52
  53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  54
  55 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
  56
  57 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu))
  58 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu))
  59
  60 #define MLX5E_MAX_NUM_TC        8
  61
  62 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  63 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  64 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  65
  66 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  67 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  68 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  69
  70 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  71 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  72 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  73
  74 #define MLX5_RX_HEADROOM NET_SKB_PAD
  75 #define MLX5_SKB_FRAG_SZ(len)   (SKB_DATA_ALIGN(len) +  \
  76                                  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
  77
  78 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
  79         (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
  80 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
  81         max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
  82 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)       MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
  83 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
  84
  85 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  86 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  87                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  88 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  89 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  90                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  91
  92 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  93 #define MLX5E_REQUIRED_MTTS(wqes)               \
  94         (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  95 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
  96
  97 #define MLX5_UMR_ALIGN                          (2048)
  98 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (256)
  99
 100 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
 101 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
 102 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
 103
 104 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
 105 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
 106 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
 107 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
 108 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
 109 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
 110 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
 111
 112 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 113 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 114 #define MLX5E_MIN_NUM_CHANNELS         0x1
 115 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 116 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 117 #define MLX5E_TX_CQ_POLL_BUDGET        128
 118 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 119
 120 #define MLX5E_ICOSQ_MAX_WQEBBS \
 121         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 122
 123 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 124 #define MLX5E_XDP_TX_DS_COUNT \
 125         ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 126
 127 #define MLX5E_NUM_MAIN_GROUPS 9
 128
 129 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 130 {
 131         switch (wq_type) {
 132         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 133                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 134                              wq_size / 2);
 135         default:
 136                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 137                              wq_size / 2);
 138         }
 139 }
 140
 141 static inline int mlx5_min_log_rq_size(int wq_type)
 142 {
 143         switch (wq_type) {
 144         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 145                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 146         default:
 147                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 148         }
 149 }
 150
 151 static inline int mlx5_max_log_rq_size(int wq_type)
 152 {
 153         switch (wq_type) {
 154         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 155                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 156         default:
 157                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 158         }
 159 }
 160
 161 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 162 {
 163         return is_kdump_kernel() ?
 164                 MLX5E_MIN_NUM_CHANNELS :
 165                 min_t(int, mdev->priv.eq_table.num_comp_vectors,
 166                       MLX5E_MAX_NUM_CHANNELS);
 167 }
 168
 169 struct mlx5e_tx_wqe {
 170         struct mlx5_wqe_ctrl_seg ctrl;
 171         struct mlx5_wqe_eth_seg  eth;
 172 };
 173
 174 struct mlx5e_rx_wqe {
 175         struct mlx5_wqe_srq_next_seg  next;
 176         struct mlx5_wqe_data_seg      data;
 177 };
 178
 179 struct mlx5e_umr_wqe {
 180         struct mlx5_wqe_ctrl_seg       ctrl;
 181         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 182         struct mlx5_mkey_seg           mkc;
 183         struct mlx5_wqe_data_seg       data;
 184 };
 185
 186 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
 187
 188 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 189         "rx_cqe_moder",
 190         "rx_cqe_compress",
 191 };
 192
 193 enum mlx5e_priv_flag {
 194         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 195         MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
 196 };
 197
 198 #define MLX5E_SET_PFLAG(params, pflag, enable)                  \
 199         do {                                                    \
 200                 if (enable)                                     \
 201                         (params)->pflags |= (pflag);            \
 202                 else                                            \
 203                         (params)->pflags &= ~(pflag);           \
 204         } while (0)
 205
 206 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
 207
 208 #ifdef CONFIG_MLX5_CORE_EN_DCB
 209 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 210 #endif
 211
 212 struct mlx5e_cq_moder {
 213         u16 usec;
 214         u16 pkts;
 215 };
 216
 217 struct mlx5e_params {
 218         u8  log_sq_size;
 219         u8  rq_wq_type;
 220         u16 rq_headroom;
 221         u8  mpwqe_log_stride_sz;
 222         u8  mpwqe_log_num_strides;
 223         u8  log_rq_size;
 224         u16 num_channels;
 225         u8  num_tc;
 226         u8  rx_cq_period_mode;
 227         bool rx_cqe_compress_def;
 228         struct mlx5e_cq_moder rx_cq_moderation;
 229         struct mlx5e_cq_moder tx_cq_moderation;
 230         bool lro_en;
 231         u32 lro_wqe_sz;
 232         u16 tx_max_inline;
 233         u8  tx_min_inline_mode;
 234         u8  rss_hfunc;
 235         u8  toeplitz_hash_key[40];
 236         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 237         bool vlan_strip_disable;
 238         bool scatter_fcs_en;
 239         bool rx_am_enabled;
 240         u32 lro_timeout;
 241         u32 pflags;
 242         struct bpf_prog *xdp_prog;
 243 };
 244
 245 #ifdef CONFIG_MLX5_CORE_EN_DCB
 246 struct mlx5e_cee_config {
 247         /* bw pct for priority group */
 248         u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];
 249         u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];
 250         bool                       pfc_setting[CEE_DCBX_MAX_PRIO];
 251         bool                       pfc_enable;
 252 };
 253
 254 enum {
 255         MLX5_DCB_CHG_RESET,
 256         MLX5_DCB_NO_CHG,
 257         MLX5_DCB_CHG_NO_RESET,
 258 };
 259
 260 struct mlx5e_dcbx {
 261         enum mlx5_dcbx_oper_mode   mode;
 262         struct mlx5e_cee_config    cee_cfg; /* pending configuration */
 263
 264         /* The only setting that cannot be read from FW */
 265         u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];
 266 };
 267 #endif
 268
 269 struct mlx5e_tstamp {
 270         rwlock_t                   lock;
 271         struct cyclecounter        cycles;
 272         struct timecounter         clock;
 273         struct hwtstamp_config     hwtstamp_config;
 274         u32                        nominal_c_mult;
 275         unsigned long              overflow_period;
 276         struct delayed_work        overflow_work;
 277         struct mlx5_core_dev      *mdev;
 278         struct ptp_clock          *ptp;
 279         struct ptp_clock_info      ptp_info;
 280         u8                        *pps_pin_caps;
 281 };
 282
 283 enum {
 284         MLX5E_RQ_STATE_ENABLED,
 285         MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
 286         MLX5E_RQ_STATE_AM,
 287 };
 288
 289 struct mlx5e_cq {
 290         /* data path - accessed per cqe */
 291         struct mlx5_cqwq           wq;
 292
 293         /* data path - accessed per napi poll */
 294         u16                        event_ctr;
 295         struct napi_struct        *napi;
 296         struct mlx5_core_cq        mcq;
 297         struct mlx5e_channel      *channel;
 298
 299         /* cqe decompression */
 300         struct mlx5_cqe64          title;
 301         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 302         u8                         mini_arr_idx;
 303         u16                        decmprs_left;
 304         u16                        decmprs_wqe_counter;
 305
 306         /* control */
 307         struct mlx5_core_dev      *mdev;
 308         struct mlx5_frag_wq_ctrl   wq_ctrl;
 309 } ____cacheline_aligned_in_smp;
 310
 311 struct mlx5e_tx_wqe_info {
 312         struct sk_buff *skb;
 313         u32 num_bytes;
 314         u8  num_wqebbs;
 315         u8  num_dma;
 316 };
 317
 318 enum mlx5e_dma_map_type {
 319         MLX5E_DMA_MAP_SINGLE,
 320         MLX5E_DMA_MAP_PAGE
 321 };
 322
 323 struct mlx5e_sq_dma {
 324         dma_addr_t              addr;
 325         u32                     size;
 326         enum mlx5e_dma_map_type type;
 327 };
 328
 329 enum {
 330         MLX5E_SQ_STATE_ENABLED,
 331         MLX5E_SQ_STATE_IPSEC,
 332 };
 333
 334 struct mlx5e_sq_wqe_info {
 335         u8  opcode;
 336         u8  num_wqebbs;
 337 };
 338
 339 struct mlx5e_txqsq {
 340         /* data path */
 341
 342         /* dirtied @completion */
 343         u16                        cc;
 344         u32                        dma_fifo_cc;
 345
 346         /* dirtied @xmit */
 347         u16                        pc ____cacheline_aligned_in_smp;
 348         u32                        dma_fifo_pc;
 349         struct mlx5e_sq_stats      stats;
 350
 351         struct mlx5e_cq            cq;
 352
 353         /* write@xmit, read@completion */
 354         struct {
 355                 struct mlx5e_sq_dma       *dma_fifo;
 356                 struct mlx5e_tx_wqe_info  *wqe_info;
 357         } db;
 358
 359         /* read only */
 360         struct mlx5_wq_cyc         wq;
 361         u32                        dma_fifo_mask;
 362         void __iomem              *uar_map;
 363         struct netdev_queue       *txq;
 364         u32                        sqn;
 365         u16                        max_inline;
 366         u8                         min_inline_mode;
 367         u16                        edge;
 368         struct device             *pdev;
 369         struct mlx5e_tstamp       *tstamp;
 370         __be32                     mkey_be;
 371         unsigned long              state;
 372
 373         /* control path */
 374         struct mlx5_wq_ctrl        wq_ctrl;
 375         struct mlx5e_channel      *channel;
 376         int                        txq_ix;
 377         u32                        rate_limit;
 378 } ____cacheline_aligned_in_smp;
 379
 380 struct mlx5e_xdpsq {
 381         /* data path */
 382
 383         /* dirtied @rx completion */
 384         u16                        cc;
 385         u16                        pc;
 386
 387         struct mlx5e_cq            cq;
 388
 389         /* write@xmit, read@completion */
 390         struct {
 391                 struct mlx5e_dma_info     *di;
 392                 bool                       doorbell;
 393         } db;
 394
 395         /* read only */
 396         struct mlx5_wq_cyc         wq;
 397         void __iomem              *uar_map;
 398         u32                        sqn;
 399         struct device             *pdev;
 400         __be32                     mkey_be;
 401         u8                         min_inline_mode;
 402         unsigned long              state;
 403
 404         /* control path */
 405         struct mlx5_wq_ctrl        wq_ctrl;
 406         struct mlx5e_channel      *channel;
 407 } ____cacheline_aligned_in_smp;
 408
 409 struct mlx5e_icosq {
 410         /* data path */
 411
 412         /* dirtied @completion */
 413         u16                        cc;
 414
 415         /* dirtied @xmit */
 416         u16                        pc ____cacheline_aligned_in_smp;
 417         u32                        dma_fifo_pc;
 418         u16                        prev_cc;
 419
 420         struct mlx5e_cq            cq;
 421
 422         /* write@xmit, read@completion */
 423         struct {
 424                 struct mlx5e_sq_wqe_info *ico_wqe;
 425         } db;
 426
 427         /* read only */
 428         struct mlx5_wq_cyc         wq;
 429         void __iomem              *uar_map;
 430         u32                        sqn;
 431         u16                        edge;
 432         struct device             *pdev;
 433         __be32                     mkey_be;
 434         unsigned long              state;
 435
 436         /* control path */
 437         struct mlx5_wq_ctrl        wq_ctrl;
 438         struct mlx5e_channel      *channel;
 439 } ____cacheline_aligned_in_smp;
 440
 441 static inline bool
 442 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
 443 {
 444         return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
 445 }
 446
 447 struct mlx5e_dma_info {
 448         struct page     *page;
 449         dma_addr_t      addr;
 450 };
 451
 452 struct mlx5e_wqe_frag_info {
 453         struct mlx5e_dma_info di;
 454         u32 offset;
 455 };
 456
 457 struct mlx5e_umr_dma_info {
 458         __be64                *mtt;
 459         dma_addr_t             mtt_addr;
 460         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 461         struct mlx5e_umr_wqe   wqe;
 462 };
 463
 464 struct mlx5e_mpw_info {
 465         struct mlx5e_umr_dma_info umr;
 466         u16 consumed_strides;
 467         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 468 };
 469
 470 struct mlx5e_rx_am_stats {
 471         int ppms; /* packets per msec */
 472         int bpms; /* bytes per msec */
 473         int epms; /* events per msec */
 474 };
 475
 476 struct mlx5e_rx_am_sample {
 477         ktime_t time;
 478         u32     pkt_ctr;
 479         u32     byte_ctr;
 480         u16     event_ctr;
 481 };
 482
 483 struct mlx5e_rx_am { /* Adaptive Moderation */
 484         u8                                      state;
 485         struct mlx5e_rx_am_stats                prev_stats;
 486         struct mlx5e_rx_am_sample               start_sample;
 487         struct work_struct                      work;
 488         u8                                      profile_ix;
 489         u8                                      mode;
 490         u8                                      tune_state;
 491         u8                                      steps_right;
 492         u8                                      steps_left;
 493         u8                                      tired;
 494 };
 495
 496 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 497  * or a MPWQE (for striding rq).
 498  */
 499 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 500                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 501 #define MLX5E_CACHE_SIZE        (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 502 struct mlx5e_page_cache {
 503         u32 head;
 504         u32 tail;
 505         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 506 };
 507
 508 struct mlx5e_rq;
 509 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
 510 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16);
 511 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
 512
 513 struct mlx5e_rq {
 514         /* data path */
 515         struct mlx5_wq_ll      wq;
 516
 517         union {
 518                 struct {
 519                         struct mlx5e_wqe_frag_info *frag_info;
 520                         u32 frag_sz;    /* max possible skb frag_sz */
 521                         bool page_reuse;
 522                         bool xdp_xmit;
 523                 } wqe;
 524                 struct {
 525                         struct mlx5e_mpw_info *info;
 526                         void                  *mtt_no_align;
 527                 } mpwqe;
 528         };
 529         struct {
 530                 u8             page_order;
 531                 u32            wqe_sz;    /* wqe data buffer size */
 532                 u8             map_dir;   /* dma map direction */
 533         } buff;
 534         __be32                 mkey_be;
 535
 536         struct device         *pdev;
 537         struct net_device     *netdev;
 538         struct mlx5e_tstamp   *tstamp;
 539         struct mlx5e_rq_stats  stats;
 540         struct mlx5e_cq        cq;
 541         struct mlx5e_page_cache page_cache;
 542
 543         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 544         mlx5e_fp_alloc_wqe     alloc_wqe;
 545         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 546
 547         unsigned long          state;
 548         int                    ix;
 549         u16                    rx_headroom;
 550
 551         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 552
 553         /* XDP */
 554         struct bpf_prog       *xdp_prog;
 555         struct mlx5e_xdpsq     xdpsq;
 556
 557         /* control */
 558         struct mlx5_wq_ctrl    wq_ctrl;
 559         u8                     wq_type;
 560         u32                    mpwqe_stride_sz;
 561         u32                    mpwqe_num_strides;
 562         u32                    rqn;
 563         struct mlx5e_channel  *channel;
 564         struct mlx5_core_dev  *mdev;
 565         struct mlx5_core_mkey  umr_mkey;
 566 } ____cacheline_aligned_in_smp;
 567
 568 enum channel_flags {
 569         MLX5E_CHANNEL_NAPI_SCHED = 1,
 570 };
 571
 572 struct mlx5e_channel {
 573         /* data path */
 574         struct mlx5e_rq            rq;
 575         struct mlx5e_txqsq         sq[MLX5E_MAX_NUM_TC];
 576         struct mlx5e_icosq         icosq;   /* internal control operations */
 577         bool                       xdp;
 578         struct napi_struct         napi;
 579         struct device             *pdev;
 580         struct net_device         *netdev;
 581         __be32                     mkey_be;
 582         u8                         num_tc;
 583         unsigned long              flags;
 584
 585         /* control */
 586         struct mlx5e_priv         *priv;
 587         struct mlx5_core_dev      *mdev;
 588         struct mlx5e_tstamp       *tstamp;
 589         int                        ix;
 590         int                        cpu;
 591 };
 592
 593 struct mlx5e_channels {
 594         struct mlx5e_channel **c;
 595         unsigned int           num;
 596         struct mlx5e_params    params;
 597 };
 598
 599 enum mlx5e_traffic_types {
 600         MLX5E_TT_IPV4_TCP,
 601         MLX5E_TT_IPV6_TCP,
 602         MLX5E_TT_IPV4_UDP,
 603         MLX5E_TT_IPV6_UDP,
 604         MLX5E_TT_IPV4_IPSEC_AH,
 605         MLX5E_TT_IPV6_IPSEC_AH,
 606         MLX5E_TT_IPV4_IPSEC_ESP,
 607         MLX5E_TT_IPV6_IPSEC_ESP,
 608         MLX5E_TT_IPV4,
 609         MLX5E_TT_IPV6,
 610         MLX5E_TT_ANY,
 611         MLX5E_NUM_TT,
 612         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 613 };
 614
 615 enum {
 616         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 617         MLX5E_STATE_OPENED,
 618         MLX5E_STATE_DESTROYING,
 619 };
 620
 621 struct mlx5e_vxlan_db {
 622         spinlock_t                      lock; /* protect vxlan table */
 623         struct radix_tree_root          tree;
 624 };
 625
 626 struct mlx5e_l2_rule {
 627         u8  addr[ETH_ALEN + 2];
 628         struct mlx5_flow_handle *rule;
 629 };
 630
 631 struct mlx5e_flow_table {
 632         int num_groups;
 633         struct mlx5_flow_table *t;
 634         struct mlx5_flow_group **g;
 635 };
 636
 637 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 638
 639 struct mlx5e_tc_table {
 640         struct mlx5_flow_table          *t;
 641
 642         struct rhashtable_params        ht_params;
 643         struct rhashtable               ht;
 644
 645         DECLARE_HASHTABLE(mod_hdr_tbl, 8);
 646 };
 647
 648 struct mlx5e_vlan_table {
 649         struct mlx5e_flow_table         ft;
 650         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 651         struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
 652         struct mlx5_flow_handle *untagged_rule;
 653         struct mlx5_flow_handle *any_cvlan_rule;
 654         struct mlx5_flow_handle *any_svlan_rule;
 655         bool                    filter_disabled;
 656 };
 657
 658 struct mlx5e_l2_table {
 659         struct mlx5e_flow_table    ft;
 660         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 661         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 662         struct mlx5e_l2_rule       broadcast;
 663         struct mlx5e_l2_rule       allmulti;
 664         struct mlx5e_l2_rule       promisc;
 665         bool                       broadcast_enabled;
 666         bool                       allmulti_enabled;
 667         bool                       promisc_enabled;
 668 };
 669
 670 /* L3/L4 traffic type classifier */
 671 struct mlx5e_ttc_table {
 672         struct mlx5e_flow_table  ft;
 673         struct mlx5_flow_handle  *rules[MLX5E_NUM_TT];
 674 };
 675
 676 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 677 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 678 struct arfs_table {
 679         struct mlx5e_flow_table  ft;
 680         struct mlx5_flow_handle  *default_rule;
 681         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 682 };
 683
 684 enum  arfs_type {
 685         ARFS_IPV4_TCP,
 686         ARFS_IPV6_TCP,
 687         ARFS_IPV4_UDP,
 688         ARFS_IPV6_UDP,
 689         ARFS_NUM_TYPES,
 690 };
 691
 692 struct mlx5e_arfs_tables {
 693         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 694         /* Protect aRFS rules list */
 695         spinlock_t                     arfs_lock;
 696         struct list_head               rules;
 697         int                            last_filter_id;
 698         struct workqueue_struct        *wq;
 699 };
 700
 701 /* NIC prio FTS */
 702 enum {
 703         MLX5E_VLAN_FT_LEVEL = 0,
 704         MLX5E_L2_FT_LEVEL,
 705         MLX5E_TTC_FT_LEVEL,
 706         MLX5E_ARFS_FT_LEVEL
 707 };
 708
 709 struct mlx5e_ethtool_table {
 710         struct mlx5_flow_table *ft;
 711         int                    num_rules;
 712 };
 713
 714 #define ETHTOOL_NUM_L3_L4_FTS 7
 715 #define ETHTOOL_NUM_L2_FTS 4
 716
 717 struct mlx5e_ethtool_steering {
 718         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 719         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 720         struct list_head                rules;
 721         int                             tot_num_rules;
 722 };
 723
 724 struct mlx5e_flow_steering {
 725         struct mlx5_flow_namespace      *ns;
 726         struct mlx5e_ethtool_steering   ethtool;
 727         struct mlx5e_tc_table           tc;
 728         struct mlx5e_vlan_table         vlan;
 729         struct mlx5e_l2_table           l2;
 730         struct mlx5e_ttc_table          ttc;
 731         struct mlx5e_arfs_tables        arfs;
 732 };
 733
 734 struct mlx5e_rqt {
 735         u32              rqtn;
 736         bool             enabled;
 737 };
 738
 739 struct mlx5e_tir {
 740         u32               tirn;
 741         struct mlx5e_rqt  rqt;
 742         struct list_head  list;
 743 };
 744
 745 enum {
 746         MLX5E_TC_PRIO = 0,
 747         MLX5E_NIC_PRIO
 748 };
 749
 750 struct mlx5e_priv {
 751         /* priv data path fields - start */
 752         struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
 753         int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 754         /* priv data path fields - end */
 755
 756         unsigned long              state;
 757         struct mutex               state_lock; /* Protects Interface state */
 758         struct mlx5e_rq            drop_rq;
 759
 760         struct mlx5e_channels      channels;
 761         u32                        tisn[MLX5E_MAX_NUM_TC];
 762         struct mlx5e_rqt           indir_rqt;
 763         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 764         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 765         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 766         int                        hard_mtu;
 767
 768         struct mlx5e_flow_steering fs;
 769         struct mlx5e_vxlan_db      vxlan;
 770
 771         struct workqueue_struct    *wq;
 772         struct work_struct         update_carrier_work;
 773         struct work_struct         set_rx_mode_work;
 774         struct work_struct         tx_timeout_work;
 775         struct delayed_work        update_stats_work;
 776
 777         struct mlx5_core_dev      *mdev;
 778         struct net_device         *netdev;
 779         struct mlx5e_stats         stats;
 780         struct mlx5e_tstamp        tstamp;
 781         u16 q_counter;
 782 #ifdef CONFIG_MLX5_CORE_EN_DCB
 783         struct mlx5e_dcbx          dcbx;
 784 #endif
 785
 786         const struct mlx5e_profile *profile;
 787         void                      *ppriv;
 788 #ifdef CONFIG_MLX5_EN_IPSEC
 789         struct mlx5e_ipsec        *ipsec;
 790 #endif
 791 };
 792
 793 struct mlx5e_profile {
 794         void    (*init)(struct mlx5_core_dev *mdev,
 795                         struct net_device *netdev,
 796                         const struct mlx5e_profile *profile, void *ppriv);
 797         void    (*cleanup)(struct mlx5e_priv *priv);
 798         int     (*init_rx)(struct mlx5e_priv *priv);
 799         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 800         int     (*init_tx)(struct mlx5e_priv *priv);
 801         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 802         void    (*enable)(struct mlx5e_priv *priv);
 803         void    (*disable)(struct mlx5e_priv *priv);
 804         void    (*update_stats)(struct mlx5e_priv *priv);
 805         void    (*update_carrier)(struct mlx5e_priv *priv);
 806         int     (*max_nch)(struct mlx5_core_dev *mdev);
 807         struct {
 808                 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 809                 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
 810         } rx_handlers;
 811         int     max_tc;
 812 };
 813
 814 void mlx5e_build_ptys2ethtool_map(void);
 815
 816 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 817                        void *accel_priv, select_queue_fallback_t fallback);
 818 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 819
 820 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 821 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 822 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 823 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 824 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 825 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
 826 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
 827 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
 828
 829 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 830                         bool recycle);
 831 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 832 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 833 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 834 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 835 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 836 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 837 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 838 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 839 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 840
 841 void mlx5e_rx_am(struct mlx5e_rq *rq);
 842 void mlx5e_rx_am_work(struct work_struct *work);
 843 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 844
 845 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full);
 846
 847 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 848 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 849 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 850 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 851 int mlx5e_self_test_num(struct mlx5e_priv *priv);
 852 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
 853                      u64 *buf);
 854 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 855                            int location);
 856 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 857                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 858 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 859                                struct ethtool_rx_flow_spec *fs);
 860 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 861                               int location);
 862 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 863 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 864 void mlx5e_set_rx_mode_work(struct work_struct *work);
 865
 866 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 867                         struct skb_shared_hwtstamps *hwts);
 868 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 869 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 870 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
 871                              struct ptp_clock_event *event);
 872 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
 873 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
 874 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
 875
 876 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 877                           u16 vid);
 878 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 879                            u16 vid);
 880 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 881 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 882
 883 struct mlx5e_redirect_rqt_param {
 884         bool is_rss;
 885         union {
 886                 u32 rqn; /* Direct RQN (Non-RSS) */
 887                 struct {
 888                         u8 hfunc;
 889                         struct mlx5e_channels *channels;
 890                 } rss; /* RSS data */
 891         };
 892 };
 893
 894 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
 895                        struct mlx5e_redirect_rqt_param rrp);
 896 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
 897                                     enum mlx5e_traffic_types tt,
 898                                     void *tirc);
 899
 900 int mlx5e_open_locked(struct net_device *netdev);
 901 int mlx5e_close_locked(struct net_device *netdev);
 902
 903 int mlx5e_open_channels(struct mlx5e_priv *priv,
 904                         struct mlx5e_channels *chs);
 905 void mlx5e_close_channels(struct mlx5e_channels *chs);
 906
 907 /* Function pointer to be used to modify WH settings while
 908  * switching channels
 909  */
 910 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
 911 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
 912                                 struct mlx5e_channels *new_chs,
 913                                 mlx5e_fp_hw_modify hw_modify);
 914 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
 915 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
 916
 917 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 918                                    u32 *indirection_rqt, int len,
 919                                    int num_channels);
 920 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 921
 922 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 923                                  u8 cq_period_mode);
 924 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
 925                               struct mlx5e_params *params, u8 rq_type);
 926
 927 static inline
 928 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
 929 {
 930         u16                         pi   = *pc & wq->sz_m1;
 931         struct mlx5e_tx_wqe        *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 932         struct mlx5_wqe_ctrl_seg   *cseg = &wqe->ctrl;
 933
 934         memset(cseg, 0, sizeof(*cseg));
 935
 936         cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
 937         cseg->qpn_ds           = cpu_to_be32((sqn << 8) | 0x01);
 938
 939         (*pc)++;
 940
 941         return wqe;
 942 }
 943
 944 static inline
 945 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
 946                      void __iomem *uar_map,
 947                      struct mlx5_wqe_ctrl_seg *ctrl)
 948 {
 949         ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
 950         /* ensure wqe is visible to device before updating doorbell record */
 951         dma_wmb();
 952
 953         *wq->db = cpu_to_be32(pc);
 954
 955         /* ensure doorbell record is visible to device before ringing the
 956          * doorbell
 957          */
 958         wmb();
 959
 960         mlx5_write64((__be32 *)ctrl, uar_map, NULL);
 961 }
 962
 963 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 964 {
 965         struct mlx5_core_cq *mcq;
 966
 967         mcq = &cq->mcq;
 968         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 969 }
 970
 971 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 972 {
 973         return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 974 }
 975
 976 extern const struct ethtool_ops mlx5e_ethtool_ops;
 977 #ifdef CONFIG_MLX5_CORE_EN_DCB
 978 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 979 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 980 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
 981 #endif
 982
 983 #ifndef CONFIG_RFS_ACCEL
 984 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
 985 {
 986         return 0;
 987 }
 988
 989 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
 990
 991 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
 992 {
 993         return -EOPNOTSUPP;
 994 }
 995
 996 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
 997 {
 998         return -EOPNOTSUPP;
 999 }
1000 #else
1001 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
1002 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
1003 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
1004 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
1005 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1006                         u16 rxq_index, u32 flow_id);
1007 #endif
1008
1009 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1010 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1011                      struct mlx5e_tir *tir, u32 *in, int inlen);
1012 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1013                        struct mlx5e_tir *tir);
1014 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1015 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1016 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1017
1018 /* common netdev helpers */
1019 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1020
1021 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
1022 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1023
1024 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1025 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1026 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1027 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1028 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1029
1030 int mlx5e_create_ttc_table(struct mlx5e_priv *priv);
1031 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
1032
1033 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1034                      u32 underlay_qpn, u32 *tisn);
1035 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1036
1037 int mlx5e_create_tises(struct mlx5e_priv *priv);
1038 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1039 int mlx5e_close(struct net_device *netdev);
1040 int mlx5e_open(struct net_device *netdev);
1041 void mlx5e_update_stats_work(struct work_struct *work);
1042 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
1043
1044 /* ethtool helpers */
1045 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1046                                struct ethtool_drvinfo *drvinfo);
1047 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1048                                uint32_t stringset, uint8_t *data);
1049 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1050 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1051                                      struct ethtool_stats *stats, u64 *data);
1052 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1053                                  struct ethtool_ringparam *param);
1054 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1055                                 struct ethtool_ringparam *param);
1056 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1057                                 struct ethtool_channels *ch);
1058 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1059                                struct ethtool_channels *ch);
1060 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1061                                struct ethtool_coalesce *coal);
1062 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1063                                struct ethtool_coalesce *coal);
1064 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1065                               struct ethtool_ts_info *info);
1066 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1067                                struct ethtool_flash *flash);
1068
1069 /* mlx5e generic netdev management API */
1070 struct net_device*
1071 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1072                     void *ppriv);
1073 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1074 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1075 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1076 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1077                             struct mlx5e_params *params,
1078                             u16 max_channels);
1079
1080 #endif /* __MLX5_EN_H__ */