2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include <net/switchdev.h>
49 #include "mlx5_core.h"
52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
54 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
55 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
57 #define MLX5E_MAX_NUM_TC 8
59 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
60 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
71 #define MLX5_RX_HEADROOM NET_SKB_PAD
73 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
74 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
75 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
76 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
77 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
78 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
80 #define MLX5_MPWRQ_LOG_WQE_SZ 18
81 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
82 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
83 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
84 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
85 MLX5_MPWRQ_WQE_PAGE_ORDER)
87 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
88 #define MLX5E_REQUIRED_MTTS(wqes) \
89 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
90 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
92 #define MLX5_UMR_ALIGN (2048)
93 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
95 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
96 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
97 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
102 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
103 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
104 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
105 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
107 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
108 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
109 #define MLX5E_MIN_NUM_CHANNELS 0x1
110 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
111 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
112 #define MLX5E_TX_CQ_POLL_BUDGET 128
113 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
114 #define MLX5E_SQ_BF_BUDGET 16
116 #define MLX5E_ICOSQ_MAX_WQEBBS \
117 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
119 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
120 #define MLX5E_XDP_IHS_DS_COUNT \
121 DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
122 #define MLX5E_XDP_TX_DS_COUNT \
123 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
124 #define MLX5E_XDP_TX_WQEBBS \
125 DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
127 #define MLX5E_NUM_MAIN_GROUPS 9
129 static inline u16
mlx5_min_rx_wqes(int wq_type
, u32 wq_size
)
132 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
133 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW
,
136 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
,
141 static inline int mlx5_min_log_rq_size(int wq_type
)
144 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
145 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
;
147 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
;
151 static inline int mlx5_max_log_rq_size(int wq_type
)
154 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
155 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW
;
157 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE
;
161 struct mlx5e_tx_wqe
{
162 struct mlx5_wqe_ctrl_seg ctrl
;
163 struct mlx5_wqe_eth_seg eth
;
166 struct mlx5e_rx_wqe
{
167 struct mlx5_wqe_srq_next_seg next
;
168 struct mlx5_wqe_data_seg data
;
171 struct mlx5e_umr_wqe
{
172 struct mlx5_wqe_ctrl_seg ctrl
;
173 struct mlx5_wqe_umr_ctrl_seg uctrl
;
174 struct mlx5_mkey_seg mkc
;
175 struct mlx5_wqe_data_seg data
;
178 extern const char mlx5e_self_tests
[][ETH_GSTRING_LEN
];
180 static const char mlx5e_priv_flags
[][ETH_GSTRING_LEN
] = {
185 enum mlx5e_priv_flag
{
186 MLX5E_PFLAG_RX_CQE_BASED_MODER
= (1 << 0),
187 MLX5E_PFLAG_RX_CQE_COMPRESS
= (1 << 1),
190 #define MLX5E_SET_PFLAG(priv, pflag, enable) \
193 (priv)->params.pflags |= (pflag); \
195 (priv)->params.pflags &= ~(pflag); \
198 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
200 #ifdef CONFIG_MLX5_CORE_EN_DCB
201 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
204 struct mlx5e_cq_moder
{
209 struct mlx5e_params
{
212 u8 mpwqe_log_stride_sz
;
213 u8 mpwqe_log_num_strides
;
217 u8 rx_cq_period_mode
;
218 bool rx_cqe_compress_def
;
219 struct mlx5e_cq_moder rx_cq_moderation
;
220 struct mlx5e_cq_moder tx_cq_moderation
;
225 u8 tx_min_inline_mode
;
227 u8 toeplitz_hash_key
[40];
228 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
229 bool vlan_strip_disable
;
235 #ifdef CONFIG_MLX5_CORE_EN_DCB
236 struct mlx5e_cee_config
{
237 /* bw pct for priority group */
238 u8 pg_bw_pct
[CEE_DCBX_MAX_PGS
];
239 u8 prio_to_pg_map
[CEE_DCBX_MAX_PRIO
];
240 bool pfc_setting
[CEE_DCBX_MAX_PRIO
];
247 MLX5_DCB_CHG_NO_RESET
,
251 enum mlx5_dcbx_oper_mode mode
;
252 struct mlx5e_cee_config cee_cfg
; /* pending configuration */
254 /* The only setting that cannot be read from FW */
255 u8 tc_tsa
[IEEE_8021QAZ_MAX_TCS
];
259 struct mlx5e_tstamp
{
261 struct cyclecounter cycles
;
262 struct timecounter clock
;
263 struct hwtstamp_config hwtstamp_config
;
265 unsigned long overflow_period
;
266 struct delayed_work overflow_work
;
267 struct mlx5_core_dev
*mdev
;
268 struct ptp_clock
*ptp
;
269 struct ptp_clock_info ptp_info
;
274 MLX5E_RQ_STATE_ENABLED
,
275 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS
,
280 /* data path - accessed per cqe */
283 /* data path - accessed per napi poll */
285 struct napi_struct
*napi
;
286 struct mlx5_core_cq mcq
;
287 struct mlx5e_channel
*channel
;
288 struct mlx5e_priv
*priv
;
290 /* cqe decompression */
291 struct mlx5_cqe64 title
;
292 struct mlx5_mini_cqe8 mini_arr
[MLX5_MINI_CQE_ARRAY_SIZE
];
295 u16 decmprs_wqe_counter
;
298 struct mlx5_frag_wq_ctrl wq_ctrl
;
299 } ____cacheline_aligned_in_smp
;
302 typedef void (*mlx5e_fp_handle_rx_cqe
)(struct mlx5e_rq
*rq
,
303 struct mlx5_cqe64
*cqe
);
304 typedef int (*mlx5e_fp_alloc_wqe
)(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
,
307 typedef void (*mlx5e_fp_dealloc_wqe
)(struct mlx5e_rq
*rq
, u16 ix
);
309 struct mlx5e_dma_info
{
314 struct mlx5e_rx_am_stats
{
315 int ppms
; /* packets per msec */
316 int epms
; /* events per msec */
319 struct mlx5e_rx_am_sample
{
321 unsigned int pkt_ctr
;
325 struct mlx5e_rx_am
{ /* Adaptive Moderation */
327 struct mlx5e_rx_am_stats prev_stats
;
328 struct mlx5e_rx_am_sample start_sample
;
329 struct work_struct work
;
338 /* a single cache unit is capable to serve one napi call (for non-striding rq)
339 * or a MPWQE (for striding rq).
341 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
342 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
343 #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
344 struct mlx5e_page_cache
{
347 struct mlx5e_dma_info page_cache
[MLX5E_CACHE_SIZE
];
352 struct mlx5_wq_ll wq
;
355 struct mlx5e_dma_info
*dma_info
;
357 struct mlx5e_mpw_info
*info
;
363 u32 wqe_sz
; /* wqe data buffer size */
364 u8 map_dir
; /* dma map direction */
369 struct net_device
*netdev
;
370 struct mlx5e_tstamp
*tstamp
;
371 struct mlx5e_rq_stats stats
;
373 struct mlx5e_page_cache page_cache
;
375 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
376 mlx5e_fp_alloc_wqe alloc_wqe
;
377 mlx5e_fp_dealloc_wqe dealloc_wqe
;
383 struct mlx5e_rx_am am
; /* Adaptive Moderation */
384 struct bpf_prog
*xdp_prog
;
387 struct mlx5_wq_ctrl wq_ctrl
;
390 u32 mpwqe_num_strides
;
392 struct mlx5e_channel
*channel
;
393 struct mlx5e_priv
*priv
;
394 struct mlx5_core_mkey umr_mkey
;
395 } ____cacheline_aligned_in_smp
;
397 struct mlx5e_umr_dma_info
{
400 struct mlx5e_dma_info dma_info
[MLX5_MPWRQ_PAGES_PER_WQE
];
401 struct mlx5e_umr_wqe wqe
;
404 struct mlx5e_mpw_info
{
405 struct mlx5e_umr_dma_info umr
;
406 u16 consumed_strides
;
407 u16 skbs_frags
[MLX5_MPWRQ_PAGES_PER_WQE
];
410 struct mlx5e_tx_wqe_info
{
416 enum mlx5e_dma_map_type
{
417 MLX5E_DMA_MAP_SINGLE
,
421 struct mlx5e_sq_dma
{
424 enum mlx5e_dma_map_type type
;
428 MLX5E_SQ_STATE_ENABLED
,
429 MLX5E_SQ_STATE_BF_ENABLE
,
432 struct mlx5e_sq_wqe_info
{
446 /* dirtied @completion */
451 u16 pc ____cacheline_aligned_in_smp
;
456 struct mlx5e_sq_stats stats
;
460 /* pointers to per tx element info: write@xmit, read@completion */
463 struct sk_buff
**skb
;
464 struct mlx5e_sq_dma
*dma_fifo
;
465 struct mlx5e_tx_wqe_info
*wqe_info
;
467 struct mlx5e_sq_wqe_info
*ico_wqe
;
469 struct mlx5e_sq_wqe_info
*wqe_info
;
470 struct mlx5e_dma_info
*di
;
476 struct mlx5_wq_cyc wq
;
478 void __iomem
*uar_map
;
479 struct netdev_queue
*txq
;
486 struct mlx5e_tstamp
*tstamp
;
491 struct mlx5_wq_ctrl wq_ctrl
;
492 struct mlx5_sq_bfreg bfreg
;
493 struct mlx5e_channel
*channel
;
497 } ____cacheline_aligned_in_smp
;
499 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq
*sq
, u16 n
)
501 return (((sq
->wq
.sz_m1
& (sq
->cc
- sq
->pc
)) >= n
) ||
506 MLX5E_CHANNEL_NAPI_SCHED
= 1,
509 struct mlx5e_channel
{
512 struct mlx5e_sq xdp_sq
;
513 struct mlx5e_sq sq
[MLX5E_MAX_NUM_TC
];
514 struct mlx5e_sq icosq
; /* internal control operations */
516 struct napi_struct napi
;
518 struct net_device
*netdev
;
524 struct mlx5e_priv
*priv
;
529 enum mlx5e_traffic_types
{
534 MLX5E_TT_IPV4_IPSEC_AH
,
535 MLX5E_TT_IPV6_IPSEC_AH
,
536 MLX5E_TT_IPV4_IPSEC_ESP
,
537 MLX5E_TT_IPV6_IPSEC_ESP
,
542 MLX5E_NUM_INDIR_TIRS
= MLX5E_TT_ANY
,
546 MLX5E_STATE_ASYNC_EVENTS_ENABLED
,
548 MLX5E_STATE_DESTROYING
,
551 struct mlx5e_vxlan_db
{
552 spinlock_t lock
; /* protect vxlan table */
553 struct radix_tree_root tree
;
556 struct mlx5e_l2_rule
{
557 u8 addr
[ETH_ALEN
+ 2];
558 struct mlx5_flow_handle
*rule
;
561 struct mlx5e_flow_table
{
563 struct mlx5_flow_table
*t
;
564 struct mlx5_flow_group
**g
;
567 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
569 struct mlx5e_tc_table
{
570 struct mlx5_flow_table
*t
;
572 struct rhashtable_params ht_params
;
573 struct rhashtable ht
;
576 struct mlx5e_vlan_table
{
577 struct mlx5e_flow_table ft
;
578 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
579 struct mlx5_flow_handle
*active_vlans_rule
[VLAN_N_VID
];
580 struct mlx5_flow_handle
*untagged_rule
;
581 struct mlx5_flow_handle
*any_cvlan_rule
;
582 struct mlx5_flow_handle
*any_svlan_rule
;
583 bool filter_disabled
;
586 struct mlx5e_l2_table
{
587 struct mlx5e_flow_table ft
;
588 struct hlist_head netdev_uc
[MLX5E_L2_ADDR_HASH_SIZE
];
589 struct hlist_head netdev_mc
[MLX5E_L2_ADDR_HASH_SIZE
];
590 struct mlx5e_l2_rule broadcast
;
591 struct mlx5e_l2_rule allmulti
;
592 struct mlx5e_l2_rule promisc
;
593 bool broadcast_enabled
;
594 bool allmulti_enabled
;
595 bool promisc_enabled
;
598 /* L3/L4 traffic type classifier */
599 struct mlx5e_ttc_table
{
600 struct mlx5e_flow_table ft
;
601 struct mlx5_flow_handle
*rules
[MLX5E_NUM_TT
];
604 #define ARFS_HASH_SHIFT BITS_PER_BYTE
605 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
607 struct mlx5e_flow_table ft
;
608 struct mlx5_flow_handle
*default_rule
;
609 struct hlist_head rules_hash
[ARFS_HASH_SIZE
];
620 struct mlx5e_arfs_tables
{
621 struct arfs_table arfs_tables
[ARFS_NUM_TYPES
];
622 /* Protect aRFS rules list */
623 spinlock_t arfs_lock
;
624 struct list_head rules
;
626 struct workqueue_struct
*wq
;
631 MLX5E_VLAN_FT_LEVEL
= 0,
637 struct mlx5e_ethtool_table
{
638 struct mlx5_flow_table
*ft
;
642 #define ETHTOOL_NUM_L3_L4_FTS 7
643 #define ETHTOOL_NUM_L2_FTS 4
645 struct mlx5e_ethtool_steering
{
646 struct mlx5e_ethtool_table l3_l4_ft
[ETHTOOL_NUM_L3_L4_FTS
];
647 struct mlx5e_ethtool_table l2_ft
[ETHTOOL_NUM_L2_FTS
];
648 struct list_head rules
;
652 struct mlx5e_flow_steering
{
653 struct mlx5_flow_namespace
*ns
;
654 struct mlx5e_ethtool_steering ethtool
;
655 struct mlx5e_tc_table tc
;
656 struct mlx5e_vlan_table vlan
;
657 struct mlx5e_l2_table l2
;
658 struct mlx5e_ttc_table ttc
;
659 struct mlx5e_arfs_tables arfs
;
669 struct mlx5e_rqt rqt
;
670 struct list_head list
;
678 struct mlx5e_profile
{
679 void (*init
)(struct mlx5_core_dev
*mdev
,
680 struct net_device
*netdev
,
681 const struct mlx5e_profile
*profile
, void *ppriv
);
682 void (*cleanup
)(struct mlx5e_priv
*priv
);
683 int (*init_rx
)(struct mlx5e_priv
*priv
);
684 void (*cleanup_rx
)(struct mlx5e_priv
*priv
);
685 int (*init_tx
)(struct mlx5e_priv
*priv
);
686 void (*cleanup_tx
)(struct mlx5e_priv
*priv
);
687 void (*enable
)(struct mlx5e_priv
*priv
);
688 void (*disable
)(struct mlx5e_priv
*priv
);
689 void (*update_stats
)(struct mlx5e_priv
*priv
);
690 int (*max_nch
)(struct mlx5_core_dev
*mdev
);
695 /* priv data path fields - start */
696 struct mlx5e_sq
**txq_to_sq_map
;
697 int channeltc_to_txq_map
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
698 struct bpf_prog
*xdp_prog
;
699 /* priv data path fields - end */
702 struct mutex state_lock
; /* Protects Interface state */
703 struct mlx5e_rq drop_rq
;
705 struct mlx5e_channel
**channel
;
706 u32 tisn
[MLX5E_MAX_NUM_TC
];
707 struct mlx5e_rqt indir_rqt
;
708 struct mlx5e_tir indir_tir
[MLX5E_NUM_INDIR_TIRS
];
709 struct mlx5e_tir direct_tir
[MLX5E_MAX_NUM_CHANNELS
];
710 u32 tx_rates
[MLX5E_MAX_NUM_SQS
];
712 struct mlx5e_flow_steering fs
;
713 struct mlx5e_vxlan_db vxlan
;
715 struct mlx5e_params params
;
716 struct workqueue_struct
*wq
;
717 struct work_struct update_carrier_work
;
718 struct work_struct set_rx_mode_work
;
719 struct work_struct tx_timeout_work
;
720 struct delayed_work update_stats_work
;
722 struct mlx5_core_dev
*mdev
;
723 struct net_device
*netdev
;
724 struct mlx5e_stats stats
;
725 struct mlx5e_tstamp tstamp
;
727 #ifdef CONFIG_MLX5_CORE_EN_DCB
728 struct mlx5e_dcbx dcbx
;
731 const struct mlx5e_profile
*profile
;
735 void mlx5e_build_ptys2ethtool_map(void);
737 void mlx5e_send_nop(struct mlx5e_sq
*sq
, bool notify_hw
);
738 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
739 void *accel_priv
, select_queue_fallback_t fallback
);
740 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
742 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
);
743 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
744 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
745 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
, int napi_budget
);
746 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
747 void mlx5e_free_sq_descs(struct mlx5e_sq
*sq
);
749 void mlx5e_page_release(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
,
751 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
752 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
753 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
754 int mlx5e_alloc_rx_wqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
);
755 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
);
756 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
);
757 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
);
758 void mlx5e_post_rx_mpwqe(struct mlx5e_rq
*rq
);
759 void mlx5e_free_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
);
760 struct mlx5_cqe64
*mlx5e_get_cqe(struct mlx5e_cq
*cq
);
762 void mlx5e_rx_am(struct mlx5e_rq
*rq
);
763 void mlx5e_rx_am_work(struct work_struct
*work
);
764 struct mlx5e_cq_moder
mlx5e_am_get_def_profile(u8 rx_cq_period_mode
);
766 void mlx5e_update_stats(struct mlx5e_priv
*priv
);
768 int mlx5e_create_flow_steering(struct mlx5e_priv
*priv
);
769 void mlx5e_destroy_flow_steering(struct mlx5e_priv
*priv
);
770 void mlx5e_init_l2_addr(struct mlx5e_priv
*priv
);
771 void mlx5e_destroy_flow_table(struct mlx5e_flow_table
*ft
);
772 int mlx5e_self_test_num(struct mlx5e_priv
*priv
);
773 void mlx5e_self_test(struct net_device
*ndev
, struct ethtool_test
*etest
,
775 int mlx5e_ethtool_get_flow(struct mlx5e_priv
*priv
, struct ethtool_rxnfc
*info
,
777 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv
*priv
,
778 struct ethtool_rxnfc
*info
, u32
*rule_locs
);
779 int mlx5e_ethtool_flow_replace(struct mlx5e_priv
*priv
,
780 struct ethtool_rx_flow_spec
*fs
);
781 int mlx5e_ethtool_flow_remove(struct mlx5e_priv
*priv
,
783 void mlx5e_ethtool_init_steering(struct mlx5e_priv
*priv
);
784 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv
*priv
);
785 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
787 void mlx5e_fill_hwstamp(struct mlx5e_tstamp
*clock
, u64 timestamp
,
788 struct skb_shared_hwtstamps
*hwts
);
789 void mlx5e_timestamp_init(struct mlx5e_priv
*priv
);
790 void mlx5e_timestamp_cleanup(struct mlx5e_priv
*priv
);
791 void mlx5e_pps_event_handler(struct mlx5e_priv
*priv
,
792 struct ptp_clock_event
*event
);
793 int mlx5e_hwstamp_set(struct net_device
*dev
, struct ifreq
*ifr
);
794 int mlx5e_hwstamp_get(struct net_device
*dev
, struct ifreq
*ifr
);
795 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv
*priv
, bool val
);
797 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
799 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
801 void mlx5e_enable_vlan_filter(struct mlx5e_priv
*priv
);
802 void mlx5e_disable_vlan_filter(struct mlx5e_priv
*priv
);
804 int mlx5e_modify_rqs_vsd(struct mlx5e_priv
*priv
, bool vsd
);
806 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
, int ix
);
807 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv
*priv
, void *tirc
,
808 enum mlx5e_traffic_types tt
);
810 int mlx5e_open_locked(struct net_device
*netdev
);
811 int mlx5e_close_locked(struct net_device
*netdev
);
812 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev
*mdev
,
813 u32
*indirection_rqt
, int len
,
815 int mlx5e_get_max_linkspeed(struct mlx5_core_dev
*mdev
, u32
*speed
);
817 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
,
819 void mlx5e_set_rq_type_params(struct mlx5e_priv
*priv
, u8 rq_type
);
821 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq
*sq
,
822 struct mlx5_wqe_ctrl_seg
*ctrl
, int bf_sz
)
824 u16 ofst
= sq
->bf_offset
;
826 /* ensure wqe is visible to device before updating doorbell record */
829 *sq
->wq
.db
= cpu_to_be32(sq
->pc
);
831 /* ensure doorbell record is visible to device before ringing the
836 __iowrite64_copy(sq
->uar_map
+ ofst
, ctrl
, bf_sz
);
838 mlx5_write64((__be32
*)ctrl
, sq
->uar_map
+ ofst
, NULL
);
839 /* flush the write-combining mapped buffer */
842 sq
->bf_offset
^= sq
->bf_buf_size
;
845 static inline void mlx5e_cq_arm(struct mlx5e_cq
*cq
)
847 struct mlx5_core_cq
*mcq
;
850 mlx5_cq_arm(mcq
, MLX5_CQ_DB_REQ_NOT
, mcq
->uar
->map
, cq
->wq
.cc
);
853 static inline u32
mlx5e_get_wqe_mtt_offset(struct mlx5e_rq
*rq
, u16 wqe_ix
)
855 return wqe_ix
* ALIGN(MLX5_MPWRQ_PAGES_PER_WQE
, 8);
858 extern const struct ethtool_ops mlx5e_ethtool_ops
;
859 #ifdef CONFIG_MLX5_CORE_EN_DCB
860 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops
;
861 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv
*priv
, struct ieee_ets
*ets
);
862 void mlx5e_dcbnl_initialize(struct mlx5e_priv
*priv
);
865 #ifndef CONFIG_RFS_ACCEL
866 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv
*priv
)
871 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv
*priv
) {}
873 static inline int mlx5e_arfs_enable(struct mlx5e_priv
*priv
)
878 static inline int mlx5e_arfs_disable(struct mlx5e_priv
*priv
)
883 int mlx5e_arfs_create_tables(struct mlx5e_priv
*priv
);
884 void mlx5e_arfs_destroy_tables(struct mlx5e_priv
*priv
);
885 int mlx5e_arfs_enable(struct mlx5e_priv
*priv
);
886 int mlx5e_arfs_disable(struct mlx5e_priv
*priv
);
887 int mlx5e_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
888 u16 rxq_index
, u32 flow_id
);
891 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
);
892 int mlx5e_create_tir(struct mlx5_core_dev
*mdev
,
893 struct mlx5e_tir
*tir
, u32
*in
, int inlen
);
894 void mlx5e_destroy_tir(struct mlx5_core_dev
*mdev
,
895 struct mlx5e_tir
*tir
);
896 int mlx5e_create_mdev_resources(struct mlx5_core_dev
*mdev
);
897 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev
*mdev
);
898 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev
*mdev
,
901 struct mlx5_eswitch_rep
;
902 int mlx5e_vport_rep_load(struct mlx5_eswitch
*esw
,
903 struct mlx5_eswitch_rep
*rep
);
904 void mlx5e_vport_rep_unload(struct mlx5_eswitch
*esw
,
905 struct mlx5_eswitch_rep
*rep
);
906 int mlx5e_nic_rep_load(struct mlx5_eswitch
*esw
, struct mlx5_eswitch_rep
*rep
);
907 void mlx5e_nic_rep_unload(struct mlx5_eswitch
*esw
,
908 struct mlx5_eswitch_rep
*rep
);
909 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv
*priv
);
910 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv
*priv
);
911 int mlx5e_attr_get(struct net_device
*dev
, struct switchdev_attr
*attr
);
912 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
913 void mlx5e_update_hw_rep_counters(struct mlx5e_priv
*priv
);
915 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
);
916 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
);
917 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
);
918 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
);
919 int mlx5e_create_tises(struct mlx5e_priv
*priv
);
920 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
);
921 int mlx5e_close(struct net_device
*netdev
);
922 int mlx5e_open(struct net_device
*netdev
);
923 void mlx5e_update_stats_work(struct work_struct
*work
);
924 struct net_device
*mlx5e_create_netdev(struct mlx5_core_dev
*mdev
,
925 const struct mlx5e_profile
*profile
,
927 void mlx5e_destroy_netdev(struct mlx5_core_dev
*mdev
, struct mlx5e_priv
*priv
);
928 int mlx5e_attach_netdev(struct mlx5_core_dev
*mdev
, struct net_device
*netdev
);
929 void mlx5e_detach_netdev(struct mlx5_core_dev
*mdev
, struct net_device
*netdev
);
930 u32
mlx5e_choose_lro_timeout(struct mlx5_core_dev
*mdev
, u32 wanted_timeout
);
932 int mlx5e_get_offload_stats(int attr_id
, const struct net_device
*dev
,
934 bool mlx5e_has_offload_stats(const struct net_device
*dev
, int attr_id
);
936 bool mlx5e_is_uplink_rep(struct mlx5e_priv
*priv
);
937 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv
*priv
);
938 #endif /* __MLX5_EN_H__ */