drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include <net/switchdev.h>
  48 #include "wq.h"
  49 #include "mlx5_core.h"
  50 #include "en_stats.h"
  51
  52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  53
  54 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  55 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  56
  57 #define MLX5E_MAX_NUM_TC        8
  58
  59 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  60 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  61 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  62
  63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  66
  67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  70
  71 #define MLX5_RX_HEADROOM NET_SKB_PAD
  72
  73 #define MLX5_MPWRQ_LOG_STRIDE_SIZE              6  /* >= 6, HW restriction */
  74 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8  /* >= 6, HW restriction */
  75 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  76 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  77                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  78 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  79 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  80                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  81
  82 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  83 #define MLX5E_REQUIRED_MTTS(wqes)               \
  84         (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  85 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
  86
  87 #define MLX5_UMR_ALIGN                          (2048)
  88 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (128)
  89
  90 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  91 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
  92 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
  93
  94 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
  95 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
  96 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
  97 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
  98 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
  99 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
 100 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
 101
 102 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 103 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 104 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 105 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 106 #define MLX5E_TX_CQ_POLL_BUDGET        128
 107 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 108 #define MLX5E_SQ_BF_BUDGET             16
 109
 110 #define MLX5E_ICOSQ_MAX_WQEBBS \
 111         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 112
 113 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 114 #define MLX5E_XDP_IHS_DS_COUNT \
 115         DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
 116 #define MLX5E_XDP_TX_DS_COUNT \
 117         (MLX5E_XDP_IHS_DS_COUNT + \
 118          (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 119 #define MLX5E_XDP_TX_WQEBBS \
 120         DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
 121
 122 #define MLX5E_NUM_MAIN_GROUPS 9
 123
 124 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 125 {
 126         switch (wq_type) {
 127         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 128                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 129                              wq_size / 2);
 130         default:
 131                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 132                              wq_size / 2);
 133         }
 134 }
 135
 136 static inline int mlx5_min_log_rq_size(int wq_type)
 137 {
 138         switch (wq_type) {
 139         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 140                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 141         default:
 142                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 143         }
 144 }
 145
 146 static inline int mlx5_max_log_rq_size(int wq_type)
 147 {
 148         switch (wq_type) {
 149         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 150                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 151         default:
 152                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 153         }
 154 }
 155
 156 struct mlx5e_tx_wqe {
 157         struct mlx5_wqe_ctrl_seg ctrl;
 158         struct mlx5_wqe_eth_seg  eth;
 159 };
 160
 161 struct mlx5e_rx_wqe {
 162         struct mlx5_wqe_srq_next_seg  next;
 163         struct mlx5_wqe_data_seg      data;
 164 };
 165
 166 struct mlx5e_umr_wqe {
 167         struct mlx5_wqe_ctrl_seg       ctrl;
 168         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 169         struct mlx5_mkey_seg           mkc;
 170         struct mlx5_wqe_data_seg       data;
 171 };
 172
 173 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
 174
 175 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 176         "rx_cqe_moder",
 177         "rx_cqe_compress",
 178 };
 179
 180 enum mlx5e_priv_flag {
 181         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 182         MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
 183 };
 184
 185 #define MLX5E_SET_PFLAG(priv, pflag, enable)                    \
 186         do {                                                    \
 187                 if (enable)                                     \
 188                         (priv)->params.pflags |= (pflag);       \
 189                 else                                            \
 190                         (priv)->params.pflags &= ~(pflag);      \
 191         } while (0)
 192
 193 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
 194
 195 #ifdef CONFIG_MLX5_CORE_EN_DCB
 196 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 197 #endif
 198
 199 struct mlx5e_cq_moder {
 200         u16 usec;
 201         u16 pkts;
 202 };
 203
 204 struct mlx5e_params {
 205         u8  log_sq_size;
 206         u8  rq_wq_type;
 207         u8  mpwqe_log_stride_sz;
 208         u8  mpwqe_log_num_strides;
 209         u8  log_rq_size;
 210         u16 num_channels;
 211         u8  num_tc;
 212         u8  rx_cq_period_mode;
 213         bool rx_cqe_compress_def;
 214         struct mlx5e_cq_moder rx_cq_moderation;
 215         struct mlx5e_cq_moder tx_cq_moderation;
 216         u16 min_rx_wqes;
 217         bool lro_en;
 218         u32 lro_wqe_sz;
 219         u16 tx_max_inline;
 220         u8  tx_min_inline_mode;
 221         u8  rss_hfunc;
 222         u8  toeplitz_hash_key[40];
 223         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 224         bool vlan_strip_disable;
 225         bool rx_am_enabled;
 226         u32 lro_timeout;
 227         u32 pflags;
 228 };
 229
 230 #ifdef CONFIG_MLX5_CORE_EN_DCB
 231 struct mlx5e_cee_config {
 232         /* bw pct for priority group */
 233         u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];
 234         u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];
 235         bool                       pfc_setting[CEE_DCBX_MAX_PRIO];
 236         bool                       pfc_enable;
 237 };
 238
 239 enum {
 240         MLX5_DCB_CHG_RESET,
 241         MLX5_DCB_NO_CHG,
 242         MLX5_DCB_CHG_NO_RESET,
 243 };
 244
 245 struct mlx5e_dcbx {
 246         enum mlx5_dcbx_oper_mode   mode;
 247         struct mlx5e_cee_config    cee_cfg; /* pending configuration */
 248
 249         /* The only setting that cannot be read from FW */
 250         u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];
 251 };
 252 #endif
 253
 254 struct mlx5e_tstamp {
 255         rwlock_t                   lock;
 256         struct cyclecounter        cycles;
 257         struct timecounter         clock;
 258         struct hwtstamp_config     hwtstamp_config;
 259         u32                        nominal_c_mult;
 260         unsigned long              overflow_period;
 261         struct delayed_work        overflow_work;
 262         struct mlx5_core_dev      *mdev;
 263         struct ptp_clock          *ptp;
 264         struct ptp_clock_info      ptp_info;
 265 };
 266
 267 enum {
 268         MLX5E_RQ_STATE_ENABLED,
 269         MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
 270         MLX5E_RQ_STATE_AM,
 271 };
 272
 273 struct mlx5e_cq {
 274         /* data path - accessed per cqe */
 275         struct mlx5_cqwq           wq;
 276
 277         /* data path - accessed per napi poll */
 278         u16                        event_ctr;
 279         struct napi_struct        *napi;
 280         struct mlx5_core_cq        mcq;
 281         struct mlx5e_channel      *channel;
 282         struct mlx5e_priv         *priv;
 283
 284         /* cqe decompression */
 285         struct mlx5_cqe64          title;
 286         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 287         u8                         mini_arr_idx;
 288         u16                        decmprs_left;
 289         u16                        decmprs_wqe_counter;
 290
 291         /* control */
 292         struct mlx5_frag_wq_ctrl   wq_ctrl;
 293 } ____cacheline_aligned_in_smp;
 294
 295 struct mlx5e_rq;
 296 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
 297                                        struct mlx5_cqe64 *cqe);
 298 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
 299                                   u16 ix);
 300
 301 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
 302
 303 struct mlx5e_dma_info {
 304         struct page     *page;
 305         dma_addr_t      addr;
 306 };
 307
 308 struct mlx5e_rx_am_stats {
 309         int ppms; /* packets per msec */
 310         int epms; /* events per msec */
 311 };
 312
 313 struct mlx5e_rx_am_sample {
 314         ktime_t         time;
 315         unsigned int    pkt_ctr;
 316         u16             event_ctr;
 317 };
 318
 319 struct mlx5e_rx_am { /* Adaptive Moderation */
 320         u8                                      state;
 321         struct mlx5e_rx_am_stats                prev_stats;
 322         struct mlx5e_rx_am_sample               start_sample;
 323         struct work_struct                      work;
 324         u8                                      profile_ix;
 325         u8                                      mode;
 326         u8                                      tune_state;
 327         u8                                      steps_right;
 328         u8                                      steps_left;
 329         u8                                      tired;
 330 };
 331
 332 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 333  * or a MPWQE (for striding rq).
 334  */
 335 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 336                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 337 #define MLX5E_CACHE_SIZE        (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 338 struct mlx5e_page_cache {
 339         u32 head;
 340         u32 tail;
 341         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 342 };
 343
 344 struct mlx5e_rq {
 345         /* data path */
 346         struct mlx5_wq_ll      wq;
 347
 348         union {
 349                 struct mlx5e_dma_info *dma_info;
 350                 struct {
 351                         struct mlx5e_mpw_info *info;
 352                         void                  *mtt_no_align;
 353                 } mpwqe;
 354         };
 355         struct {
 356                 u8             page_order;
 357                 u32            wqe_sz;    /* wqe data buffer size */
 358                 u8             map_dir;   /* dma map direction */
 359         } buff;
 360         __be32                 mkey_be;
 361
 362         struct device         *pdev;
 363         struct net_device     *netdev;
 364         struct mlx5e_tstamp   *tstamp;
 365         struct mlx5e_rq_stats  stats;
 366         struct mlx5e_cq        cq;
 367         struct mlx5e_page_cache page_cache;
 368
 369         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 370         mlx5e_fp_alloc_wqe     alloc_wqe;
 371         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 372
 373         unsigned long          state;
 374         int                    ix;
 375         u16                    rx_headroom;
 376
 377         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 378         struct bpf_prog       *xdp_prog;
 379
 380         /* control */
 381         struct mlx5_wq_ctrl    wq_ctrl;
 382         u8                     wq_type;
 383         u32                    mpwqe_stride_sz;
 384         u32                    mpwqe_num_strides;
 385         u32                    rqn;
 386         struct mlx5e_channel  *channel;
 387         struct mlx5e_priv     *priv;
 388         struct mlx5_core_mkey  umr_mkey;
 389 } ____cacheline_aligned_in_smp;
 390
 391 struct mlx5e_umr_dma_info {
 392         __be64                *mtt;
 393         dma_addr_t             mtt_addr;
 394         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 395         struct mlx5e_umr_wqe   wqe;
 396 };
 397
 398 struct mlx5e_mpw_info {
 399         struct mlx5e_umr_dma_info umr;
 400         u16 consumed_strides;
 401         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 402 };
 403
 404 struct mlx5e_tx_wqe_info {
 405         u32 num_bytes;
 406         u8  num_wqebbs;
 407         u8  num_dma;
 408 };
 409
 410 enum mlx5e_dma_map_type {
 411         MLX5E_DMA_MAP_SINGLE,
 412         MLX5E_DMA_MAP_PAGE
 413 };
 414
 415 struct mlx5e_sq_dma {
 416         dma_addr_t              addr;
 417         u32                     size;
 418         enum mlx5e_dma_map_type type;
 419 };
 420
 421 enum {
 422         MLX5E_SQ_STATE_ENABLED,
 423         MLX5E_SQ_STATE_BF_ENABLE,
 424 };
 425
 426 struct mlx5e_sq_wqe_info {
 427         u8  opcode;
 428         u8  num_wqebbs;
 429 };
 430
 431 enum mlx5e_sq_type {
 432         MLX5E_SQ_TXQ,
 433         MLX5E_SQ_ICO,
 434         MLX5E_SQ_XDP
 435 };
 436
 437 struct mlx5e_sq {
 438         /* data path */
 439
 440         /* dirtied @completion */
 441         u16                        cc;
 442         u32                        dma_fifo_cc;
 443
 444         /* dirtied @xmit */
 445         u16                        pc ____cacheline_aligned_in_smp;
 446         u32                        dma_fifo_pc;
 447         u16                        bf_offset;
 448         u16                        prev_cc;
 449         u8                         bf_budget;
 450         struct mlx5e_sq_stats      stats;
 451
 452         struct mlx5e_cq            cq;
 453
 454         /* pointers to per tx element info: write@xmit, read@completion */
 455         union {
 456                 struct {
 457                         struct sk_buff           **skb;
 458                         struct mlx5e_sq_dma       *dma_fifo;
 459                         struct mlx5e_tx_wqe_info  *wqe_info;
 460                 } txq;
 461                 struct mlx5e_sq_wqe_info *ico_wqe;
 462                 struct {
 463                         struct mlx5e_sq_wqe_info  *wqe_info;
 464                         struct mlx5e_dma_info     *di;
 465                         bool                       doorbell;
 466                 } xdp;
 467         } db;
 468
 469         /* read only */
 470         struct mlx5_wq_cyc         wq;
 471         u32                        dma_fifo_mask;
 472         struct netdev_queue       *txq;
 473         u32                        sqn;
 474         u16                        bf_buf_size;
 475         u16                        max_inline;
 476         u8                         min_inline_mode;
 477         u16                        edge;
 478         struct device             *pdev;
 479         struct mlx5e_tstamp       *tstamp;
 480         __be32                     mkey_be;
 481         unsigned long              state;
 482
 483         /* control path */
 484         struct mlx5_wq_ctrl        wq_ctrl;
 485         struct mlx5_sq_bfreg       bfreg;
 486         struct mlx5e_channel      *channel;
 487         int                        tc;
 488         u32                        rate_limit;
 489         u8                         type;
 490 } ____cacheline_aligned_in_smp;
 491
 492 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 493 {
 494         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 495                 (sq->cc  == sq->pc));
 496 }
 497
 498 enum channel_flags {
 499         MLX5E_CHANNEL_NAPI_SCHED = 1,
 500 };
 501
 502 struct mlx5e_channel {
 503         /* data path */
 504         struct mlx5e_rq            rq;
 505         struct mlx5e_sq            xdp_sq;
 506         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 507         struct mlx5e_sq            icosq;   /* internal control operations */
 508         bool                       xdp;
 509         struct napi_struct         napi;
 510         struct device             *pdev;
 511         struct net_device         *netdev;
 512         __be32                     mkey_be;
 513         u8                         num_tc;
 514         unsigned long              flags;
 515
 516         /* control */
 517         struct mlx5e_priv         *priv;
 518         int                        ix;
 519         int                        cpu;
 520 };
 521
 522 enum mlx5e_traffic_types {
 523         MLX5E_TT_IPV4_TCP,
 524         MLX5E_TT_IPV6_TCP,
 525         MLX5E_TT_IPV4_UDP,
 526         MLX5E_TT_IPV6_UDP,
 527         MLX5E_TT_IPV4_IPSEC_AH,
 528         MLX5E_TT_IPV6_IPSEC_AH,
 529         MLX5E_TT_IPV4_IPSEC_ESP,
 530         MLX5E_TT_IPV6_IPSEC_ESP,
 531         MLX5E_TT_IPV4,
 532         MLX5E_TT_IPV6,
 533         MLX5E_TT_ANY,
 534         MLX5E_NUM_TT,
 535         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 536 };
 537
 538 enum {
 539         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 540         MLX5E_STATE_OPENED,
 541         MLX5E_STATE_DESTROYING,
 542 };
 543
 544 struct mlx5e_vxlan_db {
 545         spinlock_t                      lock; /* protect vxlan table */
 546         struct radix_tree_root          tree;
 547 };
 548
 549 struct mlx5e_l2_rule {
 550         u8  addr[ETH_ALEN + 2];
 551         struct mlx5_flow_handle *rule;
 552 };
 553
 554 struct mlx5e_flow_table {
 555         int num_groups;
 556         struct mlx5_flow_table *t;
 557         struct mlx5_flow_group **g;
 558 };
 559
 560 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 561
 562 struct mlx5e_tc_table {
 563         struct mlx5_flow_table          *t;
 564
 565         struct rhashtable_params        ht_params;
 566         struct rhashtable               ht;
 567 };
 568
 569 struct mlx5e_vlan_table {
 570         struct mlx5e_flow_table         ft;
 571         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 572         struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
 573         struct mlx5_flow_handle *untagged_rule;
 574         struct mlx5_flow_handle *any_vlan_rule;
 575         bool            filter_disabled;
 576 };
 577
 578 struct mlx5e_l2_table {
 579         struct mlx5e_flow_table    ft;
 580         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 581         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 582         struct mlx5e_l2_rule       broadcast;
 583         struct mlx5e_l2_rule       allmulti;
 584         struct mlx5e_l2_rule       promisc;
 585         bool                       broadcast_enabled;
 586         bool                       allmulti_enabled;
 587         bool                       promisc_enabled;
 588 };
 589
 590 /* L3/L4 traffic type classifier */
 591 struct mlx5e_ttc_table {
 592         struct mlx5e_flow_table  ft;
 593         struct mlx5_flow_handle  *rules[MLX5E_NUM_TT];
 594 };
 595
 596 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 597 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 598 struct arfs_table {
 599         struct mlx5e_flow_table  ft;
 600         struct mlx5_flow_handle  *default_rule;
 601         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 602 };
 603
 604 enum  arfs_type {
 605         ARFS_IPV4_TCP,
 606         ARFS_IPV6_TCP,
 607         ARFS_IPV4_UDP,
 608         ARFS_IPV6_UDP,
 609         ARFS_NUM_TYPES,
 610 };
 611
 612 struct mlx5e_arfs_tables {
 613         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 614         /* Protect aRFS rules list */
 615         spinlock_t                     arfs_lock;
 616         struct list_head               rules;
 617         int                            last_filter_id;
 618         struct workqueue_struct        *wq;
 619 };
 620
 621 /* NIC prio FTS */
 622 enum {
 623         MLX5E_VLAN_FT_LEVEL = 0,
 624         MLX5E_L2_FT_LEVEL,
 625         MLX5E_TTC_FT_LEVEL,
 626         MLX5E_ARFS_FT_LEVEL
 627 };
 628
 629 struct mlx5e_ethtool_table {
 630         struct mlx5_flow_table *ft;
 631         int                    num_rules;
 632 };
 633
 634 #define ETHTOOL_NUM_L3_L4_FTS 7
 635 #define ETHTOOL_NUM_L2_FTS 4
 636
 637 struct mlx5e_ethtool_steering {
 638         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 639         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 640         struct list_head                rules;
 641         int                             tot_num_rules;
 642 };
 643
 644 struct mlx5e_flow_steering {
 645         struct mlx5_flow_namespace      *ns;
 646         struct mlx5e_ethtool_steering   ethtool;
 647         struct mlx5e_tc_table           tc;
 648         struct mlx5e_vlan_table         vlan;
 649         struct mlx5e_l2_table           l2;
 650         struct mlx5e_ttc_table          ttc;
 651         struct mlx5e_arfs_tables        arfs;
 652 };
 653
 654 struct mlx5e_rqt {
 655         u32              rqtn;
 656         bool             enabled;
 657 };
 658
 659 struct mlx5e_tir {
 660         u32               tirn;
 661         struct mlx5e_rqt  rqt;
 662         struct list_head  list;
 663 };
 664
 665 enum {
 666         MLX5E_TC_PRIO = 0,
 667         MLX5E_NIC_PRIO
 668 };
 669
 670 struct mlx5e_profile {
 671         void    (*init)(struct mlx5_core_dev *mdev,
 672                         struct net_device *netdev,
 673                         const struct mlx5e_profile *profile, void *ppriv);
 674         void    (*cleanup)(struct mlx5e_priv *priv);
 675         int     (*init_rx)(struct mlx5e_priv *priv);
 676         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 677         int     (*init_tx)(struct mlx5e_priv *priv);
 678         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 679         void    (*enable)(struct mlx5e_priv *priv);
 680         void    (*disable)(struct mlx5e_priv *priv);
 681         void    (*update_stats)(struct mlx5e_priv *priv);
 682         int     (*max_nch)(struct mlx5_core_dev *mdev);
 683         int     max_tc;
 684 };
 685
 686 struct mlx5e_priv {
 687         /* priv data path fields - start */
 688         struct mlx5e_sq            **txq_to_sq_map;
 689         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 690         struct bpf_prog *xdp_prog;
 691         /* priv data path fields - end */
 692
 693         unsigned long              state;
 694         struct mutex               state_lock; /* Protects Interface state */
 695         struct mlx5e_rq            drop_rq;
 696
 697         struct mlx5e_channel     **channel;
 698         u32                        tisn[MLX5E_MAX_NUM_TC];
 699         struct mlx5e_rqt           indir_rqt;
 700         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 701         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 702         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 703
 704         struct mlx5e_flow_steering fs;
 705         struct mlx5e_vxlan_db      vxlan;
 706
 707         struct mlx5e_params        params;
 708         struct workqueue_struct    *wq;
 709         struct work_struct         update_carrier_work;
 710         struct work_struct         set_rx_mode_work;
 711         struct work_struct         tx_timeout_work;
 712         struct delayed_work        update_stats_work;
 713
 714         struct mlx5_core_dev      *mdev;
 715         struct net_device         *netdev;
 716         struct mlx5e_stats         stats;
 717         struct mlx5e_tstamp        tstamp;
 718         u16 q_counter;
 719 #ifdef CONFIG_MLX5_CORE_EN_DCB
 720         struct mlx5e_dcbx          dcbx;
 721 #endif
 722
 723         const struct mlx5e_profile *profile;
 724         void                      *ppriv;
 725 };
 726
 727 void mlx5e_build_ptys2ethtool_map(void);
 728
 729 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 730 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 731                        void *accel_priv, select_queue_fallback_t fallback);
 732 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 733
 734 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 735 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 736 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 737 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 738 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 739 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
 740
 741 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 742                         bool recycle);
 743 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 744 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 745 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 746 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 747 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 748 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 749 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 750 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 751 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 752 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 753
 754 void mlx5e_rx_am(struct mlx5e_rq *rq);
 755 void mlx5e_rx_am_work(struct work_struct *work);
 756 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 757
 758 void mlx5e_update_stats(struct mlx5e_priv *priv);
 759
 760 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 761 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 762 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 763 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 764 int mlx5e_self_test_num(struct mlx5e_priv *priv);
 765 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
 766                      u64 *buf);
 767 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 768                            int location);
 769 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 770                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 771 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 772                                struct ethtool_rx_flow_spec *fs);
 773 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 774                               int location);
 775 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 776 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 777 void mlx5e_set_rx_mode_work(struct work_struct *work);
 778
 779 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 780                         struct skb_shared_hwtstamps *hwts);
 781 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 782 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 783 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 784 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 785 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
 786
 787 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 788                           u16 vid);
 789 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 790                            u16 vid);
 791 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 792 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 793
 794 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
 795
 796 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
 797 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
 798
 799 int mlx5e_open_locked(struct net_device *netdev);
 800 int mlx5e_close_locked(struct net_device *netdev);
 801 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 802                                    u32 *indirection_rqt, int len,
 803                                    int num_channels);
 804 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 805
 806 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 807                                  u8 cq_period_mode);
 808
 809 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
 810                                       struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
 811 {
 812         u16 ofst = sq->bf_offset;
 813
 814         /* ensure wqe is visible to device before updating doorbell record */
 815         dma_wmb();
 816
 817         *sq->wq.db = cpu_to_be32(sq->pc);
 818
 819         /* ensure doorbell record is visible to device before ringing the
 820          * doorbell
 821          */
 822         wmb();
 823         if (bf_sz)
 824                 __iowrite64_copy(sq->bfreg.map + ofst, ctrl, bf_sz);
 825         else
 826                 mlx5_write64((__be32 *)ctrl, sq->bfreg.map + ofst, NULL);
 827         /* flush the write-combining mapped buffer */
 828         wmb();
 829
 830         sq->bf_offset ^= sq->bf_buf_size;
 831 }
 832
 833 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 834 {
 835         struct mlx5_core_cq *mcq;
 836
 837         mcq = &cq->mcq;
 838         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 839 }
 840
 841 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 842 {
 843         return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 844 }
 845
 846 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 847 {
 848         return min_t(int, mdev->priv.eq_table.num_comp_vectors,
 849                      MLX5E_MAX_NUM_CHANNELS);
 850 }
 851
 852 extern const struct ethtool_ops mlx5e_ethtool_ops;
 853 #ifdef CONFIG_MLX5_CORE_EN_DCB
 854 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 855 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 856 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
 857 #endif
 858
 859 #ifndef CONFIG_RFS_ACCEL
 860 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
 861 {
 862         return 0;
 863 }
 864
 865 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
 866
 867 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
 868 {
 869         return -ENOTSUPP;
 870 }
 871
 872 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
 873 {
 874         return -ENOTSUPP;
 875 }
 876 #else
 877 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
 878 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
 879 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
 880 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
 881 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
 882                         u16 rxq_index, u32 flow_id);
 883 #endif
 884
 885 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 886 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
 887                      struct mlx5e_tir *tir, u32 *in, int inlen);
 888 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
 889                        struct mlx5e_tir *tir);
 890 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
 891 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
 892 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
 893                                      bool enable_uc_lb);
 894
 895 struct mlx5_eswitch_rep;
 896 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
 897                          struct mlx5_eswitch_rep *rep);
 898 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
 899                             struct mlx5_eswitch_rep *rep);
 900 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
 901 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
 902                           struct mlx5_eswitch_rep *rep);
 903 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
 904 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
 905 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
 906 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 907 void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv);
 908
 909 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
 910 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
 911 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
 912 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
 913 int mlx5e_create_tises(struct mlx5e_priv *priv);
 914 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
 915 int mlx5e_close(struct net_device *netdev);
 916 int mlx5e_open(struct net_device *netdev);
 917 void mlx5e_update_stats_work(struct work_struct *work);
 918 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
 919                                        const struct mlx5e_profile *profile,
 920                                        void *ppriv);
 921 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
 922 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 923 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 924 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
 925 void mlx5e_add_vxlan_port(struct net_device *netdev,
 926                           struct udp_tunnel_info *ti);
 927 void mlx5e_del_vxlan_port(struct net_device *netdev,
 928                           struct udp_tunnel_info *ti);
 929
 930 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
 931                             void *sp);
 932 bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id);
 933
 934 bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv);
 935 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv);
 936 #endif /* __MLX5_EN_H__ */