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Merge tag 'csky-for-linus-5.0-rc6' of git://github.com/c-sky/csky-linux
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34 #include "en/port.h"
35 #include "lib/clock.h"
36
37 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
38 struct ethtool_drvinfo *drvinfo)
39 {
40 struct mlx5_core_dev *mdev = priv->mdev;
41
42 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
43 strlcpy(drvinfo->version, DRIVER_VERSION,
44 sizeof(drvinfo->version));
45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 "%d.%d.%04d (%.16s)",
47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
48 mdev->board_id);
49 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
50 sizeof(drvinfo->bus_info));
51 }
52
53 static void mlx5e_get_drvinfo(struct net_device *dev,
54 struct ethtool_drvinfo *drvinfo)
55 {
56 struct mlx5e_priv *priv = netdev_priv(dev);
57
58 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
59 }
60
61 struct ptys2ethtool_config {
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
64 };
65
66 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
67
68 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, ...) \
69 ({ \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
72 unsigned int i; \
73 cfg = &ptys2ethtool_table[reg_]; \
74 bitmap_zero(cfg->supported, \
75 __ETHTOOL_LINK_MODE_MASK_NBITS); \
76 bitmap_zero(cfg->advertised, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
79 __set_bit(modes[i], cfg->supported); \
80 __set_bit(modes[i], cfg->advertised); \
81 } \
82 })
83
84 void mlx5e_build_ptys2ethtool_map(void)
85 {
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII,
87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX,
89 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4,
91 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4,
93 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR,
95 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2,
97 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4,
99 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4,
101 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4,
103 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR,
105 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR,
107 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER,
109 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4,
111 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4,
113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2,
115 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4,
117 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4,
119 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4,
121 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4,
123 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T,
125 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR,
127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR,
129 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR,
131 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2,
133 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2,
135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
136 }
137
138 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
139
140 struct pflag_desc {
141 char name[ETH_GSTRING_LEN];
142 mlx5e_pflag_handler handler;
143 };
144
145 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
146
147 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
148 {
149 int i, num_stats = 0;
150
151 switch (sset) {
152 case ETH_SS_STATS:
153 for (i = 0; i < mlx5e_num_stats_grps; i++)
154 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
155 return num_stats;
156 case ETH_SS_PRIV_FLAGS:
157 return MLX5E_NUM_PFLAGS;
158 case ETH_SS_TEST:
159 return mlx5e_self_test_num(priv);
160 /* fallthrough */
161 default:
162 return -EOPNOTSUPP;
163 }
164 }
165
166 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
167 {
168 struct mlx5e_priv *priv = netdev_priv(dev);
169
170 return mlx5e_ethtool_get_sset_count(priv, sset);
171 }
172
173 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
174 {
175 int i, idx = 0;
176
177 for (i = 0; i < mlx5e_num_stats_grps; i++)
178 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
179 }
180
181 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
182 {
183 int i;
184
185 switch (stringset) {
186 case ETH_SS_PRIV_FLAGS:
187 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
188 strcpy(data + i * ETH_GSTRING_LEN,
189 mlx5e_priv_flags[i].name);
190 break;
191
192 case ETH_SS_TEST:
193 for (i = 0; i < mlx5e_self_test_num(priv); i++)
194 strcpy(data + i * ETH_GSTRING_LEN,
195 mlx5e_self_tests[i]);
196 break;
197
198 case ETH_SS_STATS:
199 mlx5e_fill_stats_strings(priv, data);
200 break;
201 }
202 }
203
204 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
205 {
206 struct mlx5e_priv *priv = netdev_priv(dev);
207
208 mlx5e_ethtool_get_strings(priv, stringset, data);
209 }
210
211 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
212 struct ethtool_stats *stats, u64 *data)
213 {
214 int i, idx = 0;
215
216 mutex_lock(&priv->state_lock);
217 mlx5e_update_stats(priv);
218 mutex_unlock(&priv->state_lock);
219
220 for (i = 0; i < mlx5e_num_stats_grps; i++)
221 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
222 }
223
224 static void mlx5e_get_ethtool_stats(struct net_device *dev,
225 struct ethtool_stats *stats,
226 u64 *data)
227 {
228 struct mlx5e_priv *priv = netdev_priv(dev);
229
230 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
231 }
232
233 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
234 struct ethtool_ringparam *param)
235 {
236 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
237 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
238 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
239 param->tx_pending = 1 << priv->channels.params.log_sq_size;
240 }
241
242 static void mlx5e_get_ringparam(struct net_device *dev,
243 struct ethtool_ringparam *param)
244 {
245 struct mlx5e_priv *priv = netdev_priv(dev);
246
247 mlx5e_ethtool_get_ringparam(priv, param);
248 }
249
250 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
251 struct ethtool_ringparam *param)
252 {
253 struct mlx5e_channels new_channels = {};
254 u8 log_rq_size;
255 u8 log_sq_size;
256 int err = 0;
257
258 if (param->rx_jumbo_pending) {
259 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
260 __func__);
261 return -EINVAL;
262 }
263 if (param->rx_mini_pending) {
264 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
265 __func__);
266 return -EINVAL;
267 }
268
269 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
270 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
271 __func__, param->rx_pending,
272 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
273 return -EINVAL;
274 }
275
276 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
277 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
278 __func__, param->tx_pending,
279 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
280 return -EINVAL;
281 }
282
283 log_rq_size = order_base_2(param->rx_pending);
284 log_sq_size = order_base_2(param->tx_pending);
285
286 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
287 log_sq_size == priv->channels.params.log_sq_size)
288 return 0;
289
290 mutex_lock(&priv->state_lock);
291
292 new_channels.params = priv->channels.params;
293 new_channels.params.log_rq_mtu_frames = log_rq_size;
294 new_channels.params.log_sq_size = log_sq_size;
295
296 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
297 priv->channels.params = new_channels.params;
298 goto unlock;
299 }
300
301 err = mlx5e_open_channels(priv, &new_channels);
302 if (err)
303 goto unlock;
304
305 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
306
307 unlock:
308 mutex_unlock(&priv->state_lock);
309
310 return err;
311 }
312
313 static int mlx5e_set_ringparam(struct net_device *dev,
314 struct ethtool_ringparam *param)
315 {
316 struct mlx5e_priv *priv = netdev_priv(dev);
317
318 return mlx5e_ethtool_set_ringparam(priv, param);
319 }
320
321 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
322 struct ethtool_channels *ch)
323 {
324 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
325 ch->combined_count = priv->channels.params.num_channels;
326 }
327
328 static void mlx5e_get_channels(struct net_device *dev,
329 struct ethtool_channels *ch)
330 {
331 struct mlx5e_priv *priv = netdev_priv(dev);
332
333 mlx5e_ethtool_get_channels(priv, ch);
334 }
335
336 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
337 struct ethtool_channels *ch)
338 {
339 unsigned int count = ch->combined_count;
340 struct mlx5e_channels new_channels = {};
341 bool arfs_enabled;
342 int err = 0;
343
344 if (!count) {
345 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
346 __func__);
347 return -EINVAL;
348 }
349
350 if (priv->channels.params.num_channels == count)
351 return 0;
352
353 mutex_lock(&priv->state_lock);
354
355 new_channels.params = priv->channels.params;
356 new_channels.params.num_channels = count;
357
358 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
359 priv->channels.params = new_channels.params;
360 goto out;
361 }
362
363 /* Create fresh channels with new parameters */
364 err = mlx5e_open_channels(priv, &new_channels);
365 if (err)
366 goto out;
367
368 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
369 if (arfs_enabled)
370 mlx5e_arfs_disable(priv);
371
372 if (!netif_is_rxfh_configured(priv->netdev))
373 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
374 MLX5E_INDIR_RQT_SIZE, count);
375
376 /* Switch to new channels, set new parameters and close old ones */
377 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
378
379 if (arfs_enabled) {
380 err = mlx5e_arfs_enable(priv);
381 if (err)
382 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
383 __func__, err);
384 }
385
386 out:
387 mutex_unlock(&priv->state_lock);
388
389 return err;
390 }
391
392 static int mlx5e_set_channels(struct net_device *dev,
393 struct ethtool_channels *ch)
394 {
395 struct mlx5e_priv *priv = netdev_priv(dev);
396
397 return mlx5e_ethtool_set_channels(priv, ch);
398 }
399
400 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
401 struct ethtool_coalesce *coal)
402 {
403 struct net_dim_cq_moder *rx_moder, *tx_moder;
404
405 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
406 return -EOPNOTSUPP;
407
408 rx_moder = &priv->channels.params.rx_cq_moderation;
409 coal->rx_coalesce_usecs = rx_moder->usec;
410 coal->rx_max_coalesced_frames = rx_moder->pkts;
411 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
412
413 tx_moder = &priv->channels.params.tx_cq_moderation;
414 coal->tx_coalesce_usecs = tx_moder->usec;
415 coal->tx_max_coalesced_frames = tx_moder->pkts;
416 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
417
418 return 0;
419 }
420
421 static int mlx5e_get_coalesce(struct net_device *netdev,
422 struct ethtool_coalesce *coal)
423 {
424 struct mlx5e_priv *priv = netdev_priv(netdev);
425
426 return mlx5e_ethtool_get_coalesce(priv, coal);
427 }
428
429 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
430 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
431
432 static void
433 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
434 {
435 struct mlx5_core_dev *mdev = priv->mdev;
436 int tc;
437 int i;
438
439 for (i = 0; i < priv->channels.num; ++i) {
440 struct mlx5e_channel *c = priv->channels.c[i];
441
442 for (tc = 0; tc < c->num_tc; tc++) {
443 mlx5_core_modify_cq_moderation(mdev,
444 &c->sq[tc].cq.mcq,
445 coal->tx_coalesce_usecs,
446 coal->tx_max_coalesced_frames);
447 }
448
449 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
450 coal->rx_coalesce_usecs,
451 coal->rx_max_coalesced_frames);
452 }
453 }
454
455 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
456 struct ethtool_coalesce *coal)
457 {
458 struct net_dim_cq_moder *rx_moder, *tx_moder;
459 struct mlx5_core_dev *mdev = priv->mdev;
460 struct mlx5e_channels new_channels = {};
461 int err = 0;
462 bool reset;
463
464 if (!MLX5_CAP_GEN(mdev, cq_moderation))
465 return -EOPNOTSUPP;
466
467 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
468 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
469 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
470 __func__, MLX5E_MAX_COAL_TIME);
471 return -ERANGE;
472 }
473
474 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
475 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
476 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
477 __func__, MLX5E_MAX_COAL_FRAMES);
478 return -ERANGE;
479 }
480
481 mutex_lock(&priv->state_lock);
482 new_channels.params = priv->channels.params;
483
484 rx_moder = &new_channels.params.rx_cq_moderation;
485 rx_moder->usec = coal->rx_coalesce_usecs;
486 rx_moder->pkts = coal->rx_max_coalesced_frames;
487 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
488
489 tx_moder = &new_channels.params.tx_cq_moderation;
490 tx_moder->usec = coal->tx_coalesce_usecs;
491 tx_moder->pkts = coal->tx_max_coalesced_frames;
492 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
493
494 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
495 priv->channels.params = new_channels.params;
496 goto out;
497 }
498 /* we are opened */
499
500 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
501 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
502
503 if (!reset) {
504 mlx5e_set_priv_channels_coalesce(priv, coal);
505 priv->channels.params = new_channels.params;
506 goto out;
507 }
508
509 /* open fresh channels with new coal parameters */
510 err = mlx5e_open_channels(priv, &new_channels);
511 if (err)
512 goto out;
513
514 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
515
516 out:
517 mutex_unlock(&priv->state_lock);
518 return err;
519 }
520
521 static int mlx5e_set_coalesce(struct net_device *netdev,
522 struct ethtool_coalesce *coal)
523 {
524 struct mlx5e_priv *priv = netdev_priv(netdev);
525
526 return mlx5e_ethtool_set_coalesce(priv, coal);
527 }
528
529 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
530 u32 eth_proto_cap)
531 {
532 unsigned long proto_cap = eth_proto_cap;
533 int proto;
534
535 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
536 bitmap_or(supported_modes, supported_modes,
537 ptys2ethtool_table[proto].supported,
538 __ETHTOOL_LINK_MODE_MASK_NBITS);
539 }
540
541 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
542 u32 eth_proto_cap)
543 {
544 unsigned long proto_cap = eth_proto_cap;
545 int proto;
546
547 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
548 bitmap_or(advertising_modes, advertising_modes,
549 ptys2ethtool_table[proto].advertised,
550 __ETHTOOL_LINK_MODE_MASK_NBITS);
551 }
552
553 static const u32 pplm_fec_2_ethtool[] = {
554 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
555 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
556 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
557 };
558
559 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
560 {
561 int mode = 0;
562
563 if (!fec_mode)
564 return ETHTOOL_FEC_AUTO;
565
566 mode = find_first_bit(&fec_mode, size);
567
568 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
569 return pplm_fec_2_ethtool[mode];
570
571 return 0;
572 }
573
574 /* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
575 static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
576 {
577 u32 offset;
578
579 offset = find_first_bit(&ethtool_fec_code, sizeof(u32));
580 offset -= ETHTOOL_FEC_OFF_BIT;
581 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
582
583 return offset;
584 }
585
586 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
587 struct ethtool_link_ksettings *link_ksettings)
588 {
589 u_long fec_caps = 0;
590 u32 active_fec = 0;
591 u32 offset;
592 u32 bitn;
593 int err;
594
595 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
596 if (err)
597 return (err == -EOPNOTSUPP) ? 0 : err;
598
599 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
600 if (err)
601 return err;
602
603 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
604 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
605
606 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
607 __set_bit(offset, link_ksettings->link_modes.supported);
608 }
609
610 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
611 offset = ethtool_fec2ethtool_caps(active_fec);
612 __set_bit(offset, link_ksettings->link_modes.advertising);
613
614 return 0;
615 }
616
617 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
618 u32 eth_proto_cap,
619 u8 connector_type)
620 {
621 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
622 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
623 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
624 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
625 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
626 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
627 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
628 ethtool_link_ksettings_add_link_mode(link_ksettings,
629 supported,
630 FIBRE);
631 ethtool_link_ksettings_add_link_mode(link_ksettings,
632 advertising,
633 FIBRE);
634 }
635
636 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
637 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
638 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
639 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
640 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
641 ethtool_link_ksettings_add_link_mode(link_ksettings,
642 supported,
643 Backplane);
644 ethtool_link_ksettings_add_link_mode(link_ksettings,
645 advertising,
646 Backplane);
647 }
648 return;
649 }
650
651 switch (connector_type) {
652 case MLX5E_PORT_TP:
653 ethtool_link_ksettings_add_link_mode(link_ksettings,
654 supported, TP);
655 ethtool_link_ksettings_add_link_mode(link_ksettings,
656 advertising, TP);
657 break;
658 case MLX5E_PORT_AUI:
659 ethtool_link_ksettings_add_link_mode(link_ksettings,
660 supported, AUI);
661 ethtool_link_ksettings_add_link_mode(link_ksettings,
662 advertising, AUI);
663 break;
664 case MLX5E_PORT_BNC:
665 ethtool_link_ksettings_add_link_mode(link_ksettings,
666 supported, BNC);
667 ethtool_link_ksettings_add_link_mode(link_ksettings,
668 advertising, BNC);
669 break;
670 case MLX5E_PORT_MII:
671 ethtool_link_ksettings_add_link_mode(link_ksettings,
672 supported, MII);
673 ethtool_link_ksettings_add_link_mode(link_ksettings,
674 advertising, MII);
675 break;
676 case MLX5E_PORT_FIBRE:
677 ethtool_link_ksettings_add_link_mode(link_ksettings,
678 supported, FIBRE);
679 ethtool_link_ksettings_add_link_mode(link_ksettings,
680 advertising, FIBRE);
681 break;
682 case MLX5E_PORT_DA:
683 ethtool_link_ksettings_add_link_mode(link_ksettings,
684 supported, Backplane);
685 ethtool_link_ksettings_add_link_mode(link_ksettings,
686 advertising, Backplane);
687 break;
688 case MLX5E_PORT_NONE:
689 case MLX5E_PORT_OTHER:
690 default:
691 break;
692 }
693 }
694
695 static void get_speed_duplex(struct net_device *netdev,
696 u32 eth_proto_oper,
697 struct ethtool_link_ksettings *link_ksettings)
698 {
699 u32 speed = SPEED_UNKNOWN;
700 u8 duplex = DUPLEX_UNKNOWN;
701
702 if (!netif_carrier_ok(netdev))
703 goto out;
704
705 speed = mlx5e_port_ptys2speed(eth_proto_oper);
706 if (!speed) {
707 speed = SPEED_UNKNOWN;
708 goto out;
709 }
710
711 duplex = DUPLEX_FULL;
712
713 out:
714 link_ksettings->base.speed = speed;
715 link_ksettings->base.duplex = duplex;
716 }
717
718 static void get_supported(u32 eth_proto_cap,
719 struct ethtool_link_ksettings *link_ksettings)
720 {
721 unsigned long *supported = link_ksettings->link_modes.supported;
722
723 ptys2ethtool_supported_link(supported, eth_proto_cap);
724 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
725 }
726
727 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
728 u8 rx_pause,
729 struct ethtool_link_ksettings *link_ksettings)
730 {
731 unsigned long *advertising = link_ksettings->link_modes.advertising;
732
733 ptys2ethtool_adver_link(advertising, eth_proto_cap);
734 if (rx_pause)
735 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
736 if (tx_pause ^ rx_pause)
737 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
738 }
739
740 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
741 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
742 [MLX5E_PORT_NONE] = PORT_NONE,
743 [MLX5E_PORT_TP] = PORT_TP,
744 [MLX5E_PORT_AUI] = PORT_AUI,
745 [MLX5E_PORT_BNC] = PORT_BNC,
746 [MLX5E_PORT_MII] = PORT_MII,
747 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
748 [MLX5E_PORT_DA] = PORT_DA,
749 [MLX5E_PORT_OTHER] = PORT_OTHER,
750 };
751
752 static u8 get_connector_port(u32 eth_proto, u8 connector_type)
753 {
754 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
755 return ptys2connector_type[connector_type];
756
757 if (eth_proto &
758 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
759 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
760 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
761 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
762 return PORT_FIBRE;
763 }
764
765 if (eth_proto &
766 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
767 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
768 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
769 return PORT_DA;
770 }
771
772 if (eth_proto &
773 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
774 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
775 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
776 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
777 return PORT_NONE;
778 }
779
780 return PORT_OTHER;
781 }
782
783 static void get_lp_advertising(u32 eth_proto_lp,
784 struct ethtool_link_ksettings *link_ksettings)
785 {
786 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
787
788 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
789 }
790
791 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
792 struct ethtool_link_ksettings *link_ksettings)
793 {
794 struct mlx5_core_dev *mdev = priv->mdev;
795 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
796 u32 rx_pause = 0;
797 u32 tx_pause = 0;
798 u32 eth_proto_cap;
799 u32 eth_proto_admin;
800 u32 eth_proto_lp;
801 u32 eth_proto_oper;
802 u8 an_disable_admin;
803 u8 an_status;
804 u8 connector_type;
805 int err;
806
807 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
808 if (err) {
809 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
810 __func__, err);
811 goto err_query_regs;
812 }
813
814 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
815 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
816 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
817 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
818 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
819 an_status = MLX5_GET(ptys_reg, out, an_status);
820 connector_type = MLX5_GET(ptys_reg, out, connector_type);
821
822 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
823
824 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
825 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
826
827 get_supported(eth_proto_cap, link_ksettings);
828 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
829 get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings);
830
831 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
832
833 link_ksettings->base.port = get_connector_port(eth_proto_oper,
834 connector_type);
835 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
836 connector_type);
837 get_lp_advertising(eth_proto_lp, link_ksettings);
838
839 if (an_status == MLX5_AN_COMPLETE)
840 ethtool_link_ksettings_add_link_mode(link_ksettings,
841 lp_advertising, Autoneg);
842
843 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
844 AUTONEG_ENABLE;
845 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
846 Autoneg);
847
848 err = get_fec_supported_advertised(mdev, link_ksettings);
849 if (err) {
850 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
851 __func__, err);
852 err = 0; /* don't fail caps query because of FEC error */
853 }
854
855 if (!an_disable_admin)
856 ethtool_link_ksettings_add_link_mode(link_ksettings,
857 advertising, Autoneg);
858
859 err_query_regs:
860 return err;
861 }
862
863 static int mlx5e_get_link_ksettings(struct net_device *netdev,
864 struct ethtool_link_ksettings *link_ksettings)
865 {
866 struct mlx5e_priv *priv = netdev_priv(netdev);
867
868 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
869 }
870
871 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
872 {
873 u32 i, ptys_modes = 0;
874
875 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
876 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
877 link_modes,
878 __ETHTOOL_LINK_MODE_MASK_NBITS))
879 ptys_modes |= MLX5E_PROT_MASK(i);
880 }
881
882 return ptys_modes;
883 }
884
885 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
886 const struct ethtool_link_ksettings *link_ksettings)
887 {
888 struct mlx5_core_dev *mdev = priv->mdev;
889 u32 eth_proto_cap, eth_proto_admin;
890 bool an_changes = false;
891 u8 an_disable_admin;
892 u8 an_disable_cap;
893 bool an_disable;
894 u32 link_modes;
895 u8 an_status;
896 u32 speed;
897 int err;
898
899 speed = link_ksettings->base.speed;
900
901 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
902 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
903 mlx5e_port_speed2linkmodes(speed);
904
905 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
906 if (err) {
907 netdev_err(priv->netdev, "%s: query port eth proto cap failed: %d\n",
908 __func__, err);
909 goto out;
910 }
911
912 link_modes = link_modes & eth_proto_cap;
913 if (!link_modes) {
914 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
915 __func__);
916 err = -EINVAL;
917 goto out;
918 }
919
920 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
921 if (err) {
922 netdev_err(priv->netdev, "%s: query port eth proto admin failed: %d\n",
923 __func__, err);
924 goto out;
925 }
926
927 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
928 &an_disable_cap, &an_disable_admin);
929
930 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
931 an_changes = ((!an_disable && an_disable_admin) ||
932 (an_disable && !an_disable_admin));
933
934 if (!an_changes && link_modes == eth_proto_admin)
935 goto out;
936
937 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
938 mlx5_toggle_port_link(mdev);
939
940 out:
941 return err;
942 }
943
944 static int mlx5e_set_link_ksettings(struct net_device *netdev,
945 const struct ethtool_link_ksettings *link_ksettings)
946 {
947 struct mlx5e_priv *priv = netdev_priv(netdev);
948
949 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
950 }
951
952 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
953 {
954 return sizeof(priv->rss_params.toeplitz_hash_key);
955 }
956
957 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
958 {
959 struct mlx5e_priv *priv = netdev_priv(netdev);
960
961 return mlx5e_ethtool_get_rxfh_key_size(priv);
962 }
963
964 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
965 {
966 return MLX5E_INDIR_RQT_SIZE;
967 }
968
969 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
970 {
971 struct mlx5e_priv *priv = netdev_priv(netdev);
972
973 return mlx5e_ethtool_get_rxfh_indir_size(priv);
974 }
975
976 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
977 u8 *hfunc)
978 {
979 struct mlx5e_priv *priv = netdev_priv(netdev);
980 struct mlx5e_rss_params *rss = &priv->rss_params;
981
982 if (indir)
983 memcpy(indir, rss->indirection_rqt,
984 sizeof(rss->indirection_rqt));
985
986 if (key)
987 memcpy(key, rss->toeplitz_hash_key,
988 sizeof(rss->toeplitz_hash_key));
989
990 if (hfunc)
991 *hfunc = rss->hfunc;
992
993 return 0;
994 }
995
996 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
997 const u8 *key, const u8 hfunc)
998 {
999 struct mlx5e_priv *priv = netdev_priv(dev);
1000 struct mlx5e_rss_params *rss = &priv->rss_params;
1001 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1002 bool hash_changed = false;
1003 void *in;
1004
1005 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1006 (hfunc != ETH_RSS_HASH_XOR) &&
1007 (hfunc != ETH_RSS_HASH_TOP))
1008 return -EINVAL;
1009
1010 in = kvzalloc(inlen, GFP_KERNEL);
1011 if (!in)
1012 return -ENOMEM;
1013
1014 mutex_lock(&priv->state_lock);
1015
1016 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1017 rss->hfunc = hfunc;
1018 hash_changed = true;
1019 }
1020
1021 if (indir) {
1022 memcpy(rss->indirection_rqt, indir,
1023 sizeof(rss->indirection_rqt));
1024
1025 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1026 u32 rqtn = priv->indir_rqt.rqtn;
1027 struct mlx5e_redirect_rqt_param rrp = {
1028 .is_rss = true,
1029 {
1030 .rss = {
1031 .hfunc = rss->hfunc,
1032 .channels = &priv->channels,
1033 },
1034 },
1035 };
1036
1037 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1038 }
1039 }
1040
1041 if (key) {
1042 memcpy(rss->toeplitz_hash_key, key,
1043 sizeof(rss->toeplitz_hash_key));
1044 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1045 }
1046
1047 if (hash_changed)
1048 mlx5e_modify_tirs_hash(priv, in, inlen);
1049
1050 mutex_unlock(&priv->state_lock);
1051
1052 kvfree(in);
1053
1054 return 0;
1055 }
1056
1057 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1058 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1059 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1060 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1061 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1062 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1063 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1064
1065 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1066 u16 *pfc_prevention_tout)
1067 {
1068 struct mlx5e_priv *priv = netdev_priv(netdev);
1069 struct mlx5_core_dev *mdev = priv->mdev;
1070
1071 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1072 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1073 return -EOPNOTSUPP;
1074
1075 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1076 }
1077
1078 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1079 u16 pfc_preven)
1080 {
1081 struct mlx5e_priv *priv = netdev_priv(netdev);
1082 struct mlx5_core_dev *mdev = priv->mdev;
1083 u16 critical_tout;
1084 u16 minor;
1085
1086 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1087 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1088 return -EOPNOTSUPP;
1089
1090 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1091 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1092 pfc_preven;
1093
1094 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1095 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1096 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1097 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1098 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1099 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1100 return -EINVAL;
1101 }
1102
1103 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1104 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1105 minor);
1106 }
1107
1108 static int mlx5e_get_tunable(struct net_device *dev,
1109 const struct ethtool_tunable *tuna,
1110 void *data)
1111 {
1112 int err;
1113
1114 switch (tuna->id) {
1115 case ETHTOOL_PFC_PREVENTION_TOUT:
1116 err = mlx5e_get_pfc_prevention_tout(dev, data);
1117 break;
1118 default:
1119 err = -EINVAL;
1120 break;
1121 }
1122
1123 return err;
1124 }
1125
1126 static int mlx5e_set_tunable(struct net_device *dev,
1127 const struct ethtool_tunable *tuna,
1128 const void *data)
1129 {
1130 struct mlx5e_priv *priv = netdev_priv(dev);
1131 int err;
1132
1133 mutex_lock(&priv->state_lock);
1134
1135 switch (tuna->id) {
1136 case ETHTOOL_PFC_PREVENTION_TOUT:
1137 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1138 break;
1139 default:
1140 err = -EINVAL;
1141 break;
1142 }
1143
1144 mutex_unlock(&priv->state_lock);
1145 return err;
1146 }
1147
1148 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1149 struct ethtool_pauseparam *pauseparam)
1150 {
1151 struct mlx5_core_dev *mdev = priv->mdev;
1152 int err;
1153
1154 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1155 &pauseparam->tx_pause);
1156 if (err) {
1157 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1158 __func__, err);
1159 }
1160 }
1161
1162 static void mlx5e_get_pauseparam(struct net_device *netdev,
1163 struct ethtool_pauseparam *pauseparam)
1164 {
1165 struct mlx5e_priv *priv = netdev_priv(netdev);
1166
1167 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1168 }
1169
1170 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1171 struct ethtool_pauseparam *pauseparam)
1172 {
1173 struct mlx5_core_dev *mdev = priv->mdev;
1174 int err;
1175
1176 if (pauseparam->autoneg)
1177 return -EINVAL;
1178
1179 err = mlx5_set_port_pause(mdev,
1180 pauseparam->rx_pause ? 1 : 0,
1181 pauseparam->tx_pause ? 1 : 0);
1182 if (err) {
1183 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1184 __func__, err);
1185 }
1186
1187 return err;
1188 }
1189
1190 static int mlx5e_set_pauseparam(struct net_device *netdev,
1191 struct ethtool_pauseparam *pauseparam)
1192 {
1193 struct mlx5e_priv *priv = netdev_priv(netdev);
1194
1195 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1196 }
1197
1198 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1199 struct ethtool_ts_info *info)
1200 {
1201 struct mlx5_core_dev *mdev = priv->mdev;
1202
1203 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1204
1205 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1206 info->phc_index == -1)
1207 return 0;
1208
1209 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1210 SOF_TIMESTAMPING_RX_HARDWARE |
1211 SOF_TIMESTAMPING_RAW_HARDWARE;
1212
1213 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1214 BIT(HWTSTAMP_TX_ON);
1215
1216 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1217 BIT(HWTSTAMP_FILTER_ALL);
1218
1219 return 0;
1220 }
1221
1222 static int mlx5e_get_ts_info(struct net_device *dev,
1223 struct ethtool_ts_info *info)
1224 {
1225 struct mlx5e_priv *priv = netdev_priv(dev);
1226
1227 return mlx5e_ethtool_get_ts_info(priv, info);
1228 }
1229
1230 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1231 {
1232 __u32 ret = 0;
1233
1234 if (MLX5_CAP_GEN(mdev, wol_g))
1235 ret |= WAKE_MAGIC;
1236
1237 if (MLX5_CAP_GEN(mdev, wol_s))
1238 ret |= WAKE_MAGICSECURE;
1239
1240 if (MLX5_CAP_GEN(mdev, wol_a))
1241 ret |= WAKE_ARP;
1242
1243 if (MLX5_CAP_GEN(mdev, wol_b))
1244 ret |= WAKE_BCAST;
1245
1246 if (MLX5_CAP_GEN(mdev, wol_m))
1247 ret |= WAKE_MCAST;
1248
1249 if (MLX5_CAP_GEN(mdev, wol_u))
1250 ret |= WAKE_UCAST;
1251
1252 if (MLX5_CAP_GEN(mdev, wol_p))
1253 ret |= WAKE_PHY;
1254
1255 return ret;
1256 }
1257
1258 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1259 {
1260 __u32 ret = 0;
1261
1262 if (mode & MLX5_WOL_MAGIC)
1263 ret |= WAKE_MAGIC;
1264
1265 if (mode & MLX5_WOL_SECURED_MAGIC)
1266 ret |= WAKE_MAGICSECURE;
1267
1268 if (mode & MLX5_WOL_ARP)
1269 ret |= WAKE_ARP;
1270
1271 if (mode & MLX5_WOL_BROADCAST)
1272 ret |= WAKE_BCAST;
1273
1274 if (mode & MLX5_WOL_MULTICAST)
1275 ret |= WAKE_MCAST;
1276
1277 if (mode & MLX5_WOL_UNICAST)
1278 ret |= WAKE_UCAST;
1279
1280 if (mode & MLX5_WOL_PHY_ACTIVITY)
1281 ret |= WAKE_PHY;
1282
1283 return ret;
1284 }
1285
1286 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1287 {
1288 u8 ret = 0;
1289
1290 if (mode & WAKE_MAGIC)
1291 ret |= MLX5_WOL_MAGIC;
1292
1293 if (mode & WAKE_MAGICSECURE)
1294 ret |= MLX5_WOL_SECURED_MAGIC;
1295
1296 if (mode & WAKE_ARP)
1297 ret |= MLX5_WOL_ARP;
1298
1299 if (mode & WAKE_BCAST)
1300 ret |= MLX5_WOL_BROADCAST;
1301
1302 if (mode & WAKE_MCAST)
1303 ret |= MLX5_WOL_MULTICAST;
1304
1305 if (mode & WAKE_UCAST)
1306 ret |= MLX5_WOL_UNICAST;
1307
1308 if (mode & WAKE_PHY)
1309 ret |= MLX5_WOL_PHY_ACTIVITY;
1310
1311 return ret;
1312 }
1313
1314 static void mlx5e_get_wol(struct net_device *netdev,
1315 struct ethtool_wolinfo *wol)
1316 {
1317 struct mlx5e_priv *priv = netdev_priv(netdev);
1318 struct mlx5_core_dev *mdev = priv->mdev;
1319 u8 mlx5_wol_mode;
1320 int err;
1321
1322 memset(wol, 0, sizeof(*wol));
1323
1324 wol->supported = mlx5e_get_wol_supported(mdev);
1325 if (!wol->supported)
1326 return;
1327
1328 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1329 if (err)
1330 return;
1331
1332 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1333 }
1334
1335 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1336 {
1337 struct mlx5e_priv *priv = netdev_priv(netdev);
1338 struct mlx5_core_dev *mdev = priv->mdev;
1339 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1340 u32 mlx5_wol_mode;
1341
1342 if (!wol_supported)
1343 return -EOPNOTSUPP;
1344
1345 if (wol->wolopts & ~wol_supported)
1346 return -EINVAL;
1347
1348 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1349
1350 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1351 }
1352
1353 static int mlx5e_get_fecparam(struct net_device *netdev,
1354 struct ethtool_fecparam *fecparam)
1355 {
1356 struct mlx5e_priv *priv = netdev_priv(netdev);
1357 struct mlx5_core_dev *mdev = priv->mdev;
1358 u8 fec_configured = 0;
1359 u32 fec_active = 0;
1360 int err;
1361
1362 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1363
1364 if (err)
1365 return err;
1366
1367 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1368 sizeof(u32) * BITS_PER_BYTE);
1369
1370 if (!fecparam->active_fec)
1371 return -EOPNOTSUPP;
1372
1373 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1374 sizeof(u8) * BITS_PER_BYTE);
1375
1376 return 0;
1377 }
1378
1379 static int mlx5e_set_fecparam(struct net_device *netdev,
1380 struct ethtool_fecparam *fecparam)
1381 {
1382 struct mlx5e_priv *priv = netdev_priv(netdev);
1383 struct mlx5_core_dev *mdev = priv->mdev;
1384 u8 fec_policy = 0;
1385 int mode;
1386 int err;
1387
1388 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1389 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1390 continue;
1391 fec_policy |= (1 << mode);
1392 break;
1393 }
1394
1395 err = mlx5e_set_fec_mode(mdev, fec_policy);
1396
1397 if (err)
1398 return err;
1399
1400 mlx5_toggle_port_link(mdev);
1401
1402 return 0;
1403 }
1404
1405 static u32 mlx5e_get_msglevel(struct net_device *dev)
1406 {
1407 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1408 }
1409
1410 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1411 {
1412 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1413 }
1414
1415 static int mlx5e_set_phys_id(struct net_device *dev,
1416 enum ethtool_phys_id_state state)
1417 {
1418 struct mlx5e_priv *priv = netdev_priv(dev);
1419 struct mlx5_core_dev *mdev = priv->mdev;
1420 u16 beacon_duration;
1421
1422 if (!MLX5_CAP_GEN(mdev, beacon_led))
1423 return -EOPNOTSUPP;
1424
1425 switch (state) {
1426 case ETHTOOL_ID_ACTIVE:
1427 beacon_duration = MLX5_BEACON_DURATION_INF;
1428 break;
1429 case ETHTOOL_ID_INACTIVE:
1430 beacon_duration = MLX5_BEACON_DURATION_OFF;
1431 break;
1432 default:
1433 return -EOPNOTSUPP;
1434 }
1435
1436 return mlx5_set_port_beacon(mdev, beacon_duration);
1437 }
1438
1439 static int mlx5e_get_module_info(struct net_device *netdev,
1440 struct ethtool_modinfo *modinfo)
1441 {
1442 struct mlx5e_priv *priv = netdev_priv(netdev);
1443 struct mlx5_core_dev *dev = priv->mdev;
1444 int size_read = 0;
1445 u8 data[4];
1446
1447 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1448 if (size_read < 2)
1449 return -EIO;
1450
1451 /* data[0] = identifier byte */
1452 switch (data[0]) {
1453 case MLX5_MODULE_ID_QSFP:
1454 modinfo->type = ETH_MODULE_SFF_8436;
1455 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1456 break;
1457 case MLX5_MODULE_ID_QSFP_PLUS:
1458 case MLX5_MODULE_ID_QSFP28:
1459 /* data[1] = revision id */
1460 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1461 modinfo->type = ETH_MODULE_SFF_8636;
1462 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1463 } else {
1464 modinfo->type = ETH_MODULE_SFF_8436;
1465 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1466 }
1467 break;
1468 case MLX5_MODULE_ID_SFP:
1469 modinfo->type = ETH_MODULE_SFF_8472;
1470 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1471 break;
1472 default:
1473 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1474 __func__, data[0]);
1475 return -EINVAL;
1476 }
1477
1478 return 0;
1479 }
1480
1481 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1482 struct ethtool_eeprom *ee,
1483 u8 *data)
1484 {
1485 struct mlx5e_priv *priv = netdev_priv(netdev);
1486 struct mlx5_core_dev *mdev = priv->mdev;
1487 int offset = ee->offset;
1488 int size_read;
1489 int i = 0;
1490
1491 if (!ee->len)
1492 return -EINVAL;
1493
1494 memset(data, 0, ee->len);
1495
1496 while (i < ee->len) {
1497 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1498 data + i);
1499
1500 if (!size_read)
1501 /* Done reading */
1502 return 0;
1503
1504 if (size_read < 0) {
1505 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1506 __func__, size_read);
1507 return 0;
1508 }
1509
1510 i += size_read;
1511 offset += size_read;
1512 }
1513
1514 return 0;
1515 }
1516
1517 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1518 bool is_rx_cq)
1519 {
1520 struct mlx5e_priv *priv = netdev_priv(netdev);
1521 struct mlx5_core_dev *mdev = priv->mdev;
1522 struct mlx5e_channels new_channels = {};
1523 bool mode_changed;
1524 u8 cq_period_mode, current_cq_period_mode;
1525 int err = 0;
1526
1527 cq_period_mode = enable ?
1528 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1529 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1530 current_cq_period_mode = is_rx_cq ?
1531 priv->channels.params.rx_cq_moderation.cq_period_mode :
1532 priv->channels.params.tx_cq_moderation.cq_period_mode;
1533 mode_changed = cq_period_mode != current_cq_period_mode;
1534
1535 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1536 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1537 return -EOPNOTSUPP;
1538
1539 if (!mode_changed)
1540 return 0;
1541
1542 new_channels.params = priv->channels.params;
1543 if (is_rx_cq)
1544 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1545 else
1546 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1547
1548 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1549 priv->channels.params = new_channels.params;
1550 return 0;
1551 }
1552
1553 err = mlx5e_open_channels(priv, &new_channels);
1554 if (err)
1555 return err;
1556
1557 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1558 return 0;
1559 }
1560
1561 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1562 {
1563 return set_pflag_cqe_based_moder(netdev, enable, false);
1564 }
1565
1566 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1567 {
1568 return set_pflag_cqe_based_moder(netdev, enable, true);
1569 }
1570
1571 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1572 {
1573 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1574 struct mlx5e_channels new_channels = {};
1575 int err = 0;
1576
1577 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1578 return new_val ? -EOPNOTSUPP : 0;
1579
1580 if (curr_val == new_val)
1581 return 0;
1582
1583 new_channels.params = priv->channels.params;
1584 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1585
1586 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1587 priv->channels.params = new_channels.params;
1588 return 0;
1589 }
1590
1591 err = mlx5e_open_channels(priv, &new_channels);
1592 if (err)
1593 return err;
1594
1595 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1596 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1597 MLX5E_GET_PFLAG(&priv->channels.params,
1598 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1599
1600 return 0;
1601 }
1602
1603 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1604 bool enable)
1605 {
1606 struct mlx5e_priv *priv = netdev_priv(netdev);
1607 struct mlx5_core_dev *mdev = priv->mdev;
1608
1609 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1610 return -EOPNOTSUPP;
1611
1612 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1613 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1614 return -EINVAL;
1615 }
1616
1617 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1618 priv->channels.params.rx_cqe_compress_def = enable;
1619
1620 return 0;
1621 }
1622
1623 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1624 {
1625 struct mlx5e_priv *priv = netdev_priv(netdev);
1626 struct mlx5_core_dev *mdev = priv->mdev;
1627 struct mlx5e_channels new_channels = {};
1628 int err;
1629
1630 if (enable) {
1631 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1632 return -EOPNOTSUPP;
1633 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1634 return -EINVAL;
1635 } else if (priv->channels.params.lro_en) {
1636 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1637 return -EINVAL;
1638 }
1639
1640 new_channels.params = priv->channels.params;
1641
1642 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1643 mlx5e_set_rq_type(mdev, &new_channels.params);
1644
1645 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1646 priv->channels.params = new_channels.params;
1647 return 0;
1648 }
1649
1650 err = mlx5e_open_channels(priv, &new_channels);
1651 if (err)
1652 return err;
1653
1654 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1655 return 0;
1656 }
1657
1658 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1659 {
1660 struct mlx5e_priv *priv = netdev_priv(netdev);
1661 struct mlx5e_channels *channels = &priv->channels;
1662 struct mlx5e_channel *c;
1663 int i;
1664
1665 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1666 return 0;
1667
1668 for (i = 0; i < channels->num; i++) {
1669 c = channels->c[i];
1670 if (enable)
1671 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1672 else
1673 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1674 }
1675
1676 return 0;
1677 }
1678
1679 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1680 {
1681 struct mlx5e_priv *priv = netdev_priv(netdev);
1682 struct mlx5_core_dev *mdev = priv->mdev;
1683 struct mlx5e_channels new_channels = {};
1684 int err;
1685
1686 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1687 return -EOPNOTSUPP;
1688
1689 new_channels.params = priv->channels.params;
1690
1691 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1692
1693 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1694 priv->channels.params = new_channels.params;
1695 return 0;
1696 }
1697
1698 err = mlx5e_open_channels(priv, &new_channels);
1699 if (err)
1700 return err;
1701
1702 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1703 return 0;
1704 }
1705
1706 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1707 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1708 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1709 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1710 { "rx_striding_rq", set_pflag_rx_striding_rq },
1711 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1712 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1713 };
1714
1715 static int mlx5e_handle_pflag(struct net_device *netdev,
1716 u32 wanted_flags,
1717 enum mlx5e_priv_flag flag)
1718 {
1719 struct mlx5e_priv *priv = netdev_priv(netdev);
1720 bool enable = !!(wanted_flags & BIT(flag));
1721 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1722 int err;
1723
1724 if (!(changes & BIT(flag)))
1725 return 0;
1726
1727 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1728 if (err) {
1729 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1730 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1731 return err;
1732 }
1733
1734 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1735 return 0;
1736 }
1737
1738 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1739 {
1740 struct mlx5e_priv *priv = netdev_priv(netdev);
1741 enum mlx5e_priv_flag pflag;
1742 int err;
1743
1744 mutex_lock(&priv->state_lock);
1745
1746 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1747 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1748 if (err)
1749 break;
1750 }
1751
1752 mutex_unlock(&priv->state_lock);
1753
1754 /* Need to fix some features.. */
1755 netdev_update_features(netdev);
1756
1757 return err;
1758 }
1759
1760 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1761 {
1762 struct mlx5e_priv *priv = netdev_priv(netdev);
1763
1764 return priv->channels.params.pflags;
1765 }
1766
1767 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1768 struct ethtool_flash *flash)
1769 {
1770 struct mlx5_core_dev *mdev = priv->mdev;
1771 struct net_device *dev = priv->netdev;
1772 const struct firmware *fw;
1773 int err;
1774
1775 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1776 return -EOPNOTSUPP;
1777
1778 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1779 if (err)
1780 return err;
1781
1782 dev_hold(dev);
1783 rtnl_unlock();
1784
1785 err = mlx5_firmware_flash(mdev, fw);
1786 release_firmware(fw);
1787
1788 rtnl_lock();
1789 dev_put(dev);
1790 return err;
1791 }
1792
1793 static int mlx5e_flash_device(struct net_device *dev,
1794 struct ethtool_flash *flash)
1795 {
1796 struct mlx5e_priv *priv = netdev_priv(dev);
1797
1798 return mlx5e_ethtool_flash_device(priv, flash);
1799 }
1800
1801 const struct ethtool_ops mlx5e_ethtool_ops = {
1802 .get_drvinfo = mlx5e_get_drvinfo,
1803 .get_link = ethtool_op_get_link,
1804 .get_strings = mlx5e_get_strings,
1805 .get_sset_count = mlx5e_get_sset_count,
1806 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1807 .get_ringparam = mlx5e_get_ringparam,
1808 .set_ringparam = mlx5e_set_ringparam,
1809 .get_channels = mlx5e_get_channels,
1810 .set_channels = mlx5e_set_channels,
1811 .get_coalesce = mlx5e_get_coalesce,
1812 .set_coalesce = mlx5e_set_coalesce,
1813 .get_link_ksettings = mlx5e_get_link_ksettings,
1814 .set_link_ksettings = mlx5e_set_link_ksettings,
1815 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1816 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1817 .get_rxfh = mlx5e_get_rxfh,
1818 .set_rxfh = mlx5e_set_rxfh,
1819 #ifdef CONFIG_MLX5_EN_RXNFC
1820 .get_rxnfc = mlx5e_get_rxnfc,
1821 .set_rxnfc = mlx5e_set_rxnfc,
1822 #endif
1823 .flash_device = mlx5e_flash_device,
1824 .get_tunable = mlx5e_get_tunable,
1825 .set_tunable = mlx5e_set_tunable,
1826 .get_pauseparam = mlx5e_get_pauseparam,
1827 .set_pauseparam = mlx5e_set_pauseparam,
1828 .get_ts_info = mlx5e_get_ts_info,
1829 .set_phys_id = mlx5e_set_phys_id,
1830 .get_wol = mlx5e_get_wol,
1831 .set_wol = mlx5e_set_wol,
1832 .get_module_info = mlx5e_get_module_info,
1833 .get_module_eeprom = mlx5e_get_module_eeprom,
1834 .get_priv_flags = mlx5e_get_priv_flags,
1835 .set_priv_flags = mlx5e_set_priv_flags,
1836 .self_test = mlx5e_self_test,
1837 .get_msglevel = mlx5e_get_msglevel,
1838 .set_msglevel = mlx5e_set_msglevel,
1839 .get_fecparam = mlx5e_get_fecparam,
1840 .set_fecparam = mlx5e_set_fecparam,
1841 };
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